ehci.c revision 1.234.2.49
1 /* $NetBSD: ehci.c,v 1.234.2.49 2015/06/06 14:40:13 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.49 2015/06/06 14:40:13 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctrl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Iso pipe */ 146 struct { 147 u_int next_frame; 148 u_int cur_xfers; 149 } isoc; 150 }; 151 }; 152 153 Static usbd_status ehci_open(struct usbd_pipe *); 154 Static void ehci_poll(struct usbd_bus *); 155 Static void ehci_softintr(void *); 156 Static int ehci_intr1(ehci_softc_t *); 157 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 158 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 159 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 160 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 161 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 162 Static void ehci_idone(struct ehci_xfer *); 163 Static void ehci_timeout(void *); 164 Static void ehci_timeout_task(void *); 165 Static void ehci_intrlist_timeout(void *); 166 Static void ehci_doorbell(void *); 167 Static void ehci_pcd(void *); 168 169 Static struct usbd_xfer * 170 ehci_allocx(struct usbd_bus *); 171 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 173 Static int ehci_roothub_ctrl(struct usbd_bus *, 174 usb_device_request_t *, void *, int); 175 176 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 177 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 178 Static void ehci_root_intr_abort(struct usbd_xfer *); 179 Static void ehci_root_intr_close(struct usbd_pipe *); 180 Static void ehci_root_intr_done(struct usbd_xfer *); 181 182 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 183 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 184 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 185 Static void ehci_device_ctrl_close(struct usbd_pipe *); 186 Static void ehci_device_ctrl_done(struct usbd_xfer *); 187 188 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 189 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 190 Static void ehci_device_bulk_abort(struct usbd_xfer *); 191 Static void ehci_device_bulk_close(struct usbd_pipe *); 192 Static void ehci_device_bulk_done(struct usbd_xfer *); 193 194 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 195 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 196 Static void ehci_device_intr_abort(struct usbd_xfer *); 197 Static void ehci_device_intr_close(struct usbd_pipe *); 198 Static void ehci_device_intr_done(struct usbd_xfer *); 199 200 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 201 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 202 Static void ehci_device_isoc_abort(struct usbd_xfer *); 203 Static void ehci_device_isoc_close(struct usbd_pipe *); 204 Static void ehci_device_isoc_done(struct usbd_xfer *); 205 206 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 207 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 208 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 209 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 210 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 211 212 Static void ehci_device_clear_toggle(struct usbd_pipe *); 213 Static void ehci_noop(struct usbd_pipe *); 214 215 Static void ehci_disown(ehci_softc_t *, int, int); 216 217 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 218 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 219 220 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 221 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 222 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 223 ehci_softc_t *, int, int, struct usbd_xfer *, 224 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 225 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 226 ehci_soft_qtd_t *); 227 228 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 229 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 230 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 231 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 232 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 233 struct ehci_xfer *); 234 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 235 struct ehci_xfer *); 236 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, 237 usbd_status); 238 239 Static usbd_status ehci_device_request(struct usbd_xfer *); 240 241 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 242 int); 243 244 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 245 ehci_soft_qh_t *); 246 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 247 ehci_soft_qh_t *); 248 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 249 Static void ehci_sync_hc(ehci_softc_t *); 250 251 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 252 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 253 254 #ifdef EHCI_DEBUG 255 Static ehci_softc_t *theehci; 256 void ehci_dump(void); 257 #endif 258 259 #ifdef EHCI_DEBUG 260 Static void ehci_dump_regs(ehci_softc_t *); 261 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 262 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 263 Static void ehci_dump_qtd(ehci_qtd_t *); 264 Static void ehci_dump_sqh(ehci_soft_qh_t *); 265 Static void ehci_dump_sitd(struct ehci_soft_itd *); 266 Static void ehci_dump_itd(struct ehci_soft_itd *); 267 Static void ehci_dump_exfer(struct ehci_xfer *); 268 #endif 269 270 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 271 272 #define ehci_add_intr_list(sc, ex) \ 273 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 274 #define ehci_del_intr_list(sc, ex) \ 275 do { \ 276 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 277 (ex)->ex_next.tqe_prev = NULL; \ 278 } while (0) 279 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 280 281 Static const struct usbd_bus_methods ehci_bus_methods = { 282 .ubm_open = ehci_open, 283 .ubm_softint = ehci_softintr, 284 .ubm_dopoll = ehci_poll, 285 .ubm_allocx = ehci_allocx, 286 .ubm_freex = ehci_freex, 287 .ubm_getlock = ehci_get_lock, 288 .ubm_rhctrl = ehci_roothub_ctrl, 289 }; 290 291 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 292 .upm_transfer = ehci_root_intr_transfer, 293 .upm_start = ehci_root_intr_start, 294 .upm_abort = ehci_root_intr_abort, 295 .upm_close = ehci_root_intr_close, 296 .upm_cleartoggle = ehci_noop, 297 .upm_done = ehci_root_intr_done, 298 }; 299 300 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 301 .upm_transfer = ehci_device_ctrl_transfer, 302 .upm_start = ehci_device_ctrl_start, 303 .upm_abort = ehci_device_ctrl_abort, 304 .upm_close = ehci_device_ctrl_close, 305 .upm_cleartoggle = ehci_noop, 306 .upm_done = ehci_device_ctrl_done, 307 }; 308 309 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 310 .upm_transfer = ehci_device_intr_transfer, 311 .upm_start = ehci_device_intr_start, 312 .upm_abort = ehci_device_intr_abort, 313 .upm_close = ehci_device_intr_close, 314 .upm_cleartoggle = ehci_device_clear_toggle, 315 .upm_done = ehci_device_intr_done, 316 }; 317 318 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 319 .upm_transfer = ehci_device_bulk_transfer, 320 .upm_start = ehci_device_bulk_start, 321 .upm_abort = ehci_device_bulk_abort, 322 .upm_close = ehci_device_bulk_close, 323 .upm_cleartoggle = ehci_device_clear_toggle, 324 .upm_done = ehci_device_bulk_done, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 328 .upm_transfer = ehci_device_isoc_transfer, 329 .upm_start = ehci_device_isoc_start, 330 .upm_abort = ehci_device_isoc_abort, 331 .upm_close = ehci_device_isoc_close, 332 .upm_cleartoggle = ehci_noop, 333 .upm_done = ehci_device_isoc_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 337 .upm_transfer = ehci_device_fs_isoc_transfer, 338 .upm_start = ehci_device_fs_isoc_start, 339 .upm_abort = ehci_device_fs_isoc_abort, 340 .upm_close = ehci_device_fs_isoc_close, 341 .upm_cleartoggle = ehci_noop, 342 .upm_done = ehci_device_fs_isoc_done, 343 }; 344 345 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 346 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 347 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 348 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 349 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 350 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 351 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 352 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 353 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 354 }; 355 356 int 357 ehci_init(ehci_softc_t *sc) 358 { 359 uint32_t vers, sparams, cparams, hcr; 360 u_int i; 361 usbd_status err; 362 ehci_soft_qh_t *sqh; 363 u_int ncomp; 364 365 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 366 #ifdef EHCI_DEBUG 367 theehci = sc; 368 #endif 369 370 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 371 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 372 cv_init(&sc->sc_softwake_cv, "ehciab"); 373 cv_init(&sc->sc_doorbell, "ehcidi"); 374 375 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 376 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 377 378 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 379 ehci_doorbell, sc); 380 KASSERT(sc->sc_doorbell_si != NULL); 381 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_pcd, sc); 383 KASSERT(sc->sc_pcd_si != NULL); 384 385 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 386 387 vers = EREAD2(sc, EHCI_HCIVERSION); 388 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 389 vers >> 8, vers & 0xff); 390 391 sparams = EREAD4(sc, EHCI_HCSPARAMS); 392 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 393 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 394 ncomp = EHCI_HCS_N_CC(sparams); 395 if (ncomp != sc->sc_ncomp) { 396 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 397 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 398 #if NOHCI == 0 || NUHCI == 0 399 aprint_error("%s: ohci or uhci probably not configured\n", 400 device_xname(sc->sc_dev)); 401 #endif 402 if (ncomp < sc->sc_ncomp) 403 sc->sc_ncomp = ncomp; 404 } 405 if (sc->sc_ncomp > 0) { 406 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 407 aprint_normal("%s: companion controller%s, %d port%s each:", 408 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 409 EHCI_HCS_N_PCC(sparams), 410 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 411 for (i = 0; i < sc->sc_ncomp; i++) 412 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 413 aprint_normal("\n"); 414 } 415 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 416 cparams = EREAD4(sc, EHCI_HCCPARAMS); 417 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 418 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 419 420 if (EHCI_HCC_64BIT(cparams)) { 421 /* MUST clear segment register if 64 bit capable. */ 422 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 423 } 424 425 sc->sc_bus.ub_revision = USBREV_2_0; 426 sc->sc_bus.ub_usedma = true; 427 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 428 429 /* Reset the controller */ 430 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 431 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 432 usb_delay_ms(&sc->sc_bus, 1); 433 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 434 for (i = 0; i < 100; i++) { 435 usb_delay_ms(&sc->sc_bus, 1); 436 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 437 if (!hcr) 438 break; 439 } 440 if (hcr) { 441 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 442 return EIO; 443 } 444 if (sc->sc_vendor_init) 445 sc->sc_vendor_init(sc); 446 447 /* 448 * If we are doing embedded transaction translation function, force 449 * the controller to host mode. 450 */ 451 if (sc->sc_flags & EHCIF_ETTF) { 452 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 453 usbmode &= ~EHCI_USBMODE_CM; 454 usbmode |= EHCI_USBMODE_CM_HOST; 455 EWRITE4(sc, EHCI_USBMODE, usbmode); 456 } 457 458 /* XXX need proper intr scheduling */ 459 sc->sc_rand = 96; 460 461 /* frame list size at default, read back what we got and use that */ 462 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 463 case 0: sc->sc_flsize = 1024; break; 464 case 1: sc->sc_flsize = 512; break; 465 case 2: sc->sc_flsize = 256; break; 466 case 3: return EIO; 467 } 468 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 469 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 470 if (err) 471 return err; 472 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 473 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 474 475 for (i = 0; i < sc->sc_flsize; i++) { 476 sc->sc_flist[i] = EHCI_NULL; 477 } 478 479 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 480 481 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 482 KM_SLEEP); 483 if (sc->sc_softitds == NULL) 484 return ENOMEM; 485 LIST_INIT(&sc->sc_freeitds); 486 LIST_INIT(&sc->sc_freesitds); 487 TAILQ_INIT(&sc->sc_intrhead); 488 489 /* Set up the bus struct. */ 490 sc->sc_bus.ub_methods = &ehci_bus_methods; 491 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 492 493 sc->sc_eintrs = EHCI_NORMAL_INTRS; 494 495 /* 496 * Allocate the interrupt dummy QHs. These are arranged to give poll 497 * intervals that are powers of 2 times 1ms. 498 */ 499 for (i = 0; i < EHCI_INTRQHS; i++) { 500 sqh = ehci_alloc_sqh(sc); 501 if (sqh == NULL) { 502 err = ENOMEM; 503 goto bad1; 504 } 505 sc->sc_islots[i].sqh = sqh; 506 } 507 for (i = 0; i < EHCI_INTRQHS; i++) { 508 sqh = sc->sc_islots[i].sqh; 509 if (i == 0) { 510 /* The last (1ms) QH terminates. */ 511 sqh->qh.qh_link = EHCI_NULL; 512 sqh->next = NULL; 513 } else { 514 /* Otherwise the next QH has half the poll interval */ 515 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 516 sqh->qh.qh_link = htole32(sqh->next->physaddr | 517 EHCI_LINK_QH); 518 } 519 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 520 sqh->qh.qh_curqtd = EHCI_NULL; 521 sqh->next = NULL; 522 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 523 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 524 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 525 sqh->sqtd = NULL; 526 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 528 } 529 /* Point the frame list at the last level (128ms). */ 530 for (i = 0; i < sc->sc_flsize; i++) { 531 int j; 532 533 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 534 revbits[i & (EHCI_MAX_POLLRATE-1)]; 535 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 536 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 537 i)].sqh->physaddr); 538 } 539 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 540 BUS_DMASYNC_PREWRITE); 541 542 /* Allocate dummy QH that starts the async list. */ 543 sqh = ehci_alloc_sqh(sc); 544 if (sqh == NULL) { 545 err = ENOMEM; 546 goto bad1; 547 } 548 /* Fill the QH */ 549 sqh->qh.qh_endp = 550 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 551 sqh->qh.qh_link = 552 htole32(sqh->physaddr | EHCI_LINK_QH); 553 sqh->qh.qh_curqtd = EHCI_NULL; 554 sqh->next = NULL; 555 /* Fill the overlay qTD */ 556 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 557 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 558 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 559 sqh->sqtd = NULL; 560 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 562 #ifdef EHCI_DEBUG 563 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 564 ehci_dump_sqh(sqh); 565 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 566 #endif 567 568 /* Point to async list */ 569 sc->sc_async_head = sqh; 570 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 571 572 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 573 574 /* Turn on controller */ 575 EOWRITE4(sc, EHCI_USBCMD, 576 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 577 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 578 EHCI_CMD_ASE | 579 EHCI_CMD_PSE | 580 EHCI_CMD_RS); 581 582 /* Take over port ownership */ 583 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 584 585 for (i = 0; i < 100; i++) { 586 usb_delay_ms(&sc->sc_bus, 1); 587 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 588 if (!hcr) 589 break; 590 } 591 if (hcr) { 592 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 593 return EIO; 594 } 595 596 /* Enable interrupts */ 597 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 598 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 599 600 return 0; 601 602 #if 0 603 bad2: 604 ehci_free_sqh(sc, sc->sc_async_head); 605 #endif 606 bad1: 607 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 608 return err; 609 } 610 611 int 612 ehci_intr(void *v) 613 { 614 ehci_softc_t *sc = v; 615 int ret = 0; 616 617 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 618 619 if (sc == NULL) 620 return 0; 621 622 mutex_spin_enter(&sc->sc_intr_lock); 623 624 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 625 goto done; 626 627 /* If we get an interrupt while polling, then just ignore it. */ 628 if (sc->sc_bus.ub_usepolling) { 629 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 630 631 if (intrs) 632 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 633 USBHIST_LOGN(ehcidebug, 16, 634 "ignored interrupt while polling", 0, 0, 0, 0); 635 goto done; 636 } 637 638 ret = ehci_intr1(sc); 639 640 done: 641 mutex_spin_exit(&sc->sc_intr_lock); 642 return ret; 643 } 644 645 Static int 646 ehci_intr1(ehci_softc_t *sc) 647 { 648 uint32_t intrs, eintrs; 649 650 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 651 652 /* In case the interrupt occurs before initialization has completed. */ 653 if (sc == NULL) { 654 #ifdef DIAGNOSTIC 655 printf("ehci_intr1: sc == NULL\n"); 656 #endif 657 return 0; 658 } 659 660 KASSERT(mutex_owned(&sc->sc_intr_lock)); 661 662 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 663 if (!intrs) 664 return 0; 665 666 eintrs = intrs & sc->sc_eintrs; 667 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 668 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 669 if (!eintrs) 670 return 0; 671 672 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 673 if (eintrs & EHCI_STS_IAA) { 674 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 675 kpreempt_disable(); 676 KASSERT(sc->sc_doorbell_si != NULL); 677 softint_schedule(sc->sc_doorbell_si); 678 kpreempt_enable(); 679 eintrs &= ~EHCI_STS_IAA; 680 } 681 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 682 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 683 eintrs & EHCI_STS_INT ? 1 : 0, 684 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 685 usb_schedsoftintr(&sc->sc_bus); 686 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 687 } 688 if (eintrs & EHCI_STS_HSE) { 689 printf("%s: unrecoverable error, controller halted\n", 690 device_xname(sc->sc_dev)); 691 /* XXX what else */ 692 } 693 if (eintrs & EHCI_STS_PCD) { 694 kpreempt_disable(); 695 KASSERT(sc->sc_pcd_si != NULL); 696 softint_schedule(sc->sc_pcd_si); 697 kpreempt_enable(); 698 eintrs &= ~EHCI_STS_PCD; 699 } 700 701 if (eintrs != 0) { 702 /* Block unprocessed interrupts. */ 703 sc->sc_eintrs &= ~eintrs; 704 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 705 printf("%s: blocking intrs 0x%x\n", 706 device_xname(sc->sc_dev), eintrs); 707 } 708 709 return 1; 710 } 711 712 Static void 713 ehci_doorbell(void *addr) 714 { 715 ehci_softc_t *sc = addr; 716 717 mutex_enter(&sc->sc_lock); 718 cv_broadcast(&sc->sc_doorbell); 719 mutex_exit(&sc->sc_lock); 720 } 721 722 Static void 723 ehci_pcd(void *addr) 724 { 725 ehci_softc_t *sc = addr; 726 struct usbd_xfer *xfer; 727 u_char *p; 728 int i, m; 729 730 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 731 732 mutex_enter(&sc->sc_lock); 733 xfer = sc->sc_intrxfer; 734 735 if (xfer == NULL) { 736 /* Just ignore the change. */ 737 goto done; 738 } 739 740 p = xfer->ux_buf; 741 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 742 memset(p, 0, xfer->ux_length); 743 for (i = 1; i <= m; i++) { 744 /* Pick out CHANGE bits from the status reg. */ 745 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 746 p[i/8] |= 1 << (i%8); 747 if (i % 8 == 7) 748 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 749 p[i/8], 0, 0); 750 } 751 xfer->ux_actlen = xfer->ux_length; 752 xfer->ux_status = USBD_NORMAL_COMPLETION; 753 754 usb_transfer_complete(xfer); 755 756 done: 757 mutex_exit(&sc->sc_lock); 758 } 759 760 Static void 761 ehci_softintr(void *v) 762 { 763 struct usbd_bus *bus = v; 764 ehci_softc_t *sc = bus->ub_hcpriv; 765 struct ehci_xfer *ex, *nextex; 766 767 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 768 769 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 770 771 /* 772 * The only explanation I can think of for why EHCI is as brain dead 773 * as UHCI interrupt-wise is that Intel was involved in both. 774 * An interrupt just tells us that something is done, we have no 775 * clue what, so we need to scan through all active transfers. :-( 776 */ 777 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 778 nextex = TAILQ_NEXT(ex, ex_next); 779 ehci_check_intr(sc, ex); 780 } 781 782 /* Schedule a callout to catch any dropped transactions. */ 783 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 784 !TAILQ_EMPTY(&sc->sc_intrhead)) 785 callout_reset(&sc->sc_tmo_intrlist, 786 hz, ehci_intrlist_timeout, sc); 787 788 if (sc->sc_softwake) { 789 sc->sc_softwake = 0; 790 cv_broadcast(&sc->sc_softwake_cv); 791 } 792 } 793 794 /* Check for an interrupt. */ 795 Static void 796 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 797 { 798 struct usbd_device *dev = ex->ex_xfer.ux_pipe->up_dev; 799 int attr; 800 801 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 802 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 803 804 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 805 806 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 807 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 808 if (dev->ud_speed == USB_SPEED_HIGH) 809 ehci_check_itd_intr(sc, ex); 810 else 811 ehci_check_sitd_intr(sc, ex); 812 } else 813 ehci_check_qh_intr(sc, ex); 814 815 return; 816 } 817 818 Static void 819 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 820 { 821 ehci_soft_qtd_t *sqtd, *lsqtd; 822 uint32_t status; 823 824 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 825 826 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 827 828 if (ex->ex_sqtdstart == NULL) { 829 printf("ehci_check_qh_intr: not valid sqtd\n"); 830 return; 831 } 832 833 lsqtd = ex->ex_sqtdend; 834 #ifdef DIAGNOSTIC 835 if (lsqtd == NULL) { 836 printf("ehci_check_qh_intr: lsqtd==0\n"); 837 return; 838 } 839 #endif 840 /* 841 * If the last TD is still active we need to check whether there 842 * is an error somewhere in the middle, or whether there was a 843 * short packet (SPD and not ACTIVE). 844 */ 845 usb_syncmem(&lsqtd->dma, 846 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 847 sizeof(lsqtd->qtd.qtd_status), 848 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 849 status = le32toh(lsqtd->qtd.qtd_status); 850 usb_syncmem(&lsqtd->dma, 851 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 852 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 853 if (status & EHCI_QTD_ACTIVE) { 854 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 855 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 856 sqtd = sqtd->nextqtd) { 857 usb_syncmem(&sqtd->dma, 858 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 859 sizeof(sqtd->qtd.qtd_status), 860 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 861 status = le32toh(sqtd->qtd.qtd_status); 862 usb_syncmem(&sqtd->dma, 863 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 864 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 865 /* If there's an active QTD the xfer isn't done. */ 866 if (status & EHCI_QTD_ACTIVE) 867 break; 868 /* Any kind of error makes the xfer done. */ 869 if (status & EHCI_QTD_HALTED) 870 goto done; 871 /* Handle short packets */ 872 if (EHCI_QTD_GET_BYTES(status) != 0) { 873 struct usbd_pipe *pipe = ex->ex_xfer.ux_pipe; 874 usb_endpoint_descriptor_t *ed = 875 pipe->up_endpoint->ue_edesc; 876 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 877 878 /* 879 * If we get here for a control transfer then 880 * we need to let the hardware complete the 881 * status phase. That is, we're not done 882 * quite yet. 883 * 884 * Otherwise, we're done. 885 */ 886 if (xt == UE_CONTROL) { 887 break; 888 } 889 goto done; 890 } 891 } 892 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 893 ex, ex->ex_sqtdstart, 0, 0); 894 #ifdef EHCI_DEBUG 895 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 0, 0); 896 ehci_dump_sqtds(ex->ex_sqtdstart); 897 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 0); 898 #endif 899 return; 900 } 901 done: 902 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 903 callout_stop(&ex->ex_xfer.ux_callout); 904 ehci_idone(ex); 905 } 906 907 Static void 908 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 909 { 910 ehci_soft_itd_t *itd; 911 int i; 912 913 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 914 915 KASSERT(mutex_owned(&sc->sc_lock)); 916 917 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 918 return; 919 920 if (ex->ex_itdstart == NULL) { 921 printf("ehci_check_itd_intr: not valid itd\n"); 922 return; 923 } 924 925 itd = ex->ex_itdend; 926 #ifdef DIAGNOSTIC 927 if (itd == NULL) { 928 printf("ehci_check_itd_intr: itdend == 0\n"); 929 return; 930 } 931 #endif 932 933 /* 934 * check no active transfers in last itd, meaning we're finished 935 */ 936 937 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 938 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 939 BUS_DMASYNC_POSTREAD); 940 941 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 942 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 943 break; 944 } 945 946 if (i == EHCI_ITD_NUFRAMES) { 947 goto done; /* All 8 descriptors inactive, it's done */ 948 } 949 950 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 951 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 952 953 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 954 ex->ex_itdstart, 0, 0); 955 return; 956 done: 957 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 958 callout_stop(&ex->ex_xfer.ux_callout); 959 ehci_idone(ex); 960 } 961 962 void 963 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 964 { 965 ehci_soft_sitd_t *sitd; 966 967 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 968 969 KASSERT(mutex_owned(&sc->sc_lock)); 970 971 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 972 return; 973 974 if (ex->ex_sitdstart == NULL) { 975 printf("ehci_check_sitd_intr: not valid sitd\n"); 976 return; 977 } 978 979 sitd = ex->ex_sitdend; 980 #ifdef DIAGNOSTIC 981 if (sitd == NULL) { 982 printf("ehci_check_sitd_intr: sitdend == 0\n"); 983 return; 984 } 985 #endif 986 987 /* 988 * check no active transfers in last sitd, meaning we're finished 989 */ 990 991 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 992 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_POSTWRITE | 993 BUS_DMASYNC_POSTREAD); 994 995 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 996 return; 997 998 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 999 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1000 1001 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1002 callout_stop(&(ex->ex_xfer.ux_callout)); 1003 ehci_idone(ex); 1004 } 1005 1006 1007 Static void 1008 ehci_idone(struct ehci_xfer *ex) 1009 { 1010 struct usbd_xfer *xfer = &ex->ex_xfer; 1011 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1012 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1013 ehci_soft_qtd_t *sqtd, *lsqtd; 1014 uint32_t status = 0, nstatus = 0; 1015 int actlen; 1016 1017 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1018 1019 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1020 1021 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1022 1023 #ifdef DIAGNOSTIC 1024 #ifdef EHCI_DEBUG 1025 if (ex->ex_isdone) { 1026 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1027 ehci_dump_exfer(ex); 1028 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1029 } 1030 #endif 1031 KASSERT(!ex->ex_isdone); 1032 ex->ex_isdone = true; 1033 #endif 1034 1035 if (xfer->ux_status == USBD_CANCELLED || 1036 xfer->ux_status == USBD_TIMEOUT) { 1037 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1038 return; 1039 } 1040 1041 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1042 1043 /* The transfer is done, compute actual length and status. */ 1044 1045 u_int xfertype, speed; 1046 1047 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1048 speed = xfer->ux_pipe->up_dev->ud_speed; 1049 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1050 /* HS isoc transfer */ 1051 1052 struct ehci_soft_itd *itd; 1053 int i, nframes, len, uframes; 1054 1055 nframes = 0; 1056 actlen = 0; 1057 1058 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1059 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1060 1061 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1062 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1063 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1064 BUS_DMASYNC_POSTREAD); 1065 1066 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1067 /* 1068 * XXX - driver didn't fill in the frame full 1069 * of uframes. This leads to scheduling 1070 * inefficiencies, but working around 1071 * this doubles complexity of tracking 1072 * an xfer. 1073 */ 1074 if (nframes >= xfer->ux_nframes) 1075 break; 1076 1077 status = le32toh(itd->itd.itd_ctl[i]); 1078 len = EHCI_ITD_GET_LEN(status); 1079 if (EHCI_ITD_GET_STATUS(status) != 0) 1080 len = 0; /*No valid data on error*/ 1081 1082 xfer->ux_frlengths[nframes++] = len; 1083 actlen += len; 1084 } 1085 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1086 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1087 1088 if (nframes >= xfer->ux_nframes) 1089 break; 1090 } 1091 1092 xfer->ux_actlen = actlen; 1093 xfer->ux_status = USBD_NORMAL_COMPLETION; 1094 goto end; 1095 } 1096 1097 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1098 /* FS isoc transfer */ 1099 struct ehci_soft_sitd *sitd; 1100 int nframes, len; 1101 1102 nframes = 0; 1103 actlen = 0; 1104 1105 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1106 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1107 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_POSTWRITE | 1108 BUS_DMASYNC_POSTREAD); 1109 1110 /* 1111 * XXX - driver didn't fill in the frame full 1112 * of uframes. This leads to scheduling 1113 * inefficiencies, but working around 1114 * this doubles complexity of tracking 1115 * an xfer. 1116 */ 1117 if (nframes >= xfer->ux_nframes) 1118 break; 1119 1120 status = le32toh(sitd->sitd.sitd_trans); 1121 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1122 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1123 1124 len = EHCI_SITD_GET_LEN(status); 1125 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1126 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1127 /* No valid data on error */ 1128 len = xfer->ux_frlengths[nframes]; 1129 } 1130 1131 /* 1132 * frlengths[i]: # of bytes to send 1133 * len: # of bytes host didn't send 1134 */ 1135 xfer->ux_frlengths[nframes] -= len; 1136 /* frlengths[i]: # of bytes host sent */ 1137 actlen += xfer->ux_frlengths[nframes++]; 1138 1139 if (nframes >= xfer->ux_nframes) 1140 break; 1141 } 1142 1143 xfer->ux_actlen = actlen; 1144 xfer->ux_status = USBD_NORMAL_COMPLETION; 1145 goto end; 1146 } 1147 KASSERT(xfertype != UE_ISOCHRONOUS); 1148 1149 /* Continue processing xfers using queue heads */ 1150 1151 #ifdef EHCI_DEBUG 1152 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1153 ehci_dump_sqtds(ex->ex_sqtdstart); 1154 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1155 #endif 1156 1157 lsqtd = ex->ex_sqtdend; 1158 actlen = 0; 1159 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1160 sqtd = sqtd->nextqtd) { 1161 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1162 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1163 nstatus = le32toh(sqtd->qtd.qtd_status); 1164 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1165 BUS_DMASYNC_PREREAD); 1166 if (nstatus & EHCI_QTD_ACTIVE) 1167 break; 1168 1169 status = nstatus; 1170 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1171 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1172 } 1173 1174 1175 /* 1176 * If there are left over TDs we need to update the toggle. 1177 * The default pipe doesn't need it since control transfers 1178 * start the toggle at 0 every time. 1179 * For a short transfer we need to update the toggle for the missing 1180 * packets within the qTD. 1181 */ 1182 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1183 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1184 USBHIST_LOG(ehcidebug, 1185 "toggle update status=0x%08x nstatus=0x%08x", 1186 status, nstatus, 0, 0); 1187 #if 0 1188 ehci_dump_sqh(epipe->sqh); 1189 ehci_dump_sqtds(ex->ex_sqtdstart); 1190 #endif 1191 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1192 } 1193 1194 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1195 actlen, status, 0); 1196 xfer->ux_actlen = actlen; 1197 if (status & EHCI_QTD_HALTED) { 1198 #ifdef EHCI_DEBUG 1199 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1200 xfer->ux_pipe->up_dev->ud_addr, 1201 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1202 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1203 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1204 0, 0); 1205 USBHIST_LOG(ehcidebug, 1206 "active =%d halted=%d buferr=%d babble=%d", 1207 status & EHCI_QTD_ACTIVE ? 1 : 0, 1208 status & EHCI_QTD_HALTED ? 1 : 0, 1209 status & EHCI_QTD_BUFERR ? 1 : 0, 1210 status & EHCI_QTD_BABBLE ? 1 : 0); 1211 1212 USBHIST_LOG(ehcidebug, 1213 "xacterr=%d missed=%d split =%d ping =%d", 1214 status & EHCI_QTD_XACTERR ? 1 : 0, 1215 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1216 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1217 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1218 1219 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1220 ehci_dump_sqh(epipe->sqh); 1221 ehci_dump_sqtds(ex->ex_sqtdstart); 1222 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1223 #endif 1224 /* low&full speed has an extra error flag */ 1225 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1226 EHCI_QH_SPEED_HIGH) 1227 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1228 else 1229 status &= EHCI_QTD_STATERRS; 1230 if (status == 0) /* no other errors means a stall */ { 1231 xfer->ux_status = USBD_STALLED; 1232 } else { 1233 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1234 } 1235 /* XXX need to reset TT on missed microframe */ 1236 if (status & EHCI_QTD_MISSEDMICRO) { 1237 printf("%s: missed microframe, TT reset not " 1238 "implemented, hub might be inoperational\n", 1239 device_xname(sc->sc_dev)); 1240 } 1241 } else { 1242 xfer->ux_status = USBD_NORMAL_COMPLETION; 1243 } 1244 1245 end: 1246 /* 1247 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1248 * during this call, before methods->done is called: dma sync required 1249 * beforehand? 1250 */ 1251 usb_transfer_complete(xfer); 1252 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1253 } 1254 1255 /* 1256 * Wait here until controller claims to have an interrupt. 1257 * Then call ehci_intr and return. Use timeout to avoid waiting 1258 * too long. 1259 */ 1260 Static void 1261 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1262 { 1263 int timo; 1264 uint32_t intrs; 1265 1266 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1267 1268 xfer->ux_status = USBD_IN_PROGRESS; 1269 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1270 usb_delay_ms(&sc->sc_bus, 1); 1271 if (sc->sc_dying) 1272 break; 1273 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1274 sc->sc_eintrs; 1275 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1276 #ifdef EHCI_DEBUG 1277 if (ehcidebug > 15) 1278 ehci_dump_regs(sc); 1279 #endif 1280 if (intrs) { 1281 mutex_spin_enter(&sc->sc_intr_lock); 1282 ehci_intr1(sc); 1283 mutex_spin_exit(&sc->sc_intr_lock); 1284 if (xfer->ux_status != USBD_IN_PROGRESS) 1285 return; 1286 } 1287 } 1288 1289 /* Timeout */ 1290 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1291 xfer->ux_status = USBD_TIMEOUT; 1292 mutex_enter(&sc->sc_lock); 1293 usb_transfer_complete(xfer); 1294 mutex_exit(&sc->sc_lock); 1295 /* XXX should free TD */ 1296 } 1297 1298 Static void 1299 ehci_poll(struct usbd_bus *bus) 1300 { 1301 ehci_softc_t *sc = bus->ub_hcpriv; 1302 1303 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1304 1305 #ifdef EHCI_DEBUG 1306 static int last; 1307 int new; 1308 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1309 if (new != last) { 1310 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1311 last = new; 1312 } 1313 #endif 1314 1315 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1316 mutex_spin_enter(&sc->sc_intr_lock); 1317 ehci_intr1(sc); 1318 mutex_spin_exit(&sc->sc_intr_lock); 1319 } 1320 } 1321 1322 void 1323 ehci_childdet(device_t self, device_t child) 1324 { 1325 struct ehci_softc *sc = device_private(self); 1326 1327 KASSERT(sc->sc_child == child); 1328 sc->sc_child = NULL; 1329 } 1330 1331 int 1332 ehci_detach(struct ehci_softc *sc, int flags) 1333 { 1334 int rv = 0; 1335 1336 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1337 1338 if (sc->sc_child != NULL) 1339 rv = config_detach(sc->sc_child, flags); 1340 1341 if (rv != 0) 1342 return rv; 1343 1344 callout_halt(&sc->sc_tmo_intrlist, NULL); 1345 callout_destroy(&sc->sc_tmo_intrlist); 1346 1347 /* XXX free other data structures XXX */ 1348 if (sc->sc_softitds) 1349 kmem_free(sc->sc_softitds, 1350 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1351 cv_destroy(&sc->sc_doorbell); 1352 cv_destroy(&sc->sc_softwake_cv); 1353 1354 #if 0 1355 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1356 1357 softint_disestablish(sc->sc_doorbell_si); 1358 softint_disestablish(sc->sc_pcd_si); 1359 1360 mutex_destroy(&sc->sc_lock); 1361 mutex_destroy(&sc->sc_intr_lock); 1362 #endif 1363 1364 pool_cache_destroy(sc->sc_xferpool); 1365 1366 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1367 1368 return rv; 1369 } 1370 1371 1372 int 1373 ehci_activate(device_t self, enum devact act) 1374 { 1375 struct ehci_softc *sc = device_private(self); 1376 1377 switch (act) { 1378 case DVACT_DEACTIVATE: 1379 sc->sc_dying = 1; 1380 return 0; 1381 default: 1382 return EOPNOTSUPP; 1383 } 1384 } 1385 1386 /* 1387 * Handle suspend/resume. 1388 * 1389 * We need to switch to polling mode here, because this routine is 1390 * called from an interrupt context. This is all right since we 1391 * are almost suspended anyway. 1392 * 1393 * Note that this power handler isn't to be registered directly; the 1394 * bus glue needs to call out to it. 1395 */ 1396 bool 1397 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1398 { 1399 ehci_softc_t *sc = device_private(dv); 1400 int i; 1401 uint32_t cmd, hcr; 1402 1403 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1404 1405 mutex_spin_enter(&sc->sc_intr_lock); 1406 sc->sc_bus.ub_usepolling++; 1407 mutex_spin_exit(&sc->sc_intr_lock); 1408 1409 for (i = 1; i <= sc->sc_noport; i++) { 1410 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1411 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1412 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1413 } 1414 1415 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1416 1417 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1418 EOWRITE4(sc, EHCI_USBCMD, cmd); 1419 1420 for (i = 0; i < 100; i++) { 1421 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1422 if (hcr == 0) 1423 break; 1424 1425 usb_delay_ms(&sc->sc_bus, 1); 1426 } 1427 if (hcr != 0) 1428 printf("%s: reset timeout\n", device_xname(dv)); 1429 1430 cmd &= ~EHCI_CMD_RS; 1431 EOWRITE4(sc, EHCI_USBCMD, cmd); 1432 1433 for (i = 0; i < 100; i++) { 1434 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1435 if (hcr == EHCI_STS_HCH) 1436 break; 1437 1438 usb_delay_ms(&sc->sc_bus, 1); 1439 } 1440 if (hcr != EHCI_STS_HCH) 1441 printf("%s: config timeout\n", device_xname(dv)); 1442 1443 mutex_spin_enter(&sc->sc_intr_lock); 1444 sc->sc_bus.ub_usepolling--; 1445 mutex_spin_exit(&sc->sc_intr_lock); 1446 1447 return true; 1448 } 1449 1450 bool 1451 ehci_resume(device_t dv, const pmf_qual_t *qual) 1452 { 1453 ehci_softc_t *sc = device_private(dv); 1454 int i; 1455 uint32_t cmd, hcr; 1456 1457 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1458 1459 /* restore things in case the bios sucks */ 1460 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1461 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1462 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1463 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1464 1465 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1466 1467 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1468 1469 hcr = 0; 1470 for (i = 1; i <= sc->sc_noport; i++) { 1471 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1472 if ((cmd & EHCI_PS_PO) == 0 && 1473 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1474 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1475 hcr = 1; 1476 } 1477 } 1478 1479 if (hcr) { 1480 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1481 1482 for (i = 1; i <= sc->sc_noport; i++) { 1483 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1484 if ((cmd & EHCI_PS_PO) == 0 && 1485 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1486 EOWRITE4(sc, EHCI_PORTSC(i), 1487 cmd & ~EHCI_PS_FPR); 1488 } 1489 } 1490 1491 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1492 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1493 1494 for (i = 0; i < 100; i++) { 1495 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1496 if (hcr != EHCI_STS_HCH) 1497 break; 1498 1499 usb_delay_ms(&sc->sc_bus, 1); 1500 } 1501 if (hcr == EHCI_STS_HCH) 1502 printf("%s: config timeout\n", device_xname(dv)); 1503 1504 return true; 1505 } 1506 1507 /* 1508 * Shut down the controller when the system is going down. 1509 */ 1510 bool 1511 ehci_shutdown(device_t self, int flags) 1512 { 1513 ehci_softc_t *sc = device_private(self); 1514 1515 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1516 1517 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1518 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1519 return true; 1520 } 1521 1522 Static struct usbd_xfer * 1523 ehci_allocx(struct usbd_bus *bus) 1524 { 1525 struct ehci_softc *sc = bus->ub_hcpriv; 1526 struct usbd_xfer *xfer; 1527 1528 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1529 if (xfer != NULL) { 1530 memset(xfer, 0, sizeof(struct ehci_xfer)); 1531 #ifdef DIAGNOSTIC 1532 EXFER(xfer)->ex_isdone = true; 1533 xfer->ux_state = XFER_BUSY; 1534 #endif 1535 } 1536 return xfer; 1537 } 1538 1539 Static void 1540 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1541 { 1542 struct ehci_softc *sc = bus->ub_hcpriv; 1543 1544 KASSERT(xfer->ux_state == XFER_BUSY); 1545 KASSERT(EXFER(xfer)->ex_isdone); 1546 #ifdef DIAGNOSTIC 1547 xfer->ux_state = XFER_FREE; 1548 #endif 1549 pool_cache_put(sc->sc_xferpool, xfer); 1550 } 1551 1552 Static void 1553 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1554 { 1555 struct ehci_softc *sc = bus->ub_hcpriv; 1556 1557 *lock = &sc->sc_lock; 1558 } 1559 1560 Static void 1561 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1562 { 1563 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1564 1565 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1566 1567 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1568 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1569 #ifdef EHCI_DEBUG 1570 if (ehcidebug) 1571 usbd_dump_pipe(pipe); 1572 #endif 1573 epipe->nexttoggle = 0; 1574 } 1575 1576 Static void 1577 ehci_noop(struct usbd_pipe *pipe) 1578 { 1579 } 1580 1581 #ifdef EHCI_DEBUG 1582 /* 1583 * Unused function - this is meant to be called from a kernel 1584 * debugger. 1585 */ 1586 void 1587 ehci_dump(void) 1588 { 1589 ehci_softc_t *sc = theehci; 1590 int i; 1591 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1592 EOREAD4(sc, EHCI_USBCMD), 1593 EOREAD4(sc, EHCI_USBSTS), 1594 EOREAD4(sc, EHCI_USBINTR)); 1595 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1596 EOREAD4(sc, EHCI_FRINDEX), 1597 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1598 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1599 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1600 for (i = 1; i <= sc->sc_noport; i++) 1601 printf("port %d status=0x%08x\n", i, 1602 EOREAD4(sc, EHCI_PORTSC(i))); 1603 } 1604 1605 Static void 1606 ehci_dump_regs(ehci_softc_t *sc) 1607 { 1608 int i; 1609 1610 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1611 1612 USBHIST_LOG(ehcidebug, 1613 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1614 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1615 EOREAD4(sc, EHCI_USBINTR), 0); 1616 USBHIST_LOG(ehcidebug, 1617 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1618 "async = 0x%08x", 1619 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1620 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1621 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1622 for (i = 1; i <= sc->sc_noport; i += 2) { 1623 if (i == sc->sc_noport) { 1624 USBHIST_LOG(ehcidebug, 1625 "port %d status = 0x%08x", i, 1626 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1627 } else { 1628 USBHIST_LOG(ehcidebug, 1629 "port %d status = 0x%08x port %d status = 0x%08x", 1630 i, EOREAD4(sc, EHCI_PORTSC(i)), 1631 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1632 } 1633 } 1634 } 1635 1636 #ifdef EHCI_DEBUG 1637 #define ehci_dump_link(link, type) do { \ 1638 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1639 link, \ 1640 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1641 if (type) { \ 1642 USBHIST_LOG(ehcidebug, \ 1643 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1644 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1645 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1646 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1647 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1648 } \ 1649 } while(0) 1650 #else 1651 #define ehci_dump_link(link, type) 1652 #endif 1653 1654 Static void 1655 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1656 { 1657 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1658 int i; 1659 uint32_t stop = 0; 1660 1661 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1662 ehci_dump_sqtd(sqtd); 1663 usb_syncmem(&sqtd->dma, 1664 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1665 sizeof(sqtd->qtd), 1666 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1667 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1668 usb_syncmem(&sqtd->dma, 1669 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1670 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1671 } 1672 if (!stop) 1673 USBHIST_LOG(ehcidebug, 1674 "dump aborted, too many TDs", 0, 0, 0, 0); 1675 } 1676 1677 Static void 1678 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1679 { 1680 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1681 1682 usb_syncmem(&sqtd->dma, sqtd->offs, 1683 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1684 1685 USBHIST_LOGN(ehcidebug, 10, 1686 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1687 ehci_dump_qtd(&sqtd->qtd); 1688 1689 usb_syncmem(&sqtd->dma, sqtd->offs, 1690 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1691 } 1692 1693 Static void 1694 ehci_dump_qtd(ehci_qtd_t *qtd) 1695 { 1696 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1697 1698 #ifdef USBHIST 1699 uint32_t s = le32toh(qtd->qtd_status); 1700 #endif 1701 1702 USBHIST_LOGN(ehcidebug, 10, 1703 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1704 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1705 USBHIST_LOGN(ehcidebug, 10, 1706 " toggle = %d ioc = %d bytes = %#x " 1707 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1708 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1709 USBHIST_LOGN(ehcidebug, 10, 1710 " cerr = %d pid = %d stat = %x", 1711 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1712 0); 1713 USBHIST_LOGN(ehcidebug, 10, 1714 "active =%d halted=%d buferr=%d babble=%d", 1715 s & EHCI_QTD_ACTIVE ? 1 : 0, 1716 s & EHCI_QTD_HALTED ? 1 : 0, 1717 s & EHCI_QTD_BUFERR ? 1 : 0, 1718 s & EHCI_QTD_BABBLE ? 1 : 0); 1719 USBHIST_LOGN(ehcidebug, 10, 1720 "xacterr=%d missed=%d split =%d ping =%d", 1721 s & EHCI_QTD_XACTERR ? 1 : 0, 1722 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1723 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1724 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1725 USBHIST_LOGN(ehcidebug, 10, 1726 "buffer[0] = %#x buffer[1] = %#x " 1727 "buffer[2] = %#x buffer[3] = %#x", 1728 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1729 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1730 USBHIST_LOGN(ehcidebug, 10, 1731 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1732 } 1733 1734 Static void 1735 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1736 { 1737 #ifdef USBHIST 1738 ehci_qh_t *qh = &sqh->qh; 1739 ehci_link_t link; 1740 #endif 1741 uint32_t endp, endphub; 1742 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1743 1744 usb_syncmem(&sqh->dma, sqh->offs, 1745 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1746 1747 USBHIST_LOGN(ehcidebug, 10, 1748 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1749 link = le32toh(qh->qh_link); 1750 ehci_dump_link(link, true); 1751 1752 endp = le32toh(qh->qh_endp); 1753 USBHIST_LOGN(ehcidebug, 10, 1754 " endp = %#x", endp, 0, 0, 0); 1755 USBHIST_LOGN(ehcidebug, 10, 1756 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1757 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1758 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1759 USBHIST_LOGN(ehcidebug, 10, 1760 " dtc = %d hrecl = %d", 1761 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1762 USBHIST_LOGN(ehcidebug, 10, 1763 " ctl = %d nrl = %d mpl = %#x(%d)", 1764 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1765 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1766 1767 endphub = le32toh(qh->qh_endphub); 1768 USBHIST_LOGN(ehcidebug, 10, 1769 " endphub = %#x", endphub, 0, 0, 0); 1770 USBHIST_LOGN(ehcidebug, 10, 1771 " smask = 0x%02x cmask = 0x%02x", 1772 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1773 USBHIST_LOGN(ehcidebug, 10, 1774 " huba = 0x%02x port = %d mult = %d", 1775 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1776 EHCI_QH_GET_MULT(endphub), 0); 1777 1778 link = le32toh(qh->qh_curqtd); 1779 ehci_dump_link(link, false); 1780 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1781 ehci_dump_qtd(&qh->qh_qtd); 1782 1783 usb_syncmem(&sqh->dma, sqh->offs, 1784 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1785 } 1786 1787 Static void 1788 ehci_dump_itd(struct ehci_soft_itd *itd) 1789 { 1790 ehci_isoc_trans_t t; 1791 ehci_isoc_bufr_ptr_t b, b2, b3; 1792 int i; 1793 1794 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1795 1796 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1797 0, 0); 1798 1799 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1800 t = le32toh(itd->itd.itd_ctl[i]); 1801 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1802 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1803 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1804 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1805 EHCI_ITD_GET_OFFS(t), 0); 1806 } 1807 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1808 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1809 USBHIST_LOG(ehcidebug, " %x", 1810 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1811 1812 b = le32toh(itd->itd.itd_bufr[0]); 1813 b2 = le32toh(itd->itd.itd_bufr[1]); 1814 b3 = le32toh(itd->itd.itd_bufr[2]); 1815 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1816 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1817 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1818 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1819 } 1820 1821 Static void 1822 ehci_dump_sitd(struct ehci_soft_itd *itd) 1823 { 1824 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1825 1826 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1827 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1828 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1829 itd->xfer_next, itd->physaddr, itd->slot, 0); 1830 } 1831 1832 Static void 1833 ehci_dump_exfer(struct ehci_xfer *ex) 1834 { 1835 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1836 1837 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1838 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1839 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1840 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1841 } 1842 #endif 1843 1844 Static usbd_status 1845 ehci_open(struct usbd_pipe *pipe) 1846 { 1847 struct usbd_device *dev = pipe->up_dev; 1848 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1849 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1850 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1851 uint8_t addr = dev->ud_addr; 1852 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1853 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1854 ehci_soft_qh_t *sqh; 1855 usbd_status err; 1856 int ival, speed, naks; 1857 int hshubaddr, hshubport; 1858 1859 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1860 1861 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1862 pipe, addr, ed->bEndpointAddress, rhaddr); 1863 1864 if (dev->ud_myhsport) { 1865 /* 1866 * When directly attached FS/LS device while doing embedded 1867 * transaction translations and we are the hub, set the hub 1868 * address to 0 (us). 1869 */ 1870 if (!(sc->sc_flags & EHCIF_ETTF) 1871 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1872 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1873 } else { 1874 hshubaddr = 0; 1875 } 1876 hshubport = dev->ud_myhsport->up_portno; 1877 } else { 1878 hshubaddr = 0; 1879 hshubport = 0; 1880 } 1881 1882 if (sc->sc_dying) 1883 return USBD_IOERROR; 1884 1885 /* toggle state needed for bulk endpoints */ 1886 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1887 1888 if (addr == rhaddr) { 1889 switch (ed->bEndpointAddress) { 1890 case USB_CONTROL_ENDPOINT: 1891 pipe->up_methods = &roothub_ctrl_methods; 1892 break; 1893 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1894 pipe->up_methods = &ehci_root_intr_methods; 1895 break; 1896 default: 1897 USBHIST_LOG(ehcidebug, 1898 "bad bEndpointAddress 0x%02x", 1899 ed->bEndpointAddress, 0, 0, 0); 1900 return USBD_INVAL; 1901 } 1902 return USBD_NORMAL_COMPLETION; 1903 } 1904 1905 /* XXX All this stuff is only valid for async. */ 1906 switch (dev->ud_speed) { 1907 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1908 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1909 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1910 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1911 } 1912 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1913 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1914 hshubaddr, hshubport, 0, 0); 1915 return USBD_INVAL; 1916 } 1917 1918 /* 1919 * For interrupt transfer, nak throttling must be disabled, but for 1920 * the other transfer type, nak throttling should be enabled from the 1921 * viewpoint that avoids the memory thrashing. 1922 */ 1923 naks = (xfertype == UE_INTERRUPT) ? 0 1924 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1925 1926 /* Allocate sqh for everything, save isoc xfers */ 1927 if (xfertype != UE_ISOCHRONOUS) { 1928 sqh = ehci_alloc_sqh(sc); 1929 if (sqh == NULL) 1930 return USBD_NOMEM; 1931 /* qh_link filled when the QH is added */ 1932 sqh->qh.qh_endp = htole32( 1933 EHCI_QH_SET_ADDR(addr) | 1934 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1935 EHCI_QH_SET_EPS(speed) | 1936 EHCI_QH_DTC | 1937 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1938 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1939 EHCI_QH_CTL : 0) | 1940 EHCI_QH_SET_NRL(naks) 1941 ); 1942 sqh->qh.qh_endphub = htole32( 1943 EHCI_QH_SET_MULT(1) | 1944 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1945 ); 1946 if (speed != EHCI_QH_SPEED_HIGH) 1947 sqh->qh.qh_endphub |= htole32( 1948 EHCI_QH_SET_PORT(hshubport) | 1949 EHCI_QH_SET_HUBA(hshubaddr) | 1950 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1951 ); 1952 sqh->qh.qh_curqtd = EHCI_NULL; 1953 /* Fill the overlay qTD */ 1954 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1955 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1956 sqh->qh.qh_qtd.qtd_status = htole32(0); 1957 1958 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1959 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1960 epipe->sqh = sqh; 1961 } else { 1962 sqh = NULL; 1963 } /*xfertype == UE_ISOC*/ 1964 1965 switch (xfertype) { 1966 case UE_CONTROL: 1967 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1968 0, &epipe->ctrl.reqdma); 1969 #ifdef EHCI_DEBUG 1970 if (err) 1971 printf("ehci_open: usb_allocmem()=%d\n", err); 1972 #endif 1973 if (err) 1974 goto bad; 1975 pipe->up_methods = &ehci_device_ctrl_methods; 1976 mutex_enter(&sc->sc_lock); 1977 ehci_add_qh(sc, sqh, sc->sc_async_head); 1978 mutex_exit(&sc->sc_lock); 1979 break; 1980 case UE_BULK: 1981 pipe->up_methods = &ehci_device_bulk_methods; 1982 mutex_enter(&sc->sc_lock); 1983 ehci_add_qh(sc, sqh, sc->sc_async_head); 1984 mutex_exit(&sc->sc_lock); 1985 break; 1986 case UE_INTERRUPT: 1987 pipe->up_methods = &ehci_device_intr_methods; 1988 ival = pipe->up_interval; 1989 if (ival == USBD_DEFAULT_INTERVAL) { 1990 if (speed == EHCI_QH_SPEED_HIGH) { 1991 if (ed->bInterval > 16) { 1992 /* 1993 * illegal with high-speed, but there 1994 * were documentation bugs in the spec, 1995 * so be generous 1996 */ 1997 ival = 256; 1998 } else 1999 ival = (1 << (ed->bInterval - 1)) / 8; 2000 } else 2001 ival = ed->bInterval; 2002 } 2003 err = ehci_device_setintr(sc, sqh, ival); 2004 if (err) 2005 goto bad; 2006 break; 2007 case UE_ISOCHRONOUS: 2008 if (speed == EHCI_QH_SPEED_HIGH) 2009 pipe->up_methods = &ehci_device_isoc_methods; 2010 else 2011 pipe->up_methods = &ehci_device_fs_isoc_methods; 2012 if (ed->bInterval == 0 || ed->bInterval > 16) { 2013 printf("ehci: opening pipe with invalid bInterval\n"); 2014 err = USBD_INVAL; 2015 goto bad; 2016 } 2017 if (UGETW(ed->wMaxPacketSize) == 0) { 2018 printf("ehci: zero length endpoint open request\n"); 2019 err = USBD_INVAL; 2020 goto bad; 2021 } 2022 epipe->isoc.next_frame = 0; 2023 epipe->isoc.cur_xfers = 0; 2024 break; 2025 default: 2026 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2027 err = USBD_INVAL; 2028 goto bad; 2029 } 2030 return USBD_NORMAL_COMPLETION; 2031 2032 bad: 2033 if (sqh != NULL) 2034 ehci_free_sqh(sc, sqh); 2035 return err; 2036 } 2037 2038 /* 2039 * Add an ED to the schedule. Called with USB lock held. 2040 */ 2041 Static void 2042 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2043 { 2044 2045 KASSERT(mutex_owned(&sc->sc_lock)); 2046 2047 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2048 2049 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2050 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2051 2052 sqh->next = head->next; 2053 sqh->qh.qh_link = head->qh.qh_link; 2054 2055 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2056 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2057 2058 head->next = sqh; 2059 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2060 2061 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2062 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2063 2064 #ifdef EHCI_DEBUG 2065 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2066 ehci_dump_sqh(sqh); 2067 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2068 #endif 2069 } 2070 2071 /* 2072 * Remove an ED from the schedule. Called with USB lock held. 2073 */ 2074 Static void 2075 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2076 { 2077 ehci_soft_qh_t *p; 2078 2079 KASSERT(mutex_owned(&sc->sc_lock)); 2080 2081 /* XXX */ 2082 for (p = head; p != NULL && p->next != sqh; p = p->next) 2083 ; 2084 if (p == NULL) 2085 panic("ehci_rem_qh: ED not found"); 2086 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2087 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2088 p->next = sqh->next; 2089 p->qh.qh_link = sqh->qh.qh_link; 2090 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2091 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2092 2093 ehci_sync_hc(sc); 2094 } 2095 2096 Static void 2097 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2098 { 2099 int i; 2100 uint32_t status; 2101 2102 /* Save toggle bit and ping status. */ 2103 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2104 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2105 status = sqh->qh.qh_qtd.qtd_status & 2106 htole32(EHCI_QTD_TOGGLE_MASK | 2107 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2108 /* Set HALTED to make hw leave it alone. */ 2109 sqh->qh.qh_qtd.qtd_status = 2110 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2111 usb_syncmem(&sqh->dma, 2112 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2113 sizeof(sqh->qh.qh_qtd.qtd_status), 2114 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2115 sqh->qh.qh_curqtd = 0; 2116 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2117 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2118 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2119 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2120 sqh->sqtd = sqtd; 2121 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2122 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2123 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2124 sqh->qh.qh_qtd.qtd_status = status; 2125 usb_syncmem(&sqh->dma, 2126 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2127 sizeof(sqh->qh.qh_qtd.qtd_status), 2128 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2129 } 2130 2131 /* 2132 * Ensure that the HC has released all references to the QH. We do this 2133 * by asking for a Async Advance Doorbell interrupt and then we wait for 2134 * the interrupt. 2135 * To make this easier we first obtain exclusive use of the doorbell. 2136 */ 2137 Static void 2138 ehci_sync_hc(ehci_softc_t *sc) 2139 { 2140 int error __diagused; 2141 2142 KASSERT(mutex_owned(&sc->sc_lock)); 2143 2144 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2145 2146 if (sc->sc_dying) { 2147 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2148 return; 2149 } 2150 /* ask for doorbell */ 2151 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2152 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2153 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2154 2155 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2156 2157 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2158 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2159 #ifdef DIAGNOSTIC 2160 if (error) 2161 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2162 #endif 2163 } 2164 2165 Static void 2166 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2167 { 2168 struct ehci_soft_itd *itd, *prev; 2169 2170 prev = NULL; 2171 2172 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2173 panic("ehci isoc xfer being freed, but with no itd chain"); 2174 2175 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2176 prev = itd->frame_list.prev; 2177 /* Unlink itd from hardware chain, or frame array */ 2178 if (prev == NULL) { /* We're at the table head */ 2179 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2180 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2181 usb_syncmem(&sc->sc_fldma, 2182 sizeof(ehci_link_t) * itd->slot, 2183 sizeof(ehci_link_t), 2184 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2185 2186 if (itd->frame_list.next != NULL) 2187 itd->frame_list.next->frame_list.prev = NULL; 2188 } else { 2189 /* XXX this part is untested... */ 2190 prev->itd.itd_next = itd->itd.itd_next; 2191 usb_syncmem(&itd->dma, 2192 itd->offs + offsetof(ehci_itd_t, itd_next), 2193 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2194 2195 prev->frame_list.next = itd->frame_list.next; 2196 if (itd->frame_list.next != NULL) 2197 itd->frame_list.next->frame_list.prev = prev; 2198 } 2199 } 2200 2201 prev = NULL; 2202 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2203 if (prev != NULL) 2204 ehci_free_itd(sc, prev); 2205 prev = itd; 2206 } 2207 if (prev) 2208 ehci_free_itd(sc, prev); 2209 exfer->ex_itdstart = NULL; 2210 exfer->ex_itdend = NULL; 2211 } 2212 2213 Static void 2214 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2215 { 2216 struct ehci_soft_sitd *sitd, *prev; 2217 2218 prev = NULL; 2219 2220 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2221 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2222 2223 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2224 prev = sitd->frame_list.prev; 2225 /* Unlink sitd from hardware chain, or frame array */ 2226 if (prev == NULL) { /* We're at the table head */ 2227 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2228 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2229 usb_syncmem(&sc->sc_fldma, 2230 sizeof(ehci_link_t) * sitd->slot, 2231 sizeof(ehci_link_t), 2232 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2233 2234 if (sitd->frame_list.next != NULL) 2235 sitd->frame_list.next->frame_list.prev = NULL; 2236 } else { 2237 /* XXX this part is untested... */ 2238 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2239 usb_syncmem(&sitd->dma, 2240 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2241 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2242 2243 prev->frame_list.next = sitd->frame_list.next; 2244 if (sitd->frame_list.next != NULL) 2245 sitd->frame_list.next->frame_list.prev = prev; 2246 } 2247 } 2248 2249 prev = NULL; 2250 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2251 if (prev != NULL) 2252 ehci_free_sitd(sc, prev); 2253 prev = sitd; 2254 } 2255 if (prev) 2256 ehci_free_sitd(sc, prev); 2257 exfer->ex_sitdstart = NULL; 2258 exfer->ex_sitdend = NULL; 2259 } 2260 2261 /***********/ 2262 2263 Static int 2264 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2265 void *buf, int buflen) 2266 { 2267 ehci_softc_t *sc = bus->ub_hcpriv; 2268 usb_hub_descriptor_t hubd; 2269 usb_port_status_t ps; 2270 uint16_t len, value, index; 2271 int l, totlen = 0; 2272 int port, i; 2273 uint32_t v; 2274 2275 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2276 2277 if (sc->sc_dying) 2278 return -1; 2279 2280 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2281 req->bmRequestType, req->bRequest, 0, 0); 2282 2283 len = UGETW(req->wLength); 2284 value = UGETW(req->wValue); 2285 index = UGETW(req->wIndex); 2286 2287 #define C(x,y) ((x) | ((y) << 8)) 2288 switch (C(req->bRequest, req->bmRequestType)) { 2289 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2290 if (len == 0) 2291 break; 2292 switch (value) { 2293 case C(0, UDESC_DEVICE): { 2294 usb_device_descriptor_t devd; 2295 totlen = min(buflen, sizeof(devd)); 2296 memcpy(&devd, buf, totlen); 2297 USETW(devd.idVendor, sc->sc_id_vendor); 2298 memcpy(buf, &devd, totlen); 2299 break; 2300 2301 } 2302 #define sd ((usb_string_descriptor_t *)buf) 2303 case C(1, UDESC_STRING): 2304 /* Vendor */ 2305 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2306 break; 2307 case C(2, UDESC_STRING): 2308 /* Product */ 2309 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2310 break; 2311 #undef sd 2312 default: 2313 /* default from usbroothub */ 2314 return buflen; 2315 } 2316 break; 2317 2318 /* Hub requests */ 2319 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2320 break; 2321 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2322 USBHIST_LOG(ehcidebug, 2323 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2324 0, 0); 2325 if (index < 1 || index > sc->sc_noport) { 2326 return -1; 2327 } 2328 port = EHCI_PORTSC(index); 2329 v = EOREAD4(sc, port); 2330 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2331 v &= ~EHCI_PS_CLEAR; 2332 switch (value) { 2333 case UHF_PORT_ENABLE: 2334 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2335 break; 2336 case UHF_PORT_SUSPEND: 2337 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2338 break; 2339 v &= ~EHCI_PS_SUSP; 2340 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2341 /* see USB2 spec ch. 7.1.7.7 */ 2342 usb_delay_ms(&sc->sc_bus, 20); 2343 EOWRITE4(sc, port, v); 2344 usb_delay_ms(&sc->sc_bus, 2); 2345 #ifdef DEBUG 2346 v = EOREAD4(sc, port); 2347 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2348 printf("ehci: resume failed: %x\n", v); 2349 #endif 2350 break; 2351 case UHF_PORT_POWER: 2352 if (sc->sc_hasppc) 2353 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2354 break; 2355 case UHF_PORT_TEST: 2356 USBHIST_LOG(ehcidebug, "clear port test " 2357 "%d", index, 0, 0, 0); 2358 break; 2359 case UHF_PORT_INDICATOR: 2360 USBHIST_LOG(ehcidebug, "clear port ind " 2361 "%d", index, 0, 0, 0); 2362 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2363 break; 2364 case UHF_C_PORT_CONNECTION: 2365 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2366 break; 2367 case UHF_C_PORT_ENABLE: 2368 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2369 break; 2370 case UHF_C_PORT_SUSPEND: 2371 /* how? */ 2372 break; 2373 case UHF_C_PORT_OVER_CURRENT: 2374 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2375 break; 2376 case UHF_C_PORT_RESET: 2377 sc->sc_isreset[index] = 0; 2378 break; 2379 default: 2380 return -1; 2381 } 2382 #if 0 2383 switch(value) { 2384 case UHF_C_PORT_CONNECTION: 2385 case UHF_C_PORT_ENABLE: 2386 case UHF_C_PORT_SUSPEND: 2387 case UHF_C_PORT_OVER_CURRENT: 2388 case UHF_C_PORT_RESET: 2389 default: 2390 break; 2391 } 2392 #endif 2393 break; 2394 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2395 if (len == 0) 2396 break; 2397 if ((value & 0xff) != 0) { 2398 return -1; 2399 } 2400 totlen = min(buflen, sizeof(hubd)); 2401 memcpy(&hubd, buf, totlen); 2402 hubd.bNbrPorts = sc->sc_noport; 2403 v = EOREAD4(sc, EHCI_HCSPARAMS); 2404 USETW(hubd.wHubCharacteristics, 2405 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2406 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2407 ? UHD_PORT_IND : 0); 2408 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2409 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2410 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2411 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2412 totlen = min(totlen, hubd.bDescLength); 2413 memcpy(buf, &hubd, totlen); 2414 break; 2415 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2416 if (len != 4) { 2417 return -1; 2418 } 2419 memset(buf, 0, len); /* ? XXX */ 2420 totlen = len; 2421 break; 2422 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2423 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2424 if (index < 1 || index > sc->sc_noport) { 2425 return -1; 2426 } 2427 if (len != 4) { 2428 return -1; 2429 } 2430 v = EOREAD4(sc, EHCI_PORTSC(index)); 2431 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2432 2433 i = UPS_HIGH_SPEED; 2434 if (sc->sc_flags & EHCIF_ETTF) { 2435 /* 2436 * If we are doing embedded transaction translation, 2437 * then directly attached LS/FS devices are reset by 2438 * the EHCI controller itself. PSPD is encoded 2439 * the same way as in USBSTATUS. 2440 */ 2441 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2442 } 2443 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2444 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2445 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2446 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2447 if (v & EHCI_PS_PR) i |= UPS_RESET; 2448 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2449 if (sc->sc_vendor_port_status) 2450 i = sc->sc_vendor_port_status(sc, v, i); 2451 USETW(ps.wPortStatus, i); 2452 i = 0; 2453 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2454 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2455 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2456 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2457 USETW(ps.wPortChange, i); 2458 totlen = min(len, sizeof(ps)); 2459 memcpy(buf, &ps, totlen); 2460 break; 2461 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2462 return -1; 2463 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2464 break; 2465 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2466 if (index < 1 || index > sc->sc_noport) { 2467 return -1; 2468 } 2469 port = EHCI_PORTSC(index); 2470 v = EOREAD4(sc, port); 2471 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2472 v &= ~EHCI_PS_CLEAR; 2473 switch(value) { 2474 case UHF_PORT_ENABLE: 2475 EOWRITE4(sc, port, v | EHCI_PS_PE); 2476 break; 2477 case UHF_PORT_SUSPEND: 2478 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2479 break; 2480 case UHF_PORT_RESET: 2481 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2482 if (EHCI_PS_IS_LOWSPEED(v) 2483 && sc->sc_ncomp > 0 2484 && !(sc->sc_flags & EHCIF_ETTF)) { 2485 /* 2486 * Low speed device on non-ETTF controller or 2487 * unaccompanied controller, give up ownership. 2488 */ 2489 ehci_disown(sc, index, 1); 2490 break; 2491 } 2492 /* Start reset sequence. */ 2493 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2494 EOWRITE4(sc, port, v | EHCI_PS_PR); 2495 /* Wait for reset to complete. */ 2496 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2497 if (sc->sc_dying) { 2498 return -1; 2499 } 2500 /* 2501 * An embedded transaction translator will automatically 2502 * terminate the reset sequence so there's no need to 2503 * it. 2504 */ 2505 v = EOREAD4(sc, port); 2506 if (v & EHCI_PS_PR) { 2507 /* Terminate reset sequence. */ 2508 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2509 /* Wait for HC to complete reset. */ 2510 usb_delay_ms(&sc->sc_bus, 2511 EHCI_PORT_RESET_COMPLETE); 2512 if (sc->sc_dying) { 2513 return -1; 2514 } 2515 } 2516 2517 v = EOREAD4(sc, port); 2518 USBHIST_LOG(ehcidebug, 2519 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2520 if (v & EHCI_PS_PR) { 2521 printf("%s: port reset timeout\n", 2522 device_xname(sc->sc_dev)); 2523 return USBD_TIMEOUT; 2524 } 2525 if (!(v & EHCI_PS_PE)) { 2526 /* Not a high speed device, give up ownership.*/ 2527 ehci_disown(sc, index, 0); 2528 break; 2529 } 2530 sc->sc_isreset[index] = 1; 2531 USBHIST_LOG(ehcidebug, 2532 "ehci port %d reset, status = 0x%08x", index, v, 0, 2533 0); 2534 break; 2535 case UHF_PORT_POWER: 2536 USBHIST_LOG(ehcidebug, 2537 "set port power %d (has PPC = %d)", index, 2538 sc->sc_hasppc, 0, 0); 2539 if (sc->sc_hasppc) 2540 EOWRITE4(sc, port, v | EHCI_PS_PP); 2541 break; 2542 case UHF_PORT_TEST: 2543 USBHIST_LOG(ehcidebug, "set port test %d", 2544 index, 0, 0, 0); 2545 break; 2546 case UHF_PORT_INDICATOR: 2547 USBHIST_LOG(ehcidebug, "set port ind %d", 2548 index, 0, 0, 0); 2549 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2550 break; 2551 default: 2552 return -1; 2553 } 2554 break; 2555 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2556 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2557 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2558 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2559 break; 2560 default: 2561 /* default from usbroothub */ 2562 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2563 buflen, 0, 0, 0); 2564 2565 return buflen; 2566 } 2567 2568 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2569 2570 return totlen; 2571 } 2572 2573 Static void 2574 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2575 { 2576 int port; 2577 uint32_t v; 2578 2579 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2580 2581 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2582 #ifdef DIAGNOSTIC 2583 if (sc->sc_npcomp != 0) { 2584 int i = (index-1) / sc->sc_npcomp; 2585 if (i >= sc->sc_ncomp) 2586 printf("%s: strange port\n", 2587 device_xname(sc->sc_dev)); 2588 else 2589 printf("%s: handing over %s speed device on " 2590 "port %d to %s\n", 2591 device_xname(sc->sc_dev), 2592 lowspeed ? "low" : "full", 2593 index, device_xname(sc->sc_comps[i])); 2594 } else { 2595 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2596 } 2597 #endif 2598 port = EHCI_PORTSC(index); 2599 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2600 EOWRITE4(sc, port, v | EHCI_PS_PO); 2601 } 2602 2603 Static usbd_status 2604 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2605 { 2606 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2607 usbd_status err; 2608 2609 /* Insert last in queue. */ 2610 mutex_enter(&sc->sc_lock); 2611 err = usb_insert_transfer(xfer); 2612 mutex_exit(&sc->sc_lock); 2613 if (err) 2614 return err; 2615 2616 /* Pipe isn't running, start first */ 2617 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2618 } 2619 2620 Static usbd_status 2621 ehci_root_intr_start(struct usbd_xfer *xfer) 2622 { 2623 struct usbd_pipe *pipe = xfer->ux_pipe; 2624 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2625 2626 if (sc->sc_dying) 2627 return USBD_IOERROR; 2628 2629 mutex_enter(&sc->sc_lock); 2630 sc->sc_intrxfer = xfer; 2631 mutex_exit(&sc->sc_lock); 2632 2633 return USBD_IN_PROGRESS; 2634 } 2635 2636 /* Abort a root interrupt request. */ 2637 Static void 2638 ehci_root_intr_abort(struct usbd_xfer *xfer) 2639 { 2640 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2641 2642 KASSERT(mutex_owned(&sc->sc_lock)); 2643 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2644 2645 sc->sc_intrxfer = NULL; 2646 2647 xfer->ux_status = USBD_CANCELLED; 2648 usb_transfer_complete(xfer); 2649 } 2650 2651 /* Close the root pipe. */ 2652 Static void 2653 ehci_root_intr_close(struct usbd_pipe *pipe) 2654 { 2655 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2656 2657 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2658 2659 KASSERT(mutex_owned(&sc->sc_lock)); 2660 2661 sc->sc_intrxfer = NULL; 2662 } 2663 2664 Static void 2665 ehci_root_intr_done(struct usbd_xfer *xfer) 2666 { 2667 xfer->ux_hcpriv = NULL; 2668 } 2669 2670 /************************/ 2671 2672 Static ehci_soft_qh_t * 2673 ehci_alloc_sqh(ehci_softc_t *sc) 2674 { 2675 ehci_soft_qh_t *sqh; 2676 usbd_status err; 2677 int i, offs; 2678 usb_dma_t dma; 2679 2680 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2681 2682 if (sc->sc_freeqhs == NULL) { 2683 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2684 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2685 EHCI_PAGE_SIZE, &dma); 2686 #ifdef EHCI_DEBUG 2687 if (err) 2688 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2689 #endif 2690 if (err) 2691 return NULL; 2692 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2693 offs = i * EHCI_SQH_SIZE; 2694 sqh = KERNADDR(&dma, offs); 2695 sqh->physaddr = DMAADDR(&dma, offs); 2696 sqh->dma = dma; 2697 sqh->offs = offs; 2698 sqh->next = sc->sc_freeqhs; 2699 sc->sc_freeqhs = sqh; 2700 } 2701 } 2702 sqh = sc->sc_freeqhs; 2703 sc->sc_freeqhs = sqh->next; 2704 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2705 sqh->next = NULL; 2706 return sqh; 2707 } 2708 2709 Static void 2710 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2711 { 2712 sqh->next = sc->sc_freeqhs; 2713 sc->sc_freeqhs = sqh; 2714 } 2715 2716 Static ehci_soft_qtd_t * 2717 ehci_alloc_sqtd(ehci_softc_t *sc) 2718 { 2719 ehci_soft_qtd_t *sqtd = NULL; 2720 usbd_status err; 2721 int i, offs; 2722 usb_dma_t dma; 2723 2724 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2725 2726 if (sc->sc_freeqtds == NULL) { 2727 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2728 2729 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2730 EHCI_PAGE_SIZE, &dma); 2731 #ifdef EHCI_DEBUG 2732 if (err) 2733 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2734 #endif 2735 if (err) 2736 goto done; 2737 2738 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2739 offs = i * EHCI_SQTD_SIZE; 2740 sqtd = KERNADDR(&dma, offs); 2741 sqtd->physaddr = DMAADDR(&dma, offs); 2742 sqtd->dma = dma; 2743 sqtd->offs = offs; 2744 2745 sqtd->nextqtd = sc->sc_freeqtds; 2746 sc->sc_freeqtds = sqtd; 2747 } 2748 } 2749 2750 sqtd = sc->sc_freeqtds; 2751 sc->sc_freeqtds = sqtd->nextqtd; 2752 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2753 sqtd->nextqtd = NULL; 2754 sqtd->xfer = NULL; 2755 2756 done: 2757 return sqtd; 2758 } 2759 2760 Static void 2761 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2762 { 2763 2764 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2765 2766 sqtd->nextqtd = sc->sc_freeqtds; 2767 sc->sc_freeqtds = sqtd; 2768 } 2769 2770 Static usbd_status 2771 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2772 int alen, int rd, struct usbd_xfer *xfer, 2773 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2774 { 2775 ehci_soft_qtd_t *next, *cur; 2776 ehci_physaddr_t nextphys; 2777 uint32_t qtdstatus; 2778 int len, curlen, mps; 2779 int i, tog; 2780 int pages, pageoffs; 2781 size_t curoffs; 2782 vaddr_t va, va_offs; 2783 usb_dma_t *dma = &xfer->ux_dmabuf; 2784 uint16_t flags = xfer->ux_flags; 2785 paddr_t a; 2786 2787 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2788 2789 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2790 2791 len = alen; 2792 qtdstatus = EHCI_QTD_ACTIVE | 2793 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2794 EHCI_QTD_SET_CERR(3) 2795 /* IOC set below */ 2796 /* BYTES set below */ 2797 ; 2798 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2799 tog = epipe->nexttoggle; 2800 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2801 2802 cur = ehci_alloc_sqtd(sc); 2803 *sp = cur; 2804 if (cur == NULL) 2805 goto nomem; 2806 2807 usb_syncmem(dma, 0, alen, 2808 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2809 curoffs = 0; 2810 for (;;) { 2811 /* The EHCI hardware can handle at most 5 pages. */ 2812 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2813 va_offs = EHCI_PAGE_OFFSET(va_offs); 2814 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2815 /* we can handle it in this QTD */ 2816 curlen = len - curoffs; 2817 } else { 2818 /* must use multiple TDs, fill as much as possible. */ 2819 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2820 2821 /* the length must be a multiple of the max size */ 2822 curlen -= curlen % mps; 2823 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2824 "curlen=%d", curlen, 0, 0, 0); 2825 KASSERT(curlen != 0); 2826 } 2827 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2828 len, curlen, curoffs, 0); 2829 2830 /* 2831 * Allocate another transfer if there's more data left, 2832 * or if force last short transfer flag is set and we're 2833 * allocating a multiple of the max packet size. 2834 */ 2835 2836 if (curoffs + curlen != len || 2837 ((curlen % mps) == 0 && !rd && curlen != 0 && 2838 (flags & USBD_FORCE_SHORT_XFER))) { 2839 next = ehci_alloc_sqtd(sc); 2840 if (next == NULL) 2841 goto nomem; 2842 nextphys = htole32(next->physaddr); 2843 } else { 2844 next = NULL; 2845 nextphys = EHCI_NULL; 2846 } 2847 2848 /* Find number of pages we'll be using, insert dma addresses */ 2849 pages = EHCI_NPAGES(curlen); 2850 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2851 pageoffs = EHCI_PAGE(curoffs); 2852 for (i = 0; i < pages; i++) { 2853 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2854 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2855 /* Cast up to avoid compiler warnings */ 2856 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2857 } 2858 2859 /* First buffer pointer requires a page offset to start at */ 2860 va = (vaddr_t)KERNADDR(dma, curoffs); 2861 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2862 2863 cur->nextqtd = next; 2864 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2865 cur->qtd.qtd_status = 2866 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2867 cur->xfer = xfer; 2868 cur->len = curlen; 2869 2870 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2871 curoffs, curoffs + curlen, 0, 0); 2872 2873 /* 2874 * adjust the toggle based on the number of packets in this 2875 * qtd 2876 */ 2877 if (((curlen + mps - 1) / mps) & 1) { 2878 tog ^= 1; 2879 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2880 } 2881 if (next == NULL) 2882 break; 2883 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2885 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2886 if (len) 2887 curoffs += curlen; 2888 cur = next; 2889 } 2890 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2891 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2893 *ep = cur; 2894 epipe->nexttoggle = tog; 2895 2896 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2897 *sp, *ep, 0, 0); 2898 2899 return USBD_NORMAL_COMPLETION; 2900 2901 nomem: 2902 /* XXX free chain */ 2903 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2904 return USBD_NOMEM; 2905 } 2906 2907 Static void 2908 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2909 ehci_soft_qtd_t *sqtdend) 2910 { 2911 ehci_soft_qtd_t *p; 2912 int i; 2913 2914 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2915 2916 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2917 sqtd, sqtdend, 0, 0); 2918 2919 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2920 p = sqtd->nextqtd; 2921 ehci_free_sqtd(sc, sqtd); 2922 } 2923 } 2924 2925 Static ehci_soft_itd_t * 2926 ehci_alloc_itd(ehci_softc_t *sc) 2927 { 2928 struct ehci_soft_itd *itd, *freeitd; 2929 usbd_status err; 2930 int i, offs, frindex, previndex; 2931 usb_dma_t dma; 2932 2933 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2934 2935 mutex_enter(&sc->sc_lock); 2936 2937 /* 2938 * Find an itd that wasn't freed this frame or last frame. This can 2939 * discard itds that were freed before frindex wrapped around 2940 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2941 * interrupt and fiddling with list when that happens 2942 */ 2943 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2944 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2945 2946 freeitd = NULL; 2947 LIST_FOREACH(itd, &sc->sc_freeitds, free_list) { 2948 if (itd == NULL) 2949 break; 2950 if (itd->slot != frindex && itd->slot != previndex) { 2951 freeitd = itd; 2952 break; 2953 } 2954 } 2955 2956 if (freeitd == NULL) { 2957 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2958 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2959 EHCI_PAGE_SIZE, &dma); 2960 2961 if (err) { 2962 USBHIST_LOG(ehcidebug, 2963 "alloc returned %d", err, 0, 0, 0); 2964 mutex_exit(&sc->sc_lock); 2965 return NULL; 2966 } 2967 2968 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2969 offs = i * EHCI_ITD_SIZE; 2970 itd = KERNADDR(&dma, offs); 2971 itd->physaddr = DMAADDR(&dma, offs); 2972 itd->dma = dma; 2973 itd->offs = offs; 2974 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 2975 } 2976 freeitd = LIST_FIRST(&sc->sc_freeitds); 2977 } 2978 2979 itd = freeitd; 2980 LIST_REMOVE(itd, free_list); 2981 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2982 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2983 sizeof(itd->itd.itd_next), 2984 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2985 2986 itd->frame_list.next = NULL; 2987 itd->frame_list.prev = NULL; 2988 itd->xfer_next = NULL; 2989 itd->slot = 0; 2990 2991 mutex_exit(&sc->sc_lock); 2992 2993 return itd; 2994 } 2995 2996 Static ehci_soft_sitd_t * 2997 ehci_alloc_sitd(ehci_softc_t *sc) 2998 { 2999 struct ehci_soft_sitd *sitd, *freesitd; 3000 usbd_status err; 3001 int i, offs, frindex, previndex; 3002 usb_dma_t dma; 3003 3004 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3005 3006 mutex_enter(&sc->sc_lock); 3007 3008 /* 3009 * Find an sitd that wasn't freed this frame or last frame. This can 3010 * discard sitds that were freed before frindex wrapped around 3011 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3012 * interrupt and fiddling with list when that happens 3013 */ 3014 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3015 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3016 3017 freesitd = NULL; 3018 LIST_FOREACH(sitd, &sc->sc_freesitds, free_list) { 3019 if (sitd == NULL) 3020 break; 3021 if (sitd->slot != frindex && sitd->slot != previndex) { 3022 freesitd = sitd; 3023 break; 3024 } 3025 } 3026 3027 if (freesitd == NULL) { 3028 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3029 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3030 EHCI_PAGE_SIZE, &dma); 3031 3032 if (err) { 3033 USBHIST_LOG(ehcidebug, 3034 "alloc returned %d", err, 0, 0, 0); 3035 mutex_exit(&sc->sc_lock); 3036 return NULL; 3037 } 3038 3039 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3040 offs = i * EHCI_SITD_SIZE; 3041 sitd = KERNADDR(&dma, offs); 3042 sitd->physaddr = DMAADDR(&dma, offs); 3043 sitd->dma = dma; 3044 sitd->offs = offs; 3045 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3046 } 3047 freesitd = LIST_FIRST(&sc->sc_freesitds); 3048 } 3049 3050 sitd = freesitd; 3051 LIST_REMOVE(sitd, free_list); 3052 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3053 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3054 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3055 BUS_DMASYNC_PREREAD); 3056 3057 sitd->frame_list.next = NULL; 3058 sitd->frame_list.prev = NULL; 3059 sitd->xfer_next = NULL; 3060 sitd->slot = 0; 3061 3062 mutex_exit(&sc->sc_lock); 3063 3064 return sitd; 3065 } 3066 3067 Static void 3068 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3069 { 3070 3071 KASSERT(mutex_owned(&sc->sc_lock)); 3072 3073 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3074 } 3075 3076 Static void 3077 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3078 { 3079 3080 KASSERT(mutex_owned(&sc->sc_lock)); 3081 3082 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3083 } 3084 3085 /****************/ 3086 3087 /* 3088 * Close a reqular pipe. 3089 * Assumes that there are no pending transactions. 3090 */ 3091 Static void 3092 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3093 { 3094 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3095 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3096 ehci_soft_qh_t *sqh = epipe->sqh; 3097 3098 KASSERT(mutex_owned(&sc->sc_lock)); 3099 3100 ehci_rem_qh(sc, sqh, head); 3101 ehci_free_sqh(sc, epipe->sqh); 3102 } 3103 3104 /* 3105 * Abort a device request. 3106 * If this routine is called at splusb() it guarantees that the request 3107 * will be removed from the hardware scheduling and that the callback 3108 * for it will be called with USBD_CANCELLED status. 3109 * It's impossible to guarantee that the requested transfer will not 3110 * have happened since the hardware runs concurrently. 3111 * If the transaction has already happened we rely on the ordinary 3112 * interrupt processing to process it. 3113 * XXX This is most probably wrong. 3114 * XXXMRG this doesn't make sense anymore. 3115 */ 3116 Static void 3117 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3118 { 3119 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3120 struct ehci_xfer *exfer = EXFER(xfer); 3121 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3122 ehci_soft_qh_t *sqh = epipe->sqh; 3123 ehci_soft_qtd_t *sqtd; 3124 ehci_physaddr_t cur; 3125 uint32_t qhstatus; 3126 int hit; 3127 int wake; 3128 3129 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3130 3131 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3132 3133 KASSERT(mutex_owned(&sc->sc_lock)); 3134 ASSERT_SLEEPABLE(); 3135 3136 if (sc->sc_dying) { 3137 /* If we're dying, just do the software part. */ 3138 xfer->ux_status = status; /* make software ignore it */ 3139 callout_stop(&xfer->ux_callout); 3140 usb_transfer_complete(xfer); 3141 return; 3142 } 3143 3144 /* 3145 * If an abort is already in progress then just wait for it to 3146 * complete and return. 3147 */ 3148 if (xfer->ux_hcflags & UXFER_ABORTING) { 3149 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3150 #ifdef DIAGNOSTIC 3151 if (status == USBD_TIMEOUT) 3152 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3153 #endif 3154 /* Override the status which might be USBD_TIMEOUT. */ 3155 xfer->ux_status = status; 3156 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3157 0, 0, 0, 0); 3158 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3159 while (xfer->ux_hcflags & UXFER_ABORTING) 3160 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3161 return; 3162 } 3163 xfer->ux_hcflags |= UXFER_ABORTING; 3164 3165 /* 3166 * Step 1: Make interrupt routine and hardware ignore xfer. 3167 */ 3168 xfer->ux_status = status; /* make software ignore it */ 3169 callout_stop(&xfer->ux_callout); 3170 3171 usb_syncmem(&sqh->dma, 3172 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3173 sizeof(sqh->qh.qh_qtd.qtd_status), 3174 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3175 qhstatus = sqh->qh.qh_qtd.qtd_status; 3176 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3177 usb_syncmem(&sqh->dma, 3178 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3179 sizeof(sqh->qh.qh_qtd.qtd_status), 3180 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3181 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3182 usb_syncmem(&sqtd->dma, 3183 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3184 sizeof(sqtd->qtd.qtd_status), 3185 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3186 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3187 usb_syncmem(&sqtd->dma, 3188 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3189 sizeof(sqtd->qtd.qtd_status), 3190 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3191 if (sqtd == exfer->ex_sqtdend) 3192 break; 3193 } 3194 3195 /* 3196 * Step 2: Wait until we know hardware has finished any possible 3197 * use of the xfer. Also make sure the soft interrupt routine 3198 * has run. 3199 */ 3200 ehci_sync_hc(sc); 3201 sc->sc_softwake = 1; 3202 usb_schedsoftintr(&sc->sc_bus); 3203 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3204 3205 /* 3206 * Step 3: Remove any vestiges of the xfer from the hardware. 3207 * The complication here is that the hardware may have executed 3208 * beyond the xfer we're trying to abort. So as we're scanning 3209 * the TDs of this xfer we check if the hardware points to 3210 * any of them. 3211 */ 3212 3213 usb_syncmem(&sqh->dma, 3214 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3215 sizeof(sqh->qh.qh_curqtd), 3216 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3217 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3218 hit = 0; 3219 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3220 hit |= cur == sqtd->physaddr; 3221 if (sqtd == exfer->ex_sqtdend) 3222 break; 3223 } 3224 sqtd = sqtd->nextqtd; 3225 /* Zap curqtd register if hardware pointed inside the xfer. */ 3226 if (hit && sqtd != NULL) { 3227 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3228 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3229 usb_syncmem(&sqh->dma, 3230 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3231 sizeof(sqh->qh.qh_curqtd), 3232 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3233 sqh->qh.qh_qtd.qtd_status = qhstatus; 3234 usb_syncmem(&sqh->dma, 3235 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3236 sizeof(sqh->qh.qh_qtd.qtd_status), 3237 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3238 } else { 3239 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3240 usb_syncmem(&sqh->dma, 3241 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3242 sizeof(sqh->qh.qh_curqtd), 3243 BUS_DMASYNC_PREREAD); 3244 } 3245 3246 /* 3247 * Step 4: Execute callback. 3248 */ 3249 #ifdef DIAGNOSTIC 3250 exfer->ex_isdone = true; 3251 #endif 3252 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3253 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3254 usb_transfer_complete(xfer); 3255 if (wake) { 3256 cv_broadcast(&xfer->ux_hccv); 3257 } 3258 3259 KASSERT(mutex_owned(&sc->sc_lock)); 3260 } 3261 3262 Static void 3263 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3264 { 3265 ehci_isoc_trans_t trans_status; 3266 struct ehci_pipe *epipe; 3267 struct ehci_xfer *exfer; 3268 ehci_softc_t *sc; 3269 struct ehci_soft_itd *itd; 3270 struct ehci_soft_sitd *sitd; 3271 int i, wake; 3272 3273 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3274 3275 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3276 exfer = EXFER(xfer); 3277 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3278 3279 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3280 3281 KASSERT(mutex_owned(&sc->sc_lock)); 3282 3283 if (sc->sc_dying) { 3284 xfer->ux_status = status; 3285 callout_stop(&xfer->ux_callout); 3286 usb_transfer_complete(xfer); 3287 return; 3288 } 3289 3290 if (xfer->ux_hcflags & UXFER_ABORTING) { 3291 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3292 3293 #ifdef DIAGNOSTIC 3294 if (status == USBD_TIMEOUT) 3295 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3296 #endif 3297 3298 xfer->ux_status = status; 3299 USBHIST_LOG(ehcidebug, 3300 "waiting for abort to finish", 0, 0, 0, 0); 3301 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3302 while (xfer->ux_hcflags & UXFER_ABORTING) 3303 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3304 goto done; 3305 } 3306 xfer->ux_hcflags |= UXFER_ABORTING; 3307 3308 xfer->ux_status = status; 3309 callout_stop(&xfer->ux_callout); 3310 3311 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3312 for (itd = exfer->ex_itdstart; itd != NULL; 3313 itd = itd->xfer_next) { 3314 usb_syncmem(&itd->dma, 3315 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3316 sizeof(itd->itd.itd_ctl), 3317 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3318 3319 for (i = 0; i < 8; i++) { 3320 trans_status = le32toh(itd->itd.itd_ctl[i]); 3321 trans_status &= ~EHCI_ITD_ACTIVE; 3322 itd->itd.itd_ctl[i] = htole32(trans_status); 3323 } 3324 3325 usb_syncmem(&itd->dma, 3326 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3327 sizeof(itd->itd.itd_ctl), 3328 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3329 } 3330 } else { 3331 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3332 sitd = sitd->xfer_next) { 3333 usb_syncmem(&sitd->dma, 3334 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3335 sizeof(sitd->sitd.sitd_buffer), 3336 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3337 3338 trans_status = le32toh(sitd->sitd.sitd_trans); 3339 trans_status &= ~EHCI_SITD_ACTIVE; 3340 sitd->sitd.sitd_trans = htole32(trans_status); 3341 3342 usb_syncmem(&sitd->dma, 3343 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3344 sizeof(sitd->sitd.sitd_buffer), 3345 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3346 } 3347 } 3348 3349 sc->sc_softwake = 1; 3350 usb_schedsoftintr(&sc->sc_bus); 3351 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3352 3353 #ifdef DIAGNOSTIC 3354 exfer->ex_isdone = true; 3355 #endif 3356 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3357 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3358 usb_transfer_complete(xfer); 3359 if (wake) { 3360 cv_broadcast(&xfer->ux_hccv); 3361 } 3362 3363 done: 3364 KASSERT(mutex_owned(&sc->sc_lock)); 3365 return; 3366 } 3367 3368 Static void 3369 ehci_timeout(void *addr) 3370 { 3371 struct ehci_xfer *exfer = addr; 3372 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3373 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3374 3375 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3376 3377 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3378 #ifdef EHCI_DEBUG 3379 if (ehcidebug > 1) 3380 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3381 #endif 3382 3383 if (sc->sc_dying) { 3384 mutex_enter(&sc->sc_lock); 3385 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3386 mutex_exit(&sc->sc_lock); 3387 return; 3388 } 3389 3390 /* Execute the abort in a process context. */ 3391 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3392 USB_TASKQ_MPSAFE); 3393 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3394 USB_TASKQ_HC); 3395 } 3396 3397 Static void 3398 ehci_timeout_task(void *addr) 3399 { 3400 struct usbd_xfer *xfer = addr; 3401 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3402 3403 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3404 3405 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3406 3407 mutex_enter(&sc->sc_lock); 3408 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3409 mutex_exit(&sc->sc_lock); 3410 } 3411 3412 /************************/ 3413 3414 Static usbd_status 3415 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3416 { 3417 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3418 usbd_status err; 3419 3420 /* Insert last in queue. */ 3421 mutex_enter(&sc->sc_lock); 3422 err = usb_insert_transfer(xfer); 3423 mutex_exit(&sc->sc_lock); 3424 if (err) 3425 return err; 3426 3427 /* Pipe isn't running, start first */ 3428 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3429 } 3430 3431 Static usbd_status 3432 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3433 { 3434 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3435 usbd_status err; 3436 3437 if (sc->sc_dying) 3438 return USBD_IOERROR; 3439 3440 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3441 3442 err = ehci_device_request(xfer); 3443 if (err) { 3444 return err; 3445 } 3446 3447 if (sc->sc_bus.ub_usepolling) 3448 ehci_waitintr(sc, xfer); 3449 3450 return USBD_IN_PROGRESS; 3451 } 3452 3453 Static void 3454 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3455 { 3456 struct ehci_xfer *ex = EXFER(xfer); 3457 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3458 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3459 usb_device_request_t *req = &xfer->ux_request; 3460 int len = UGETW(req->wLength); 3461 int rd = req->bmRequestType & UT_READ; 3462 3463 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3464 3465 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3466 3467 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3468 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3469 3470 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3471 ehci_del_intr_list(sc, ex); /* remove from active list */ 3472 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3473 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3474 BUS_DMASYNC_POSTWRITE); 3475 if (len) 3476 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3477 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3478 } 3479 3480 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3481 } 3482 3483 /* Abort a device control request. */ 3484 Static void 3485 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3486 { 3487 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3488 3489 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3490 ehci_abort_xfer(xfer, USBD_CANCELLED); 3491 } 3492 3493 /* Close a device control pipe. */ 3494 Static void 3495 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3496 { 3497 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3498 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3499 3500 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3501 3502 KASSERT(mutex_owned(&sc->sc_lock)); 3503 3504 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3505 3506 ehci_close_pipe(pipe, sc->sc_async_head); 3507 } 3508 3509 Static usbd_status 3510 ehci_device_request(struct usbd_xfer *xfer) 3511 { 3512 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3513 struct ehci_xfer *exfer = EXFER(xfer); 3514 usb_device_request_t *req = &xfer->ux_request; 3515 struct usbd_device *dev = epipe->pipe.up_dev; 3516 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3517 ehci_soft_qtd_t *setup, *stat, *next; 3518 ehci_soft_qh_t *sqh; 3519 int isread; 3520 int len; 3521 usbd_status err; 3522 3523 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3524 3525 isread = req->bmRequestType & UT_READ; 3526 len = UGETW(req->wLength); 3527 3528 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3529 "wValue=0x%04x, wIndex=0x%04x", 3530 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3531 UGETW(req->wIndex)); 3532 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3533 len, dev->ud_addr, 3534 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3535 3536 setup = ehci_alloc_sqtd(sc); 3537 if (setup == NULL) { 3538 err = USBD_NOMEM; 3539 goto bad1; 3540 } 3541 stat = ehci_alloc_sqtd(sc); 3542 if (stat == NULL) { 3543 err = USBD_NOMEM; 3544 goto bad2; 3545 } 3546 3547 mutex_enter(&sc->sc_lock); 3548 3549 sqh = epipe->sqh; 3550 3551 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3552 "address QH %" __PRIuBIT " pipe %d\n", 3553 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3554 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3555 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3556 "MPS QH %" __PRIuBIT " pipe %d\n", 3557 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3558 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3559 3560 /* Set up data transaction */ 3561 if (len != 0) { 3562 ehci_soft_qtd_t *end; 3563 3564 /* Start toggle at 1. */ 3565 epipe->nexttoggle = 1; 3566 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3567 &next, &end); 3568 if (err) 3569 goto bad3; 3570 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3571 end->nextqtd = stat; 3572 end->qtd.qtd_next = end->qtd.qtd_altnext = 3573 htole32(stat->physaddr); 3574 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3575 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3576 } else { 3577 next = stat; 3578 } 3579 3580 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3581 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3582 3583 /* Clear toggle */ 3584 setup->qtd.qtd_status = htole32( 3585 EHCI_QTD_ACTIVE | 3586 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3587 EHCI_QTD_SET_CERR(3) | 3588 EHCI_QTD_SET_TOGGLE(0) | 3589 EHCI_QTD_SET_BYTES(sizeof(*req)) 3590 ); 3591 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3592 setup->qtd.qtd_buffer_hi[0] = 0; 3593 setup->nextqtd = next; 3594 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3595 setup->xfer = xfer; 3596 setup->len = sizeof(*req); 3597 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3598 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3599 3600 stat->qtd.qtd_status = htole32( 3601 EHCI_QTD_ACTIVE | 3602 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3603 EHCI_QTD_SET_CERR(3) | 3604 EHCI_QTD_SET_TOGGLE(1) | 3605 EHCI_QTD_IOC 3606 ); 3607 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3608 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3609 stat->nextqtd = NULL; 3610 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3611 stat->xfer = xfer; 3612 stat->len = 0; 3613 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3614 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3615 3616 #ifdef EHCI_DEBUG 3617 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3618 ehci_dump_sqh(sqh); 3619 ehci_dump_sqtds(setup); 3620 #endif 3621 3622 exfer->ex_sqtdstart = setup; 3623 exfer->ex_sqtdend = stat; 3624 KASSERT(exfer->ex_isdone); 3625 #ifdef DIAGNOSTIC 3626 exfer->ex_isdone = false; 3627 #endif 3628 3629 /* Insert qTD in QH list. */ 3630 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3631 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3632 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3633 ehci_timeout, xfer); 3634 } 3635 ehci_add_intr_list(sc, exfer); 3636 xfer->ux_status = USBD_IN_PROGRESS; 3637 mutex_exit(&sc->sc_lock); 3638 3639 #ifdef EHCI_DEBUG 3640 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3641 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3642 // delay(10000); 3643 ehci_dump_regs(sc); 3644 ehci_dump_sqh(sc->sc_async_head); 3645 ehci_dump_sqh(sqh); 3646 ehci_dump_sqtds(setup); 3647 #endif 3648 3649 return USBD_NORMAL_COMPLETION; 3650 3651 bad3: 3652 mutex_exit(&sc->sc_lock); 3653 ehci_free_sqtd(sc, stat); 3654 bad2: 3655 ehci_free_sqtd(sc, setup); 3656 bad1: 3657 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3658 mutex_enter(&sc->sc_lock); 3659 xfer->ux_status = err; 3660 usb_transfer_complete(xfer); 3661 mutex_exit(&sc->sc_lock); 3662 return err; 3663 } 3664 3665 /* 3666 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3667 * qTD status, or miss signalling occasionally under heavy load. If the host 3668 * machine is too fast, we we can miss transaction completion - when we scan 3669 * the active list the transaction still seems to be active. This generally 3670 * exhibits itself as a umass stall that never recovers. 3671 * 3672 * We work around this behaviour by setting up this callback after any softintr 3673 * that completes with transactions still pending, giving us another chance to 3674 * check for completion after the writeback has taken place. 3675 */ 3676 Static void 3677 ehci_intrlist_timeout(void *arg) 3678 { 3679 ehci_softc_t *sc = arg; 3680 3681 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3682 3683 usb_schedsoftintr(&sc->sc_bus); 3684 } 3685 3686 /************************/ 3687 3688 Static usbd_status 3689 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3690 { 3691 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3692 usbd_status err; 3693 3694 /* Insert last in queue. */ 3695 mutex_enter(&sc->sc_lock); 3696 err = usb_insert_transfer(xfer); 3697 mutex_exit(&sc->sc_lock); 3698 if (err) 3699 return err; 3700 3701 /* Pipe isn't running, start first */ 3702 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3703 } 3704 3705 Static usbd_status 3706 ehci_device_bulk_start(struct usbd_xfer *xfer) 3707 { 3708 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3709 struct ehci_xfer *exfer = EXFER(xfer); 3710 struct usbd_device *dev = epipe->pipe.up_dev; 3711 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3712 ehci_soft_qtd_t *data, *dataend; 3713 ehci_soft_qh_t *sqh; 3714 usbd_status err; 3715 int len, isread, endpt; 3716 3717 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3718 3719 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3720 xfer, xfer->ux_length, xfer->ux_flags, 0); 3721 3722 if (sc->sc_dying) 3723 return USBD_IOERROR; 3724 3725 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3726 3727 mutex_enter(&sc->sc_lock); 3728 3729 len = xfer->ux_length; 3730 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3731 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3732 sqh = epipe->sqh; 3733 3734 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3735 &dataend); 3736 if (err) { 3737 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3738 xfer->ux_status = err; 3739 usb_transfer_complete(xfer); 3740 mutex_exit(&sc->sc_lock); 3741 return err; 3742 } 3743 3744 #ifdef EHCI_DEBUG 3745 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3746 ehci_dump_sqh(sqh); 3747 ehci_dump_sqtds(data); 3748 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3749 #endif 3750 3751 /* Set up interrupt info. */ 3752 exfer->ex_sqtdstart = data; 3753 exfer->ex_sqtdend = dataend; 3754 KASSERT(exfer->ex_isdone); 3755 #ifdef DIAGNOSTIC 3756 exfer->ex_isdone = false; 3757 #endif 3758 3759 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3760 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3761 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3762 ehci_timeout, xfer); 3763 } 3764 ehci_add_intr_list(sc, exfer); 3765 xfer->ux_status = USBD_IN_PROGRESS; 3766 mutex_exit(&sc->sc_lock); 3767 3768 #ifdef EHCI_DEBUG 3769 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3770 // delay(10000); 3771 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3772 ehci_dump_regs(sc); 3773 #if 0 3774 printf("async_head:\n"); 3775 ehci_dump_sqh(sc->sc_async_head); 3776 #endif 3777 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3778 ehci_dump_sqh(sqh); 3779 ehci_dump_sqtds(data); 3780 #endif 3781 3782 if (sc->sc_bus.ub_usepolling) 3783 ehci_waitintr(sc, xfer); 3784 3785 return USBD_IN_PROGRESS; 3786 } 3787 3788 Static void 3789 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3790 { 3791 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3792 3793 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3794 ehci_abort_xfer(xfer, USBD_CANCELLED); 3795 } 3796 3797 /* 3798 * Close a device bulk pipe. 3799 */ 3800 Static void 3801 ehci_device_bulk_close(struct usbd_pipe *pipe) 3802 { 3803 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3804 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3805 3806 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3807 3808 KASSERT(mutex_owned(&sc->sc_lock)); 3809 3810 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3811 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3812 ehci_close_pipe(pipe, sc->sc_async_head); 3813 } 3814 3815 Static void 3816 ehci_device_bulk_done(struct usbd_xfer *xfer) 3817 { 3818 struct ehci_xfer *ex = EXFER(xfer); 3819 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3820 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3821 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3822 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3823 3824 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3825 3826 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3827 xfer, xfer->ux_actlen, 0, 0); 3828 3829 KASSERT(mutex_owned(&sc->sc_lock)); 3830 3831 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3832 ehci_del_intr_list(sc, ex); /* remove from active list */ 3833 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3834 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3835 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3836 } 3837 3838 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3839 } 3840 3841 /************************/ 3842 3843 Static usbd_status 3844 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3845 { 3846 struct ehci_soft_islot *isp; 3847 int islot, lev; 3848 3849 /* Find a poll rate that is large enough. */ 3850 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3851 if (EHCI_ILEV_IVAL(lev) <= ival) 3852 break; 3853 3854 /* Pick an interrupt slot at the right level. */ 3855 /* XXX could do better than picking at random */ 3856 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3857 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3858 3859 sqh->islot = islot; 3860 isp = &sc->sc_islots[islot]; 3861 mutex_enter(&sc->sc_lock); 3862 ehci_add_qh(sc, sqh, isp->sqh); 3863 mutex_exit(&sc->sc_lock); 3864 3865 return USBD_NORMAL_COMPLETION; 3866 } 3867 3868 Static usbd_status 3869 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3870 { 3871 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3872 usbd_status err; 3873 3874 /* Insert last in queue. */ 3875 mutex_enter(&sc->sc_lock); 3876 err = usb_insert_transfer(xfer); 3877 mutex_exit(&sc->sc_lock); 3878 if (err) 3879 return err; 3880 3881 /* 3882 * Pipe isn't running (otherwise err would be USBD_INPROG), 3883 * so start it first. 3884 */ 3885 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3886 } 3887 3888 Static usbd_status 3889 ehci_device_intr_start(struct usbd_xfer *xfer) 3890 { 3891 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3892 struct ehci_xfer *exfer = EXFER(xfer); 3893 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3894 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3895 ehci_soft_qtd_t *data, *dataend; 3896 ehci_soft_qh_t *sqh; 3897 usbd_status err; 3898 int len, isread, endpt; 3899 3900 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3901 3902 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3903 xfer, xfer->ux_length, xfer->ux_flags, 0); 3904 3905 if (sc->sc_dying) 3906 return USBD_IOERROR; 3907 3908 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3909 3910 mutex_enter(&sc->sc_lock); 3911 3912 len = xfer->ux_length; 3913 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3914 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3915 sqh = epipe->sqh; 3916 3917 epipe->intr.length = len; 3918 3919 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3920 &dataend); 3921 if (err) { 3922 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3923 xfer->ux_status = err; 3924 usb_transfer_complete(xfer); 3925 mutex_exit(&sc->sc_lock); 3926 return err; 3927 } 3928 3929 #ifdef EHCI_DEBUG 3930 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3931 ehci_dump_sqh(sqh); 3932 ehci_dump_sqtds(data); 3933 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3934 #endif 3935 3936 /* Set up interrupt info. */ 3937 exfer->ex_sqtdstart = data; 3938 exfer->ex_sqtdend = dataend; 3939 KASSERT(exfer->ex_isdone); 3940 #ifdef DIAGNOSTIC 3941 exfer->ex_isdone = false; 3942 #endif 3943 3944 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3945 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3946 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3947 ehci_timeout, xfer); 3948 } 3949 ehci_add_intr_list(sc, exfer); 3950 xfer->ux_status = USBD_IN_PROGRESS; 3951 mutex_exit(&sc->sc_lock); 3952 3953 #ifdef EHCI_DEBUG 3954 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3955 // delay(10000); 3956 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3957 ehci_dump_regs(sc); 3958 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3959 ehci_dump_sqh(sqh); 3960 ehci_dump_sqtds(data); 3961 #endif 3962 3963 if (sc->sc_bus.ub_usepolling) 3964 ehci_waitintr(sc, xfer); 3965 3966 return USBD_IN_PROGRESS; 3967 } 3968 3969 Static void 3970 ehci_device_intr_abort(struct usbd_xfer *xfer) 3971 { 3972 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3973 3974 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3975 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3976 3977 /* 3978 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3979 * async doorbell. That's dependent on the async list, wheras 3980 * intr xfers are periodic, should not use this? 3981 */ 3982 ehci_abort_xfer(xfer, USBD_CANCELLED); 3983 } 3984 3985 Static void 3986 ehci_device_intr_close(struct usbd_pipe *pipe) 3987 { 3988 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3989 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3990 struct ehci_soft_islot *isp; 3991 3992 KASSERT(mutex_owned(&sc->sc_lock)); 3993 3994 isp = &sc->sc_islots[epipe->sqh->islot]; 3995 ehci_close_pipe(pipe, isp->sqh); 3996 } 3997 3998 Static void 3999 ehci_device_intr_done(struct usbd_xfer *xfer) 4000 { 4001 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4002 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4003 struct ehci_xfer *exfer = EXFER(xfer); 4004 ehci_soft_qtd_t *data, *dataend; 4005 ehci_soft_qh_t *sqh; 4006 usbd_status err; 4007 int len, isread, endpt; 4008 4009 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4010 4011 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4012 xfer, xfer->ux_actlen, 0, 0); 4013 4014 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4015 4016 if (xfer->ux_pipe->up_repeat) { 4017 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4018 4019 len = epipe->intr.length; 4020 xfer->ux_length = len; 4021 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4022 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4023 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4024 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4025 sqh = epipe->sqh; 4026 4027 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4028 &data, &dataend); 4029 if (err) { 4030 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4031 xfer->ux_status = err; 4032 return; 4033 } 4034 4035 /* Set up interrupt info. */ 4036 exfer->ex_sqtdstart = data; 4037 exfer->ex_sqtdend = dataend; 4038 KASSERT(exfer->ex_isdone); 4039 #ifdef DIAGNOSTIC 4040 exfer->ex_isdone = false; 4041 #endif 4042 4043 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4044 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4045 callout_reset(&xfer->ux_callout, 4046 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4047 } 4048 4049 xfer->ux_status = USBD_IN_PROGRESS; 4050 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4051 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4052 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4053 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4054 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4055 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4056 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4057 } 4058 } 4059 4060 /************************/ 4061 4062 Static usbd_status 4063 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4064 { 4065 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4066 usbd_status err; 4067 4068 mutex_enter(&sc->sc_lock); 4069 err = usb_insert_transfer(xfer); 4070 mutex_exit(&sc->sc_lock); 4071 4072 if (err && err != USBD_IN_PROGRESS) 4073 return err; 4074 4075 return ehci_device_fs_isoc_start(xfer); 4076 } 4077 4078 Static usbd_status 4079 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4080 { 4081 struct ehci_pipe *epipe; 4082 struct usbd_device *dev; 4083 ehci_softc_t *sc; 4084 struct ehci_xfer *exfer; 4085 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4086 usb_dma_t *dma_buf; 4087 int i, j, k, frames; 4088 int offs, total_length; 4089 int frindex; 4090 u_int huba, dir; 4091 4092 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4093 4094 start = NULL; 4095 prev = NULL; 4096 sitd = NULL; 4097 total_length = 0; 4098 exfer = (struct ehci_xfer *) xfer; 4099 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4100 dev = xfer->ux_pipe->up_dev; 4101 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4102 4103 /* 4104 * To allow continuous transfers, above we start all transfers 4105 * immediately. However, we're still going to get usbd_start_next call 4106 * this when another xfer completes. So, check if this is already 4107 * in progress or not 4108 */ 4109 4110 if (exfer->ex_sitdstart != NULL) 4111 return USBD_IN_PROGRESS; 4112 4113 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4114 xfer, xfer->ux_length, xfer->ux_flags, 0); 4115 4116 if (sc->sc_dying) 4117 return USBD_IOERROR; 4118 4119 /* 4120 * To avoid complication, don't allow a request right now that'll span 4121 * the entire frame table. To within 4 frames, to allow some leeway 4122 * on either side of where the hc currently is. 4123 */ 4124 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4125 xfer->ux_nframes >= sc->sc_flsize - 4) { 4126 printf("ehci: isoc descriptor requested that spans the entire" 4127 "frametable, too many frames\n"); 4128 return USBD_INVAL; 4129 } 4130 4131 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4132 KASSERT(exfer->ex_isdone); 4133 4134 #ifdef DIAGNOSTIC 4135 exfer->ex_isdone = false; 4136 #endif 4137 4138 /* 4139 * Step 1: Allocate and initialize sitds. 4140 */ 4141 4142 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4143 if (i > 16 || i == 0) { 4144 /* Spec page 271 says intervals > 16 are invalid */ 4145 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4146 4147 return USBD_INVAL; 4148 } 4149 4150 frames = xfer->ux_nframes; 4151 4152 if (frames == 0) { 4153 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4154 4155 return USBD_INVAL; 4156 } 4157 4158 dma_buf = &xfer->ux_dmabuf; 4159 offs = 0; 4160 4161 for (i = 0; i < frames; i++) { 4162 sitd = ehci_alloc_sitd(sc); 4163 4164 if (prev) 4165 prev->xfer_next = sitd; 4166 else 4167 start = sitd; 4168 4169 #ifdef DIAGNOSTIC 4170 if (xfer->ux_frlengths[i] > 0x3ff) { 4171 printf("ehci: invalid frame length\n"); 4172 xfer->ux_frlengths[i] = 0x3ff; 4173 } 4174 #endif 4175 4176 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4177 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4178 4179 /* Set page0 index and offset. */ 4180 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4181 4182 total_length += xfer->ux_frlengths[i]; 4183 offs += xfer->ux_frlengths[i]; 4184 4185 sitd->sitd.sitd_buffer[1] = 4186 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4187 4188 huba = dev->ud_myhsport->up_parent->ud_addr; 4189 4190 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4191 // Set hub address to 0 if embedded TT is used. 4192 if (huba == sc->sc_addr) 4193 huba = 0; 4194 } 4195 */ 4196 4197 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4198 dir = UE_GET_DIR(k) ? 1 : 0; 4199 sitd->sitd.sitd_endp = 4200 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4201 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4202 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4203 EHCI_SITD_SET_HUBA(huba) | 4204 EHCI_SITD_SET_DIR(dir)); 4205 4206 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4207 4208 /* XXX */ 4209 u_char sa, sb; 4210 u_int temp, tlen; 4211 sa = 0; 4212 4213 if (dir == 0) { /* OUT */ 4214 temp = 0; 4215 tlen = xfer->ux_frlengths[i]; 4216 if (tlen <= 188) { 4217 temp |= 1; /* T-count = 1, TP = ALL */ 4218 tlen = 1; 4219 } else { 4220 tlen += 187; 4221 tlen /= 188; 4222 temp |= tlen; /* T-count = [1..6] */ 4223 temp |= 8; /* TP = Begin */ 4224 } 4225 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4226 4227 tlen += sa; 4228 4229 if (tlen >= 8) { 4230 sb = 0; 4231 } else { 4232 sb = (1 << tlen); 4233 } 4234 4235 sa = (1 << sa); 4236 sa = (sb - sa) & 0x3F; 4237 sb = 0; 4238 } else { 4239 sb = (-(4 << sa)) & 0xFE; 4240 sa = (1 << sa) & 0x3F; 4241 sa = 0x01; 4242 sb = 0xfc; 4243 } 4244 4245 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4246 EHCI_SITD_SET_CMASK(sb)); 4247 4248 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4249 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4250 4251 prev = sitd; 4252 } /* End of frame */ 4253 4254 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4255 4256 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4257 sizeof(sitd->sitd.sitd_trans), 4258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4259 4260 stop = sitd; 4261 stop->xfer_next = NULL; 4262 4263 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4264 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4265 4266 /* 4267 * Part 2: Transfer descriptors have now been set up, now they must 4268 * be scheduled into the periodic frame list. Erk. Not wanting to 4269 * complicate matters, transfer is denied if the transfer spans 4270 * more than the period frame list. 4271 */ 4272 4273 mutex_enter(&sc->sc_lock); 4274 4275 /* Start inserting frames */ 4276 if (epipe->isoc.cur_xfers > 0) { 4277 frindex = epipe->isoc.next_frame; 4278 } else { 4279 frindex = EOREAD4(sc, EHCI_FRINDEX); 4280 frindex = frindex >> 3; /* Erase microframe index */ 4281 frindex += 2; 4282 } 4283 4284 if (frindex >= sc->sc_flsize) 4285 frindex &= (sc->sc_flsize - 1); 4286 4287 /* Whats the frame interval? */ 4288 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4289 4290 sitd = start; 4291 for (j = 0; j < frames; j++) { 4292 if (sitd == NULL) 4293 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4294 4295 usb_syncmem(&sc->sc_fldma, 4296 sizeof(ehci_link_t) * frindex, 4297 sizeof(ehci_link_t), 4298 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4299 4300 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4301 if (sitd->sitd.sitd_next == 0) 4302 /* 4303 * FIXME: frindex table gets initialized to NULL 4304 * or EHCI_NULL? 4305 */ 4306 sitd->sitd.sitd_next = EHCI_NULL; 4307 4308 usb_syncmem(&sitd->dma, 4309 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4310 sizeof(ehci_sitd_t), 4311 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4312 4313 sc->sc_flist[frindex] = 4314 htole32(EHCI_LINK_SITD | sitd->physaddr); 4315 4316 usb_syncmem(&sc->sc_fldma, 4317 sizeof(ehci_link_t) * frindex, 4318 sizeof(ehci_link_t), 4319 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4320 4321 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4322 sc->sc_softsitds[frindex] = sitd; 4323 if (sitd->frame_list.next != NULL) 4324 sitd->frame_list.next->frame_list.prev = sitd; 4325 sitd->slot = frindex; 4326 sitd->frame_list.prev = NULL; 4327 4328 frindex += i; 4329 if (frindex >= sc->sc_flsize) 4330 frindex -= sc->sc_flsize; 4331 4332 sitd = sitd->xfer_next; 4333 } 4334 4335 epipe->isoc.cur_xfers++; 4336 epipe->isoc.next_frame = frindex; 4337 4338 exfer->ex_sitdstart = start; 4339 exfer->ex_sitdend = stop; 4340 4341 ehci_add_intr_list(sc, exfer); 4342 xfer->ux_status = USBD_IN_PROGRESS; 4343 4344 mutex_exit(&sc->sc_lock); 4345 4346 if (sc->sc_bus.ub_usepolling) { 4347 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4348 ehci_waitintr(sc, xfer); 4349 } 4350 4351 return USBD_IN_PROGRESS; 4352 } 4353 4354 Static void 4355 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4356 { 4357 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4358 4359 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4360 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4361 } 4362 4363 Static void 4364 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4365 { 4366 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4367 4368 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4369 } 4370 4371 Static void 4372 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4373 { 4374 struct ehci_xfer *exfer; 4375 ehci_softc_t *sc; 4376 struct ehci_pipe *epipe; 4377 4378 exfer = EXFER(xfer); 4379 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4380 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4381 4382 KASSERT(mutex_owned(&sc->sc_lock)); 4383 4384 epipe->isoc.cur_xfers--; 4385 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4386 ehci_del_intr_list(sc, exfer); 4387 ehci_rem_free_sitd_chain(sc, exfer); 4388 } 4389 4390 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4391 BUS_DMASYNC_POSTREAD); 4392 } 4393 Static usbd_status 4394 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4395 { 4396 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4397 usbd_status err; 4398 4399 mutex_enter(&sc->sc_lock); 4400 err = usb_insert_transfer(xfer); 4401 mutex_exit(&sc->sc_lock); 4402 if (err && err != USBD_IN_PROGRESS) 4403 return err; 4404 4405 return ehci_device_isoc_start(xfer); 4406 } 4407 4408 Static usbd_status 4409 ehci_device_isoc_start(struct usbd_xfer *xfer) 4410 { 4411 struct ehci_pipe *epipe; 4412 ehci_softc_t *sc; 4413 struct ehci_xfer *exfer; 4414 ehci_soft_itd_t *itd, *prev, *start, *stop; 4415 usb_dma_t *dma_buf; 4416 int i, j, k, frames, uframes, ufrperframe; 4417 int trans_count, offs, total_length; 4418 int frindex; 4419 4420 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4421 4422 start = NULL; 4423 prev = NULL; 4424 itd = NULL; 4425 trans_count = 0; 4426 total_length = 0; 4427 exfer = (struct ehci_xfer *) xfer; 4428 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4429 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4430 4431 /* 4432 * To allow continuous transfers, above we start all transfers 4433 * immediately. However, we're still going to get usbd_start_next call 4434 * this when another xfer completes. So, check if this is already 4435 * in progress or not 4436 */ 4437 4438 if (exfer->ex_itdstart != NULL) 4439 return USBD_IN_PROGRESS; 4440 4441 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4442 xfer, xfer->ux_length, xfer->ux_flags, 0); 4443 4444 if (sc->sc_dying) 4445 return USBD_IOERROR; 4446 4447 /* 4448 * To avoid complication, don't allow a request right now that'll span 4449 * the entire frame table. To within 4 frames, to allow some leeway 4450 * on either side of where the hc currently is. 4451 */ 4452 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4453 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4454 USBHIST_LOG(ehcidebug, 4455 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4456 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4457 return USBD_INVAL; 4458 } 4459 4460 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4461 KASSERT(exfer->ex_isdone); 4462 #ifdef DIAGNOSTIC 4463 exfer->ex_isdone = false; 4464 #endif 4465 4466 /* 4467 * Step 1: Allocate and initialize itds, how many do we need? 4468 * One per transfer if interval >= 8 microframes, fewer if we use 4469 * multiple microframes per frame. 4470 */ 4471 4472 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4473 if (i > 16 || i == 0) { 4474 /* Spec page 271 says intervals > 16 are invalid */ 4475 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4476 return USBD_INVAL; 4477 } 4478 4479 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4480 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4481 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4482 4483 if (frames == 0) { 4484 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4485 return USBD_INVAL; 4486 } 4487 4488 dma_buf = &xfer->ux_dmabuf; 4489 offs = 0; 4490 4491 for (i = 0; i < frames; i++) { 4492 int froffs = offs; 4493 itd = ehci_alloc_itd(sc); 4494 4495 if (prev != NULL) { 4496 prev->itd.itd_next = 4497 htole32(itd->physaddr | EHCI_LINK_ITD); 4498 usb_syncmem(&prev->dma, 4499 prev->offs + offsetof(ehci_itd_t, itd_next), 4500 sizeof(prev->itd.itd_next), 4501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4502 4503 prev->xfer_next = itd; 4504 } else { 4505 start = itd; 4506 } 4507 4508 /* 4509 * Step 1.5, initialize uframes 4510 */ 4511 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4512 /* Calculate which page in the list this starts in */ 4513 int addr = DMAADDR(dma_buf, froffs); 4514 addr = EHCI_PAGE_OFFSET(addr); 4515 addr += (offs - froffs); 4516 addr = EHCI_PAGE(addr); 4517 addr /= EHCI_PAGE_SIZE; 4518 4519 /* 4520 * This gets the initial offset into the first page, 4521 * looks how far further along the current uframe 4522 * offset is. Works out how many pages that is. 4523 */ 4524 4525 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4526 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4527 EHCI_ITD_SET_PG(addr) | 4528 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4529 4530 total_length += xfer->ux_frlengths[trans_count]; 4531 offs += xfer->ux_frlengths[trans_count]; 4532 trans_count++; 4533 4534 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4535 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4536 break; 4537 } 4538 } 4539 4540 /* 4541 * Step 1.75, set buffer pointers. To simplify matters, all 4542 * pointers are filled out for the next 7 hardware pages in 4543 * the dma block, so no need to worry what pages to cover 4544 * and what to not. 4545 */ 4546 4547 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4548 /* 4549 * Don't try to lookup a page that's past the end 4550 * of buffer 4551 */ 4552 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4553 if (page_offs >= dma_buf->udma_block->size) 4554 break; 4555 4556 unsigned long long page = DMAADDR(dma_buf, page_offs); 4557 page = EHCI_PAGE(page); 4558 itd->itd.itd_bufr[j] = 4559 htole32(EHCI_ITD_SET_BPTR(page)); 4560 itd->itd.itd_bufr_hi[j] = 4561 htole32(page >> 32); 4562 } 4563 4564 /* 4565 * Other special values 4566 */ 4567 4568 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4569 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4570 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4571 4572 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4573 ? 1 : 0; 4574 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4575 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4576 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4577 4578 /* FIXME: handle invalid trans */ 4579 itd->itd.itd_bufr[2] |= 4580 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4581 4582 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4584 4585 prev = itd; 4586 } /* End of frame */ 4587 4588 stop = itd; 4589 stop->xfer_next = NULL; 4590 4591 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4592 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4593 4594 /* 4595 * Part 2: Transfer descriptors have now been set up, now they must 4596 * be scheduled into the period frame list. Erk. Not wanting to 4597 * complicate matters, transfer is denied if the transfer spans 4598 * more than the period frame list. 4599 */ 4600 4601 mutex_enter(&sc->sc_lock); 4602 4603 /* Start inserting frames */ 4604 if (epipe->isoc.cur_xfers > 0) { 4605 frindex = epipe->isoc.next_frame; 4606 } else { 4607 frindex = EOREAD4(sc, EHCI_FRINDEX); 4608 frindex = frindex >> 3; /* Erase microframe index */ 4609 frindex += 2; 4610 } 4611 4612 if (frindex >= sc->sc_flsize) 4613 frindex &= (sc->sc_flsize - 1); 4614 4615 /* What's the frame interval? */ 4616 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4617 if (i / USB_UFRAMES_PER_FRAME == 0) 4618 i = 1; 4619 else 4620 i /= USB_UFRAMES_PER_FRAME; 4621 4622 itd = start; 4623 for (j = 0; j < frames; j++) { 4624 if (itd == NULL) 4625 panic("ehci: unexpectedly ran out of isoc itds, isoc_start"); 4626 4627 usb_syncmem(&sc->sc_fldma, 4628 sizeof(ehci_link_t) * frindex, 4629 sizeof(ehci_link_t), 4630 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4631 4632 itd->itd.itd_next = sc->sc_flist[frindex]; 4633 if (itd->itd.itd_next == 0) 4634 /* FIXME: frindex table gets initialized to NULL 4635 * or EHCI_NULL? */ 4636 itd->itd.itd_next = EHCI_NULL; 4637 4638 usb_syncmem(&itd->dma, 4639 itd->offs + offsetof(ehci_itd_t, itd_next), 4640 sizeof(itd->itd.itd_next), 4641 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4642 4643 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4644 4645 usb_syncmem(&sc->sc_fldma, 4646 sizeof(ehci_link_t) * frindex, 4647 sizeof(ehci_link_t), 4648 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4649 4650 itd->frame_list.next = sc->sc_softitds[frindex]; 4651 sc->sc_softitds[frindex] = itd; 4652 if (itd->frame_list.next != NULL) 4653 itd->frame_list.next->frame_list.prev = itd; 4654 itd->slot = frindex; 4655 itd->frame_list.prev = NULL; 4656 4657 frindex += i; 4658 if (frindex >= sc->sc_flsize) 4659 frindex -= sc->sc_flsize; 4660 4661 itd = itd->xfer_next; 4662 } 4663 4664 epipe->isoc.cur_xfers++; 4665 epipe->isoc.next_frame = frindex; 4666 4667 exfer->ex_itdstart = start; 4668 exfer->ex_itdend = stop; 4669 4670 ehci_add_intr_list(sc, exfer); 4671 xfer->ux_status = USBD_IN_PROGRESS; 4672 mutex_exit(&sc->sc_lock); 4673 4674 if (sc->sc_bus.ub_usepolling) { 4675 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4676 ehci_waitintr(sc, xfer); 4677 } 4678 4679 return USBD_IN_PROGRESS; 4680 } 4681 4682 Static void 4683 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4684 { 4685 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4686 4687 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4688 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4689 } 4690 4691 Static void 4692 ehci_device_isoc_close(struct usbd_pipe *pipe) 4693 { 4694 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4695 4696 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4697 } 4698 4699 Static void 4700 ehci_device_isoc_done(struct usbd_xfer *xfer) 4701 { 4702 struct ehci_xfer *exfer; 4703 ehci_softc_t *sc; 4704 struct ehci_pipe *epipe; 4705 4706 exfer = EXFER(xfer); 4707 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4708 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4709 4710 KASSERT(mutex_owned(&sc->sc_lock)); 4711 4712 epipe->isoc.cur_xfers--; 4713 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4714 ehci_del_intr_list(sc, exfer); 4715 ehci_rem_free_itd_chain(sc, exfer); 4716 } 4717 4718 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4719 BUS_DMASYNC_POSTREAD); 4720 4721 } 4722
Indexes created Wed Oct 01 19:09:53 GMT 2025