ehci.c revision 1.234.2.50
1 /* $NetBSD: ehci.c,v 1.234.2.50 2015/09/22 12:06:01 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.50 2015/09/22 12:06:01 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 ehci_soft_qtd_t *qtd; 136 /* ehci_soft_itd_t *itd; */ 137 /* ehci_soft_sitd_t *sitd; */ 138 } tail; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 Static usbd_status ehci_open(struct usbd_pipe *); 157 Static void ehci_poll(struct usbd_bus *); 158 Static void ehci_softintr(void *); 159 Static int ehci_intr1(ehci_softc_t *); 160 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 161 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_idone(struct ehci_xfer *); 166 Static void ehci_timeout(void *); 167 Static void ehci_timeout_task(void *); 168 Static void ehci_intrlist_timeout(void *); 169 Static void ehci_doorbell(void *); 170 Static void ehci_pcd(void *); 171 172 Static struct usbd_xfer * 173 ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 180 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 181 Static void ehci_root_intr_abort(struct usbd_xfer *); 182 Static void ehci_root_intr_close(struct usbd_pipe *); 183 Static void ehci_root_intr_done(struct usbd_xfer *); 184 185 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 186 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 187 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 188 Static void ehci_device_ctrl_close(struct usbd_pipe *); 189 Static void ehci_device_ctrl_done(struct usbd_xfer *); 190 191 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 193 Static void ehci_device_bulk_abort(struct usbd_xfer *); 194 Static void ehci_device_bulk_close(struct usbd_pipe *); 195 Static void ehci_device_bulk_done(struct usbd_xfer *); 196 197 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 198 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 199 Static void ehci_device_intr_abort(struct usbd_xfer *); 200 Static void ehci_device_intr_close(struct usbd_pipe *); 201 Static void ehci_device_intr_done(struct usbd_xfer *); 202 203 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 204 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 205 Static void ehci_device_isoc_abort(struct usbd_xfer *); 206 Static void ehci_device_isoc_close(struct usbd_pipe *); 207 Static void ehci_device_isoc_done(struct usbd_xfer *); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 210 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 211 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 212 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 213 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 214 215 Static void ehci_device_clear_toggle(struct usbd_pipe *); 216 Static void ehci_noop(struct usbd_pipe *); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, struct usbd_xfer *, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(struct usbd_xfer *); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* XXX need proper intr scheduling */ 451 sc->sc_rand = 96; 452 453 /* frame list size at default, read back what we got and use that */ 454 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 455 case 0: sc->sc_flsize = 1024; break; 456 case 1: sc->sc_flsize = 512; break; 457 case 2: sc->sc_flsize = 256; break; 458 case 3: return EIO; 459 } 460 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 461 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 462 if (err) 463 return err; 464 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 465 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 466 467 for (i = 0; i < sc->sc_flsize; i++) { 468 sc->sc_flist[i] = EHCI_NULL; 469 } 470 471 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 472 473 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 474 KM_SLEEP); 475 if (sc->sc_softitds == NULL) 476 return ENOMEM; 477 LIST_INIT(&sc->sc_freeitds); 478 LIST_INIT(&sc->sc_freesitds); 479 TAILQ_INIT(&sc->sc_intrhead); 480 481 /* Set up the bus struct. */ 482 sc->sc_bus.ub_methods = &ehci_bus_methods; 483 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 484 485 sc->sc_eintrs = EHCI_NORMAL_INTRS; 486 487 /* 488 * Allocate the interrupt dummy QHs. These are arranged to give poll 489 * intervals that are powers of 2 times 1ms. 490 */ 491 for (i = 0; i < EHCI_INTRQHS; i++) { 492 sqh = ehci_alloc_sqh(sc); 493 if (sqh == NULL) { 494 err = ENOMEM; 495 goto bad1; 496 } 497 sc->sc_islots[i].sqh = sqh; 498 } 499 for (i = 0; i < EHCI_INTRQHS; i++) { 500 sqh = sc->sc_islots[i].sqh; 501 if (i == 0) { 502 /* The last (1ms) QH terminates. */ 503 sqh->qh.qh_link = EHCI_NULL; 504 sqh->next = NULL; 505 } else { 506 /* Otherwise the next QH has half the poll interval */ 507 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 508 sqh->qh.qh_link = htole32(sqh->next->physaddr | 509 EHCI_LINK_QH); 510 } 511 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 512 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 513 sqh->qh.qh_curqtd = EHCI_NULL; 514 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 515 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 516 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 517 sqh->sqtd = NULL; 518 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 520 } 521 /* Point the frame list at the last level (128ms). */ 522 for (i = 0; i < sc->sc_flsize; i++) { 523 int j; 524 525 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 526 revbits[i & (EHCI_MAX_POLLRATE-1)]; 527 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 528 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 529 i)].sqh->physaddr); 530 } 531 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 532 BUS_DMASYNC_PREWRITE); 533 534 /* Allocate dummy QH that starts the async list. */ 535 sqh = ehci_alloc_sqh(sc); 536 if (sqh == NULL) { 537 err = ENOMEM; 538 goto bad1; 539 } 540 /* Fill the QH */ 541 sqh->qh.qh_endp = 542 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 543 sqh->qh.qh_link = 544 htole32(sqh->physaddr | EHCI_LINK_QH); 545 sqh->qh.qh_curqtd = EHCI_NULL; 546 sqh->next = NULL; 547 /* Fill the overlay qTD */ 548 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 549 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 550 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 551 sqh->sqtd = NULL; 552 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 553 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 554 #ifdef EHCI_DEBUG 555 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 556 ehci_dump_sqh(sqh); 557 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 558 #endif 559 560 /* Point to async list */ 561 sc->sc_async_head = sqh; 562 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 563 564 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 565 566 /* Turn on controller */ 567 EOWRITE4(sc, EHCI_USBCMD, 568 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 569 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 570 EHCI_CMD_ASE | 571 EHCI_CMD_PSE | 572 EHCI_CMD_RS); 573 574 /* Take over port ownership */ 575 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 576 577 for (i = 0; i < 100; i++) { 578 usb_delay_ms(&sc->sc_bus, 1); 579 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 580 if (!hcr) 581 break; 582 } 583 if (hcr) { 584 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 585 return EIO; 586 } 587 588 /* Enable interrupts */ 589 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 590 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 591 592 return 0; 593 594 #if 0 595 bad2: 596 ehci_free_sqh(sc, sc->sc_async_head); 597 #endif 598 bad1: 599 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 600 return err; 601 } 602 603 int 604 ehci_intr(void *v) 605 { 606 ehci_softc_t *sc = v; 607 int ret = 0; 608 609 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 610 611 if (sc == NULL) 612 return 0; 613 614 mutex_spin_enter(&sc->sc_intr_lock); 615 616 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 617 goto done; 618 619 /* If we get an interrupt while polling, then just ignore it. */ 620 if (sc->sc_bus.ub_usepolling) { 621 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 622 623 if (intrs) 624 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 625 USBHIST_LOGN(ehcidebug, 16, 626 "ignored interrupt while polling", 0, 0, 0, 0); 627 goto done; 628 } 629 630 ret = ehci_intr1(sc); 631 632 done: 633 mutex_spin_exit(&sc->sc_intr_lock); 634 return ret; 635 } 636 637 Static int 638 ehci_intr1(ehci_softc_t *sc) 639 { 640 uint32_t intrs, eintrs; 641 642 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 643 644 /* In case the interrupt occurs before initialization has completed. */ 645 if (sc == NULL) { 646 #ifdef DIAGNOSTIC 647 printf("ehci_intr1: sc == NULL\n"); 648 #endif 649 return 0; 650 } 651 652 KASSERT(mutex_owned(&sc->sc_intr_lock)); 653 654 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 655 if (!intrs) 656 return 0; 657 658 eintrs = intrs & sc->sc_eintrs; 659 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 660 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 661 if (!eintrs) 662 return 0; 663 664 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 665 if (eintrs & EHCI_STS_IAA) { 666 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 667 kpreempt_disable(); 668 KASSERT(sc->sc_doorbell_si != NULL); 669 softint_schedule(sc->sc_doorbell_si); 670 kpreempt_enable(); 671 eintrs &= ~EHCI_STS_IAA; 672 } 673 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 674 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 675 eintrs & EHCI_STS_INT ? 1 : 0, 676 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 677 usb_schedsoftintr(&sc->sc_bus); 678 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 679 } 680 if (eintrs & EHCI_STS_HSE) { 681 printf("%s: unrecoverable error, controller halted\n", 682 device_xname(sc->sc_dev)); 683 /* XXX what else */ 684 } 685 if (eintrs & EHCI_STS_PCD) { 686 kpreempt_disable(); 687 KASSERT(sc->sc_pcd_si != NULL); 688 softint_schedule(sc->sc_pcd_si); 689 kpreempt_enable(); 690 eintrs &= ~EHCI_STS_PCD; 691 } 692 693 if (eintrs != 0) { 694 /* Block unprocessed interrupts. */ 695 sc->sc_eintrs &= ~eintrs; 696 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 697 printf("%s: blocking intrs 0x%x\n", 698 device_xname(sc->sc_dev), eintrs); 699 } 700 701 return 1; 702 } 703 704 Static void 705 ehci_doorbell(void *addr) 706 { 707 ehci_softc_t *sc = addr; 708 709 mutex_enter(&sc->sc_lock); 710 cv_broadcast(&sc->sc_doorbell); 711 mutex_exit(&sc->sc_lock); 712 } 713 714 Static void 715 ehci_pcd(void *addr) 716 { 717 ehci_softc_t *sc = addr; 718 struct usbd_xfer *xfer; 719 u_char *p; 720 int i, m; 721 722 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 723 724 mutex_enter(&sc->sc_lock); 725 xfer = sc->sc_intrxfer; 726 727 if (xfer == NULL) { 728 /* Just ignore the change. */ 729 goto done; 730 } 731 732 p = xfer->ux_buf; 733 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 734 memset(p, 0, xfer->ux_length); 735 for (i = 1; i <= m; i++) { 736 /* Pick out CHANGE bits from the status reg. */ 737 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 738 p[i/8] |= 1 << (i%8); 739 if (i % 8 == 7) 740 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 741 p[i/8], 0, 0); 742 } 743 xfer->ux_actlen = xfer->ux_length; 744 xfer->ux_status = USBD_NORMAL_COMPLETION; 745 746 usb_transfer_complete(xfer); 747 748 done: 749 mutex_exit(&sc->sc_lock); 750 } 751 752 Static void 753 ehci_softintr(void *v) 754 { 755 struct usbd_bus *bus = v; 756 ehci_softc_t *sc = bus->ub_hcpriv; 757 struct ehci_xfer *ex, *nextex; 758 759 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 760 761 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 762 763 /* 764 * The only explanation I can think of for why EHCI is as brain dead 765 * as UHCI interrupt-wise is that Intel was involved in both. 766 * An interrupt just tells us that something is done, we have no 767 * clue what, so we need to scan through all active transfers. :-( 768 */ 769 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 770 nextex = TAILQ_NEXT(ex, ex_next); 771 ehci_check_intr(sc, ex); 772 } 773 774 /* Schedule a callout to catch any dropped transactions. */ 775 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 776 !TAILQ_EMPTY(&sc->sc_intrhead)) 777 callout_reset(&sc->sc_tmo_intrlist, 778 hz, ehci_intrlist_timeout, sc); 779 780 if (sc->sc_softwake) { 781 sc->sc_softwake = 0; 782 cv_broadcast(&sc->sc_softwake_cv); 783 } 784 } 785 786 /* Check for an interrupt. */ 787 Static void 788 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 789 { 790 struct usbd_device *dev = ex->ex_xfer.ux_pipe->up_dev; 791 int attr; 792 793 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 794 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 795 796 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 797 798 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 799 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 800 if (dev->ud_speed == USB_SPEED_HIGH) 801 ehci_check_itd_intr(sc, ex); 802 else 803 ehci_check_sitd_intr(sc, ex); 804 } else 805 ehci_check_qh_intr(sc, ex); 806 807 return; 808 } 809 810 Static void 811 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 812 { 813 ehci_soft_qtd_t *sqtd, *lsqtd; 814 uint32_t status; 815 816 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 817 818 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 819 820 if (ex->ex_sqtdstart == NULL) { 821 printf("ehci_check_qh_intr: not valid sqtd\n"); 822 return; 823 } 824 825 lsqtd = ex->ex_sqtdend; 826 #ifdef DIAGNOSTIC 827 if (lsqtd == NULL) { 828 printf("ehci_check_qh_intr: lsqtd==0\n"); 829 return; 830 } 831 #endif 832 /* 833 * If the last TD is still active we need to check whether there 834 * is an error somewhere in the middle, or whether there was a 835 * short packet (SPD and not ACTIVE). 836 */ 837 usb_syncmem(&lsqtd->dma, 838 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 839 sizeof(lsqtd->qtd.qtd_status), 840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 841 status = le32toh(lsqtd->qtd.qtd_status); 842 usb_syncmem(&lsqtd->dma, 843 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 844 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 845 if (status & EHCI_QTD_ACTIVE) { 846 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 847 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 848 sqtd = sqtd->nextqtd) { 849 usb_syncmem(&sqtd->dma, 850 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 851 sizeof(sqtd->qtd.qtd_status), 852 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 853 status = le32toh(sqtd->qtd.qtd_status); 854 usb_syncmem(&sqtd->dma, 855 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 856 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 857 /* If there's an active QTD the xfer isn't done. */ 858 if (status & EHCI_QTD_ACTIVE) 859 break; 860 /* Any kind of error makes the xfer done. */ 861 if (status & EHCI_QTD_HALTED) 862 goto done; 863 /* Handle short packets */ 864 if (EHCI_QTD_GET_BYTES(status) != 0) { 865 struct usbd_pipe *pipe = ex->ex_xfer.ux_pipe; 866 usb_endpoint_descriptor_t *ed = 867 pipe->up_endpoint->ue_edesc; 868 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 869 870 /* 871 * If we get here for a control transfer then 872 * we need to let the hardware complete the 873 * status phase. That is, we're not done 874 * quite yet. 875 * 876 * Otherwise, we're done. 877 */ 878 if (xt == UE_CONTROL) { 879 break; 880 } 881 goto done; 882 } 883 } 884 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 885 ex, ex->ex_sqtdstart, 0, 0); 886 #ifdef EHCI_DEBUG 887 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 0, 0); 888 ehci_dump_sqtds(ex->ex_sqtdstart); 889 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 0); 890 #endif 891 return; 892 } 893 done: 894 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 895 callout_stop(&ex->ex_xfer.ux_callout); 896 ehci_idone(ex); 897 } 898 899 Static void 900 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 901 { 902 ehci_soft_itd_t *itd; 903 int i; 904 905 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 906 907 KASSERT(mutex_owned(&sc->sc_lock)); 908 909 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 910 return; 911 912 if (ex->ex_itdstart == NULL) { 913 printf("ehci_check_itd_intr: not valid itd\n"); 914 return; 915 } 916 917 itd = ex->ex_itdend; 918 #ifdef DIAGNOSTIC 919 if (itd == NULL) { 920 printf("ehci_check_itd_intr: itdend == 0\n"); 921 return; 922 } 923 #endif 924 925 /* 926 * check no active transfers in last itd, meaning we're finished 927 */ 928 929 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 930 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 931 BUS_DMASYNC_POSTREAD); 932 933 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 934 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 935 break; 936 } 937 938 if (i == EHCI_ITD_NUFRAMES) { 939 goto done; /* All 8 descriptors inactive, it's done */ 940 } 941 942 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 943 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 944 945 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 946 ex->ex_itdstart, 0, 0); 947 return; 948 done: 949 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 950 callout_stop(&ex->ex_xfer.ux_callout); 951 ehci_idone(ex); 952 } 953 954 void 955 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 956 { 957 ehci_soft_sitd_t *sitd; 958 959 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 960 961 KASSERT(mutex_owned(&sc->sc_lock)); 962 963 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 964 return; 965 966 if (ex->ex_sitdstart == NULL) { 967 printf("ehci_check_sitd_intr: not valid sitd\n"); 968 return; 969 } 970 971 sitd = ex->ex_sitdend; 972 #ifdef DIAGNOSTIC 973 if (sitd == NULL) { 974 printf("ehci_check_sitd_intr: sitdend == 0\n"); 975 return; 976 } 977 #endif 978 979 /* 980 * check no active transfers in last sitd, meaning we're finished 981 */ 982 983 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 984 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_POSTWRITE | 985 BUS_DMASYNC_POSTREAD); 986 987 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 988 return; 989 990 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 991 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 992 993 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 994 callout_stop(&(ex->ex_xfer.ux_callout)); 995 ehci_idone(ex); 996 } 997 998 999 Static void 1000 ehci_idone(struct ehci_xfer *ex) 1001 { 1002 struct usbd_xfer *xfer = &ex->ex_xfer; 1003 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1004 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1005 ehci_soft_qtd_t *sqtd, *lsqtd; 1006 uint32_t status = 0, nstatus = 0; 1007 int actlen; 1008 1009 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1010 1011 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1012 1013 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1014 1015 #ifdef DIAGNOSTIC 1016 #ifdef EHCI_DEBUG 1017 if (ex->ex_isdone) { 1018 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1019 ehci_dump_exfer(ex); 1020 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1021 } 1022 #endif 1023 KASSERT(!ex->ex_isdone); 1024 ex->ex_isdone = true; 1025 #endif 1026 1027 if (xfer->ux_status == USBD_CANCELLED || 1028 xfer->ux_status == USBD_TIMEOUT) { 1029 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1030 return; 1031 } 1032 1033 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1034 1035 /* The transfer is done, compute actual length and status. */ 1036 1037 u_int xfertype, speed; 1038 1039 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1040 speed = xfer->ux_pipe->up_dev->ud_speed; 1041 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1042 /* HS isoc transfer */ 1043 1044 struct ehci_soft_itd *itd; 1045 int i, nframes, len, uframes; 1046 1047 nframes = 0; 1048 actlen = 0; 1049 1050 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1051 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1052 1053 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1054 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1055 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1056 BUS_DMASYNC_POSTREAD); 1057 1058 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1059 /* 1060 * XXX - driver didn't fill in the frame full 1061 * of uframes. This leads to scheduling 1062 * inefficiencies, but working around 1063 * this doubles complexity of tracking 1064 * an xfer. 1065 */ 1066 if (nframes >= xfer->ux_nframes) 1067 break; 1068 1069 status = le32toh(itd->itd.itd_ctl[i]); 1070 len = EHCI_ITD_GET_LEN(status); 1071 if (EHCI_ITD_GET_STATUS(status) != 0) 1072 len = 0; /*No valid data on error*/ 1073 1074 xfer->ux_frlengths[nframes++] = len; 1075 actlen += len; 1076 } 1077 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1078 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1079 1080 if (nframes >= xfer->ux_nframes) 1081 break; 1082 } 1083 1084 xfer->ux_actlen = actlen; 1085 xfer->ux_status = USBD_NORMAL_COMPLETION; 1086 goto end; 1087 } 1088 1089 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1090 /* FS isoc transfer */ 1091 struct ehci_soft_sitd *sitd; 1092 int nframes, len; 1093 1094 nframes = 0; 1095 actlen = 0; 1096 1097 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1098 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1099 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_POSTWRITE | 1100 BUS_DMASYNC_POSTREAD); 1101 1102 /* 1103 * XXX - driver didn't fill in the frame full 1104 * of uframes. This leads to scheduling 1105 * inefficiencies, but working around 1106 * this doubles complexity of tracking 1107 * an xfer. 1108 */ 1109 if (nframes >= xfer->ux_nframes) 1110 break; 1111 1112 status = le32toh(sitd->sitd.sitd_trans); 1113 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1114 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1115 1116 len = EHCI_SITD_GET_LEN(status); 1117 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1118 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1119 /* No valid data on error */ 1120 len = xfer->ux_frlengths[nframes]; 1121 } 1122 1123 /* 1124 * frlengths[i]: # of bytes to send 1125 * len: # of bytes host didn't send 1126 */ 1127 xfer->ux_frlengths[nframes] -= len; 1128 /* frlengths[i]: # of bytes host sent */ 1129 actlen += xfer->ux_frlengths[nframes++]; 1130 1131 if (nframes >= xfer->ux_nframes) 1132 break; 1133 } 1134 1135 xfer->ux_actlen = actlen; 1136 xfer->ux_status = USBD_NORMAL_COMPLETION; 1137 goto end; 1138 } 1139 KASSERT(xfertype != UE_ISOCHRONOUS); 1140 1141 /* Continue processing xfers using queue heads */ 1142 1143 #ifdef EHCI_DEBUG 1144 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1145 ehci_dump_sqtds(ex->ex_sqtdstart); 1146 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1147 #endif 1148 1149 lsqtd = ex->ex_sqtdend; 1150 actlen = 0; 1151 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1152 sqtd = sqtd->nextqtd) { 1153 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1154 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1155 nstatus = le32toh(sqtd->qtd.qtd_status); 1156 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1157 BUS_DMASYNC_PREREAD); 1158 if (nstatus & EHCI_QTD_ACTIVE) 1159 break; 1160 1161 status = nstatus; 1162 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1163 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1164 } 1165 1166 1167 /* 1168 * If there are left over TDs we need to update the toggle. 1169 * The default pipe doesn't need it since control transfers 1170 * start the toggle at 0 every time. 1171 * For a short transfer we need to update the toggle for the missing 1172 * packets within the qTD. 1173 */ 1174 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1175 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1176 USBHIST_LOG(ehcidebug, 1177 "toggle update status=0x%08x nstatus=0x%08x", 1178 status, nstatus, 0, 0); 1179 #if 0 1180 ehci_dump_sqh(epipe->sqh); 1181 ehci_dump_sqtds(ex->ex_sqtdstart); 1182 #endif 1183 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1184 } 1185 1186 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1187 actlen, status, 0); 1188 xfer->ux_actlen = actlen; 1189 if (status & EHCI_QTD_HALTED) { 1190 #ifdef EHCI_DEBUG 1191 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1192 xfer->ux_pipe->up_dev->ud_addr, 1193 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1194 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1195 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1196 0, 0); 1197 USBHIST_LOG(ehcidebug, 1198 "active =%d halted=%d buferr=%d babble=%d", 1199 status & EHCI_QTD_ACTIVE ? 1 : 0, 1200 status & EHCI_QTD_HALTED ? 1 : 0, 1201 status & EHCI_QTD_BUFERR ? 1 : 0, 1202 status & EHCI_QTD_BABBLE ? 1 : 0); 1203 1204 USBHIST_LOG(ehcidebug, 1205 "xacterr=%d missed=%d split =%d ping =%d", 1206 status & EHCI_QTD_XACTERR ? 1 : 0, 1207 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1208 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1209 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1210 1211 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1212 ehci_dump_sqh(epipe->sqh); 1213 ehci_dump_sqtds(ex->ex_sqtdstart); 1214 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1215 #endif 1216 /* low&full speed has an extra error flag */ 1217 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1218 EHCI_QH_SPEED_HIGH) 1219 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1220 else 1221 status &= EHCI_QTD_STATERRS; 1222 if (status == 0) /* no other errors means a stall */ { 1223 xfer->ux_status = USBD_STALLED; 1224 } else { 1225 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1226 } 1227 /* XXX need to reset TT on missed microframe */ 1228 if (status & EHCI_QTD_MISSEDMICRO) { 1229 printf("%s: missed microframe, TT reset not " 1230 "implemented, hub might be inoperational\n", 1231 device_xname(sc->sc_dev)); 1232 } 1233 } else { 1234 xfer->ux_status = USBD_NORMAL_COMPLETION; 1235 } 1236 1237 end: 1238 /* 1239 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1240 * during this call, before methods->done is called: dma sync required 1241 * beforehand? 1242 */ 1243 usb_transfer_complete(xfer); 1244 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1245 } 1246 1247 /* 1248 * Wait here until controller claims to have an interrupt. 1249 * Then call ehci_intr and return. Use timeout to avoid waiting 1250 * too long. 1251 */ 1252 Static void 1253 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1254 { 1255 int timo; 1256 uint32_t intrs; 1257 1258 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1259 1260 xfer->ux_status = USBD_IN_PROGRESS; 1261 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1262 usb_delay_ms(&sc->sc_bus, 1); 1263 if (sc->sc_dying) 1264 break; 1265 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1266 sc->sc_eintrs; 1267 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1268 #ifdef EHCI_DEBUG 1269 if (ehcidebug > 15) 1270 ehci_dump_regs(sc); 1271 #endif 1272 if (intrs) { 1273 mutex_spin_enter(&sc->sc_intr_lock); 1274 ehci_intr1(sc); 1275 mutex_spin_exit(&sc->sc_intr_lock); 1276 if (xfer->ux_status != USBD_IN_PROGRESS) 1277 return; 1278 } 1279 } 1280 1281 /* Timeout */ 1282 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1283 xfer->ux_status = USBD_TIMEOUT; 1284 mutex_enter(&sc->sc_lock); 1285 usb_transfer_complete(xfer); 1286 mutex_exit(&sc->sc_lock); 1287 /* XXX should free TD */ 1288 } 1289 1290 Static void 1291 ehci_poll(struct usbd_bus *bus) 1292 { 1293 ehci_softc_t *sc = bus->ub_hcpriv; 1294 1295 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1296 1297 #ifdef EHCI_DEBUG 1298 static int last; 1299 int new; 1300 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1301 if (new != last) { 1302 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1303 last = new; 1304 } 1305 #endif 1306 1307 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1308 mutex_spin_enter(&sc->sc_intr_lock); 1309 ehci_intr1(sc); 1310 mutex_spin_exit(&sc->sc_intr_lock); 1311 } 1312 } 1313 1314 void 1315 ehci_childdet(device_t self, device_t child) 1316 { 1317 struct ehci_softc *sc = device_private(self); 1318 1319 KASSERT(sc->sc_child == child); 1320 sc->sc_child = NULL; 1321 } 1322 1323 int 1324 ehci_detach(struct ehci_softc *sc, int flags) 1325 { 1326 int rv = 0; 1327 1328 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1329 1330 if (sc->sc_child != NULL) 1331 rv = config_detach(sc->sc_child, flags); 1332 1333 if (rv != 0) 1334 return rv; 1335 1336 callout_halt(&sc->sc_tmo_intrlist, NULL); 1337 callout_destroy(&sc->sc_tmo_intrlist); 1338 1339 /* XXX free other data structures XXX */ 1340 if (sc->sc_softitds) 1341 kmem_free(sc->sc_softitds, 1342 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1343 cv_destroy(&sc->sc_doorbell); 1344 cv_destroy(&sc->sc_softwake_cv); 1345 1346 #if 0 1347 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1348 1349 softint_disestablish(sc->sc_doorbell_si); 1350 softint_disestablish(sc->sc_pcd_si); 1351 1352 mutex_destroy(&sc->sc_lock); 1353 mutex_destroy(&sc->sc_intr_lock); 1354 #endif 1355 1356 pool_cache_destroy(sc->sc_xferpool); 1357 1358 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1359 1360 return rv; 1361 } 1362 1363 1364 int 1365 ehci_activate(device_t self, enum devact act) 1366 { 1367 struct ehci_softc *sc = device_private(self); 1368 1369 switch (act) { 1370 case DVACT_DEACTIVATE: 1371 sc->sc_dying = 1; 1372 return 0; 1373 default: 1374 return EOPNOTSUPP; 1375 } 1376 } 1377 1378 /* 1379 * Handle suspend/resume. 1380 * 1381 * We need to switch to polling mode here, because this routine is 1382 * called from an interrupt context. This is all right since we 1383 * are almost suspended anyway. 1384 * 1385 * Note that this power handler isn't to be registered directly; the 1386 * bus glue needs to call out to it. 1387 */ 1388 bool 1389 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1390 { 1391 ehci_softc_t *sc = device_private(dv); 1392 int i; 1393 uint32_t cmd, hcr; 1394 1395 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1396 1397 mutex_spin_enter(&sc->sc_intr_lock); 1398 sc->sc_bus.ub_usepolling++; 1399 mutex_spin_exit(&sc->sc_intr_lock); 1400 1401 for (i = 1; i <= sc->sc_noport; i++) { 1402 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1403 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1404 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1405 } 1406 1407 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1408 1409 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1410 EOWRITE4(sc, EHCI_USBCMD, cmd); 1411 1412 for (i = 0; i < 100; i++) { 1413 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1414 if (hcr == 0) 1415 break; 1416 1417 usb_delay_ms(&sc->sc_bus, 1); 1418 } 1419 if (hcr != 0) 1420 printf("%s: reset timeout\n", device_xname(dv)); 1421 1422 cmd &= ~EHCI_CMD_RS; 1423 EOWRITE4(sc, EHCI_USBCMD, cmd); 1424 1425 for (i = 0; i < 100; i++) { 1426 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1427 if (hcr == EHCI_STS_HCH) 1428 break; 1429 1430 usb_delay_ms(&sc->sc_bus, 1); 1431 } 1432 if (hcr != EHCI_STS_HCH) 1433 printf("%s: config timeout\n", device_xname(dv)); 1434 1435 mutex_spin_enter(&sc->sc_intr_lock); 1436 sc->sc_bus.ub_usepolling--; 1437 mutex_spin_exit(&sc->sc_intr_lock); 1438 1439 return true; 1440 } 1441 1442 bool 1443 ehci_resume(device_t dv, const pmf_qual_t *qual) 1444 { 1445 ehci_softc_t *sc = device_private(dv); 1446 int i; 1447 uint32_t cmd, hcr; 1448 1449 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1450 1451 /* restore things in case the bios sucks */ 1452 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1453 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1454 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1455 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1456 1457 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1458 1459 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1460 1461 hcr = 0; 1462 for (i = 1; i <= sc->sc_noport; i++) { 1463 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1464 if ((cmd & EHCI_PS_PO) == 0 && 1465 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1466 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1467 hcr = 1; 1468 } 1469 } 1470 1471 if (hcr) { 1472 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1473 1474 for (i = 1; i <= sc->sc_noport; i++) { 1475 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1476 if ((cmd & EHCI_PS_PO) == 0 && 1477 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1478 EOWRITE4(sc, EHCI_PORTSC(i), 1479 cmd & ~EHCI_PS_FPR); 1480 } 1481 } 1482 1483 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1484 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1485 1486 for (i = 0; i < 100; i++) { 1487 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1488 if (hcr != EHCI_STS_HCH) 1489 break; 1490 1491 usb_delay_ms(&sc->sc_bus, 1); 1492 } 1493 if (hcr == EHCI_STS_HCH) 1494 printf("%s: config timeout\n", device_xname(dv)); 1495 1496 return true; 1497 } 1498 1499 /* 1500 * Shut down the controller when the system is going down. 1501 */ 1502 bool 1503 ehci_shutdown(device_t self, int flags) 1504 { 1505 ehci_softc_t *sc = device_private(self); 1506 1507 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1508 1509 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1510 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1511 return true; 1512 } 1513 1514 Static struct usbd_xfer * 1515 ehci_allocx(struct usbd_bus *bus) 1516 { 1517 struct ehci_softc *sc = bus->ub_hcpriv; 1518 struct usbd_xfer *xfer; 1519 1520 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1521 if (xfer != NULL) { 1522 memset(xfer, 0, sizeof(struct ehci_xfer)); 1523 #ifdef DIAGNOSTIC 1524 EXFER(xfer)->ex_isdone = true; 1525 xfer->ux_state = XFER_BUSY; 1526 #endif 1527 } 1528 return xfer; 1529 } 1530 1531 Static void 1532 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1533 { 1534 struct ehci_softc *sc = bus->ub_hcpriv; 1535 1536 KASSERT(xfer->ux_state == XFER_BUSY); 1537 KASSERT(EXFER(xfer)->ex_isdone); 1538 #ifdef DIAGNOSTIC 1539 xfer->ux_state = XFER_FREE; 1540 #endif 1541 pool_cache_put(sc->sc_xferpool, xfer); 1542 } 1543 1544 Static void 1545 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1546 { 1547 struct ehci_softc *sc = bus->ub_hcpriv; 1548 1549 *lock = &sc->sc_lock; 1550 } 1551 1552 Static void 1553 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1554 { 1555 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1556 1557 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1558 1559 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1560 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1561 #ifdef EHCI_DEBUG 1562 if (ehcidebug) 1563 usbd_dump_pipe(pipe); 1564 #endif 1565 epipe->nexttoggle = 0; 1566 } 1567 1568 Static void 1569 ehci_noop(struct usbd_pipe *pipe) 1570 { 1571 } 1572 1573 #ifdef EHCI_DEBUG 1574 /* 1575 * Unused function - this is meant to be called from a kernel 1576 * debugger. 1577 */ 1578 void 1579 ehci_dump(void) 1580 { 1581 ehci_softc_t *sc = theehci; 1582 int i; 1583 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1584 EOREAD4(sc, EHCI_USBCMD), 1585 EOREAD4(sc, EHCI_USBSTS), 1586 EOREAD4(sc, EHCI_USBINTR)); 1587 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1588 EOREAD4(sc, EHCI_FRINDEX), 1589 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1590 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1591 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1592 for (i = 1; i <= sc->sc_noport; i++) 1593 printf("port %d status=0x%08x\n", i, 1594 EOREAD4(sc, EHCI_PORTSC(i))); 1595 } 1596 1597 Static void 1598 ehci_dump_regs(ehci_softc_t *sc) 1599 { 1600 int i; 1601 1602 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1603 1604 USBHIST_LOG(ehcidebug, 1605 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1606 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1607 EOREAD4(sc, EHCI_USBINTR), 0); 1608 USBHIST_LOG(ehcidebug, 1609 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1610 "async = 0x%08x", 1611 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1612 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1613 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1614 for (i = 1; i <= sc->sc_noport; i += 2) { 1615 if (i == sc->sc_noport) { 1616 USBHIST_LOG(ehcidebug, 1617 "port %d status = 0x%08x", i, 1618 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1619 } else { 1620 USBHIST_LOG(ehcidebug, 1621 "port %d status = 0x%08x port %d status = 0x%08x", 1622 i, EOREAD4(sc, EHCI_PORTSC(i)), 1623 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1624 } 1625 } 1626 } 1627 1628 #ifdef EHCI_DEBUG 1629 #define ehci_dump_link(link, type) do { \ 1630 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1631 link, \ 1632 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1633 if (type) { \ 1634 USBHIST_LOG(ehcidebug, \ 1635 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1636 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1637 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1638 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1639 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1640 } \ 1641 } while(0) 1642 #else 1643 #define ehci_dump_link(link, type) 1644 #endif 1645 1646 Static void 1647 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1648 { 1649 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1650 int i; 1651 uint32_t stop = 0; 1652 1653 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1654 ehci_dump_sqtd(sqtd); 1655 usb_syncmem(&sqtd->dma, 1656 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1657 sizeof(sqtd->qtd), 1658 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1659 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1660 usb_syncmem(&sqtd->dma, 1661 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1662 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1663 } 1664 if (!stop) 1665 USBHIST_LOG(ehcidebug, 1666 "dump aborted, too many TDs", 0, 0, 0, 0); 1667 } 1668 1669 Static void 1670 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1671 { 1672 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1673 1674 usb_syncmem(&sqtd->dma, sqtd->offs, 1675 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1676 1677 USBHIST_LOGN(ehcidebug, 10, 1678 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1679 ehci_dump_qtd(&sqtd->qtd); 1680 1681 usb_syncmem(&sqtd->dma, sqtd->offs, 1682 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1683 } 1684 1685 Static void 1686 ehci_dump_qtd(ehci_qtd_t *qtd) 1687 { 1688 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1689 1690 #ifdef USBHIST 1691 uint32_t s = le32toh(qtd->qtd_status); 1692 #endif 1693 1694 USBHIST_LOGN(ehcidebug, 10, 1695 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1696 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1697 USBHIST_LOGN(ehcidebug, 10, 1698 " toggle = %d ioc = %d bytes = %#x " 1699 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1700 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1701 USBHIST_LOGN(ehcidebug, 10, 1702 " cerr = %d pid = %d stat = %x", 1703 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1704 0); 1705 USBHIST_LOGN(ehcidebug, 10, 1706 "active =%d halted=%d buferr=%d babble=%d", 1707 s & EHCI_QTD_ACTIVE ? 1 : 0, 1708 s & EHCI_QTD_HALTED ? 1 : 0, 1709 s & EHCI_QTD_BUFERR ? 1 : 0, 1710 s & EHCI_QTD_BABBLE ? 1 : 0); 1711 USBHIST_LOGN(ehcidebug, 10, 1712 "xacterr=%d missed=%d split =%d ping =%d", 1713 s & EHCI_QTD_XACTERR ? 1 : 0, 1714 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1715 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1716 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1717 USBHIST_LOGN(ehcidebug, 10, 1718 "buffer[0] = %#x buffer[1] = %#x " 1719 "buffer[2] = %#x buffer[3] = %#x", 1720 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1721 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1722 USBHIST_LOGN(ehcidebug, 10, 1723 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1724 } 1725 1726 Static void 1727 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1728 { 1729 #ifdef USBHIST 1730 ehci_qh_t *qh = &sqh->qh; 1731 ehci_link_t link; 1732 #endif 1733 uint32_t endp, endphub; 1734 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1735 1736 usb_syncmem(&sqh->dma, sqh->offs, 1737 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1738 1739 USBHIST_LOGN(ehcidebug, 10, 1740 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1741 link = le32toh(qh->qh_link); 1742 ehci_dump_link(link, true); 1743 1744 endp = le32toh(qh->qh_endp); 1745 USBHIST_LOGN(ehcidebug, 10, 1746 " endp = %#x", endp, 0, 0, 0); 1747 USBHIST_LOGN(ehcidebug, 10, 1748 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1749 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1750 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1751 USBHIST_LOGN(ehcidebug, 10, 1752 " dtc = %d hrecl = %d", 1753 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1754 USBHIST_LOGN(ehcidebug, 10, 1755 " ctl = %d nrl = %d mpl = %#x(%d)", 1756 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1757 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1758 1759 endphub = le32toh(qh->qh_endphub); 1760 USBHIST_LOGN(ehcidebug, 10, 1761 " endphub = %#x", endphub, 0, 0, 0); 1762 USBHIST_LOGN(ehcidebug, 10, 1763 " smask = 0x%02x cmask = 0x%02x", 1764 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1765 USBHIST_LOGN(ehcidebug, 10, 1766 " huba = 0x%02x port = %d mult = %d", 1767 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1768 EHCI_QH_GET_MULT(endphub), 0); 1769 1770 link = le32toh(qh->qh_curqtd); 1771 ehci_dump_link(link, false); 1772 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1773 ehci_dump_qtd(&qh->qh_qtd); 1774 1775 usb_syncmem(&sqh->dma, sqh->offs, 1776 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1777 } 1778 1779 Static void 1780 ehci_dump_itd(struct ehci_soft_itd *itd) 1781 { 1782 ehci_isoc_trans_t t; 1783 ehci_isoc_bufr_ptr_t b, b2, b3; 1784 int i; 1785 1786 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1787 1788 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1789 0, 0); 1790 1791 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1792 t = le32toh(itd->itd.itd_ctl[i]); 1793 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1794 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1795 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1796 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1797 EHCI_ITD_GET_OFFS(t), 0); 1798 } 1799 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1800 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1801 USBHIST_LOG(ehcidebug, " %x", 1802 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1803 1804 b = le32toh(itd->itd.itd_bufr[0]); 1805 b2 = le32toh(itd->itd.itd_bufr[1]); 1806 b3 = le32toh(itd->itd.itd_bufr[2]); 1807 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1808 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1809 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1810 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1811 } 1812 1813 Static void 1814 ehci_dump_sitd(struct ehci_soft_itd *itd) 1815 { 1816 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1817 1818 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1819 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1820 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1821 itd->xfer_next, itd->physaddr, itd->slot, 0); 1822 } 1823 1824 Static void 1825 ehci_dump_exfer(struct ehci_xfer *ex) 1826 { 1827 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1828 1829 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1830 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1831 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1832 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1833 } 1834 #endif 1835 1836 Static usbd_status 1837 ehci_open(struct usbd_pipe *pipe) 1838 { 1839 struct usbd_device *dev = pipe->up_dev; 1840 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1841 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1842 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1843 uint8_t addr = dev->ud_addr; 1844 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1845 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1846 ehci_soft_qh_t *sqh; 1847 usbd_status err; 1848 int ival, speed, naks; 1849 int hshubaddr, hshubport; 1850 1851 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1852 1853 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1854 pipe, addr, ed->bEndpointAddress, rhaddr); 1855 1856 if (dev->ud_myhsport) { 1857 /* 1858 * When directly attached FS/LS device while doing embedded 1859 * transaction translations and we are the hub, set the hub 1860 * address to 0 (us). 1861 */ 1862 if (!(sc->sc_flags & EHCIF_ETTF) 1863 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1864 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1865 } else { 1866 hshubaddr = 0; 1867 } 1868 hshubport = dev->ud_myhsport->up_portno; 1869 } else { 1870 hshubaddr = 0; 1871 hshubport = 0; 1872 } 1873 1874 if (sc->sc_dying) 1875 return USBD_IOERROR; 1876 1877 /* toggle state needed for bulk endpoints */ 1878 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1879 1880 if (addr == rhaddr) { 1881 switch (ed->bEndpointAddress) { 1882 case USB_CONTROL_ENDPOINT: 1883 pipe->up_methods = &roothub_ctrl_methods; 1884 break; 1885 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1886 pipe->up_methods = &ehci_root_intr_methods; 1887 break; 1888 default: 1889 USBHIST_LOG(ehcidebug, 1890 "bad bEndpointAddress 0x%02x", 1891 ed->bEndpointAddress, 0, 0, 0); 1892 return USBD_INVAL; 1893 } 1894 return USBD_NORMAL_COMPLETION; 1895 } 1896 1897 /* XXX All this stuff is only valid for async. */ 1898 switch (dev->ud_speed) { 1899 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1900 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1901 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1902 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1903 } 1904 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1905 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1906 hshubaddr, hshubport, 0, 0); 1907 return USBD_INVAL; 1908 } 1909 1910 /* 1911 * For interrupt transfer, nak throttling must be disabled, but for 1912 * the other transfer type, nak throttling should be enabled from the 1913 * viewpoint that avoids the memory thrashing. 1914 */ 1915 naks = (xfertype == UE_INTERRUPT) ? 0 1916 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1917 1918 /* Allocate sqh for everything, save isoc xfers */ 1919 if (xfertype != UE_ISOCHRONOUS) { 1920 sqh = ehci_alloc_sqh(sc); 1921 if (sqh == NULL) 1922 return USBD_NOMEM; 1923 /* qh_link filled when the QH is added */ 1924 sqh->qh.qh_endp = htole32( 1925 EHCI_QH_SET_ADDR(addr) | 1926 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1927 EHCI_QH_SET_EPS(speed) | 1928 EHCI_QH_DTC | 1929 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1930 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1931 EHCI_QH_CTL : 0) | 1932 EHCI_QH_SET_NRL(naks) 1933 ); 1934 sqh->qh.qh_endphub = htole32( 1935 EHCI_QH_SET_MULT(1) | 1936 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1937 ); 1938 if (speed != EHCI_QH_SPEED_HIGH) 1939 sqh->qh.qh_endphub |= htole32( 1940 EHCI_QH_SET_PORT(hshubport) | 1941 EHCI_QH_SET_HUBA(hshubaddr) | 1942 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1943 ); 1944 sqh->qh.qh_curqtd = EHCI_NULL; 1945 /* Fill the overlay qTD */ 1946 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1947 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1948 sqh->qh.qh_qtd.qtd_status = htole32(0); 1949 1950 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1951 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1952 epipe->sqh = sqh; 1953 } else { 1954 sqh = NULL; 1955 } /*xfertype == UE_ISOC*/ 1956 1957 switch (xfertype) { 1958 case UE_CONTROL: 1959 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1960 0, &epipe->ctrl.reqdma); 1961 #ifdef EHCI_DEBUG 1962 if (err) 1963 printf("ehci_open: usb_allocmem()=%d\n", err); 1964 #endif 1965 if (err) 1966 goto bad; 1967 pipe->up_methods = &ehci_device_ctrl_methods; 1968 mutex_enter(&sc->sc_lock); 1969 ehci_add_qh(sc, sqh, sc->sc_async_head); 1970 mutex_exit(&sc->sc_lock); 1971 break; 1972 case UE_BULK: 1973 pipe->up_methods = &ehci_device_bulk_methods; 1974 mutex_enter(&sc->sc_lock); 1975 ehci_add_qh(sc, sqh, sc->sc_async_head); 1976 mutex_exit(&sc->sc_lock); 1977 break; 1978 case UE_INTERRUPT: 1979 pipe->up_methods = &ehci_device_intr_methods; 1980 ival = pipe->up_interval; 1981 if (ival == USBD_DEFAULT_INTERVAL) { 1982 if (speed == EHCI_QH_SPEED_HIGH) { 1983 if (ed->bInterval > 16) { 1984 /* 1985 * illegal with high-speed, but there 1986 * were documentation bugs in the spec, 1987 * so be generous 1988 */ 1989 ival = 256; 1990 } else 1991 ival = (1 << (ed->bInterval - 1)) / 8; 1992 } else 1993 ival = ed->bInterval; 1994 } 1995 err = ehci_device_setintr(sc, sqh, ival); 1996 if (err) 1997 goto bad; 1998 break; 1999 case UE_ISOCHRONOUS: 2000 if (speed == EHCI_QH_SPEED_HIGH) 2001 pipe->up_methods = &ehci_device_isoc_methods; 2002 else 2003 pipe->up_methods = &ehci_device_fs_isoc_methods; 2004 if (ed->bInterval == 0 || ed->bInterval > 16) { 2005 printf("ehci: opening pipe with invalid bInterval\n"); 2006 err = USBD_INVAL; 2007 goto bad; 2008 } 2009 if (UGETW(ed->wMaxPacketSize) == 0) { 2010 printf("ehci: zero length endpoint open request\n"); 2011 err = USBD_INVAL; 2012 goto bad; 2013 } 2014 epipe->isoc.next_frame = 0; 2015 epipe->isoc.cur_xfers = 0; 2016 break; 2017 default: 2018 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2019 err = USBD_INVAL; 2020 goto bad; 2021 } 2022 return USBD_NORMAL_COMPLETION; 2023 2024 bad: 2025 if (sqh != NULL) 2026 ehci_free_sqh(sc, sqh); 2027 return err; 2028 } 2029 2030 /* 2031 * Add an ED to the schedule. Called with USB lock held. 2032 */ 2033 Static void 2034 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2035 { 2036 2037 KASSERT(mutex_owned(&sc->sc_lock)); 2038 2039 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2040 2041 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2042 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2043 2044 sqh->next = head->next; 2045 sqh->qh.qh_link = head->qh.qh_link; 2046 2047 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2048 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2049 2050 head->next = sqh; 2051 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2052 2053 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2054 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2055 2056 #ifdef EHCI_DEBUG 2057 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2058 ehci_dump_sqh(sqh); 2059 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2060 #endif 2061 } 2062 2063 /* 2064 * Remove an ED from the schedule. Called with USB lock held. 2065 */ 2066 Static void 2067 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2068 { 2069 ehci_soft_qh_t *p; 2070 2071 KASSERT(mutex_owned(&sc->sc_lock)); 2072 2073 /* XXX */ 2074 for (p = head; p != NULL && p->next != sqh; p = p->next) 2075 ; 2076 if (p == NULL) 2077 panic("ehci_rem_qh: ED not found"); 2078 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2079 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2080 p->next = sqh->next; 2081 p->qh.qh_link = sqh->qh.qh_link; 2082 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2083 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2084 2085 ehci_sync_hc(sc); 2086 } 2087 2088 Static void 2089 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2090 { 2091 int i; 2092 uint32_t status; 2093 2094 /* Save toggle bit and ping status. */ 2095 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2096 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2097 status = sqh->qh.qh_qtd.qtd_status & 2098 htole32(EHCI_QTD_TOGGLE_MASK | 2099 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2100 /* Set HALTED to make hw leave it alone. */ 2101 sqh->qh.qh_qtd.qtd_status = 2102 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2103 usb_syncmem(&sqh->dma, 2104 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2105 sizeof(sqh->qh.qh_qtd.qtd_status), 2106 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2107 sqh->qh.qh_curqtd = 0; 2108 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2109 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2110 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2111 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2112 sqh->sqtd = sqtd; 2113 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2114 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2115 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2116 sqh->qh.qh_qtd.qtd_status = status; 2117 usb_syncmem(&sqh->dma, 2118 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2119 sizeof(sqh->qh.qh_qtd.qtd_status), 2120 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2121 } 2122 2123 /* 2124 * Ensure that the HC has released all references to the QH. We do this 2125 * by asking for a Async Advance Doorbell interrupt and then we wait for 2126 * the interrupt. 2127 * To make this easier we first obtain exclusive use of the doorbell. 2128 */ 2129 Static void 2130 ehci_sync_hc(ehci_softc_t *sc) 2131 { 2132 int error __diagused; 2133 2134 KASSERT(mutex_owned(&sc->sc_lock)); 2135 2136 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2137 2138 if (sc->sc_dying) { 2139 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2140 return; 2141 } 2142 /* ask for doorbell */ 2143 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2144 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2145 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2146 2147 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2148 2149 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2150 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2151 #ifdef DIAGNOSTIC 2152 if (error) 2153 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2154 #endif 2155 } 2156 2157 Static void 2158 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2159 { 2160 struct ehci_soft_itd *itd, *prev; 2161 2162 prev = NULL; 2163 2164 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2165 panic("ehci isoc xfer being freed, but with no itd chain"); 2166 2167 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2168 prev = itd->frame_list.prev; 2169 /* Unlink itd from hardware chain, or frame array */ 2170 if (prev == NULL) { /* We're at the table head */ 2171 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2172 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2173 usb_syncmem(&sc->sc_fldma, 2174 sizeof(ehci_link_t) * itd->slot, 2175 sizeof(ehci_link_t), 2176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2177 2178 if (itd->frame_list.next != NULL) 2179 itd->frame_list.next->frame_list.prev = NULL; 2180 } else { 2181 /* XXX this part is untested... */ 2182 prev->itd.itd_next = itd->itd.itd_next; 2183 usb_syncmem(&itd->dma, 2184 itd->offs + offsetof(ehci_itd_t, itd_next), 2185 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2186 2187 prev->frame_list.next = itd->frame_list.next; 2188 if (itd->frame_list.next != NULL) 2189 itd->frame_list.next->frame_list.prev = prev; 2190 } 2191 } 2192 2193 prev = NULL; 2194 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2195 if (prev != NULL) 2196 ehci_free_itd(sc, prev); 2197 prev = itd; 2198 } 2199 if (prev) 2200 ehci_free_itd(sc, prev); 2201 exfer->ex_itdstart = NULL; 2202 exfer->ex_itdend = NULL; 2203 } 2204 2205 Static void 2206 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2207 { 2208 struct ehci_soft_sitd *sitd, *prev; 2209 2210 prev = NULL; 2211 2212 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2213 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2214 2215 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2216 prev = sitd->frame_list.prev; 2217 /* Unlink sitd from hardware chain, or frame array */ 2218 if (prev == NULL) { /* We're at the table head */ 2219 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2220 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2221 usb_syncmem(&sc->sc_fldma, 2222 sizeof(ehci_link_t) * sitd->slot, 2223 sizeof(ehci_link_t), 2224 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2225 2226 if (sitd->frame_list.next != NULL) 2227 sitd->frame_list.next->frame_list.prev = NULL; 2228 } else { 2229 /* XXX this part is untested... */ 2230 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2231 usb_syncmem(&sitd->dma, 2232 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2233 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2234 2235 prev->frame_list.next = sitd->frame_list.next; 2236 if (sitd->frame_list.next != NULL) 2237 sitd->frame_list.next->frame_list.prev = prev; 2238 } 2239 } 2240 2241 prev = NULL; 2242 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2243 if (prev != NULL) 2244 ehci_free_sitd(sc, prev); 2245 prev = sitd; 2246 } 2247 if (prev) 2248 ehci_free_sitd(sc, prev); 2249 exfer->ex_sitdstart = NULL; 2250 exfer->ex_sitdend = NULL; 2251 } 2252 2253 /***********/ 2254 2255 Static int 2256 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2257 void *buf, int buflen) 2258 { 2259 ehci_softc_t *sc = bus->ub_hcpriv; 2260 usb_hub_descriptor_t hubd; 2261 usb_port_status_t ps; 2262 uint16_t len, value, index; 2263 int l, totlen = 0; 2264 int port, i; 2265 uint32_t v; 2266 2267 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2268 2269 if (sc->sc_dying) 2270 return -1; 2271 2272 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2273 req->bmRequestType, req->bRequest, 0, 0); 2274 2275 len = UGETW(req->wLength); 2276 value = UGETW(req->wValue); 2277 index = UGETW(req->wIndex); 2278 2279 #define C(x,y) ((x) | ((y) << 8)) 2280 switch (C(req->bRequest, req->bmRequestType)) { 2281 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2282 if (len == 0) 2283 break; 2284 switch (value) { 2285 case C(0, UDESC_DEVICE): { 2286 usb_device_descriptor_t devd; 2287 totlen = min(buflen, sizeof(devd)); 2288 memcpy(&devd, buf, totlen); 2289 USETW(devd.idVendor, sc->sc_id_vendor); 2290 memcpy(buf, &devd, totlen); 2291 break; 2292 2293 } 2294 #define sd ((usb_string_descriptor_t *)buf) 2295 case C(1, UDESC_STRING): 2296 /* Vendor */ 2297 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2298 break; 2299 case C(2, UDESC_STRING): 2300 /* Product */ 2301 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2302 break; 2303 #undef sd 2304 default: 2305 /* default from usbroothub */ 2306 return buflen; 2307 } 2308 break; 2309 2310 /* Hub requests */ 2311 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2312 break; 2313 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2314 USBHIST_LOG(ehcidebug, 2315 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2316 0, 0); 2317 if (index < 1 || index > sc->sc_noport) { 2318 return -1; 2319 } 2320 port = EHCI_PORTSC(index); 2321 v = EOREAD4(sc, port); 2322 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2323 v &= ~EHCI_PS_CLEAR; 2324 switch (value) { 2325 case UHF_PORT_ENABLE: 2326 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2327 break; 2328 case UHF_PORT_SUSPEND: 2329 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2330 break; 2331 v &= ~EHCI_PS_SUSP; 2332 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2333 /* see USB2 spec ch. 7.1.7.7 */ 2334 usb_delay_ms(&sc->sc_bus, 20); 2335 EOWRITE4(sc, port, v); 2336 usb_delay_ms(&sc->sc_bus, 2); 2337 #ifdef DEBUG 2338 v = EOREAD4(sc, port); 2339 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2340 printf("ehci: resume failed: %x\n", v); 2341 #endif 2342 break; 2343 case UHF_PORT_POWER: 2344 if (sc->sc_hasppc) 2345 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2346 break; 2347 case UHF_PORT_TEST: 2348 USBHIST_LOG(ehcidebug, "clear port test " 2349 "%d", index, 0, 0, 0); 2350 break; 2351 case UHF_PORT_INDICATOR: 2352 USBHIST_LOG(ehcidebug, "clear port ind " 2353 "%d", index, 0, 0, 0); 2354 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2355 break; 2356 case UHF_C_PORT_CONNECTION: 2357 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2358 break; 2359 case UHF_C_PORT_ENABLE: 2360 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2361 break; 2362 case UHF_C_PORT_SUSPEND: 2363 /* how? */ 2364 break; 2365 case UHF_C_PORT_OVER_CURRENT: 2366 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2367 break; 2368 case UHF_C_PORT_RESET: 2369 sc->sc_isreset[index] = 0; 2370 break; 2371 default: 2372 return -1; 2373 } 2374 #if 0 2375 switch(value) { 2376 case UHF_C_PORT_CONNECTION: 2377 case UHF_C_PORT_ENABLE: 2378 case UHF_C_PORT_SUSPEND: 2379 case UHF_C_PORT_OVER_CURRENT: 2380 case UHF_C_PORT_RESET: 2381 default: 2382 break; 2383 } 2384 #endif 2385 break; 2386 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2387 if (len == 0) 2388 break; 2389 if ((value & 0xff) != 0) { 2390 return -1; 2391 } 2392 totlen = min(buflen, sizeof(hubd)); 2393 memcpy(&hubd, buf, totlen); 2394 hubd.bNbrPorts = sc->sc_noport; 2395 v = EOREAD4(sc, EHCI_HCSPARAMS); 2396 USETW(hubd.wHubCharacteristics, 2397 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2398 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2399 ? UHD_PORT_IND : 0); 2400 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2401 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2402 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2403 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2404 totlen = min(totlen, hubd.bDescLength); 2405 memcpy(buf, &hubd, totlen); 2406 break; 2407 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2408 if (len != 4) { 2409 return -1; 2410 } 2411 memset(buf, 0, len); /* ? XXX */ 2412 totlen = len; 2413 break; 2414 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2415 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2416 if (index < 1 || index > sc->sc_noport) { 2417 return -1; 2418 } 2419 if (len != 4) { 2420 return -1; 2421 } 2422 v = EOREAD4(sc, EHCI_PORTSC(index)); 2423 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2424 2425 i = UPS_HIGH_SPEED; 2426 if (sc->sc_flags & EHCIF_ETTF) { 2427 /* 2428 * If we are doing embedded transaction translation, 2429 * then directly attached LS/FS devices are reset by 2430 * the EHCI controller itself. PSPD is encoded 2431 * the same way as in USBSTATUS. 2432 */ 2433 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2434 } 2435 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2436 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2437 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2438 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2439 if (v & EHCI_PS_PR) i |= UPS_RESET; 2440 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2441 if (sc->sc_vendor_port_status) 2442 i = sc->sc_vendor_port_status(sc, v, i); 2443 USETW(ps.wPortStatus, i); 2444 i = 0; 2445 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2446 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2447 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2448 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2449 USETW(ps.wPortChange, i); 2450 totlen = min(len, sizeof(ps)); 2451 memcpy(buf, &ps, totlen); 2452 break; 2453 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2454 return -1; 2455 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2456 break; 2457 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2458 if (index < 1 || index > sc->sc_noport) { 2459 return -1; 2460 } 2461 port = EHCI_PORTSC(index); 2462 v = EOREAD4(sc, port); 2463 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2464 v &= ~EHCI_PS_CLEAR; 2465 switch(value) { 2466 case UHF_PORT_ENABLE: 2467 EOWRITE4(sc, port, v | EHCI_PS_PE); 2468 break; 2469 case UHF_PORT_SUSPEND: 2470 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2471 break; 2472 case UHF_PORT_RESET: 2473 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2474 if (EHCI_PS_IS_LOWSPEED(v) 2475 && sc->sc_ncomp > 0 2476 && !(sc->sc_flags & EHCIF_ETTF)) { 2477 /* 2478 * Low speed device on non-ETTF controller or 2479 * unaccompanied controller, give up ownership. 2480 */ 2481 ehci_disown(sc, index, 1); 2482 break; 2483 } 2484 /* Start reset sequence. */ 2485 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2486 EOWRITE4(sc, port, v | EHCI_PS_PR); 2487 /* Wait for reset to complete. */ 2488 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2489 if (sc->sc_dying) { 2490 return -1; 2491 } 2492 /* 2493 * An embedded transaction translator will automatically 2494 * terminate the reset sequence so there's no need to 2495 * it. 2496 */ 2497 v = EOREAD4(sc, port); 2498 if (v & EHCI_PS_PR) { 2499 /* Terminate reset sequence. */ 2500 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2501 /* Wait for HC to complete reset. */ 2502 usb_delay_ms(&sc->sc_bus, 2503 EHCI_PORT_RESET_COMPLETE); 2504 if (sc->sc_dying) { 2505 return -1; 2506 } 2507 } 2508 2509 v = EOREAD4(sc, port); 2510 USBHIST_LOG(ehcidebug, 2511 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2512 if (v & EHCI_PS_PR) { 2513 printf("%s: port reset timeout\n", 2514 device_xname(sc->sc_dev)); 2515 return USBD_TIMEOUT; 2516 } 2517 if (!(v & EHCI_PS_PE)) { 2518 /* Not a high speed device, give up ownership.*/ 2519 ehci_disown(sc, index, 0); 2520 break; 2521 } 2522 sc->sc_isreset[index] = 1; 2523 USBHIST_LOG(ehcidebug, 2524 "ehci port %d reset, status = 0x%08x", index, v, 0, 2525 0); 2526 break; 2527 case UHF_PORT_POWER: 2528 USBHIST_LOG(ehcidebug, 2529 "set port power %d (has PPC = %d)", index, 2530 sc->sc_hasppc, 0, 0); 2531 if (sc->sc_hasppc) 2532 EOWRITE4(sc, port, v | EHCI_PS_PP); 2533 break; 2534 case UHF_PORT_TEST: 2535 USBHIST_LOG(ehcidebug, "set port test %d", 2536 index, 0, 0, 0); 2537 break; 2538 case UHF_PORT_INDICATOR: 2539 USBHIST_LOG(ehcidebug, "set port ind %d", 2540 index, 0, 0, 0); 2541 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2542 break; 2543 default: 2544 return -1; 2545 } 2546 break; 2547 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2548 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2549 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2550 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2551 break; 2552 default: 2553 /* default from usbroothub */ 2554 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2555 buflen, 0, 0, 0); 2556 2557 return buflen; 2558 } 2559 2560 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2561 2562 return totlen; 2563 } 2564 2565 Static void 2566 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2567 { 2568 int port; 2569 uint32_t v; 2570 2571 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2572 2573 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2574 #ifdef DIAGNOSTIC 2575 if (sc->sc_npcomp != 0) { 2576 int i = (index-1) / sc->sc_npcomp; 2577 if (i >= sc->sc_ncomp) 2578 printf("%s: strange port\n", 2579 device_xname(sc->sc_dev)); 2580 else 2581 printf("%s: handing over %s speed device on " 2582 "port %d to %s\n", 2583 device_xname(sc->sc_dev), 2584 lowspeed ? "low" : "full", 2585 index, device_xname(sc->sc_comps[i])); 2586 } else { 2587 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2588 } 2589 #endif 2590 port = EHCI_PORTSC(index); 2591 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2592 EOWRITE4(sc, port, v | EHCI_PS_PO); 2593 } 2594 2595 Static usbd_status 2596 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2597 { 2598 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2599 usbd_status err; 2600 2601 /* Insert last in queue. */ 2602 mutex_enter(&sc->sc_lock); 2603 err = usb_insert_transfer(xfer); 2604 mutex_exit(&sc->sc_lock); 2605 if (err) 2606 return err; 2607 2608 /* Pipe isn't running, start first */ 2609 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2610 } 2611 2612 Static usbd_status 2613 ehci_root_intr_start(struct usbd_xfer *xfer) 2614 { 2615 struct usbd_pipe *pipe = xfer->ux_pipe; 2616 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2617 2618 if (sc->sc_dying) 2619 return USBD_IOERROR; 2620 2621 mutex_enter(&sc->sc_lock); 2622 sc->sc_intrxfer = xfer; 2623 mutex_exit(&sc->sc_lock); 2624 2625 return USBD_IN_PROGRESS; 2626 } 2627 2628 /* Abort a root interrupt request. */ 2629 Static void 2630 ehci_root_intr_abort(struct usbd_xfer *xfer) 2631 { 2632 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2633 2634 KASSERT(mutex_owned(&sc->sc_lock)); 2635 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2636 2637 sc->sc_intrxfer = NULL; 2638 2639 xfer->ux_status = USBD_CANCELLED; 2640 usb_transfer_complete(xfer); 2641 } 2642 2643 /* Close the root pipe. */ 2644 Static void 2645 ehci_root_intr_close(struct usbd_pipe *pipe) 2646 { 2647 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2648 2649 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2650 2651 KASSERT(mutex_owned(&sc->sc_lock)); 2652 2653 sc->sc_intrxfer = NULL; 2654 } 2655 2656 Static void 2657 ehci_root_intr_done(struct usbd_xfer *xfer) 2658 { 2659 xfer->ux_hcpriv = NULL; 2660 } 2661 2662 /************************/ 2663 2664 Static ehci_soft_qh_t * 2665 ehci_alloc_sqh(ehci_softc_t *sc) 2666 { 2667 ehci_soft_qh_t *sqh; 2668 usbd_status err; 2669 int i, offs; 2670 usb_dma_t dma; 2671 2672 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2673 2674 if (sc->sc_freeqhs == NULL) { 2675 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2676 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2677 EHCI_PAGE_SIZE, &dma); 2678 #ifdef EHCI_DEBUG 2679 if (err) 2680 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2681 #endif 2682 if (err) 2683 return NULL; 2684 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2685 offs = i * EHCI_SQH_SIZE; 2686 sqh = KERNADDR(&dma, offs); 2687 sqh->physaddr = DMAADDR(&dma, offs); 2688 sqh->dma = dma; 2689 sqh->offs = offs; 2690 sqh->next = sc->sc_freeqhs; 2691 sc->sc_freeqhs = sqh; 2692 } 2693 } 2694 sqh = sc->sc_freeqhs; 2695 sc->sc_freeqhs = sqh->next; 2696 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2697 sqh->next = NULL; 2698 return sqh; 2699 } 2700 2701 Static void 2702 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2703 { 2704 sqh->next = sc->sc_freeqhs; 2705 sc->sc_freeqhs = sqh; 2706 } 2707 2708 Static ehci_soft_qtd_t * 2709 ehci_alloc_sqtd(ehci_softc_t *sc) 2710 { 2711 ehci_soft_qtd_t *sqtd = NULL; 2712 usbd_status err; 2713 int i, offs; 2714 usb_dma_t dma; 2715 2716 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2717 2718 if (sc->sc_freeqtds == NULL) { 2719 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2720 2721 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2722 EHCI_PAGE_SIZE, &dma); 2723 #ifdef EHCI_DEBUG 2724 if (err) 2725 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2726 #endif 2727 if (err) 2728 goto done; 2729 2730 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2731 offs = i * EHCI_SQTD_SIZE; 2732 sqtd = KERNADDR(&dma, offs); 2733 sqtd->physaddr = DMAADDR(&dma, offs); 2734 sqtd->dma = dma; 2735 sqtd->offs = offs; 2736 2737 sqtd->nextqtd = sc->sc_freeqtds; 2738 sc->sc_freeqtds = sqtd; 2739 } 2740 } 2741 2742 sqtd = sc->sc_freeqtds; 2743 sc->sc_freeqtds = sqtd->nextqtd; 2744 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2745 sqtd->nextqtd = NULL; 2746 sqtd->xfer = NULL; 2747 2748 done: 2749 return sqtd; 2750 } 2751 2752 Static void 2753 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2754 { 2755 2756 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2757 2758 sqtd->nextqtd = sc->sc_freeqtds; 2759 sc->sc_freeqtds = sqtd; 2760 } 2761 2762 Static usbd_status 2763 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2764 int alen, int rd, struct usbd_xfer *xfer, 2765 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2766 { 2767 ehci_soft_qtd_t *next, *cur; 2768 ehci_physaddr_t nextphys; 2769 uint32_t qtdstatus; 2770 int len, curlen, mps; 2771 int i, tog; 2772 int pages, pageoffs; 2773 size_t curoffs; 2774 vaddr_t va, va_offs; 2775 usb_dma_t *dma = &xfer->ux_dmabuf; 2776 uint16_t flags = xfer->ux_flags; 2777 paddr_t a; 2778 2779 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2780 2781 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2782 2783 len = alen; 2784 qtdstatus = EHCI_QTD_ACTIVE | 2785 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2786 EHCI_QTD_SET_CERR(3) 2787 /* IOC set below */ 2788 /* BYTES set below */ 2789 ; 2790 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2791 tog = epipe->nexttoggle; 2792 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2793 2794 cur = ehci_alloc_sqtd(sc); 2795 *sp = cur; 2796 if (cur == NULL) 2797 goto nomem; 2798 2799 usb_syncmem(dma, 0, alen, 2800 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2801 curoffs = 0; 2802 for (;;) { 2803 /* The EHCI hardware can handle at most 5 pages. */ 2804 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2805 va_offs = EHCI_PAGE_OFFSET(va_offs); 2806 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2807 /* we can handle it in this QTD */ 2808 curlen = len - curoffs; 2809 } else { 2810 /* must use multiple TDs, fill as much as possible. */ 2811 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2812 2813 /* the length must be a multiple of the max size */ 2814 curlen -= curlen % mps; 2815 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2816 "curlen=%d", curlen, 0, 0, 0); 2817 KASSERT(curlen != 0); 2818 } 2819 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2820 len, curlen, curoffs, 0); 2821 2822 /* 2823 * Allocate another transfer if there's more data left, 2824 * or if force last short transfer flag is set and we're 2825 * allocating a multiple of the max packet size. 2826 */ 2827 2828 if (curoffs + curlen != len || 2829 ((curlen % mps) == 0 && !rd && curlen != 0 && 2830 (flags & USBD_FORCE_SHORT_XFER))) { 2831 next = ehci_alloc_sqtd(sc); 2832 if (next == NULL) 2833 goto nomem; 2834 nextphys = htole32(next->physaddr); 2835 } else { 2836 next = NULL; 2837 nextphys = EHCI_NULL; 2838 } 2839 2840 /* Find number of pages we'll be using, insert dma addresses */ 2841 pages = EHCI_NPAGES(curlen); 2842 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2843 pageoffs = EHCI_PAGE(curoffs); 2844 for (i = 0; i < pages; i++) { 2845 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2846 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2847 /* Cast up to avoid compiler warnings */ 2848 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2849 } 2850 2851 /* First buffer pointer requires a page offset to start at */ 2852 va = (vaddr_t)KERNADDR(dma, curoffs); 2853 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2854 2855 cur->nextqtd = next; 2856 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2857 cur->qtd.qtd_status = 2858 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2859 cur->xfer = xfer; 2860 cur->len = curlen; 2861 2862 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2863 curoffs, curoffs + curlen, 0, 0); 2864 2865 /* 2866 * adjust the toggle based on the number of packets in this 2867 * qtd 2868 */ 2869 if (((curlen + mps - 1) / mps) & 1) { 2870 tog ^= 1; 2871 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2872 } 2873 if (next == NULL) 2874 break; 2875 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2876 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2877 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2878 if (len) 2879 curoffs += curlen; 2880 cur = next; 2881 } 2882 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2883 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2885 *ep = cur; 2886 epipe->nexttoggle = tog; 2887 2888 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2889 *sp, *ep, 0, 0); 2890 2891 return USBD_NORMAL_COMPLETION; 2892 2893 nomem: 2894 /* XXX free chain */ 2895 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2896 return USBD_NOMEM; 2897 } 2898 2899 Static void 2900 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2901 ehci_soft_qtd_t *sqtdend) 2902 { 2903 ehci_soft_qtd_t *p; 2904 int i; 2905 2906 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2907 2908 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2909 sqtd, sqtdend, 0, 0); 2910 2911 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2912 p = sqtd->nextqtd; 2913 ehci_free_sqtd(sc, sqtd); 2914 } 2915 } 2916 2917 Static ehci_soft_itd_t * 2918 ehci_alloc_itd(ehci_softc_t *sc) 2919 { 2920 struct ehci_soft_itd *itd, *freeitd; 2921 usbd_status err; 2922 int i, offs, frindex, previndex; 2923 usb_dma_t dma; 2924 2925 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2926 2927 mutex_enter(&sc->sc_lock); 2928 2929 /* 2930 * Find an itd that wasn't freed this frame or last frame. This can 2931 * discard itds that were freed before frindex wrapped around 2932 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2933 * interrupt and fiddling with list when that happens 2934 */ 2935 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2936 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2937 2938 freeitd = NULL; 2939 LIST_FOREACH(itd, &sc->sc_freeitds, free_list) { 2940 if (itd == NULL) 2941 break; 2942 if (itd->slot != frindex && itd->slot != previndex) { 2943 freeitd = itd; 2944 break; 2945 } 2946 } 2947 2948 if (freeitd == NULL) { 2949 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2950 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2951 EHCI_PAGE_SIZE, &dma); 2952 2953 if (err) { 2954 USBHIST_LOG(ehcidebug, 2955 "alloc returned %d", err, 0, 0, 0); 2956 mutex_exit(&sc->sc_lock); 2957 return NULL; 2958 } 2959 2960 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2961 offs = i * EHCI_ITD_SIZE; 2962 itd = KERNADDR(&dma, offs); 2963 itd->physaddr = DMAADDR(&dma, offs); 2964 itd->dma = dma; 2965 itd->offs = offs; 2966 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 2967 } 2968 freeitd = LIST_FIRST(&sc->sc_freeitds); 2969 } 2970 2971 itd = freeitd; 2972 LIST_REMOVE(itd, free_list); 2973 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2974 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2975 sizeof(itd->itd.itd_next), 2976 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2977 2978 itd->frame_list.next = NULL; 2979 itd->frame_list.prev = NULL; 2980 itd->xfer_next = NULL; 2981 itd->slot = 0; 2982 2983 mutex_exit(&sc->sc_lock); 2984 2985 return itd; 2986 } 2987 2988 Static ehci_soft_sitd_t * 2989 ehci_alloc_sitd(ehci_softc_t *sc) 2990 { 2991 struct ehci_soft_sitd *sitd, *freesitd; 2992 usbd_status err; 2993 int i, offs, frindex, previndex; 2994 usb_dma_t dma; 2995 2996 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2997 2998 mutex_enter(&sc->sc_lock); 2999 3000 /* 3001 * Find an sitd that wasn't freed this frame or last frame. This can 3002 * discard sitds that were freed before frindex wrapped around 3003 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3004 * interrupt and fiddling with list when that happens 3005 */ 3006 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3007 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3008 3009 freesitd = NULL; 3010 LIST_FOREACH(sitd, &sc->sc_freesitds, free_list) { 3011 if (sitd == NULL) 3012 break; 3013 if (sitd->slot != frindex && sitd->slot != previndex) { 3014 freesitd = sitd; 3015 break; 3016 } 3017 } 3018 3019 if (freesitd == NULL) { 3020 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3021 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3022 EHCI_PAGE_SIZE, &dma); 3023 3024 if (err) { 3025 USBHIST_LOG(ehcidebug, 3026 "alloc returned %d", err, 0, 0, 0); 3027 mutex_exit(&sc->sc_lock); 3028 return NULL; 3029 } 3030 3031 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3032 offs = i * EHCI_SITD_SIZE; 3033 sitd = KERNADDR(&dma, offs); 3034 sitd->physaddr = DMAADDR(&dma, offs); 3035 sitd->dma = dma; 3036 sitd->offs = offs; 3037 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3038 } 3039 freesitd = LIST_FIRST(&sc->sc_freesitds); 3040 } 3041 3042 sitd = freesitd; 3043 LIST_REMOVE(sitd, free_list); 3044 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3045 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3046 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3047 BUS_DMASYNC_PREREAD); 3048 3049 sitd->frame_list.next = NULL; 3050 sitd->frame_list.prev = NULL; 3051 sitd->xfer_next = NULL; 3052 sitd->slot = 0; 3053 3054 mutex_exit(&sc->sc_lock); 3055 3056 return sitd; 3057 } 3058 3059 Static void 3060 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3061 { 3062 3063 KASSERT(mutex_owned(&sc->sc_lock)); 3064 3065 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3066 } 3067 3068 Static void 3069 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3070 { 3071 3072 KASSERT(mutex_owned(&sc->sc_lock)); 3073 3074 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3075 } 3076 3077 /****************/ 3078 3079 /* 3080 * Close a reqular pipe. 3081 * Assumes that there are no pending transactions. 3082 */ 3083 Static void 3084 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3085 { 3086 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3087 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3088 ehci_soft_qh_t *sqh = epipe->sqh; 3089 3090 KASSERT(mutex_owned(&sc->sc_lock)); 3091 3092 ehci_rem_qh(sc, sqh, head); 3093 ehci_free_sqh(sc, epipe->sqh); 3094 } 3095 3096 /* 3097 * Abort a device request. 3098 * If this routine is called at splusb() it guarantees that the request 3099 * will be removed from the hardware scheduling and that the callback 3100 * for it will be called with USBD_CANCELLED status. 3101 * It's impossible to guarantee that the requested transfer will not 3102 * have happened since the hardware runs concurrently. 3103 * If the transaction has already happened we rely on the ordinary 3104 * interrupt processing to process it. 3105 * XXX This is most probably wrong. 3106 * XXXMRG this doesn't make sense anymore. 3107 */ 3108 Static void 3109 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3110 { 3111 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3112 struct ehci_xfer *exfer = EXFER(xfer); 3113 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3114 ehci_soft_qh_t *sqh = epipe->sqh; 3115 ehci_soft_qtd_t *sqtd; 3116 ehci_physaddr_t cur; 3117 uint32_t qhstatus; 3118 int hit; 3119 int wake; 3120 3121 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3122 3123 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3124 3125 KASSERT(mutex_owned(&sc->sc_lock)); 3126 ASSERT_SLEEPABLE(); 3127 3128 if (sc->sc_dying) { 3129 /* If we're dying, just do the software part. */ 3130 xfer->ux_status = status; /* make software ignore it */ 3131 callout_stop(&xfer->ux_callout); 3132 usb_transfer_complete(xfer); 3133 return; 3134 } 3135 3136 /* 3137 * If an abort is already in progress then just wait for it to 3138 * complete and return. 3139 */ 3140 if (xfer->ux_hcflags & UXFER_ABORTING) { 3141 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3142 #ifdef DIAGNOSTIC 3143 if (status == USBD_TIMEOUT) 3144 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3145 #endif 3146 /* Override the status which might be USBD_TIMEOUT. */ 3147 xfer->ux_status = status; 3148 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3149 0, 0, 0, 0); 3150 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3151 while (xfer->ux_hcflags & UXFER_ABORTING) 3152 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3153 return; 3154 } 3155 xfer->ux_hcflags |= UXFER_ABORTING; 3156 3157 /* 3158 * Step 1: Make interrupt routine and hardware ignore xfer. 3159 */ 3160 xfer->ux_status = status; /* make software ignore it */ 3161 callout_stop(&xfer->ux_callout); 3162 3163 usb_syncmem(&sqh->dma, 3164 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3165 sizeof(sqh->qh.qh_qtd.qtd_status), 3166 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3167 qhstatus = sqh->qh.qh_qtd.qtd_status; 3168 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3169 usb_syncmem(&sqh->dma, 3170 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3171 sizeof(sqh->qh.qh_qtd.qtd_status), 3172 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3173 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3174 usb_syncmem(&sqtd->dma, 3175 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3176 sizeof(sqtd->qtd.qtd_status), 3177 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3178 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3179 usb_syncmem(&sqtd->dma, 3180 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3181 sizeof(sqtd->qtd.qtd_status), 3182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3183 if (sqtd == exfer->ex_sqtdend) 3184 break; 3185 } 3186 3187 /* 3188 * Step 2: Wait until we know hardware has finished any possible 3189 * use of the xfer. Also make sure the soft interrupt routine 3190 * has run. 3191 */ 3192 ehci_sync_hc(sc); 3193 sc->sc_softwake = 1; 3194 usb_schedsoftintr(&sc->sc_bus); 3195 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3196 3197 /* 3198 * Step 3: Remove any vestiges of the xfer from the hardware. 3199 * The complication here is that the hardware may have executed 3200 * beyond the xfer we're trying to abort. So as we're scanning 3201 * the TDs of this xfer we check if the hardware points to 3202 * any of them. 3203 */ 3204 3205 usb_syncmem(&sqh->dma, 3206 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3207 sizeof(sqh->qh.qh_curqtd), 3208 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3209 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3210 hit = 0; 3211 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3212 hit |= cur == sqtd->physaddr; 3213 if (sqtd == exfer->ex_sqtdend) 3214 break; 3215 } 3216 sqtd = sqtd->nextqtd; 3217 /* Zap curqtd register if hardware pointed inside the xfer. */ 3218 if (hit && sqtd != NULL) { 3219 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3220 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3221 usb_syncmem(&sqh->dma, 3222 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3223 sizeof(sqh->qh.qh_curqtd), 3224 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3225 sqh->qh.qh_qtd.qtd_status = qhstatus; 3226 usb_syncmem(&sqh->dma, 3227 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3228 sizeof(sqh->qh.qh_qtd.qtd_status), 3229 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3230 } else { 3231 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3232 usb_syncmem(&sqh->dma, 3233 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3234 sizeof(sqh->qh.qh_curqtd), 3235 BUS_DMASYNC_PREREAD); 3236 } 3237 3238 /* 3239 * Step 4: Execute callback. 3240 */ 3241 #ifdef DIAGNOSTIC 3242 exfer->ex_isdone = true; 3243 #endif 3244 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3245 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3246 usb_transfer_complete(xfer); 3247 if (wake) { 3248 cv_broadcast(&xfer->ux_hccv); 3249 } 3250 3251 KASSERT(mutex_owned(&sc->sc_lock)); 3252 } 3253 3254 Static void 3255 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3256 { 3257 ehci_isoc_trans_t trans_status; 3258 struct ehci_pipe *epipe; 3259 struct ehci_xfer *exfer; 3260 ehci_softc_t *sc; 3261 struct ehci_soft_itd *itd; 3262 struct ehci_soft_sitd *sitd; 3263 int i, wake; 3264 3265 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3266 3267 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3268 exfer = EXFER(xfer); 3269 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3270 3271 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3272 3273 KASSERT(mutex_owned(&sc->sc_lock)); 3274 3275 if (sc->sc_dying) { 3276 xfer->ux_status = status; 3277 callout_stop(&xfer->ux_callout); 3278 usb_transfer_complete(xfer); 3279 return; 3280 } 3281 3282 if (xfer->ux_hcflags & UXFER_ABORTING) { 3283 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3284 3285 #ifdef DIAGNOSTIC 3286 if (status == USBD_TIMEOUT) 3287 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3288 #endif 3289 3290 xfer->ux_status = status; 3291 USBHIST_LOG(ehcidebug, 3292 "waiting for abort to finish", 0, 0, 0, 0); 3293 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3294 while (xfer->ux_hcflags & UXFER_ABORTING) 3295 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3296 goto done; 3297 } 3298 xfer->ux_hcflags |= UXFER_ABORTING; 3299 3300 xfer->ux_status = status; 3301 callout_stop(&xfer->ux_callout); 3302 3303 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3304 for (itd = exfer->ex_itdstart; itd != NULL; 3305 itd = itd->xfer_next) { 3306 usb_syncmem(&itd->dma, 3307 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3308 sizeof(itd->itd.itd_ctl), 3309 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3310 3311 for (i = 0; i < 8; i++) { 3312 trans_status = le32toh(itd->itd.itd_ctl[i]); 3313 trans_status &= ~EHCI_ITD_ACTIVE; 3314 itd->itd.itd_ctl[i] = htole32(trans_status); 3315 } 3316 3317 usb_syncmem(&itd->dma, 3318 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3319 sizeof(itd->itd.itd_ctl), 3320 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3321 } 3322 } else { 3323 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3324 sitd = sitd->xfer_next) { 3325 usb_syncmem(&sitd->dma, 3326 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3327 sizeof(sitd->sitd.sitd_buffer), 3328 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3329 3330 trans_status = le32toh(sitd->sitd.sitd_trans); 3331 trans_status &= ~EHCI_SITD_ACTIVE; 3332 sitd->sitd.sitd_trans = htole32(trans_status); 3333 3334 usb_syncmem(&sitd->dma, 3335 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3336 sizeof(sitd->sitd.sitd_buffer), 3337 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3338 } 3339 } 3340 3341 sc->sc_softwake = 1; 3342 usb_schedsoftintr(&sc->sc_bus); 3343 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3344 3345 #ifdef DIAGNOSTIC 3346 exfer->ex_isdone = true; 3347 #endif 3348 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3349 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3350 usb_transfer_complete(xfer); 3351 if (wake) { 3352 cv_broadcast(&xfer->ux_hccv); 3353 } 3354 3355 done: 3356 KASSERT(mutex_owned(&sc->sc_lock)); 3357 return; 3358 } 3359 3360 Static void 3361 ehci_timeout(void *addr) 3362 { 3363 struct ehci_xfer *exfer = addr; 3364 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3365 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3366 3367 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3368 3369 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3370 #ifdef EHCI_DEBUG 3371 if (ehcidebug > 1) 3372 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3373 #endif 3374 3375 if (sc->sc_dying) { 3376 mutex_enter(&sc->sc_lock); 3377 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3378 mutex_exit(&sc->sc_lock); 3379 return; 3380 } 3381 3382 /* Execute the abort in a process context. */ 3383 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3384 USB_TASKQ_MPSAFE); 3385 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3386 USB_TASKQ_HC); 3387 } 3388 3389 Static void 3390 ehci_timeout_task(void *addr) 3391 { 3392 struct usbd_xfer *xfer = addr; 3393 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3394 3395 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3396 3397 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3398 3399 mutex_enter(&sc->sc_lock); 3400 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3401 mutex_exit(&sc->sc_lock); 3402 } 3403 3404 /************************/ 3405 3406 Static usbd_status 3407 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3408 { 3409 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3410 usbd_status err; 3411 3412 /* Insert last in queue. */ 3413 mutex_enter(&sc->sc_lock); 3414 err = usb_insert_transfer(xfer); 3415 mutex_exit(&sc->sc_lock); 3416 if (err) 3417 return err; 3418 3419 /* Pipe isn't running, start first */ 3420 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3421 } 3422 3423 Static usbd_status 3424 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3425 { 3426 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3427 usbd_status err; 3428 3429 if (sc->sc_dying) 3430 return USBD_IOERROR; 3431 3432 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3433 3434 err = ehci_device_request(xfer); 3435 if (err) { 3436 return err; 3437 } 3438 3439 if (sc->sc_bus.ub_usepolling) 3440 ehci_waitintr(sc, xfer); 3441 3442 return USBD_IN_PROGRESS; 3443 } 3444 3445 Static void 3446 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3447 { 3448 struct ehci_xfer *ex = EXFER(xfer); 3449 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3450 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3451 usb_device_request_t *req = &xfer->ux_request; 3452 int len = UGETW(req->wLength); 3453 int rd = req->bmRequestType & UT_READ; 3454 3455 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3456 3457 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3458 3459 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3460 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3461 3462 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3463 ehci_del_intr_list(sc, ex); /* remove from active list */ 3464 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3465 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3466 BUS_DMASYNC_POSTWRITE); 3467 if (len) 3468 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3469 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3470 } 3471 3472 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3473 } 3474 3475 /* Abort a device control request. */ 3476 Static void 3477 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3478 { 3479 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3480 3481 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3482 ehci_abort_xfer(xfer, USBD_CANCELLED); 3483 } 3484 3485 /* Close a device control pipe. */ 3486 Static void 3487 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3488 { 3489 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3490 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3491 3492 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3493 3494 KASSERT(mutex_owned(&sc->sc_lock)); 3495 3496 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3497 3498 ehci_close_pipe(pipe, sc->sc_async_head); 3499 } 3500 3501 Static usbd_status 3502 ehci_device_request(struct usbd_xfer *xfer) 3503 { 3504 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3505 struct ehci_xfer *exfer = EXFER(xfer); 3506 usb_device_request_t *req = &xfer->ux_request; 3507 struct usbd_device *dev = epipe->pipe.up_dev; 3508 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3509 ehci_soft_qtd_t *setup, *stat, *next; 3510 ehci_soft_qh_t *sqh; 3511 int isread; 3512 int len; 3513 usbd_status err; 3514 3515 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3516 3517 isread = req->bmRequestType & UT_READ; 3518 len = UGETW(req->wLength); 3519 3520 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3521 "wValue=0x%04x, wIndex=0x%04x", 3522 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3523 UGETW(req->wIndex)); 3524 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3525 len, dev->ud_addr, 3526 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3527 3528 setup = ehci_alloc_sqtd(sc); 3529 if (setup == NULL) { 3530 err = USBD_NOMEM; 3531 goto bad1; 3532 } 3533 stat = ehci_alloc_sqtd(sc); 3534 if (stat == NULL) { 3535 err = USBD_NOMEM; 3536 goto bad2; 3537 } 3538 3539 mutex_enter(&sc->sc_lock); 3540 3541 sqh = epipe->sqh; 3542 3543 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3544 "address QH %" __PRIuBIT " pipe %d\n", 3545 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3546 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3547 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3548 "MPS QH %" __PRIuBIT " pipe %d\n", 3549 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3550 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3551 3552 /* Set up data transaction */ 3553 if (len != 0) { 3554 ehci_soft_qtd_t *end; 3555 3556 /* Start toggle at 1. */ 3557 epipe->nexttoggle = 1; 3558 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3559 &next, &end); 3560 if (err) 3561 goto bad3; 3562 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3563 end->nextqtd = stat; 3564 end->qtd.qtd_next = end->qtd.qtd_altnext = 3565 htole32(stat->physaddr); 3566 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3567 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3568 } else { 3569 next = stat; 3570 } 3571 3572 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3573 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3574 3575 /* Clear toggle */ 3576 setup->qtd.qtd_status = htole32( 3577 EHCI_QTD_ACTIVE | 3578 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3579 EHCI_QTD_SET_CERR(3) | 3580 EHCI_QTD_SET_TOGGLE(0) | 3581 EHCI_QTD_SET_BYTES(sizeof(*req)) 3582 ); 3583 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3584 setup->qtd.qtd_buffer_hi[0] = 0; 3585 setup->nextqtd = next; 3586 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3587 setup->xfer = xfer; 3588 setup->len = sizeof(*req); 3589 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3590 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3591 3592 stat->qtd.qtd_status = htole32( 3593 EHCI_QTD_ACTIVE | 3594 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3595 EHCI_QTD_SET_CERR(3) | 3596 EHCI_QTD_SET_TOGGLE(1) | 3597 EHCI_QTD_IOC 3598 ); 3599 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3600 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3601 stat->nextqtd = NULL; 3602 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3603 stat->xfer = xfer; 3604 stat->len = 0; 3605 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3607 3608 #ifdef EHCI_DEBUG 3609 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3610 ehci_dump_sqh(sqh); 3611 ehci_dump_sqtds(setup); 3612 #endif 3613 3614 exfer->ex_sqtdstart = setup; 3615 exfer->ex_sqtdend = stat; 3616 KASSERT(exfer->ex_isdone); 3617 #ifdef DIAGNOSTIC 3618 exfer->ex_isdone = false; 3619 #endif 3620 3621 /* Insert qTD in QH list. */ 3622 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3623 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3624 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3625 ehci_timeout, xfer); 3626 } 3627 ehci_add_intr_list(sc, exfer); 3628 xfer->ux_status = USBD_IN_PROGRESS; 3629 mutex_exit(&sc->sc_lock); 3630 3631 #ifdef EHCI_DEBUG 3632 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3633 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3634 // delay(10000); 3635 ehci_dump_regs(sc); 3636 ehci_dump_sqh(sc->sc_async_head); 3637 ehci_dump_sqh(sqh); 3638 ehci_dump_sqtds(setup); 3639 #endif 3640 3641 return USBD_NORMAL_COMPLETION; 3642 3643 bad3: 3644 mutex_exit(&sc->sc_lock); 3645 ehci_free_sqtd(sc, stat); 3646 bad2: 3647 ehci_free_sqtd(sc, setup); 3648 bad1: 3649 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3650 mutex_enter(&sc->sc_lock); 3651 xfer->ux_status = err; 3652 usb_transfer_complete(xfer); 3653 mutex_exit(&sc->sc_lock); 3654 return err; 3655 } 3656 3657 /* 3658 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3659 * qTD status, or miss signalling occasionally under heavy load. If the host 3660 * machine is too fast, we we can miss transaction completion - when we scan 3661 * the active list the transaction still seems to be active. This generally 3662 * exhibits itself as a umass stall that never recovers. 3663 * 3664 * We work around this behaviour by setting up this callback after any softintr 3665 * that completes with transactions still pending, giving us another chance to 3666 * check for completion after the writeback has taken place. 3667 */ 3668 Static void 3669 ehci_intrlist_timeout(void *arg) 3670 { 3671 ehci_softc_t *sc = arg; 3672 3673 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3674 3675 usb_schedsoftintr(&sc->sc_bus); 3676 } 3677 3678 /************************/ 3679 3680 Static usbd_status 3681 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3682 { 3683 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3684 usbd_status err; 3685 3686 /* Insert last in queue. */ 3687 mutex_enter(&sc->sc_lock); 3688 err = usb_insert_transfer(xfer); 3689 mutex_exit(&sc->sc_lock); 3690 if (err) 3691 return err; 3692 3693 /* Pipe isn't running, start first */ 3694 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3695 } 3696 3697 Static usbd_status 3698 ehci_device_bulk_start(struct usbd_xfer *xfer) 3699 { 3700 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3701 struct ehci_xfer *exfer = EXFER(xfer); 3702 struct usbd_device *dev = epipe->pipe.up_dev; 3703 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3704 ehci_soft_qtd_t *data, *dataend; 3705 ehci_soft_qh_t *sqh; 3706 usbd_status err; 3707 int len, isread, endpt; 3708 3709 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3710 3711 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3712 xfer, xfer->ux_length, xfer->ux_flags, 0); 3713 3714 if (sc->sc_dying) 3715 return USBD_IOERROR; 3716 3717 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3718 3719 mutex_enter(&sc->sc_lock); 3720 3721 len = xfer->ux_length; 3722 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3723 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3724 sqh = epipe->sqh; 3725 3726 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3727 &dataend); 3728 if (err) { 3729 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3730 xfer->ux_status = err; 3731 usb_transfer_complete(xfer); 3732 mutex_exit(&sc->sc_lock); 3733 return err; 3734 } 3735 3736 #ifdef EHCI_DEBUG 3737 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3738 ehci_dump_sqh(sqh); 3739 ehci_dump_sqtds(data); 3740 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3741 #endif 3742 3743 /* Set up interrupt info. */ 3744 exfer->ex_sqtdstart = data; 3745 exfer->ex_sqtdend = dataend; 3746 KASSERT(exfer->ex_isdone); 3747 #ifdef DIAGNOSTIC 3748 exfer->ex_isdone = false; 3749 #endif 3750 3751 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3752 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3753 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3754 ehci_timeout, xfer); 3755 } 3756 ehci_add_intr_list(sc, exfer); 3757 xfer->ux_status = USBD_IN_PROGRESS; 3758 mutex_exit(&sc->sc_lock); 3759 3760 #ifdef EHCI_DEBUG 3761 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3762 // delay(10000); 3763 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3764 ehci_dump_regs(sc); 3765 #if 0 3766 printf("async_head:\n"); 3767 ehci_dump_sqh(sc->sc_async_head); 3768 #endif 3769 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3770 ehci_dump_sqh(sqh); 3771 ehci_dump_sqtds(data); 3772 #endif 3773 3774 if (sc->sc_bus.ub_usepolling) 3775 ehci_waitintr(sc, xfer); 3776 3777 return USBD_IN_PROGRESS; 3778 } 3779 3780 Static void 3781 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3782 { 3783 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3784 3785 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3786 ehci_abort_xfer(xfer, USBD_CANCELLED); 3787 } 3788 3789 /* 3790 * Close a device bulk pipe. 3791 */ 3792 Static void 3793 ehci_device_bulk_close(struct usbd_pipe *pipe) 3794 { 3795 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3796 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3797 3798 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3799 3800 KASSERT(mutex_owned(&sc->sc_lock)); 3801 3802 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3803 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3804 ehci_close_pipe(pipe, sc->sc_async_head); 3805 } 3806 3807 Static void 3808 ehci_device_bulk_done(struct usbd_xfer *xfer) 3809 { 3810 struct ehci_xfer *ex = EXFER(xfer); 3811 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3812 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3813 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3814 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3815 3816 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3817 3818 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3819 xfer, xfer->ux_actlen, 0, 0); 3820 3821 KASSERT(mutex_owned(&sc->sc_lock)); 3822 3823 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3824 ehci_del_intr_list(sc, ex); /* remove from active list */ 3825 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3826 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3827 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3828 } 3829 3830 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3831 } 3832 3833 /************************/ 3834 3835 Static usbd_status 3836 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3837 { 3838 struct ehci_soft_islot *isp; 3839 int islot, lev; 3840 3841 /* Find a poll rate that is large enough. */ 3842 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3843 if (EHCI_ILEV_IVAL(lev) <= ival) 3844 break; 3845 3846 /* Pick an interrupt slot at the right level. */ 3847 /* XXX could do better than picking at random */ 3848 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3849 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3850 3851 sqh->islot = islot; 3852 isp = &sc->sc_islots[islot]; 3853 mutex_enter(&sc->sc_lock); 3854 ehci_add_qh(sc, sqh, isp->sqh); 3855 mutex_exit(&sc->sc_lock); 3856 3857 return USBD_NORMAL_COMPLETION; 3858 } 3859 3860 Static usbd_status 3861 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3862 { 3863 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3864 usbd_status err; 3865 3866 /* Insert last in queue. */ 3867 mutex_enter(&sc->sc_lock); 3868 err = usb_insert_transfer(xfer); 3869 mutex_exit(&sc->sc_lock); 3870 if (err) 3871 return err; 3872 3873 /* 3874 * Pipe isn't running (otherwise err would be USBD_INPROG), 3875 * so start it first. 3876 */ 3877 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3878 } 3879 3880 Static usbd_status 3881 ehci_device_intr_start(struct usbd_xfer *xfer) 3882 { 3883 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3884 struct ehci_xfer *exfer = EXFER(xfer); 3885 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3886 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3887 ehci_soft_qtd_t *data, *dataend; 3888 ehci_soft_qh_t *sqh; 3889 usbd_status err; 3890 int len, isread, endpt; 3891 3892 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3893 3894 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3895 xfer, xfer->ux_length, xfer->ux_flags, 0); 3896 3897 if (sc->sc_dying) 3898 return USBD_IOERROR; 3899 3900 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3901 3902 mutex_enter(&sc->sc_lock); 3903 3904 len = xfer->ux_length; 3905 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3906 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3907 sqh = epipe->sqh; 3908 3909 epipe->intr.length = len; 3910 3911 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3912 &dataend); 3913 if (err) { 3914 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3915 xfer->ux_status = err; 3916 usb_transfer_complete(xfer); 3917 mutex_exit(&sc->sc_lock); 3918 return err; 3919 } 3920 3921 #ifdef EHCI_DEBUG 3922 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3923 ehci_dump_sqh(sqh); 3924 ehci_dump_sqtds(data); 3925 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3926 #endif 3927 3928 /* Set up interrupt info. */ 3929 exfer->ex_sqtdstart = data; 3930 exfer->ex_sqtdend = dataend; 3931 KASSERT(exfer->ex_isdone); 3932 #ifdef DIAGNOSTIC 3933 exfer->ex_isdone = false; 3934 #endif 3935 3936 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3937 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3938 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3939 ehci_timeout, xfer); 3940 } 3941 ehci_add_intr_list(sc, exfer); 3942 xfer->ux_status = USBD_IN_PROGRESS; 3943 mutex_exit(&sc->sc_lock); 3944 3945 #ifdef EHCI_DEBUG 3946 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3947 // delay(10000); 3948 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3949 ehci_dump_regs(sc); 3950 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3951 ehci_dump_sqh(sqh); 3952 ehci_dump_sqtds(data); 3953 #endif 3954 3955 if (sc->sc_bus.ub_usepolling) 3956 ehci_waitintr(sc, xfer); 3957 3958 return USBD_IN_PROGRESS; 3959 } 3960 3961 Static void 3962 ehci_device_intr_abort(struct usbd_xfer *xfer) 3963 { 3964 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3965 3966 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3967 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3968 3969 /* 3970 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3971 * async doorbell. That's dependent on the async list, wheras 3972 * intr xfers are periodic, should not use this? 3973 */ 3974 ehci_abort_xfer(xfer, USBD_CANCELLED); 3975 } 3976 3977 Static void 3978 ehci_device_intr_close(struct usbd_pipe *pipe) 3979 { 3980 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3981 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3982 struct ehci_soft_islot *isp; 3983 3984 KASSERT(mutex_owned(&sc->sc_lock)); 3985 3986 isp = &sc->sc_islots[epipe->sqh->islot]; 3987 ehci_close_pipe(pipe, isp->sqh); 3988 } 3989 3990 Static void 3991 ehci_device_intr_done(struct usbd_xfer *xfer) 3992 { 3993 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3994 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3995 struct ehci_xfer *exfer = EXFER(xfer); 3996 ehci_soft_qtd_t *data, *dataend; 3997 ehci_soft_qh_t *sqh; 3998 usbd_status err; 3999 int len, isread, endpt; 4000 4001 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4002 4003 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4004 xfer, xfer->ux_actlen, 0, 0); 4005 4006 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4007 4008 if (xfer->ux_pipe->up_repeat) { 4009 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4010 4011 len = epipe->intr.length; 4012 xfer->ux_length = len; 4013 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4014 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4015 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4016 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4017 sqh = epipe->sqh; 4018 4019 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4020 &data, &dataend); 4021 if (err) { 4022 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4023 xfer->ux_status = err; 4024 return; 4025 } 4026 4027 /* Set up interrupt info. */ 4028 exfer->ex_sqtdstart = data; 4029 exfer->ex_sqtdend = dataend; 4030 KASSERT(exfer->ex_isdone); 4031 #ifdef DIAGNOSTIC 4032 exfer->ex_isdone = false; 4033 #endif 4034 4035 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4036 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4037 callout_reset(&xfer->ux_callout, 4038 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4039 } 4040 4041 xfer->ux_status = USBD_IN_PROGRESS; 4042 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4043 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4044 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4045 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4046 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4047 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4048 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4049 } 4050 } 4051 4052 /************************/ 4053 4054 Static usbd_status 4055 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4056 { 4057 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4058 usbd_status err; 4059 4060 mutex_enter(&sc->sc_lock); 4061 err = usb_insert_transfer(xfer); 4062 mutex_exit(&sc->sc_lock); 4063 4064 if (err && err != USBD_IN_PROGRESS) 4065 return err; 4066 4067 return ehci_device_fs_isoc_start(xfer); 4068 } 4069 4070 Static usbd_status 4071 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4072 { 4073 struct ehci_pipe *epipe; 4074 struct usbd_device *dev; 4075 ehci_softc_t *sc; 4076 struct ehci_xfer *exfer; 4077 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4078 usb_dma_t *dma_buf; 4079 int i, j, k, frames; 4080 int offs, total_length; 4081 int frindex; 4082 u_int huba, dir; 4083 4084 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4085 4086 start = NULL; 4087 prev = NULL; 4088 sitd = NULL; 4089 total_length = 0; 4090 exfer = (struct ehci_xfer *) xfer; 4091 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4092 dev = xfer->ux_pipe->up_dev; 4093 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4094 4095 /* 4096 * To allow continuous transfers, above we start all transfers 4097 * immediately. However, we're still going to get usbd_start_next call 4098 * this when another xfer completes. So, check if this is already 4099 * in progress or not 4100 */ 4101 4102 if (exfer->ex_sitdstart != NULL) 4103 return USBD_IN_PROGRESS; 4104 4105 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4106 xfer, xfer->ux_length, xfer->ux_flags, 0); 4107 4108 if (sc->sc_dying) 4109 return USBD_IOERROR; 4110 4111 /* 4112 * To avoid complication, don't allow a request right now that'll span 4113 * the entire frame table. To within 4 frames, to allow some leeway 4114 * on either side of where the hc currently is. 4115 */ 4116 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4117 xfer->ux_nframes >= sc->sc_flsize - 4) { 4118 printf("ehci: isoc descriptor requested that spans the entire" 4119 "frametable, too many frames\n"); 4120 return USBD_INVAL; 4121 } 4122 4123 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4124 KASSERT(exfer->ex_isdone); 4125 4126 #ifdef DIAGNOSTIC 4127 exfer->ex_isdone = false; 4128 #endif 4129 4130 /* 4131 * Step 1: Allocate and initialize sitds. 4132 */ 4133 4134 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4135 if (i > 16 || i == 0) { 4136 /* Spec page 271 says intervals > 16 are invalid */ 4137 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4138 4139 return USBD_INVAL; 4140 } 4141 4142 frames = xfer->ux_nframes; 4143 4144 if (frames == 0) { 4145 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4146 4147 return USBD_INVAL; 4148 } 4149 4150 dma_buf = &xfer->ux_dmabuf; 4151 offs = 0; 4152 4153 for (i = 0; i < frames; i++) { 4154 sitd = ehci_alloc_sitd(sc); 4155 4156 if (prev) 4157 prev->xfer_next = sitd; 4158 else 4159 start = sitd; 4160 4161 #ifdef DIAGNOSTIC 4162 if (xfer->ux_frlengths[i] > 0x3ff) { 4163 printf("ehci: invalid frame length\n"); 4164 xfer->ux_frlengths[i] = 0x3ff; 4165 } 4166 #endif 4167 4168 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4169 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4170 4171 /* Set page0 index and offset. */ 4172 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4173 4174 total_length += xfer->ux_frlengths[i]; 4175 offs += xfer->ux_frlengths[i]; 4176 4177 sitd->sitd.sitd_buffer[1] = 4178 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4179 4180 huba = dev->ud_myhsport->up_parent->ud_addr; 4181 4182 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4183 // Set hub address to 0 if embedded TT is used. 4184 if (huba == sc->sc_addr) 4185 huba = 0; 4186 } 4187 */ 4188 4189 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4190 dir = UE_GET_DIR(k) ? 1 : 0; 4191 sitd->sitd.sitd_endp = 4192 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4193 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4194 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4195 EHCI_SITD_SET_HUBA(huba) | 4196 EHCI_SITD_SET_DIR(dir)); 4197 4198 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4199 4200 /* XXX */ 4201 u_char sa, sb; 4202 u_int temp, tlen; 4203 sa = 0; 4204 4205 if (dir == 0) { /* OUT */ 4206 temp = 0; 4207 tlen = xfer->ux_frlengths[i]; 4208 if (tlen <= 188) { 4209 temp |= 1; /* T-count = 1, TP = ALL */ 4210 tlen = 1; 4211 } else { 4212 tlen += 187; 4213 tlen /= 188; 4214 temp |= tlen; /* T-count = [1..6] */ 4215 temp |= 8; /* TP = Begin */ 4216 } 4217 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4218 4219 tlen += sa; 4220 4221 if (tlen >= 8) { 4222 sb = 0; 4223 } else { 4224 sb = (1 << tlen); 4225 } 4226 4227 sa = (1 << sa); 4228 sa = (sb - sa) & 0x3F; 4229 sb = 0; 4230 } else { 4231 sb = (-(4 << sa)) & 0xFE; 4232 sa = (1 << sa) & 0x3F; 4233 sa = 0x01; 4234 sb = 0xfc; 4235 } 4236 4237 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4238 EHCI_SITD_SET_CMASK(sb)); 4239 4240 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4241 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4242 4243 prev = sitd; 4244 } /* End of frame */ 4245 4246 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4247 4248 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4249 sizeof(sitd->sitd.sitd_trans), 4250 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4251 4252 stop = sitd; 4253 stop->xfer_next = NULL; 4254 4255 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4256 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4257 4258 /* 4259 * Part 2: Transfer descriptors have now been set up, now they must 4260 * be scheduled into the periodic frame list. Erk. Not wanting to 4261 * complicate matters, transfer is denied if the transfer spans 4262 * more than the period frame list. 4263 */ 4264 4265 mutex_enter(&sc->sc_lock); 4266 4267 /* Start inserting frames */ 4268 if (epipe->isoc.cur_xfers > 0) { 4269 frindex = epipe->isoc.next_frame; 4270 } else { 4271 frindex = EOREAD4(sc, EHCI_FRINDEX); 4272 frindex = frindex >> 3; /* Erase microframe index */ 4273 frindex += 2; 4274 } 4275 4276 if (frindex >= sc->sc_flsize) 4277 frindex &= (sc->sc_flsize - 1); 4278 4279 /* Whats the frame interval? */ 4280 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4281 4282 sitd = start; 4283 for (j = 0; j < frames; j++) { 4284 if (sitd == NULL) 4285 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4286 4287 usb_syncmem(&sc->sc_fldma, 4288 sizeof(ehci_link_t) * frindex, 4289 sizeof(ehci_link_t), 4290 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4291 4292 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4293 if (sitd->sitd.sitd_next == 0) 4294 /* 4295 * FIXME: frindex table gets initialized to NULL 4296 * or EHCI_NULL? 4297 */ 4298 sitd->sitd.sitd_next = EHCI_NULL; 4299 4300 usb_syncmem(&sitd->dma, 4301 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4302 sizeof(ehci_sitd_t), 4303 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4304 4305 sc->sc_flist[frindex] = 4306 htole32(EHCI_LINK_SITD | sitd->physaddr); 4307 4308 usb_syncmem(&sc->sc_fldma, 4309 sizeof(ehci_link_t) * frindex, 4310 sizeof(ehci_link_t), 4311 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4312 4313 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4314 sc->sc_softsitds[frindex] = sitd; 4315 if (sitd->frame_list.next != NULL) 4316 sitd->frame_list.next->frame_list.prev = sitd; 4317 sitd->slot = frindex; 4318 sitd->frame_list.prev = NULL; 4319 4320 frindex += i; 4321 if (frindex >= sc->sc_flsize) 4322 frindex -= sc->sc_flsize; 4323 4324 sitd = sitd->xfer_next; 4325 } 4326 4327 epipe->isoc.cur_xfers++; 4328 epipe->isoc.next_frame = frindex; 4329 4330 exfer->ex_sitdstart = start; 4331 exfer->ex_sitdend = stop; 4332 4333 ehci_add_intr_list(sc, exfer); 4334 xfer->ux_status = USBD_IN_PROGRESS; 4335 4336 mutex_exit(&sc->sc_lock); 4337 4338 if (sc->sc_bus.ub_usepolling) { 4339 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4340 ehci_waitintr(sc, xfer); 4341 } 4342 4343 return USBD_IN_PROGRESS; 4344 } 4345 4346 Static void 4347 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4348 { 4349 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4350 4351 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4352 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4353 } 4354 4355 Static void 4356 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4357 { 4358 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4359 4360 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4361 } 4362 4363 Static void 4364 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4365 { 4366 struct ehci_xfer *exfer; 4367 ehci_softc_t *sc; 4368 struct ehci_pipe *epipe; 4369 4370 exfer = EXFER(xfer); 4371 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4372 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4373 4374 KASSERT(mutex_owned(&sc->sc_lock)); 4375 4376 epipe->isoc.cur_xfers--; 4377 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4378 ehci_del_intr_list(sc, exfer); 4379 ehci_rem_free_sitd_chain(sc, exfer); 4380 } 4381 4382 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4383 BUS_DMASYNC_POSTREAD); 4384 } 4385 Static usbd_status 4386 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4387 { 4388 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4389 usbd_status err; 4390 4391 mutex_enter(&sc->sc_lock); 4392 err = usb_insert_transfer(xfer); 4393 mutex_exit(&sc->sc_lock); 4394 if (err && err != USBD_IN_PROGRESS) 4395 return err; 4396 4397 return ehci_device_isoc_start(xfer); 4398 } 4399 4400 Static usbd_status 4401 ehci_device_isoc_start(struct usbd_xfer *xfer) 4402 { 4403 struct ehci_pipe *epipe; 4404 ehci_softc_t *sc; 4405 struct ehci_xfer *exfer; 4406 ehci_soft_itd_t *itd, *prev, *start, *stop; 4407 usb_dma_t *dma_buf; 4408 int i, j, k, frames, uframes, ufrperframe; 4409 int trans_count, offs, total_length; 4410 int frindex; 4411 4412 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4413 4414 start = NULL; 4415 prev = NULL; 4416 itd = NULL; 4417 trans_count = 0; 4418 total_length = 0; 4419 exfer = (struct ehci_xfer *) xfer; 4420 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4421 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4422 4423 /* 4424 * To allow continuous transfers, above we start all transfers 4425 * immediately. However, we're still going to get usbd_start_next call 4426 * this when another xfer completes. So, check if this is already 4427 * in progress or not 4428 */ 4429 4430 if (exfer->ex_itdstart != NULL) 4431 return USBD_IN_PROGRESS; 4432 4433 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4434 xfer, xfer->ux_length, xfer->ux_flags, 0); 4435 4436 if (sc->sc_dying) 4437 return USBD_IOERROR; 4438 4439 /* 4440 * To avoid complication, don't allow a request right now that'll span 4441 * the entire frame table. To within 4 frames, to allow some leeway 4442 * on either side of where the hc currently is. 4443 */ 4444 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4445 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4446 USBHIST_LOG(ehcidebug, 4447 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4448 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4449 return USBD_INVAL; 4450 } 4451 4452 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4453 KASSERT(exfer->ex_isdone); 4454 #ifdef DIAGNOSTIC 4455 exfer->ex_isdone = false; 4456 #endif 4457 4458 /* 4459 * Step 1: Allocate and initialize itds, how many do we need? 4460 * One per transfer if interval >= 8 microframes, fewer if we use 4461 * multiple microframes per frame. 4462 */ 4463 4464 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4465 if (i > 16 || i == 0) { 4466 /* Spec page 271 says intervals > 16 are invalid */ 4467 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4468 return USBD_INVAL; 4469 } 4470 4471 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4472 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4473 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4474 4475 if (frames == 0) { 4476 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4477 return USBD_INVAL; 4478 } 4479 4480 dma_buf = &xfer->ux_dmabuf; 4481 offs = 0; 4482 4483 for (i = 0; i < frames; i++) { 4484 int froffs = offs; 4485 itd = ehci_alloc_itd(sc); 4486 4487 if (prev != NULL) { 4488 prev->itd.itd_next = 4489 htole32(itd->physaddr | EHCI_LINK_ITD); 4490 usb_syncmem(&prev->dma, 4491 prev->offs + offsetof(ehci_itd_t, itd_next), 4492 sizeof(prev->itd.itd_next), 4493 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4494 4495 prev->xfer_next = itd; 4496 } else { 4497 start = itd; 4498 } 4499 4500 /* 4501 * Step 1.5, initialize uframes 4502 */ 4503 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4504 /* Calculate which page in the list this starts in */ 4505 int addr = DMAADDR(dma_buf, froffs); 4506 addr = EHCI_PAGE_OFFSET(addr); 4507 addr += (offs - froffs); 4508 addr = EHCI_PAGE(addr); 4509 addr /= EHCI_PAGE_SIZE; 4510 4511 /* 4512 * This gets the initial offset into the first page, 4513 * looks how far further along the current uframe 4514 * offset is. Works out how many pages that is. 4515 */ 4516 4517 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4518 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4519 EHCI_ITD_SET_PG(addr) | 4520 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4521 4522 total_length += xfer->ux_frlengths[trans_count]; 4523 offs += xfer->ux_frlengths[trans_count]; 4524 trans_count++; 4525 4526 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4527 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4528 break; 4529 } 4530 } 4531 4532 /* 4533 * Step 1.75, set buffer pointers. To simplify matters, all 4534 * pointers are filled out for the next 7 hardware pages in 4535 * the dma block, so no need to worry what pages to cover 4536 * and what to not. 4537 */ 4538 4539 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4540 /* 4541 * Don't try to lookup a page that's past the end 4542 * of buffer 4543 */ 4544 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4545 if (page_offs >= dma_buf->udma_block->size) 4546 break; 4547 4548 unsigned long long page = DMAADDR(dma_buf, page_offs); 4549 page = EHCI_PAGE(page); 4550 itd->itd.itd_bufr[j] = 4551 htole32(EHCI_ITD_SET_BPTR(page)); 4552 itd->itd.itd_bufr_hi[j] = 4553 htole32(page >> 32); 4554 } 4555 4556 /* 4557 * Other special values 4558 */ 4559 4560 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4561 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4562 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4563 4564 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4565 ? 1 : 0; 4566 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4567 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4568 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4569 4570 /* FIXME: handle invalid trans */ 4571 itd->itd.itd_bufr[2] |= 4572 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4573 4574 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4575 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4576 4577 prev = itd; 4578 } /* End of frame */ 4579 4580 stop = itd; 4581 stop->xfer_next = NULL; 4582 4583 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4584 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4585 4586 /* 4587 * Part 2: Transfer descriptors have now been set up, now they must 4588 * be scheduled into the period frame list. Erk. Not wanting to 4589 * complicate matters, transfer is denied if the transfer spans 4590 * more than the period frame list. 4591 */ 4592 4593 mutex_enter(&sc->sc_lock); 4594 4595 /* Start inserting frames */ 4596 if (epipe->isoc.cur_xfers > 0) { 4597 frindex = epipe->isoc.next_frame; 4598 } else { 4599 frindex = EOREAD4(sc, EHCI_FRINDEX); 4600 frindex = frindex >> 3; /* Erase microframe index */ 4601 frindex += 2; 4602 } 4603 4604 if (frindex >= sc->sc_flsize) 4605 frindex &= (sc->sc_flsize - 1); 4606 4607 /* What's the frame interval? */ 4608 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4609 if (i / USB_UFRAMES_PER_FRAME == 0) 4610 i = 1; 4611 else 4612 i /= USB_UFRAMES_PER_FRAME; 4613 4614 itd = start; 4615 for (j = 0; j < frames; j++) { 4616 if (itd == NULL) 4617 panic("ehci: unexpectedly ran out of isoc itds, isoc_start"); 4618 4619 usb_syncmem(&sc->sc_fldma, 4620 sizeof(ehci_link_t) * frindex, 4621 sizeof(ehci_link_t), 4622 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4623 4624 itd->itd.itd_next = sc->sc_flist[frindex]; 4625 if (itd->itd.itd_next == 0) 4626 /* FIXME: frindex table gets initialized to NULL 4627 * or EHCI_NULL? */ 4628 itd->itd.itd_next = EHCI_NULL; 4629 4630 usb_syncmem(&itd->dma, 4631 itd->offs + offsetof(ehci_itd_t, itd_next), 4632 sizeof(itd->itd.itd_next), 4633 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4634 4635 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4636 4637 usb_syncmem(&sc->sc_fldma, 4638 sizeof(ehci_link_t) * frindex, 4639 sizeof(ehci_link_t), 4640 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4641 4642 itd->frame_list.next = sc->sc_softitds[frindex]; 4643 sc->sc_softitds[frindex] = itd; 4644 if (itd->frame_list.next != NULL) 4645 itd->frame_list.next->frame_list.prev = itd; 4646 itd->slot = frindex; 4647 itd->frame_list.prev = NULL; 4648 4649 frindex += i; 4650 if (frindex >= sc->sc_flsize) 4651 frindex -= sc->sc_flsize; 4652 4653 itd = itd->xfer_next; 4654 } 4655 4656 epipe->isoc.cur_xfers++; 4657 epipe->isoc.next_frame = frindex; 4658 4659 exfer->ex_itdstart = start; 4660 exfer->ex_itdend = stop; 4661 4662 ehci_add_intr_list(sc, exfer); 4663 xfer->ux_status = USBD_IN_PROGRESS; 4664 mutex_exit(&sc->sc_lock); 4665 4666 if (sc->sc_bus.ub_usepolling) { 4667 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4668 ehci_waitintr(sc, xfer); 4669 } 4670 4671 return USBD_IN_PROGRESS; 4672 } 4673 4674 Static void 4675 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4676 { 4677 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4678 4679 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4680 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4681 } 4682 4683 Static void 4684 ehci_device_isoc_close(struct usbd_pipe *pipe) 4685 { 4686 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4687 4688 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4689 } 4690 4691 Static void 4692 ehci_device_isoc_done(struct usbd_xfer *xfer) 4693 { 4694 struct ehci_xfer *exfer; 4695 ehci_softc_t *sc; 4696 struct ehci_pipe *epipe; 4697 4698 exfer = EXFER(xfer); 4699 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4700 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4701 4702 KASSERT(mutex_owned(&sc->sc_lock)); 4703 4704 epipe->isoc.cur_xfers--; 4705 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4706 ehci_del_intr_list(sc, exfer); 4707 ehci_rem_free_itd_chain(sc, exfer); 4708 } 4709 4710 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4711 BUS_DMASYNC_POSTREAD); 4712 4713 } 4714
Indexes created Thu Oct 02 01:09:59 GMT 2025