ehci.c revision 1.234.2.51
1 /* $NetBSD: ehci.c,v 1.234.2.51 2015/10/09 09:16:43 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.51 2015/10/09 09:16:43 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 ehci_soft_qtd_t *qtd; 136 /* ehci_soft_itd_t *itd; */ 137 /* ehci_soft_sitd_t *sitd; */ 138 } tail; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 Static usbd_status ehci_open(struct usbd_pipe *); 157 Static void ehci_poll(struct usbd_bus *); 158 Static void ehci_softintr(void *); 159 Static int ehci_intr1(ehci_softc_t *); 160 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 161 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_idone(struct ehci_xfer *); 166 Static void ehci_timeout(void *); 167 Static void ehci_timeout_task(void *); 168 Static void ehci_intrlist_timeout(void *); 169 Static void ehci_doorbell(void *); 170 Static void ehci_pcd(void *); 171 172 Static struct usbd_xfer * 173 ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 180 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 181 Static void ehci_root_intr_abort(struct usbd_xfer *); 182 Static void ehci_root_intr_close(struct usbd_pipe *); 183 Static void ehci_root_intr_done(struct usbd_xfer *); 184 185 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 186 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 187 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 188 Static void ehci_device_ctrl_close(struct usbd_pipe *); 189 Static void ehci_device_ctrl_done(struct usbd_xfer *); 190 191 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 193 Static void ehci_device_bulk_abort(struct usbd_xfer *); 194 Static void ehci_device_bulk_close(struct usbd_pipe *); 195 Static void ehci_device_bulk_done(struct usbd_xfer *); 196 197 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 198 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 199 Static void ehci_device_intr_abort(struct usbd_xfer *); 200 Static void ehci_device_intr_close(struct usbd_pipe *); 201 Static void ehci_device_intr_done(struct usbd_xfer *); 202 203 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 204 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 205 Static void ehci_device_isoc_abort(struct usbd_xfer *); 206 Static void ehci_device_isoc_close(struct usbd_pipe *); 207 Static void ehci_device_isoc_done(struct usbd_xfer *); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 210 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 211 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 212 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 213 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 214 215 Static void ehci_device_clear_toggle(struct usbd_pipe *); 216 Static void ehci_noop(struct usbd_pipe *); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, struct usbd_xfer *, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(struct usbd_xfer *); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* XXX need proper intr scheduling */ 451 sc->sc_rand = 96; 452 453 /* frame list size at default, read back what we got and use that */ 454 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 455 case 0: sc->sc_flsize = 1024; break; 456 case 1: sc->sc_flsize = 512; break; 457 case 2: sc->sc_flsize = 256; break; 458 case 3: return EIO; 459 } 460 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 461 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 462 if (err) 463 return err; 464 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 465 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 466 467 for (i = 0; i < sc->sc_flsize; i++) { 468 sc->sc_flist[i] = EHCI_NULL; 469 } 470 471 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 472 473 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 474 KM_SLEEP); 475 if (sc->sc_softitds == NULL) 476 return ENOMEM; 477 LIST_INIT(&sc->sc_freeitds); 478 LIST_INIT(&sc->sc_freesitds); 479 TAILQ_INIT(&sc->sc_intrhead); 480 481 /* Set up the bus struct. */ 482 sc->sc_bus.ub_methods = &ehci_bus_methods; 483 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 484 485 sc->sc_eintrs = EHCI_NORMAL_INTRS; 486 487 /* 488 * Allocate the interrupt dummy QHs. These are arranged to give poll 489 * intervals that are powers of 2 times 1ms. 490 */ 491 for (i = 0; i < EHCI_INTRQHS; i++) { 492 sqh = ehci_alloc_sqh(sc); 493 if (sqh == NULL) { 494 err = ENOMEM; 495 goto bad1; 496 } 497 sc->sc_islots[i].sqh = sqh; 498 } 499 for (i = 0; i < EHCI_INTRQHS; i++) { 500 sqh = sc->sc_islots[i].sqh; 501 if (i == 0) { 502 /* The last (1ms) QH terminates. */ 503 sqh->qh.qh_link = EHCI_NULL; 504 sqh->next = NULL; 505 } else { 506 /* Otherwise the next QH has half the poll interval */ 507 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 508 sqh->qh.qh_link = htole32(sqh->next->physaddr | 509 EHCI_LINK_QH); 510 } 511 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 512 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 513 sqh->qh.qh_curqtd = EHCI_NULL; 514 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 515 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 516 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 517 sqh->sqtd = NULL; 518 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 520 } 521 /* Point the frame list at the last level (128ms). */ 522 for (i = 0; i < sc->sc_flsize; i++) { 523 int j; 524 525 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 526 revbits[i & (EHCI_MAX_POLLRATE-1)]; 527 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 528 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 529 i)].sqh->physaddr); 530 } 531 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 532 BUS_DMASYNC_PREWRITE); 533 534 /* Allocate dummy QH that starts the async list. */ 535 sqh = ehci_alloc_sqh(sc); 536 if (sqh == NULL) { 537 err = ENOMEM; 538 goto bad1; 539 } 540 /* Fill the QH */ 541 sqh->qh.qh_endp = 542 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 543 sqh->qh.qh_link = 544 htole32(sqh->physaddr | EHCI_LINK_QH); 545 sqh->qh.qh_curqtd = EHCI_NULL; 546 sqh->next = NULL; 547 /* Fill the overlay qTD */ 548 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 549 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 550 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 551 sqh->sqtd = NULL; 552 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 553 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 554 #ifdef EHCI_DEBUG 555 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 556 ehci_dump_sqh(sqh); 557 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 558 #endif 559 560 /* Point to async list */ 561 sc->sc_async_head = sqh; 562 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 563 564 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 565 566 /* Turn on controller */ 567 EOWRITE4(sc, EHCI_USBCMD, 568 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 569 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 570 EHCI_CMD_ASE | 571 EHCI_CMD_PSE | 572 EHCI_CMD_RS); 573 574 /* Take over port ownership */ 575 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 576 577 for (i = 0; i < 100; i++) { 578 usb_delay_ms(&sc->sc_bus, 1); 579 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 580 if (!hcr) 581 break; 582 } 583 if (hcr) { 584 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 585 return EIO; 586 } 587 588 /* Enable interrupts */ 589 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 590 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 591 592 return 0; 593 594 #if 0 595 bad2: 596 ehci_free_sqh(sc, sc->sc_async_head); 597 #endif 598 bad1: 599 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 600 return err; 601 } 602 603 int 604 ehci_intr(void *v) 605 { 606 ehci_softc_t *sc = v; 607 int ret = 0; 608 609 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 610 611 if (sc == NULL) 612 return 0; 613 614 mutex_spin_enter(&sc->sc_intr_lock); 615 616 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 617 goto done; 618 619 /* If we get an interrupt while polling, then just ignore it. */ 620 if (sc->sc_bus.ub_usepolling) { 621 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 622 623 if (intrs) 624 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 625 USBHIST_LOGN(ehcidebug, 16, 626 "ignored interrupt while polling", 0, 0, 0, 0); 627 goto done; 628 } 629 630 ret = ehci_intr1(sc); 631 632 done: 633 mutex_spin_exit(&sc->sc_intr_lock); 634 return ret; 635 } 636 637 Static int 638 ehci_intr1(ehci_softc_t *sc) 639 { 640 uint32_t intrs, eintrs; 641 642 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 643 644 /* In case the interrupt occurs before initialization has completed. */ 645 if (sc == NULL) { 646 #ifdef DIAGNOSTIC 647 printf("ehci_intr1: sc == NULL\n"); 648 #endif 649 return 0; 650 } 651 652 KASSERT(mutex_owned(&sc->sc_intr_lock)); 653 654 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 655 if (!intrs) 656 return 0; 657 658 eintrs = intrs & sc->sc_eintrs; 659 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 660 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 661 if (!eintrs) 662 return 0; 663 664 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 665 if (eintrs & EHCI_STS_IAA) { 666 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 667 kpreempt_disable(); 668 KASSERT(sc->sc_doorbell_si != NULL); 669 softint_schedule(sc->sc_doorbell_si); 670 kpreempt_enable(); 671 eintrs &= ~EHCI_STS_IAA; 672 } 673 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 674 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 675 eintrs & EHCI_STS_INT ? 1 : 0, 676 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 677 usb_schedsoftintr(&sc->sc_bus); 678 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 679 } 680 if (eintrs & EHCI_STS_HSE) { 681 printf("%s: unrecoverable error, controller halted\n", 682 device_xname(sc->sc_dev)); 683 /* XXX what else */ 684 } 685 if (eintrs & EHCI_STS_PCD) { 686 kpreempt_disable(); 687 KASSERT(sc->sc_pcd_si != NULL); 688 softint_schedule(sc->sc_pcd_si); 689 kpreempt_enable(); 690 eintrs &= ~EHCI_STS_PCD; 691 } 692 693 if (eintrs != 0) { 694 /* Block unprocessed interrupts. */ 695 sc->sc_eintrs &= ~eintrs; 696 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 697 printf("%s: blocking intrs 0x%x\n", 698 device_xname(sc->sc_dev), eintrs); 699 } 700 701 return 1; 702 } 703 704 Static void 705 ehci_doorbell(void *addr) 706 { 707 ehci_softc_t *sc = addr; 708 709 mutex_enter(&sc->sc_lock); 710 cv_broadcast(&sc->sc_doorbell); 711 mutex_exit(&sc->sc_lock); 712 } 713 714 Static void 715 ehci_pcd(void *addr) 716 { 717 ehci_softc_t *sc = addr; 718 struct usbd_xfer *xfer; 719 u_char *p; 720 int i, m; 721 722 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 723 724 mutex_enter(&sc->sc_lock); 725 xfer = sc->sc_intrxfer; 726 727 if (xfer == NULL) { 728 /* Just ignore the change. */ 729 goto done; 730 } 731 732 p = xfer->ux_buf; 733 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 734 memset(p, 0, xfer->ux_length); 735 for (i = 1; i <= m; i++) { 736 /* Pick out CHANGE bits from the status reg. */ 737 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 738 p[i/8] |= 1 << (i%8); 739 if (i % 8 == 7) 740 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 741 p[i/8], 0, 0); 742 } 743 xfer->ux_actlen = xfer->ux_length; 744 xfer->ux_status = USBD_NORMAL_COMPLETION; 745 746 usb_transfer_complete(xfer); 747 748 done: 749 mutex_exit(&sc->sc_lock); 750 } 751 752 Static void 753 ehci_softintr(void *v) 754 { 755 struct usbd_bus *bus = v; 756 ehci_softc_t *sc = bus->ub_hcpriv; 757 struct ehci_xfer *ex, *nextex; 758 759 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 760 761 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 762 763 /* 764 * The only explanation I can think of for why EHCI is as brain dead 765 * as UHCI interrupt-wise is that Intel was involved in both. 766 * An interrupt just tells us that something is done, we have no 767 * clue what, so we need to scan through all active transfers. :-( 768 */ 769 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 770 nextex = TAILQ_NEXT(ex, ex_next); 771 ehci_check_intr(sc, ex); 772 } 773 774 /* Schedule a callout to catch any dropped transactions. */ 775 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 776 !TAILQ_EMPTY(&sc->sc_intrhead)) 777 callout_reset(&sc->sc_tmo_intrlist, 778 hz, ehci_intrlist_timeout, sc); 779 780 if (sc->sc_softwake) { 781 sc->sc_softwake = 0; 782 cv_broadcast(&sc->sc_softwake_cv); 783 } 784 } 785 786 /* Check for an interrupt. */ 787 Static void 788 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 789 { 790 struct usbd_device *dev = ex->ex_xfer.ux_pipe->up_dev; 791 int attr; 792 793 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 794 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 795 796 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 797 798 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 799 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 800 if (dev->ud_speed == USB_SPEED_HIGH) 801 ehci_check_itd_intr(sc, ex); 802 else 803 ehci_check_sitd_intr(sc, ex); 804 } else 805 ehci_check_qh_intr(sc, ex); 806 807 return; 808 } 809 810 Static void 811 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 812 { 813 ehci_soft_qtd_t *sqtd, *lsqtd; 814 uint32_t status; 815 816 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 817 818 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 819 820 if (ex->ex_sqtdstart == NULL) { 821 printf("ehci_check_qh_intr: not valid sqtd\n"); 822 return; 823 } 824 825 lsqtd = ex->ex_sqtdend; 826 #ifdef DIAGNOSTIC 827 if (lsqtd == NULL) { 828 printf("ehci_check_qh_intr: lsqtd==0\n"); 829 return; 830 } 831 #endif 832 /* 833 * If the last TD is still active we need to check whether there 834 * is an error somewhere in the middle, or whether there was a 835 * short packet (SPD and not ACTIVE). 836 */ 837 usb_syncmem(&lsqtd->dma, 838 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 839 sizeof(lsqtd->qtd.qtd_status), 840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 841 status = le32toh(lsqtd->qtd.qtd_status); 842 usb_syncmem(&lsqtd->dma, 843 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 844 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 845 if (status & EHCI_QTD_ACTIVE) { 846 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 847 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 848 sqtd = sqtd->nextqtd) { 849 usb_syncmem(&sqtd->dma, 850 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 851 sizeof(sqtd->qtd.qtd_status), 852 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 853 status = le32toh(sqtd->qtd.qtd_status); 854 usb_syncmem(&sqtd->dma, 855 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 856 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 857 /* If there's an active QTD the xfer isn't done. */ 858 if (status & EHCI_QTD_ACTIVE) 859 break; 860 /* Any kind of error makes the xfer done. */ 861 if (status & EHCI_QTD_HALTED) 862 goto done; 863 /* Handle short packets */ 864 if (EHCI_QTD_GET_BYTES(status) != 0) { 865 struct usbd_pipe *pipe = ex->ex_xfer.ux_pipe; 866 usb_endpoint_descriptor_t *ed = 867 pipe->up_endpoint->ue_edesc; 868 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 869 870 /* 871 * If we get here for a control transfer then 872 * we need to let the hardware complete the 873 * status phase. That is, we're not done 874 * quite yet. 875 * 876 * Otherwise, we're done. 877 */ 878 if (xt == UE_CONTROL) { 879 break; 880 } 881 goto done; 882 } 883 } 884 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 885 ex, ex->ex_sqtdstart, 0, 0); 886 #ifdef EHCI_DEBUG 887 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 888 0, 0); 889 ehci_dump_sqtds(ex->ex_sqtdstart); 890 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 891 0); 892 #endif 893 return; 894 } 895 done: 896 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 897 callout_stop(&ex->ex_xfer.ux_callout); 898 ehci_idone(ex); 899 } 900 901 Static void 902 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 903 { 904 ehci_soft_itd_t *itd; 905 int i; 906 907 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 908 909 KASSERT(mutex_owned(&sc->sc_lock)); 910 911 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 912 return; 913 914 if (ex->ex_itdstart == NULL) { 915 printf("ehci_check_itd_intr: not valid itd\n"); 916 return; 917 } 918 919 itd = ex->ex_itdend; 920 #ifdef DIAGNOSTIC 921 if (itd == NULL) { 922 printf("ehci_check_itd_intr: itdend == 0\n"); 923 return; 924 } 925 #endif 926 927 /* 928 * check no active transfers in last itd, meaning we're finished 929 */ 930 931 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 932 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 933 BUS_DMASYNC_POSTREAD); 934 935 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 936 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 937 break; 938 } 939 940 if (i == EHCI_ITD_NUFRAMES) { 941 goto done; /* All 8 descriptors inactive, it's done */ 942 } 943 944 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 945 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 946 947 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 948 ex->ex_itdstart, 0, 0); 949 return; 950 done: 951 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 952 callout_stop(&ex->ex_xfer.ux_callout); 953 ehci_idone(ex); 954 } 955 956 void 957 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 958 { 959 ehci_soft_sitd_t *sitd; 960 961 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 962 963 KASSERT(mutex_owned(&sc->sc_lock)); 964 965 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 966 return; 967 968 if (ex->ex_sitdstart == NULL) { 969 printf("ehci_check_sitd_intr: not valid sitd\n"); 970 return; 971 } 972 973 sitd = ex->ex_sitdend; 974 #ifdef DIAGNOSTIC 975 if (sitd == NULL) { 976 printf("ehci_check_sitd_intr: sitdend == 0\n"); 977 return; 978 } 979 #endif 980 981 /* 982 * check no active transfers in last sitd, meaning we're finished 983 */ 984 985 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 986 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_POSTWRITE | 987 BUS_DMASYNC_POSTREAD); 988 989 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 990 return; 991 992 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 993 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 994 995 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 996 callout_stop(&(ex->ex_xfer.ux_callout)); 997 ehci_idone(ex); 998 } 999 1000 1001 Static void 1002 ehci_idone(struct ehci_xfer *ex) 1003 { 1004 struct usbd_xfer *xfer = &ex->ex_xfer; 1005 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1006 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1007 ehci_soft_qtd_t *sqtd, *lsqtd; 1008 uint32_t status = 0, nstatus = 0; 1009 int actlen; 1010 1011 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1012 1013 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1014 1015 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1016 1017 #ifdef DIAGNOSTIC 1018 #ifdef EHCI_DEBUG 1019 if (ex->ex_isdone) { 1020 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1021 ehci_dump_exfer(ex); 1022 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1023 } 1024 #endif 1025 KASSERT(!ex->ex_isdone); 1026 ex->ex_isdone = true; 1027 #endif 1028 1029 if (xfer->ux_status == USBD_CANCELLED || 1030 xfer->ux_status == USBD_TIMEOUT) { 1031 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1032 return; 1033 } 1034 1035 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1036 1037 /* The transfer is done, compute actual length and status. */ 1038 1039 u_int xfertype, speed; 1040 1041 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1042 speed = xfer->ux_pipe->up_dev->ud_speed; 1043 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1044 /* HS isoc transfer */ 1045 1046 struct ehci_soft_itd *itd; 1047 int i, nframes, len, uframes; 1048 1049 nframes = 0; 1050 actlen = 0; 1051 1052 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1053 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1054 1055 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1056 usb_syncmem(&itd->dma, 1057 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1058 sizeof(itd->itd.itd_ctl), 1059 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1060 1061 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1062 /* 1063 * XXX - driver didn't fill in the frame full 1064 * of uframes. This leads to scheduling 1065 * inefficiencies, but working around 1066 * this doubles complexity of tracking 1067 * an xfer. 1068 */ 1069 if (nframes >= xfer->ux_nframes) 1070 break; 1071 1072 status = le32toh(itd->itd.itd_ctl[i]); 1073 len = EHCI_ITD_GET_LEN(status); 1074 if (EHCI_ITD_GET_STATUS(status) != 0) 1075 len = 0; /*No valid data on error*/ 1076 1077 xfer->ux_frlengths[nframes++] = len; 1078 actlen += len; 1079 } 1080 usb_syncmem(&itd->dma, 1081 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1082 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1083 1084 if (nframes >= xfer->ux_nframes) 1085 break; 1086 } 1087 1088 xfer->ux_actlen = actlen; 1089 xfer->ux_status = USBD_NORMAL_COMPLETION; 1090 goto end; 1091 } 1092 1093 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1094 /* FS isoc transfer */ 1095 struct ehci_soft_sitd *sitd; 1096 int nframes, len; 1097 1098 nframes = 0; 1099 actlen = 0; 1100 1101 for (sitd = ex->ex_sitdstart; sitd != NULL; 1102 sitd = sitd->xfer_next) { 1103 usb_syncmem(&sitd->dma, 1104 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1105 sizeof(sitd->sitd.sitd_trans), 1106 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1107 1108 /* 1109 * XXX - driver didn't fill in the frame full 1110 * of uframes. This leads to scheduling 1111 * inefficiencies, but working around 1112 * this doubles complexity of tracking 1113 * an xfer. 1114 */ 1115 if (nframes >= xfer->ux_nframes) 1116 break; 1117 1118 status = le32toh(sitd->sitd.sitd_trans); 1119 usb_syncmem(&sitd->dma, 1120 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1121 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1122 1123 len = EHCI_SITD_GET_LEN(status); 1124 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1125 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1126 /* No valid data on error */ 1127 len = xfer->ux_frlengths[nframes]; 1128 } 1129 1130 /* 1131 * frlengths[i]: # of bytes to send 1132 * len: # of bytes host didn't send 1133 */ 1134 xfer->ux_frlengths[nframes] -= len; 1135 /* frlengths[i]: # of bytes host sent */ 1136 actlen += xfer->ux_frlengths[nframes++]; 1137 1138 if (nframes >= xfer->ux_nframes) 1139 break; 1140 } 1141 1142 xfer->ux_actlen = actlen; 1143 xfer->ux_status = USBD_NORMAL_COMPLETION; 1144 goto end; 1145 } 1146 KASSERT(xfertype != UE_ISOCHRONOUS); 1147 1148 /* Continue processing xfers using queue heads */ 1149 1150 #ifdef EHCI_DEBUG 1151 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1152 ehci_dump_sqtds(ex->ex_sqtdstart); 1153 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1154 #endif 1155 1156 lsqtd = ex->ex_sqtdend; 1157 actlen = 0; 1158 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1159 sqtd = sqtd->nextqtd) { 1160 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1161 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1162 nstatus = le32toh(sqtd->qtd.qtd_status); 1163 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1164 BUS_DMASYNC_PREREAD); 1165 if (nstatus & EHCI_QTD_ACTIVE) 1166 break; 1167 1168 status = nstatus; 1169 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1170 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1171 } 1172 1173 /* 1174 * If there are left over TDs we need to update the toggle. 1175 * The default pipe doesn't need it since control transfers 1176 * start the toggle at 0 every time. 1177 * For a short transfer we need to update the toggle for the missing 1178 * packets within the qTD. 1179 */ 1180 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1181 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1182 USBHIST_LOG(ehcidebug, 1183 "toggle update status=0x%08x nstatus=0x%08x", 1184 status, nstatus, 0, 0); 1185 #if 0 1186 ehci_dump_sqh(epipe->sqh); 1187 ehci_dump_sqtds(ex->ex_sqtdstart); 1188 #endif 1189 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1190 } 1191 1192 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1193 actlen, status, 0); 1194 xfer->ux_actlen = actlen; 1195 if (status & EHCI_QTD_HALTED) { 1196 #ifdef EHCI_DEBUG 1197 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1198 xfer->ux_pipe->up_dev->ud_addr, 1199 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1200 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1201 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1202 0, 0); 1203 USBHIST_LOG(ehcidebug, 1204 "active =%d halted=%d buferr=%d babble=%d", 1205 status & EHCI_QTD_ACTIVE ? 1 : 0, 1206 status & EHCI_QTD_HALTED ? 1 : 0, 1207 status & EHCI_QTD_BUFERR ? 1 : 0, 1208 status & EHCI_QTD_BABBLE ? 1 : 0); 1209 1210 USBHIST_LOG(ehcidebug, 1211 "xacterr=%d missed=%d split =%d ping =%d", 1212 status & EHCI_QTD_XACTERR ? 1 : 0, 1213 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1214 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1215 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1216 1217 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1218 ehci_dump_sqh(epipe->sqh); 1219 ehci_dump_sqtds(ex->ex_sqtdstart); 1220 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1221 #endif 1222 /* low&full speed has an extra error flag */ 1223 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1224 EHCI_QH_SPEED_HIGH) 1225 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1226 else 1227 status &= EHCI_QTD_STATERRS; 1228 if (status == 0) /* no other errors means a stall */ { 1229 xfer->ux_status = USBD_STALLED; 1230 } else { 1231 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1232 } 1233 /* XXX need to reset TT on missed microframe */ 1234 if (status & EHCI_QTD_MISSEDMICRO) { 1235 printf("%s: missed microframe, TT reset not " 1236 "implemented, hub might be inoperational\n", 1237 device_xname(sc->sc_dev)); 1238 } 1239 } else { 1240 xfer->ux_status = USBD_NORMAL_COMPLETION; 1241 } 1242 1243 end: 1244 /* 1245 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1246 * during this call, before methods->done is called: dma sync required 1247 * beforehand? 1248 */ 1249 usb_transfer_complete(xfer); 1250 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1251 } 1252 1253 /* 1254 * Wait here until controller claims to have an interrupt. 1255 * Then call ehci_intr and return. Use timeout to avoid waiting 1256 * too long. 1257 */ 1258 Static void 1259 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1260 { 1261 int timo; 1262 uint32_t intrs; 1263 1264 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1265 1266 xfer->ux_status = USBD_IN_PROGRESS; 1267 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1268 usb_delay_ms(&sc->sc_bus, 1); 1269 if (sc->sc_dying) 1270 break; 1271 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1272 sc->sc_eintrs; 1273 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1274 #ifdef EHCI_DEBUG 1275 if (ehcidebug > 15) 1276 ehci_dump_regs(sc); 1277 #endif 1278 if (intrs) { 1279 mutex_spin_enter(&sc->sc_intr_lock); 1280 ehci_intr1(sc); 1281 mutex_spin_exit(&sc->sc_intr_lock); 1282 if (xfer->ux_status != USBD_IN_PROGRESS) 1283 return; 1284 } 1285 } 1286 1287 /* Timeout */ 1288 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1289 xfer->ux_status = USBD_TIMEOUT; 1290 mutex_enter(&sc->sc_lock); 1291 usb_transfer_complete(xfer); 1292 mutex_exit(&sc->sc_lock); 1293 /* XXX should free TD */ 1294 } 1295 1296 Static void 1297 ehci_poll(struct usbd_bus *bus) 1298 { 1299 ehci_softc_t *sc = bus->ub_hcpriv; 1300 1301 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1302 1303 #ifdef EHCI_DEBUG 1304 static int last; 1305 int new; 1306 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1307 if (new != last) { 1308 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1309 last = new; 1310 } 1311 #endif 1312 1313 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1314 mutex_spin_enter(&sc->sc_intr_lock); 1315 ehci_intr1(sc); 1316 mutex_spin_exit(&sc->sc_intr_lock); 1317 } 1318 } 1319 1320 void 1321 ehci_childdet(device_t self, device_t child) 1322 { 1323 struct ehci_softc *sc = device_private(self); 1324 1325 KASSERT(sc->sc_child == child); 1326 sc->sc_child = NULL; 1327 } 1328 1329 int 1330 ehci_detach(struct ehci_softc *sc, int flags) 1331 { 1332 int rv = 0; 1333 1334 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1335 1336 if (sc->sc_child != NULL) 1337 rv = config_detach(sc->sc_child, flags); 1338 1339 if (rv != 0) 1340 return rv; 1341 1342 callout_halt(&sc->sc_tmo_intrlist, NULL); 1343 callout_destroy(&sc->sc_tmo_intrlist); 1344 1345 /* XXX free other data structures XXX */ 1346 if (sc->sc_softitds) 1347 kmem_free(sc->sc_softitds, 1348 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1349 cv_destroy(&sc->sc_doorbell); 1350 cv_destroy(&sc->sc_softwake_cv); 1351 1352 #if 0 1353 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1354 1355 softint_disestablish(sc->sc_doorbell_si); 1356 softint_disestablish(sc->sc_pcd_si); 1357 1358 mutex_destroy(&sc->sc_lock); 1359 mutex_destroy(&sc->sc_intr_lock); 1360 #endif 1361 1362 pool_cache_destroy(sc->sc_xferpool); 1363 1364 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1365 1366 return rv; 1367 } 1368 1369 1370 int 1371 ehci_activate(device_t self, enum devact act) 1372 { 1373 struct ehci_softc *sc = device_private(self); 1374 1375 switch (act) { 1376 case DVACT_DEACTIVATE: 1377 sc->sc_dying = 1; 1378 return 0; 1379 default: 1380 return EOPNOTSUPP; 1381 } 1382 } 1383 1384 /* 1385 * Handle suspend/resume. 1386 * 1387 * We need to switch to polling mode here, because this routine is 1388 * called from an interrupt context. This is all right since we 1389 * are almost suspended anyway. 1390 * 1391 * Note that this power handler isn't to be registered directly; the 1392 * bus glue needs to call out to it. 1393 */ 1394 bool 1395 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1396 { 1397 ehci_softc_t *sc = device_private(dv); 1398 int i; 1399 uint32_t cmd, hcr; 1400 1401 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1402 1403 mutex_spin_enter(&sc->sc_intr_lock); 1404 sc->sc_bus.ub_usepolling++; 1405 mutex_spin_exit(&sc->sc_intr_lock); 1406 1407 for (i = 1; i <= sc->sc_noport; i++) { 1408 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1409 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1410 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1411 } 1412 1413 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1414 1415 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1416 EOWRITE4(sc, EHCI_USBCMD, cmd); 1417 1418 for (i = 0; i < 100; i++) { 1419 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1420 if (hcr == 0) 1421 break; 1422 1423 usb_delay_ms(&sc->sc_bus, 1); 1424 } 1425 if (hcr != 0) 1426 printf("%s: reset timeout\n", device_xname(dv)); 1427 1428 cmd &= ~EHCI_CMD_RS; 1429 EOWRITE4(sc, EHCI_USBCMD, cmd); 1430 1431 for (i = 0; i < 100; i++) { 1432 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1433 if (hcr == EHCI_STS_HCH) 1434 break; 1435 1436 usb_delay_ms(&sc->sc_bus, 1); 1437 } 1438 if (hcr != EHCI_STS_HCH) 1439 printf("%s: config timeout\n", device_xname(dv)); 1440 1441 mutex_spin_enter(&sc->sc_intr_lock); 1442 sc->sc_bus.ub_usepolling--; 1443 mutex_spin_exit(&sc->sc_intr_lock); 1444 1445 return true; 1446 } 1447 1448 bool 1449 ehci_resume(device_t dv, const pmf_qual_t *qual) 1450 { 1451 ehci_softc_t *sc = device_private(dv); 1452 int i; 1453 uint32_t cmd, hcr; 1454 1455 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1456 1457 /* restore things in case the bios sucks */ 1458 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1459 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1460 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1461 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1462 1463 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1464 1465 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1466 1467 hcr = 0; 1468 for (i = 1; i <= sc->sc_noport; i++) { 1469 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1470 if ((cmd & EHCI_PS_PO) == 0 && 1471 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1472 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1473 hcr = 1; 1474 } 1475 } 1476 1477 if (hcr) { 1478 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1479 1480 for (i = 1; i <= sc->sc_noport; i++) { 1481 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1482 if ((cmd & EHCI_PS_PO) == 0 && 1483 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1484 EOWRITE4(sc, EHCI_PORTSC(i), 1485 cmd & ~EHCI_PS_FPR); 1486 } 1487 } 1488 1489 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1490 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1491 1492 for (i = 0; i < 100; i++) { 1493 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1494 if (hcr != EHCI_STS_HCH) 1495 break; 1496 1497 usb_delay_ms(&sc->sc_bus, 1); 1498 } 1499 if (hcr == EHCI_STS_HCH) 1500 printf("%s: config timeout\n", device_xname(dv)); 1501 1502 return true; 1503 } 1504 1505 /* 1506 * Shut down the controller when the system is going down. 1507 */ 1508 bool 1509 ehci_shutdown(device_t self, int flags) 1510 { 1511 ehci_softc_t *sc = device_private(self); 1512 1513 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1514 1515 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1516 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1517 return true; 1518 } 1519 1520 Static struct usbd_xfer * 1521 ehci_allocx(struct usbd_bus *bus) 1522 { 1523 struct ehci_softc *sc = bus->ub_hcpriv; 1524 struct usbd_xfer *xfer; 1525 1526 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1527 if (xfer != NULL) { 1528 memset(xfer, 0, sizeof(struct ehci_xfer)); 1529 #ifdef DIAGNOSTIC 1530 EXFER(xfer)->ex_isdone = true; 1531 xfer->ux_state = XFER_BUSY; 1532 #endif 1533 } 1534 return xfer; 1535 } 1536 1537 Static void 1538 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1539 { 1540 struct ehci_softc *sc = bus->ub_hcpriv; 1541 1542 KASSERT(xfer->ux_state == XFER_BUSY); 1543 KASSERT(EXFER(xfer)->ex_isdone); 1544 #ifdef DIAGNOSTIC 1545 xfer->ux_state = XFER_FREE; 1546 #endif 1547 pool_cache_put(sc->sc_xferpool, xfer); 1548 } 1549 1550 Static void 1551 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1552 { 1553 struct ehci_softc *sc = bus->ub_hcpriv; 1554 1555 *lock = &sc->sc_lock; 1556 } 1557 1558 Static void 1559 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1560 { 1561 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1562 1563 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1564 1565 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1566 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1567 #ifdef EHCI_DEBUG 1568 if (ehcidebug) 1569 usbd_dump_pipe(pipe); 1570 #endif 1571 epipe->nexttoggle = 0; 1572 } 1573 1574 Static void 1575 ehci_noop(struct usbd_pipe *pipe) 1576 { 1577 } 1578 1579 #ifdef EHCI_DEBUG 1580 /* 1581 * Unused function - this is meant to be called from a kernel 1582 * debugger. 1583 */ 1584 void 1585 ehci_dump(void) 1586 { 1587 ehci_softc_t *sc = theehci; 1588 int i; 1589 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1590 EOREAD4(sc, EHCI_USBCMD), 1591 EOREAD4(sc, EHCI_USBSTS), 1592 EOREAD4(sc, EHCI_USBINTR)); 1593 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1594 EOREAD4(sc, EHCI_FRINDEX), 1595 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1596 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1597 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1598 for (i = 1; i <= sc->sc_noport; i++) 1599 printf("port %d status=0x%08x\n", i, 1600 EOREAD4(sc, EHCI_PORTSC(i))); 1601 } 1602 1603 Static void 1604 ehci_dump_regs(ehci_softc_t *sc) 1605 { 1606 int i; 1607 1608 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1609 1610 USBHIST_LOG(ehcidebug, 1611 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1612 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1613 EOREAD4(sc, EHCI_USBINTR), 0); 1614 USBHIST_LOG(ehcidebug, 1615 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1616 "async = 0x%08x", 1617 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1618 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1619 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1620 for (i = 1; i <= sc->sc_noport; i += 2) { 1621 if (i == sc->sc_noport) { 1622 USBHIST_LOG(ehcidebug, 1623 "port %d status = 0x%08x", i, 1624 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1625 } else { 1626 USBHIST_LOG(ehcidebug, 1627 "port %d status = 0x%08x port %d status = 0x%08x", 1628 i, EOREAD4(sc, EHCI_PORTSC(i)), 1629 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1630 } 1631 } 1632 } 1633 1634 #ifdef EHCI_DEBUG 1635 #define ehci_dump_link(link, type) do { \ 1636 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1637 link, \ 1638 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1639 if (type) { \ 1640 USBHIST_LOG(ehcidebug, \ 1641 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1642 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1643 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1644 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1645 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1646 } \ 1647 } while(0) 1648 #else 1649 #define ehci_dump_link(link, type) 1650 #endif 1651 1652 Static void 1653 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1654 { 1655 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1656 int i; 1657 uint32_t stop = 0; 1658 1659 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1660 ehci_dump_sqtd(sqtd); 1661 usb_syncmem(&sqtd->dma, 1662 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1663 sizeof(sqtd->qtd), 1664 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1665 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1666 usb_syncmem(&sqtd->dma, 1667 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1668 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1669 } 1670 if (!stop) 1671 USBHIST_LOG(ehcidebug, 1672 "dump aborted, too many TDs", 0, 0, 0, 0); 1673 } 1674 1675 Static void 1676 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1677 { 1678 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1679 1680 usb_syncmem(&sqtd->dma, sqtd->offs, 1681 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1682 1683 USBHIST_LOGN(ehcidebug, 10, 1684 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1685 ehci_dump_qtd(&sqtd->qtd); 1686 1687 usb_syncmem(&sqtd->dma, sqtd->offs, 1688 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1689 } 1690 1691 Static void 1692 ehci_dump_qtd(ehci_qtd_t *qtd) 1693 { 1694 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1695 1696 #ifdef USBHIST 1697 uint32_t s = le32toh(qtd->qtd_status); 1698 #endif 1699 1700 USBHIST_LOGN(ehcidebug, 10, 1701 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1702 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1703 USBHIST_LOGN(ehcidebug, 10, 1704 " toggle = %d ioc = %d bytes = %#x " 1705 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1706 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1707 USBHIST_LOGN(ehcidebug, 10, 1708 " cerr = %d pid = %d stat = %x", 1709 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1710 0); 1711 USBHIST_LOGN(ehcidebug, 10, 1712 "active =%d halted=%d buferr=%d babble=%d", 1713 s & EHCI_QTD_ACTIVE ? 1 : 0, 1714 s & EHCI_QTD_HALTED ? 1 : 0, 1715 s & EHCI_QTD_BUFERR ? 1 : 0, 1716 s & EHCI_QTD_BABBLE ? 1 : 0); 1717 USBHIST_LOGN(ehcidebug, 10, 1718 "xacterr=%d missed=%d split =%d ping =%d", 1719 s & EHCI_QTD_XACTERR ? 1 : 0, 1720 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1721 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1722 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1723 USBHIST_LOGN(ehcidebug, 10, 1724 "buffer[0] = %#x buffer[1] = %#x " 1725 "buffer[2] = %#x buffer[3] = %#x", 1726 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1727 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1728 USBHIST_LOGN(ehcidebug, 10, 1729 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1730 } 1731 1732 Static void 1733 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1734 { 1735 #ifdef USBHIST 1736 ehci_qh_t *qh = &sqh->qh; 1737 ehci_link_t link; 1738 #endif 1739 uint32_t endp, endphub; 1740 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1741 1742 usb_syncmem(&sqh->dma, sqh->offs, 1743 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1744 1745 USBHIST_LOGN(ehcidebug, 10, 1746 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1747 link = le32toh(qh->qh_link); 1748 ehci_dump_link(link, true); 1749 1750 endp = le32toh(qh->qh_endp); 1751 USBHIST_LOGN(ehcidebug, 10, 1752 " endp = %#x", endp, 0, 0, 0); 1753 USBHIST_LOGN(ehcidebug, 10, 1754 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1755 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1756 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1757 USBHIST_LOGN(ehcidebug, 10, 1758 " dtc = %d hrecl = %d", 1759 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1760 USBHIST_LOGN(ehcidebug, 10, 1761 " ctl = %d nrl = %d mpl = %#x(%d)", 1762 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1763 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1764 1765 endphub = le32toh(qh->qh_endphub); 1766 USBHIST_LOGN(ehcidebug, 10, 1767 " endphub = %#x", endphub, 0, 0, 0); 1768 USBHIST_LOGN(ehcidebug, 10, 1769 " smask = 0x%02x cmask = 0x%02x", 1770 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1771 USBHIST_LOGN(ehcidebug, 10, 1772 " huba = 0x%02x port = %d mult = %d", 1773 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1774 EHCI_QH_GET_MULT(endphub), 0); 1775 1776 link = le32toh(qh->qh_curqtd); 1777 ehci_dump_link(link, false); 1778 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1779 ehci_dump_qtd(&qh->qh_qtd); 1780 1781 usb_syncmem(&sqh->dma, sqh->offs, 1782 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1783 } 1784 1785 Static void 1786 ehci_dump_itd(struct ehci_soft_itd *itd) 1787 { 1788 ehci_isoc_trans_t t; 1789 ehci_isoc_bufr_ptr_t b, b2, b3; 1790 int i; 1791 1792 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1793 1794 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1795 0, 0); 1796 1797 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1798 t = le32toh(itd->itd.itd_ctl[i]); 1799 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1800 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1801 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1802 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1803 EHCI_ITD_GET_OFFS(t), 0); 1804 } 1805 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1806 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1807 USBHIST_LOG(ehcidebug, " %x", 1808 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1809 1810 b = le32toh(itd->itd.itd_bufr[0]); 1811 b2 = le32toh(itd->itd.itd_bufr[1]); 1812 b3 = le32toh(itd->itd.itd_bufr[2]); 1813 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1814 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1815 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1816 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1817 } 1818 1819 Static void 1820 ehci_dump_sitd(struct ehci_soft_itd *itd) 1821 { 1822 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1823 1824 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1825 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1826 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1827 itd->xfer_next, itd->physaddr, itd->slot, 0); 1828 } 1829 1830 Static void 1831 ehci_dump_exfer(struct ehci_xfer *ex) 1832 { 1833 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1834 1835 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1836 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1837 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1838 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1839 } 1840 #endif 1841 1842 Static usbd_status 1843 ehci_open(struct usbd_pipe *pipe) 1844 { 1845 struct usbd_device *dev = pipe->up_dev; 1846 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1847 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1848 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1849 uint8_t addr = dev->ud_addr; 1850 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1851 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1852 ehci_soft_qh_t *sqh; 1853 usbd_status err; 1854 int ival, speed, naks; 1855 int hshubaddr, hshubport; 1856 1857 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1858 1859 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1860 pipe, addr, ed->bEndpointAddress, rhaddr); 1861 1862 if (dev->ud_myhsport) { 1863 /* 1864 * When directly attached FS/LS device while doing embedded 1865 * transaction translations and we are the hub, set the hub 1866 * address to 0 (us). 1867 */ 1868 if (!(sc->sc_flags & EHCIF_ETTF) 1869 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1870 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1871 } else { 1872 hshubaddr = 0; 1873 } 1874 hshubport = dev->ud_myhsport->up_portno; 1875 } else { 1876 hshubaddr = 0; 1877 hshubport = 0; 1878 } 1879 1880 if (sc->sc_dying) 1881 return USBD_IOERROR; 1882 1883 /* toggle state needed for bulk endpoints */ 1884 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1885 1886 if (addr == rhaddr) { 1887 switch (ed->bEndpointAddress) { 1888 case USB_CONTROL_ENDPOINT: 1889 pipe->up_methods = &roothub_ctrl_methods; 1890 break; 1891 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1892 pipe->up_methods = &ehci_root_intr_methods; 1893 break; 1894 default: 1895 USBHIST_LOG(ehcidebug, 1896 "bad bEndpointAddress 0x%02x", 1897 ed->bEndpointAddress, 0, 0, 0); 1898 return USBD_INVAL; 1899 } 1900 return USBD_NORMAL_COMPLETION; 1901 } 1902 1903 /* XXX All this stuff is only valid for async. */ 1904 switch (dev->ud_speed) { 1905 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1906 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1907 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1908 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1909 } 1910 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1911 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1912 hshubaddr, hshubport, 0, 0); 1913 return USBD_INVAL; 1914 } 1915 1916 /* 1917 * For interrupt transfer, nak throttling must be disabled, but for 1918 * the other transfer type, nak throttling should be enabled from the 1919 * viewpoint that avoids the memory thrashing. 1920 */ 1921 naks = (xfertype == UE_INTERRUPT) ? 0 1922 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1923 1924 /* Allocate sqh for everything, save isoc xfers */ 1925 if (xfertype != UE_ISOCHRONOUS) { 1926 sqh = ehci_alloc_sqh(sc); 1927 if (sqh == NULL) 1928 return USBD_NOMEM; 1929 /* qh_link filled when the QH is added */ 1930 sqh->qh.qh_endp = htole32( 1931 EHCI_QH_SET_ADDR(addr) | 1932 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1933 EHCI_QH_SET_EPS(speed) | 1934 EHCI_QH_DTC | 1935 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1936 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1937 EHCI_QH_CTL : 0) | 1938 EHCI_QH_SET_NRL(naks) 1939 ); 1940 sqh->qh.qh_endphub = htole32( 1941 EHCI_QH_SET_MULT(1) | 1942 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1943 ); 1944 if (speed != EHCI_QH_SPEED_HIGH) 1945 sqh->qh.qh_endphub |= htole32( 1946 EHCI_QH_SET_PORT(hshubport) | 1947 EHCI_QH_SET_HUBA(hshubaddr) | 1948 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1949 ); 1950 sqh->qh.qh_curqtd = EHCI_NULL; 1951 /* Fill the overlay qTD */ 1952 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1953 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1954 sqh->qh.qh_qtd.qtd_status = htole32(0); 1955 1956 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1957 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1958 epipe->sqh = sqh; 1959 } else { 1960 sqh = NULL; 1961 } /*xfertype == UE_ISOC*/ 1962 1963 switch (xfertype) { 1964 case UE_CONTROL: 1965 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1966 0, &epipe->ctrl.reqdma); 1967 #ifdef EHCI_DEBUG 1968 if (err) 1969 printf("ehci_open: usb_allocmem()=%d\n", err); 1970 #endif 1971 if (err) 1972 goto bad; 1973 pipe->up_methods = &ehci_device_ctrl_methods; 1974 mutex_enter(&sc->sc_lock); 1975 ehci_add_qh(sc, sqh, sc->sc_async_head); 1976 mutex_exit(&sc->sc_lock); 1977 break; 1978 case UE_BULK: 1979 pipe->up_methods = &ehci_device_bulk_methods; 1980 mutex_enter(&sc->sc_lock); 1981 ehci_add_qh(sc, sqh, sc->sc_async_head); 1982 mutex_exit(&sc->sc_lock); 1983 break; 1984 case UE_INTERRUPT: 1985 pipe->up_methods = &ehci_device_intr_methods; 1986 ival = pipe->up_interval; 1987 if (ival == USBD_DEFAULT_INTERVAL) { 1988 if (speed == EHCI_QH_SPEED_HIGH) { 1989 if (ed->bInterval > 16) { 1990 /* 1991 * illegal with high-speed, but there 1992 * were documentation bugs in the spec, 1993 * so be generous 1994 */ 1995 ival = 256; 1996 } else 1997 ival = (1 << (ed->bInterval - 1)) / 8; 1998 } else 1999 ival = ed->bInterval; 2000 } 2001 err = ehci_device_setintr(sc, sqh, ival); 2002 if (err) 2003 goto bad; 2004 break; 2005 case UE_ISOCHRONOUS: 2006 if (speed == EHCI_QH_SPEED_HIGH) 2007 pipe->up_methods = &ehci_device_isoc_methods; 2008 else 2009 pipe->up_methods = &ehci_device_fs_isoc_methods; 2010 if (ed->bInterval == 0 || ed->bInterval > 16) { 2011 printf("ehci: opening pipe with invalid bInterval\n"); 2012 err = USBD_INVAL; 2013 goto bad; 2014 } 2015 if (UGETW(ed->wMaxPacketSize) == 0) { 2016 printf("ehci: zero length endpoint open request\n"); 2017 err = USBD_INVAL; 2018 goto bad; 2019 } 2020 epipe->isoc.next_frame = 0; 2021 epipe->isoc.cur_xfers = 0; 2022 break; 2023 default: 2024 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2025 err = USBD_INVAL; 2026 goto bad; 2027 } 2028 return USBD_NORMAL_COMPLETION; 2029 2030 bad: 2031 if (sqh != NULL) 2032 ehci_free_sqh(sc, sqh); 2033 return err; 2034 } 2035 2036 /* 2037 * Add an ED to the schedule. Called with USB lock held. 2038 */ 2039 Static void 2040 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2041 { 2042 2043 KASSERT(mutex_owned(&sc->sc_lock)); 2044 2045 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2046 2047 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2048 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2049 2050 sqh->next = head->next; 2051 sqh->qh.qh_link = head->qh.qh_link; 2052 2053 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2054 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2055 2056 head->next = sqh; 2057 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2058 2059 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2060 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2061 2062 #ifdef EHCI_DEBUG 2063 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2064 ehci_dump_sqh(sqh); 2065 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2066 #endif 2067 } 2068 2069 /* 2070 * Remove an ED from the schedule. Called with USB lock held. 2071 */ 2072 Static void 2073 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2074 { 2075 ehci_soft_qh_t *p; 2076 2077 KASSERT(mutex_owned(&sc->sc_lock)); 2078 2079 /* XXX */ 2080 for (p = head; p != NULL && p->next != sqh; p = p->next) 2081 ; 2082 if (p == NULL) 2083 panic("ehci_rem_qh: ED not found"); 2084 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2085 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2086 p->next = sqh->next; 2087 p->qh.qh_link = sqh->qh.qh_link; 2088 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2089 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2090 2091 ehci_sync_hc(sc); 2092 } 2093 2094 Static void 2095 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2096 { 2097 int i; 2098 uint32_t status; 2099 2100 /* Save toggle bit and ping status. */ 2101 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2102 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2103 status = sqh->qh.qh_qtd.qtd_status & 2104 htole32(EHCI_QTD_TOGGLE_MASK | 2105 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2106 /* Set HALTED to make hw leave it alone. */ 2107 sqh->qh.qh_qtd.qtd_status = 2108 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2109 usb_syncmem(&sqh->dma, 2110 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2111 sizeof(sqh->qh.qh_qtd.qtd_status), 2112 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2113 sqh->qh.qh_curqtd = 0; 2114 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2115 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2116 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2117 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2118 sqh->sqtd = sqtd; 2119 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2120 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2121 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2122 sqh->qh.qh_qtd.qtd_status = status; 2123 usb_syncmem(&sqh->dma, 2124 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2125 sizeof(sqh->qh.qh_qtd.qtd_status), 2126 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2127 } 2128 2129 /* 2130 * Ensure that the HC has released all references to the QH. We do this 2131 * by asking for a Async Advance Doorbell interrupt and then we wait for 2132 * the interrupt. 2133 * To make this easier we first obtain exclusive use of the doorbell. 2134 */ 2135 Static void 2136 ehci_sync_hc(ehci_softc_t *sc) 2137 { 2138 int error __diagused; 2139 2140 KASSERT(mutex_owned(&sc->sc_lock)); 2141 2142 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2143 2144 if (sc->sc_dying) { 2145 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2146 return; 2147 } 2148 /* ask for doorbell */ 2149 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2150 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2151 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2152 2153 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2154 2155 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2156 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2157 #ifdef DIAGNOSTIC 2158 if (error) 2159 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2160 #endif 2161 } 2162 2163 Static void 2164 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2165 { 2166 struct ehci_soft_itd *itd, *prev; 2167 2168 prev = NULL; 2169 2170 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2171 panic("ehci isoc xfer being freed, but with no itd chain"); 2172 2173 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2174 prev = itd->frame_list.prev; 2175 /* Unlink itd from hardware chain, or frame array */ 2176 if (prev == NULL) { /* We're at the table head */ 2177 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2178 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2179 usb_syncmem(&sc->sc_fldma, 2180 sizeof(ehci_link_t) * itd->slot, 2181 sizeof(ehci_link_t), 2182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2183 2184 if (itd->frame_list.next != NULL) 2185 itd->frame_list.next->frame_list.prev = NULL; 2186 } else { 2187 /* XXX this part is untested... */ 2188 prev->itd.itd_next = itd->itd.itd_next; 2189 usb_syncmem(&itd->dma, 2190 itd->offs + offsetof(ehci_itd_t, itd_next), 2191 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2192 2193 prev->frame_list.next = itd->frame_list.next; 2194 if (itd->frame_list.next != NULL) 2195 itd->frame_list.next->frame_list.prev = prev; 2196 } 2197 } 2198 2199 prev = NULL; 2200 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2201 if (prev != NULL) 2202 ehci_free_itd(sc, prev); 2203 prev = itd; 2204 } 2205 if (prev) 2206 ehci_free_itd(sc, prev); 2207 exfer->ex_itdstart = NULL; 2208 exfer->ex_itdend = NULL; 2209 } 2210 2211 Static void 2212 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2213 { 2214 struct ehci_soft_sitd *sitd, *prev; 2215 2216 prev = NULL; 2217 2218 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2219 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2220 2221 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2222 prev = sitd->frame_list.prev; 2223 /* Unlink sitd from hardware chain, or frame array */ 2224 if (prev == NULL) { /* We're at the table head */ 2225 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2226 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2227 usb_syncmem(&sc->sc_fldma, 2228 sizeof(ehci_link_t) * sitd->slot, 2229 sizeof(ehci_link_t), 2230 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2231 2232 if (sitd->frame_list.next != NULL) 2233 sitd->frame_list.next->frame_list.prev = NULL; 2234 } else { 2235 /* XXX this part is untested... */ 2236 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2237 usb_syncmem(&sitd->dma, 2238 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2239 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2240 2241 prev->frame_list.next = sitd->frame_list.next; 2242 if (sitd->frame_list.next != NULL) 2243 sitd->frame_list.next->frame_list.prev = prev; 2244 } 2245 } 2246 2247 prev = NULL; 2248 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2249 if (prev != NULL) 2250 ehci_free_sitd(sc, prev); 2251 prev = sitd; 2252 } 2253 if (prev) 2254 ehci_free_sitd(sc, prev); 2255 exfer->ex_sitdstart = NULL; 2256 exfer->ex_sitdend = NULL; 2257 } 2258 2259 /***********/ 2260 2261 Static int 2262 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2263 void *buf, int buflen) 2264 { 2265 ehci_softc_t *sc = bus->ub_hcpriv; 2266 usb_hub_descriptor_t hubd; 2267 usb_port_status_t ps; 2268 uint16_t len, value, index; 2269 int l, totlen = 0; 2270 int port, i; 2271 uint32_t v; 2272 2273 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2274 2275 if (sc->sc_dying) 2276 return -1; 2277 2278 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2279 req->bmRequestType, req->bRequest, 0, 0); 2280 2281 len = UGETW(req->wLength); 2282 value = UGETW(req->wValue); 2283 index = UGETW(req->wIndex); 2284 2285 #define C(x,y) ((x) | ((y) << 8)) 2286 switch (C(req->bRequest, req->bmRequestType)) { 2287 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2288 if (len == 0) 2289 break; 2290 switch (value) { 2291 case C(0, UDESC_DEVICE): { 2292 usb_device_descriptor_t devd; 2293 totlen = min(buflen, sizeof(devd)); 2294 memcpy(&devd, buf, totlen); 2295 USETW(devd.idVendor, sc->sc_id_vendor); 2296 memcpy(buf, &devd, totlen); 2297 break; 2298 2299 } 2300 #define sd ((usb_string_descriptor_t *)buf) 2301 case C(1, UDESC_STRING): 2302 /* Vendor */ 2303 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2304 break; 2305 case C(2, UDESC_STRING): 2306 /* Product */ 2307 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2308 break; 2309 #undef sd 2310 default: 2311 /* default from usbroothub */ 2312 return buflen; 2313 } 2314 break; 2315 2316 /* Hub requests */ 2317 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2318 break; 2319 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2320 USBHIST_LOG(ehcidebug, 2321 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2322 0, 0); 2323 if (index < 1 || index > sc->sc_noport) { 2324 return -1; 2325 } 2326 port = EHCI_PORTSC(index); 2327 v = EOREAD4(sc, port); 2328 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2329 v &= ~EHCI_PS_CLEAR; 2330 switch (value) { 2331 case UHF_PORT_ENABLE: 2332 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2333 break; 2334 case UHF_PORT_SUSPEND: 2335 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2336 break; 2337 v &= ~EHCI_PS_SUSP; 2338 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2339 /* see USB2 spec ch. 7.1.7.7 */ 2340 usb_delay_ms(&sc->sc_bus, 20); 2341 EOWRITE4(sc, port, v); 2342 usb_delay_ms(&sc->sc_bus, 2); 2343 #ifdef DEBUG 2344 v = EOREAD4(sc, port); 2345 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2346 printf("ehci: resume failed: %x\n", v); 2347 #endif 2348 break; 2349 case UHF_PORT_POWER: 2350 if (sc->sc_hasppc) 2351 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2352 break; 2353 case UHF_PORT_TEST: 2354 USBHIST_LOG(ehcidebug, "clear port test " 2355 "%d", index, 0, 0, 0); 2356 break; 2357 case UHF_PORT_INDICATOR: 2358 USBHIST_LOG(ehcidebug, "clear port ind " 2359 "%d", index, 0, 0, 0); 2360 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2361 break; 2362 case UHF_C_PORT_CONNECTION: 2363 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2364 break; 2365 case UHF_C_PORT_ENABLE: 2366 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2367 break; 2368 case UHF_C_PORT_SUSPEND: 2369 /* how? */ 2370 break; 2371 case UHF_C_PORT_OVER_CURRENT: 2372 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2373 break; 2374 case UHF_C_PORT_RESET: 2375 sc->sc_isreset[index] = 0; 2376 break; 2377 default: 2378 return -1; 2379 } 2380 #if 0 2381 switch(value) { 2382 case UHF_C_PORT_CONNECTION: 2383 case UHF_C_PORT_ENABLE: 2384 case UHF_C_PORT_SUSPEND: 2385 case UHF_C_PORT_OVER_CURRENT: 2386 case UHF_C_PORT_RESET: 2387 default: 2388 break; 2389 } 2390 #endif 2391 break; 2392 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2393 if (len == 0) 2394 break; 2395 if ((value & 0xff) != 0) { 2396 return -1; 2397 } 2398 totlen = min(buflen, sizeof(hubd)); 2399 memcpy(&hubd, buf, totlen); 2400 hubd.bNbrPorts = sc->sc_noport; 2401 v = EOREAD4(sc, EHCI_HCSPARAMS); 2402 USETW(hubd.wHubCharacteristics, 2403 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2404 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2405 ? UHD_PORT_IND : 0); 2406 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2407 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2408 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2409 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2410 totlen = min(totlen, hubd.bDescLength); 2411 memcpy(buf, &hubd, totlen); 2412 break; 2413 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2414 if (len != 4) { 2415 return -1; 2416 } 2417 memset(buf, 0, len); /* ? XXX */ 2418 totlen = len; 2419 break; 2420 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2421 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2422 if (index < 1 || index > sc->sc_noport) { 2423 return -1; 2424 } 2425 if (len != 4) { 2426 return -1; 2427 } 2428 v = EOREAD4(sc, EHCI_PORTSC(index)); 2429 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2430 2431 i = UPS_HIGH_SPEED; 2432 if (sc->sc_flags & EHCIF_ETTF) { 2433 /* 2434 * If we are doing embedded transaction translation, 2435 * then directly attached LS/FS devices are reset by 2436 * the EHCI controller itself. PSPD is encoded 2437 * the same way as in USBSTATUS. 2438 */ 2439 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2440 } 2441 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2442 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2443 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2444 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2445 if (v & EHCI_PS_PR) i |= UPS_RESET; 2446 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2447 if (sc->sc_vendor_port_status) 2448 i = sc->sc_vendor_port_status(sc, v, i); 2449 USETW(ps.wPortStatus, i); 2450 i = 0; 2451 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2452 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2453 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2454 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2455 USETW(ps.wPortChange, i); 2456 totlen = min(len, sizeof(ps)); 2457 memcpy(buf, &ps, totlen); 2458 break; 2459 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2460 return -1; 2461 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2462 break; 2463 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2464 if (index < 1 || index > sc->sc_noport) { 2465 return -1; 2466 } 2467 port = EHCI_PORTSC(index); 2468 v = EOREAD4(sc, port); 2469 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2470 v &= ~EHCI_PS_CLEAR; 2471 switch(value) { 2472 case UHF_PORT_ENABLE: 2473 EOWRITE4(sc, port, v | EHCI_PS_PE); 2474 break; 2475 case UHF_PORT_SUSPEND: 2476 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2477 break; 2478 case UHF_PORT_RESET: 2479 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2480 if (EHCI_PS_IS_LOWSPEED(v) 2481 && sc->sc_ncomp > 0 2482 && !(sc->sc_flags & EHCIF_ETTF)) { 2483 /* 2484 * Low speed device on non-ETTF controller or 2485 * unaccompanied controller, give up ownership. 2486 */ 2487 ehci_disown(sc, index, 1); 2488 break; 2489 } 2490 /* Start reset sequence. */ 2491 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2492 EOWRITE4(sc, port, v | EHCI_PS_PR); 2493 /* Wait for reset to complete. */ 2494 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2495 if (sc->sc_dying) { 2496 return -1; 2497 } 2498 /* 2499 * An embedded transaction translator will automatically 2500 * terminate the reset sequence so there's no need to 2501 * it. 2502 */ 2503 v = EOREAD4(sc, port); 2504 if (v & EHCI_PS_PR) { 2505 /* Terminate reset sequence. */ 2506 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2507 /* Wait for HC to complete reset. */ 2508 usb_delay_ms(&sc->sc_bus, 2509 EHCI_PORT_RESET_COMPLETE); 2510 if (sc->sc_dying) { 2511 return -1; 2512 } 2513 } 2514 2515 v = EOREAD4(sc, port); 2516 USBHIST_LOG(ehcidebug, 2517 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2518 if (v & EHCI_PS_PR) { 2519 printf("%s: port reset timeout\n", 2520 device_xname(sc->sc_dev)); 2521 return USBD_TIMEOUT; 2522 } 2523 if (!(v & EHCI_PS_PE)) { 2524 /* Not a high speed device, give up ownership.*/ 2525 ehci_disown(sc, index, 0); 2526 break; 2527 } 2528 sc->sc_isreset[index] = 1; 2529 USBHIST_LOG(ehcidebug, 2530 "ehci port %d reset, status = 0x%08x", index, v, 0, 2531 0); 2532 break; 2533 case UHF_PORT_POWER: 2534 USBHIST_LOG(ehcidebug, 2535 "set port power %d (has PPC = %d)", index, 2536 sc->sc_hasppc, 0, 0); 2537 if (sc->sc_hasppc) 2538 EOWRITE4(sc, port, v | EHCI_PS_PP); 2539 break; 2540 case UHF_PORT_TEST: 2541 USBHIST_LOG(ehcidebug, "set port test %d", 2542 index, 0, 0, 0); 2543 break; 2544 case UHF_PORT_INDICATOR: 2545 USBHIST_LOG(ehcidebug, "set port ind %d", 2546 index, 0, 0, 0); 2547 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2548 break; 2549 default: 2550 return -1; 2551 } 2552 break; 2553 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2554 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2555 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2556 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2557 break; 2558 default: 2559 /* default from usbroothub */ 2560 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2561 buflen, 0, 0, 0); 2562 2563 return buflen; 2564 } 2565 2566 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2567 2568 return totlen; 2569 } 2570 2571 Static void 2572 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2573 { 2574 int port; 2575 uint32_t v; 2576 2577 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2578 2579 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2580 #ifdef DIAGNOSTIC 2581 if (sc->sc_npcomp != 0) { 2582 int i = (index-1) / sc->sc_npcomp; 2583 if (i >= sc->sc_ncomp) 2584 printf("%s: strange port\n", 2585 device_xname(sc->sc_dev)); 2586 else 2587 printf("%s: handing over %s speed device on " 2588 "port %d to %s\n", 2589 device_xname(sc->sc_dev), 2590 lowspeed ? "low" : "full", 2591 index, device_xname(sc->sc_comps[i])); 2592 } else { 2593 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2594 } 2595 #endif 2596 port = EHCI_PORTSC(index); 2597 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2598 EOWRITE4(sc, port, v | EHCI_PS_PO); 2599 } 2600 2601 Static usbd_status 2602 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2603 { 2604 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2605 usbd_status err; 2606 2607 /* Insert last in queue. */ 2608 mutex_enter(&sc->sc_lock); 2609 err = usb_insert_transfer(xfer); 2610 mutex_exit(&sc->sc_lock); 2611 if (err) 2612 return err; 2613 2614 /* Pipe isn't running, start first */ 2615 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2616 } 2617 2618 Static usbd_status 2619 ehci_root_intr_start(struct usbd_xfer *xfer) 2620 { 2621 struct usbd_pipe *pipe = xfer->ux_pipe; 2622 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2623 2624 if (sc->sc_dying) 2625 return USBD_IOERROR; 2626 2627 mutex_enter(&sc->sc_lock); 2628 sc->sc_intrxfer = xfer; 2629 mutex_exit(&sc->sc_lock); 2630 2631 return USBD_IN_PROGRESS; 2632 } 2633 2634 /* Abort a root interrupt request. */ 2635 Static void 2636 ehci_root_intr_abort(struct usbd_xfer *xfer) 2637 { 2638 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2639 2640 KASSERT(mutex_owned(&sc->sc_lock)); 2641 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2642 2643 sc->sc_intrxfer = NULL; 2644 2645 xfer->ux_status = USBD_CANCELLED; 2646 usb_transfer_complete(xfer); 2647 } 2648 2649 /* Close the root pipe. */ 2650 Static void 2651 ehci_root_intr_close(struct usbd_pipe *pipe) 2652 { 2653 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2654 2655 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2656 2657 KASSERT(mutex_owned(&sc->sc_lock)); 2658 2659 sc->sc_intrxfer = NULL; 2660 } 2661 2662 Static void 2663 ehci_root_intr_done(struct usbd_xfer *xfer) 2664 { 2665 xfer->ux_hcpriv = NULL; 2666 } 2667 2668 /************************/ 2669 2670 Static ehci_soft_qh_t * 2671 ehci_alloc_sqh(ehci_softc_t *sc) 2672 { 2673 ehci_soft_qh_t *sqh; 2674 usbd_status err; 2675 int i, offs; 2676 usb_dma_t dma; 2677 2678 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2679 2680 if (sc->sc_freeqhs == NULL) { 2681 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2682 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2683 EHCI_PAGE_SIZE, &dma); 2684 #ifdef EHCI_DEBUG 2685 if (err) 2686 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2687 #endif 2688 if (err) 2689 return NULL; 2690 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2691 offs = i * EHCI_SQH_SIZE; 2692 sqh = KERNADDR(&dma, offs); 2693 sqh->physaddr = DMAADDR(&dma, offs); 2694 sqh->dma = dma; 2695 sqh->offs = offs; 2696 sqh->next = sc->sc_freeqhs; 2697 sc->sc_freeqhs = sqh; 2698 } 2699 } 2700 sqh = sc->sc_freeqhs; 2701 sc->sc_freeqhs = sqh->next; 2702 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2703 sqh->next = NULL; 2704 return sqh; 2705 } 2706 2707 Static void 2708 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2709 { 2710 sqh->next = sc->sc_freeqhs; 2711 sc->sc_freeqhs = sqh; 2712 } 2713 2714 Static ehci_soft_qtd_t * 2715 ehci_alloc_sqtd(ehci_softc_t *sc) 2716 { 2717 ehci_soft_qtd_t *sqtd = NULL; 2718 usbd_status err; 2719 int i, offs; 2720 usb_dma_t dma; 2721 2722 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2723 2724 if (sc->sc_freeqtds == NULL) { 2725 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2726 2727 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2728 EHCI_PAGE_SIZE, &dma); 2729 #ifdef EHCI_DEBUG 2730 if (err) 2731 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2732 #endif 2733 if (err) 2734 goto done; 2735 2736 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2737 offs = i * EHCI_SQTD_SIZE; 2738 sqtd = KERNADDR(&dma, offs); 2739 sqtd->physaddr = DMAADDR(&dma, offs); 2740 sqtd->dma = dma; 2741 sqtd->offs = offs; 2742 2743 sqtd->nextqtd = sc->sc_freeqtds; 2744 sc->sc_freeqtds = sqtd; 2745 } 2746 } 2747 2748 sqtd = sc->sc_freeqtds; 2749 sc->sc_freeqtds = sqtd->nextqtd; 2750 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2751 sqtd->nextqtd = NULL; 2752 sqtd->xfer = NULL; 2753 2754 done: 2755 return sqtd; 2756 } 2757 2758 Static void 2759 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2760 { 2761 2762 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2763 2764 sqtd->nextqtd = sc->sc_freeqtds; 2765 sc->sc_freeqtds = sqtd; 2766 } 2767 2768 Static usbd_status 2769 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2770 int alen, int rd, struct usbd_xfer *xfer, 2771 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2772 { 2773 ehci_soft_qtd_t *next, *cur; 2774 ehci_physaddr_t nextphys; 2775 uint32_t qtdstatus; 2776 int len, curlen, mps; 2777 int i, tog; 2778 int pages, pageoffs; 2779 size_t curoffs; 2780 vaddr_t va, va_offs; 2781 usb_dma_t *dma = &xfer->ux_dmabuf; 2782 uint16_t flags = xfer->ux_flags; 2783 paddr_t a; 2784 2785 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2786 2787 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2788 2789 len = alen; 2790 qtdstatus = EHCI_QTD_ACTIVE | 2791 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2792 EHCI_QTD_SET_CERR(3) 2793 /* IOC set below */ 2794 /* BYTES set below */ 2795 ; 2796 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2797 tog = epipe->nexttoggle; 2798 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2799 2800 cur = ehci_alloc_sqtd(sc); 2801 *sp = cur; 2802 if (cur == NULL) 2803 goto nomem; 2804 2805 usb_syncmem(dma, 0, alen, 2806 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2807 curoffs = 0; 2808 for (;;) { 2809 /* The EHCI hardware can handle at most 5 pages. */ 2810 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2811 va_offs = EHCI_PAGE_OFFSET(va_offs); 2812 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2813 /* we can handle it in this QTD */ 2814 curlen = len - curoffs; 2815 } else { 2816 /* must use multiple TDs, fill as much as possible. */ 2817 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2818 2819 /* the length must be a multiple of the max size */ 2820 curlen -= curlen % mps; 2821 USBHIST_LOG(ehcidebug, "multiple QTDs, curlen=%d", 2822 curlen, 0, 0, 0); 2823 KASSERT(curlen != 0); 2824 } 2825 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", len, 2826 curlen, curoffs, 0); 2827 2828 /* 2829 * Allocate another transfer if there's more data left, 2830 * or if force last short transfer flag is set and we're 2831 * allocating a multiple of the max packet size. 2832 */ 2833 2834 if (curoffs + curlen != len || 2835 ((curlen % mps) == 0 && !rd && curlen != 0 && 2836 (flags & USBD_FORCE_SHORT_XFER))) { 2837 next = ehci_alloc_sqtd(sc); 2838 if (next == NULL) 2839 goto nomem; 2840 nextphys = htole32(next->physaddr); 2841 } else { 2842 next = NULL; 2843 nextphys = EHCI_NULL; 2844 } 2845 2846 /* Find number of pages we'll be using, insert dma addresses */ 2847 pages = EHCI_NPAGES(curlen); 2848 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2849 pageoffs = EHCI_PAGE(curoffs); 2850 for (i = 0; i < pages; i++) { 2851 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2852 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2853 /* Cast up to avoid compiler warnings */ 2854 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2855 } 2856 2857 /* First buffer pointer requires a page offset to start at */ 2858 va = (vaddr_t)KERNADDR(dma, curoffs); 2859 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2860 2861 cur->nextqtd = next; 2862 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2863 cur->qtd.qtd_status = 2864 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2865 cur->xfer = xfer; 2866 cur->len = curlen; 2867 2868 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2869 curoffs, curoffs + curlen, 0, 0); 2870 2871 /* 2872 * adjust the toggle based on the number of packets in this 2873 * qtd 2874 */ 2875 if (((curlen + mps - 1) / mps) & 1) { 2876 tog ^= 1; 2877 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2878 } 2879 if (next == NULL) 2880 break; 2881 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2882 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2883 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2884 if (len) 2885 curoffs += curlen; 2886 cur = next; 2887 } 2888 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2889 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2890 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2891 *ep = cur; 2892 epipe->nexttoggle = tog; 2893 2894 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", *sp, *ep, 0, 0); 2895 2896 return USBD_NORMAL_COMPLETION; 2897 2898 nomem: 2899 /* XXX free chain */ 2900 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2901 return USBD_NOMEM; 2902 } 2903 2904 Static void 2905 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2906 ehci_soft_qtd_t *sqtdend) 2907 { 2908 ehci_soft_qtd_t *p; 2909 int i; 2910 2911 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2912 2913 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", sqtd, sqtdend, 0, 0); 2914 2915 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2916 p = sqtd->nextqtd; 2917 ehci_free_sqtd(sc, sqtd); 2918 } 2919 } 2920 2921 Static ehci_soft_itd_t * 2922 ehci_alloc_itd(ehci_softc_t *sc) 2923 { 2924 struct ehci_soft_itd *itd, *freeitd; 2925 usbd_status err; 2926 int i, offs, frindex, previndex; 2927 usb_dma_t dma; 2928 2929 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2930 2931 mutex_enter(&sc->sc_lock); 2932 2933 /* 2934 * Find an itd that wasn't freed this frame or last frame. This can 2935 * discard itds that were freed before frindex wrapped around 2936 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2937 * interrupt and fiddling with list when that happens 2938 */ 2939 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2940 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2941 2942 freeitd = NULL; 2943 LIST_FOREACH(itd, &sc->sc_freeitds, free_list) { 2944 if (itd == NULL) 2945 break; 2946 if (itd->slot != frindex && itd->slot != previndex) { 2947 freeitd = itd; 2948 break; 2949 } 2950 } 2951 2952 if (freeitd == NULL) { 2953 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2954 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2955 EHCI_PAGE_SIZE, &dma); 2956 2957 if (err) { 2958 USBHIST_LOG(ehcidebug, 2959 "alloc returned %d", err, 0, 0, 0); 2960 mutex_exit(&sc->sc_lock); 2961 return NULL; 2962 } 2963 2964 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2965 offs = i * EHCI_ITD_SIZE; 2966 itd = KERNADDR(&dma, offs); 2967 itd->physaddr = DMAADDR(&dma, offs); 2968 itd->dma = dma; 2969 itd->offs = offs; 2970 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 2971 } 2972 freeitd = LIST_FIRST(&sc->sc_freeitds); 2973 } 2974 2975 itd = freeitd; 2976 LIST_REMOVE(itd, free_list); 2977 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2978 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2979 sizeof(itd->itd.itd_next), 2980 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2981 2982 itd->frame_list.next = NULL; 2983 itd->frame_list.prev = NULL; 2984 itd->xfer_next = NULL; 2985 itd->slot = 0; 2986 2987 mutex_exit(&sc->sc_lock); 2988 2989 return itd; 2990 } 2991 2992 Static ehci_soft_sitd_t * 2993 ehci_alloc_sitd(ehci_softc_t *sc) 2994 { 2995 struct ehci_soft_sitd *sitd, *freesitd; 2996 usbd_status err; 2997 int i, offs, frindex, previndex; 2998 usb_dma_t dma; 2999 3000 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3001 3002 mutex_enter(&sc->sc_lock); 3003 3004 /* 3005 * Find an sitd that wasn't freed this frame or last frame. This can 3006 * discard sitds that were freed before frindex wrapped around 3007 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3008 * interrupt and fiddling with list when that happens 3009 */ 3010 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3011 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3012 3013 freesitd = NULL; 3014 LIST_FOREACH(sitd, &sc->sc_freesitds, free_list) { 3015 if (sitd == NULL) 3016 break; 3017 if (sitd->slot != frindex && sitd->slot != previndex) { 3018 freesitd = sitd; 3019 break; 3020 } 3021 } 3022 3023 if (freesitd == NULL) { 3024 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3025 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3026 EHCI_PAGE_SIZE, &dma); 3027 3028 if (err) { 3029 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 3030 0); 3031 mutex_exit(&sc->sc_lock); 3032 return NULL; 3033 } 3034 3035 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3036 offs = i * EHCI_SITD_SIZE; 3037 sitd = KERNADDR(&dma, offs); 3038 sitd->physaddr = DMAADDR(&dma, offs); 3039 sitd->dma = dma; 3040 sitd->offs = offs; 3041 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3042 } 3043 freesitd = LIST_FIRST(&sc->sc_freesitds); 3044 } 3045 3046 sitd = freesitd; 3047 LIST_REMOVE(sitd, free_list); 3048 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3049 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3050 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3051 BUS_DMASYNC_PREREAD); 3052 3053 sitd->frame_list.next = NULL; 3054 sitd->frame_list.prev = NULL; 3055 sitd->xfer_next = NULL; 3056 sitd->slot = 0; 3057 3058 mutex_exit(&sc->sc_lock); 3059 3060 return sitd; 3061 } 3062 3063 Static void 3064 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3065 { 3066 3067 KASSERT(mutex_owned(&sc->sc_lock)); 3068 3069 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3070 } 3071 3072 Static void 3073 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3074 { 3075 3076 KASSERT(mutex_owned(&sc->sc_lock)); 3077 3078 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3079 } 3080 3081 /****************/ 3082 3083 /* 3084 * Close a reqular pipe. 3085 * Assumes that there are no pending transactions. 3086 */ 3087 Static void 3088 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3089 { 3090 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3091 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3092 ehci_soft_qh_t *sqh = epipe->sqh; 3093 3094 KASSERT(mutex_owned(&sc->sc_lock)); 3095 3096 ehci_rem_qh(sc, sqh, head); 3097 ehci_free_sqh(sc, epipe->sqh); 3098 } 3099 3100 /* 3101 * Abort a device request. 3102 * If this routine is called at splusb() it guarantees that the request 3103 * will be removed from the hardware scheduling and that the callback 3104 * for it will be called with USBD_CANCELLED status. 3105 * It's impossible to guarantee that the requested transfer will not 3106 * have happened since the hardware runs concurrently. 3107 * If the transaction has already happened we rely on the ordinary 3108 * interrupt processing to process it. 3109 * XXX This is most probably wrong. 3110 * XXXMRG this doesn't make sense anymore. 3111 */ 3112 Static void 3113 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3114 { 3115 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3116 struct ehci_xfer *exfer = EXFER(xfer); 3117 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3118 ehci_soft_qh_t *sqh = epipe->sqh; 3119 ehci_soft_qtd_t *sqtd; 3120 ehci_physaddr_t cur; 3121 uint32_t qhstatus; 3122 int hit; 3123 int wake; 3124 3125 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3126 3127 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3128 3129 KASSERT(mutex_owned(&sc->sc_lock)); 3130 ASSERT_SLEEPABLE(); 3131 3132 if (sc->sc_dying) { 3133 /* If we're dying, just do the software part. */ 3134 xfer->ux_status = status; /* make software ignore it */ 3135 callout_stop(&xfer->ux_callout); 3136 usb_transfer_complete(xfer); 3137 return; 3138 } 3139 3140 /* 3141 * If an abort is already in progress then just wait for it to 3142 * complete and return. 3143 */ 3144 if (xfer->ux_hcflags & UXFER_ABORTING) { 3145 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3146 #ifdef DIAGNOSTIC 3147 if (status == USBD_TIMEOUT) 3148 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3149 #endif 3150 /* Override the status which might be USBD_TIMEOUT. */ 3151 xfer->ux_status = status; 3152 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3153 0, 0, 0, 0); 3154 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3155 while (xfer->ux_hcflags & UXFER_ABORTING) 3156 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3157 return; 3158 } 3159 xfer->ux_hcflags |= UXFER_ABORTING; 3160 3161 /* 3162 * Step 1: Make interrupt routine and hardware ignore xfer. 3163 */ 3164 xfer->ux_status = status; /* make software ignore it */ 3165 callout_stop(&xfer->ux_callout); 3166 3167 usb_syncmem(&sqh->dma, 3168 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3169 sizeof(sqh->qh.qh_qtd.qtd_status), 3170 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3171 qhstatus = sqh->qh.qh_qtd.qtd_status; 3172 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3173 usb_syncmem(&sqh->dma, 3174 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3175 sizeof(sqh->qh.qh_qtd.qtd_status), 3176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3177 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3178 usb_syncmem(&sqtd->dma, 3179 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3180 sizeof(sqtd->qtd.qtd_status), 3181 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3182 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3183 usb_syncmem(&sqtd->dma, 3184 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3185 sizeof(sqtd->qtd.qtd_status), 3186 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3187 if (sqtd == exfer->ex_sqtdend) 3188 break; 3189 } 3190 3191 /* 3192 * Step 2: Wait until we know hardware has finished any possible 3193 * use of the xfer. Also make sure the soft interrupt routine 3194 * has run. 3195 */ 3196 ehci_sync_hc(sc); 3197 sc->sc_softwake = 1; 3198 usb_schedsoftintr(&sc->sc_bus); 3199 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3200 3201 /* 3202 * Step 3: Remove any vestiges of the xfer from the hardware. 3203 * The complication here is that the hardware may have executed 3204 * beyond the xfer we're trying to abort. So as we're scanning 3205 * the TDs of this xfer we check if the hardware points to 3206 * any of them. 3207 */ 3208 3209 usb_syncmem(&sqh->dma, 3210 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3211 sizeof(sqh->qh.qh_curqtd), 3212 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3213 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3214 hit = 0; 3215 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3216 hit |= cur == sqtd->physaddr; 3217 if (sqtd == exfer->ex_sqtdend) 3218 break; 3219 } 3220 sqtd = sqtd->nextqtd; 3221 /* Zap curqtd register if hardware pointed inside the xfer. */ 3222 if (hit && sqtd != NULL) { 3223 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3224 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3225 usb_syncmem(&sqh->dma, 3226 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3227 sizeof(sqh->qh.qh_curqtd), 3228 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3229 sqh->qh.qh_qtd.qtd_status = qhstatus; 3230 usb_syncmem(&sqh->dma, 3231 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3232 sizeof(sqh->qh.qh_qtd.qtd_status), 3233 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3234 } else { 3235 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3236 usb_syncmem(&sqh->dma, 3237 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3238 sizeof(sqh->qh.qh_curqtd), 3239 BUS_DMASYNC_PREREAD); 3240 } 3241 3242 /* 3243 * Step 4: Execute callback. 3244 */ 3245 #ifdef DIAGNOSTIC 3246 exfer->ex_isdone = true; 3247 #endif 3248 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3249 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3250 usb_transfer_complete(xfer); 3251 if (wake) { 3252 cv_broadcast(&xfer->ux_hccv); 3253 } 3254 3255 KASSERT(mutex_owned(&sc->sc_lock)); 3256 } 3257 3258 Static void 3259 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3260 { 3261 ehci_isoc_trans_t trans_status; 3262 struct ehci_pipe *epipe; 3263 struct ehci_xfer *exfer; 3264 ehci_softc_t *sc; 3265 struct ehci_soft_itd *itd; 3266 struct ehci_soft_sitd *sitd; 3267 int i, wake; 3268 3269 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3270 3271 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3272 exfer = EXFER(xfer); 3273 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3274 3275 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3276 3277 KASSERT(mutex_owned(&sc->sc_lock)); 3278 3279 if (sc->sc_dying) { 3280 xfer->ux_status = status; 3281 callout_stop(&xfer->ux_callout); 3282 usb_transfer_complete(xfer); 3283 return; 3284 } 3285 3286 if (xfer->ux_hcflags & UXFER_ABORTING) { 3287 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3288 3289 #ifdef DIAGNOSTIC 3290 if (status == USBD_TIMEOUT) 3291 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3292 #endif 3293 3294 xfer->ux_status = status; 3295 USBHIST_LOG(ehcidebug, 3296 "waiting for abort to finish", 0, 0, 0, 0); 3297 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3298 while (xfer->ux_hcflags & UXFER_ABORTING) 3299 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3300 goto done; 3301 } 3302 xfer->ux_hcflags |= UXFER_ABORTING; 3303 3304 xfer->ux_status = status; 3305 callout_stop(&xfer->ux_callout); 3306 3307 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3308 for (itd = exfer->ex_itdstart; itd != NULL; 3309 itd = itd->xfer_next) { 3310 usb_syncmem(&itd->dma, 3311 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3312 sizeof(itd->itd.itd_ctl), 3313 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3314 3315 for (i = 0; i < 8; i++) { 3316 trans_status = le32toh(itd->itd.itd_ctl[i]); 3317 trans_status &= ~EHCI_ITD_ACTIVE; 3318 itd->itd.itd_ctl[i] = htole32(trans_status); 3319 } 3320 3321 usb_syncmem(&itd->dma, 3322 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3323 sizeof(itd->itd.itd_ctl), 3324 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3325 } 3326 } else { 3327 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3328 sitd = sitd->xfer_next) { 3329 usb_syncmem(&sitd->dma, 3330 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3331 sizeof(sitd->sitd.sitd_buffer), 3332 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3333 3334 trans_status = le32toh(sitd->sitd.sitd_trans); 3335 trans_status &= ~EHCI_SITD_ACTIVE; 3336 sitd->sitd.sitd_trans = htole32(trans_status); 3337 3338 usb_syncmem(&sitd->dma, 3339 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3340 sizeof(sitd->sitd.sitd_buffer), 3341 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3342 } 3343 } 3344 3345 sc->sc_softwake = 1; 3346 usb_schedsoftintr(&sc->sc_bus); 3347 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3348 3349 #ifdef DIAGNOSTIC 3350 exfer->ex_isdone = true; 3351 #endif 3352 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3353 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3354 usb_transfer_complete(xfer); 3355 if (wake) { 3356 cv_broadcast(&xfer->ux_hccv); 3357 } 3358 3359 done: 3360 KASSERT(mutex_owned(&sc->sc_lock)); 3361 return; 3362 } 3363 3364 Static void 3365 ehci_timeout(void *addr) 3366 { 3367 struct ehci_xfer *exfer = addr; 3368 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3369 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3370 3371 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3372 3373 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3374 #ifdef EHCI_DEBUG 3375 if (ehcidebug > 1) 3376 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3377 #endif 3378 3379 if (sc->sc_dying) { 3380 mutex_enter(&sc->sc_lock); 3381 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3382 mutex_exit(&sc->sc_lock); 3383 return; 3384 } 3385 3386 /* Execute the abort in a process context. */ 3387 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3388 USB_TASKQ_MPSAFE); 3389 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3390 USB_TASKQ_HC); 3391 } 3392 3393 Static void 3394 ehci_timeout_task(void *addr) 3395 { 3396 struct usbd_xfer *xfer = addr; 3397 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3398 3399 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3400 3401 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3402 3403 mutex_enter(&sc->sc_lock); 3404 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3405 mutex_exit(&sc->sc_lock); 3406 } 3407 3408 /************************/ 3409 3410 Static usbd_status 3411 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3412 { 3413 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3414 usbd_status err; 3415 3416 /* Insert last in queue. */ 3417 mutex_enter(&sc->sc_lock); 3418 err = usb_insert_transfer(xfer); 3419 mutex_exit(&sc->sc_lock); 3420 if (err) 3421 return err; 3422 3423 /* Pipe isn't running, start first */ 3424 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3425 } 3426 3427 Static usbd_status 3428 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3429 { 3430 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3431 usbd_status err; 3432 3433 if (sc->sc_dying) 3434 return USBD_IOERROR; 3435 3436 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3437 3438 err = ehci_device_request(xfer); 3439 if (err) { 3440 return err; 3441 } 3442 3443 if (sc->sc_bus.ub_usepolling) 3444 ehci_waitintr(sc, xfer); 3445 3446 return USBD_IN_PROGRESS; 3447 } 3448 3449 Static void 3450 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3451 { 3452 struct ehci_xfer *ex = EXFER(xfer); 3453 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3454 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3455 usb_device_request_t *req = &xfer->ux_request; 3456 int len = UGETW(req->wLength); 3457 int rd = req->bmRequestType & UT_READ; 3458 3459 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3460 3461 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3462 3463 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3464 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3465 3466 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3467 ehci_del_intr_list(sc, ex); /* remove from active list */ 3468 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3469 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3470 BUS_DMASYNC_POSTWRITE); 3471 if (len) 3472 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3473 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3474 } 3475 3476 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3477 } 3478 3479 /* Abort a device control request. */ 3480 Static void 3481 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3482 { 3483 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3484 3485 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3486 ehci_abort_xfer(xfer, USBD_CANCELLED); 3487 } 3488 3489 /* Close a device control pipe. */ 3490 Static void 3491 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3492 { 3493 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3494 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3495 3496 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3497 3498 KASSERT(mutex_owned(&sc->sc_lock)); 3499 3500 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3501 3502 ehci_close_pipe(pipe, sc->sc_async_head); 3503 } 3504 3505 Static usbd_status 3506 ehci_device_request(struct usbd_xfer *xfer) 3507 { 3508 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3509 struct ehci_xfer *exfer = EXFER(xfer); 3510 usb_device_request_t *req = &xfer->ux_request; 3511 struct usbd_device *dev = epipe->pipe.up_dev; 3512 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3513 ehci_soft_qtd_t *setup, *stat, *next; 3514 ehci_soft_qh_t *sqh; 3515 int isread; 3516 int len; 3517 usbd_status err; 3518 3519 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3520 3521 isread = req->bmRequestType & UT_READ; 3522 len = UGETW(req->wLength); 3523 3524 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3525 "wValue=0x%04x, wIndex=0x%04x", 3526 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3527 UGETW(req->wIndex)); 3528 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3529 len, dev->ud_addr, 3530 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3531 3532 setup = ehci_alloc_sqtd(sc); 3533 if (setup == NULL) { 3534 err = USBD_NOMEM; 3535 goto bad1; 3536 } 3537 stat = ehci_alloc_sqtd(sc); 3538 if (stat == NULL) { 3539 err = USBD_NOMEM; 3540 goto bad2; 3541 } 3542 3543 mutex_enter(&sc->sc_lock); 3544 3545 sqh = epipe->sqh; 3546 3547 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3548 "address QH %" __PRIuBIT " pipe %d\n", 3549 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3550 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3551 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3552 "MPS QH %" __PRIuBIT " pipe %d\n", 3553 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3554 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3555 3556 /* Set up data transaction */ 3557 if (len != 0) { 3558 ehci_soft_qtd_t *end; 3559 3560 /* Start toggle at 1. */ 3561 epipe->nexttoggle = 1; 3562 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3563 &next, &end); 3564 if (err) 3565 goto bad3; 3566 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3567 end->nextqtd = stat; 3568 end->qtd.qtd_next = end->qtd.qtd_altnext = 3569 htole32(stat->physaddr); 3570 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3572 } else { 3573 next = stat; 3574 } 3575 3576 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3577 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3578 3579 /* Clear toggle */ 3580 setup->qtd.qtd_status = htole32( 3581 EHCI_QTD_ACTIVE | 3582 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3583 EHCI_QTD_SET_CERR(3) | 3584 EHCI_QTD_SET_TOGGLE(0) | 3585 EHCI_QTD_SET_BYTES(sizeof(*req)) 3586 ); 3587 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3588 setup->qtd.qtd_buffer_hi[0] = 0; 3589 setup->nextqtd = next; 3590 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3591 setup->xfer = xfer; 3592 setup->len = sizeof(*req); 3593 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3594 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3595 3596 stat->qtd.qtd_status = htole32( 3597 EHCI_QTD_ACTIVE | 3598 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3599 EHCI_QTD_SET_CERR(3) | 3600 EHCI_QTD_SET_TOGGLE(1) | 3601 EHCI_QTD_IOC 3602 ); 3603 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3604 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3605 stat->nextqtd = NULL; 3606 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3607 stat->xfer = xfer; 3608 stat->len = 0; 3609 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3611 3612 #ifdef EHCI_DEBUG 3613 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3614 ehci_dump_sqh(sqh); 3615 ehci_dump_sqtds(setup); 3616 #endif 3617 3618 exfer->ex_sqtdstart = setup; 3619 exfer->ex_sqtdend = stat; 3620 KASSERT(exfer->ex_isdone); 3621 #ifdef DIAGNOSTIC 3622 exfer->ex_isdone = false; 3623 #endif 3624 3625 /* Insert qTD in QH list. */ 3626 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3627 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3628 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3629 ehci_timeout, xfer); 3630 } 3631 ehci_add_intr_list(sc, exfer); 3632 xfer->ux_status = USBD_IN_PROGRESS; 3633 mutex_exit(&sc->sc_lock); 3634 3635 #ifdef EHCI_DEBUG 3636 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3637 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3638 // delay(10000); 3639 ehci_dump_regs(sc); 3640 ehci_dump_sqh(sc->sc_async_head); 3641 ehci_dump_sqh(sqh); 3642 ehci_dump_sqtds(setup); 3643 #endif 3644 3645 return USBD_NORMAL_COMPLETION; 3646 3647 bad3: 3648 mutex_exit(&sc->sc_lock); 3649 ehci_free_sqtd(sc, stat); 3650 bad2: 3651 ehci_free_sqtd(sc, setup); 3652 bad1: 3653 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3654 mutex_enter(&sc->sc_lock); 3655 xfer->ux_status = err; 3656 usb_transfer_complete(xfer); 3657 mutex_exit(&sc->sc_lock); 3658 return err; 3659 } 3660 3661 /* 3662 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3663 * qTD status, or miss signalling occasionally under heavy load. If the host 3664 * machine is too fast, we we can miss transaction completion - when we scan 3665 * the active list the transaction still seems to be active. This generally 3666 * exhibits itself as a umass stall that never recovers. 3667 * 3668 * We work around this behaviour by setting up this callback after any softintr 3669 * that completes with transactions still pending, giving us another chance to 3670 * check for completion after the writeback has taken place. 3671 */ 3672 Static void 3673 ehci_intrlist_timeout(void *arg) 3674 { 3675 ehci_softc_t *sc = arg; 3676 3677 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3678 3679 usb_schedsoftintr(&sc->sc_bus); 3680 } 3681 3682 /************************/ 3683 3684 Static usbd_status 3685 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3686 { 3687 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3688 usbd_status err; 3689 3690 /* Insert last in queue. */ 3691 mutex_enter(&sc->sc_lock); 3692 err = usb_insert_transfer(xfer); 3693 mutex_exit(&sc->sc_lock); 3694 if (err) 3695 return err; 3696 3697 /* Pipe isn't running, start first */ 3698 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3699 } 3700 3701 Static usbd_status 3702 ehci_device_bulk_start(struct usbd_xfer *xfer) 3703 { 3704 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3705 struct ehci_xfer *exfer = EXFER(xfer); 3706 struct usbd_device *dev = epipe->pipe.up_dev; 3707 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3708 ehci_soft_qtd_t *data, *dataend; 3709 ehci_soft_qh_t *sqh; 3710 usbd_status err; 3711 int len, isread, endpt; 3712 3713 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3714 3715 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3716 xfer, xfer->ux_length, xfer->ux_flags, 0); 3717 3718 if (sc->sc_dying) 3719 return USBD_IOERROR; 3720 3721 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3722 3723 mutex_enter(&sc->sc_lock); 3724 3725 len = xfer->ux_length; 3726 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3727 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3728 sqh = epipe->sqh; 3729 3730 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3731 &dataend); 3732 if (err) { 3733 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3734 xfer->ux_status = err; 3735 usb_transfer_complete(xfer); 3736 mutex_exit(&sc->sc_lock); 3737 return err; 3738 } 3739 3740 #ifdef EHCI_DEBUG 3741 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3742 ehci_dump_sqh(sqh); 3743 ehci_dump_sqtds(data); 3744 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3745 #endif 3746 3747 /* Set up interrupt info. */ 3748 exfer->ex_sqtdstart = data; 3749 exfer->ex_sqtdend = dataend; 3750 KASSERT(exfer->ex_isdone); 3751 #ifdef DIAGNOSTIC 3752 exfer->ex_isdone = false; 3753 #endif 3754 3755 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3756 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3757 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3758 ehci_timeout, xfer); 3759 } 3760 ehci_add_intr_list(sc, exfer); 3761 xfer->ux_status = USBD_IN_PROGRESS; 3762 mutex_exit(&sc->sc_lock); 3763 3764 #ifdef EHCI_DEBUG 3765 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3766 // delay(10000); 3767 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3768 ehci_dump_regs(sc); 3769 #if 0 3770 printf("async_head:\n"); 3771 ehci_dump_sqh(sc->sc_async_head); 3772 #endif 3773 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3774 ehci_dump_sqh(sqh); 3775 ehci_dump_sqtds(data); 3776 #endif 3777 3778 if (sc->sc_bus.ub_usepolling) 3779 ehci_waitintr(sc, xfer); 3780 3781 return USBD_IN_PROGRESS; 3782 } 3783 3784 Static void 3785 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3786 { 3787 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3788 3789 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3790 ehci_abort_xfer(xfer, USBD_CANCELLED); 3791 } 3792 3793 /* 3794 * Close a device bulk pipe. 3795 */ 3796 Static void 3797 ehci_device_bulk_close(struct usbd_pipe *pipe) 3798 { 3799 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3800 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3801 3802 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3803 3804 KASSERT(mutex_owned(&sc->sc_lock)); 3805 3806 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3807 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3808 ehci_close_pipe(pipe, sc->sc_async_head); 3809 } 3810 3811 Static void 3812 ehci_device_bulk_done(struct usbd_xfer *xfer) 3813 { 3814 struct ehci_xfer *ex = EXFER(xfer); 3815 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3816 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3817 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3818 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3819 3820 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3821 3822 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3823 xfer, xfer->ux_actlen, 0, 0); 3824 3825 KASSERT(mutex_owned(&sc->sc_lock)); 3826 3827 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3828 ehci_del_intr_list(sc, ex); /* remove from active list */ 3829 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3830 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3831 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3832 } 3833 3834 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3835 } 3836 3837 /************************/ 3838 3839 Static usbd_status 3840 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3841 { 3842 struct ehci_soft_islot *isp; 3843 int islot, lev; 3844 3845 /* Find a poll rate that is large enough. */ 3846 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3847 if (EHCI_ILEV_IVAL(lev) <= ival) 3848 break; 3849 3850 /* Pick an interrupt slot at the right level. */ 3851 /* XXX could do better than picking at random */ 3852 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3853 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3854 3855 sqh->islot = islot; 3856 isp = &sc->sc_islots[islot]; 3857 mutex_enter(&sc->sc_lock); 3858 ehci_add_qh(sc, sqh, isp->sqh); 3859 mutex_exit(&sc->sc_lock); 3860 3861 return USBD_NORMAL_COMPLETION; 3862 } 3863 3864 Static usbd_status 3865 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3866 { 3867 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3868 usbd_status err; 3869 3870 /* Insert last in queue. */ 3871 mutex_enter(&sc->sc_lock); 3872 err = usb_insert_transfer(xfer); 3873 mutex_exit(&sc->sc_lock); 3874 if (err) 3875 return err; 3876 3877 /* 3878 * Pipe isn't running (otherwise err would be USBD_INPROG), 3879 * so start it first. 3880 */ 3881 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3882 } 3883 3884 Static usbd_status 3885 ehci_device_intr_start(struct usbd_xfer *xfer) 3886 { 3887 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3888 struct ehci_xfer *exfer = EXFER(xfer); 3889 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3890 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3891 ehci_soft_qtd_t *data, *dataend; 3892 ehci_soft_qh_t *sqh; 3893 usbd_status err; 3894 int len, isread, endpt; 3895 3896 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3897 3898 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3899 xfer, xfer->ux_length, xfer->ux_flags, 0); 3900 3901 if (sc->sc_dying) 3902 return USBD_IOERROR; 3903 3904 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3905 3906 mutex_enter(&sc->sc_lock); 3907 3908 len = xfer->ux_length; 3909 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3910 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3911 sqh = epipe->sqh; 3912 3913 epipe->intr.length = len; 3914 3915 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3916 &dataend); 3917 if (err) { 3918 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3919 xfer->ux_status = err; 3920 usb_transfer_complete(xfer); 3921 mutex_exit(&sc->sc_lock); 3922 return err; 3923 } 3924 3925 #ifdef EHCI_DEBUG 3926 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3927 ehci_dump_sqh(sqh); 3928 ehci_dump_sqtds(data); 3929 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3930 #endif 3931 3932 /* Set up interrupt info. */ 3933 exfer->ex_sqtdstart = data; 3934 exfer->ex_sqtdend = dataend; 3935 KASSERT(exfer->ex_isdone); 3936 #ifdef DIAGNOSTIC 3937 exfer->ex_isdone = false; 3938 #endif 3939 3940 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3941 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3942 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3943 ehci_timeout, xfer); 3944 } 3945 ehci_add_intr_list(sc, exfer); 3946 xfer->ux_status = USBD_IN_PROGRESS; 3947 mutex_exit(&sc->sc_lock); 3948 3949 #ifdef EHCI_DEBUG 3950 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3951 // delay(10000); 3952 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3953 ehci_dump_regs(sc); 3954 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3955 ehci_dump_sqh(sqh); 3956 ehci_dump_sqtds(data); 3957 #endif 3958 3959 if (sc->sc_bus.ub_usepolling) 3960 ehci_waitintr(sc, xfer); 3961 3962 return USBD_IN_PROGRESS; 3963 } 3964 3965 Static void 3966 ehci_device_intr_abort(struct usbd_xfer *xfer) 3967 { 3968 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3969 3970 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3971 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3972 3973 /* 3974 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3975 * async doorbell. That's dependent on the async list, wheras 3976 * intr xfers are periodic, should not use this? 3977 */ 3978 ehci_abort_xfer(xfer, USBD_CANCELLED); 3979 } 3980 3981 Static void 3982 ehci_device_intr_close(struct usbd_pipe *pipe) 3983 { 3984 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3985 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3986 struct ehci_soft_islot *isp; 3987 3988 KASSERT(mutex_owned(&sc->sc_lock)); 3989 3990 isp = &sc->sc_islots[epipe->sqh->islot]; 3991 ehci_close_pipe(pipe, isp->sqh); 3992 } 3993 3994 Static void 3995 ehci_device_intr_done(struct usbd_xfer *xfer) 3996 { 3997 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3998 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3999 struct ehci_xfer *exfer = EXFER(xfer); 4000 ehci_soft_qtd_t *data, *dataend; 4001 ehci_soft_qh_t *sqh; 4002 usbd_status err; 4003 int len, isread, endpt; 4004 4005 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4006 4007 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4008 xfer, xfer->ux_actlen, 0, 0); 4009 4010 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4011 4012 if (xfer->ux_pipe->up_repeat) { 4013 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4014 4015 len = epipe->intr.length; 4016 xfer->ux_length = len; 4017 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4018 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4019 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4020 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4021 sqh = epipe->sqh; 4022 4023 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4024 &data, &dataend); 4025 if (err) { 4026 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4027 xfer->ux_status = err; 4028 return; 4029 } 4030 4031 /* Set up interrupt info. */ 4032 exfer->ex_sqtdstart = data; 4033 exfer->ex_sqtdend = dataend; 4034 KASSERT(exfer->ex_isdone); 4035 #ifdef DIAGNOSTIC 4036 exfer->ex_isdone = false; 4037 #endif 4038 4039 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4040 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4041 callout_reset(&xfer->ux_callout, 4042 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4043 } 4044 4045 xfer->ux_status = USBD_IN_PROGRESS; 4046 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4047 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4048 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4049 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4050 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4051 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4052 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4053 } 4054 } 4055 4056 /************************/ 4057 4058 Static usbd_status 4059 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4060 { 4061 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4062 usbd_status err; 4063 4064 mutex_enter(&sc->sc_lock); 4065 err = usb_insert_transfer(xfer); 4066 mutex_exit(&sc->sc_lock); 4067 4068 if (err && err != USBD_IN_PROGRESS) 4069 return err; 4070 4071 return ehci_device_fs_isoc_start(xfer); 4072 } 4073 4074 Static usbd_status 4075 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4076 { 4077 struct ehci_pipe *epipe; 4078 struct usbd_device *dev; 4079 ehci_softc_t *sc; 4080 struct ehci_xfer *exfer; 4081 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4082 usb_dma_t *dma_buf; 4083 int i, j, k, frames; 4084 int offs, total_length; 4085 int frindex; 4086 u_int huba, dir; 4087 4088 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4089 4090 start = NULL; 4091 prev = NULL; 4092 sitd = NULL; 4093 total_length = 0; 4094 exfer = (struct ehci_xfer *) xfer; 4095 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4096 dev = xfer->ux_pipe->up_dev; 4097 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4098 4099 /* 4100 * To allow continuous transfers, above we start all transfers 4101 * immediately. However, we're still going to get usbd_start_next call 4102 * this when another xfer completes. So, check if this is already 4103 * in progress or not 4104 */ 4105 4106 if (exfer->ex_sitdstart != NULL) 4107 return USBD_IN_PROGRESS; 4108 4109 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4110 xfer, xfer->ux_length, xfer->ux_flags, 0); 4111 4112 if (sc->sc_dying) 4113 return USBD_IOERROR; 4114 4115 /* 4116 * To avoid complication, don't allow a request right now that'll span 4117 * the entire frame table. To within 4 frames, to allow some leeway 4118 * on either side of where the hc currently is. 4119 */ 4120 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4121 xfer->ux_nframes >= sc->sc_flsize - 4) { 4122 printf("ehci: isoc descriptor requested that spans the entire" 4123 "frametable, too many frames\n"); 4124 return USBD_INVAL; 4125 } 4126 4127 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4128 KASSERT(exfer->ex_isdone); 4129 4130 #ifdef DIAGNOSTIC 4131 exfer->ex_isdone = false; 4132 #endif 4133 4134 /* 4135 * Step 1: Allocate and initialize sitds. 4136 */ 4137 4138 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4139 if (i > 16 || i == 0) { 4140 /* Spec page 271 says intervals > 16 are invalid */ 4141 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4142 4143 return USBD_INVAL; 4144 } 4145 4146 frames = xfer->ux_nframes; 4147 4148 if (frames == 0) { 4149 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4150 4151 return USBD_INVAL; 4152 } 4153 4154 dma_buf = &xfer->ux_dmabuf; 4155 offs = 0; 4156 4157 for (i = 0; i < frames; i++) { 4158 sitd = ehci_alloc_sitd(sc); 4159 4160 if (prev) 4161 prev->xfer_next = sitd; 4162 else 4163 start = sitd; 4164 4165 #ifdef DIAGNOSTIC 4166 if (xfer->ux_frlengths[i] > 0x3ff) { 4167 printf("ehci: invalid frame length\n"); 4168 xfer->ux_frlengths[i] = 0x3ff; 4169 } 4170 #endif 4171 4172 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4173 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4174 4175 /* Set page0 index and offset. */ 4176 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4177 4178 total_length += xfer->ux_frlengths[i]; 4179 offs += xfer->ux_frlengths[i]; 4180 4181 sitd->sitd.sitd_buffer[1] = 4182 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4183 4184 huba = dev->ud_myhsport->up_parent->ud_addr; 4185 4186 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4187 // Set hub address to 0 if embedded TT is used. 4188 if (huba == sc->sc_addr) 4189 huba = 0; 4190 } 4191 */ 4192 4193 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4194 dir = UE_GET_DIR(k) ? 1 : 0; 4195 sitd->sitd.sitd_endp = 4196 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4197 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4198 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4199 EHCI_SITD_SET_HUBA(huba) | 4200 EHCI_SITD_SET_DIR(dir)); 4201 4202 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4203 4204 /* XXX */ 4205 u_char sa, sb; 4206 u_int temp, tlen; 4207 sa = 0; 4208 4209 if (dir == 0) { /* OUT */ 4210 temp = 0; 4211 tlen = xfer->ux_frlengths[i]; 4212 if (tlen <= 188) { 4213 temp |= 1; /* T-count = 1, TP = ALL */ 4214 tlen = 1; 4215 } else { 4216 tlen += 187; 4217 tlen /= 188; 4218 temp |= tlen; /* T-count = [1..6] */ 4219 temp |= 8; /* TP = Begin */ 4220 } 4221 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4222 4223 tlen += sa; 4224 4225 if (tlen >= 8) { 4226 sb = 0; 4227 } else { 4228 sb = (1 << tlen); 4229 } 4230 4231 sa = (1 << sa); 4232 sa = (sb - sa) & 0x3F; 4233 sb = 0; 4234 } else { 4235 sb = (-(4 << sa)) & 0xFE; 4236 sa = (1 << sa) & 0x3F; 4237 sa = 0x01; 4238 sb = 0xfc; 4239 } 4240 4241 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4242 EHCI_SITD_SET_CMASK(sb)); 4243 4244 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4245 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4246 4247 prev = sitd; 4248 } /* End of frame */ 4249 4250 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4251 4252 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4253 sizeof(sitd->sitd.sitd_trans), 4254 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4255 4256 stop = sitd; 4257 stop->xfer_next = NULL; 4258 4259 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4260 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4261 4262 /* 4263 * Part 2: Transfer descriptors have now been set up, now they must 4264 * be scheduled into the periodic frame list. Erk. Not wanting to 4265 * complicate matters, transfer is denied if the transfer spans 4266 * more than the period frame list. 4267 */ 4268 4269 mutex_enter(&sc->sc_lock); 4270 4271 /* Start inserting frames */ 4272 if (epipe->isoc.cur_xfers > 0) { 4273 frindex = epipe->isoc.next_frame; 4274 } else { 4275 frindex = EOREAD4(sc, EHCI_FRINDEX); 4276 frindex = frindex >> 3; /* Erase microframe index */ 4277 frindex += 2; 4278 } 4279 4280 if (frindex >= sc->sc_flsize) 4281 frindex &= (sc->sc_flsize - 1); 4282 4283 /* Whats the frame interval? */ 4284 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4285 4286 sitd = start; 4287 for (j = 0; j < frames; j++) { 4288 if (sitd == NULL) 4289 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4290 4291 usb_syncmem(&sc->sc_fldma, 4292 sizeof(ehci_link_t) * frindex, 4293 sizeof(ehci_link_t), 4294 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4295 4296 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4297 if (sitd->sitd.sitd_next == 0) 4298 /* 4299 * FIXME: frindex table gets initialized to NULL 4300 * or EHCI_NULL? 4301 */ 4302 sitd->sitd.sitd_next = EHCI_NULL; 4303 4304 usb_syncmem(&sitd->dma, 4305 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4306 sizeof(ehci_sitd_t), 4307 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4308 4309 sc->sc_flist[frindex] = 4310 htole32(EHCI_LINK_SITD | sitd->physaddr); 4311 4312 usb_syncmem(&sc->sc_fldma, 4313 sizeof(ehci_link_t) * frindex, 4314 sizeof(ehci_link_t), 4315 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4316 4317 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4318 sc->sc_softsitds[frindex] = sitd; 4319 if (sitd->frame_list.next != NULL) 4320 sitd->frame_list.next->frame_list.prev = sitd; 4321 sitd->slot = frindex; 4322 sitd->frame_list.prev = NULL; 4323 4324 frindex += i; 4325 if (frindex >= sc->sc_flsize) 4326 frindex -= sc->sc_flsize; 4327 4328 sitd = sitd->xfer_next; 4329 } 4330 4331 epipe->isoc.cur_xfers++; 4332 epipe->isoc.next_frame = frindex; 4333 4334 exfer->ex_sitdstart = start; 4335 exfer->ex_sitdend = stop; 4336 4337 ehci_add_intr_list(sc, exfer); 4338 xfer->ux_status = USBD_IN_PROGRESS; 4339 4340 mutex_exit(&sc->sc_lock); 4341 4342 if (sc->sc_bus.ub_usepolling) { 4343 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4344 ehci_waitintr(sc, xfer); 4345 } 4346 4347 return USBD_IN_PROGRESS; 4348 } 4349 4350 Static void 4351 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4352 { 4353 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4354 4355 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4356 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4357 } 4358 4359 Static void 4360 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4361 { 4362 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4363 4364 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4365 } 4366 4367 Static void 4368 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4369 { 4370 struct ehci_xfer *exfer; 4371 ehci_softc_t *sc; 4372 struct ehci_pipe *epipe; 4373 4374 exfer = EXFER(xfer); 4375 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4376 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4377 4378 KASSERT(mutex_owned(&sc->sc_lock)); 4379 4380 epipe->isoc.cur_xfers--; 4381 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4382 ehci_del_intr_list(sc, exfer); 4383 ehci_rem_free_sitd_chain(sc, exfer); 4384 } 4385 4386 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4387 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4388 } 4389 Static usbd_status 4390 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4391 { 4392 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4393 usbd_status err; 4394 4395 mutex_enter(&sc->sc_lock); 4396 err = usb_insert_transfer(xfer); 4397 mutex_exit(&sc->sc_lock); 4398 if (err && err != USBD_IN_PROGRESS) 4399 return err; 4400 4401 return ehci_device_isoc_start(xfer); 4402 } 4403 4404 Static usbd_status 4405 ehci_device_isoc_start(struct usbd_xfer *xfer) 4406 { 4407 struct ehci_pipe *epipe; 4408 ehci_softc_t *sc; 4409 struct ehci_xfer *exfer; 4410 ehci_soft_itd_t *itd, *prev, *start, *stop; 4411 usb_dma_t *dma_buf; 4412 int i, j, k, frames, uframes, ufrperframe; 4413 int trans_count, offs, total_length; 4414 int frindex; 4415 4416 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4417 4418 start = NULL; 4419 prev = NULL; 4420 itd = NULL; 4421 trans_count = 0; 4422 total_length = 0; 4423 exfer = (struct ehci_xfer *) xfer; 4424 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4425 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4426 4427 /* 4428 * To allow continuous transfers, above we start all transfers 4429 * immediately. However, we're still going to get usbd_start_next call 4430 * this when another xfer completes. So, check if this is already 4431 * in progress or not 4432 */ 4433 4434 if (exfer->ex_itdstart != NULL) 4435 return USBD_IN_PROGRESS; 4436 4437 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4438 xfer, xfer->ux_length, xfer->ux_flags, 0); 4439 4440 if (sc->sc_dying) 4441 return USBD_IOERROR; 4442 4443 /* 4444 * To avoid complication, don't allow a request right now that'll span 4445 * the entire frame table. To within 4 frames, to allow some leeway 4446 * on either side of where the hc currently is. 4447 */ 4448 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4449 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4450 USBHIST_LOG(ehcidebug, 4451 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4452 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4453 return USBD_INVAL; 4454 } 4455 4456 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4457 KASSERT(exfer->ex_isdone); 4458 #ifdef DIAGNOSTIC 4459 exfer->ex_isdone = false; 4460 #endif 4461 4462 /* 4463 * Step 1: Allocate and initialize itds, how many do we need? 4464 * One per transfer if interval >= 8 microframes, fewer if we use 4465 * multiple microframes per frame. 4466 */ 4467 4468 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4469 if (i > 16 || i == 0) { 4470 /* Spec page 271 says intervals > 16 are invalid */ 4471 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4472 return USBD_INVAL; 4473 } 4474 4475 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4476 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4477 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4478 4479 if (frames == 0) { 4480 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4481 return USBD_INVAL; 4482 } 4483 4484 dma_buf = &xfer->ux_dmabuf; 4485 offs = 0; 4486 4487 for (i = 0; i < frames; i++) { 4488 int froffs = offs; 4489 itd = ehci_alloc_itd(sc); 4490 4491 if (prev != NULL) { 4492 prev->itd.itd_next = 4493 htole32(itd->physaddr | EHCI_LINK_ITD); 4494 usb_syncmem(&prev->dma, 4495 prev->offs + offsetof(ehci_itd_t, itd_next), 4496 sizeof(prev->itd.itd_next), 4497 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4498 4499 prev->xfer_next = itd; 4500 } else { 4501 start = itd; 4502 } 4503 4504 /* 4505 * Step 1.5, initialize uframes 4506 */ 4507 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4508 /* Calculate which page in the list this starts in */ 4509 int addr = DMAADDR(dma_buf, froffs); 4510 addr = EHCI_PAGE_OFFSET(addr); 4511 addr += (offs - froffs); 4512 addr = EHCI_PAGE(addr); 4513 addr /= EHCI_PAGE_SIZE; 4514 4515 /* 4516 * This gets the initial offset into the first page, 4517 * looks how far further along the current uframe 4518 * offset is. Works out how many pages that is. 4519 */ 4520 4521 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4522 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4523 EHCI_ITD_SET_PG(addr) | 4524 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4525 4526 total_length += xfer->ux_frlengths[trans_count]; 4527 offs += xfer->ux_frlengths[trans_count]; 4528 trans_count++; 4529 4530 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4531 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4532 break; 4533 } 4534 } 4535 4536 /* 4537 * Step 1.75, set buffer pointers. To simplify matters, all 4538 * pointers are filled out for the next 7 hardware pages in 4539 * the dma block, so no need to worry what pages to cover 4540 * and what to not. 4541 */ 4542 4543 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4544 /* 4545 * Don't try to lookup a page that's past the end 4546 * of buffer 4547 */ 4548 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4549 if (page_offs >= dma_buf->udma_block->size) 4550 break; 4551 4552 unsigned long long page = DMAADDR(dma_buf, page_offs); 4553 page = EHCI_PAGE(page); 4554 itd->itd.itd_bufr[j] = 4555 htole32(EHCI_ITD_SET_BPTR(page)); 4556 itd->itd.itd_bufr_hi[j] = 4557 htole32(page >> 32); 4558 } 4559 4560 /* 4561 * Other special values 4562 */ 4563 4564 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4565 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4566 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4567 4568 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4569 ? 1 : 0; 4570 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4571 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4572 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4573 4574 /* FIXME: handle invalid trans */ 4575 itd->itd.itd_bufr[2] |= 4576 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4577 4578 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4579 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4580 4581 prev = itd; 4582 } /* End of frame */ 4583 4584 stop = itd; 4585 stop->xfer_next = NULL; 4586 4587 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4588 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4589 4590 /* 4591 * Part 2: Transfer descriptors have now been set up, now they must 4592 * be scheduled into the period frame list. Erk. Not wanting to 4593 * complicate matters, transfer is denied if the transfer spans 4594 * more than the period frame list. 4595 */ 4596 4597 mutex_enter(&sc->sc_lock); 4598 4599 /* Start inserting frames */ 4600 if (epipe->isoc.cur_xfers > 0) { 4601 frindex = epipe->isoc.next_frame; 4602 } else { 4603 frindex = EOREAD4(sc, EHCI_FRINDEX); 4604 frindex = frindex >> 3; /* Erase microframe index */ 4605 frindex += 2; 4606 } 4607 4608 if (frindex >= sc->sc_flsize) 4609 frindex &= (sc->sc_flsize - 1); 4610 4611 /* What's the frame interval? */ 4612 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4613 if (i / USB_UFRAMES_PER_FRAME == 0) 4614 i = 1; 4615 else 4616 i /= USB_UFRAMES_PER_FRAME; 4617 4618 itd = start; 4619 for (j = 0; j < frames; j++) { 4620 if (itd == NULL) 4621 panic("ehci: unexpectedly ran out of isoc itds, isoc_start"); 4622 4623 usb_syncmem(&sc->sc_fldma, 4624 sizeof(ehci_link_t) * frindex, 4625 sizeof(ehci_link_t), 4626 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4627 4628 itd->itd.itd_next = sc->sc_flist[frindex]; 4629 if (itd->itd.itd_next == 0) 4630 /* FIXME: frindex table gets initialized to NULL 4631 * or EHCI_NULL? */ 4632 itd->itd.itd_next = EHCI_NULL; 4633 4634 usb_syncmem(&itd->dma, 4635 itd->offs + offsetof(ehci_itd_t, itd_next), 4636 sizeof(itd->itd.itd_next), 4637 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4638 4639 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4640 4641 usb_syncmem(&sc->sc_fldma, 4642 sizeof(ehci_link_t) * frindex, 4643 sizeof(ehci_link_t), 4644 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4645 4646 itd->frame_list.next = sc->sc_softitds[frindex]; 4647 sc->sc_softitds[frindex] = itd; 4648 if (itd->frame_list.next != NULL) 4649 itd->frame_list.next->frame_list.prev = itd; 4650 itd->slot = frindex; 4651 itd->frame_list.prev = NULL; 4652 4653 frindex += i; 4654 if (frindex >= sc->sc_flsize) 4655 frindex -= sc->sc_flsize; 4656 4657 itd = itd->xfer_next; 4658 } 4659 4660 epipe->isoc.cur_xfers++; 4661 epipe->isoc.next_frame = frindex; 4662 4663 exfer->ex_itdstart = start; 4664 exfer->ex_itdend = stop; 4665 4666 ehci_add_intr_list(sc, exfer); 4667 xfer->ux_status = USBD_IN_PROGRESS; 4668 mutex_exit(&sc->sc_lock); 4669 4670 if (sc->sc_bus.ub_usepolling) { 4671 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4672 ehci_waitintr(sc, xfer); 4673 } 4674 4675 return USBD_IN_PROGRESS; 4676 } 4677 4678 Static void 4679 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4680 { 4681 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4682 4683 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4684 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4685 } 4686 4687 Static void 4688 ehci_device_isoc_close(struct usbd_pipe *pipe) 4689 { 4690 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4691 4692 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4693 } 4694 4695 Static void 4696 ehci_device_isoc_done(struct usbd_xfer *xfer) 4697 { 4698 struct ehci_xfer *exfer; 4699 ehci_softc_t *sc; 4700 struct ehci_pipe *epipe; 4701 4702 exfer = EXFER(xfer); 4703 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4704 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4705 4706 KASSERT(mutex_owned(&sc->sc_lock)); 4707 4708 epipe->isoc.cur_xfers--; 4709 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4710 ehci_del_intr_list(sc, exfer); 4711 ehci_rem_free_itd_chain(sc, exfer); 4712 } 4713 4714 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4715 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4716 4717 } 4718
Indexes created Wed Oct 01 19:09:53 GMT 2025