ehci.c revision 1.234.2.6
1 /* $NetBSD: ehci.c,v 1.234.2.6 2014/12/01 12:38:39 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.6 2014/12/01 12:38:39 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 #include <dev/usb/usbroothub_subr.h> 85 86 #include <dev/usb/ehcireg.h> 87 #include <dev/usb/ehcivar.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 174 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 175 176 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 177 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 178 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 179 180 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 182 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 183 Static void ehci_root_ctrl_close(usbd_pipe_handle); 184 Static void ehci_root_ctrl_done(usbd_xfer_handle); 185 186 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 187 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 188 Static void ehci_root_intr_abort(usbd_xfer_handle); 189 Static void ehci_root_intr_close(usbd_pipe_handle); 190 Static void ehci_root_intr_done(usbd_xfer_handle); 191 192 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 193 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 194 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 195 Static void ehci_device_ctrl_close(usbd_pipe_handle); 196 Static void ehci_device_ctrl_done(usbd_xfer_handle); 197 198 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 199 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 200 Static void ehci_device_bulk_abort(usbd_xfer_handle); 201 Static void ehci_device_bulk_close(usbd_pipe_handle); 202 Static void ehci_device_bulk_done(usbd_xfer_handle); 203 204 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 205 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 206 Static void ehci_device_intr_abort(usbd_xfer_handle); 207 Static void ehci_device_intr_close(usbd_pipe_handle); 208 Static void ehci_device_intr_done(usbd_xfer_handle); 209 210 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 211 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 212 Static void ehci_device_isoc_abort(usbd_xfer_handle); 213 Static void ehci_device_isoc_close(usbd_pipe_handle); 214 Static void ehci_device_isoc_done(usbd_xfer_handle); 215 216 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 217 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 218 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 219 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 220 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 221 222 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 223 Static void ehci_noop(usbd_pipe_handle pipe); 224 225 Static void ehci_disown(ehci_softc_t *, int, int); 226 227 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 228 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 229 230 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 231 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 232 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 233 ehci_softc_t *, int, int, usbd_xfer_handle, 234 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 235 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 236 ehci_soft_qtd_t *); 237 238 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 239 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *sc); 240 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 241 Static void ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *); 242 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 243 struct ehci_xfer *exfer); 244 Static void ehci_rem_free_sitd_chain(ehci_softc_t *sc, 245 struct ehci_xfer *exfer); 246 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 247 usbd_status status); 248 249 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 250 251 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 252 int ival); 253 254 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 255 ehci_soft_qh_t *); 256 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 257 ehci_soft_qh_t *); 258 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 259 Static void ehci_sync_hc(ehci_softc_t *); 260 261 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 262 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 263 264 #ifdef EHCI_DEBUG 265 Static ehci_softc_t *theehci; 266 void ehci_dump(void); 267 #endif 268 269 #ifdef EHCI_DEBUG 270 Static void ehci_dump_regs(ehci_softc_t *); 271 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 272 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 273 Static void ehci_dump_qtd(ehci_qtd_t *); 274 Static void ehci_dump_sqh(ehci_soft_qh_t *); 275 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 276 Static void ehci_dump_itd(struct ehci_soft_itd *); 277 Static void ehci_dump_exfer(struct ehci_xfer *); 278 #endif 279 280 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 281 282 #define EHCI_INTR_ENDPT 1 283 284 #define ehci_add_intr_list(sc, ex) \ 285 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 286 #define ehci_del_intr_list(sc, ex) \ 287 do { \ 288 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 289 (ex)->inext.tqe_prev = NULL; \ 290 } while (0) 291 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 292 293 Static const struct usbd_bus_methods ehci_bus_methods = { 294 .ubm_open = ehci_open, 295 .ubm_softint = ehci_softintr, 296 .ubm_dopoll = ehci_poll, 297 .ubm_allocm = ehci_allocm, 298 .ubm_freem = ehci_freem, 299 .ubm_allocx = ehci_allocx, 300 .ubm_freex = ehci_freex, 301 .ubm_getlock = ehci_get_lock, 302 .ubm_newdev = NULL, 303 }; 304 305 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 306 .upm_transfer = ehci_root_ctrl_transfer, 307 .upm_start = ehci_root_ctrl_start, 308 .upm_abort = ehci_root_ctrl_abort, 309 .upm_close = ehci_root_ctrl_close, 310 .upm_cleartoggle = ehci_noop, 311 .upm_done = ehci_root_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 315 .upm_transfer = ehci_root_intr_transfer, 316 .upm_start = ehci_root_intr_start, 317 .upm_abort = ehci_root_intr_abort, 318 .upm_close = ehci_root_intr_close, 319 .upm_cleartoggle = ehci_noop, 320 .upm_done = ehci_root_intr_done, 321 }; 322 323 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 324 .upm_transfer = ehci_device_ctrl_transfer, 325 .upm_start = ehci_device_ctrl_start, 326 .upm_abort = ehci_device_ctrl_abort, 327 .upm_close = ehci_device_ctrl_close, 328 .upm_cleartoggle = ehci_noop, 329 .upm_done = ehci_device_ctrl_done, 330 }; 331 332 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 333 .upm_transfer = ehci_device_intr_transfer, 334 .upm_start = ehci_device_intr_start, 335 .upm_abort = ehci_device_intr_abort, 336 .upm_close = ehci_device_intr_close, 337 .upm_cleartoggle = ehci_device_clear_toggle, 338 .upm_done = ehci_device_intr_done, 339 }; 340 341 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 342 .upm_transfer = ehci_device_bulk_transfer, 343 .upm_start = ehci_device_bulk_start, 344 .upm_abort = ehci_device_bulk_abort, 345 .upm_close = ehci_device_bulk_close, 346 .upm_cleartoggle = ehci_device_clear_toggle, 347 .upm_done = ehci_device_bulk_done, 348 }; 349 350 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 351 .upm_transfer = ehci_device_isoc_transfer, 352 .upm_start = ehci_device_isoc_start, 353 .upm_abort = ehci_device_isoc_abort, 354 .upm_close = ehci_device_isoc_close, 355 .upm_cleartoggle = ehci_noop, 356 .upm_done = ehci_device_isoc_done, 357 }; 358 359 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 360 .upm_transfer = ehci_device_fs_isoc_transfer, 361 .upm_start = ehci_device_fs_isoc_start, 362 .upm_abort = ehci_device_fs_isoc_abort, 363 .upm_close = ehci_device_fs_isoc_close, 364 .upm_cleartoggle = ehci_noop, 365 .upm_done = ehci_device_fs_isoc_done, 366 }; 367 368 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 369 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 370 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 371 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 372 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 373 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 374 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 375 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 376 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 377 }; 378 379 usbd_status 380 ehci_init(ehci_softc_t *sc) 381 { 382 uint32_t vers, sparams, cparams, hcr; 383 u_int i; 384 usbd_status err; 385 ehci_soft_qh_t *sqh; 386 u_int ncomp; 387 388 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 389 #ifdef EHCI_DEBUG 390 theehci = sc; 391 #endif 392 393 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 394 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 395 cv_init(&sc->sc_softwake_cv, "ehciab"); 396 cv_init(&sc->sc_doorbell, "ehcidi"); 397 398 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 399 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 400 401 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 402 ehci_doorbell, sc); 403 KASSERT(sc->sc_doorbell_si != NULL); 404 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 405 ehci_pcd, sc); 406 KASSERT(sc->sc_pcd_si != NULL); 407 408 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 409 410 vers = EREAD2(sc, EHCI_HCIVERSION); 411 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 412 vers >> 8, vers & 0xff); 413 414 sparams = EREAD4(sc, EHCI_HCSPARAMS); 415 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 416 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 417 ncomp = EHCI_HCS_N_CC(sparams); 418 if (ncomp != sc->sc_ncomp) { 419 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 420 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 421 #if NOHCI == 0 || NUHCI == 0 422 aprint_error("%s: ohci or uhci probably not configured\n", 423 device_xname(sc->sc_dev)); 424 #endif 425 if (ncomp < sc->sc_ncomp) 426 sc->sc_ncomp = ncomp; 427 } 428 if (sc->sc_ncomp > 0) { 429 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 430 aprint_normal("%s: companion controller%s, %d port%s each:", 431 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 432 EHCI_HCS_N_PCC(sparams), 433 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 434 for (i = 0; i < sc->sc_ncomp; i++) 435 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 436 aprint_normal("\n"); 437 } 438 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 439 cparams = EREAD4(sc, EHCI_HCCPARAMS); 440 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 441 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 442 443 if (EHCI_HCC_64BIT(cparams)) { 444 /* MUST clear segment register if 64 bit capable. */ 445 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 446 } 447 448 sc->sc_bus.usbrev = USBREV_2_0; 449 450 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 451 USB_MEM_RESERVE); 452 453 /* Reset the controller */ 454 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 455 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 456 usb_delay_ms(&sc->sc_bus, 1); 457 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 458 for (i = 0; i < 100; i++) { 459 usb_delay_ms(&sc->sc_bus, 1); 460 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 461 if (!hcr) 462 break; 463 } 464 if (hcr) { 465 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 466 return (USBD_IOERROR); 467 } 468 if (sc->sc_vendor_init) 469 sc->sc_vendor_init(sc); 470 471 /* 472 * If we are doing embedded transaction translation function, force 473 * the controller to host mode. 474 */ 475 if (sc->sc_flags & EHCIF_ETTF) { 476 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 477 usbmode &= ~EHCI_USBMODE_CM; 478 usbmode |= EHCI_USBMODE_CM_HOST; 479 EWRITE4(sc, EHCI_USBMODE, usbmode); 480 } 481 482 /* XXX need proper intr scheduling */ 483 sc->sc_rand = 96; 484 485 /* frame list size at default, read back what we got and use that */ 486 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 487 case 0: sc->sc_flsize = 1024; break; 488 case 1: sc->sc_flsize = 512; break; 489 case 2: sc->sc_flsize = 256; break; 490 case 3: return (USBD_IOERROR); 491 } 492 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 493 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 494 if (err) 495 return (err); 496 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 497 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 498 499 for (i = 0; i < sc->sc_flsize; i++) { 500 sc->sc_flist[i] = EHCI_NULL; 501 } 502 503 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 504 505 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 506 KM_SLEEP); 507 if (sc->sc_softitds == NULL) 508 return ENOMEM; 509 LIST_INIT(&sc->sc_freeitds); 510 LIST_INIT(&sc->sc_freesitds); 511 TAILQ_INIT(&sc->sc_intrhead); 512 513 /* Set up the bus struct. */ 514 sc->sc_bus.methods = &ehci_bus_methods; 515 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 516 517 sc->sc_eintrs = EHCI_NORMAL_INTRS; 518 519 /* 520 * Allocate the interrupt dummy QHs. These are arranged to give poll 521 * intervals that are powers of 2 times 1ms. 522 */ 523 for (i = 0; i < EHCI_INTRQHS; i++) { 524 sqh = ehci_alloc_sqh(sc); 525 if (sqh == NULL) { 526 err = USBD_NOMEM; 527 goto bad1; 528 } 529 sc->sc_islots[i].sqh = sqh; 530 } 531 for (i = 0; i < EHCI_INTRQHS; i++) { 532 sqh = sc->sc_islots[i].sqh; 533 if (i == 0) { 534 /* The last (1ms) QH terminates. */ 535 sqh->qh.qh_link = EHCI_NULL; 536 sqh->next = NULL; 537 } else { 538 /* Otherwise the next QH has half the poll interval */ 539 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 540 sqh->qh.qh_link = htole32(sqh->next->physaddr | 541 EHCI_LINK_QH); 542 } 543 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 544 sqh->qh.qh_curqtd = EHCI_NULL; 545 sqh->next = NULL; 546 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 547 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 548 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 549 sqh->sqtd = NULL; 550 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 551 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 552 } 553 /* Point the frame list at the last level (128ms). */ 554 for (i = 0; i < sc->sc_flsize; i++) { 555 int j; 556 557 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 558 revbits[i & (EHCI_MAX_POLLRATE-1)]; 559 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 560 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 561 i)].sqh->physaddr); 562 } 563 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 564 BUS_DMASYNC_PREWRITE); 565 566 /* Allocate dummy QH that starts the async list. */ 567 sqh = ehci_alloc_sqh(sc); 568 if (sqh == NULL) { 569 err = USBD_NOMEM; 570 goto bad1; 571 } 572 /* Fill the QH */ 573 sqh->qh.qh_endp = 574 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 575 sqh->qh.qh_link = 576 htole32(sqh->physaddr | EHCI_LINK_QH); 577 sqh->qh.qh_curqtd = EHCI_NULL; 578 sqh->next = NULL; 579 /* Fill the overlay qTD */ 580 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 581 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 582 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 583 sqh->sqtd = NULL; 584 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 585 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 586 #ifdef EHCI_DEBUG 587 ehci_dump_sqh(sqh); 588 #endif 589 590 /* Point to async list */ 591 sc->sc_async_head = sqh; 592 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 593 594 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 595 596 /* Turn on controller */ 597 EOWRITE4(sc, EHCI_USBCMD, 598 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 599 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 600 EHCI_CMD_ASE | 601 EHCI_CMD_PSE | 602 EHCI_CMD_RS); 603 604 /* Take over port ownership */ 605 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 606 607 for (i = 0; i < 100; i++) { 608 usb_delay_ms(&sc->sc_bus, 1); 609 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 610 if (!hcr) 611 break; 612 } 613 if (hcr) { 614 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 615 return (USBD_IOERROR); 616 } 617 618 /* Enable interrupts */ 619 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 620 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 621 622 return (USBD_NORMAL_COMPLETION); 623 624 #if 0 625 bad2: 626 ehci_free_sqh(sc, sc->sc_async_head); 627 #endif 628 bad1: 629 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 630 return (err); 631 } 632 633 int 634 ehci_intr(void *v) 635 { 636 ehci_softc_t *sc = v; 637 int ret = 0; 638 639 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 640 641 if (sc == NULL) 642 return 0; 643 644 mutex_spin_enter(&sc->sc_intr_lock); 645 646 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 647 goto done; 648 649 /* If we get an interrupt while polling, then just ignore it. */ 650 if (sc->sc_bus.use_polling) { 651 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 652 653 if (intrs) 654 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 655 #ifdef DIAGNOSTIC 656 USBHIST_LOGN(ehcidebug, 16, 657 "ignored interrupt while polling", 0, 0, 0, 0); 658 #endif 659 goto done; 660 } 661 662 ret = ehci_intr1(sc); 663 664 done: 665 mutex_spin_exit(&sc->sc_intr_lock); 666 return ret; 667 } 668 669 Static int 670 ehci_intr1(ehci_softc_t *sc) 671 { 672 uint32_t intrs, eintrs; 673 674 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 675 676 /* In case the interrupt occurs before initialization has completed. */ 677 if (sc == NULL) { 678 #ifdef DIAGNOSTIC 679 printf("ehci_intr1: sc == NULL\n"); 680 #endif 681 return (0); 682 } 683 684 KASSERT(mutex_owned(&sc->sc_intr_lock)); 685 686 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 687 if (!intrs) 688 return (0); 689 690 eintrs = intrs & sc->sc_eintrs; 691 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 692 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 693 if (!eintrs) 694 return (0); 695 696 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 697 if (eintrs & EHCI_STS_IAA) { 698 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 699 kpreempt_disable(); 700 KASSERT(sc->sc_doorbell_si != NULL); 701 softint_schedule(sc->sc_doorbell_si); 702 kpreempt_enable(); 703 eintrs &= ~EHCI_STS_IAA; 704 } 705 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 706 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 707 eintrs & EHCI_STS_INT ? 1 : 0, 708 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 709 usb_schedsoftintr(&sc->sc_bus); 710 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 711 } 712 if (eintrs & EHCI_STS_HSE) { 713 printf("%s: unrecoverable error, controller halted\n", 714 device_xname(sc->sc_dev)); 715 /* XXX what else */ 716 } 717 if (eintrs & EHCI_STS_PCD) { 718 kpreempt_disable(); 719 KASSERT(sc->sc_pcd_si != NULL); 720 softint_schedule(sc->sc_pcd_si); 721 kpreempt_enable(); 722 eintrs &= ~EHCI_STS_PCD; 723 } 724 725 if (eintrs != 0) { 726 /* Block unprocessed interrupts. */ 727 sc->sc_eintrs &= ~eintrs; 728 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 729 printf("%s: blocking intrs 0x%x\n", 730 device_xname(sc->sc_dev), eintrs); 731 } 732 733 return (1); 734 } 735 736 Static void 737 ehci_doorbell(void *addr) 738 { 739 ehci_softc_t *sc = addr; 740 741 mutex_enter(&sc->sc_lock); 742 cv_broadcast(&sc->sc_doorbell); 743 mutex_exit(&sc->sc_lock); 744 } 745 746 Static void 747 ehci_pcd(void *addr) 748 { 749 ehci_softc_t *sc = addr; 750 usbd_xfer_handle xfer; 751 u_char *p; 752 int i, m; 753 754 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 755 756 mutex_enter(&sc->sc_lock); 757 xfer = sc->sc_intrxfer; 758 759 if (xfer == NULL) { 760 /* Just ignore the change. */ 761 goto done; 762 } 763 764 p = KERNADDR(&xfer->dmabuf, 0); 765 m = min(sc->sc_noport, xfer->length * 8 - 1); 766 memset(p, 0, xfer->length); 767 for (i = 1; i <= m; i++) { 768 /* Pick out CHANGE bits from the status reg. */ 769 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 770 p[i/8] |= 1 << (i%8); 771 if (i % 8 == 7) 772 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 773 p[i/8], 0, 0); 774 } 775 xfer->actlen = xfer->length; 776 xfer->status = USBD_NORMAL_COMPLETION; 777 778 usb_transfer_complete(xfer); 779 780 done: 781 mutex_exit(&sc->sc_lock); 782 } 783 784 Static void 785 ehci_softintr(void *v) 786 { 787 struct usbd_bus *bus = v; 788 ehci_softc_t *sc = bus->hci_private; 789 struct ehci_xfer *ex, *nextex; 790 791 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 792 793 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 794 795 /* 796 * The only explanation I can think of for why EHCI is as brain dead 797 * as UHCI interrupt-wise is that Intel was involved in both. 798 * An interrupt just tells us that something is done, we have no 799 * clue what, so we need to scan through all active transfers. :-( 800 */ 801 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 802 nextex = TAILQ_NEXT(ex, inext); 803 ehci_check_intr(sc, ex); 804 } 805 806 /* Schedule a callout to catch any dropped transactions. */ 807 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 808 !TAILQ_EMPTY(&sc->sc_intrhead)) 809 callout_reset(&sc->sc_tmo_intrlist, 810 hz, ehci_intrlist_timeout, sc); 811 812 if (sc->sc_softwake) { 813 sc->sc_softwake = 0; 814 cv_broadcast(&sc->sc_softwake_cv); 815 } 816 } 817 818 /* Check for an interrupt. */ 819 Static void 820 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 821 { 822 usbd_device_handle dev = ex->xfer.pipe->device; 823 int attr; 824 825 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 826 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 827 828 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 829 830 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 831 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 832 if (dev->speed == USB_SPEED_HIGH) 833 ehci_check_itd_intr(sc, ex); 834 else 835 ehci_check_sitd_intr(sc, ex); 836 } else 837 ehci_check_qh_intr(sc, ex); 838 839 return; 840 } 841 842 Static void 843 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 844 { 845 ehci_soft_qtd_t *sqtd, *lsqtd; 846 uint32_t status; 847 848 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 849 850 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 851 852 if (ex->sqtdstart == NULL) { 853 printf("ehci_check_qh_intr: not valid sqtd\n"); 854 return; 855 } 856 857 lsqtd = ex->sqtdend; 858 #ifdef DIAGNOSTIC 859 if (lsqtd == NULL) { 860 printf("ehci_check_qh_intr: lsqtd==0\n"); 861 return; 862 } 863 #endif 864 /* 865 * If the last TD is still active we need to check whether there 866 * is an error somewhere in the middle, or whether there was a 867 * short packet (SPD and not ACTIVE). 868 */ 869 usb_syncmem(&lsqtd->dma, 870 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 871 sizeof(lsqtd->qtd.qtd_status), 872 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 873 status = le32toh(lsqtd->qtd.qtd_status); 874 usb_syncmem(&lsqtd->dma, 875 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 876 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 877 if (status & EHCI_QTD_ACTIVE) { 878 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 879 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 880 usb_syncmem(&sqtd->dma, 881 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 882 sizeof(sqtd->qtd.qtd_status), 883 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 884 status = le32toh(sqtd->qtd.qtd_status); 885 usb_syncmem(&sqtd->dma, 886 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 887 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 888 /* If there's an active QTD the xfer isn't done. */ 889 if (status & EHCI_QTD_ACTIVE) 890 break; 891 /* Any kind of error makes the xfer done. */ 892 if (status & EHCI_QTD_HALTED) 893 goto done; 894 /* Handle short packets */ 895 if (EHCI_QTD_GET_BYTES(status) != 0) { 896 usbd_pipe_handle pipe = ex->xfer.pipe; 897 usb_endpoint_descriptor_t *ed = 898 pipe->endpoint->edesc; 899 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 900 901 /* 902 * If we get here for a control transfer then 903 * we need to let the hardware complete the 904 * status phase. That is, we're not done 905 * quite yet. 906 * 907 * Otherwise, we're done. 908 */ 909 if (xt == UE_CONTROL) { 910 break; 911 } 912 goto done; 913 } 914 } 915 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 916 ex, ex->sqtdstart, 0, 0); 917 return; 918 } 919 done: 920 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 921 callout_stop(&ex->xfer.timeout_handle); 922 ehci_idone(ex); 923 } 924 925 Static void 926 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 927 { 928 ehci_soft_itd_t *itd; 929 int i; 930 931 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 932 933 KASSERT(mutex_owned(&sc->sc_lock)); 934 935 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 936 return; 937 938 if (ex->itdstart == NULL) { 939 printf("ehci_check_itd_intr: not valid itd\n"); 940 return; 941 } 942 943 itd = ex->itdend; 944 #ifdef DIAGNOSTIC 945 if (itd == NULL) { 946 printf("ehci_check_itd_intr: itdend == 0\n"); 947 return; 948 } 949 #endif 950 951 /* 952 * check no active transfers in last itd, meaning we're finished 953 */ 954 955 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 956 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 957 BUS_DMASYNC_POSTREAD); 958 959 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 960 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 961 break; 962 } 963 964 if (i == EHCI_ITD_NUFRAMES) { 965 goto done; /* All 8 descriptors inactive, it's done */ 966 } 967 968 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 969 ex->itdstart, 0, 0); 970 return; 971 done: 972 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 973 callout_stop(&ex->xfer.timeout_handle); 974 ehci_idone(ex); 975 } 976 977 void 978 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 979 { 980 ehci_soft_sitd_t *sitd; 981 982 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 983 984 KASSERT(mutex_owned(&sc->sc_lock)); 985 986 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 987 return; 988 989 if (ex->sitdstart == NULL) { 990 printf("ehci_check_sitd_intr: not valid sitd\n"); 991 return; 992 } 993 994 sitd = ex->sitdend; 995 #ifdef DIAGNOSTIC 996 if (sitd == NULL) { 997 printf("ehci_check_sitd_intr: sitdend == 0\n"); 998 return; 999 } 1000 #endif 1001 1002 /* 1003 * check no active transfers in last sitd, meaning we're finished 1004 */ 1005 1006 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1007 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1008 BUS_DMASYNC_POSTREAD); 1009 1010 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 1011 return; 1012 1013 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1014 callout_stop(&(ex->xfer.timeout_handle)); 1015 ehci_idone(ex); 1016 } 1017 1018 1019 Static void 1020 ehci_idone(struct ehci_xfer *ex) 1021 { 1022 usbd_xfer_handle xfer = &ex->xfer; 1023 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 1024 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 1025 ehci_soft_qtd_t *sqtd, *lsqtd; 1026 uint32_t status = 0, nstatus = 0; 1027 int actlen; 1028 1029 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1030 1031 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1032 1033 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1034 1035 #ifdef DIAGNOSTIC 1036 if (ex->isdone) { 1037 printf("ehci_idone: ex=%p is done!\n", ex); 1038 #ifdef EHCI_DEBUG 1039 ehci_dump_exfer(ex); 1040 #endif 1041 return; 1042 } 1043 ex->isdone = 1; 1044 #endif 1045 1046 if (xfer->status == USBD_CANCELLED || 1047 xfer->status == USBD_TIMEOUT) { 1048 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1049 return; 1050 } 1051 1052 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1053 #ifdef EHCI_DEBUG 1054 ehci_dump_sqtds(ex->sqtdstart); 1055 #endif 1056 1057 /* The transfer is done, compute actual length and status. */ 1058 1059 u_int xfertype, speed; 1060 1061 xfertype = UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes); 1062 speed = xfer->pipe->device->speed; 1063 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1064 /* HS isoc transfer */ 1065 1066 struct ehci_soft_itd *itd; 1067 int i, nframes, len, uframes; 1068 1069 nframes = 0; 1070 actlen = 0; 1071 1072 i = xfer->pipe->endpoint->edesc->bInterval; 1073 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1074 1075 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1076 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1077 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1078 BUS_DMASYNC_POSTREAD); 1079 1080 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1081 /* XXX - driver didn't fill in the frame full 1082 * of uframes. This leads to scheduling 1083 * inefficiencies, but working around 1084 * this doubles complexity of tracking 1085 * an xfer. 1086 */ 1087 if (nframes >= xfer->nframes) 1088 break; 1089 1090 status = le32toh(itd->itd.itd_ctl[i]); 1091 len = EHCI_ITD_GET_LEN(status); 1092 if (EHCI_ITD_GET_STATUS(status) != 0) 1093 len = 0; /*No valid data on error*/ 1094 1095 xfer->frlengths[nframes++] = len; 1096 actlen += len; 1097 } 1098 1099 if (nframes >= xfer->nframes) 1100 break; 1101 } 1102 1103 xfer->actlen = actlen; 1104 xfer->status = USBD_NORMAL_COMPLETION; 1105 goto end; 1106 } 1107 1108 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1109 /* FS isoc transfer */ 1110 struct ehci_soft_sitd *sitd; 1111 int nframes, len; 1112 1113 nframes = 0; 1114 actlen = 0; 1115 1116 for (sitd = ex->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1117 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1118 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1119 BUS_DMASYNC_POSTREAD); 1120 1121 /* XXX - driver didn't fill in the frame full 1122 * of uframes. This leads to scheduling 1123 * inefficiencies, but working around 1124 * this doubles complexity of tracking 1125 * an xfer. 1126 */ 1127 if (nframes >= xfer->nframes) 1128 break; 1129 1130 status = le32toh(sitd->sitd.sitd_trans); 1131 len = EHCI_SITD_GET_LEN(status); 1132 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1133 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1134 /* No valid data on error */ 1135 len = xfer->frlengths[nframes]; 1136 } 1137 1138 /* 1139 * frlengths[i]: # of bytes to send 1140 * len: # of bytes host didn't send 1141 */ 1142 xfer->frlengths[nframes] -= len; 1143 /* frlengths[i]: # of bytes host sent */ 1144 actlen += xfer->frlengths[nframes++]; 1145 1146 if (nframes >= xfer->nframes) 1147 break; 1148 } 1149 1150 xfer->actlen = actlen; 1151 xfer->status = USBD_NORMAL_COMPLETION; 1152 goto end; 1153 } 1154 1155 /* Continue processing xfers using queue heads */ 1156 1157 lsqtd = ex->sqtdend; 1158 actlen = 0; 1159 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 1160 sqtd = sqtd->nextqtd) { 1161 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1162 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1163 nstatus = le32toh(sqtd->qtd.qtd_status); 1164 if (nstatus & EHCI_QTD_ACTIVE) 1165 break; 1166 1167 status = nstatus; 1168 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1169 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1170 } 1171 1172 1173 /* 1174 * If there are left over TDs we need to update the toggle. 1175 * The default pipe doesn't need it since control transfers 1176 * start the toggle at 0 every time. 1177 * For a short transfer we need to update the toggle for the missing 1178 * packets within the qTD. 1179 */ 1180 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1181 xfer->pipe->device->default_pipe != xfer->pipe) { 1182 USBHIST_LOG(ehcidebug, 1183 "toggle update status=0x%08x nstatus=0x%08x", 1184 status, nstatus, 0, 0); 1185 #if 0 1186 ehci_dump_sqh(epipe->sqh); 1187 ehci_dump_sqtds(ex->sqtdstart); 1188 #endif 1189 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1190 } 1191 1192 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->length, 1193 actlen, status, 0); 1194 xfer->actlen = actlen; 1195 if (status & EHCI_QTD_HALTED) { 1196 #ifdef EHCI_DEBUG 1197 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1198 xfer->pipe->device->address, 1199 xfer->pipe->endpoint->edesc->bEndpointAddress, 0, 0); 1200 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1201 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1202 status, 0); 1203 USBHIST_LOG(ehcidebug, 1204 "active =%d halted=%d buferr=%d babble=%d", 1205 status & EHCI_QTD_ACTIVE ? 1 : 0, 1206 status & EHCI_QTD_HALTED ? 1 : 0, 1207 status & EHCI_QTD_BUFERR ? 1 : 0, 1208 status & EHCI_QTD_BABBLE ? 1 : 0); 1209 1210 USBHIST_LOG(ehcidebug, 1211 "xacterr=%d missed=%d split =%d ping =%d", 1212 status & EHCI_QTD_XACTERR ? 1 : 0, 1213 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1214 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1215 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1216 1217 ehci_dump_sqh(epipe->sqh); 1218 ehci_dump_sqtds(ex->sqtdstart); 1219 #endif 1220 /* low&full speed has an extra error flag */ 1221 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1222 EHCI_QH_SPEED_HIGH) 1223 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1224 else 1225 status &= EHCI_QTD_STATERRS; 1226 if (status == 0) /* no other errors means a stall */ { 1227 xfer->status = USBD_STALLED; 1228 } else { 1229 xfer->status = USBD_IOERROR; /* more info XXX */ 1230 } 1231 /* XXX need to reset TT on missed microframe */ 1232 if (status & EHCI_QTD_MISSEDMICRO) { 1233 printf("%s: missed microframe, TT reset not " 1234 "implemented, hub might be inoperational\n", 1235 device_xname(sc->sc_dev)); 1236 } 1237 } else { 1238 xfer->status = USBD_NORMAL_COMPLETION; 1239 } 1240 1241 end: 1242 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1243 * during this call, before methods->done is called: dma sync required 1244 * beforehand? */ 1245 usb_transfer_complete(xfer); 1246 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1247 } 1248 1249 /* 1250 * Wait here until controller claims to have an interrupt. 1251 * Then call ehci_intr and return. Use timeout to avoid waiting 1252 * too long. 1253 */ 1254 Static void 1255 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1256 { 1257 int timo; 1258 uint32_t intrs; 1259 1260 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1261 1262 xfer->status = USBD_IN_PROGRESS; 1263 for (timo = xfer->timeout; timo >= 0; timo--) { 1264 usb_delay_ms(&sc->sc_bus, 1); 1265 if (sc->sc_dying) 1266 break; 1267 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1268 sc->sc_eintrs; 1269 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1270 #ifdef EHCI_DEBUG 1271 if (ehcidebug > 15) 1272 ehci_dump_regs(sc); 1273 #endif 1274 if (intrs) { 1275 mutex_spin_enter(&sc->sc_intr_lock); 1276 ehci_intr1(sc); 1277 mutex_spin_exit(&sc->sc_intr_lock); 1278 if (xfer->status != USBD_IN_PROGRESS) 1279 return; 1280 } 1281 } 1282 1283 /* Timeout */ 1284 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1285 xfer->status = USBD_TIMEOUT; 1286 mutex_enter(&sc->sc_lock); 1287 usb_transfer_complete(xfer); 1288 mutex_exit(&sc->sc_lock); 1289 /* XXX should free TD */ 1290 } 1291 1292 Static void 1293 ehci_poll(struct usbd_bus *bus) 1294 { 1295 ehci_softc_t *sc = bus->hci_private; 1296 1297 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1298 1299 #ifdef EHCI_DEBUG 1300 static int last; 1301 int new; 1302 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1303 if (new != last) { 1304 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1305 last = new; 1306 } 1307 #endif 1308 1309 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1310 mutex_spin_enter(&sc->sc_intr_lock); 1311 ehci_intr1(sc); 1312 mutex_spin_exit(&sc->sc_intr_lock); 1313 } 1314 } 1315 1316 void 1317 ehci_childdet(device_t self, device_t child) 1318 { 1319 struct ehci_softc *sc = device_private(self); 1320 1321 KASSERT(sc->sc_child == child); 1322 sc->sc_child = NULL; 1323 } 1324 1325 int 1326 ehci_detach(struct ehci_softc *sc, int flags) 1327 { 1328 int rv = 0; 1329 1330 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1331 1332 if (sc->sc_child != NULL) 1333 rv = config_detach(sc->sc_child, flags); 1334 1335 if (rv != 0) 1336 return (rv); 1337 1338 callout_halt(&sc->sc_tmo_intrlist, NULL); 1339 callout_destroy(&sc->sc_tmo_intrlist); 1340 1341 /* XXX free other data structures XXX */ 1342 if (sc->sc_softitds) 1343 kmem_free(sc->sc_softitds, 1344 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1345 cv_destroy(&sc->sc_doorbell); 1346 cv_destroy(&sc->sc_softwake_cv); 1347 1348 #if 0 1349 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1350 1351 softint_disestablish(sc->sc_doorbell_si); 1352 softint_disestablish(sc->sc_pcd_si); 1353 1354 mutex_destroy(&sc->sc_lock); 1355 mutex_destroy(&sc->sc_intr_lock); 1356 #endif 1357 1358 pool_cache_destroy(sc->sc_xferpool); 1359 1360 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1361 1362 return (rv); 1363 } 1364 1365 1366 int 1367 ehci_activate(device_t self, enum devact act) 1368 { 1369 struct ehci_softc *sc = device_private(self); 1370 1371 switch (act) { 1372 case DVACT_DEACTIVATE: 1373 sc->sc_dying = 1; 1374 return 0; 1375 default: 1376 return EOPNOTSUPP; 1377 } 1378 } 1379 1380 /* 1381 * Handle suspend/resume. 1382 * 1383 * We need to switch to polling mode here, because this routine is 1384 * called from an interrupt context. This is all right since we 1385 * are almost suspended anyway. 1386 * 1387 * Note that this power handler isn't to be registered directly; the 1388 * bus glue needs to call out to it. 1389 */ 1390 bool 1391 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1392 { 1393 ehci_softc_t *sc = device_private(dv); 1394 int i; 1395 uint32_t cmd, hcr; 1396 1397 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1398 1399 mutex_spin_enter(&sc->sc_intr_lock); 1400 sc->sc_bus.use_polling++; 1401 mutex_spin_exit(&sc->sc_intr_lock); 1402 1403 for (i = 1; i <= sc->sc_noport; i++) { 1404 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1405 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1406 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1407 } 1408 1409 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1410 1411 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1412 EOWRITE4(sc, EHCI_USBCMD, cmd); 1413 1414 for (i = 0; i < 100; i++) { 1415 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1416 if (hcr == 0) 1417 break; 1418 1419 usb_delay_ms(&sc->sc_bus, 1); 1420 } 1421 if (hcr != 0) 1422 printf("%s: reset timeout\n", device_xname(dv)); 1423 1424 cmd &= ~EHCI_CMD_RS; 1425 EOWRITE4(sc, EHCI_USBCMD, cmd); 1426 1427 for (i = 0; i < 100; i++) { 1428 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1429 if (hcr == EHCI_STS_HCH) 1430 break; 1431 1432 usb_delay_ms(&sc->sc_bus, 1); 1433 } 1434 if (hcr != EHCI_STS_HCH) 1435 printf("%s: config timeout\n", device_xname(dv)); 1436 1437 mutex_spin_enter(&sc->sc_intr_lock); 1438 sc->sc_bus.use_polling--; 1439 mutex_spin_exit(&sc->sc_intr_lock); 1440 1441 return true; 1442 } 1443 1444 bool 1445 ehci_resume(device_t dv, const pmf_qual_t *qual) 1446 { 1447 ehci_softc_t *sc = device_private(dv); 1448 int i; 1449 uint32_t cmd, hcr; 1450 1451 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1452 1453 /* restore things in case the bios sucks */ 1454 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1455 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1456 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1457 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1458 1459 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1460 1461 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1462 1463 hcr = 0; 1464 for (i = 1; i <= sc->sc_noport; i++) { 1465 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1466 if ((cmd & EHCI_PS_PO) == 0 && 1467 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1468 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1469 hcr = 1; 1470 } 1471 } 1472 1473 if (hcr) { 1474 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1475 1476 for (i = 1; i <= sc->sc_noport; i++) { 1477 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1478 if ((cmd & EHCI_PS_PO) == 0 && 1479 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1480 EOWRITE4(sc, EHCI_PORTSC(i), 1481 cmd & ~EHCI_PS_FPR); 1482 } 1483 } 1484 1485 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1486 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1487 1488 for (i = 0; i < 100; i++) { 1489 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1490 if (hcr != EHCI_STS_HCH) 1491 break; 1492 1493 usb_delay_ms(&sc->sc_bus, 1); 1494 } 1495 if (hcr == EHCI_STS_HCH) 1496 printf("%s: config timeout\n", device_xname(dv)); 1497 1498 return true; 1499 } 1500 1501 /* 1502 * Shut down the controller when the system is going down. 1503 */ 1504 bool 1505 ehci_shutdown(device_t self, int flags) 1506 { 1507 ehci_softc_t *sc = device_private(self); 1508 1509 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1510 1511 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1512 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1513 return true; 1514 } 1515 1516 Static usbd_status 1517 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 1518 { 1519 struct ehci_softc *sc = bus->hci_private; 1520 usbd_status err; 1521 1522 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1523 #ifdef EHCI_DEBUG 1524 if (err) 1525 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1526 usbd_errstr(err), err); 1527 #endif 1528 if (err == USBD_NOMEM) 1529 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1530 #ifdef EHCI_DEBUG 1531 if (err) 1532 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1533 usbd_errstr(err), err); 1534 #endif 1535 return (err); 1536 } 1537 1538 Static void 1539 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1540 { 1541 struct ehci_softc *sc = bus->hci_private; 1542 1543 if (dma->block->flags & USB_DMA_RESERVE) { 1544 usb_reserve_freem(&sc->sc_dma_reserve, 1545 dma); 1546 return; 1547 } 1548 usb_freemem(&sc->sc_bus, dma); 1549 } 1550 1551 Static usbd_xfer_handle 1552 ehci_allocx(struct usbd_bus *bus) 1553 { 1554 struct ehci_softc *sc = bus->hci_private; 1555 usbd_xfer_handle xfer; 1556 1557 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1558 if (xfer != NULL) { 1559 memset(xfer, 0, sizeof(struct ehci_xfer)); 1560 #ifdef DIAGNOSTIC 1561 EXFER(xfer)->isdone = 1; 1562 xfer->busy_free = XFER_BUSY; 1563 #endif 1564 } 1565 return (xfer); 1566 } 1567 1568 Static void 1569 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1570 { 1571 struct ehci_softc *sc = bus->hci_private; 1572 1573 #ifdef DIAGNOSTIC 1574 if (xfer->busy_free != XFER_BUSY) { 1575 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1576 xfer->busy_free); 1577 } 1578 xfer->busy_free = XFER_FREE; 1579 if (!EXFER(xfer)->isdone) { 1580 printf("ehci_freex: !isdone\n"); 1581 } 1582 #endif 1583 pool_cache_put(sc->sc_xferpool, xfer); 1584 } 1585 1586 Static void 1587 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1588 { 1589 struct ehci_softc *sc = bus->hci_private; 1590 1591 *lock = &sc->sc_lock; 1592 } 1593 1594 Static void 1595 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1596 { 1597 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1598 1599 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1600 1601 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1602 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1603 #ifdef EHCI_DEBUG 1604 if (ehcidebug) 1605 usbd_dump_pipe(pipe); 1606 #endif 1607 epipe->nexttoggle = 0; 1608 } 1609 1610 Static void 1611 ehci_noop(usbd_pipe_handle pipe) 1612 { 1613 } 1614 1615 #ifdef EHCI_DEBUG 1616 /* 1617 * Unused function - this is meant to be called from a kernel 1618 * debugger. 1619 */ 1620 void 1621 ehci_dump(void) 1622 { 1623 ehci_softc_t *sc = theehci; 1624 int i; 1625 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1626 EOREAD4(sc, EHCI_USBCMD), 1627 EOREAD4(sc, EHCI_USBSTS), 1628 EOREAD4(sc, EHCI_USBINTR)); 1629 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1630 EOREAD4(sc, EHCI_FRINDEX), 1631 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1632 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1633 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1634 for (i = 1; i <= sc->sc_noport; i++) 1635 printf("port %d status=0x%08x\n", i, 1636 EOREAD4(sc, EHCI_PORTSC(i))); 1637 } 1638 1639 Static void 1640 ehci_dump_regs(ehci_softc_t *sc) 1641 { 1642 int i; 1643 1644 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1645 1646 USBHIST_LOG(ehcidebug, 1647 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1648 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1649 EOREAD4(sc, EHCI_USBINTR), 0); 1650 USBHIST_LOG(ehcidebug, 1651 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1652 "async = 0x%08x", 1653 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1654 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1655 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1656 for (i = 1; i <= sc->sc_noport; i += 2) { 1657 if (i == sc->sc_noport) { 1658 USBHIST_LOG(ehcidebug, 1659 "port %d status = 0x%08x", i, 1660 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1661 } else { 1662 USBHIST_LOG(ehcidebug, 1663 "port %d status = 0x%08x port %d status = 0x%08x", 1664 i, EOREAD4(sc, EHCI_PORTSC(i)), 1665 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1666 } 1667 } 1668 } 1669 1670 #ifdef EHCI_DEBUG 1671 #define ehci_dump_link(link, type) do { \ 1672 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1673 link, \ 1674 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1675 if (type) { \ 1676 USBHIST_LOG(ehcidebug, \ 1677 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1678 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1679 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1680 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1681 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1682 } \ 1683 } while(0) 1684 #else 1685 #define ehci_dump_link(link, type) 1686 #endif 1687 1688 Static void 1689 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1690 { 1691 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1692 int i; 1693 uint32_t stop = 0; 1694 1695 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1696 ehci_dump_sqtd(sqtd); 1697 usb_syncmem(&sqtd->dma, 1698 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1699 sizeof(sqtd->qtd), 1700 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1701 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1702 usb_syncmem(&sqtd->dma, 1703 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1704 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1705 } 1706 if (sqtd) 1707 USBHIST_LOG(ehcidebug, 1708 "dump aborted, too many TDs", 0, 0, 0, 0); 1709 } 1710 1711 Static void 1712 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1713 { 1714 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1715 1716 usb_syncmem(&sqtd->dma, sqtd->offs, 1717 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1718 1719 USBHIST_LOGN(ehcidebug, 10, 1720 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1721 ehci_dump_qtd(&sqtd->qtd); 1722 1723 usb_syncmem(&sqtd->dma, sqtd->offs, 1724 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1725 } 1726 1727 Static void 1728 ehci_dump_qtd(ehci_qtd_t *qtd) 1729 { 1730 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1731 1732 #ifdef USBHIST 1733 uint32_t s = le32toh(qtd->qtd_status); 1734 #endif 1735 1736 USBHIST_LOGN(ehcidebug, 10, 1737 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1738 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1739 USBHIST_LOGN(ehcidebug, 10, 1740 " toggle = %d ioc = %d bytes = %#x " 1741 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1742 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1743 USBHIST_LOGN(ehcidebug, 10, 1744 " cerr = %d pid = %d stat = %x", 1745 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1746 0); 1747 USBHIST_LOGN(ehcidebug, 10, 1748 "active =%d halted=%d buferr=%d babble=%d", 1749 s & EHCI_QTD_ACTIVE ? 1 : 0, 1750 s & EHCI_QTD_HALTED ? 1 : 0, 1751 s & EHCI_QTD_BUFERR ? 1 : 0, 1752 s & EHCI_QTD_BABBLE ? 1 : 0); 1753 USBHIST_LOGN(ehcidebug, 10, 1754 "xacterr=%d missed=%d split =%d ping =%d", 1755 s & EHCI_QTD_XACTERR ? 1 : 0, 1756 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1757 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1758 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1759 USBHIST_LOGN(ehcidebug, 10, 1760 "buffer[0] = %#x buffer[1] = %#x " 1761 "buffer[2] = %#x buffer[3] = %#x", 1762 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1763 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1764 USBHIST_LOGN(ehcidebug, 10, 1765 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1766 } 1767 1768 Static void 1769 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1770 { 1771 #ifdef USBHIST 1772 ehci_qh_t *qh = &sqh->qh; 1773 ehci_link_t link; 1774 #endif 1775 uint32_t endp, endphub; 1776 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1777 1778 usb_syncmem(&sqh->dma, sqh->offs, 1779 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1780 1781 USBHIST_LOGN(ehcidebug, 10, 1782 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1783 link = le32toh(qh->qh_link); 1784 ehci_dump_link(link, true); 1785 1786 endp = le32toh(qh->qh_endp); 1787 USBHIST_LOGN(ehcidebug, 10, 1788 " endp = %#x", endp, 0, 0, 0); 1789 USBHIST_LOGN(ehcidebug, 10, 1790 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1791 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1792 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1793 USBHIST_LOGN(ehcidebug, 10, 1794 " dtc = %d hrecl = %d", 1795 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1796 USBHIST_LOGN(ehcidebug, 10, 1797 " ctl = %d nrl = %d mpl = %#x(%d)", 1798 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1799 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1800 1801 endphub = le32toh(qh->qh_endphub); 1802 USBHIST_LOGN(ehcidebug, 10, 1803 " endphub = %#x", endphub, 0, 0, 0); 1804 USBHIST_LOGN(ehcidebug, 10, 1805 " smask = 0x%02x cmask = 0x%02x", 1806 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1807 USBHIST_LOGN(ehcidebug, 10, 1808 " huba = 0x%02x port = %d mult = %d", 1809 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1810 EHCI_QH_GET_MULT(endphub), 0); 1811 1812 link = le32toh(qh->qh_curqtd); 1813 ehci_dump_link(link, false); 1814 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1815 ehci_dump_qtd(&qh->qh_qtd); 1816 1817 usb_syncmem(&sqh->dma, sqh->offs, 1818 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1819 } 1820 1821 Static void 1822 ehci_dump_itd(struct ehci_soft_itd *itd) 1823 { 1824 ehci_isoc_trans_t t; 1825 ehci_isoc_bufr_ptr_t b, b2, b3; 1826 int i; 1827 1828 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1829 1830 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1831 0, 0); 1832 1833 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1834 t = le32toh(itd->itd.itd_ctl[i]); 1835 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1836 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1837 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1838 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1839 EHCI_ITD_GET_OFFS(t), 0); 1840 } 1841 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1842 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1843 USBHIST_LOG(ehcidebug, " %x", 1844 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1845 1846 b = le32toh(itd->itd.itd_bufr[0]); 1847 b2 = le32toh(itd->itd.itd_bufr[1]); 1848 b3 = le32toh(itd->itd.itd_bufr[2]); 1849 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1850 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1851 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1852 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1853 } 1854 1855 Static void 1856 ehci_dump_sitd(struct ehci_soft_itd *itd) 1857 { 1858 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1859 1860 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1861 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1862 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1863 itd->xfer_next, itd->physaddr, itd->slot, 0); 1864 } 1865 1866 Static void 1867 ehci_dump_exfer(struct ehci_xfer *ex) 1868 { 1869 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1870 1871 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1872 ex, ex->sqtdstart, ex->sqtdend, 0); 1873 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1874 ex->itdstart, ex->itdend, ex->isdone, 0); 1875 } 1876 #endif 1877 1878 Static usbd_status 1879 ehci_open(usbd_pipe_handle pipe) 1880 { 1881 usbd_device_handle dev = pipe->device; 1882 ehci_softc_t *sc = dev->bus->hci_private; 1883 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1884 uint8_t addr = dev->address; 1885 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1886 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1887 ehci_soft_qh_t *sqh; 1888 usbd_status err; 1889 int ival, speed, naks; 1890 int hshubaddr, hshubport; 1891 1892 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1893 1894 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1895 pipe, addr, ed->bEndpointAddress, sc->sc_addr); 1896 1897 if (dev->myhsport) { 1898 /* 1899 * When directly attached FS/LS device while doing embedded 1900 * transaction translations and we are the hub, set the hub 1901 * address to 0 (us). 1902 */ 1903 if (!(sc->sc_flags & EHCIF_ETTF) 1904 || (dev->myhsport->parent->address != sc->sc_addr)) { 1905 hshubaddr = dev->myhsport->parent->address; 1906 } else { 1907 hshubaddr = 0; 1908 } 1909 hshubport = dev->myhsport->portno; 1910 } else { 1911 hshubaddr = 0; 1912 hshubport = 0; 1913 } 1914 1915 if (sc->sc_dying) 1916 return (USBD_IOERROR); 1917 1918 /* toggle state needed for bulk endpoints */ 1919 epipe->nexttoggle = pipe->endpoint->datatoggle; 1920 1921 if (addr == sc->sc_addr) { 1922 switch (ed->bEndpointAddress) { 1923 case USB_CONTROL_ENDPOINT: 1924 pipe->methods = &ehci_root_ctrl_methods; 1925 break; 1926 case UE_DIR_IN | EHCI_INTR_ENDPT: 1927 pipe->methods = &ehci_root_intr_methods; 1928 break; 1929 default: 1930 USBHIST_LOG(ehcidebug, 1931 "bad bEndpointAddress 0x%02x", 1932 ed->bEndpointAddress, 0, 0, 0); 1933 return (USBD_INVAL); 1934 } 1935 return (USBD_NORMAL_COMPLETION); 1936 } 1937 1938 /* XXX All this stuff is only valid for async. */ 1939 switch (dev->speed) { 1940 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1941 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1942 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1943 default: panic("ehci_open: bad device speed %d", dev->speed); 1944 } 1945 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1946 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1947 hshubaddr, hshubport, 0, 0); 1948 return USBD_INVAL; 1949 } 1950 1951 /* 1952 * For interrupt transfer, nak throttling must be disabled, but for 1953 * the other transfer type, nak throttling should be enabled from the 1954 * viewpoint that avoids the memory thrashing. 1955 */ 1956 naks = (xfertype == UE_INTERRUPT) ? 0 1957 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1958 1959 /* Allocate sqh for everything, save isoc xfers */ 1960 if (xfertype != UE_ISOCHRONOUS) { 1961 sqh = ehci_alloc_sqh(sc); 1962 if (sqh == NULL) 1963 return (USBD_NOMEM); 1964 /* qh_link filled when the QH is added */ 1965 sqh->qh.qh_endp = htole32( 1966 EHCI_QH_SET_ADDR(addr) | 1967 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1968 EHCI_QH_SET_EPS(speed) | 1969 EHCI_QH_DTC | 1970 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1971 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1972 EHCI_QH_CTL : 0) | 1973 EHCI_QH_SET_NRL(naks) 1974 ); 1975 sqh->qh.qh_endphub = htole32( 1976 EHCI_QH_SET_MULT(1) | 1977 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1978 ); 1979 if (speed != EHCI_QH_SPEED_HIGH) 1980 sqh->qh.qh_endphub |= htole32( 1981 EHCI_QH_SET_PORT(hshubport) | 1982 EHCI_QH_SET_HUBA(hshubaddr) | 1983 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1984 ); 1985 sqh->qh.qh_curqtd = EHCI_NULL; 1986 /* Fill the overlay qTD */ 1987 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1988 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1989 sqh->qh.qh_qtd.qtd_status = htole32(0); 1990 1991 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1992 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1993 epipe->sqh = sqh; 1994 } else { 1995 sqh = NULL; 1996 } /*xfertype == UE_ISOC*/ 1997 1998 switch (xfertype) { 1999 case UE_CONTROL: 2000 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2001 0, &epipe->u.ctl.reqdma); 2002 #ifdef EHCI_DEBUG 2003 if (err) 2004 printf("ehci_open: usb_allocmem()=%d\n", err); 2005 #endif 2006 if (err) 2007 goto bad; 2008 pipe->methods = &ehci_device_ctrl_methods; 2009 mutex_enter(&sc->sc_lock); 2010 ehci_add_qh(sc, sqh, sc->sc_async_head); 2011 mutex_exit(&sc->sc_lock); 2012 break; 2013 case UE_BULK: 2014 pipe->methods = &ehci_device_bulk_methods; 2015 mutex_enter(&sc->sc_lock); 2016 ehci_add_qh(sc, sqh, sc->sc_async_head); 2017 mutex_exit(&sc->sc_lock); 2018 break; 2019 case UE_INTERRUPT: 2020 pipe->methods = &ehci_device_intr_methods; 2021 ival = pipe->interval; 2022 if (ival == USBD_DEFAULT_INTERVAL) { 2023 if (speed == EHCI_QH_SPEED_HIGH) { 2024 if (ed->bInterval > 16) { 2025 /* 2026 * illegal with high-speed, but there 2027 * were documentation bugs in the spec, 2028 * so be generous 2029 */ 2030 ival = 256; 2031 } else 2032 ival = (1 << (ed->bInterval - 1)) / 8; 2033 } else 2034 ival = ed->bInterval; 2035 } 2036 err = ehci_device_setintr(sc, sqh, ival); 2037 if (err) 2038 goto bad; 2039 break; 2040 case UE_ISOCHRONOUS: 2041 if (speed == EHCI_QH_SPEED_HIGH) 2042 pipe->methods = &ehci_device_isoc_methods; 2043 else 2044 pipe->methods = &ehci_device_fs_isoc_methods; 2045 if (ed->bInterval == 0 || ed->bInterval > 16) { 2046 printf("ehci: opening pipe with invalid bInterval\n"); 2047 err = USBD_INVAL; 2048 goto bad; 2049 } 2050 if (UGETW(ed->wMaxPacketSize) == 0) { 2051 printf("ehci: zero length endpoint open request\n"); 2052 err = USBD_INVAL; 2053 goto bad; 2054 } 2055 epipe->u.isoc.next_frame = 0; 2056 epipe->u.isoc.cur_xfers = 0; 2057 break; 2058 default: 2059 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2060 err = USBD_INVAL; 2061 goto bad; 2062 } 2063 return (USBD_NORMAL_COMPLETION); 2064 2065 bad: 2066 if (sqh != NULL) 2067 ehci_free_sqh(sc, sqh); 2068 return (err); 2069 } 2070 2071 /* 2072 * Add an ED to the schedule. Called with USB lock held. 2073 */ 2074 Static void 2075 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2076 { 2077 2078 KASSERT(mutex_owned(&sc->sc_lock)); 2079 2080 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2081 2082 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2083 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2084 2085 sqh->next = head->next; 2086 sqh->qh.qh_link = head->qh.qh_link; 2087 2088 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2089 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2090 2091 head->next = sqh; 2092 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2093 2094 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2095 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2096 2097 #ifdef EHCI_DEBUG 2098 ehci_dump_sqh(sqh); 2099 #endif 2100 } 2101 2102 /* 2103 * Remove an ED from the schedule. Called with USB lock held. 2104 */ 2105 Static void 2106 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2107 { 2108 ehci_soft_qh_t *p; 2109 2110 KASSERT(mutex_owned(&sc->sc_lock)); 2111 2112 /* XXX */ 2113 for (p = head; p != NULL && p->next != sqh; p = p->next) 2114 ; 2115 if (p == NULL) 2116 panic("ehci_rem_qh: ED not found"); 2117 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2118 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2119 p->next = sqh->next; 2120 p->qh.qh_link = sqh->qh.qh_link; 2121 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2122 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2123 2124 ehci_sync_hc(sc); 2125 } 2126 2127 Static void 2128 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2129 { 2130 int i; 2131 uint32_t status; 2132 2133 /* Save toggle bit and ping status. */ 2134 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2135 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2136 status = sqh->qh.qh_qtd.qtd_status & 2137 htole32(EHCI_QTD_TOGGLE_MASK | 2138 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2139 /* Set HALTED to make hw leave it alone. */ 2140 sqh->qh.qh_qtd.qtd_status = 2141 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2142 usb_syncmem(&sqh->dma, 2143 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2144 sizeof(sqh->qh.qh_qtd.qtd_status), 2145 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2146 sqh->qh.qh_curqtd = 0; 2147 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2148 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2149 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2150 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2151 sqh->sqtd = sqtd; 2152 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2153 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2154 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2155 sqh->qh.qh_qtd.qtd_status = status; 2156 usb_syncmem(&sqh->dma, 2157 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2158 sizeof(sqh->qh.qh_qtd.qtd_status), 2159 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2160 } 2161 2162 /* 2163 * Ensure that the HC has released all references to the QH. We do this 2164 * by asking for a Async Advance Doorbell interrupt and then we wait for 2165 * the interrupt. 2166 * To make this easier we first obtain exclusive use of the doorbell. 2167 */ 2168 Static void 2169 ehci_sync_hc(ehci_softc_t *sc) 2170 { 2171 int error __diagused; 2172 2173 KASSERT(mutex_owned(&sc->sc_lock)); 2174 2175 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2176 2177 if (sc->sc_dying) { 2178 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2179 return; 2180 } 2181 /* ask for doorbell */ 2182 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2183 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2184 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2185 2186 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2187 2188 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2189 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2190 #ifdef DIAGNOSTIC 2191 if (error) 2192 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2193 #endif 2194 } 2195 2196 Static void 2197 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2198 { 2199 struct ehci_soft_itd *itd, *prev; 2200 2201 prev = NULL; 2202 2203 if (exfer->itdstart == NULL || exfer->itdend == NULL) 2204 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2205 2206 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2207 prev = itd->u.frame_list.prev; 2208 /* Unlink itd from hardware chain, or frame array */ 2209 if (prev == NULL) { /* We're at the table head */ 2210 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2211 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2212 usb_syncmem(&sc->sc_fldma, 2213 sizeof(ehci_link_t) * itd->slot, 2214 sizeof(ehci_link_t), 2215 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2216 2217 if (itd->u.frame_list.next != NULL) 2218 itd->u.frame_list.next->u.frame_list.prev = NULL; 2219 } else { 2220 /* XXX this part is untested... */ 2221 prev->itd.itd_next = itd->itd.itd_next; 2222 usb_syncmem(&itd->dma, 2223 itd->offs + offsetof(ehci_itd_t, itd_next), 2224 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2225 2226 prev->u.frame_list.next = itd->u.frame_list.next; 2227 if (itd->u.frame_list.next != NULL) 2228 itd->u.frame_list.next->u.frame_list.prev = prev; 2229 } 2230 } 2231 2232 prev = NULL; 2233 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2234 if (prev != NULL) 2235 ehci_free_itd(sc, prev); 2236 prev = itd; 2237 } 2238 if (prev) 2239 ehci_free_itd(sc, prev); 2240 exfer->itdstart = NULL; 2241 exfer->itdend = NULL; 2242 } 2243 2244 Static void 2245 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2246 { 2247 struct ehci_soft_sitd *sitd, *prev; 2248 2249 prev = NULL; 2250 2251 if (exfer->sitdstart == NULL || exfer->sitdend == NULL) 2252 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2253 2254 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2255 prev = sitd->u.frame_list.prev; 2256 /* Unlink sitd from hardware chain, or frame array */ 2257 if (prev == NULL) { /* We're at the table head */ 2258 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2259 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2260 usb_syncmem(&sc->sc_fldma, 2261 sizeof(ehci_link_t) * sitd->slot, 2262 sizeof(ehci_link_t), 2263 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2264 2265 if (sitd->u.frame_list.next != NULL) 2266 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2267 } else { 2268 /* XXX this part is untested... */ 2269 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2270 usb_syncmem(&sitd->dma, 2271 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2272 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2273 2274 prev->u.frame_list.next = sitd->u.frame_list.next; 2275 if (sitd->u.frame_list.next != NULL) 2276 sitd->u.frame_list.next->u.frame_list.prev = prev; 2277 } 2278 } 2279 2280 prev = NULL; 2281 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2282 if (prev != NULL) 2283 ehci_free_sitd(sc, prev); 2284 prev = sitd; 2285 } 2286 if (prev) 2287 ehci_free_sitd(sc, prev); 2288 exfer->sitdstart = NULL; 2289 exfer->sitdend = NULL; 2290 } 2291 2292 2293 /***********/ 2294 2295 /* 2296 * Data structures and routines to emulate the root hub. 2297 */ 2298 Static usb_device_descriptor_t ehci_devd = { 2299 USB_DEVICE_DESCRIPTOR_SIZE, 2300 UDESC_DEVICE, /* type */ 2301 {0x00, 0x02}, /* USB version */ 2302 UDCLASS_HUB, /* class */ 2303 UDSUBCLASS_HUB, /* subclass */ 2304 UDPROTO_HSHUBSTT, /* protocol */ 2305 64, /* max packet */ 2306 {0},{0},{0x00,0x01}, /* device id */ 2307 1,2,0, /* string indicies */ 2308 1 /* # of configurations */ 2309 }; 2310 2311 Static const usb_device_qualifier_t ehci_odevd = { 2312 USB_DEVICE_DESCRIPTOR_SIZE, 2313 UDESC_DEVICE_QUALIFIER, /* type */ 2314 {0x00, 0x02}, /* USB version */ 2315 UDCLASS_HUB, /* class */ 2316 UDSUBCLASS_HUB, /* subclass */ 2317 UDPROTO_FSHUB, /* protocol */ 2318 64, /* max packet */ 2319 1, /* # of configurations */ 2320 0 2321 }; 2322 2323 Static const usb_config_descriptor_t ehci_confd = { 2324 USB_CONFIG_DESCRIPTOR_SIZE, 2325 UDESC_CONFIG, 2326 {USB_CONFIG_DESCRIPTOR_SIZE + 2327 USB_INTERFACE_DESCRIPTOR_SIZE + 2328 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2329 1, 2330 1, 2331 0, 2332 UC_ATTR_MBO | UC_SELF_POWERED, 2333 0 /* max power */ 2334 }; 2335 2336 Static const usb_interface_descriptor_t ehci_ifcd = { 2337 USB_INTERFACE_DESCRIPTOR_SIZE, 2338 UDESC_INTERFACE, 2339 0, 2340 0, 2341 1, 2342 UICLASS_HUB, 2343 UISUBCLASS_HUB, 2344 UIPROTO_HSHUBSTT, 2345 0 2346 }; 2347 2348 Static const usb_endpoint_descriptor_t ehci_endpd = { 2349 USB_ENDPOINT_DESCRIPTOR_SIZE, 2350 UDESC_ENDPOINT, 2351 UE_DIR_IN | EHCI_INTR_ENDPT, 2352 UE_INTERRUPT, 2353 {8, 0}, /* max packet */ 2354 12 2355 }; 2356 2357 Static const usb_hub_descriptor_t ehci_hubd = { 2358 USB_HUB_DESCRIPTOR_SIZE, 2359 UDESC_HUB, 2360 0, 2361 {0,0}, 2362 0, 2363 0, 2364 {""}, 2365 {""}, 2366 }; 2367 2368 /* 2369 * Simulate a hardware hub by handling all the necessary requests. 2370 */ 2371 Static usbd_status 2372 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2373 { 2374 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2375 usbd_status err; 2376 2377 /* Insert last in queue. */ 2378 mutex_enter(&sc->sc_lock); 2379 err = usb_insert_transfer(xfer); 2380 mutex_exit(&sc->sc_lock); 2381 if (err) 2382 return (err); 2383 2384 /* Pipe isn't running, start first */ 2385 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2386 } 2387 2388 Static usbd_status 2389 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2390 { 2391 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2392 usb_device_request_t *req; 2393 void *buf = NULL; 2394 int port, i; 2395 int len, value, index, l, totlen = 0; 2396 usb_port_status_t ps; 2397 usb_hub_descriptor_t hubd; 2398 usbd_status err; 2399 uint32_t v; 2400 2401 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2402 2403 if (sc->sc_dying) 2404 return (USBD_IOERROR); 2405 2406 #ifdef DIAGNOSTIC 2407 if (!(xfer->rqflags & URQ_REQUEST)) 2408 /* XXX panic */ 2409 return (USBD_INVAL); 2410 #endif 2411 req = &xfer->request; 2412 2413 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2414 req->bmRequestType, req->bRequest, 0, 0); 2415 2416 len = UGETW(req->wLength); 2417 value = UGETW(req->wValue); 2418 index = UGETW(req->wIndex); 2419 2420 if (len != 0) 2421 buf = KERNADDR(&xfer->dmabuf, 0); 2422 2423 #define C(x,y) ((x) | ((y) << 8)) 2424 switch(C(req->bRequest, req->bmRequestType)) { 2425 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2426 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2427 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2428 /* 2429 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2430 * for the integrated root hub. 2431 */ 2432 break; 2433 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2434 if (len > 0) { 2435 *(uint8_t *)buf = sc->sc_conf; 2436 totlen = 1; 2437 } 2438 break; 2439 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2440 USBHIST_LOG(ehcidebug, "wValue=0x%04x", value, 0, 0, 0); 2441 if (len == 0) 2442 break; 2443 switch(value >> 8) { 2444 case UDESC_DEVICE: 2445 if ((value & 0xff) != 0) { 2446 err = USBD_IOERROR; 2447 goto ret; 2448 } 2449 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2450 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2451 memcpy(buf, &ehci_devd, l); 2452 break; 2453 /* 2454 * We can't really operate at another speed, but the spec says 2455 * we need this descriptor. 2456 */ 2457 case UDESC_DEVICE_QUALIFIER: 2458 if ((value & 0xff) != 0) { 2459 err = USBD_IOERROR; 2460 goto ret; 2461 } 2462 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2463 memcpy(buf, &ehci_odevd, l); 2464 break; 2465 /* 2466 * We can't really operate at another speed, but the spec says 2467 * we need this descriptor. 2468 */ 2469 case UDESC_OTHER_SPEED_CONFIGURATION: 2470 case UDESC_CONFIG: 2471 if ((value & 0xff) != 0) { 2472 err = USBD_IOERROR; 2473 goto ret; 2474 } 2475 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2476 memcpy(buf, &ehci_confd, l); 2477 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2478 value >> 8; 2479 buf = (char *)buf + l; 2480 len -= l; 2481 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2482 totlen += l; 2483 memcpy(buf, &ehci_ifcd, l); 2484 buf = (char *)buf + l; 2485 len -= l; 2486 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2487 totlen += l; 2488 memcpy(buf, &ehci_endpd, l); 2489 break; 2490 case UDESC_STRING: 2491 #define sd ((usb_string_descriptor_t *)buf) 2492 switch (value & 0xff) { 2493 case 0: /* Language table */ 2494 totlen = usb_makelangtbl(sd, len); 2495 break; 2496 case 1: /* Vendor */ 2497 totlen = usb_makestrdesc(sd, len, 2498 sc->sc_vendor); 2499 break; 2500 case 2: /* Product */ 2501 totlen = usb_makestrdesc(sd, len, 2502 "EHCI root hub"); 2503 break; 2504 } 2505 #undef sd 2506 break; 2507 default: 2508 err = USBD_IOERROR; 2509 goto ret; 2510 } 2511 break; 2512 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2513 if (len > 0) { 2514 *(uint8_t *)buf = 0; 2515 totlen = 1; 2516 } 2517 break; 2518 case C(UR_GET_STATUS, UT_READ_DEVICE): 2519 if (len > 1) { 2520 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2521 totlen = 2; 2522 } 2523 break; 2524 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2525 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2526 if (len > 1) { 2527 USETW(((usb_status_t *)buf)->wStatus, 0); 2528 totlen = 2; 2529 } 2530 break; 2531 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2532 if (value >= USB_MAX_DEVICES) { 2533 err = USBD_IOERROR; 2534 goto ret; 2535 } 2536 sc->sc_addr = value; 2537 break; 2538 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2539 if (value != 0 && value != 1) { 2540 err = USBD_IOERROR; 2541 goto ret; 2542 } 2543 sc->sc_conf = value; 2544 break; 2545 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2546 break; 2547 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2548 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2549 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2550 err = USBD_IOERROR; 2551 goto ret; 2552 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2553 break; 2554 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2555 break; 2556 /* Hub requests */ 2557 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2558 break; 2559 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2560 USBHIST_LOG(ehcidebug, 2561 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2562 0, 0); 2563 if (index < 1 || index > sc->sc_noport) { 2564 err = USBD_IOERROR; 2565 goto ret; 2566 } 2567 port = EHCI_PORTSC(index); 2568 v = EOREAD4(sc, port); 2569 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2570 v &= ~EHCI_PS_CLEAR; 2571 switch(value) { 2572 case UHF_PORT_ENABLE: 2573 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2574 break; 2575 case UHF_PORT_SUSPEND: 2576 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2577 break; 2578 v &= ~EHCI_PS_SUSP; 2579 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2580 /* see USB2 spec ch. 7.1.7.7 */ 2581 usb_delay_ms(&sc->sc_bus, 20); 2582 EOWRITE4(sc, port, v); 2583 usb_delay_ms(&sc->sc_bus, 2); 2584 #ifdef DEBUG 2585 v = EOREAD4(sc, port); 2586 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2587 printf("ehci: resume failed: %x\n", v); 2588 #endif 2589 break; 2590 case UHF_PORT_POWER: 2591 if (sc->sc_hasppc) 2592 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2593 break; 2594 case UHF_PORT_TEST: 2595 USBHIST_LOG(ehcidebug, "clear port test " 2596 "%d", index, 0, 0, 0); 2597 break; 2598 case UHF_PORT_INDICATOR: 2599 USBHIST_LOG(ehcidebug, "clear port ind " 2600 "%d", index, 0, 0, 0); 2601 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2602 break; 2603 case UHF_C_PORT_CONNECTION: 2604 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2605 break; 2606 case UHF_C_PORT_ENABLE: 2607 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2608 break; 2609 case UHF_C_PORT_SUSPEND: 2610 /* how? */ 2611 break; 2612 case UHF_C_PORT_OVER_CURRENT: 2613 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2614 break; 2615 case UHF_C_PORT_RESET: 2616 sc->sc_isreset[index] = 0; 2617 break; 2618 default: 2619 err = USBD_IOERROR; 2620 goto ret; 2621 } 2622 #if 0 2623 switch(value) { 2624 case UHF_C_PORT_CONNECTION: 2625 case UHF_C_PORT_ENABLE: 2626 case UHF_C_PORT_SUSPEND: 2627 case UHF_C_PORT_OVER_CURRENT: 2628 case UHF_C_PORT_RESET: 2629 default: 2630 break; 2631 } 2632 #endif 2633 break; 2634 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2635 if (len == 0) 2636 break; 2637 if ((value & 0xff) != 0) { 2638 err = USBD_IOERROR; 2639 goto ret; 2640 } 2641 hubd = ehci_hubd; 2642 hubd.bNbrPorts = sc->sc_noport; 2643 v = EOREAD4(sc, EHCI_HCSPARAMS); 2644 USETW(hubd.wHubCharacteristics, 2645 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2646 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2647 ? UHD_PORT_IND : 0); 2648 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2649 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2650 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2651 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2652 l = min(len, hubd.bDescLength); 2653 totlen = l; 2654 memcpy(buf, &hubd, l); 2655 break; 2656 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2657 if (len != 4) { 2658 err = USBD_IOERROR; 2659 goto ret; 2660 } 2661 memset(buf, 0, len); /* ? XXX */ 2662 totlen = len; 2663 break; 2664 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2665 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2666 if (index < 1 || index > sc->sc_noport) { 2667 err = USBD_IOERROR; 2668 goto ret; 2669 } 2670 if (len != 4) { 2671 err = USBD_IOERROR; 2672 goto ret; 2673 } 2674 v = EOREAD4(sc, EHCI_PORTSC(index)); 2675 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2676 2677 i = UPS_HIGH_SPEED; 2678 if (sc->sc_flags & EHCIF_ETTF) { 2679 /* 2680 * If we are doing embedded transaction translation, 2681 * then directly attached LS/FS devices are reset by 2682 * the EHCI controller itself. PSPD is encoded 2683 * the same way as in USBSTATUS. 2684 */ 2685 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2686 } 2687 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2688 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2689 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2690 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2691 if (v & EHCI_PS_PR) i |= UPS_RESET; 2692 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2693 if (sc->sc_vendor_port_status) 2694 i = sc->sc_vendor_port_status(sc, v, i); 2695 USETW(ps.wPortStatus, i); 2696 i = 0; 2697 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2698 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2699 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2700 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2701 USETW(ps.wPortChange, i); 2702 l = min(len, sizeof ps); 2703 memcpy(buf, &ps, l); 2704 totlen = l; 2705 break; 2706 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2707 err = USBD_IOERROR; 2708 goto ret; 2709 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2710 break; 2711 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2712 if (index < 1 || index > sc->sc_noport) { 2713 err = USBD_IOERROR; 2714 goto ret; 2715 } 2716 port = EHCI_PORTSC(index); 2717 v = EOREAD4(sc, port); 2718 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2719 v &= ~EHCI_PS_CLEAR; 2720 switch(value) { 2721 case UHF_PORT_ENABLE: 2722 EOWRITE4(sc, port, v | EHCI_PS_PE); 2723 break; 2724 case UHF_PORT_SUSPEND: 2725 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2726 break; 2727 case UHF_PORT_RESET: 2728 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2729 if (EHCI_PS_IS_LOWSPEED(v) 2730 && sc->sc_ncomp > 0 2731 && !(sc->sc_flags & EHCIF_ETTF)) { 2732 /* 2733 * Low speed device on non-ETTF controller or 2734 * unaccompanied controller, give up ownership. 2735 */ 2736 ehci_disown(sc, index, 1); 2737 break; 2738 } 2739 /* Start reset sequence. */ 2740 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2741 EOWRITE4(sc, port, v | EHCI_PS_PR); 2742 /* Wait for reset to complete. */ 2743 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2744 if (sc->sc_dying) { 2745 err = USBD_IOERROR; 2746 goto ret; 2747 } 2748 /* 2749 * An embedded transaction translator will automatically 2750 * terminate the reset sequence so there's no need to 2751 * it. 2752 */ 2753 v = EOREAD4(sc, port); 2754 if (v & EHCI_PS_PR) { 2755 /* Terminate reset sequence. */ 2756 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2757 /* Wait for HC to complete reset. */ 2758 usb_delay_ms(&sc->sc_bus, 2759 EHCI_PORT_RESET_COMPLETE); 2760 if (sc->sc_dying) { 2761 err = USBD_IOERROR; 2762 goto ret; 2763 } 2764 } 2765 2766 v = EOREAD4(sc, port); 2767 USBHIST_LOG(ehcidebug, 2768 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2769 if (v & EHCI_PS_PR) { 2770 printf("%s: port reset timeout\n", 2771 device_xname(sc->sc_dev)); 2772 return (USBD_TIMEOUT); 2773 } 2774 if (!(v & EHCI_PS_PE)) { 2775 /* Not a high speed device, give up ownership.*/ 2776 ehci_disown(sc, index, 0); 2777 break; 2778 } 2779 sc->sc_isreset[index] = 1; 2780 USBHIST_LOG(ehcidebug, 2781 "ehci port %d reset, status = 0x%08x", index, v, 0, 2782 0); 2783 break; 2784 case UHF_PORT_POWER: 2785 USBHIST_LOG(ehcidebug, 2786 "set port power %d (has PPC = %d)", index, 2787 sc->sc_hasppc, 0, 0); 2788 if (sc->sc_hasppc) 2789 EOWRITE4(sc, port, v | EHCI_PS_PP); 2790 break; 2791 case UHF_PORT_TEST: 2792 USBHIST_LOG(ehcidebug, "set port test %d", 2793 index, 0, 0, 0); 2794 break; 2795 case UHF_PORT_INDICATOR: 2796 USBHIST_LOG(ehcidebug, "set port ind %d", 2797 index, 0, 0, 0); 2798 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2799 break; 2800 default: 2801 err = USBD_IOERROR; 2802 goto ret; 2803 } 2804 break; 2805 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2806 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2807 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2808 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2809 break; 2810 default: 2811 err = USBD_IOERROR; 2812 goto ret; 2813 } 2814 xfer->actlen = totlen; 2815 err = USBD_NORMAL_COMPLETION; 2816 ret: 2817 mutex_enter(&sc->sc_lock); 2818 xfer->status = err; 2819 usb_transfer_complete(xfer); 2820 mutex_exit(&sc->sc_lock); 2821 return (USBD_IN_PROGRESS); 2822 } 2823 2824 Static void 2825 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2826 { 2827 int port; 2828 uint32_t v; 2829 2830 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2831 2832 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2833 #ifdef DIAGNOSTIC 2834 if (sc->sc_npcomp != 0) { 2835 int i = (index-1) / sc->sc_npcomp; 2836 if (i >= sc->sc_ncomp) 2837 printf("%s: strange port\n", 2838 device_xname(sc->sc_dev)); 2839 else 2840 printf("%s: handing over %s speed device on " 2841 "port %d to %s\n", 2842 device_xname(sc->sc_dev), 2843 lowspeed ? "low" : "full", 2844 index, device_xname(sc->sc_comps[i])); 2845 } else { 2846 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2847 } 2848 #endif 2849 port = EHCI_PORTSC(index); 2850 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2851 EOWRITE4(sc, port, v | EHCI_PS_PO); 2852 } 2853 2854 /* Abort a root control request. */ 2855 Static void 2856 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2857 { 2858 /* Nothing to do, all transfers are synchronous. */ 2859 } 2860 2861 /* Close the root pipe. */ 2862 Static void 2863 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2864 { 2865 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2866 /* Nothing to do. */ 2867 } 2868 2869 Static void 2870 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2871 { 2872 xfer->hcpriv = NULL; 2873 } 2874 2875 Static usbd_status 2876 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2877 { 2878 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2879 usbd_status err; 2880 2881 /* Insert last in queue. */ 2882 mutex_enter(&sc->sc_lock); 2883 err = usb_insert_transfer(xfer); 2884 mutex_exit(&sc->sc_lock); 2885 if (err) 2886 return (err); 2887 2888 /* Pipe isn't running, start first */ 2889 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2890 } 2891 2892 Static usbd_status 2893 ehci_root_intr_start(usbd_xfer_handle xfer) 2894 { 2895 usbd_pipe_handle pipe = xfer->pipe; 2896 ehci_softc_t *sc = pipe->device->bus->hci_private; 2897 2898 if (sc->sc_dying) 2899 return (USBD_IOERROR); 2900 2901 mutex_enter(&sc->sc_lock); 2902 sc->sc_intrxfer = xfer; 2903 mutex_exit(&sc->sc_lock); 2904 2905 return (USBD_IN_PROGRESS); 2906 } 2907 2908 /* Abort a root interrupt request. */ 2909 Static void 2910 ehci_root_intr_abort(usbd_xfer_handle xfer) 2911 { 2912 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2913 2914 KASSERT(mutex_owned(&sc->sc_lock)); 2915 KASSERT(xfer->pipe->intrxfer == xfer); 2916 2917 sc->sc_intrxfer = NULL; 2918 2919 xfer->status = USBD_CANCELLED; 2920 usb_transfer_complete(xfer); 2921 } 2922 2923 /* Close the root pipe. */ 2924 Static void 2925 ehci_root_intr_close(usbd_pipe_handle pipe) 2926 { 2927 ehci_softc_t *sc = pipe->device->bus->hci_private; 2928 2929 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2930 2931 KASSERT(mutex_owned(&sc->sc_lock)); 2932 2933 sc->sc_intrxfer = NULL; 2934 } 2935 2936 Static void 2937 ehci_root_intr_done(usbd_xfer_handle xfer) 2938 { 2939 xfer->hcpriv = NULL; 2940 } 2941 2942 /************************/ 2943 2944 Static ehci_soft_qh_t * 2945 ehci_alloc_sqh(ehci_softc_t *sc) 2946 { 2947 ehci_soft_qh_t *sqh; 2948 usbd_status err; 2949 int i, offs; 2950 usb_dma_t dma; 2951 2952 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2953 2954 if (sc->sc_freeqhs == NULL) { 2955 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2956 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2957 EHCI_PAGE_SIZE, &dma); 2958 #ifdef EHCI_DEBUG 2959 if (err) 2960 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2961 #endif 2962 if (err) 2963 return (NULL); 2964 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2965 offs = i * EHCI_SQH_SIZE; 2966 sqh = KERNADDR(&dma, offs); 2967 sqh->physaddr = DMAADDR(&dma, offs); 2968 sqh->dma = dma; 2969 sqh->offs = offs; 2970 sqh->next = sc->sc_freeqhs; 2971 sc->sc_freeqhs = sqh; 2972 } 2973 } 2974 sqh = sc->sc_freeqhs; 2975 sc->sc_freeqhs = sqh->next; 2976 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2977 sqh->next = NULL; 2978 return (sqh); 2979 } 2980 2981 Static void 2982 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2983 { 2984 sqh->next = sc->sc_freeqhs; 2985 sc->sc_freeqhs = sqh; 2986 } 2987 2988 Static ehci_soft_qtd_t * 2989 ehci_alloc_sqtd(ehci_softc_t *sc) 2990 { 2991 ehci_soft_qtd_t *sqtd = NULL; 2992 usbd_status err; 2993 int i, offs; 2994 usb_dma_t dma; 2995 2996 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2997 2998 if (sc->sc_freeqtds == NULL) { 2999 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3000 3001 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 3002 EHCI_PAGE_SIZE, &dma); 3003 #ifdef EHCI_DEBUG 3004 if (err) 3005 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 3006 #endif 3007 if (err) 3008 goto done; 3009 3010 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 3011 offs = i * EHCI_SQTD_SIZE; 3012 sqtd = KERNADDR(&dma, offs); 3013 sqtd->physaddr = DMAADDR(&dma, offs); 3014 sqtd->dma = dma; 3015 sqtd->offs = offs; 3016 3017 sqtd->nextqtd = sc->sc_freeqtds; 3018 sc->sc_freeqtds = sqtd; 3019 } 3020 } 3021 3022 sqtd = sc->sc_freeqtds; 3023 sc->sc_freeqtds = sqtd->nextqtd; 3024 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 3025 sqtd->nextqtd = NULL; 3026 sqtd->xfer = NULL; 3027 3028 done: 3029 return (sqtd); 3030 } 3031 3032 Static void 3033 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 3034 { 3035 3036 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3037 3038 sqtd->nextqtd = sc->sc_freeqtds; 3039 sc->sc_freeqtds = sqtd; 3040 } 3041 3042 Static usbd_status 3043 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 3044 int alen, int rd, usbd_xfer_handle xfer, 3045 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 3046 { 3047 ehci_soft_qtd_t *next, *cur; 3048 ehci_physaddr_t nextphys; 3049 uint32_t qtdstatus; 3050 int len, curlen, mps; 3051 int i, tog; 3052 int pages, pageoffs; 3053 bus_size_t curoffs; 3054 vaddr_t va, va_offs; 3055 usb_dma_t *dma = &xfer->dmabuf; 3056 uint16_t flags = xfer->flags; 3057 paddr_t a; 3058 3059 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3060 3061 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 3062 3063 len = alen; 3064 qtdstatus = EHCI_QTD_ACTIVE | 3065 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3066 EHCI_QTD_SET_CERR(3) 3067 /* IOC set below */ 3068 /* BYTES set below */ 3069 ; 3070 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3071 tog = epipe->nexttoggle; 3072 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 3073 3074 cur = ehci_alloc_sqtd(sc); 3075 *sp = cur; 3076 if (cur == NULL) 3077 goto nomem; 3078 3079 usb_syncmem(dma, 0, alen, 3080 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3081 curoffs = 0; 3082 for (;;) { 3083 /* The EHCI hardware can handle at most 5 pages. */ 3084 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 3085 va_offs = EHCI_PAGE_OFFSET(va_offs); 3086 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 3087 /* we can handle it in this QTD */ 3088 curlen = len - curoffs; 3089 } else { 3090 /* must use multiple TDs, fill as much as possible. */ 3091 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 3092 3093 /* the length must be a multiple of the max size */ 3094 curlen -= curlen % mps; 3095 USBHIST_LOG(ehcidebug, "multiple QTDs, " 3096 "curlen=%d", curlen, 0, 0, 0); 3097 #ifdef DIAGNOSTIC 3098 if (curlen == 0) 3099 panic("ehci_alloc_sqtd_chain: curlen == 0"); 3100 #endif 3101 } 3102 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 3103 len, curlen, (size_t)curoffs, 0); 3104 3105 /* 3106 * Allocate another transfer if there's more data left, 3107 * or if force last short transfer flag is set and we're 3108 * allocating a multiple of the max packet size. 3109 */ 3110 3111 if (curoffs + curlen != len || 3112 ((curlen % mps) == 0 && !rd && curlen != 0 && 3113 (flags & USBD_FORCE_SHORT_XFER))) { 3114 next = ehci_alloc_sqtd(sc); 3115 if (next == NULL) 3116 goto nomem; 3117 nextphys = htole32(next->physaddr); 3118 } else { 3119 next = NULL; 3120 nextphys = EHCI_NULL; 3121 } 3122 3123 /* Find number of pages we'll be using, insert dma addresses */ 3124 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 3125 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3126 pageoffs = EHCI_PAGE(curoffs); 3127 for (i = 0; i < pages; i++) { 3128 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 3129 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 3130 /* Cast up to avoid compiler warnings */ 3131 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 3132 } 3133 3134 /* First buffer pointer requires a page offset to start at */ 3135 va = (vaddr_t)KERNADDR(dma, curoffs); 3136 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3137 3138 cur->nextqtd = next; 3139 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 3140 cur->qtd.qtd_status = 3141 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 3142 cur->xfer = xfer; 3143 cur->len = curlen; 3144 3145 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 3146 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 3147 3148 /* adjust the toggle based on the number of packets in this 3149 qtd */ 3150 if (((curlen + mps - 1) / mps) & 1) { 3151 tog ^= 1; 3152 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 3153 } 3154 if (next == NULL) 3155 break; 3156 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 3157 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3158 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 3159 if (len) 3160 curoffs += curlen; 3161 cur = next; 3162 } 3163 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3164 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 3165 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3166 *ep = cur; 3167 epipe->nexttoggle = tog; 3168 3169 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 3170 *sp, *ep, 0, 0); 3171 3172 return (USBD_NORMAL_COMPLETION); 3173 3174 nomem: 3175 /* XXX free chain */ 3176 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3177 return (USBD_NOMEM); 3178 } 3179 3180 Static void 3181 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 3182 ehci_soft_qtd_t *sqtdend) 3183 { 3184 ehci_soft_qtd_t *p; 3185 int i; 3186 3187 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3188 3189 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 3190 sqtd, sqtdend, 0, 0); 3191 3192 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 3193 p = sqtd->nextqtd; 3194 ehci_free_sqtd(sc, sqtd); 3195 } 3196 } 3197 3198 Static ehci_soft_itd_t * 3199 ehci_alloc_itd(ehci_softc_t *sc) 3200 { 3201 struct ehci_soft_itd *itd, *freeitd; 3202 usbd_status err; 3203 int i, offs, frindex, previndex; 3204 usb_dma_t dma; 3205 3206 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3207 3208 mutex_enter(&sc->sc_lock); 3209 3210 /* Find an itd that wasn't freed this frame or last frame. This can 3211 * discard itds that were freed before frindex wrapped around 3212 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3213 * interrupt and fiddling with list when that happens */ 3214 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3215 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3216 3217 freeitd = NULL; 3218 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 3219 if (itd == NULL) 3220 break; 3221 if (itd->slot != frindex && itd->slot != previndex) { 3222 freeitd = itd; 3223 break; 3224 } 3225 } 3226 3227 if (freeitd == NULL) { 3228 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3229 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3230 EHCI_PAGE_SIZE, &dma); 3231 3232 if (err) { 3233 USBHIST_LOG(ehcidebug, 3234 "alloc returned %d", err, 0, 0, 0); 3235 mutex_exit(&sc->sc_lock); 3236 return NULL; 3237 } 3238 3239 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 3240 offs = i * EHCI_ITD_SIZE; 3241 itd = KERNADDR(&dma, offs); 3242 itd->physaddr = DMAADDR(&dma, offs); 3243 itd->dma = dma; 3244 itd->offs = offs; 3245 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3246 } 3247 freeitd = LIST_FIRST(&sc->sc_freeitds); 3248 } 3249 3250 itd = freeitd; 3251 LIST_REMOVE(itd, u.free_list); 3252 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3253 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 3254 sizeof(itd->itd.itd_next), 3255 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3256 3257 itd->u.frame_list.next = NULL; 3258 itd->u.frame_list.prev = NULL; 3259 itd->xfer_next = NULL; 3260 itd->slot = 0; 3261 3262 mutex_exit(&sc->sc_lock); 3263 3264 return itd; 3265 } 3266 3267 Static ehci_soft_sitd_t * 3268 ehci_alloc_sitd(ehci_softc_t *sc) 3269 { 3270 struct ehci_soft_sitd *sitd, *freesitd; 3271 usbd_status err; 3272 int i, offs, frindex, previndex; 3273 usb_dma_t dma; 3274 3275 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3276 3277 mutex_enter(&sc->sc_lock); 3278 3279 /* Find an sitd that wasn't freed this frame or last frame. This can 3280 * discard sitds that were freed before frindex wrapped around 3281 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3282 * interrupt and fiddling with list when that happens */ 3283 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3284 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3285 3286 freesitd = NULL; 3287 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 3288 if (sitd == NULL) 3289 break; 3290 if (sitd->slot != frindex && sitd->slot != previndex) { 3291 freesitd = sitd; 3292 break; 3293 } 3294 } 3295 3296 if (freesitd == NULL) { 3297 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3298 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3299 EHCI_PAGE_SIZE, &dma); 3300 3301 if (err) { 3302 USBHIST_LOG(ehcidebug, 3303 "alloc returned %d", err, 0, 0, 0); 3304 mutex_exit(&sc->sc_lock); 3305 return NULL; 3306 } 3307 3308 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3309 offs = i * EHCI_SITD_SIZE; 3310 sitd = KERNADDR(&dma, offs); 3311 sitd->physaddr = DMAADDR(&dma, offs); 3312 sitd->dma = dma; 3313 sitd->offs = offs; 3314 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3315 } 3316 freesitd = LIST_FIRST(&sc->sc_freesitds); 3317 } 3318 3319 sitd = freesitd; 3320 LIST_REMOVE(sitd, u.free_list); 3321 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3322 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3323 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3324 BUS_DMASYNC_PREREAD); 3325 3326 sitd->u.frame_list.next = NULL; 3327 sitd->u.frame_list.prev = NULL; 3328 sitd->xfer_next = NULL; 3329 sitd->slot = 0; 3330 3331 mutex_exit(&sc->sc_lock); 3332 3333 return sitd; 3334 } 3335 3336 Static void 3337 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3338 { 3339 3340 KASSERT(mutex_owned(&sc->sc_lock)); 3341 3342 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3343 } 3344 3345 Static void 3346 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3347 { 3348 3349 KASSERT(mutex_owned(&sc->sc_lock)); 3350 3351 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3352 } 3353 3354 /****************/ 3355 3356 /* 3357 * Close a reqular pipe. 3358 * Assumes that there are no pending transactions. 3359 */ 3360 Static void 3361 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3362 { 3363 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3364 ehci_softc_t *sc = pipe->device->bus->hci_private; 3365 ehci_soft_qh_t *sqh = epipe->sqh; 3366 3367 KASSERT(mutex_owned(&sc->sc_lock)); 3368 3369 ehci_rem_qh(sc, sqh, head); 3370 ehci_free_sqh(sc, epipe->sqh); 3371 } 3372 3373 /* 3374 * Abort a device request. 3375 * If this routine is called at splusb() it guarantees that the request 3376 * will be removed from the hardware scheduling and that the callback 3377 * for it will be called with USBD_CANCELLED status. 3378 * It's impossible to guarantee that the requested transfer will not 3379 * have happened since the hardware runs concurrently. 3380 * If the transaction has already happened we rely on the ordinary 3381 * interrupt processing to process it. 3382 * XXX This is most probably wrong. 3383 * XXXMRG this doesn't make sense anymore. 3384 */ 3385 Static void 3386 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3387 { 3388 #define exfer EXFER(xfer) 3389 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3390 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3391 ehci_soft_qh_t *sqh = epipe->sqh; 3392 ehci_soft_qtd_t *sqtd; 3393 ehci_physaddr_t cur; 3394 uint32_t qhstatus; 3395 int hit; 3396 int wake; 3397 3398 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3399 3400 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3401 3402 KASSERT(mutex_owned(&sc->sc_lock)); 3403 ASSERT_SLEEPABLE(); 3404 3405 if (sc->sc_dying) { 3406 /* If we're dying, just do the software part. */ 3407 xfer->status = status; /* make software ignore it */ 3408 callout_stop(&xfer->timeout_handle); 3409 usb_transfer_complete(xfer); 3410 return; 3411 } 3412 3413 /* 3414 * If an abort is already in progress then just wait for it to 3415 * complete and return. 3416 */ 3417 if (xfer->hcflags & UXFER_ABORTING) { 3418 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3419 #ifdef DIAGNOSTIC 3420 if (status == USBD_TIMEOUT) 3421 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3422 #endif 3423 /* Override the status which might be USBD_TIMEOUT. */ 3424 xfer->status = status; 3425 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3426 0, 0, 0, 0); 3427 xfer->hcflags |= UXFER_ABORTWAIT; 3428 while (xfer->hcflags & UXFER_ABORTING) 3429 cv_wait(&xfer->hccv, &sc->sc_lock); 3430 return; 3431 } 3432 xfer->hcflags |= UXFER_ABORTING; 3433 3434 /* 3435 * Step 1: Make interrupt routine and hardware ignore xfer. 3436 */ 3437 xfer->status = status; /* make software ignore it */ 3438 callout_stop(&xfer->timeout_handle); 3439 3440 usb_syncmem(&sqh->dma, 3441 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3442 sizeof(sqh->qh.qh_qtd.qtd_status), 3443 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3444 qhstatus = sqh->qh.qh_qtd.qtd_status; 3445 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3446 usb_syncmem(&sqh->dma, 3447 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3448 sizeof(sqh->qh.qh_qtd.qtd_status), 3449 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3450 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3451 usb_syncmem(&sqtd->dma, 3452 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3453 sizeof(sqtd->qtd.qtd_status), 3454 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3455 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3456 usb_syncmem(&sqtd->dma, 3457 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3458 sizeof(sqtd->qtd.qtd_status), 3459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3460 if (sqtd == exfer->sqtdend) 3461 break; 3462 } 3463 3464 /* 3465 * Step 2: Wait until we know hardware has finished any possible 3466 * use of the xfer. Also make sure the soft interrupt routine 3467 * has run. 3468 */ 3469 ehci_sync_hc(sc); 3470 sc->sc_softwake = 1; 3471 usb_schedsoftintr(&sc->sc_bus); 3472 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3473 3474 /* 3475 * Step 3: Remove any vestiges of the xfer from the hardware. 3476 * The complication here is that the hardware may have executed 3477 * beyond the xfer we're trying to abort. So as we're scanning 3478 * the TDs of this xfer we check if the hardware points to 3479 * any of them. 3480 */ 3481 3482 usb_syncmem(&sqh->dma, 3483 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3484 sizeof(sqh->qh.qh_curqtd), 3485 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3486 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3487 hit = 0; 3488 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3489 hit |= cur == sqtd->physaddr; 3490 if (sqtd == exfer->sqtdend) 3491 break; 3492 } 3493 sqtd = sqtd->nextqtd; 3494 /* Zap curqtd register if hardware pointed inside the xfer. */ 3495 if (hit && sqtd != NULL) { 3496 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3497 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3498 usb_syncmem(&sqh->dma, 3499 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3500 sizeof(sqh->qh.qh_curqtd), 3501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3502 sqh->qh.qh_qtd.qtd_status = qhstatus; 3503 usb_syncmem(&sqh->dma, 3504 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3505 sizeof(sqh->qh.qh_qtd.qtd_status), 3506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3507 } else { 3508 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3509 } 3510 3511 /* 3512 * Step 4: Execute callback. 3513 */ 3514 #ifdef DIAGNOSTIC 3515 exfer->isdone = 1; 3516 #endif 3517 wake = xfer->hcflags & UXFER_ABORTWAIT; 3518 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3519 usb_transfer_complete(xfer); 3520 if (wake) { 3521 cv_broadcast(&xfer->hccv); 3522 } 3523 3524 KASSERT(mutex_owned(&sc->sc_lock)); 3525 #undef exfer 3526 } 3527 3528 Static void 3529 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3530 { 3531 ehci_isoc_trans_t trans_status; 3532 struct ehci_pipe *epipe; 3533 struct ehci_xfer *exfer; 3534 ehci_softc_t *sc; 3535 struct ehci_soft_itd *itd; 3536 struct ehci_soft_sitd *sitd; 3537 int i, wake; 3538 3539 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3540 3541 epipe = (struct ehci_pipe *) xfer->pipe; 3542 exfer = EXFER(xfer); 3543 sc = epipe->pipe.device->bus->hci_private; 3544 3545 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3546 3547 KASSERT(mutex_owned(&sc->sc_lock)); 3548 3549 if (sc->sc_dying) { 3550 xfer->status = status; 3551 callout_stop(&xfer->timeout_handle); 3552 usb_transfer_complete(xfer); 3553 return; 3554 } 3555 3556 if (xfer->hcflags & UXFER_ABORTING) { 3557 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3558 3559 #ifdef DIAGNOSTIC 3560 if (status == USBD_TIMEOUT) 3561 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3562 #endif 3563 3564 xfer->status = status; 3565 USBHIST_LOG(ehcidebug, 3566 "waiting for abort to finish", 0, 0, 0, 0); 3567 xfer->hcflags |= UXFER_ABORTWAIT; 3568 while (xfer->hcflags & UXFER_ABORTING) 3569 cv_wait(&xfer->hccv, &sc->sc_lock); 3570 goto done; 3571 } 3572 xfer->hcflags |= UXFER_ABORTING; 3573 3574 xfer->status = status; 3575 callout_stop(&xfer->timeout_handle); 3576 3577 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3578 usb_syncmem(&itd->dma, 3579 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3580 sizeof(itd->itd.itd_ctl), 3581 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3582 3583 for (i = 0; i < 8; i++) { 3584 trans_status = le32toh(itd->itd.itd_ctl[i]); 3585 trans_status &= ~EHCI_ITD_ACTIVE; 3586 itd->itd.itd_ctl[i] = htole32(trans_status); 3587 } 3588 3589 usb_syncmem(&itd->dma, 3590 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3591 sizeof(itd->itd.itd_ctl), 3592 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3593 } 3594 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 3595 usb_syncmem(&sitd->dma, 3596 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3597 sizeof(sitd->sitd.sitd_buffer), 3598 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3599 3600 trans_status = le32toh(sitd->sitd.sitd_trans); 3601 trans_status &= ~EHCI_SITD_ACTIVE; 3602 sitd->sitd.sitd_trans = htole32(trans_status); 3603 3604 usb_syncmem(&sitd->dma, 3605 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3606 sizeof(sitd->sitd.sitd_buffer), 3607 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3608 } 3609 3610 sc->sc_softwake = 1; 3611 usb_schedsoftintr(&sc->sc_bus); 3612 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3613 3614 #ifdef DIAGNOSTIC 3615 exfer->isdone = 1; 3616 #endif 3617 wake = xfer->hcflags & UXFER_ABORTWAIT; 3618 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3619 usb_transfer_complete(xfer); 3620 if (wake) { 3621 cv_broadcast(&xfer->hccv); 3622 } 3623 3624 done: 3625 KASSERT(mutex_owned(&sc->sc_lock)); 3626 return; 3627 } 3628 3629 Static void 3630 ehci_timeout(void *addr) 3631 { 3632 struct ehci_xfer *exfer = addr; 3633 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3634 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3635 3636 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3637 3638 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3639 #ifdef EHCI_DEBUG 3640 if (ehcidebug > 1) 3641 usbd_dump_pipe(exfer->xfer.pipe); 3642 #endif 3643 3644 if (sc->sc_dying) { 3645 mutex_enter(&sc->sc_lock); 3646 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3647 mutex_exit(&sc->sc_lock); 3648 return; 3649 } 3650 3651 /* Execute the abort in a process context. */ 3652 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3653 USB_TASKQ_MPSAFE); 3654 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3655 USB_TASKQ_HC); 3656 } 3657 3658 Static void 3659 ehci_timeout_task(void *addr) 3660 { 3661 usbd_xfer_handle xfer = addr; 3662 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3663 3664 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3665 3666 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3667 3668 mutex_enter(&sc->sc_lock); 3669 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3670 mutex_exit(&sc->sc_lock); 3671 } 3672 3673 /************************/ 3674 3675 Static usbd_status 3676 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3677 { 3678 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3679 usbd_status err; 3680 3681 /* Insert last in queue. */ 3682 mutex_enter(&sc->sc_lock); 3683 err = usb_insert_transfer(xfer); 3684 mutex_exit(&sc->sc_lock); 3685 if (err) 3686 return (err); 3687 3688 /* Pipe isn't running, start first */ 3689 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3690 } 3691 3692 Static usbd_status 3693 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3694 { 3695 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3696 usbd_status err; 3697 3698 if (sc->sc_dying) 3699 return (USBD_IOERROR); 3700 3701 #ifdef DIAGNOSTIC 3702 if (!(xfer->rqflags & URQ_REQUEST)) { 3703 /* XXX panic */ 3704 printf("ehci_device_ctrl_transfer: not a request\n"); 3705 return (USBD_INVAL); 3706 } 3707 #endif 3708 3709 err = ehci_device_request(xfer); 3710 if (err) { 3711 return (err); 3712 } 3713 3714 if (sc->sc_bus.use_polling) 3715 ehci_waitintr(sc, xfer); 3716 3717 return (USBD_IN_PROGRESS); 3718 } 3719 3720 Static void 3721 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3722 { 3723 struct ehci_xfer *ex = EXFER(xfer); 3724 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3725 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3726 usb_device_request_t *req = &xfer->request; 3727 int len = UGETW(req->wLength); 3728 int rd = req->bmRequestType & UT_READ; 3729 3730 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3731 3732 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3733 3734 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3735 3736 #ifdef DIAGNOSTIC 3737 if (!(xfer->rqflags & URQ_REQUEST)) { 3738 panic("ehci_ctrl_done: not a request"); 3739 } 3740 #endif 3741 3742 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3743 ehci_del_intr_list(sc, ex); /* remove from active list */ 3744 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3745 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3746 BUS_DMASYNC_POSTWRITE); 3747 if (len) 3748 usb_syncmem(&xfer->dmabuf, 0, len, 3749 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3750 } 3751 3752 USBHIST_LOG(ehcidebug, "length=%d", xfer->actlen, 0, 0, 0); 3753 } 3754 3755 /* Abort a device control request. */ 3756 Static void 3757 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3758 { 3759 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3760 3761 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3762 ehci_abort_xfer(xfer, USBD_CANCELLED); 3763 } 3764 3765 /* Close a device control pipe. */ 3766 Static void 3767 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3768 { 3769 ehci_softc_t *sc = pipe->device->bus->hci_private; 3770 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3771 3772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3773 3774 KASSERT(mutex_owned(&sc->sc_lock)); 3775 3776 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3777 3778 ehci_close_pipe(pipe, sc->sc_async_head); 3779 } 3780 3781 Static usbd_status 3782 ehci_device_request(usbd_xfer_handle xfer) 3783 { 3784 #define exfer EXFER(xfer) 3785 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3786 usb_device_request_t *req = &xfer->request; 3787 usbd_device_handle dev = epipe->pipe.device; 3788 ehci_softc_t *sc = dev->bus->hci_private; 3789 ehci_soft_qtd_t *setup, *stat, *next; 3790 ehci_soft_qh_t *sqh; 3791 int isread; 3792 int len; 3793 usbd_status err; 3794 3795 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3796 3797 isread = req->bmRequestType & UT_READ; 3798 len = UGETW(req->wLength); 3799 3800 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3801 "wValue=0x%04x, wIndex=0x%04x", 3802 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3803 UGETW(req->wIndex)); 3804 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3805 len, dev->address, 3806 epipe->pipe.endpoint->edesc->bEndpointAddress, 0); 3807 3808 setup = ehci_alloc_sqtd(sc); 3809 if (setup == NULL) { 3810 err = USBD_NOMEM; 3811 goto bad1; 3812 } 3813 stat = ehci_alloc_sqtd(sc); 3814 if (stat == NULL) { 3815 err = USBD_NOMEM; 3816 goto bad2; 3817 } 3818 3819 mutex_enter(&sc->sc_lock); 3820 3821 sqh = epipe->sqh; 3822 3823 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->address, 3824 "address QH %d pipe %d\n", 3825 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->address); 3826 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3827 UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize), 3828 "MPS QH %d pipe %d\n", 3829 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3830 UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)); 3831 3832 /* Set up data transaction */ 3833 if (len != 0) { 3834 ehci_soft_qtd_t *end; 3835 3836 /* Start toggle at 1. */ 3837 epipe->nexttoggle = 1; 3838 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3839 &next, &end); 3840 if (err) 3841 goto bad3; 3842 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3843 end->nextqtd = stat; 3844 end->qtd.qtd_next = end->qtd.qtd_altnext = 3845 htole32(stat->physaddr); 3846 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3847 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3848 } else { 3849 next = stat; 3850 } 3851 3852 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3853 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3854 3855 /* Clear toggle */ 3856 setup->qtd.qtd_status = htole32( 3857 EHCI_QTD_ACTIVE | 3858 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3859 EHCI_QTD_SET_CERR(3) | 3860 EHCI_QTD_SET_TOGGLE(0) | 3861 EHCI_QTD_SET_BYTES(sizeof *req) 3862 ); 3863 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3864 setup->qtd.qtd_buffer_hi[0] = 0; 3865 setup->nextqtd = next; 3866 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3867 setup->xfer = xfer; 3868 setup->len = sizeof *req; 3869 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3870 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3871 3872 stat->qtd.qtd_status = htole32( 3873 EHCI_QTD_ACTIVE | 3874 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3875 EHCI_QTD_SET_CERR(3) | 3876 EHCI_QTD_SET_TOGGLE(1) | 3877 EHCI_QTD_IOC 3878 ); 3879 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3880 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3881 stat->nextqtd = NULL; 3882 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3883 stat->xfer = xfer; 3884 stat->len = 0; 3885 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3886 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3887 3888 #ifdef EHCI_DEBUG 3889 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3890 ehci_dump_sqh(sqh); 3891 ehci_dump_sqtds(setup); 3892 #endif 3893 3894 exfer->sqtdstart = setup; 3895 exfer->sqtdend = stat; 3896 #ifdef DIAGNOSTIC 3897 if (!exfer->isdone) { 3898 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3899 } 3900 exfer->isdone = 0; 3901 #endif 3902 3903 /* Insert qTD in QH list. */ 3904 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3905 if (xfer->timeout && !sc->sc_bus.use_polling) { 3906 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3907 ehci_timeout, xfer); 3908 } 3909 ehci_add_intr_list(sc, exfer); 3910 xfer->status = USBD_IN_PROGRESS; 3911 mutex_exit(&sc->sc_lock); 3912 3913 #ifdef EHCI_DEBUG 3914 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3915 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3916 // delay(10000); 3917 ehci_dump_regs(sc); 3918 ehci_dump_sqh(sc->sc_async_head); 3919 ehci_dump_sqh(sqh); 3920 ehci_dump_sqtds(setup); 3921 #endif 3922 3923 return (USBD_NORMAL_COMPLETION); 3924 3925 bad3: 3926 mutex_exit(&sc->sc_lock); 3927 ehci_free_sqtd(sc, stat); 3928 bad2: 3929 ehci_free_sqtd(sc, setup); 3930 bad1: 3931 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3932 mutex_enter(&sc->sc_lock); 3933 xfer->status = err; 3934 usb_transfer_complete(xfer); 3935 mutex_exit(&sc->sc_lock); 3936 return (err); 3937 #undef exfer 3938 } 3939 3940 /* 3941 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3942 * qTD status, or miss signalling occasionally under heavy load. If the host 3943 * machine is too fast, we we can miss transaction completion - when we scan 3944 * the active list the transaction still seems to be active. This generally 3945 * exhibits itself as a umass stall that never recovers. 3946 * 3947 * We work around this behaviour by setting up this callback after any softintr 3948 * that completes with transactions still pending, giving us another chance to 3949 * check for completion after the writeback has taken place. 3950 */ 3951 Static void 3952 ehci_intrlist_timeout(void *arg) 3953 { 3954 ehci_softc_t *sc = arg; 3955 3956 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3957 3958 usb_schedsoftintr(&sc->sc_bus); 3959 } 3960 3961 /************************/ 3962 3963 Static usbd_status 3964 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3965 { 3966 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3967 usbd_status err; 3968 3969 /* Insert last in queue. */ 3970 mutex_enter(&sc->sc_lock); 3971 err = usb_insert_transfer(xfer); 3972 mutex_exit(&sc->sc_lock); 3973 if (err) 3974 return (err); 3975 3976 /* Pipe isn't running, start first */ 3977 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3978 } 3979 3980 Static usbd_status 3981 ehci_device_bulk_start(usbd_xfer_handle xfer) 3982 { 3983 #define exfer EXFER(xfer) 3984 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3985 usbd_device_handle dev = epipe->pipe.device; 3986 ehci_softc_t *sc = dev->bus->hci_private; 3987 ehci_soft_qtd_t *data, *dataend; 3988 ehci_soft_qh_t *sqh; 3989 usbd_status err; 3990 int len, isread, endpt; 3991 3992 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3993 3994 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3995 xfer, xfer->length, xfer->flags, 0); 3996 3997 if (sc->sc_dying) 3998 return (USBD_IOERROR); 3999 4000 #ifdef DIAGNOSTIC 4001 if (xfer->rqflags & URQ_REQUEST) 4002 panic("ehci_device_bulk_start: a request"); 4003 #endif 4004 4005 mutex_enter(&sc->sc_lock); 4006 4007 len = xfer->length; 4008 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 4009 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4010 sqh = epipe->sqh; 4011 4012 epipe->u.bulk.length = len; 4013 4014 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 4015 &dataend); 4016 if (err) { 4017 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4018 xfer->status = err; 4019 usb_transfer_complete(xfer); 4020 mutex_exit(&sc->sc_lock); 4021 return (err); 4022 } 4023 4024 #ifdef EHCI_DEBUG 4025 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 4026 ehci_dump_sqh(sqh); 4027 ehci_dump_sqtds(data); 4028 #endif 4029 4030 /* Set up interrupt info. */ 4031 exfer->sqtdstart = data; 4032 exfer->sqtdend = dataend; 4033 #ifdef DIAGNOSTIC 4034 if (!exfer->isdone) { 4035 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 4036 } 4037 exfer->isdone = 0; 4038 #endif 4039 4040 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4041 if (xfer->timeout && !sc->sc_bus.use_polling) { 4042 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 4043 ehci_timeout, xfer); 4044 } 4045 ehci_add_intr_list(sc, exfer); 4046 xfer->status = USBD_IN_PROGRESS; 4047 mutex_exit(&sc->sc_lock); 4048 4049 #ifdef EHCI_DEBUG 4050 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4051 // delay(10000); 4052 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4053 ehci_dump_regs(sc); 4054 #if 0 4055 printf("async_head:\n"); 4056 ehci_dump_sqh(sc->sc_async_head); 4057 #endif 4058 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 4059 ehci_dump_sqh(sqh); 4060 ehci_dump_sqtds(data); 4061 #endif 4062 4063 if (sc->sc_bus.use_polling) 4064 ehci_waitintr(sc, xfer); 4065 4066 return (USBD_IN_PROGRESS); 4067 #undef exfer 4068 } 4069 4070 Static void 4071 ehci_device_bulk_abort(usbd_xfer_handle xfer) 4072 { 4073 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4074 4075 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 4076 ehci_abort_xfer(xfer, USBD_CANCELLED); 4077 } 4078 4079 /* 4080 * Close a device bulk pipe. 4081 */ 4082 Static void 4083 ehci_device_bulk_close(usbd_pipe_handle pipe) 4084 { 4085 ehci_softc_t *sc = pipe->device->bus->hci_private; 4086 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 4087 4088 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4089 4090 KASSERT(mutex_owned(&sc->sc_lock)); 4091 4092 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 4093 pipe->endpoint->datatoggle = epipe->nexttoggle; 4094 ehci_close_pipe(pipe, sc->sc_async_head); 4095 } 4096 4097 Static void 4098 ehci_device_bulk_done(usbd_xfer_handle xfer) 4099 { 4100 struct ehci_xfer *ex = EXFER(xfer); 4101 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 4102 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 4103 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 4104 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4105 4106 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4107 4108 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4109 xfer, xfer->actlen, 0, 0); 4110 4111 KASSERT(mutex_owned(&sc->sc_lock)); 4112 4113 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4114 ehci_del_intr_list(sc, ex); /* remove from active list */ 4115 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4116 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 4117 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4118 } 4119 4120 USBHIST_LOG(ehcidebug, "length=%d", xfer->actlen, 0, 0, 0); 4121 } 4122 4123 /************************/ 4124 4125 Static usbd_status 4126 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4127 { 4128 struct ehci_soft_islot *isp; 4129 int islot, lev; 4130 4131 /* Find a poll rate that is large enough. */ 4132 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4133 if (EHCI_ILEV_IVAL(lev) <= ival) 4134 break; 4135 4136 /* Pick an interrupt slot at the right level. */ 4137 /* XXX could do better than picking at random */ 4138 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4139 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4140 4141 sqh->islot = islot; 4142 isp = &sc->sc_islots[islot]; 4143 mutex_enter(&sc->sc_lock); 4144 ehci_add_qh(sc, sqh, isp->sqh); 4145 mutex_exit(&sc->sc_lock); 4146 4147 return (USBD_NORMAL_COMPLETION); 4148 } 4149 4150 Static usbd_status 4151 ehci_device_intr_transfer(usbd_xfer_handle xfer) 4152 { 4153 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 4154 usbd_status err; 4155 4156 /* Insert last in queue. */ 4157 mutex_enter(&sc->sc_lock); 4158 err = usb_insert_transfer(xfer); 4159 mutex_exit(&sc->sc_lock); 4160 if (err) 4161 return (err); 4162 4163 /* 4164 * Pipe isn't running (otherwise err would be USBD_INPROG), 4165 * so start it first. 4166 */ 4167 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 4168 } 4169 4170 Static usbd_status 4171 ehci_device_intr_start(usbd_xfer_handle xfer) 4172 { 4173 #define exfer EXFER(xfer) 4174 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 4175 usbd_device_handle dev = xfer->pipe->device; 4176 ehci_softc_t *sc = dev->bus->hci_private; 4177 ehci_soft_qtd_t *data, *dataend; 4178 ehci_soft_qh_t *sqh; 4179 usbd_status err; 4180 int len, isread, endpt; 4181 4182 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4183 4184 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 4185 xfer, xfer->length, xfer->flags, 0); 4186 4187 if (sc->sc_dying) 4188 return (USBD_IOERROR); 4189 4190 #ifdef DIAGNOSTIC 4191 if (xfer->rqflags & URQ_REQUEST) 4192 panic("ehci_device_intr_start: a request"); 4193 #endif 4194 4195 mutex_enter(&sc->sc_lock); 4196 4197 len = xfer->length; 4198 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 4199 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4200 sqh = epipe->sqh; 4201 4202 epipe->u.intr.length = len; 4203 4204 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 4205 &dataend); 4206 if (err) { 4207 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4208 xfer->status = err; 4209 usb_transfer_complete(xfer); 4210 mutex_exit(&sc->sc_lock); 4211 return (err); 4212 } 4213 4214 #ifdef EHCI_DEBUG 4215 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 4216 ehci_dump_sqh(sqh); 4217 ehci_dump_sqtds(data); 4218 #endif 4219 4220 /* Set up interrupt info. */ 4221 exfer->sqtdstart = data; 4222 exfer->sqtdend = dataend; 4223 #ifdef DIAGNOSTIC 4224 if (!exfer->isdone) { 4225 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 4226 } 4227 exfer->isdone = 0; 4228 #endif 4229 4230 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4231 if (xfer->timeout && !sc->sc_bus.use_polling) { 4232 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 4233 ehci_timeout, xfer); 4234 } 4235 ehci_add_intr_list(sc, exfer); 4236 xfer->status = USBD_IN_PROGRESS; 4237 mutex_exit(&sc->sc_lock); 4238 4239 #ifdef EHCI_DEBUG 4240 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4241 // delay(10000); 4242 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4243 ehci_dump_regs(sc); 4244 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4245 ehci_dump_sqh(sqh); 4246 ehci_dump_sqtds(data); 4247 #endif 4248 4249 if (sc->sc_bus.use_polling) 4250 ehci_waitintr(sc, xfer); 4251 4252 return (USBD_IN_PROGRESS); 4253 #undef exfer 4254 } 4255 4256 Static void 4257 ehci_device_intr_abort(usbd_xfer_handle xfer) 4258 { 4259 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4260 4261 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4262 KASSERT(xfer->pipe->intrxfer == xfer); 4263 4264 /* 4265 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4266 * async doorbell. That's dependent on the async list, wheras 4267 * intr xfers are periodic, should not use this? 4268 */ 4269 ehci_abort_xfer(xfer, USBD_CANCELLED); 4270 } 4271 4272 Static void 4273 ehci_device_intr_close(usbd_pipe_handle pipe) 4274 { 4275 ehci_softc_t *sc = pipe->device->bus->hci_private; 4276 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 4277 struct ehci_soft_islot *isp; 4278 4279 KASSERT(mutex_owned(&sc->sc_lock)); 4280 4281 isp = &sc->sc_islots[epipe->sqh->islot]; 4282 ehci_close_pipe(pipe, isp->sqh); 4283 } 4284 4285 Static void 4286 ehci_device_intr_done(usbd_xfer_handle xfer) 4287 { 4288 #define exfer EXFER(xfer) 4289 struct ehci_xfer *ex = EXFER(xfer); 4290 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 4291 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 4292 ehci_soft_qtd_t *data, *dataend; 4293 ehci_soft_qh_t *sqh; 4294 usbd_status err; 4295 int len, isread, endpt; 4296 4297 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4298 4299 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4300 xfer, xfer->actlen, 0, 0); 4301 4302 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 4303 4304 if (xfer->pipe->repeat) { 4305 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4306 4307 len = epipe->u.intr.length; 4308 xfer->length = len; 4309 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 4310 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4311 usb_syncmem(&xfer->dmabuf, 0, len, 4312 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4313 sqh = epipe->sqh; 4314 4315 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4316 &data, &dataend); 4317 if (err) { 4318 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4319 xfer->status = err; 4320 return; 4321 } 4322 4323 /* Set up interrupt info. */ 4324 exfer->sqtdstart = data; 4325 exfer->sqtdend = dataend; 4326 #ifdef DIAGNOSTIC 4327 if (!exfer->isdone) { 4328 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4329 exfer, 0, 0, 0); 4330 printf("ehci_device_intr_done: not done, ex=%p\n", 4331 exfer); 4332 } 4333 exfer->isdone = 0; 4334 #endif 4335 4336 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4337 if (xfer->timeout && !sc->sc_bus.use_polling) { 4338 callout_reset(&xfer->timeout_handle, 4339 mstohz(xfer->timeout), ehci_timeout, xfer); 4340 } 4341 4342 xfer->status = USBD_IN_PROGRESS; 4343 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4344 ehci_del_intr_list(sc, ex); /* remove from active list */ 4345 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4346 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 4347 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4348 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 4349 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4350 } 4351 #undef exfer 4352 } 4353 4354 /************************/ 4355 4356 Static usbd_status 4357 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4358 { 4359 usbd_status err; 4360 4361 err = usb_insert_transfer(xfer); 4362 if (err && err != USBD_IN_PROGRESS) 4363 return err; 4364 4365 return ehci_device_fs_isoc_start(xfer); 4366 } 4367 4368 Static usbd_status 4369 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4370 { 4371 struct ehci_pipe *epipe; 4372 usbd_device_handle dev; 4373 ehci_softc_t *sc; 4374 struct ehci_xfer *exfer; 4375 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4376 usb_dma_t *dma_buf; 4377 int i, j, k, frames; 4378 int offs, total_length; 4379 int frindex; 4380 u_int huba, dir; 4381 4382 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4383 4384 start = NULL; 4385 prev = NULL; 4386 sitd = NULL; 4387 total_length = 0; 4388 exfer = (struct ehci_xfer *) xfer; 4389 sc = xfer->pipe->device->bus->hci_private; 4390 dev = xfer->pipe->device; 4391 epipe = (struct ehci_pipe *)xfer->pipe; 4392 4393 /* 4394 * To allow continuous transfers, above we start all transfers 4395 * immediately. However, we're still going to get usbd_start_next call 4396 * this when another xfer completes. So, check if this is already 4397 * in progress or not 4398 */ 4399 4400 if (exfer->sitdstart != NULL) 4401 return USBD_IN_PROGRESS; 4402 4403 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4404 xfer, xfer->length, xfer->flags, 0); 4405 4406 if (sc->sc_dying) 4407 return USBD_IOERROR; 4408 4409 /* 4410 * To avoid complication, don't allow a request right now that'll span 4411 * the entire frame table. To within 4 frames, to allow some leeway 4412 * on either side of where the hc currently is. 4413 */ 4414 if (epipe->pipe.endpoint->edesc->bInterval * 4415 xfer->nframes >= sc->sc_flsize - 4) { 4416 printf("ehci: isoc descriptor requested that spans the entire" 4417 "frametable, too many frames\n"); 4418 return USBD_INVAL; 4419 } 4420 4421 #ifdef DIAGNOSTIC 4422 if (xfer->rqflags & URQ_REQUEST) 4423 panic("ehci_device_fs_isoc_start: request\n"); 4424 4425 if (!exfer->isdone) 4426 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4427 exfer->isdone = 0; 4428 #endif 4429 4430 /* 4431 * Step 1: Allocate and initialize sitds. 4432 */ 4433 4434 i = epipe->pipe.endpoint->edesc->bInterval; 4435 if (i > 16 || i == 0) { 4436 /* Spec page 271 says intervals > 16 are invalid */ 4437 USBHIST_LOG(ehcidebug, "bInverval %d invalid\n", 0, 0, 0, 0); 4438 4439 return USBD_INVAL; 4440 } 4441 4442 frames = xfer->nframes; 4443 4444 if (frames == 0) { 4445 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4446 4447 return USBD_INVAL; 4448 } 4449 4450 dma_buf = &xfer->dmabuf; 4451 offs = 0; 4452 4453 for (i = 0; i < frames; i++) { 4454 sitd = ehci_alloc_sitd(sc); 4455 4456 if (prev) 4457 prev->xfer_next = sitd; 4458 else 4459 start = sitd; 4460 4461 #ifdef DIAGNOSTIC 4462 if (xfer->frlengths[i] > 0x3ff) { 4463 printf("ehci: invalid frame length\n"); 4464 xfer->frlengths[i] = 0x3ff; 4465 } 4466 #endif 4467 4468 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4469 EHCI_SITD_SET_LEN(xfer->frlengths[i])); 4470 4471 /* Set page0 index and offset. */ 4472 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4473 4474 total_length += xfer->frlengths[i]; 4475 offs += xfer->frlengths[i]; 4476 4477 sitd->sitd.sitd_buffer[1] = 4478 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4479 4480 huba = dev->myhsport->parent->address; 4481 4482 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4483 // Set hub address to 0 if embedded TT is used. 4484 if (huba == sc->sc_addr) 4485 huba = 0; 4486 } 4487 */ 4488 4489 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4490 dir = UE_GET_DIR(k) ? 1 : 0; 4491 sitd->sitd.sitd_endp = 4492 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4493 EHCI_SITD_SET_DADDR(dev->address) | 4494 EHCI_SITD_SET_PORT(dev->myhsport->portno) | 4495 EHCI_SITD_SET_HUBA(huba) | 4496 EHCI_SITD_SET_DIR(dir)); 4497 4498 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4499 4500 /* XXX */ 4501 u_char sa, sb; 4502 u_int temp, tlen; 4503 sa = 0; 4504 4505 if (dir == 0) { /* OUT */ 4506 temp = 0; 4507 tlen = xfer->frlengths[i]; 4508 if (tlen <= 188) { 4509 temp |= 1; /* T-count = 1, TP = ALL */ 4510 tlen = 1; 4511 } else { 4512 tlen += 187; 4513 tlen /= 188; 4514 temp |= tlen; /* T-count = [1..6] */ 4515 temp |= 8; /* TP = Begin */ 4516 } 4517 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4518 4519 tlen += sa; 4520 4521 if (tlen >= 8) { 4522 sb = 0; 4523 } else { 4524 sb = (1 << tlen); 4525 } 4526 4527 sa = (1 << sa); 4528 sa = (sb - sa) & 0x3F; 4529 sb = 0; 4530 } else { 4531 sb = (-(4 << sa)) & 0xFE; 4532 sa = (1 << sa) & 0x3F; 4533 sa = 0x01; 4534 sb = 0xfc; 4535 } 4536 4537 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4538 EHCI_SITD_SET_CMASK(sb)); 4539 4540 prev = sitd; 4541 } /* End of frame */ 4542 4543 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4544 4545 stop = sitd; 4546 stop->xfer_next = NULL; 4547 exfer->isoc_len = total_length; 4548 4549 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4551 4552 /* 4553 * Part 2: Transfer descriptors have now been set up, now they must 4554 * be scheduled into the periodic frame list. Erk. Not wanting to 4555 * complicate matters, transfer is denied if the transfer spans 4556 * more than the period frame list. 4557 */ 4558 4559 mutex_enter(&sc->sc_lock); 4560 4561 /* Start inserting frames */ 4562 if (epipe->u.isoc.cur_xfers > 0) { 4563 frindex = epipe->u.isoc.next_frame; 4564 } else { 4565 frindex = EOREAD4(sc, EHCI_FRINDEX); 4566 frindex = frindex >> 3; /* Erase microframe index */ 4567 frindex += 2; 4568 } 4569 4570 if (frindex >= sc->sc_flsize) 4571 frindex &= (sc->sc_flsize - 1); 4572 4573 /* Whats the frame interval? */ 4574 i = epipe->pipe.endpoint->edesc->bInterval; 4575 4576 sitd = start; 4577 for (j = 0; j < frames; j++) { 4578 if (sitd == NULL) 4579 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4580 4581 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4582 if (sitd->sitd.sitd_next == 0) 4583 /* FIXME: frindex table gets initialized to NULL 4584 * or EHCI_NULL? */ 4585 sitd->sitd.sitd_next = EHCI_NULL; 4586 4587 usb_syncmem(&sitd->dma, 4588 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4589 sizeof(ehci_sitd_t), 4590 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4591 4592 sc->sc_flist[frindex] = 4593 htole32(EHCI_LINK_SITD | sitd->physaddr); 4594 4595 usb_syncmem(&sc->sc_fldma, 4596 sizeof(ehci_link_t) * frindex, 4597 sizeof(ehci_link_t), 4598 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4599 4600 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4601 sc->sc_softsitds[frindex] = sitd; 4602 if (sitd->u.frame_list.next != NULL) 4603 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4604 sitd->slot = frindex; 4605 sitd->u.frame_list.prev = NULL; 4606 4607 frindex += i; 4608 if (frindex >= sc->sc_flsize) 4609 frindex -= sc->sc_flsize; 4610 4611 sitd = sitd->xfer_next; 4612 } 4613 4614 epipe->u.isoc.cur_xfers++; 4615 epipe->u.isoc.next_frame = frindex; 4616 4617 exfer->sitdstart = start; 4618 exfer->sitdend = stop; 4619 exfer->sqtdstart = NULL; 4620 exfer->sqtdstart = NULL; 4621 4622 ehci_add_intr_list(sc, exfer); 4623 xfer->status = USBD_IN_PROGRESS; 4624 xfer->done = 0; 4625 4626 mutex_exit(&sc->sc_lock); 4627 4628 if (sc->sc_bus.use_polling) { 4629 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4630 ehci_waitintr(sc, xfer); 4631 } 4632 4633 return USBD_IN_PROGRESS; 4634 } 4635 4636 Static void 4637 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4638 { 4639 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4640 4641 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4642 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4643 } 4644 4645 Static void 4646 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4647 { 4648 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4649 4650 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4651 } 4652 4653 Static void 4654 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4655 { 4656 struct ehci_xfer *exfer; 4657 ehci_softc_t *sc; 4658 struct ehci_pipe *epipe; 4659 4660 exfer = EXFER(xfer); 4661 sc = xfer->pipe->device->bus->hci_private; 4662 epipe = (struct ehci_pipe *) xfer->pipe; 4663 4664 KASSERT(mutex_owned(&sc->sc_lock)); 4665 4666 epipe->u.isoc.cur_xfers--; 4667 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4668 ehci_del_intr_list(sc, exfer); 4669 ehci_rem_free_sitd_chain(sc, exfer); 4670 } 4671 4672 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4673 BUS_DMASYNC_POSTREAD); 4674 } 4675 Static usbd_status 4676 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4677 { 4678 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 4679 usbd_status err; 4680 4681 mutex_enter(&sc->sc_lock); 4682 err = usb_insert_transfer(xfer); 4683 mutex_exit(&sc->sc_lock); 4684 if (err && err != USBD_IN_PROGRESS) 4685 return err; 4686 4687 return ehci_device_isoc_start(xfer); 4688 } 4689 4690 Static usbd_status 4691 ehci_device_isoc_start(usbd_xfer_handle xfer) 4692 { 4693 struct ehci_pipe *epipe; 4694 ehci_softc_t *sc; 4695 struct ehci_xfer *exfer; 4696 ehci_soft_itd_t *itd, *prev, *start, *stop; 4697 usb_dma_t *dma_buf; 4698 int i, j, k, frames, uframes, ufrperframe; 4699 int trans_count, offs, total_length; 4700 int frindex; 4701 4702 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4703 4704 start = NULL; 4705 prev = NULL; 4706 itd = NULL; 4707 trans_count = 0; 4708 total_length = 0; 4709 exfer = (struct ehci_xfer *) xfer; 4710 sc = xfer->pipe->device->bus->hci_private; 4711 epipe = (struct ehci_pipe *)xfer->pipe; 4712 4713 /* 4714 * To allow continuous transfers, above we start all transfers 4715 * immediately. However, we're still going to get usbd_start_next call 4716 * this when another xfer completes. So, check if this is already 4717 * in progress or not 4718 */ 4719 4720 if (exfer->itdstart != NULL) 4721 return USBD_IN_PROGRESS; 4722 4723 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4724 xfer, xfer->length, xfer->flags, 0); 4725 4726 if (sc->sc_dying) 4727 return USBD_IOERROR; 4728 4729 /* 4730 * To avoid complication, don't allow a request right now that'll span 4731 * the entire frame table. To within 4 frames, to allow some leeway 4732 * on either side of where the hc currently is. 4733 */ 4734 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 4735 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 4736 USBHIST_LOG(ehcidebug, 4737 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4738 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4739 return USBD_INVAL; 4740 } 4741 4742 #ifdef DIAGNOSTIC 4743 if (xfer->rqflags & URQ_REQUEST) 4744 panic("ehci_device_isoc_start: request\n"); 4745 4746 if (!exfer->isdone) { 4747 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4748 0, 0, 0); 4749 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4750 } 4751 exfer->isdone = 0; 4752 #endif 4753 4754 /* 4755 * Step 1: Allocate and initialize itds, how many do we need? 4756 * One per transfer if interval >= 8 microframes, fewer if we use 4757 * multiple microframes per frame. 4758 */ 4759 4760 i = epipe->pipe.endpoint->edesc->bInterval; 4761 if (i > 16 || i == 0) { 4762 /* Spec page 271 says intervals > 16 are invalid */ 4763 USBHIST_LOG(ehcidebug, "bInvertal %d invalid", i, 0, 0, 0); 4764 return USBD_INVAL; 4765 } 4766 4767 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4768 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4769 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4770 4771 if (frames == 0) { 4772 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4773 return USBD_INVAL; 4774 } 4775 4776 dma_buf = &xfer->dmabuf; 4777 offs = 0; 4778 4779 for (i = 0; i < frames; i++) { 4780 int froffs = offs; 4781 itd = ehci_alloc_itd(sc); 4782 4783 if (prev != NULL) { 4784 prev->itd.itd_next = 4785 htole32(itd->physaddr | EHCI_LINK_ITD); 4786 usb_syncmem(&itd->dma, 4787 itd->offs + offsetof(ehci_itd_t, itd_next), 4788 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4789 4790 prev->xfer_next = itd; 4791 } else { 4792 start = itd; 4793 } 4794 4795 /* 4796 * Step 1.5, initialize uframes 4797 */ 4798 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4799 /* Calculate which page in the list this starts in */ 4800 int addr = DMAADDR(dma_buf, froffs); 4801 addr = EHCI_PAGE_OFFSET(addr); 4802 addr += (offs - froffs); 4803 addr = EHCI_PAGE(addr); 4804 addr /= EHCI_PAGE_SIZE; 4805 4806 /* This gets the initial offset into the first page, 4807 * looks how far further along the current uframe 4808 * offset is. Works out how many pages that is. 4809 */ 4810 4811 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4812 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4813 EHCI_ITD_SET_PG(addr) | 4814 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4815 4816 total_length += xfer->frlengths[trans_count]; 4817 offs += xfer->frlengths[trans_count]; 4818 trans_count++; 4819 4820 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4821 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4822 break; 4823 } 4824 } 4825 4826 /* Step 1.75, set buffer pointers. To simplify matters, all 4827 * pointers are filled out for the next 7 hardware pages in 4828 * the dma block, so no need to worry what pages to cover 4829 * and what to not. 4830 */ 4831 4832 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4833 /* 4834 * Don't try to lookup a page that's past the end 4835 * of buffer 4836 */ 4837 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4838 if (page_offs >= dma_buf->block->size) 4839 break; 4840 4841 unsigned long long page = DMAADDR(dma_buf, page_offs); 4842 page = EHCI_PAGE(page); 4843 itd->itd.itd_bufr[j] = 4844 htole32(EHCI_ITD_SET_BPTR(page)); 4845 itd->itd.itd_bufr_hi[j] = 4846 htole32(page >> 32); 4847 } 4848 4849 /* 4850 * Other special values 4851 */ 4852 4853 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4854 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4855 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4856 4857 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4858 ? 1 : 0; 4859 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4860 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4861 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4862 4863 /* FIXME: handle invalid trans */ 4864 itd->itd.itd_bufr[2] |= 4865 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4866 4867 usb_syncmem(&itd->dma, 4868 itd->offs + offsetof(ehci_itd_t, itd_next), 4869 sizeof(ehci_itd_t), 4870 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4871 4872 prev = itd; 4873 } /* End of frame */ 4874 4875 stop = itd; 4876 stop->xfer_next = NULL; 4877 exfer->isoc_len = total_length; 4878 4879 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4880 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4881 4882 /* 4883 * Part 2: Transfer descriptors have now been set up, now they must 4884 * be scheduled into the period frame list. Erk. Not wanting to 4885 * complicate matters, transfer is denied if the transfer spans 4886 * more than the period frame list. 4887 */ 4888 4889 mutex_enter(&sc->sc_lock); 4890 4891 /* Start inserting frames */ 4892 if (epipe->u.isoc.cur_xfers > 0) { 4893 frindex = epipe->u.isoc.next_frame; 4894 } else { 4895 frindex = EOREAD4(sc, EHCI_FRINDEX); 4896 frindex = frindex >> 3; /* Erase microframe index */ 4897 frindex += 2; 4898 } 4899 4900 if (frindex >= sc->sc_flsize) 4901 frindex &= (sc->sc_flsize - 1); 4902 4903 /* What's the frame interval? */ 4904 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4905 if (i / USB_UFRAMES_PER_FRAME == 0) 4906 i = 1; 4907 else 4908 i /= USB_UFRAMES_PER_FRAME; 4909 4910 itd = start; 4911 for (j = 0; j < frames; j++) { 4912 if (itd == NULL) 4913 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4914 4915 itd->itd.itd_next = sc->sc_flist[frindex]; 4916 if (itd->itd.itd_next == 0) 4917 /* FIXME: frindex table gets initialized to NULL 4918 * or EHCI_NULL? */ 4919 itd->itd.itd_next = EHCI_NULL; 4920 4921 usb_syncmem(&itd->dma, 4922 itd->offs + offsetof(ehci_itd_t, itd_next), 4923 sizeof(itd->itd.itd_next), 4924 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4925 4926 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4927 4928 usb_syncmem(&sc->sc_fldma, 4929 sizeof(ehci_link_t) * frindex, 4930 sizeof(ehci_link_t), 4931 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4932 4933 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4934 sc->sc_softitds[frindex] = itd; 4935 if (itd->u.frame_list.next != NULL) 4936 itd->u.frame_list.next->u.frame_list.prev = itd; 4937 itd->slot = frindex; 4938 itd->u.frame_list.prev = NULL; 4939 4940 frindex += i; 4941 if (frindex >= sc->sc_flsize) 4942 frindex -= sc->sc_flsize; 4943 4944 itd = itd->xfer_next; 4945 } 4946 4947 epipe->u.isoc.cur_xfers++; 4948 epipe->u.isoc.next_frame = frindex; 4949 4950 exfer->itdstart = start; 4951 exfer->itdend = stop; 4952 exfer->sqtdstart = NULL; 4953 exfer->sqtdend = NULL; 4954 4955 ehci_add_intr_list(sc, exfer); 4956 xfer->status = USBD_IN_PROGRESS; 4957 xfer->done = 0; 4958 mutex_exit(&sc->sc_lock); 4959 4960 if (sc->sc_bus.use_polling) { 4961 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4962 ehci_waitintr(sc, xfer); 4963 } 4964 4965 return USBD_IN_PROGRESS; 4966 } 4967 4968 Static void 4969 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4970 { 4971 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4972 4973 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4974 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4975 } 4976 4977 Static void 4978 ehci_device_isoc_close(usbd_pipe_handle pipe) 4979 { 4980 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4981 4982 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4983 } 4984 4985 Static void 4986 ehci_device_isoc_done(usbd_xfer_handle xfer) 4987 { 4988 struct ehci_xfer *exfer; 4989 ehci_softc_t *sc; 4990 struct ehci_pipe *epipe; 4991 4992 exfer = EXFER(xfer); 4993 sc = xfer->pipe->device->bus->hci_private; 4994 epipe = (struct ehci_pipe *) xfer->pipe; 4995 4996 KASSERT(mutex_owned(&sc->sc_lock)); 4997 4998 epipe->u.isoc.cur_xfers--; 4999 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 5000 ehci_del_intr_list(sc, exfer); 5001 ehci_rem_free_itd_chain(sc, exfer); 5002 } 5003 5004 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 5005 BUS_DMASYNC_POSTREAD); 5006 5007 } 5008
Indexes created Wed Oct 01 19:09:53 GMT 2025