ehci.c revision 1.234.2.60
1 /* $NetBSD: ehci.c,v 1.234.2.60 2015/10/24 15:24:13 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.60 2015/10/24 15:24:13 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 /* Control pipe */ 136 struct { 137 usb_dma_t reqdma; 138 } ctrl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Iso pipe */ 144 struct { 145 u_int next_frame; 146 u_int cur_xfers; 147 } isoc; 148 }; 149 }; 150 151 Static usbd_status ehci_open(struct usbd_pipe *); 152 Static void ehci_poll(struct usbd_bus *); 153 Static void ehci_softintr(void *); 154 Static int ehci_intr1(ehci_softc_t *); 155 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 156 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 157 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 158 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 159 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 160 Static void ehci_idone(struct ehci_xfer *); 161 Static void ehci_timeout(void *); 162 Static void ehci_timeout_task(void *); 163 Static void ehci_intrlist_timeout(void *); 164 Static void ehci_doorbell(void *); 165 Static void ehci_pcd(void *); 166 167 Static struct usbd_xfer * 168 ehci_allocx(struct usbd_bus *, unsigned int); 169 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 170 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 171 Static int ehci_roothub_ctrl(struct usbd_bus *, 172 usb_device_request_t *, void *, int); 173 174 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 175 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 176 Static void ehci_root_intr_abort(struct usbd_xfer *); 177 Static void ehci_root_intr_close(struct usbd_pipe *); 178 Static void ehci_root_intr_done(struct usbd_xfer *); 179 180 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 181 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 182 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 183 Static void ehci_device_ctrl_close(struct usbd_pipe *); 184 Static void ehci_device_ctrl_done(struct usbd_xfer *); 185 186 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 187 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 188 Static void ehci_device_bulk_abort(struct usbd_xfer *); 189 Static void ehci_device_bulk_close(struct usbd_pipe *); 190 Static void ehci_device_bulk_done(struct usbd_xfer *); 191 192 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 193 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 194 Static void ehci_device_intr_abort(struct usbd_xfer *); 195 Static void ehci_device_intr_close(struct usbd_pipe *); 196 Static void ehci_device_intr_done(struct usbd_xfer *); 197 198 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 199 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 200 Static void ehci_device_isoc_abort(struct usbd_xfer *); 201 Static void ehci_device_isoc_close(struct usbd_pipe *); 202 Static void ehci_device_isoc_done(struct usbd_xfer *); 203 204 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 205 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 206 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 207 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 208 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 209 210 Static void ehci_device_clear_toggle(struct usbd_pipe *); 211 Static void ehci_noop(struct usbd_pipe *); 212 213 Static void ehci_disown(ehci_softc_t *, int, int); 214 215 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 216 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 217 218 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 219 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 220 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 221 ehci_softc_t *, int, int, struct usbd_xfer *, 222 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 223 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 224 ehci_soft_qtd_t *); 225 226 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 227 Static ehci_soft_sitd_t * 228 ehci_alloc_sitd(ehci_softc_t *); 229 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 230 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 231 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 232 struct ehci_xfer *); 233 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 234 struct ehci_xfer *); 235 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, 236 usbd_status); 237 238 Static usbd_status ehci_device_request(struct usbd_xfer *); 239 240 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 241 int); 242 243 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 244 ehci_soft_qh_t *); 245 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 246 ehci_soft_qh_t *); 247 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 248 Static void ehci_sync_hc(ehci_softc_t *); 249 250 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 251 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 252 253 #ifdef EHCI_DEBUG 254 Static ehci_softc_t *theehci; 255 void ehci_dump(void); 256 #endif 257 258 #ifdef EHCI_DEBUG 259 Static void ehci_dump_regs(ehci_softc_t *); 260 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 261 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 262 Static void ehci_dump_qtd(ehci_qtd_t *); 263 Static void ehci_dump_sqh(ehci_soft_qh_t *); 264 Static void ehci_dump_sitd(struct ehci_soft_itd *); 265 Static void ehci_dump_itd(struct ehci_soft_itd *); 266 Static void ehci_dump_exfer(struct ehci_xfer *); 267 #endif 268 269 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 270 271 #define ehci_add_intr_list(sc, ex) \ 272 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 273 #define ehci_del_intr_list(sc, ex) \ 274 do { \ 275 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 276 (ex)->ex_next.tqe_prev = NULL; \ 277 } while (0) 278 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 279 280 Static const struct usbd_bus_methods ehci_bus_methods = { 281 .ubm_open = ehci_open, 282 .ubm_softint = ehci_softintr, 283 .ubm_dopoll = ehci_poll, 284 .ubm_allocx = ehci_allocx, 285 .ubm_freex = ehci_freex, 286 .ubm_getlock = ehci_get_lock, 287 .ubm_rhctrl = ehci_roothub_ctrl, 288 }; 289 290 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 291 .upm_transfer = ehci_root_intr_transfer, 292 .upm_start = ehci_root_intr_start, 293 .upm_abort = ehci_root_intr_abort, 294 .upm_close = ehci_root_intr_close, 295 .upm_cleartoggle = ehci_noop, 296 .upm_done = ehci_root_intr_done, 297 }; 298 299 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 300 .upm_transfer = ehci_device_ctrl_transfer, 301 .upm_start = ehci_device_ctrl_start, 302 .upm_abort = ehci_device_ctrl_abort, 303 .upm_close = ehci_device_ctrl_close, 304 .upm_cleartoggle = ehci_noop, 305 .upm_done = ehci_device_ctrl_done, 306 }; 307 308 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 309 .upm_transfer = ehci_device_intr_transfer, 310 .upm_start = ehci_device_intr_start, 311 .upm_abort = ehci_device_intr_abort, 312 .upm_close = ehci_device_intr_close, 313 .upm_cleartoggle = ehci_device_clear_toggle, 314 .upm_done = ehci_device_intr_done, 315 }; 316 317 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 318 .upm_transfer = ehci_device_bulk_transfer, 319 .upm_start = ehci_device_bulk_start, 320 .upm_abort = ehci_device_bulk_abort, 321 .upm_close = ehci_device_bulk_close, 322 .upm_cleartoggle = ehci_device_clear_toggle, 323 .upm_done = ehci_device_bulk_done, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 327 .upm_transfer = ehci_device_isoc_transfer, 328 .upm_start = ehci_device_isoc_start, 329 .upm_abort = ehci_device_isoc_abort, 330 .upm_close = ehci_device_isoc_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_device_isoc_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 336 .upm_transfer = ehci_device_fs_isoc_transfer, 337 .upm_start = ehci_device_fs_isoc_start, 338 .upm_abort = ehci_device_fs_isoc_abort, 339 .upm_close = ehci_device_fs_isoc_close, 340 .upm_cleartoggle = ehci_noop, 341 .upm_done = ehci_device_fs_isoc_done, 342 }; 343 344 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 345 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 346 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 347 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 348 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 349 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 350 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 351 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 352 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 353 }; 354 355 int 356 ehci_init(ehci_softc_t *sc) 357 { 358 uint32_t vers, sparams, cparams, hcr; 359 u_int i; 360 usbd_status err; 361 ehci_soft_qh_t *sqh; 362 u_int ncomp; 363 364 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 365 #ifdef EHCI_DEBUG 366 theehci = sc; 367 #endif 368 369 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 370 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 371 cv_init(&sc->sc_softwake_cv, "ehciab"); 372 cv_init(&sc->sc_doorbell, "ehcidi"); 373 374 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 375 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 376 377 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 378 ehci_doorbell, sc); 379 KASSERT(sc->sc_doorbell_si != NULL); 380 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 381 ehci_pcd, sc); 382 KASSERT(sc->sc_pcd_si != NULL); 383 384 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 385 386 vers = EREAD2(sc, EHCI_HCIVERSION); 387 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 388 vers >> 8, vers & 0xff); 389 390 sparams = EREAD4(sc, EHCI_HCSPARAMS); 391 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 392 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 393 ncomp = EHCI_HCS_N_CC(sparams); 394 if (ncomp != sc->sc_ncomp) { 395 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 396 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 397 #if NOHCI == 0 || NUHCI == 0 398 aprint_error("%s: ohci or uhci probably not configured\n", 399 device_xname(sc->sc_dev)); 400 #endif 401 if (ncomp < sc->sc_ncomp) 402 sc->sc_ncomp = ncomp; 403 } 404 if (sc->sc_ncomp > 0) { 405 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 406 aprint_normal("%s: companion controller%s, %d port%s each:", 407 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 408 EHCI_HCS_N_PCC(sparams), 409 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 410 for (i = 0; i < sc->sc_ncomp; i++) 411 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 412 aprint_normal("\n"); 413 } 414 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 415 cparams = EREAD4(sc, EHCI_HCCPARAMS); 416 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 417 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 418 419 if (EHCI_HCC_64BIT(cparams)) { 420 /* MUST clear segment register if 64 bit capable. */ 421 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 422 } 423 424 sc->sc_bus.ub_revision = USBREV_2_0; 425 sc->sc_bus.ub_usedma = true; 426 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 427 428 /* Reset the controller */ 429 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 430 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 431 usb_delay_ms(&sc->sc_bus, 1); 432 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 433 for (i = 0; i < 100; i++) { 434 usb_delay_ms(&sc->sc_bus, 1); 435 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 436 if (!hcr) 437 break; 438 } 439 if (hcr) { 440 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 441 return EIO; 442 } 443 if (sc->sc_vendor_init) 444 sc->sc_vendor_init(sc); 445 446 /* XXX need proper intr scheduling */ 447 sc->sc_rand = 96; 448 449 /* frame list size at default, read back what we got and use that */ 450 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 451 case 0: sc->sc_flsize = 1024; break; 452 case 1: sc->sc_flsize = 512; break; 453 case 2: sc->sc_flsize = 256; break; 454 case 3: return EIO; 455 } 456 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 457 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 458 if (err) 459 return err; 460 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 461 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 462 463 for (i = 0; i < sc->sc_flsize; i++) { 464 sc->sc_flist[i] = EHCI_NULL; 465 } 466 467 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 468 469 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 470 KM_SLEEP); 471 if (sc->sc_softitds == NULL) 472 return ENOMEM; 473 LIST_INIT(&sc->sc_freeitds); 474 LIST_INIT(&sc->sc_freesitds); 475 TAILQ_INIT(&sc->sc_intrhead); 476 477 /* Set up the bus struct. */ 478 sc->sc_bus.ub_methods = &ehci_bus_methods; 479 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 480 481 sc->sc_eintrs = EHCI_NORMAL_INTRS; 482 483 /* 484 * Allocate the interrupt dummy QHs. These are arranged to give poll 485 * intervals that are powers of 2 times 1ms. 486 */ 487 for (i = 0; i < EHCI_INTRQHS; i++) { 488 sqh = ehci_alloc_sqh(sc); 489 if (sqh == NULL) { 490 err = ENOMEM; 491 goto bad1; 492 } 493 sc->sc_islots[i].sqh = sqh; 494 } 495 for (i = 0; i < EHCI_INTRQHS; i++) { 496 sqh = sc->sc_islots[i].sqh; 497 if (i == 0) { 498 /* The last (1ms) QH terminates. */ 499 sqh->qh.qh_link = EHCI_NULL; 500 sqh->next = NULL; 501 } else { 502 /* Otherwise the next QH has half the poll interval */ 503 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 504 sqh->qh.qh_link = htole32(sqh->next->physaddr | 505 EHCI_LINK_QH); 506 } 507 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 508 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 509 sqh->qh.qh_curqtd = EHCI_NULL; 510 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 511 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 512 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 513 sqh->sqtd = NULL; 514 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 515 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 516 } 517 /* Point the frame list at the last level (128ms). */ 518 for (i = 0; i < sc->sc_flsize; i++) { 519 int j; 520 521 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 522 revbits[i & (EHCI_MAX_POLLRATE-1)]; 523 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 524 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 525 i)].sqh->physaddr); 526 } 527 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 528 BUS_DMASYNC_PREWRITE); 529 530 /* Allocate dummy QH that starts the async list. */ 531 sqh = ehci_alloc_sqh(sc); 532 if (sqh == NULL) { 533 err = ENOMEM; 534 goto bad1; 535 } 536 /* Fill the QH */ 537 sqh->qh.qh_endp = 538 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 539 sqh->qh.qh_link = 540 htole32(sqh->physaddr | EHCI_LINK_QH); 541 sqh->qh.qh_curqtd = EHCI_NULL; 542 sqh->next = NULL; 543 /* Fill the overlay qTD */ 544 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 545 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 546 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 547 sqh->sqtd = NULL; 548 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 #ifdef EHCI_DEBUG 551 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 552 ehci_dump_sqh(sqh); 553 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 554 #endif 555 556 /* Point to async list */ 557 sc->sc_async_head = sqh; 558 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 559 560 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 561 562 /* Turn on controller */ 563 EOWRITE4(sc, EHCI_USBCMD, 564 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 565 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 566 EHCI_CMD_ASE | 567 EHCI_CMD_PSE | 568 EHCI_CMD_RS); 569 570 /* Take over port ownership */ 571 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 572 573 for (i = 0; i < 100; i++) { 574 usb_delay_ms(&sc->sc_bus, 1); 575 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 576 if (!hcr) 577 break; 578 } 579 if (hcr) { 580 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 581 return EIO; 582 } 583 584 /* Enable interrupts */ 585 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 586 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 587 588 return 0; 589 590 #if 0 591 bad2: 592 ehci_free_sqh(sc, sc->sc_async_head); 593 #endif 594 bad1: 595 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 596 return err; 597 } 598 599 int 600 ehci_intr(void *v) 601 { 602 ehci_softc_t *sc = v; 603 int ret = 0; 604 605 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 606 607 if (sc == NULL) 608 return 0; 609 610 mutex_spin_enter(&sc->sc_intr_lock); 611 612 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 613 goto done; 614 615 /* If we get an interrupt while polling, then just ignore it. */ 616 if (sc->sc_bus.ub_usepolling) { 617 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 618 619 if (intrs) 620 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 621 USBHIST_LOGN(ehcidebug, 16, 622 "ignored interrupt while polling", 0, 0, 0, 0); 623 goto done; 624 } 625 626 ret = ehci_intr1(sc); 627 628 done: 629 mutex_spin_exit(&sc->sc_intr_lock); 630 return ret; 631 } 632 633 Static int 634 ehci_intr1(ehci_softc_t *sc) 635 { 636 uint32_t intrs, eintrs; 637 638 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 639 640 /* In case the interrupt occurs before initialization has completed. */ 641 if (sc == NULL) { 642 #ifdef DIAGNOSTIC 643 printf("ehci_intr1: sc == NULL\n"); 644 #endif 645 return 0; 646 } 647 648 KASSERT(mutex_owned(&sc->sc_intr_lock)); 649 650 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 651 if (!intrs) 652 return 0; 653 654 eintrs = intrs & sc->sc_eintrs; 655 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 656 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 657 if (!eintrs) 658 return 0; 659 660 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 661 if (eintrs & EHCI_STS_IAA) { 662 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 663 kpreempt_disable(); 664 KASSERT(sc->sc_doorbell_si != NULL); 665 softint_schedule(sc->sc_doorbell_si); 666 kpreempt_enable(); 667 eintrs &= ~EHCI_STS_IAA; 668 } 669 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 670 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 671 eintrs & EHCI_STS_INT ? 1 : 0, 672 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 673 usb_schedsoftintr(&sc->sc_bus); 674 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 675 } 676 if (eintrs & EHCI_STS_HSE) { 677 printf("%s: unrecoverable error, controller halted\n", 678 device_xname(sc->sc_dev)); 679 /* XXX what else */ 680 } 681 if (eintrs & EHCI_STS_PCD) { 682 kpreempt_disable(); 683 KASSERT(sc->sc_pcd_si != NULL); 684 softint_schedule(sc->sc_pcd_si); 685 kpreempt_enable(); 686 eintrs &= ~EHCI_STS_PCD; 687 } 688 689 if (eintrs != 0) { 690 /* Block unprocessed interrupts. */ 691 sc->sc_eintrs &= ~eintrs; 692 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 693 printf("%s: blocking intrs 0x%x\n", 694 device_xname(sc->sc_dev), eintrs); 695 } 696 697 return 1; 698 } 699 700 Static void 701 ehci_doorbell(void *addr) 702 { 703 ehci_softc_t *sc = addr; 704 705 mutex_enter(&sc->sc_lock); 706 cv_broadcast(&sc->sc_doorbell); 707 mutex_exit(&sc->sc_lock); 708 } 709 710 Static void 711 ehci_pcd(void *addr) 712 { 713 ehci_softc_t *sc = addr; 714 struct usbd_xfer *xfer; 715 u_char *p; 716 int i, m; 717 718 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 719 720 mutex_enter(&sc->sc_lock); 721 xfer = sc->sc_intrxfer; 722 723 if (xfer == NULL) { 724 /* Just ignore the change. */ 725 goto done; 726 } 727 728 p = xfer->ux_buf; 729 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 730 memset(p, 0, xfer->ux_length); 731 for (i = 1; i <= m; i++) { 732 /* Pick out CHANGE bits from the status reg. */ 733 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 734 p[i/8] |= 1 << (i%8); 735 if (i % 8 == 7) 736 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 737 p[i/8], 0, 0); 738 } 739 xfer->ux_actlen = xfer->ux_length; 740 xfer->ux_status = USBD_NORMAL_COMPLETION; 741 742 usb_transfer_complete(xfer); 743 744 done: 745 mutex_exit(&sc->sc_lock); 746 } 747 748 Static void 749 ehci_softintr(void *v) 750 { 751 struct usbd_bus *bus = v; 752 ehci_softc_t *sc = EHCI_BUS2SC(bus); 753 struct ehci_xfer *ex, *nextex; 754 755 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 756 757 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 758 759 /* 760 * The only explanation I can think of for why EHCI is as brain dead 761 * as UHCI interrupt-wise is that Intel was involved in both. 762 * An interrupt just tells us that something is done, we have no 763 * clue what, so we need to scan through all active transfers. :-( 764 */ 765 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 766 nextex = TAILQ_NEXT(ex, ex_next); 767 ehci_check_intr(sc, ex); 768 } 769 770 /* Schedule a callout to catch any dropped transactions. */ 771 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 772 !TAILQ_EMPTY(&sc->sc_intrhead)) 773 callout_reset(&sc->sc_tmo_intrlist, 774 hz, ehci_intrlist_timeout, sc); 775 776 if (sc->sc_softwake) { 777 sc->sc_softwake = 0; 778 cv_broadcast(&sc->sc_softwake_cv); 779 } 780 } 781 782 /* Check for an interrupt. */ 783 Static void 784 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 785 { 786 struct usbd_device *dev = ex->ex_xfer.ux_pipe->up_dev; 787 int attr; 788 789 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 790 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 791 792 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 793 794 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 795 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 796 if (dev->ud_speed == USB_SPEED_HIGH) 797 ehci_check_itd_intr(sc, ex); 798 else 799 ehci_check_sitd_intr(sc, ex); 800 } else 801 ehci_check_qh_intr(sc, ex); 802 803 return; 804 } 805 806 Static void 807 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 808 { 809 ehci_soft_qtd_t *sqtd, *lsqtd; 810 uint32_t status; 811 812 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 813 814 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 815 816 if (ex->ex_sqtdstart == NULL) { 817 printf("ehci_check_qh_intr: not valid sqtd\n"); 818 return; 819 } 820 821 lsqtd = ex->ex_sqtdend; 822 #ifdef DIAGNOSTIC 823 if (lsqtd == NULL) { 824 printf("ehci_check_qh_intr: lsqtd==0\n"); 825 return; 826 } 827 #endif 828 /* 829 * If the last TD is still active we need to check whether there 830 * is an error somewhere in the middle, or whether there was a 831 * short packet (SPD and not ACTIVE). 832 */ 833 usb_syncmem(&lsqtd->dma, 834 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 835 sizeof(lsqtd->qtd.qtd_status), 836 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 837 status = le32toh(lsqtd->qtd.qtd_status); 838 usb_syncmem(&lsqtd->dma, 839 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 840 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 841 if (status & EHCI_QTD_ACTIVE) { 842 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 843 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 844 sqtd = sqtd->nextqtd) { 845 usb_syncmem(&sqtd->dma, 846 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 847 sizeof(sqtd->qtd.qtd_status), 848 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 849 status = le32toh(sqtd->qtd.qtd_status); 850 usb_syncmem(&sqtd->dma, 851 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 852 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 853 /* If there's an active QTD the xfer isn't done. */ 854 if (status & EHCI_QTD_ACTIVE) 855 break; 856 /* Any kind of error makes the xfer done. */ 857 if (status & EHCI_QTD_HALTED) 858 goto done; 859 /* Handle short packets */ 860 if (EHCI_QTD_GET_BYTES(status) != 0) { 861 struct usbd_pipe *pipe = ex->ex_xfer.ux_pipe; 862 usb_endpoint_descriptor_t *ed = 863 pipe->up_endpoint->ue_edesc; 864 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 865 866 /* 867 * If we get here for a control transfer then 868 * we need to let the hardware complete the 869 * status phase. That is, we're not done 870 * quite yet. 871 * 872 * Otherwise, we're done. 873 */ 874 if (xt == UE_CONTROL) { 875 break; 876 } 877 goto done; 878 } 879 } 880 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 881 ex, ex->ex_sqtdstart, 0, 0); 882 #ifdef EHCI_DEBUG 883 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 884 0, 0); 885 ehci_dump_sqtds(ex->ex_sqtdstart); 886 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 887 0); 888 #endif 889 return; 890 } 891 done: 892 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 893 callout_stop(&ex->ex_xfer.ux_callout); 894 ehci_idone(ex); 895 } 896 897 Static void 898 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 899 { 900 ehci_soft_itd_t *itd; 901 int i; 902 903 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 904 905 KASSERT(mutex_owned(&sc->sc_lock)); 906 907 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 908 return; 909 910 if (ex->ex_itdstart == NULL) { 911 printf("ehci_check_itd_intr: not valid itd\n"); 912 return; 913 } 914 915 itd = ex->ex_itdend; 916 #ifdef DIAGNOSTIC 917 if (itd == NULL) { 918 printf("ehci_check_itd_intr: itdend == 0\n"); 919 return; 920 } 921 #endif 922 923 /* 924 * check no active transfers in last itd, meaning we're finished 925 */ 926 927 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 928 sizeof(itd->itd.itd_ctl), 929 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 930 931 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 932 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 933 break; 934 } 935 936 if (i == EHCI_ITD_NUFRAMES) { 937 goto done; /* All 8 descriptors inactive, it's done */ 938 } 939 940 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 941 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 942 943 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 944 ex->ex_itdstart, 0, 0); 945 return; 946 done: 947 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 948 callout_stop(&ex->ex_xfer.ux_callout); 949 ehci_idone(ex); 950 } 951 952 void 953 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 954 { 955 ehci_soft_sitd_t *sitd; 956 957 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 958 959 KASSERT(mutex_owned(&sc->sc_lock)); 960 961 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 962 return; 963 964 if (ex->ex_sitdstart == NULL) { 965 printf("ehci_check_sitd_intr: not valid sitd\n"); 966 return; 967 } 968 969 sitd = ex->ex_sitdend; 970 #ifdef DIAGNOSTIC 971 if (sitd == NULL) { 972 printf("ehci_check_sitd_intr: sitdend == 0\n"); 973 return; 974 } 975 #endif 976 977 /* 978 * check no active transfers in last sitd, meaning we're finished 979 */ 980 981 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 982 sizeof(sitd->sitd.sitd_trans), 983 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 984 985 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 986 return; 987 988 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 989 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 990 991 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 992 callout_stop(&(ex->ex_xfer.ux_callout)); 993 ehci_idone(ex); 994 } 995 996 997 Static void 998 ehci_idone(struct ehci_xfer *ex) 999 { 1000 struct usbd_xfer *xfer = &ex->ex_xfer; 1001 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1002 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1003 ehci_soft_qtd_t *sqtd, *lsqtd; 1004 uint32_t status = 0, nstatus = 0; 1005 int actlen; 1006 1007 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1008 1009 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1010 1011 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1012 1013 #ifdef DIAGNOSTIC 1014 #ifdef EHCI_DEBUG 1015 if (ex->ex_isdone) { 1016 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1017 ehci_dump_exfer(ex); 1018 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1019 } 1020 #endif 1021 KASSERT(!ex->ex_isdone); 1022 ex->ex_isdone = true; 1023 #endif 1024 1025 if (xfer->ux_status == USBD_CANCELLED || 1026 xfer->ux_status == USBD_TIMEOUT) { 1027 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1028 return; 1029 } 1030 1031 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1032 1033 /* The transfer is done, compute actual length and status. */ 1034 1035 u_int xfertype, speed; 1036 1037 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1038 speed = xfer->ux_pipe->up_dev->ud_speed; 1039 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1040 /* HS isoc transfer */ 1041 1042 struct ehci_soft_itd *itd; 1043 int i, nframes, len, uframes; 1044 1045 nframes = 0; 1046 actlen = 0; 1047 1048 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1049 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1050 1051 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1052 usb_syncmem(&itd->dma, 1053 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1054 sizeof(itd->itd.itd_ctl), 1055 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1056 1057 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1058 /* 1059 * XXX - driver didn't fill in the frame full 1060 * of uframes. This leads to scheduling 1061 * inefficiencies, but working around 1062 * this doubles complexity of tracking 1063 * an xfer. 1064 */ 1065 if (nframes >= xfer->ux_nframes) 1066 break; 1067 1068 status = le32toh(itd->itd.itd_ctl[i]); 1069 len = EHCI_ITD_GET_LEN(status); 1070 if (EHCI_ITD_GET_STATUS(status) != 0) 1071 len = 0; /*No valid data on error*/ 1072 1073 xfer->ux_frlengths[nframes++] = len; 1074 actlen += len; 1075 } 1076 usb_syncmem(&itd->dma, 1077 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1078 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1079 1080 if (nframes >= xfer->ux_nframes) 1081 break; 1082 } 1083 1084 xfer->ux_actlen = actlen; 1085 xfer->ux_status = USBD_NORMAL_COMPLETION; 1086 goto end; 1087 } 1088 1089 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1090 /* FS isoc transfer */ 1091 struct ehci_soft_sitd *sitd; 1092 int nframes, len; 1093 1094 nframes = 0; 1095 actlen = 0; 1096 1097 for (sitd = ex->ex_sitdstart; sitd != NULL; 1098 sitd = sitd->xfer_next) { 1099 usb_syncmem(&sitd->dma, 1100 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1101 sizeof(sitd->sitd.sitd_trans), 1102 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1103 1104 /* 1105 * XXX - driver didn't fill in the frame full 1106 * of uframes. This leads to scheduling 1107 * inefficiencies, but working around 1108 * this doubles complexity of tracking 1109 * an xfer. 1110 */ 1111 if (nframes >= xfer->ux_nframes) 1112 break; 1113 1114 status = le32toh(sitd->sitd.sitd_trans); 1115 usb_syncmem(&sitd->dma, 1116 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1117 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1118 1119 len = EHCI_SITD_GET_LEN(status); 1120 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1121 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1122 /* No valid data on error */ 1123 len = xfer->ux_frlengths[nframes]; 1124 } 1125 1126 /* 1127 * frlengths[i]: # of bytes to send 1128 * len: # of bytes host didn't send 1129 */ 1130 xfer->ux_frlengths[nframes] -= len; 1131 /* frlengths[i]: # of bytes host sent */ 1132 actlen += xfer->ux_frlengths[nframes++]; 1133 1134 if (nframes >= xfer->ux_nframes) 1135 break; 1136 } 1137 1138 xfer->ux_actlen = actlen; 1139 xfer->ux_status = USBD_NORMAL_COMPLETION; 1140 goto end; 1141 } 1142 KASSERT(xfertype != UE_ISOCHRONOUS); 1143 1144 /* Continue processing xfers using queue heads */ 1145 1146 #ifdef EHCI_DEBUG 1147 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1148 ehci_dump_sqtds(ex->ex_sqtdstart); 1149 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1150 #endif 1151 1152 lsqtd = ex->ex_sqtdend; 1153 actlen = 0; 1154 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1155 sqtd = sqtd->nextqtd) { 1156 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1157 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1158 nstatus = le32toh(sqtd->qtd.qtd_status); 1159 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1160 BUS_DMASYNC_PREREAD); 1161 if (nstatus & EHCI_QTD_ACTIVE) 1162 break; 1163 1164 status = nstatus; 1165 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1166 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1167 } 1168 1169 /* 1170 * If there are left over TDs we need to update the toggle. 1171 * The default pipe doesn't need it since control transfers 1172 * start the toggle at 0 every time. 1173 * For a short transfer we need to update the toggle for the missing 1174 * packets within the qTD. 1175 */ 1176 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1177 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1178 USBHIST_LOG(ehcidebug, 1179 "toggle update status=0x%08x nstatus=0x%08x", 1180 status, nstatus, 0, 0); 1181 #if 0 1182 ehci_dump_sqh(epipe->sqh); 1183 ehci_dump_sqtds(ex->ex_sqtdstart); 1184 #endif 1185 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1186 } 1187 1188 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1189 actlen, status, 0); 1190 xfer->ux_actlen = actlen; 1191 if (status & EHCI_QTD_HALTED) { 1192 #ifdef EHCI_DEBUG 1193 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1194 xfer->ux_pipe->up_dev->ud_addr, 1195 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1196 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1197 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1198 0, 0); 1199 USBHIST_LOG(ehcidebug, 1200 "active =%d halted=%d buferr=%d babble=%d", 1201 status & EHCI_QTD_ACTIVE ? 1 : 0, 1202 status & EHCI_QTD_HALTED ? 1 : 0, 1203 status & EHCI_QTD_BUFERR ? 1 : 0, 1204 status & EHCI_QTD_BABBLE ? 1 : 0); 1205 1206 USBHIST_LOG(ehcidebug, 1207 "xacterr=%d missed=%d split =%d ping =%d", 1208 status & EHCI_QTD_XACTERR ? 1 : 0, 1209 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1210 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1211 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1212 1213 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1214 ehci_dump_sqh(epipe->sqh); 1215 ehci_dump_sqtds(ex->ex_sqtdstart); 1216 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1217 #endif 1218 /* low&full speed has an extra error flag */ 1219 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1220 EHCI_QH_SPEED_HIGH) 1221 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1222 else 1223 status &= EHCI_QTD_STATERRS; 1224 if (status == 0) /* no other errors means a stall */ { 1225 xfer->ux_status = USBD_STALLED; 1226 } else { 1227 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1228 } 1229 /* XXX need to reset TT on missed microframe */ 1230 if (status & EHCI_QTD_MISSEDMICRO) { 1231 printf("%s: missed microframe, TT reset not " 1232 "implemented, hub might be inoperational\n", 1233 device_xname(sc->sc_dev)); 1234 } 1235 } else { 1236 xfer->ux_status = USBD_NORMAL_COMPLETION; 1237 } 1238 1239 end: 1240 /* 1241 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1242 * during this call, before methods->done is called: dma sync required 1243 * beforehand? 1244 */ 1245 usb_transfer_complete(xfer); 1246 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1247 } 1248 1249 /* 1250 * Wait here until controller claims to have an interrupt. 1251 * Then call ehci_intr and return. Use timeout to avoid waiting 1252 * too long. 1253 */ 1254 Static void 1255 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1256 { 1257 int timo; 1258 uint32_t intrs; 1259 1260 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1261 1262 xfer->ux_status = USBD_IN_PROGRESS; 1263 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1264 usb_delay_ms(&sc->sc_bus, 1); 1265 if (sc->sc_dying) 1266 break; 1267 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1268 sc->sc_eintrs; 1269 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1270 #ifdef EHCI_DEBUG 1271 if (ehcidebug > 15) 1272 ehci_dump_regs(sc); 1273 #endif 1274 if (intrs) { 1275 mutex_spin_enter(&sc->sc_intr_lock); 1276 ehci_intr1(sc); 1277 mutex_spin_exit(&sc->sc_intr_lock); 1278 if (xfer->ux_status != USBD_IN_PROGRESS) 1279 return; 1280 } 1281 } 1282 1283 /* Timeout */ 1284 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1285 xfer->ux_status = USBD_TIMEOUT; 1286 mutex_enter(&sc->sc_lock); 1287 usb_transfer_complete(xfer); 1288 mutex_exit(&sc->sc_lock); 1289 /* XXX should free TD */ 1290 } 1291 1292 Static void 1293 ehci_poll(struct usbd_bus *bus) 1294 { 1295 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1296 1297 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1298 1299 #ifdef EHCI_DEBUG 1300 static int last; 1301 int new; 1302 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1303 if (new != last) { 1304 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1305 last = new; 1306 } 1307 #endif 1308 1309 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1310 mutex_spin_enter(&sc->sc_intr_lock); 1311 ehci_intr1(sc); 1312 mutex_spin_exit(&sc->sc_intr_lock); 1313 } 1314 } 1315 1316 void 1317 ehci_childdet(device_t self, device_t child) 1318 { 1319 struct ehci_softc *sc = device_private(self); 1320 1321 KASSERT(sc->sc_child == child); 1322 sc->sc_child = NULL; 1323 } 1324 1325 int 1326 ehci_detach(struct ehci_softc *sc, int flags) 1327 { 1328 int rv = 0; 1329 1330 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1331 1332 if (sc->sc_child != NULL) 1333 rv = config_detach(sc->sc_child, flags); 1334 1335 if (rv != 0) 1336 return rv; 1337 1338 callout_halt(&sc->sc_tmo_intrlist, NULL); 1339 callout_destroy(&sc->sc_tmo_intrlist); 1340 1341 /* XXX free other data structures XXX */ 1342 if (sc->sc_softitds) 1343 kmem_free(sc->sc_softitds, 1344 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1345 cv_destroy(&sc->sc_doorbell); 1346 cv_destroy(&sc->sc_softwake_cv); 1347 1348 #if 0 1349 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1350 1351 softint_disestablish(sc->sc_doorbell_si); 1352 softint_disestablish(sc->sc_pcd_si); 1353 1354 mutex_destroy(&sc->sc_lock); 1355 mutex_destroy(&sc->sc_intr_lock); 1356 #endif 1357 1358 pool_cache_destroy(sc->sc_xferpool); 1359 1360 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1361 1362 return rv; 1363 } 1364 1365 1366 int 1367 ehci_activate(device_t self, enum devact act) 1368 { 1369 struct ehci_softc *sc = device_private(self); 1370 1371 switch (act) { 1372 case DVACT_DEACTIVATE: 1373 sc->sc_dying = 1; 1374 return 0; 1375 default: 1376 return EOPNOTSUPP; 1377 } 1378 } 1379 1380 /* 1381 * Handle suspend/resume. 1382 * 1383 * We need to switch to polling mode here, because this routine is 1384 * called from an interrupt context. This is all right since we 1385 * are almost suspended anyway. 1386 * 1387 * Note that this power handler isn't to be registered directly; the 1388 * bus glue needs to call out to it. 1389 */ 1390 bool 1391 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1392 { 1393 ehci_softc_t *sc = device_private(dv); 1394 int i; 1395 uint32_t cmd, hcr; 1396 1397 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1398 1399 mutex_spin_enter(&sc->sc_intr_lock); 1400 sc->sc_bus.ub_usepolling++; 1401 mutex_spin_exit(&sc->sc_intr_lock); 1402 1403 for (i = 1; i <= sc->sc_noport; i++) { 1404 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1405 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1406 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1407 } 1408 1409 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1410 1411 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1412 EOWRITE4(sc, EHCI_USBCMD, cmd); 1413 1414 for (i = 0; i < 100; i++) { 1415 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1416 if (hcr == 0) 1417 break; 1418 1419 usb_delay_ms(&sc->sc_bus, 1); 1420 } 1421 if (hcr != 0) 1422 printf("%s: reset timeout\n", device_xname(dv)); 1423 1424 cmd &= ~EHCI_CMD_RS; 1425 EOWRITE4(sc, EHCI_USBCMD, cmd); 1426 1427 for (i = 0; i < 100; i++) { 1428 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1429 if (hcr == EHCI_STS_HCH) 1430 break; 1431 1432 usb_delay_ms(&sc->sc_bus, 1); 1433 } 1434 if (hcr != EHCI_STS_HCH) 1435 printf("%s: config timeout\n", device_xname(dv)); 1436 1437 mutex_spin_enter(&sc->sc_intr_lock); 1438 sc->sc_bus.ub_usepolling--; 1439 mutex_spin_exit(&sc->sc_intr_lock); 1440 1441 return true; 1442 } 1443 1444 bool 1445 ehci_resume(device_t dv, const pmf_qual_t *qual) 1446 { 1447 ehci_softc_t *sc = device_private(dv); 1448 int i; 1449 uint32_t cmd, hcr; 1450 1451 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1452 1453 /* restore things in case the bios sucks */ 1454 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1455 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1456 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1457 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1458 1459 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1460 1461 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1462 1463 hcr = 0; 1464 for (i = 1; i <= sc->sc_noport; i++) { 1465 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1466 if ((cmd & EHCI_PS_PO) == 0 && 1467 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1468 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1469 hcr = 1; 1470 } 1471 } 1472 1473 if (hcr) { 1474 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1475 1476 for (i = 1; i <= sc->sc_noport; i++) { 1477 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1478 if ((cmd & EHCI_PS_PO) == 0 && 1479 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1480 EOWRITE4(sc, EHCI_PORTSC(i), 1481 cmd & ~EHCI_PS_FPR); 1482 } 1483 } 1484 1485 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1486 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1487 1488 for (i = 0; i < 100; i++) { 1489 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1490 if (hcr != EHCI_STS_HCH) 1491 break; 1492 1493 usb_delay_ms(&sc->sc_bus, 1); 1494 } 1495 if (hcr == EHCI_STS_HCH) 1496 printf("%s: config timeout\n", device_xname(dv)); 1497 1498 return true; 1499 } 1500 1501 /* 1502 * Shut down the controller when the system is going down. 1503 */ 1504 bool 1505 ehci_shutdown(device_t self, int flags) 1506 { 1507 ehci_softc_t *sc = device_private(self); 1508 1509 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1510 1511 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1512 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1513 return true; 1514 } 1515 1516 Static struct usbd_xfer * 1517 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1518 { 1519 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1520 struct usbd_xfer *xfer; 1521 1522 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1523 if (xfer != NULL) { 1524 memset(xfer, 0, sizeof(struct ehci_xfer)); 1525 #ifdef DIAGNOSTIC 1526 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1527 ex->ex_isdone = true; 1528 xfer->ux_state = XFER_BUSY; 1529 #endif 1530 } 1531 return xfer; 1532 } 1533 1534 Static void 1535 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1536 { 1537 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1538 1539 KASSERT(xfer->ux_state == XFER_BUSY); 1540 KASSERT(EHCI_XFER2EXFER(xfer)->ex_isdone); 1541 #ifdef DIAGNOSTIC 1542 xfer->ux_state = XFER_FREE; 1543 #endif 1544 pool_cache_put(sc->sc_xferpool, xfer); 1545 } 1546 1547 Static void 1548 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1549 { 1550 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1551 1552 *lock = &sc->sc_lock; 1553 } 1554 1555 Static void 1556 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1557 { 1558 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1559 1560 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1561 1562 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1563 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1564 #ifdef EHCI_DEBUG 1565 if (ehcidebug) 1566 usbd_dump_pipe(pipe); 1567 #endif 1568 epipe->nexttoggle = 0; 1569 } 1570 1571 Static void 1572 ehci_noop(struct usbd_pipe *pipe) 1573 { 1574 } 1575 1576 #ifdef EHCI_DEBUG 1577 /* 1578 * Unused function - this is meant to be called from a kernel 1579 * debugger. 1580 */ 1581 void 1582 ehci_dump(void) 1583 { 1584 ehci_softc_t *sc = theehci; 1585 int i; 1586 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1587 EOREAD4(sc, EHCI_USBCMD), 1588 EOREAD4(sc, EHCI_USBSTS), 1589 EOREAD4(sc, EHCI_USBINTR)); 1590 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1591 EOREAD4(sc, EHCI_FRINDEX), 1592 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1593 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1594 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1595 for (i = 1; i <= sc->sc_noport; i++) 1596 printf("port %d status=0x%08x\n", i, 1597 EOREAD4(sc, EHCI_PORTSC(i))); 1598 } 1599 1600 Static void 1601 ehci_dump_regs(ehci_softc_t *sc) 1602 { 1603 int i; 1604 1605 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1606 1607 USBHIST_LOG(ehcidebug, 1608 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1609 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1610 EOREAD4(sc, EHCI_USBINTR), 0); 1611 USBHIST_LOG(ehcidebug, 1612 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1613 "async = 0x%08x", 1614 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1615 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1616 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1617 for (i = 1; i <= sc->sc_noport; i += 2) { 1618 if (i == sc->sc_noport) { 1619 USBHIST_LOG(ehcidebug, 1620 "port %d status = 0x%08x", i, 1621 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1622 } else { 1623 USBHIST_LOG(ehcidebug, 1624 "port %d status = 0x%08x port %d status = 0x%08x", 1625 i, EOREAD4(sc, EHCI_PORTSC(i)), 1626 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1627 } 1628 } 1629 } 1630 1631 #ifdef EHCI_DEBUG 1632 #define ehci_dump_link(link, type) do { \ 1633 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1634 link, \ 1635 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1636 if (type) { \ 1637 USBHIST_LOG(ehcidebug, \ 1638 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1639 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1640 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1641 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1642 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1643 } \ 1644 } while(0) 1645 #else 1646 #define ehci_dump_link(link, type) 1647 #endif 1648 1649 Static void 1650 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1651 { 1652 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1653 int i; 1654 uint32_t stop = 0; 1655 1656 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1657 ehci_dump_sqtd(sqtd); 1658 usb_syncmem(&sqtd->dma, 1659 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1660 sizeof(sqtd->qtd), 1661 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1662 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1663 usb_syncmem(&sqtd->dma, 1664 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1665 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1666 } 1667 if (!stop) 1668 USBHIST_LOG(ehcidebug, 1669 "dump aborted, too many TDs", 0, 0, 0, 0); 1670 } 1671 1672 Static void 1673 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1674 { 1675 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1676 1677 usb_syncmem(&sqtd->dma, sqtd->offs, 1678 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1679 1680 USBHIST_LOGN(ehcidebug, 10, 1681 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1682 ehci_dump_qtd(&sqtd->qtd); 1683 1684 usb_syncmem(&sqtd->dma, sqtd->offs, 1685 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1686 } 1687 1688 Static void 1689 ehci_dump_qtd(ehci_qtd_t *qtd) 1690 { 1691 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1692 1693 #ifdef USBHIST 1694 uint32_t s = le32toh(qtd->qtd_status); 1695 #endif 1696 1697 USBHIST_LOGN(ehcidebug, 10, 1698 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1699 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1700 USBHIST_LOGN(ehcidebug, 10, 1701 " toggle = %d ioc = %d bytes = %#x " 1702 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1703 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1704 USBHIST_LOGN(ehcidebug, 10, 1705 " cerr = %d pid = %d stat = %x", 1706 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1707 0); 1708 USBHIST_LOGN(ehcidebug, 10, 1709 "active =%d halted=%d buferr=%d babble=%d", 1710 s & EHCI_QTD_ACTIVE ? 1 : 0, 1711 s & EHCI_QTD_HALTED ? 1 : 0, 1712 s & EHCI_QTD_BUFERR ? 1 : 0, 1713 s & EHCI_QTD_BABBLE ? 1 : 0); 1714 USBHIST_LOGN(ehcidebug, 10, 1715 "xacterr=%d missed=%d split =%d ping =%d", 1716 s & EHCI_QTD_XACTERR ? 1 : 0, 1717 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1718 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1719 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1720 USBHIST_LOGN(ehcidebug, 10, 1721 "buffer[0] = %#x buffer[1] = %#x " 1722 "buffer[2] = %#x buffer[3] = %#x", 1723 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1724 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1725 USBHIST_LOGN(ehcidebug, 10, 1726 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1727 } 1728 1729 Static void 1730 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1731 { 1732 #ifdef USBHIST 1733 ehci_qh_t *qh = &sqh->qh; 1734 ehci_link_t link; 1735 #endif 1736 uint32_t endp, endphub; 1737 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1738 1739 usb_syncmem(&sqh->dma, sqh->offs, 1740 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1741 1742 USBHIST_LOGN(ehcidebug, 10, 1743 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1744 link = le32toh(qh->qh_link); 1745 ehci_dump_link(link, true); 1746 1747 endp = le32toh(qh->qh_endp); 1748 USBHIST_LOGN(ehcidebug, 10, 1749 " endp = %#x", endp, 0, 0, 0); 1750 USBHIST_LOGN(ehcidebug, 10, 1751 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1752 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1753 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1754 USBHIST_LOGN(ehcidebug, 10, 1755 " dtc = %d hrecl = %d", 1756 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1757 USBHIST_LOGN(ehcidebug, 10, 1758 " ctl = %d nrl = %d mpl = %#x(%d)", 1759 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1760 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1761 1762 endphub = le32toh(qh->qh_endphub); 1763 USBHIST_LOGN(ehcidebug, 10, 1764 " endphub = %#x", endphub, 0, 0, 0); 1765 USBHIST_LOGN(ehcidebug, 10, 1766 " smask = 0x%02x cmask = 0x%02x", 1767 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1768 USBHIST_LOGN(ehcidebug, 10, 1769 " huba = 0x%02x port = %d mult = %d", 1770 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1771 EHCI_QH_GET_MULT(endphub), 0); 1772 1773 link = le32toh(qh->qh_curqtd); 1774 ehci_dump_link(link, false); 1775 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1776 ehci_dump_qtd(&qh->qh_qtd); 1777 1778 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1779 BUS_DMASYNC_PREREAD); 1780 } 1781 1782 Static void 1783 ehci_dump_itd(struct ehci_soft_itd *itd) 1784 { 1785 ehci_isoc_trans_t t; 1786 ehci_isoc_bufr_ptr_t b, b2, b3; 1787 int i; 1788 1789 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1790 1791 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1792 0, 0); 1793 1794 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1795 t = le32toh(itd->itd.itd_ctl[i]); 1796 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1797 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1798 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1799 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1800 EHCI_ITD_GET_OFFS(t), 0); 1801 } 1802 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1803 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1804 USBHIST_LOG(ehcidebug, " %x", 1805 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1806 1807 b = le32toh(itd->itd.itd_bufr[0]); 1808 b2 = le32toh(itd->itd.itd_bufr[1]); 1809 b3 = le32toh(itd->itd.itd_bufr[2]); 1810 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1811 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1812 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1813 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1814 } 1815 1816 Static void 1817 ehci_dump_sitd(struct ehci_soft_itd *itd) 1818 { 1819 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1820 1821 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1822 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1823 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1824 itd->xfer_next, itd->physaddr, itd->slot, 0); 1825 } 1826 1827 Static void 1828 ehci_dump_exfer(struct ehci_xfer *ex) 1829 { 1830 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1831 1832 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1833 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1834 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1835 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1836 } 1837 #endif 1838 1839 Static usbd_status 1840 ehci_open(struct usbd_pipe *pipe) 1841 { 1842 struct usbd_device *dev = pipe->up_dev; 1843 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1844 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1845 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1846 uint8_t addr = dev->ud_addr; 1847 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1848 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1849 ehci_soft_qh_t *sqh; 1850 usbd_status err; 1851 int ival, speed, naks; 1852 int hshubaddr, hshubport; 1853 1854 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1855 1856 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1857 pipe, addr, ed->bEndpointAddress, rhaddr); 1858 1859 if (dev->ud_myhsport) { 1860 /* 1861 * When directly attached FS/LS device while doing embedded 1862 * transaction translations and we are the hub, set the hub 1863 * address to 0 (us). 1864 */ 1865 if (!(sc->sc_flags & EHCIF_ETTF) 1866 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1867 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1868 } else { 1869 hshubaddr = 0; 1870 } 1871 hshubport = dev->ud_myhsport->up_portno; 1872 } else { 1873 hshubaddr = 0; 1874 hshubport = 0; 1875 } 1876 1877 if (sc->sc_dying) 1878 return USBD_IOERROR; 1879 1880 /* toggle state needed for bulk endpoints */ 1881 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1882 1883 if (addr == rhaddr) { 1884 switch (ed->bEndpointAddress) { 1885 case USB_CONTROL_ENDPOINT: 1886 pipe->up_methods = &roothub_ctrl_methods; 1887 break; 1888 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1889 pipe->up_methods = &ehci_root_intr_methods; 1890 break; 1891 default: 1892 USBHIST_LOG(ehcidebug, 1893 "bad bEndpointAddress 0x%02x", 1894 ed->bEndpointAddress, 0, 0, 0); 1895 return USBD_INVAL; 1896 } 1897 return USBD_NORMAL_COMPLETION; 1898 } 1899 1900 /* XXX All this stuff is only valid for async. */ 1901 switch (dev->ud_speed) { 1902 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1903 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1904 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1905 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1906 } 1907 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1908 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1909 hshubaddr, hshubport, 0, 0); 1910 return USBD_INVAL; 1911 } 1912 1913 /* 1914 * For interrupt transfer, nak throttling must be disabled, but for 1915 * the other transfer type, nak throttling should be enabled from the 1916 * viewpoint that avoids the memory thrashing. 1917 */ 1918 naks = (xfertype == UE_INTERRUPT) ? 0 1919 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1920 1921 /* Allocate sqh for everything, save isoc xfers */ 1922 if (xfertype != UE_ISOCHRONOUS) { 1923 sqh = ehci_alloc_sqh(sc); 1924 if (sqh == NULL) 1925 return USBD_NOMEM; 1926 /* qh_link filled when the QH is added */ 1927 sqh->qh.qh_endp = htole32( 1928 EHCI_QH_SET_ADDR(addr) | 1929 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1930 EHCI_QH_SET_EPS(speed) | 1931 EHCI_QH_DTC | 1932 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1933 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1934 EHCI_QH_CTL : 0) | 1935 EHCI_QH_SET_NRL(naks) 1936 ); 1937 sqh->qh.qh_endphub = htole32( 1938 EHCI_QH_SET_MULT(1) | 1939 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1940 ); 1941 if (speed != EHCI_QH_SPEED_HIGH) 1942 sqh->qh.qh_endphub |= htole32( 1943 EHCI_QH_SET_PORT(hshubport) | 1944 EHCI_QH_SET_HUBA(hshubaddr) | 1945 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1946 ); 1947 sqh->qh.qh_curqtd = EHCI_NULL; 1948 /* Fill the overlay qTD */ 1949 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1950 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1951 sqh->qh.qh_qtd.qtd_status = htole32(0); 1952 1953 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1954 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1955 epipe->sqh = sqh; 1956 } else { 1957 sqh = NULL; 1958 } /*xfertype == UE_ISOC*/ 1959 1960 switch (xfertype) { 1961 case UE_CONTROL: 1962 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1963 0, &epipe->ctrl.reqdma); 1964 #ifdef EHCI_DEBUG 1965 if (err) 1966 printf("ehci_open: usb_allocmem()=%d\n", err); 1967 #endif 1968 if (err) 1969 goto bad; 1970 pipe->up_methods = &ehci_device_ctrl_methods; 1971 mutex_enter(&sc->sc_lock); 1972 ehci_add_qh(sc, sqh, sc->sc_async_head); 1973 mutex_exit(&sc->sc_lock); 1974 break; 1975 case UE_BULK: 1976 pipe->up_methods = &ehci_device_bulk_methods; 1977 mutex_enter(&sc->sc_lock); 1978 ehci_add_qh(sc, sqh, sc->sc_async_head); 1979 mutex_exit(&sc->sc_lock); 1980 break; 1981 case UE_INTERRUPT: 1982 pipe->up_methods = &ehci_device_intr_methods; 1983 ival = pipe->up_interval; 1984 if (ival == USBD_DEFAULT_INTERVAL) { 1985 if (speed == EHCI_QH_SPEED_HIGH) { 1986 if (ed->bInterval > 16) { 1987 /* 1988 * illegal with high-speed, but there 1989 * were documentation bugs in the spec, 1990 * so be generous 1991 */ 1992 ival = 256; 1993 } else 1994 ival = (1 << (ed->bInterval - 1)) / 8; 1995 } else 1996 ival = ed->bInterval; 1997 } 1998 err = ehci_device_setintr(sc, sqh, ival); 1999 if (err) 2000 goto bad; 2001 break; 2002 case UE_ISOCHRONOUS: 2003 if (speed == EHCI_QH_SPEED_HIGH) 2004 pipe->up_methods = &ehci_device_isoc_methods; 2005 else 2006 pipe->up_methods = &ehci_device_fs_isoc_methods; 2007 if (ed->bInterval == 0 || ed->bInterval > 16) { 2008 printf("ehci: opening pipe with invalid bInterval\n"); 2009 err = USBD_INVAL; 2010 goto bad; 2011 } 2012 if (UGETW(ed->wMaxPacketSize) == 0) { 2013 printf("ehci: zero length endpoint open request\n"); 2014 err = USBD_INVAL; 2015 goto bad; 2016 } 2017 epipe->isoc.next_frame = 0; 2018 epipe->isoc.cur_xfers = 0; 2019 break; 2020 default: 2021 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2022 err = USBD_INVAL; 2023 goto bad; 2024 } 2025 return USBD_NORMAL_COMPLETION; 2026 2027 bad: 2028 if (sqh != NULL) 2029 ehci_free_sqh(sc, sqh); 2030 return err; 2031 } 2032 2033 /* 2034 * Add an ED to the schedule. Called with USB lock held. 2035 */ 2036 Static void 2037 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2038 { 2039 2040 KASSERT(mutex_owned(&sc->sc_lock)); 2041 2042 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2043 2044 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2045 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2046 2047 sqh->next = head->next; 2048 sqh->qh.qh_link = head->qh.qh_link; 2049 2050 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2051 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2052 2053 head->next = sqh; 2054 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2055 2056 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2057 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2058 2059 #ifdef EHCI_DEBUG 2060 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2061 ehci_dump_sqh(sqh); 2062 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2063 #endif 2064 } 2065 2066 /* 2067 * Remove an ED from the schedule. Called with USB lock held. 2068 */ 2069 Static void 2070 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2071 { 2072 ehci_soft_qh_t *p; 2073 2074 KASSERT(mutex_owned(&sc->sc_lock)); 2075 2076 /* XXX */ 2077 for (p = head; p != NULL && p->next != sqh; p = p->next) 2078 ; 2079 if (p == NULL) 2080 panic("ehci_rem_qh: ED not found"); 2081 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2082 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2083 p->next = sqh->next; 2084 p->qh.qh_link = sqh->qh.qh_link; 2085 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2086 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2087 2088 ehci_sync_hc(sc); 2089 } 2090 2091 Static void 2092 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2093 { 2094 int i; 2095 uint32_t status; 2096 2097 /* Save toggle bit and ping status. */ 2098 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2099 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2100 status = sqh->qh.qh_qtd.qtd_status & 2101 htole32(EHCI_QTD_TOGGLE_MASK | 2102 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2103 /* Set HALTED to make hw leave it alone. */ 2104 sqh->qh.qh_qtd.qtd_status = 2105 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2106 usb_syncmem(&sqh->dma, 2107 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2108 sizeof(sqh->qh.qh_qtd.qtd_status), 2109 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2110 sqh->qh.qh_curqtd = 0; 2111 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2112 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2113 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2114 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2115 sqh->sqtd = sqtd; 2116 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2117 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2118 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2119 sqh->qh.qh_qtd.qtd_status = status; 2120 usb_syncmem(&sqh->dma, 2121 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2122 sizeof(sqh->qh.qh_qtd.qtd_status), 2123 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2124 } 2125 2126 /* 2127 * Ensure that the HC has released all references to the QH. We do this 2128 * by asking for a Async Advance Doorbell interrupt and then we wait for 2129 * the interrupt. 2130 * To make this easier we first obtain exclusive use of the doorbell. 2131 */ 2132 Static void 2133 ehci_sync_hc(ehci_softc_t *sc) 2134 { 2135 int error __diagused; 2136 2137 KASSERT(mutex_owned(&sc->sc_lock)); 2138 2139 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2140 2141 if (sc->sc_dying) { 2142 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2143 return; 2144 } 2145 /* ask for doorbell */ 2146 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2147 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2148 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2149 2150 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2151 2152 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2153 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2154 #ifdef DIAGNOSTIC 2155 if (error) 2156 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2157 #endif 2158 } 2159 2160 Static void 2161 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2162 { 2163 struct ehci_soft_itd *itd, *prev; 2164 2165 prev = NULL; 2166 2167 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2168 panic("ehci isoc xfer being freed, but with no itd chain"); 2169 2170 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2171 prev = itd->frame_list.prev; 2172 /* Unlink itd from hardware chain, or frame array */ 2173 if (prev == NULL) { /* We're at the table head */ 2174 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2175 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2176 usb_syncmem(&sc->sc_fldma, 2177 sizeof(ehci_link_t) * itd->slot, 2178 sizeof(ehci_link_t), 2179 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2180 2181 if (itd->frame_list.next != NULL) 2182 itd->frame_list.next->frame_list.prev = NULL; 2183 } else { 2184 /* XXX this part is untested... */ 2185 prev->itd.itd_next = itd->itd.itd_next; 2186 usb_syncmem(&itd->dma, 2187 itd->offs + offsetof(ehci_itd_t, itd_next), 2188 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2189 2190 prev->frame_list.next = itd->frame_list.next; 2191 if (itd->frame_list.next != NULL) 2192 itd->frame_list.next->frame_list.prev = prev; 2193 } 2194 } 2195 2196 prev = NULL; 2197 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2198 if (prev != NULL) 2199 ehci_free_itd(sc, prev); 2200 prev = itd; 2201 } 2202 if (prev) 2203 ehci_free_itd(sc, prev); 2204 exfer->ex_itdstart = NULL; 2205 exfer->ex_itdend = NULL; 2206 } 2207 2208 Static void 2209 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2210 { 2211 struct ehci_soft_sitd *sitd, *prev; 2212 2213 prev = NULL; 2214 2215 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2216 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2217 2218 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2219 prev = sitd->frame_list.prev; 2220 /* Unlink sitd from hardware chain, or frame array */ 2221 if (prev == NULL) { /* We're at the table head */ 2222 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2223 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2224 usb_syncmem(&sc->sc_fldma, 2225 sizeof(ehci_link_t) * sitd->slot, 2226 sizeof(ehci_link_t), 2227 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2228 2229 if (sitd->frame_list.next != NULL) 2230 sitd->frame_list.next->frame_list.prev = NULL; 2231 } else { 2232 /* XXX this part is untested... */ 2233 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2234 usb_syncmem(&sitd->dma, 2235 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2236 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2237 2238 prev->frame_list.next = sitd->frame_list.next; 2239 if (sitd->frame_list.next != NULL) 2240 sitd->frame_list.next->frame_list.prev = prev; 2241 } 2242 } 2243 2244 prev = NULL; 2245 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2246 if (prev != NULL) 2247 ehci_free_sitd(sc, prev); 2248 prev = sitd; 2249 } 2250 if (prev) 2251 ehci_free_sitd(sc, prev); 2252 exfer->ex_sitdstart = NULL; 2253 exfer->ex_sitdend = NULL; 2254 } 2255 2256 /***********/ 2257 2258 Static int 2259 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2260 void *buf, int buflen) 2261 { 2262 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2263 usb_hub_descriptor_t hubd; 2264 usb_port_status_t ps; 2265 uint16_t len, value, index; 2266 int l, totlen = 0; 2267 int port, i; 2268 uint32_t v; 2269 2270 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2271 2272 if (sc->sc_dying) 2273 return -1; 2274 2275 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2276 req->bmRequestType, req->bRequest, 0, 0); 2277 2278 len = UGETW(req->wLength); 2279 value = UGETW(req->wValue); 2280 index = UGETW(req->wIndex); 2281 2282 #define C(x,y) ((x) | ((y) << 8)) 2283 switch (C(req->bRequest, req->bmRequestType)) { 2284 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2285 if (len == 0) 2286 break; 2287 switch (value) { 2288 case C(0, UDESC_DEVICE): { 2289 usb_device_descriptor_t devd; 2290 totlen = min(buflen, sizeof(devd)); 2291 memcpy(&devd, buf, totlen); 2292 USETW(devd.idVendor, sc->sc_id_vendor); 2293 memcpy(buf, &devd, totlen); 2294 break; 2295 2296 } 2297 #define sd ((usb_string_descriptor_t *)buf) 2298 case C(1, UDESC_STRING): 2299 /* Vendor */ 2300 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2301 break; 2302 case C(2, UDESC_STRING): 2303 /* Product */ 2304 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2305 break; 2306 #undef sd 2307 default: 2308 /* default from usbroothub */ 2309 return buflen; 2310 } 2311 break; 2312 2313 /* Hub requests */ 2314 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2315 break; 2316 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2317 USBHIST_LOG(ehcidebug, 2318 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2319 0, 0); 2320 if (index < 1 || index > sc->sc_noport) { 2321 return -1; 2322 } 2323 port = EHCI_PORTSC(index); 2324 v = EOREAD4(sc, port); 2325 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2326 v &= ~EHCI_PS_CLEAR; 2327 switch (value) { 2328 case UHF_PORT_ENABLE: 2329 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2330 break; 2331 case UHF_PORT_SUSPEND: 2332 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2333 break; 2334 v &= ~EHCI_PS_SUSP; 2335 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2336 /* see USB2 spec ch. 7.1.7.7 */ 2337 usb_delay_ms(&sc->sc_bus, 20); 2338 EOWRITE4(sc, port, v); 2339 usb_delay_ms(&sc->sc_bus, 2); 2340 #ifdef DEBUG 2341 v = EOREAD4(sc, port); 2342 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2343 printf("ehci: resume failed: %x\n", v); 2344 #endif 2345 break; 2346 case UHF_PORT_POWER: 2347 if (sc->sc_hasppc) 2348 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2349 break; 2350 case UHF_PORT_TEST: 2351 USBHIST_LOG(ehcidebug, "clear port test " 2352 "%d", index, 0, 0, 0); 2353 break; 2354 case UHF_PORT_INDICATOR: 2355 USBHIST_LOG(ehcidebug, "clear port ind " 2356 "%d", index, 0, 0, 0); 2357 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2358 break; 2359 case UHF_C_PORT_CONNECTION: 2360 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2361 break; 2362 case UHF_C_PORT_ENABLE: 2363 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2364 break; 2365 case UHF_C_PORT_SUSPEND: 2366 /* how? */ 2367 break; 2368 case UHF_C_PORT_OVER_CURRENT: 2369 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2370 break; 2371 case UHF_C_PORT_RESET: 2372 sc->sc_isreset[index] = 0; 2373 break; 2374 default: 2375 return -1; 2376 } 2377 #if 0 2378 switch(value) { 2379 case UHF_C_PORT_CONNECTION: 2380 case UHF_C_PORT_ENABLE: 2381 case UHF_C_PORT_SUSPEND: 2382 case UHF_C_PORT_OVER_CURRENT: 2383 case UHF_C_PORT_RESET: 2384 default: 2385 break; 2386 } 2387 #endif 2388 break; 2389 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2390 if (len == 0) 2391 break; 2392 if ((value & 0xff) != 0) { 2393 return -1; 2394 } 2395 totlen = min(buflen, sizeof(hubd)); 2396 memcpy(&hubd, buf, totlen); 2397 hubd.bNbrPorts = sc->sc_noport; 2398 v = EOREAD4(sc, EHCI_HCSPARAMS); 2399 USETW(hubd.wHubCharacteristics, 2400 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2401 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2402 ? UHD_PORT_IND : 0); 2403 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2404 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2405 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2406 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2407 totlen = min(totlen, hubd.bDescLength); 2408 memcpy(buf, &hubd, totlen); 2409 break; 2410 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2411 if (len != 4) { 2412 return -1; 2413 } 2414 memset(buf, 0, len); /* ? XXX */ 2415 totlen = len; 2416 break; 2417 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2418 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2419 if (index < 1 || index > sc->sc_noport) { 2420 return -1; 2421 } 2422 if (len != 4) { 2423 return -1; 2424 } 2425 v = EOREAD4(sc, EHCI_PORTSC(index)); 2426 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2427 2428 i = UPS_HIGH_SPEED; 2429 if (sc->sc_flags & EHCIF_ETTF) { 2430 /* 2431 * If we are doing embedded transaction translation, 2432 * then directly attached LS/FS devices are reset by 2433 * the EHCI controller itself. PSPD is encoded 2434 * the same way as in USBSTATUS. 2435 */ 2436 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2437 } 2438 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2439 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2440 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2441 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2442 if (v & EHCI_PS_PR) i |= UPS_RESET; 2443 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2444 if (sc->sc_vendor_port_status) 2445 i = sc->sc_vendor_port_status(sc, v, i); 2446 USETW(ps.wPortStatus, i); 2447 i = 0; 2448 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2449 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2450 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2451 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2452 USETW(ps.wPortChange, i); 2453 totlen = min(len, sizeof(ps)); 2454 memcpy(buf, &ps, totlen); 2455 break; 2456 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2457 return -1; 2458 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2459 break; 2460 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2461 if (index < 1 || index > sc->sc_noport) { 2462 return -1; 2463 } 2464 port = EHCI_PORTSC(index); 2465 v = EOREAD4(sc, port); 2466 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2467 v &= ~EHCI_PS_CLEAR; 2468 switch(value) { 2469 case UHF_PORT_ENABLE: 2470 EOWRITE4(sc, port, v | EHCI_PS_PE); 2471 break; 2472 case UHF_PORT_SUSPEND: 2473 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2474 break; 2475 case UHF_PORT_RESET: 2476 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2477 if (EHCI_PS_IS_LOWSPEED(v) 2478 && sc->sc_ncomp > 0 2479 && !(sc->sc_flags & EHCIF_ETTF)) { 2480 /* 2481 * Low speed device on non-ETTF controller or 2482 * unaccompanied controller, give up ownership. 2483 */ 2484 ehci_disown(sc, index, 1); 2485 break; 2486 } 2487 /* Start reset sequence. */ 2488 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2489 EOWRITE4(sc, port, v | EHCI_PS_PR); 2490 /* Wait for reset to complete. */ 2491 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2492 if (sc->sc_dying) { 2493 return -1; 2494 } 2495 /* 2496 * An embedded transaction translator will automatically 2497 * terminate the reset sequence so there's no need to 2498 * it. 2499 */ 2500 v = EOREAD4(sc, port); 2501 if (v & EHCI_PS_PR) { 2502 /* Terminate reset sequence. */ 2503 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2504 /* Wait for HC to complete reset. */ 2505 usb_delay_ms(&sc->sc_bus, 2506 EHCI_PORT_RESET_COMPLETE); 2507 if (sc->sc_dying) { 2508 return -1; 2509 } 2510 } 2511 2512 v = EOREAD4(sc, port); 2513 USBHIST_LOG(ehcidebug, 2514 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2515 if (v & EHCI_PS_PR) { 2516 printf("%s: port reset timeout\n", 2517 device_xname(sc->sc_dev)); 2518 return USBD_TIMEOUT; 2519 } 2520 if (!(v & EHCI_PS_PE)) { 2521 /* Not a high speed device, give up ownership.*/ 2522 ehci_disown(sc, index, 0); 2523 break; 2524 } 2525 sc->sc_isreset[index] = 1; 2526 USBHIST_LOG(ehcidebug, 2527 "ehci port %d reset, status = 0x%08x", index, v, 0, 2528 0); 2529 break; 2530 case UHF_PORT_POWER: 2531 USBHIST_LOG(ehcidebug, 2532 "set port power %d (has PPC = %d)", index, 2533 sc->sc_hasppc, 0, 0); 2534 if (sc->sc_hasppc) 2535 EOWRITE4(sc, port, v | EHCI_PS_PP); 2536 break; 2537 case UHF_PORT_TEST: 2538 USBHIST_LOG(ehcidebug, "set port test %d", 2539 index, 0, 0, 0); 2540 break; 2541 case UHF_PORT_INDICATOR: 2542 USBHIST_LOG(ehcidebug, "set port ind %d", 2543 index, 0, 0, 0); 2544 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2545 break; 2546 default: 2547 return -1; 2548 } 2549 break; 2550 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2551 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2552 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2553 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2554 break; 2555 default: 2556 /* default from usbroothub */ 2557 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2558 buflen, 0, 0, 0); 2559 2560 return buflen; 2561 } 2562 2563 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2564 2565 return totlen; 2566 } 2567 2568 Static void 2569 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2570 { 2571 int port; 2572 uint32_t v; 2573 2574 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2575 2576 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2577 #ifdef DIAGNOSTIC 2578 if (sc->sc_npcomp != 0) { 2579 int i = (index-1) / sc->sc_npcomp; 2580 if (i >= sc->sc_ncomp) 2581 printf("%s: strange port\n", 2582 device_xname(sc->sc_dev)); 2583 else 2584 printf("%s: handing over %s speed device on " 2585 "port %d to %s\n", 2586 device_xname(sc->sc_dev), 2587 lowspeed ? "low" : "full", 2588 index, device_xname(sc->sc_comps[i])); 2589 } else { 2590 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2591 } 2592 #endif 2593 port = EHCI_PORTSC(index); 2594 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2595 EOWRITE4(sc, port, v | EHCI_PS_PO); 2596 } 2597 2598 Static usbd_status 2599 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2600 { 2601 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2602 usbd_status err; 2603 2604 /* Insert last in queue. */ 2605 mutex_enter(&sc->sc_lock); 2606 err = usb_insert_transfer(xfer); 2607 mutex_exit(&sc->sc_lock); 2608 if (err) 2609 return err; 2610 2611 /* Pipe isn't running, start first */ 2612 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2613 } 2614 2615 Static usbd_status 2616 ehci_root_intr_start(struct usbd_xfer *xfer) 2617 { 2618 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2619 2620 if (sc->sc_dying) 2621 return USBD_IOERROR; 2622 2623 mutex_enter(&sc->sc_lock); 2624 sc->sc_intrxfer = xfer; 2625 mutex_exit(&sc->sc_lock); 2626 2627 return USBD_IN_PROGRESS; 2628 } 2629 2630 /* Abort a root interrupt request. */ 2631 Static void 2632 ehci_root_intr_abort(struct usbd_xfer *xfer) 2633 { 2634 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2635 2636 KASSERT(mutex_owned(&sc->sc_lock)); 2637 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2638 2639 sc->sc_intrxfer = NULL; 2640 2641 xfer->ux_status = USBD_CANCELLED; 2642 usb_transfer_complete(xfer); 2643 } 2644 2645 /* Close the root pipe. */ 2646 Static void 2647 ehci_root_intr_close(struct usbd_pipe *pipe) 2648 { 2649 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2650 2651 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2652 2653 KASSERT(mutex_owned(&sc->sc_lock)); 2654 2655 sc->sc_intrxfer = NULL; 2656 } 2657 2658 Static void 2659 ehci_root_intr_done(struct usbd_xfer *xfer) 2660 { 2661 xfer->ux_hcpriv = NULL; 2662 } 2663 2664 /************************/ 2665 2666 Static ehci_soft_qh_t * 2667 ehci_alloc_sqh(ehci_softc_t *sc) 2668 { 2669 ehci_soft_qh_t *sqh; 2670 usbd_status err; 2671 int i, offs; 2672 usb_dma_t dma; 2673 2674 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2675 2676 if (sc->sc_freeqhs == NULL) { 2677 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2678 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2679 EHCI_PAGE_SIZE, &dma); 2680 #ifdef EHCI_DEBUG 2681 if (err) 2682 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2683 #endif 2684 if (err) 2685 return NULL; 2686 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2687 offs = i * EHCI_SQH_SIZE; 2688 sqh = KERNADDR(&dma, offs); 2689 sqh->physaddr = DMAADDR(&dma, offs); 2690 sqh->dma = dma; 2691 sqh->offs = offs; 2692 sqh->next = sc->sc_freeqhs; 2693 sc->sc_freeqhs = sqh; 2694 } 2695 } 2696 sqh = sc->sc_freeqhs; 2697 sc->sc_freeqhs = sqh->next; 2698 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2699 sqh->next = NULL; 2700 return sqh; 2701 } 2702 2703 Static void 2704 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2705 { 2706 sqh->next = sc->sc_freeqhs; 2707 sc->sc_freeqhs = sqh; 2708 } 2709 2710 Static ehci_soft_qtd_t * 2711 ehci_alloc_sqtd(ehci_softc_t *sc) 2712 { 2713 ehci_soft_qtd_t *sqtd = NULL; 2714 usbd_status err; 2715 int i, offs; 2716 usb_dma_t dma; 2717 2718 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2719 2720 if (sc->sc_freeqtds == NULL) { 2721 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2722 2723 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2724 EHCI_PAGE_SIZE, &dma); 2725 #ifdef EHCI_DEBUG 2726 if (err) 2727 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2728 #endif 2729 if (err) 2730 goto done; 2731 2732 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2733 offs = i * EHCI_SQTD_SIZE; 2734 sqtd = KERNADDR(&dma, offs); 2735 sqtd->physaddr = DMAADDR(&dma, offs); 2736 sqtd->dma = dma; 2737 sqtd->offs = offs; 2738 2739 sqtd->nextqtd = sc->sc_freeqtds; 2740 sc->sc_freeqtds = sqtd; 2741 } 2742 } 2743 2744 sqtd = sc->sc_freeqtds; 2745 sc->sc_freeqtds = sqtd->nextqtd; 2746 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2747 sqtd->nextqtd = NULL; 2748 sqtd->xfer = NULL; 2749 2750 done: 2751 return sqtd; 2752 } 2753 2754 Static void 2755 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2756 { 2757 2758 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2759 2760 sqtd->nextqtd = sc->sc_freeqtds; 2761 sc->sc_freeqtds = sqtd; 2762 } 2763 2764 Static usbd_status 2765 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2766 int alen, int rd, struct usbd_xfer *xfer, 2767 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2768 { 2769 ehci_soft_qtd_t *next, *cur; 2770 ehci_physaddr_t nextphys; 2771 uint32_t qtdstatus; 2772 int len, curlen, mps; 2773 int i, tog; 2774 int pages, pageoffs; 2775 size_t curoffs; 2776 vaddr_t va, va_offs; 2777 usb_dma_t *dma = &xfer->ux_dmabuf; 2778 uint16_t flags = xfer->ux_flags; 2779 paddr_t a; 2780 2781 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2782 2783 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2784 2785 len = alen; 2786 qtdstatus = EHCI_QTD_ACTIVE | 2787 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2788 EHCI_QTD_SET_CERR(3) 2789 /* IOC set below */ 2790 /* BYTES set below */ 2791 ; 2792 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2793 tog = epipe->nexttoggle; 2794 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2795 2796 cur = ehci_alloc_sqtd(sc); 2797 *sp = cur; 2798 if (cur == NULL) 2799 goto nomem; 2800 2801 usb_syncmem(dma, 0, alen, 2802 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2803 curoffs = 0; 2804 for (;;) { 2805 /* The EHCI hardware can handle at most 5 pages. */ 2806 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2807 va_offs = EHCI_PAGE_OFFSET(va_offs); 2808 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2809 /* we can handle it in this QTD */ 2810 curlen = len - curoffs; 2811 } else { 2812 /* must use multiple TDs, fill as much as possible. */ 2813 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2814 2815 /* the length must be a multiple of the max size */ 2816 curlen -= curlen % mps; 2817 USBHIST_LOG(ehcidebug, "multiple QTDs, curlen=%d", 2818 curlen, 0, 0, 0); 2819 KASSERT(curlen != 0); 2820 } 2821 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", len, 2822 curlen, curoffs, 0); 2823 2824 /* 2825 * Allocate another transfer if there's more data left, 2826 * or if force last short transfer flag is set and we're 2827 * allocating a multiple of the max packet size. 2828 */ 2829 2830 if (curoffs + curlen != len || 2831 ((curlen % mps) == 0 && !rd && curlen != 0 && 2832 (flags & USBD_FORCE_SHORT_XFER))) { 2833 next = ehci_alloc_sqtd(sc); 2834 if (next == NULL) 2835 goto nomem; 2836 nextphys = htole32(next->physaddr); 2837 } else { 2838 next = NULL; 2839 nextphys = EHCI_NULL; 2840 } 2841 2842 /* Find number of pages we'll be using, insert dma addresses */ 2843 pages = EHCI_NPAGES(curlen); 2844 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2845 pageoffs = EHCI_PAGE(curoffs); 2846 for (i = 0; i < pages; i++) { 2847 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2848 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2849 /* Cast up to avoid compiler warnings */ 2850 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2851 } 2852 2853 /* First buffer pointer requires a page offset to start at */ 2854 va = (vaddr_t)KERNADDR(dma, curoffs); 2855 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2856 2857 cur->nextqtd = next; 2858 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2859 cur->qtd.qtd_status = 2860 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2861 cur->xfer = xfer; 2862 cur->len = curlen; 2863 2864 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2865 curoffs, curoffs + curlen, 0, 0); 2866 2867 /* 2868 * adjust the toggle based on the number of packets in this 2869 * qtd 2870 */ 2871 if (((curlen + mps - 1) / mps) & 1) { 2872 tog ^= 1; 2873 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2874 } 2875 if (next == NULL) 2876 break; 2877 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2878 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2879 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2880 if (len) 2881 curoffs += curlen; 2882 cur = next; 2883 } 2884 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2885 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2886 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2887 *ep = cur; 2888 epipe->nexttoggle = tog; 2889 2890 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", *sp, *ep, 0, 0); 2891 2892 return USBD_NORMAL_COMPLETION; 2893 2894 nomem: 2895 /* XXX free chain */ 2896 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2897 return USBD_NOMEM; 2898 } 2899 2900 Static void 2901 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2902 ehci_soft_qtd_t *sqtdend) 2903 { 2904 ehci_soft_qtd_t *p; 2905 int i; 2906 2907 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2908 2909 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", sqtd, sqtdend, 0, 0); 2910 2911 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2912 p = sqtd->nextqtd; 2913 ehci_free_sqtd(sc, sqtd); 2914 } 2915 } 2916 2917 Static ehci_soft_itd_t * 2918 ehci_alloc_itd(ehci_softc_t *sc) 2919 { 2920 struct ehci_soft_itd *itd, *freeitd; 2921 usbd_status err; 2922 int i, offs, frindex, previndex; 2923 usb_dma_t dma; 2924 2925 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2926 2927 mutex_enter(&sc->sc_lock); 2928 2929 /* 2930 * Find an itd that wasn't freed this frame or last frame. This can 2931 * discard itds that were freed before frindex wrapped around 2932 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2933 * interrupt and fiddling with list when that happens 2934 */ 2935 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2936 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2937 2938 freeitd = NULL; 2939 LIST_FOREACH(itd, &sc->sc_freeitds, free_list) { 2940 if (itd == NULL) 2941 break; 2942 if (itd->slot != frindex && itd->slot != previndex) { 2943 freeitd = itd; 2944 break; 2945 } 2946 } 2947 2948 if (freeitd == NULL) { 2949 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2950 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2951 EHCI_PAGE_SIZE, &dma); 2952 2953 if (err) { 2954 USBHIST_LOG(ehcidebug, 2955 "alloc returned %d", err, 0, 0, 0); 2956 mutex_exit(&sc->sc_lock); 2957 return NULL; 2958 } 2959 2960 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2961 offs = i * EHCI_ITD_SIZE; 2962 itd = KERNADDR(&dma, offs); 2963 itd->physaddr = DMAADDR(&dma, offs); 2964 itd->dma = dma; 2965 itd->offs = offs; 2966 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 2967 } 2968 freeitd = LIST_FIRST(&sc->sc_freeitds); 2969 } 2970 2971 itd = freeitd; 2972 LIST_REMOVE(itd, free_list); 2973 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2974 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2975 sizeof(itd->itd.itd_next), 2976 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2977 2978 itd->frame_list.next = NULL; 2979 itd->frame_list.prev = NULL; 2980 itd->xfer_next = NULL; 2981 itd->slot = 0; 2982 2983 mutex_exit(&sc->sc_lock); 2984 2985 return itd; 2986 } 2987 2988 Static ehci_soft_sitd_t * 2989 ehci_alloc_sitd(ehci_softc_t *sc) 2990 { 2991 struct ehci_soft_sitd *sitd, *freesitd; 2992 usbd_status err; 2993 int i, offs, frindex, previndex; 2994 usb_dma_t dma; 2995 2996 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2997 2998 mutex_enter(&sc->sc_lock); 2999 3000 /* 3001 * Find an sitd that wasn't freed this frame or last frame. This can 3002 * discard sitds that were freed before frindex wrapped around 3003 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3004 * interrupt and fiddling with list when that happens 3005 */ 3006 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3007 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3008 3009 freesitd = NULL; 3010 LIST_FOREACH(sitd, &sc->sc_freesitds, free_list) { 3011 if (sitd == NULL) 3012 break; 3013 if (sitd->slot != frindex && sitd->slot != previndex) { 3014 freesitd = sitd; 3015 break; 3016 } 3017 } 3018 3019 if (freesitd == NULL) { 3020 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3021 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3022 EHCI_PAGE_SIZE, &dma); 3023 3024 if (err) { 3025 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 3026 0); 3027 mutex_exit(&sc->sc_lock); 3028 return NULL; 3029 } 3030 3031 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3032 offs = i * EHCI_SITD_SIZE; 3033 sitd = KERNADDR(&dma, offs); 3034 sitd->physaddr = DMAADDR(&dma, offs); 3035 sitd->dma = dma; 3036 sitd->offs = offs; 3037 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3038 } 3039 freesitd = LIST_FIRST(&sc->sc_freesitds); 3040 } 3041 3042 sitd = freesitd; 3043 LIST_REMOVE(sitd, free_list); 3044 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3045 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3046 sizeof(sitd->sitd.sitd_next), 3047 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3048 3049 sitd->frame_list.next = NULL; 3050 sitd->frame_list.prev = NULL; 3051 sitd->xfer_next = NULL; 3052 sitd->slot = 0; 3053 3054 mutex_exit(&sc->sc_lock); 3055 3056 return sitd; 3057 } 3058 3059 Static void 3060 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3061 { 3062 3063 KASSERT(mutex_owned(&sc->sc_lock)); 3064 3065 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3066 } 3067 3068 Static void 3069 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3070 { 3071 3072 KASSERT(mutex_owned(&sc->sc_lock)); 3073 3074 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3075 } 3076 3077 /****************/ 3078 3079 /* 3080 * Close a reqular pipe. 3081 * Assumes that there are no pending transactions. 3082 */ 3083 Static void 3084 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3085 { 3086 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3087 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3088 ehci_soft_qh_t *sqh = epipe->sqh; 3089 3090 KASSERT(mutex_owned(&sc->sc_lock)); 3091 3092 ehci_rem_qh(sc, sqh, head); 3093 ehci_free_sqh(sc, epipe->sqh); 3094 } 3095 3096 /* 3097 * Abort a device request. 3098 * If this routine is called at splusb() it guarantees that the request 3099 * will be removed from the hardware scheduling and that the callback 3100 * for it will be called with USBD_CANCELLED status. 3101 * It's impossible to guarantee that the requested transfer will not 3102 * have happened since the hardware runs concurrently. 3103 * If the transaction has already happened we rely on the ordinary 3104 * interrupt processing to process it. 3105 * XXX This is most probably wrong. 3106 * XXXMRG this doesn't make sense anymore. 3107 */ 3108 Static void 3109 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3110 { 3111 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3112 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3113 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3114 ehci_soft_qh_t *sqh = epipe->sqh; 3115 ehci_soft_qtd_t *sqtd; 3116 ehci_physaddr_t cur; 3117 uint32_t qhstatus; 3118 int hit; 3119 int wake; 3120 3121 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3122 3123 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3124 3125 KASSERT(mutex_owned(&sc->sc_lock)); 3126 ASSERT_SLEEPABLE(); 3127 3128 if (sc->sc_dying) { 3129 /* If we're dying, just do the software part. */ 3130 xfer->ux_status = status; /* make software ignore it */ 3131 callout_stop(&xfer->ux_callout); 3132 usb_transfer_complete(xfer); 3133 return; 3134 } 3135 3136 /* 3137 * If an abort is already in progress then just wait for it to 3138 * complete and return. 3139 */ 3140 if (xfer->ux_hcflags & UXFER_ABORTING) { 3141 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3142 #ifdef DIAGNOSTIC 3143 if (status == USBD_TIMEOUT) 3144 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3145 #endif 3146 /* Override the status which might be USBD_TIMEOUT. */ 3147 xfer->ux_status = status; 3148 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3149 0, 0, 0, 0); 3150 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3151 while (xfer->ux_hcflags & UXFER_ABORTING) 3152 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3153 return; 3154 } 3155 xfer->ux_hcflags |= UXFER_ABORTING; 3156 3157 /* 3158 * Step 1: Make interrupt routine and hardware ignore xfer. 3159 */ 3160 xfer->ux_status = status; /* make software ignore it */ 3161 callout_stop(&xfer->ux_callout); 3162 3163 usb_syncmem(&sqh->dma, 3164 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3165 sizeof(sqh->qh.qh_qtd.qtd_status), 3166 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3167 qhstatus = sqh->qh.qh_qtd.qtd_status; 3168 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3169 usb_syncmem(&sqh->dma, 3170 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3171 sizeof(sqh->qh.qh_qtd.qtd_status), 3172 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3173 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3174 usb_syncmem(&sqtd->dma, 3175 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3176 sizeof(sqtd->qtd.qtd_status), 3177 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3178 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3179 usb_syncmem(&sqtd->dma, 3180 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3181 sizeof(sqtd->qtd.qtd_status), 3182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3183 if (sqtd == exfer->ex_sqtdend) 3184 break; 3185 } 3186 3187 /* 3188 * Step 2: Wait until we know hardware has finished any possible 3189 * use of the xfer. Also make sure the soft interrupt routine 3190 * has run. 3191 */ 3192 ehci_sync_hc(sc); 3193 sc->sc_softwake = 1; 3194 usb_schedsoftintr(&sc->sc_bus); 3195 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3196 3197 /* 3198 * Step 3: Remove any vestiges of the xfer from the hardware. 3199 * The complication here is that the hardware may have executed 3200 * beyond the xfer we're trying to abort. So as we're scanning 3201 * the TDs of this xfer we check if the hardware points to 3202 * any of them. 3203 */ 3204 3205 usb_syncmem(&sqh->dma, 3206 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3207 sizeof(sqh->qh.qh_curqtd), 3208 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3209 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3210 hit = 0; 3211 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3212 hit |= cur == sqtd->physaddr; 3213 if (sqtd == exfer->ex_sqtdend) 3214 break; 3215 } 3216 sqtd = sqtd->nextqtd; 3217 /* Zap curqtd register if hardware pointed inside the xfer. */ 3218 if (hit && sqtd != NULL) { 3219 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3220 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3221 usb_syncmem(&sqh->dma, 3222 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3223 sizeof(sqh->qh.qh_curqtd), 3224 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3225 sqh->qh.qh_qtd.qtd_status = qhstatus; 3226 usb_syncmem(&sqh->dma, 3227 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3228 sizeof(sqh->qh.qh_qtd.qtd_status), 3229 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3230 } else { 3231 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3232 usb_syncmem(&sqh->dma, 3233 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3234 sizeof(sqh->qh.qh_curqtd), 3235 BUS_DMASYNC_PREREAD); 3236 } 3237 3238 /* 3239 * Step 4: Execute callback. 3240 */ 3241 #ifdef DIAGNOSTIC 3242 exfer->ex_isdone = true; 3243 #endif 3244 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3245 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3246 usb_transfer_complete(xfer); 3247 if (wake) { 3248 cv_broadcast(&xfer->ux_hccv); 3249 } 3250 3251 KASSERT(mutex_owned(&sc->sc_lock)); 3252 } 3253 3254 Static void 3255 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3256 { 3257 ehci_isoc_trans_t trans_status; 3258 struct ehci_xfer *exfer; 3259 ehci_softc_t *sc; 3260 struct ehci_soft_itd *itd; 3261 struct ehci_soft_sitd *sitd; 3262 int i, wake; 3263 3264 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3265 3266 exfer = EHCI_XFER2EXFER(xfer); 3267 sc = EHCI_XFER2SC(xfer); 3268 3269 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3270 3271 KASSERT(mutex_owned(&sc->sc_lock)); 3272 3273 if (sc->sc_dying) { 3274 xfer->ux_status = status; 3275 callout_stop(&xfer->ux_callout); 3276 usb_transfer_complete(xfer); 3277 return; 3278 } 3279 3280 if (xfer->ux_hcflags & UXFER_ABORTING) { 3281 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3282 3283 #ifdef DIAGNOSTIC 3284 if (status == USBD_TIMEOUT) 3285 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3286 #endif 3287 3288 xfer->ux_status = status; 3289 USBHIST_LOG(ehcidebug, 3290 "waiting for abort to finish", 0, 0, 0, 0); 3291 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3292 while (xfer->ux_hcflags & UXFER_ABORTING) 3293 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3294 goto done; 3295 } 3296 xfer->ux_hcflags |= UXFER_ABORTING; 3297 3298 xfer->ux_status = status; 3299 callout_stop(&xfer->ux_callout); 3300 3301 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3302 for (itd = exfer->ex_itdstart; itd != NULL; 3303 itd = itd->xfer_next) { 3304 usb_syncmem(&itd->dma, 3305 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3306 sizeof(itd->itd.itd_ctl), 3307 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3308 3309 for (i = 0; i < 8; i++) { 3310 trans_status = le32toh(itd->itd.itd_ctl[i]); 3311 trans_status &= ~EHCI_ITD_ACTIVE; 3312 itd->itd.itd_ctl[i] = htole32(trans_status); 3313 } 3314 3315 usb_syncmem(&itd->dma, 3316 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3317 sizeof(itd->itd.itd_ctl), 3318 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3319 } 3320 } else { 3321 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3322 sitd = sitd->xfer_next) { 3323 usb_syncmem(&sitd->dma, 3324 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3325 sizeof(sitd->sitd.sitd_buffer), 3326 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3327 3328 trans_status = le32toh(sitd->sitd.sitd_trans); 3329 trans_status &= ~EHCI_SITD_ACTIVE; 3330 sitd->sitd.sitd_trans = htole32(trans_status); 3331 3332 usb_syncmem(&sitd->dma, 3333 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3334 sizeof(sitd->sitd.sitd_buffer), 3335 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3336 } 3337 } 3338 3339 sc->sc_softwake = 1; 3340 usb_schedsoftintr(&sc->sc_bus); 3341 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3342 3343 #ifdef DIAGNOSTIC 3344 exfer->ex_isdone = true; 3345 #endif 3346 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3347 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3348 usb_transfer_complete(xfer); 3349 if (wake) { 3350 cv_broadcast(&xfer->ux_hccv); 3351 } 3352 3353 done: 3354 KASSERT(mutex_owned(&sc->sc_lock)); 3355 return; 3356 } 3357 3358 Static void 3359 ehci_timeout(void *addr) 3360 { 3361 struct usbd_xfer *xfer = addr; 3362 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3363 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3364 3365 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3366 3367 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3368 #ifdef EHCI_DEBUG 3369 if (ehcidebug > 1) 3370 usbd_dump_pipe(xfer->ux_pipe); 3371 #endif 3372 3373 if (sc->sc_dying) { 3374 mutex_enter(&sc->sc_lock); 3375 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3376 mutex_exit(&sc->sc_lock); 3377 return; 3378 } 3379 3380 /* Execute the abort in a process context. */ 3381 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3382 USB_TASKQ_MPSAFE); 3383 usb_add_task(xfer->ux_pipe->up_dev, &exfer->ex_aborttask, 3384 USB_TASKQ_HC); 3385 } 3386 3387 Static void 3388 ehci_timeout_task(void *addr) 3389 { 3390 struct usbd_xfer *xfer = addr; 3391 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3392 3393 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3394 3395 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3396 3397 mutex_enter(&sc->sc_lock); 3398 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3399 mutex_exit(&sc->sc_lock); 3400 } 3401 3402 /************************/ 3403 3404 Static usbd_status 3405 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3406 { 3407 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3408 usbd_status err; 3409 3410 /* Insert last in queue. */ 3411 mutex_enter(&sc->sc_lock); 3412 err = usb_insert_transfer(xfer); 3413 mutex_exit(&sc->sc_lock); 3414 if (err) 3415 return err; 3416 3417 /* Pipe isn't running, start first */ 3418 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3419 } 3420 3421 Static usbd_status 3422 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3423 { 3424 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3425 usbd_status err; 3426 3427 if (sc->sc_dying) 3428 return USBD_IOERROR; 3429 3430 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3431 3432 err = ehci_device_request(xfer); 3433 if (err) { 3434 return err; 3435 } 3436 3437 if (sc->sc_bus.ub_usepolling) 3438 ehci_waitintr(sc, xfer); 3439 3440 return USBD_IN_PROGRESS; 3441 } 3442 3443 Static void 3444 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3445 { 3446 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3447 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3448 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3449 usb_device_request_t *req = &xfer->ux_request; 3450 int len = UGETW(req->wLength); 3451 int rd = req->bmRequestType & UT_READ; 3452 3453 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3454 3455 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3456 3457 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3458 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3459 3460 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3461 ehci_del_intr_list(sc, ex); /* remove from active list */ 3462 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3463 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3464 BUS_DMASYNC_POSTWRITE); 3465 if (len) 3466 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3467 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3468 } 3469 3470 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3471 } 3472 3473 /* Abort a device control request. */ 3474 Static void 3475 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3476 { 3477 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3478 3479 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3480 ehci_abort_xfer(xfer, USBD_CANCELLED); 3481 } 3482 3483 /* Close a device control pipe. */ 3484 Static void 3485 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3486 { 3487 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3488 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3489 3490 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3491 3492 KASSERT(mutex_owned(&sc->sc_lock)); 3493 3494 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3495 3496 ehci_close_pipe(pipe, sc->sc_async_head); 3497 } 3498 3499 Static usbd_status 3500 ehci_device_request(struct usbd_xfer *xfer) 3501 { 3502 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3503 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3504 usb_device_request_t *req = &xfer->ux_request; 3505 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3506 struct usbd_device *dev __diagused = epipe->pipe.up_dev; 3507 ehci_soft_qtd_t *setup, *stat, *next; 3508 ehci_soft_qh_t *sqh; 3509 int isread; 3510 int len; 3511 usbd_status err; 3512 3513 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3514 3515 isread = req->bmRequestType & UT_READ; 3516 len = UGETW(req->wLength); 3517 3518 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3519 "wValue=0x%04x, wIndex=0x%04x", 3520 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3521 UGETW(req->wIndex)); 3522 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3523 len, dev->ud_addr, 3524 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3525 3526 setup = ehci_alloc_sqtd(sc); 3527 if (setup == NULL) { 3528 err = USBD_NOMEM; 3529 goto bad1; 3530 } 3531 stat = ehci_alloc_sqtd(sc); 3532 if (stat == NULL) { 3533 err = USBD_NOMEM; 3534 goto bad2; 3535 } 3536 3537 mutex_enter(&sc->sc_lock); 3538 3539 sqh = epipe->sqh; 3540 3541 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3542 "address QH %" __PRIuBIT " pipe %d\n", 3543 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3544 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3545 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3546 "MPS QH %" __PRIuBIT " pipe %d\n", 3547 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3548 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3549 3550 /* Set up data transaction */ 3551 if (len != 0) { 3552 ehci_soft_qtd_t *end; 3553 3554 /* Start toggle at 1. */ 3555 epipe->nexttoggle = 1; 3556 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3557 &next, &end); 3558 if (err) 3559 goto bad3; 3560 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3561 end->nextqtd = stat; 3562 end->qtd.qtd_next = end->qtd.qtd_altnext = 3563 htole32(stat->physaddr); 3564 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3565 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3566 } else { 3567 next = stat; 3568 } 3569 3570 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3571 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3572 3573 /* Clear toggle */ 3574 setup->qtd.qtd_status = htole32( 3575 EHCI_QTD_ACTIVE | 3576 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3577 EHCI_QTD_SET_CERR(3) | 3578 EHCI_QTD_SET_TOGGLE(0) | 3579 EHCI_QTD_SET_BYTES(sizeof(*req)) 3580 ); 3581 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3582 setup->qtd.qtd_buffer_hi[0] = 0; 3583 setup->nextqtd = next; 3584 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3585 setup->xfer = xfer; 3586 setup->len = sizeof(*req); 3587 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3588 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3589 3590 stat->qtd.qtd_status = htole32( 3591 EHCI_QTD_ACTIVE | 3592 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3593 EHCI_QTD_SET_CERR(3) | 3594 EHCI_QTD_SET_TOGGLE(1) | 3595 EHCI_QTD_IOC 3596 ); 3597 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3598 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3599 stat->nextqtd = NULL; 3600 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3601 stat->xfer = xfer; 3602 stat->len = 0; 3603 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3604 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3605 3606 #ifdef EHCI_DEBUG 3607 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3608 ehci_dump_sqh(sqh); 3609 ehci_dump_sqtds(setup); 3610 #endif 3611 3612 exfer->ex_sqtdstart = setup; 3613 exfer->ex_sqtdend = stat; 3614 KASSERT(exfer->ex_isdone); 3615 #ifdef DIAGNOSTIC 3616 exfer->ex_isdone = false; 3617 #endif 3618 3619 /* Insert qTD in QH list. */ 3620 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3621 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3622 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3623 ehci_timeout, xfer); 3624 } 3625 ehci_add_intr_list(sc, exfer); 3626 xfer->ux_status = USBD_IN_PROGRESS; 3627 mutex_exit(&sc->sc_lock); 3628 3629 #ifdef EHCI_DEBUG 3630 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3631 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3632 // delay(10000); 3633 ehci_dump_regs(sc); 3634 ehci_dump_sqh(sc->sc_async_head); 3635 ehci_dump_sqh(sqh); 3636 ehci_dump_sqtds(setup); 3637 #endif 3638 3639 return USBD_NORMAL_COMPLETION; 3640 3641 bad3: 3642 mutex_exit(&sc->sc_lock); 3643 ehci_free_sqtd(sc, stat); 3644 bad2: 3645 ehci_free_sqtd(sc, setup); 3646 bad1: 3647 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3648 mutex_enter(&sc->sc_lock); 3649 xfer->ux_status = err; 3650 usb_transfer_complete(xfer); 3651 mutex_exit(&sc->sc_lock); 3652 return err; 3653 } 3654 3655 /* 3656 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3657 * qTD status, or miss signalling occasionally under heavy load. If the host 3658 * machine is too fast, we we can miss transaction completion - when we scan 3659 * the active list the transaction still seems to be active. This generally 3660 * exhibits itself as a umass stall that never recovers. 3661 * 3662 * We work around this behaviour by setting up this callback after any softintr 3663 * that completes with transactions still pending, giving us another chance to 3664 * check for completion after the writeback has taken place. 3665 */ 3666 Static void 3667 ehci_intrlist_timeout(void *arg) 3668 { 3669 ehci_softc_t *sc = arg; 3670 3671 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3672 3673 usb_schedsoftintr(&sc->sc_bus); 3674 } 3675 3676 /************************/ 3677 3678 Static usbd_status 3679 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3680 { 3681 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3682 usbd_status err; 3683 3684 /* Insert last in queue. */ 3685 mutex_enter(&sc->sc_lock); 3686 err = usb_insert_transfer(xfer); 3687 mutex_exit(&sc->sc_lock); 3688 if (err) 3689 return err; 3690 3691 /* Pipe isn't running, start first */ 3692 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3693 } 3694 3695 Static usbd_status 3696 ehci_device_bulk_start(struct usbd_xfer *xfer) 3697 { 3698 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3699 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3700 ehci_softc_t *sc = EHCI_XFER2SC(xfer);; 3701 ehci_soft_qtd_t *data, *dataend; 3702 ehci_soft_qh_t *sqh; 3703 usbd_status err; 3704 int len, isread, endpt; 3705 3706 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3707 3708 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3709 xfer, xfer->ux_length, xfer->ux_flags, 0); 3710 3711 if (sc->sc_dying) 3712 return USBD_IOERROR; 3713 3714 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3715 3716 mutex_enter(&sc->sc_lock); 3717 3718 len = xfer->ux_length; 3719 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3720 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3721 sqh = epipe->sqh; 3722 3723 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3724 &dataend); 3725 if (err) { 3726 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3727 xfer->ux_status = err; 3728 usb_transfer_complete(xfer); 3729 mutex_exit(&sc->sc_lock); 3730 return err; 3731 } 3732 3733 #ifdef EHCI_DEBUG 3734 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3735 ehci_dump_sqh(sqh); 3736 ehci_dump_sqtds(data); 3737 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3738 #endif 3739 3740 /* Set up interrupt info. */ 3741 exfer->ex_sqtdstart = data; 3742 exfer->ex_sqtdend = dataend; 3743 KASSERT(exfer->ex_isdone); 3744 #ifdef DIAGNOSTIC 3745 exfer->ex_isdone = false; 3746 #endif 3747 3748 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3749 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3750 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3751 ehci_timeout, xfer); 3752 } 3753 ehci_add_intr_list(sc, exfer); 3754 xfer->ux_status = USBD_IN_PROGRESS; 3755 mutex_exit(&sc->sc_lock); 3756 3757 #ifdef EHCI_DEBUG 3758 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3759 // delay(10000); 3760 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3761 ehci_dump_regs(sc); 3762 #if 0 3763 printf("async_head:\n"); 3764 ehci_dump_sqh(sc->sc_async_head); 3765 #endif 3766 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3767 ehci_dump_sqh(sqh); 3768 ehci_dump_sqtds(data); 3769 #endif 3770 3771 if (sc->sc_bus.ub_usepolling) 3772 ehci_waitintr(sc, xfer); 3773 3774 return USBD_IN_PROGRESS; 3775 } 3776 3777 Static void 3778 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3779 { 3780 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3781 3782 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3783 ehci_abort_xfer(xfer, USBD_CANCELLED); 3784 } 3785 3786 /* 3787 * Close a device bulk pipe. 3788 */ 3789 Static void 3790 ehci_device_bulk_close(struct usbd_pipe *pipe) 3791 { 3792 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3793 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3794 3795 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3796 3797 KASSERT(mutex_owned(&sc->sc_lock)); 3798 3799 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3800 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3801 ehci_close_pipe(pipe, sc->sc_async_head); 3802 } 3803 3804 Static void 3805 ehci_device_bulk_done(struct usbd_xfer *xfer) 3806 { 3807 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3808 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3809 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3810 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3811 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3812 3813 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3814 3815 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3816 xfer, xfer->ux_actlen, 0, 0); 3817 3818 KASSERT(mutex_owned(&sc->sc_lock)); 3819 3820 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3821 ehci_del_intr_list(sc, ex); /* remove from active list */ 3822 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3823 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3824 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3825 } 3826 3827 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3828 } 3829 3830 /************************/ 3831 3832 Static usbd_status 3833 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3834 { 3835 struct ehci_soft_islot *isp; 3836 int islot, lev; 3837 3838 /* Find a poll rate that is large enough. */ 3839 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3840 if (EHCI_ILEV_IVAL(lev) <= ival) 3841 break; 3842 3843 /* Pick an interrupt slot at the right level. */ 3844 /* XXX could do better than picking at random */ 3845 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3846 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3847 3848 sqh->islot = islot; 3849 isp = &sc->sc_islots[islot]; 3850 mutex_enter(&sc->sc_lock); 3851 ehci_add_qh(sc, sqh, isp->sqh); 3852 mutex_exit(&sc->sc_lock); 3853 3854 return USBD_NORMAL_COMPLETION; 3855 } 3856 3857 Static usbd_status 3858 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3859 { 3860 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3861 usbd_status err; 3862 3863 /* Insert last in queue. */ 3864 mutex_enter(&sc->sc_lock); 3865 err = usb_insert_transfer(xfer); 3866 mutex_exit(&sc->sc_lock); 3867 if (err) 3868 return err; 3869 3870 /* 3871 * Pipe isn't running (otherwise err would be USBD_INPROG), 3872 * so start it first. 3873 */ 3874 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3875 } 3876 3877 Static usbd_status 3878 ehci_device_intr_start(struct usbd_xfer *xfer) 3879 { 3880 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3881 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3882 ehci_softc_t *sc = EHCI_XFER2SC(xfer);; 3883 ehci_soft_qtd_t *data, *dataend; 3884 ehci_soft_qh_t *sqh; 3885 usbd_status err; 3886 int len, isread, endpt; 3887 3888 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3889 3890 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3891 xfer, xfer->ux_length, xfer->ux_flags, 0); 3892 3893 if (sc->sc_dying) 3894 return USBD_IOERROR; 3895 3896 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3897 3898 mutex_enter(&sc->sc_lock); 3899 3900 len = xfer->ux_length; 3901 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3902 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3903 sqh = epipe->sqh; 3904 3905 epipe->intr.length = len; 3906 3907 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3908 &dataend); 3909 if (err) { 3910 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3911 xfer->ux_status = err; 3912 usb_transfer_complete(xfer); 3913 mutex_exit(&sc->sc_lock); 3914 return err; 3915 } 3916 3917 #ifdef EHCI_DEBUG 3918 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3919 ehci_dump_sqh(sqh); 3920 ehci_dump_sqtds(data); 3921 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3922 #endif 3923 3924 /* Set up interrupt info. */ 3925 exfer->ex_sqtdstart = data; 3926 exfer->ex_sqtdend = dataend; 3927 KASSERT(exfer->ex_isdone); 3928 #ifdef DIAGNOSTIC 3929 exfer->ex_isdone = false; 3930 #endif 3931 3932 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3933 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3934 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3935 ehci_timeout, xfer); 3936 } 3937 ehci_add_intr_list(sc, exfer); 3938 xfer->ux_status = USBD_IN_PROGRESS; 3939 mutex_exit(&sc->sc_lock); 3940 3941 #ifdef EHCI_DEBUG 3942 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3943 // delay(10000); 3944 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3945 ehci_dump_regs(sc); 3946 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3947 ehci_dump_sqh(sqh); 3948 ehci_dump_sqtds(data); 3949 #endif 3950 3951 if (sc->sc_bus.ub_usepolling) 3952 ehci_waitintr(sc, xfer); 3953 3954 return USBD_IN_PROGRESS; 3955 } 3956 3957 Static void 3958 ehci_device_intr_abort(struct usbd_xfer *xfer) 3959 { 3960 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3961 3962 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3963 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3964 3965 /* 3966 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3967 * async doorbell. That's dependent on the async list, wheras 3968 * intr xfers are periodic, should not use this? 3969 */ 3970 ehci_abort_xfer(xfer, USBD_CANCELLED); 3971 } 3972 3973 Static void 3974 ehci_device_intr_close(struct usbd_pipe *pipe) 3975 { 3976 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3977 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3978 struct ehci_soft_islot *isp; 3979 3980 KASSERT(mutex_owned(&sc->sc_lock)); 3981 3982 isp = &sc->sc_islots[epipe->sqh->islot]; 3983 ehci_close_pipe(pipe, isp->sqh); 3984 } 3985 3986 Static void 3987 ehci_device_intr_done(struct usbd_xfer *xfer) 3988 { 3989 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3990 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3991 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3992 ehci_soft_qtd_t *data, *dataend; 3993 ehci_soft_qh_t *sqh; 3994 usbd_status err; 3995 int len, isread, endpt; 3996 3997 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3998 3999 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4000 xfer, xfer->ux_actlen, 0, 0); 4001 4002 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4003 4004 if (xfer->ux_pipe->up_repeat) { 4005 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4006 4007 len = epipe->intr.length; 4008 xfer->ux_length = len; 4009 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4010 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4011 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4012 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4013 sqh = epipe->sqh; 4014 4015 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4016 &data, &dataend); 4017 if (err) { 4018 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4019 xfer->ux_status = err; 4020 return; 4021 } 4022 4023 /* Set up interrupt info. */ 4024 exfer->ex_sqtdstart = data; 4025 exfer->ex_sqtdend = dataend; 4026 KASSERT(exfer->ex_isdone); 4027 #ifdef DIAGNOSTIC 4028 exfer->ex_isdone = false; 4029 #endif 4030 4031 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4032 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4033 callout_reset(&xfer->ux_callout, 4034 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4035 } 4036 4037 xfer->ux_status = USBD_IN_PROGRESS; 4038 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4039 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4040 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4041 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4042 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4043 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4044 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4045 } 4046 } 4047 4048 /************************/ 4049 4050 Static usbd_status 4051 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4052 { 4053 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4054 usbd_status err; 4055 4056 mutex_enter(&sc->sc_lock); 4057 err = usb_insert_transfer(xfer); 4058 mutex_exit(&sc->sc_lock); 4059 4060 if (err && err != USBD_IN_PROGRESS) 4061 return err; 4062 4063 return ehci_device_fs_isoc_start(xfer); 4064 } 4065 4066 Static usbd_status 4067 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4068 { 4069 struct ehci_pipe *epipe; 4070 struct usbd_device *dev; 4071 ehci_softc_t *sc; 4072 struct ehci_xfer *exfer; 4073 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4074 usb_dma_t *dma_buf; 4075 int i, j, k, frames; 4076 int offs, total_length; 4077 int frindex; 4078 u_int huba, dir; 4079 4080 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4081 4082 start = NULL; 4083 prev = NULL; 4084 sitd = NULL; 4085 total_length = 0; 4086 exfer = EHCI_XFER2EXFER(xfer); 4087 sc = EHCI_XFER2SC(xfer); 4088 dev = xfer->ux_pipe->up_dev; 4089 epipe = EHCI_XFER2EPIPE(xfer); 4090 4091 /* 4092 * To allow continuous transfers, above we start all transfers 4093 * immediately. However, we're still going to get usbd_start_next call 4094 * this when another xfer completes. So, check if this is already 4095 * in progress or not 4096 */ 4097 4098 if (exfer->ex_sitdstart != NULL) 4099 return USBD_IN_PROGRESS; 4100 4101 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4102 xfer, xfer->ux_length, xfer->ux_flags, 0); 4103 4104 if (sc->sc_dying) 4105 return USBD_IOERROR; 4106 4107 /* 4108 * To avoid complication, don't allow a request right now that'll span 4109 * the entire frame table. To within 4 frames, to allow some leeway 4110 * on either side of where the hc currently is. 4111 */ 4112 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4113 xfer->ux_nframes >= sc->sc_flsize - 4) { 4114 printf("ehci: isoc descriptor requested that spans the entire" 4115 "frametable, too many frames\n"); 4116 return USBD_INVAL; 4117 } 4118 4119 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4120 KASSERT(exfer->ex_isdone); 4121 4122 #ifdef DIAGNOSTIC 4123 exfer->ex_isdone = false; 4124 #endif 4125 4126 /* 4127 * Step 1: Allocate and initialize sitds. 4128 */ 4129 4130 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4131 if (i > 16 || i == 0) { 4132 /* Spec page 271 says intervals > 16 are invalid */ 4133 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4134 4135 return USBD_INVAL; 4136 } 4137 4138 frames = xfer->ux_nframes; 4139 4140 if (frames == 0) { 4141 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4142 4143 return USBD_INVAL; 4144 } 4145 4146 dma_buf = &xfer->ux_dmabuf; 4147 offs = 0; 4148 4149 for (i = 0; i < frames; i++) { 4150 sitd = ehci_alloc_sitd(sc); 4151 4152 if (prev) 4153 prev->xfer_next = sitd; 4154 else 4155 start = sitd; 4156 4157 #ifdef DIAGNOSTIC 4158 if (xfer->ux_frlengths[i] > 0x3ff) { 4159 printf("ehci: invalid frame length\n"); 4160 xfer->ux_frlengths[i] = 0x3ff; 4161 } 4162 #endif 4163 4164 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4165 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4166 4167 /* Set page0 index and offset. */ 4168 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4169 4170 total_length += xfer->ux_frlengths[i]; 4171 offs += xfer->ux_frlengths[i]; 4172 4173 sitd->sitd.sitd_buffer[1] = 4174 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4175 4176 huba = dev->ud_myhsport->up_parent->ud_addr; 4177 4178 #if 0 4179 if (sc->sc_flags & EHCIF_FREESCALE) { 4180 // Set hub address to 0 if embedded TT is used. 4181 if (huba == sc->sc_addr) 4182 huba = 0; 4183 } 4184 #endif 4185 4186 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4187 dir = UE_GET_DIR(k) ? 1 : 0; 4188 sitd->sitd.sitd_endp = 4189 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4190 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4191 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4192 EHCI_SITD_SET_HUBA(huba) | 4193 EHCI_SITD_SET_DIR(dir)); 4194 4195 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4196 4197 /* XXX */ 4198 u_char sa, sb; 4199 u_int temp, tlen; 4200 sa = 0; 4201 4202 if (dir == 0) { /* OUT */ 4203 temp = 0; 4204 tlen = xfer->ux_frlengths[i]; 4205 if (tlen <= 188) { 4206 temp |= 1; /* T-count = 1, TP = ALL */ 4207 tlen = 1; 4208 } else { 4209 tlen += 187; 4210 tlen /= 188; 4211 temp |= tlen; /* T-count = [1..6] */ 4212 temp |= 8; /* TP = Begin */ 4213 } 4214 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4215 4216 tlen += sa; 4217 4218 if (tlen >= 8) { 4219 sb = 0; 4220 } else { 4221 sb = (1 << tlen); 4222 } 4223 4224 sa = (1 << sa); 4225 sa = (sb - sa) & 0x3F; 4226 sb = 0; 4227 } else { 4228 sb = (-(4 << sa)) & 0xFE; 4229 sa = (1 << sa) & 0x3F; 4230 sa = 0x01; 4231 sb = 0xfc; 4232 } 4233 4234 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4235 EHCI_SITD_SET_CMASK(sb)); 4236 4237 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4238 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4239 4240 prev = sitd; 4241 } /* End of frame */ 4242 4243 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4244 4245 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4246 sizeof(sitd->sitd.sitd_trans), 4247 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4248 4249 stop = sitd; 4250 stop->xfer_next = NULL; 4251 4252 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4253 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4254 4255 /* 4256 * Part 2: Transfer descriptors have now been set up, now they must 4257 * be scheduled into the periodic frame list. Erk. Not wanting to 4258 * complicate matters, transfer is denied if the transfer spans 4259 * more than the period frame list. 4260 */ 4261 4262 mutex_enter(&sc->sc_lock); 4263 4264 /* Start inserting frames */ 4265 if (epipe->isoc.cur_xfers > 0) { 4266 frindex = epipe->isoc.next_frame; 4267 } else { 4268 frindex = EOREAD4(sc, EHCI_FRINDEX); 4269 frindex = frindex >> 3; /* Erase microframe index */ 4270 frindex += 2; 4271 } 4272 4273 if (frindex >= sc->sc_flsize) 4274 frindex &= (sc->sc_flsize - 1); 4275 4276 /* Whats the frame interval? */ 4277 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4278 4279 sitd = start; 4280 for (j = 0; j < frames; j++) { 4281 if (sitd == NULL) 4282 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4283 4284 usb_syncmem(&sc->sc_fldma, 4285 sizeof(ehci_link_t) * frindex, 4286 sizeof(ehci_link_t), 4287 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4288 4289 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4290 if (sitd->sitd.sitd_next == 0) 4291 /* 4292 * FIXME: frindex table gets initialized to NULL 4293 * or EHCI_NULL? 4294 */ 4295 sitd->sitd.sitd_next = EHCI_NULL; 4296 4297 usb_syncmem(&sitd->dma, 4298 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4299 sizeof(ehci_sitd_t), 4300 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4301 4302 sc->sc_flist[frindex] = 4303 htole32(EHCI_LINK_SITD | sitd->physaddr); 4304 4305 usb_syncmem(&sc->sc_fldma, 4306 sizeof(ehci_link_t) * frindex, 4307 sizeof(ehci_link_t), 4308 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4309 4310 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4311 sc->sc_softsitds[frindex] = sitd; 4312 if (sitd->frame_list.next != NULL) 4313 sitd->frame_list.next->frame_list.prev = sitd; 4314 sitd->slot = frindex; 4315 sitd->frame_list.prev = NULL; 4316 4317 frindex += i; 4318 if (frindex >= sc->sc_flsize) 4319 frindex -= sc->sc_flsize; 4320 4321 sitd = sitd->xfer_next; 4322 } 4323 4324 epipe->isoc.cur_xfers++; 4325 epipe->isoc.next_frame = frindex; 4326 4327 exfer->ex_sitdstart = start; 4328 exfer->ex_sitdend = stop; 4329 4330 ehci_add_intr_list(sc, exfer); 4331 xfer->ux_status = USBD_IN_PROGRESS; 4332 4333 mutex_exit(&sc->sc_lock); 4334 4335 if (sc->sc_bus.ub_usepolling) { 4336 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4337 ehci_waitintr(sc, xfer); 4338 } 4339 4340 return USBD_IN_PROGRESS; 4341 } 4342 4343 Static void 4344 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4345 { 4346 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4347 4348 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4349 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4350 } 4351 4352 Static void 4353 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4354 { 4355 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4356 4357 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4358 } 4359 4360 Static void 4361 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4362 { 4363 struct ehci_xfer *exfer; 4364 ehci_softc_t *sc; 4365 struct ehci_pipe *epipe; 4366 4367 exfer = EHCI_XFER2EXFER(xfer); 4368 sc = EHCI_XFER2SC(xfer); 4369 epipe = EHCI_XFER2EPIPE(xfer); 4370 4371 KASSERT(mutex_owned(&sc->sc_lock)); 4372 4373 epipe->isoc.cur_xfers--; 4374 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4375 ehci_del_intr_list(sc, exfer); 4376 ehci_rem_free_sitd_chain(sc, exfer); 4377 } 4378 4379 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4380 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4381 } 4382 Static usbd_status 4383 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4384 { 4385 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4386 usbd_status err; 4387 4388 mutex_enter(&sc->sc_lock); 4389 err = usb_insert_transfer(xfer); 4390 mutex_exit(&sc->sc_lock); 4391 if (err && err != USBD_IN_PROGRESS) 4392 return err; 4393 4394 return ehci_device_isoc_start(xfer); 4395 } 4396 4397 Static usbd_status 4398 ehci_device_isoc_start(struct usbd_xfer *xfer) 4399 { 4400 struct ehci_pipe *epipe; 4401 ehci_softc_t *sc; 4402 struct ehci_xfer *exfer; 4403 ehci_soft_itd_t *itd, *prev, *start, *stop; 4404 usb_dma_t *dma_buf; 4405 int i, j, k, frames, uframes, ufrperframe; 4406 int trans_count, offs, total_length; 4407 int frindex; 4408 4409 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4410 4411 start = NULL; 4412 prev = NULL; 4413 itd = NULL; 4414 trans_count = 0; 4415 total_length = 0; 4416 exfer = EHCI_XFER2EXFER(xfer); 4417 sc = EHCI_XFER2SC(xfer); 4418 epipe = EHCI_XFER2EPIPE(xfer); 4419 4420 /* 4421 * To allow continuous transfers, above we start all transfers 4422 * immediately. However, we're still going to get usbd_start_next call 4423 * this when another xfer completes. So, check if this is already 4424 * in progress or not 4425 */ 4426 4427 if (exfer->ex_itdstart != NULL) 4428 return USBD_IN_PROGRESS; 4429 4430 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4431 xfer, xfer->ux_length, xfer->ux_flags, 0); 4432 4433 if (sc->sc_dying) 4434 return USBD_IOERROR; 4435 4436 /* 4437 * To avoid complication, don't allow a request right now that'll span 4438 * the entire frame table. To within 4 frames, to allow some leeway 4439 * on either side of where the hc currently is. 4440 */ 4441 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4442 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4443 USBHIST_LOG(ehcidebug, 4444 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4445 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4446 return USBD_INVAL; 4447 } 4448 4449 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4450 KASSERT(exfer->ex_isdone); 4451 #ifdef DIAGNOSTIC 4452 exfer->ex_isdone = false; 4453 #endif 4454 4455 /* 4456 * Step 1: Allocate and initialize itds, how many do we need? 4457 * One per transfer if interval >= 8 microframes, fewer if we use 4458 * multiple microframes per frame. 4459 */ 4460 4461 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4462 if (i > 16 || i == 0) { 4463 /* Spec page 271 says intervals > 16 are invalid */ 4464 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4465 return USBD_INVAL; 4466 } 4467 4468 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4469 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4470 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4471 4472 if (frames == 0) { 4473 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4474 return USBD_INVAL; 4475 } 4476 4477 dma_buf = &xfer->ux_dmabuf; 4478 offs = 0; 4479 4480 for (i = 0; i < frames; i++) { 4481 int froffs = offs; 4482 itd = ehci_alloc_itd(sc); 4483 4484 if (prev != NULL) { 4485 prev->itd.itd_next = 4486 htole32(itd->physaddr | EHCI_LINK_ITD); 4487 usb_syncmem(&prev->dma, 4488 prev->offs + offsetof(ehci_itd_t, itd_next), 4489 sizeof(prev->itd.itd_next), 4490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4491 4492 prev->xfer_next = itd; 4493 } else { 4494 start = itd; 4495 } 4496 4497 /* 4498 * Step 1.5, initialize uframes 4499 */ 4500 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4501 /* Calculate which page in the list this starts in */ 4502 int addr = DMAADDR(dma_buf, froffs); 4503 addr = EHCI_PAGE_OFFSET(addr); 4504 addr += (offs - froffs); 4505 addr = EHCI_PAGE(addr); 4506 addr /= EHCI_PAGE_SIZE; 4507 4508 /* 4509 * This gets the initial offset into the first page, 4510 * looks how far further along the current uframe 4511 * offset is. Works out how many pages that is. 4512 */ 4513 4514 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4515 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4516 EHCI_ITD_SET_PG(addr) | 4517 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4518 4519 total_length += xfer->ux_frlengths[trans_count]; 4520 offs += xfer->ux_frlengths[trans_count]; 4521 trans_count++; 4522 4523 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4524 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4525 break; 4526 } 4527 } 4528 4529 /* 4530 * Step 1.75, set buffer pointers. To simplify matters, all 4531 * pointers are filled out for the next 7 hardware pages in 4532 * the dma block, so no need to worry what pages to cover 4533 * and what to not. 4534 */ 4535 4536 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4537 /* 4538 * Don't try to lookup a page that's past the end 4539 * of buffer 4540 */ 4541 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4542 if (page_offs >= dma_buf->udma_block->size) 4543 break; 4544 4545 unsigned long long page = DMAADDR(dma_buf, page_offs); 4546 page = EHCI_PAGE(page); 4547 itd->itd.itd_bufr[j] = 4548 htole32(EHCI_ITD_SET_BPTR(page)); 4549 itd->itd.itd_bufr_hi[j] = 4550 htole32(page >> 32); 4551 } 4552 4553 /* 4554 * Other special values 4555 */ 4556 4557 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4558 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4559 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4560 4561 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4562 ? 1 : 0; 4563 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4564 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4565 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4566 4567 /* FIXME: handle invalid trans */ 4568 itd->itd.itd_bufr[2] |= 4569 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4570 4571 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4572 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4573 4574 prev = itd; 4575 } /* End of frame */ 4576 4577 stop = itd; 4578 stop->xfer_next = NULL; 4579 4580 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4581 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4582 4583 /* 4584 * Part 2: Transfer descriptors have now been set up, now they must 4585 * be scheduled into the period frame list. Erk. Not wanting to 4586 * complicate matters, transfer is denied if the transfer spans 4587 * more than the period frame list. 4588 */ 4589 4590 mutex_enter(&sc->sc_lock); 4591 4592 /* Start inserting frames */ 4593 if (epipe->isoc.cur_xfers > 0) { 4594 frindex = epipe->isoc.next_frame; 4595 } else { 4596 frindex = EOREAD4(sc, EHCI_FRINDEX); 4597 frindex = frindex >> 3; /* Erase microframe index */ 4598 frindex += 2; 4599 } 4600 4601 if (frindex >= sc->sc_flsize) 4602 frindex &= (sc->sc_flsize - 1); 4603 4604 /* What's the frame interval? */ 4605 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4606 if (i / USB_UFRAMES_PER_FRAME == 0) 4607 i = 1; 4608 else 4609 i /= USB_UFRAMES_PER_FRAME; 4610 4611 itd = start; 4612 for (j = 0; j < frames; j++) { 4613 if (itd == NULL) 4614 panic("ehci: unexpectedly ran out of isoc itds, isoc_start"); 4615 4616 usb_syncmem(&sc->sc_fldma, 4617 sizeof(ehci_link_t) * frindex, 4618 sizeof(ehci_link_t), 4619 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4620 4621 itd->itd.itd_next = sc->sc_flist[frindex]; 4622 if (itd->itd.itd_next == 0) 4623 /* 4624 * FIXME: frindex table gets initialized to NULL 4625 * or EHCI_NULL? 4626 */ 4627 itd->itd.itd_next = EHCI_NULL; 4628 4629 usb_syncmem(&itd->dma, 4630 itd->offs + offsetof(ehci_itd_t, itd_next), 4631 sizeof(itd->itd.itd_next), 4632 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4633 4634 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4635 4636 usb_syncmem(&sc->sc_fldma, 4637 sizeof(ehci_link_t) * frindex, 4638 sizeof(ehci_link_t), 4639 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4640 4641 itd->frame_list.next = sc->sc_softitds[frindex]; 4642 sc->sc_softitds[frindex] = itd; 4643 if (itd->frame_list.next != NULL) 4644 itd->frame_list.next->frame_list.prev = itd; 4645 itd->slot = frindex; 4646 itd->frame_list.prev = NULL; 4647 4648 frindex += i; 4649 if (frindex >= sc->sc_flsize) 4650 frindex -= sc->sc_flsize; 4651 4652 itd = itd->xfer_next; 4653 } 4654 4655 epipe->isoc.cur_xfers++; 4656 epipe->isoc.next_frame = frindex; 4657 4658 exfer->ex_itdstart = start; 4659 exfer->ex_itdend = stop; 4660 4661 ehci_add_intr_list(sc, exfer); 4662 xfer->ux_status = USBD_IN_PROGRESS; 4663 mutex_exit(&sc->sc_lock); 4664 4665 if (sc->sc_bus.ub_usepolling) { 4666 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4667 ehci_waitintr(sc, xfer); 4668 } 4669 4670 return USBD_IN_PROGRESS; 4671 } 4672 4673 Static void 4674 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4675 { 4676 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4677 4678 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4679 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4680 } 4681 4682 Static void 4683 ehci_device_isoc_close(struct usbd_pipe *pipe) 4684 { 4685 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4686 4687 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4688 } 4689 4690 Static void 4691 ehci_device_isoc_done(struct usbd_xfer *xfer) 4692 { 4693 struct ehci_xfer *exfer; 4694 ehci_softc_t *sc; 4695 struct ehci_pipe *epipe; 4696 4697 exfer = EHCI_XFER2EXFER(xfer); 4698 sc = EHCI_XFER2SC(xfer); 4699 epipe = EHCI_XFER2EPIPE(xfer); 4700 4701 KASSERT(mutex_owned(&sc->sc_lock)); 4702 4703 epipe->isoc.cur_xfers--; 4704 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4705 ehci_del_intr_list(sc, exfer); 4706 ehci_rem_free_itd_chain(sc, exfer); 4707 } 4708 4709 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4710 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4711 4712 } 4713
Indexes created Wed Oct 01 19:09:53 GMT 2025