ehci.c revision 1.234.2.71
1 /* $NetBSD: ehci.c,v 1.234.2.71 2015/12/23 07:59:19 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.71 2015/12/23 07:59:19 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 /* Control pipe */ 136 struct { 137 usb_dma_t reqdma; 138 } ctrl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Iso pipe */ 144 struct { 145 u_int next_frame; 146 u_int cur_xfers; 147 } isoc; 148 }; 149 }; 150 151 Static usbd_status ehci_open(struct usbd_pipe *); 152 Static void ehci_poll(struct usbd_bus *); 153 Static void ehci_softintr(void *); 154 Static int ehci_intr1(ehci_softc_t *); 155 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 156 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 157 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 158 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 159 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 160 Static void ehci_idone(struct ehci_xfer *); 161 Static void ehci_timeout(void *); 162 Static void ehci_timeout_task(void *); 163 Static void ehci_intrlist_timeout(void *); 164 Static void ehci_doorbell(void *); 165 Static void ehci_pcd(void *); 166 167 Static struct usbd_xfer * 168 ehci_allocx(struct usbd_bus *, unsigned int); 169 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 170 171 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 172 Static int ehci_roothub_ctrl(struct usbd_bus *, 173 usb_device_request_t *, void *, int); 174 175 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 176 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 177 Static void ehci_root_intr_abort(struct usbd_xfer *); 178 Static void ehci_root_intr_close(struct usbd_pipe *); 179 Static void ehci_root_intr_done(struct usbd_xfer *); 180 181 Static int ehci_device_ctrl_init(struct usbd_xfer *); 182 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 183 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 185 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 186 Static void ehci_device_ctrl_close(struct usbd_pipe *); 187 Static void ehci_device_ctrl_done(struct usbd_xfer *); 188 189 Static int ehci_device_bulk_init(struct usbd_xfer *); 190 Static void ehci_device_bulk_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 193 Static void ehci_device_bulk_abort(struct usbd_xfer *); 194 Static void ehci_device_bulk_close(struct usbd_pipe *); 195 Static void ehci_device_bulk_done(struct usbd_xfer *); 196 197 Static int ehci_device_intr_init(struct usbd_xfer *); 198 Static void ehci_device_intr_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 201 Static void ehci_device_intr_abort(struct usbd_xfer *); 202 Static void ehci_device_intr_close(struct usbd_pipe *); 203 Static void ehci_device_intr_done(struct usbd_xfer *); 204 205 Static int ehci_device_isoc_init(struct usbd_xfer *); 206 Static void ehci_device_isoc_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 209 Static void ehci_device_isoc_abort(struct usbd_xfer *); 210 Static void ehci_device_isoc_close(struct usbd_pipe *); 211 Static void ehci_device_isoc_done(struct usbd_xfer *); 212 213 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 216 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 217 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 220 221 Static void ehci_device_clear_toggle(struct usbd_pipe *); 222 Static void ehci_noop(struct usbd_pipe *); 223 224 Static void ehci_disown(ehci_softc_t *, int, int); 225 226 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 227 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 228 229 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 230 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 231 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 232 int, int, ehci_soft_qtd_t **, ehci_soft_qtd_t **); 233 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 234 235 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 236 int, int, int *, ehci_soft_qtd_t **); 237 238 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 239 Static ehci_soft_sitd_t * 240 ehci_alloc_sitd(ehci_softc_t *); 241 242 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 243 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 244 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 245 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 246 247 static inline void 248 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 249 { 250 251 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 252 } 253 254 static inline void 255 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 259 } 260 261 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 262 263 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 264 int); 265 266 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 267 ehci_soft_qh_t *); 268 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 269 ehci_soft_qh_t *); 270 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 271 Static void ehci_sync_hc(ehci_softc_t *); 272 273 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 274 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 275 276 #ifdef EHCI_DEBUG 277 Static ehci_softc_t *theehci; 278 void ehci_dump(void); 279 #endif 280 281 #ifdef EHCI_DEBUG 282 Static void ehci_dump_regs(ehci_softc_t *); 283 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 284 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 285 Static void ehci_dump_qtd(ehci_qtd_t *); 286 Static void ehci_dump_sqh(ehci_soft_qh_t *); 287 Static void ehci_dump_sitd(struct ehci_soft_itd *); 288 Static void ehci_dump_itds(ehci_soft_itd_t *); 289 Static void ehci_dump_itd(struct ehci_soft_itd *); 290 Static void ehci_dump_exfer(struct ehci_xfer *); 291 #endif 292 293 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 294 295 #define ehci_add_intr_list(sc, ex) \ 296 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 297 #define ehci_del_intr_list(sc, ex) \ 298 do { \ 299 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 300 (ex)->ex_next.tqe_prev = NULL; \ 301 } while (0) 302 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 303 304 Static const struct usbd_bus_methods ehci_bus_methods = { 305 .ubm_open = ehci_open, 306 .ubm_softint = ehci_softintr, 307 .ubm_dopoll = ehci_poll, 308 .ubm_allocx = ehci_allocx, 309 .ubm_freex = ehci_freex, 310 .ubm_getlock = ehci_get_lock, 311 .ubm_rhctrl = ehci_roothub_ctrl, 312 }; 313 314 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 315 .upm_transfer = ehci_root_intr_transfer, 316 .upm_start = ehci_root_intr_start, 317 .upm_abort = ehci_root_intr_abort, 318 .upm_close = ehci_root_intr_close, 319 .upm_cleartoggle = ehci_noop, 320 .upm_done = ehci_root_intr_done, 321 }; 322 323 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 324 .upm_init = ehci_device_ctrl_init, 325 .upm_fini = ehci_device_ctrl_fini, 326 .upm_transfer = ehci_device_ctrl_transfer, 327 .upm_start = ehci_device_ctrl_start, 328 .upm_abort = ehci_device_ctrl_abort, 329 .upm_close = ehci_device_ctrl_close, 330 .upm_cleartoggle = ehci_noop, 331 .upm_done = ehci_device_ctrl_done, 332 }; 333 334 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 335 .upm_init = ehci_device_intr_init, 336 .upm_fini = ehci_device_intr_fini, 337 .upm_transfer = ehci_device_intr_transfer, 338 .upm_start = ehci_device_intr_start, 339 .upm_abort = ehci_device_intr_abort, 340 .upm_close = ehci_device_intr_close, 341 .upm_cleartoggle = ehci_device_clear_toggle, 342 .upm_done = ehci_device_intr_done, 343 }; 344 345 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 346 .upm_init = ehci_device_bulk_init, 347 .upm_fini = ehci_device_bulk_fini, 348 .upm_transfer = ehci_device_bulk_transfer, 349 .upm_start = ehci_device_bulk_start, 350 .upm_abort = ehci_device_bulk_abort, 351 .upm_close = ehci_device_bulk_close, 352 .upm_cleartoggle = ehci_device_clear_toggle, 353 .upm_done = ehci_device_bulk_done, 354 }; 355 356 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 357 .upm_init = ehci_device_isoc_init, 358 .upm_fini = ehci_device_isoc_fini, 359 .upm_transfer = ehci_device_isoc_transfer, 360 .upm_start = ehci_device_isoc_start, 361 .upm_abort = ehci_device_isoc_abort, 362 .upm_close = ehci_device_isoc_close, 363 .upm_cleartoggle = ehci_noop, 364 .upm_done = ehci_device_isoc_done, 365 }; 366 367 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 368 .upm_init = ehci_device_fs_isoc_init, 369 .upm_fini = ehci_device_fs_isoc_fini, 370 .upm_transfer = ehci_device_fs_isoc_transfer, 371 .upm_start = ehci_device_fs_isoc_start, 372 .upm_abort = ehci_device_fs_isoc_abort, 373 .upm_close = ehci_device_fs_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_fs_isoc_done, 376 }; 377 378 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 379 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 380 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 381 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 382 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 383 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 384 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 385 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 386 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 387 }; 388 389 int 390 ehci_init(ehci_softc_t *sc) 391 { 392 uint32_t vers, sparams, cparams, hcr; 393 u_int i; 394 usbd_status err; 395 ehci_soft_qh_t *sqh; 396 u_int ncomp; 397 398 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 399 #ifdef EHCI_DEBUG 400 theehci = sc; 401 #endif 402 403 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 404 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 405 cv_init(&sc->sc_softwake_cv, "ehciab"); 406 cv_init(&sc->sc_doorbell, "ehcidi"); 407 408 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 409 "ehcixfer", NULL, IPL_NONE, NULL, NULL, NULL); 410 411 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 412 ehci_doorbell, sc); 413 KASSERT(sc->sc_doorbell_si != NULL); 414 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 415 ehci_pcd, sc); 416 KASSERT(sc->sc_pcd_si != NULL); 417 418 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 419 420 vers = EREAD2(sc, EHCI_HCIVERSION); 421 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 422 vers >> 8, vers & 0xff); 423 424 sparams = EREAD4(sc, EHCI_HCSPARAMS); 425 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 426 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 427 ncomp = EHCI_HCS_N_CC(sparams); 428 if (ncomp != sc->sc_ncomp) { 429 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 430 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 431 #if NOHCI == 0 || NUHCI == 0 432 aprint_error("%s: ohci or uhci probably not configured\n", 433 device_xname(sc->sc_dev)); 434 #endif 435 if (ncomp < sc->sc_ncomp) 436 sc->sc_ncomp = ncomp; 437 } 438 if (sc->sc_ncomp > 0) { 439 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 440 aprint_normal("%s: companion controller%s, %d port%s each:", 441 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 442 EHCI_HCS_N_PCC(sparams), 443 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 444 for (i = 0; i < sc->sc_ncomp; i++) 445 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 446 aprint_normal("\n"); 447 } 448 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 449 cparams = EREAD4(sc, EHCI_HCCPARAMS); 450 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 451 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 452 453 if (EHCI_HCC_64BIT(cparams)) { 454 /* MUST clear segment register if 64 bit capable. */ 455 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 456 } 457 458 sc->sc_bus.ub_revision = USBREV_2_0; 459 sc->sc_bus.ub_usedma = true; 460 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 461 462 /* Reset the controller */ 463 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 464 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 465 usb_delay_ms(&sc->sc_bus, 1); 466 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 467 for (i = 0; i < 100; i++) { 468 usb_delay_ms(&sc->sc_bus, 1); 469 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 470 if (!hcr) 471 break; 472 } 473 if (hcr) { 474 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 475 return EIO; 476 } 477 if (sc->sc_vendor_init) 478 sc->sc_vendor_init(sc); 479 480 /* XXX need proper intr scheduling */ 481 sc->sc_rand = 96; 482 483 /* frame list size at default, read back what we got and use that */ 484 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 485 case 0: sc->sc_flsize = 1024; break; 486 case 1: sc->sc_flsize = 512; break; 487 case 2: sc->sc_flsize = 256; break; 488 case 3: return EIO; 489 } 490 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 491 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 492 if (err) 493 return err; 494 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 495 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 496 497 for (i = 0; i < sc->sc_flsize; i++) { 498 sc->sc_flist[i] = EHCI_NULL; 499 } 500 501 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 502 503 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 504 KM_SLEEP); 505 if (sc->sc_softitds == NULL) 506 return ENOMEM; 507 LIST_INIT(&sc->sc_freeitds); 508 LIST_INIT(&sc->sc_freesitds); 509 TAILQ_INIT(&sc->sc_intrhead); 510 511 /* Set up the bus struct. */ 512 sc->sc_bus.ub_methods = &ehci_bus_methods; 513 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 514 515 sc->sc_eintrs = EHCI_NORMAL_INTRS; 516 517 /* 518 * Allocate the interrupt dummy QHs. These are arranged to give poll 519 * intervals that are powers of 2 times 1ms. 520 */ 521 for (i = 0; i < EHCI_INTRQHS; i++) { 522 sqh = ehci_alloc_sqh(sc); 523 if (sqh == NULL) { 524 err = ENOMEM; 525 goto bad1; 526 } 527 sc->sc_islots[i].sqh = sqh; 528 } 529 for (i = 0; i < EHCI_INTRQHS; i++) { 530 sqh = sc->sc_islots[i].sqh; 531 if (i == 0) { 532 /* The last (1ms) QH terminates. */ 533 sqh->qh.qh_link = EHCI_NULL; 534 sqh->next = NULL; 535 } else { 536 /* Otherwise the next QH has half the poll interval */ 537 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 538 sqh->qh.qh_link = htole32(sqh->next->physaddr | 539 EHCI_LINK_QH); 540 } 541 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 542 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 543 sqh->qh.qh_curqtd = EHCI_NULL; 544 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 545 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 546 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 547 sqh->sqtd = NULL; 548 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 } 551 /* Point the frame list at the last level (128ms). */ 552 for (i = 0; i < sc->sc_flsize; i++) { 553 int j; 554 555 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 556 revbits[i & (EHCI_MAX_POLLRATE-1)]; 557 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 558 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 559 i)].sqh->physaddr); 560 } 561 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 562 BUS_DMASYNC_PREWRITE); 563 564 /* Allocate dummy QH that starts the async list. */ 565 sqh = ehci_alloc_sqh(sc); 566 if (sqh == NULL) { 567 err = ENOMEM; 568 goto bad1; 569 } 570 /* Fill the QH */ 571 sqh->qh.qh_endp = 572 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 573 sqh->qh.qh_link = 574 htole32(sqh->physaddr | EHCI_LINK_QH); 575 sqh->qh.qh_curqtd = EHCI_NULL; 576 sqh->next = NULL; 577 /* Fill the overlay qTD */ 578 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 579 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 580 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 581 sqh->sqtd = NULL; 582 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 584 #ifdef EHCI_DEBUG 585 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 586 ehci_dump_sqh(sqh); 587 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 588 #endif 589 590 /* Point to async list */ 591 sc->sc_async_head = sqh; 592 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 593 594 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 595 596 /* Turn on controller */ 597 EOWRITE4(sc, EHCI_USBCMD, 598 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 599 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 600 EHCI_CMD_ASE | 601 EHCI_CMD_PSE | 602 EHCI_CMD_RS); 603 604 /* Take over port ownership */ 605 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 606 607 for (i = 0; i < 100; i++) { 608 usb_delay_ms(&sc->sc_bus, 1); 609 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 610 if (!hcr) 611 break; 612 } 613 if (hcr) { 614 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 615 return EIO; 616 } 617 618 /* Enable interrupts */ 619 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 620 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 621 622 return 0; 623 624 #if 0 625 bad2: 626 ehci_free_sqh(sc, sc->sc_async_head); 627 #endif 628 bad1: 629 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 630 return err; 631 } 632 633 int 634 ehci_intr(void *v) 635 { 636 ehci_softc_t *sc = v; 637 int ret = 0; 638 639 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 640 641 if (sc == NULL) 642 return 0; 643 644 mutex_spin_enter(&sc->sc_intr_lock); 645 646 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 647 goto done; 648 649 /* If we get an interrupt while polling, then just ignore it. */ 650 if (sc->sc_bus.ub_usepolling) { 651 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 652 653 if (intrs) 654 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 655 USBHIST_LOGN(ehcidebug, 16, 656 "ignored interrupt while polling", 0, 0, 0, 0); 657 goto done; 658 } 659 660 ret = ehci_intr1(sc); 661 662 done: 663 mutex_spin_exit(&sc->sc_intr_lock); 664 return ret; 665 } 666 667 Static int 668 ehci_intr1(ehci_softc_t *sc) 669 { 670 uint32_t intrs, eintrs; 671 672 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 673 674 /* In case the interrupt occurs before initialization has completed. */ 675 if (sc == NULL) { 676 #ifdef DIAGNOSTIC 677 printf("ehci_intr1: sc == NULL\n"); 678 #endif 679 return 0; 680 } 681 682 KASSERT(mutex_owned(&sc->sc_intr_lock)); 683 684 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 685 if (!intrs) 686 return 0; 687 688 eintrs = intrs & sc->sc_eintrs; 689 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 690 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 691 if (!eintrs) 692 return 0; 693 694 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 695 if (eintrs & EHCI_STS_IAA) { 696 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 697 kpreempt_disable(); 698 KASSERT(sc->sc_doorbell_si != NULL); 699 softint_schedule(sc->sc_doorbell_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_IAA; 702 } 703 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 704 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 705 eintrs & EHCI_STS_INT ? 1 : 0, 706 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 707 usb_schedsoftintr(&sc->sc_bus); 708 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 709 } 710 if (eintrs & EHCI_STS_HSE) { 711 printf("%s: unrecoverable error, controller halted\n", 712 device_xname(sc->sc_dev)); 713 /* XXX what else */ 714 } 715 if (eintrs & EHCI_STS_PCD) { 716 kpreempt_disable(); 717 KASSERT(sc->sc_pcd_si != NULL); 718 softint_schedule(sc->sc_pcd_si); 719 kpreempt_enable(); 720 eintrs &= ~EHCI_STS_PCD; 721 } 722 723 if (eintrs != 0) { 724 /* Block unprocessed interrupts. */ 725 sc->sc_eintrs &= ~eintrs; 726 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 727 printf("%s: blocking intrs 0x%x\n", 728 device_xname(sc->sc_dev), eintrs); 729 } 730 731 return 1; 732 } 733 734 Static void 735 ehci_doorbell(void *addr) 736 { 737 ehci_softc_t *sc = addr; 738 739 mutex_enter(&sc->sc_lock); 740 cv_broadcast(&sc->sc_doorbell); 741 mutex_exit(&sc->sc_lock); 742 } 743 744 Static void 745 ehci_pcd(void *addr) 746 { 747 ehci_softc_t *sc = addr; 748 struct usbd_xfer *xfer; 749 u_char *p; 750 int i, m; 751 752 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 753 754 mutex_enter(&sc->sc_lock); 755 xfer = sc->sc_intrxfer; 756 757 if (xfer == NULL) { 758 /* Just ignore the change. */ 759 goto done; 760 } 761 762 p = xfer->ux_buf; 763 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 764 memset(p, 0, xfer->ux_length); 765 for (i = 1; i <= m; i++) { 766 /* Pick out CHANGE bits from the status reg. */ 767 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 768 p[i/8] |= 1 << (i%8); 769 if (i % 8 == 7) 770 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 771 p[i/8], 0, 0); 772 } 773 xfer->ux_actlen = xfer->ux_length; 774 xfer->ux_status = USBD_NORMAL_COMPLETION; 775 776 usb_transfer_complete(xfer); 777 778 done: 779 mutex_exit(&sc->sc_lock); 780 } 781 782 Static void 783 ehci_softintr(void *v) 784 { 785 struct usbd_bus *bus = v; 786 ehci_softc_t *sc = EHCI_BUS2SC(bus); 787 struct ehci_xfer *ex, *nextex; 788 789 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 790 791 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 792 793 /* 794 * The only explanation I can think of for why EHCI is as brain dead 795 * as UHCI interrupt-wise is that Intel was involved in both. 796 * An interrupt just tells us that something is done, we have no 797 * clue what, so we need to scan through all active transfers. :-( 798 */ 799 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 800 nextex = TAILQ_NEXT(ex, ex_next); 801 ehci_check_intr(sc, ex); 802 } 803 804 /* Schedule a callout to catch any dropped transactions. */ 805 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 806 !TAILQ_EMPTY(&sc->sc_intrhead)) 807 callout_reset(&sc->sc_tmo_intrlist, 808 hz, ehci_intrlist_timeout, sc); 809 810 if (sc->sc_softwake) { 811 sc->sc_softwake = 0; 812 cv_broadcast(&sc->sc_softwake_cv); 813 } 814 } 815 816 /* Check for an interrupt. */ 817 Static void 818 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 819 { 820 821 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 822 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 823 824 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 825 826 switch (ex->ex_type) { 827 case EX_CTRL: 828 case EX_BULK: 829 case EX_INTR: 830 ehci_check_qh_intr(sc, ex); 831 break; 832 case EX_ISOC: 833 ehci_check_itd_intr(sc, ex); 834 break; 835 case EX_FS_ISOC: 836 ehci_check_sitd_intr(sc, ex); 837 break; 838 default: 839 KASSERT(false); 840 } 841 842 return; 843 } 844 845 Static void 846 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 847 { 848 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 849 uint32_t status; 850 851 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 852 853 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 854 855 if (ex->ex_type == EX_CTRL) { 856 fsqtd = ex->ex_setup; 857 lsqtd = ex->ex_status; 858 } else { 859 fsqtd = ex->ex_sqtdstart; 860 lsqtd = ex->ex_sqtdend; 861 } 862 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 863 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 864 865 /* 866 * If the last TD is still active we need to check whether there 867 * is an error somewhere in the middle, or whether there was a 868 * short packet (SPD and not ACTIVE). 869 */ 870 usb_syncmem(&lsqtd->dma, 871 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 872 sizeof(lsqtd->qtd.qtd_status), 873 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 874 status = le32toh(lsqtd->qtd.qtd_status); 875 usb_syncmem(&lsqtd->dma, 876 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 877 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 878 if (status & EHCI_QTD_ACTIVE) { 879 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 880 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 881 usb_syncmem(&sqtd->dma, 882 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 883 sizeof(sqtd->qtd.qtd_status), 884 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 885 status = le32toh(sqtd->qtd.qtd_status); 886 usb_syncmem(&sqtd->dma, 887 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 888 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 889 /* If there's an active QTD the xfer isn't done. */ 890 if (status & EHCI_QTD_ACTIVE) 891 break; 892 /* Any kind of error makes the xfer done. */ 893 if (status & EHCI_QTD_HALTED) 894 goto done; 895 /* Handle short packets */ 896 if (EHCI_QTD_GET_BYTES(status) != 0) { 897 /* 898 * If we get here for a control transfer then 899 * we need to let the hardware complete the 900 * status phase. That is, we're not done 901 * quite yet. 902 * 903 * Otherwise, we're done. 904 */ 905 if (ex->ex_type == EX_CTRL) { 906 break; 907 } 908 goto done; 909 } 910 } 911 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 912 ex, ex->ex_sqtdstart, 0, 0); 913 #ifdef EHCI_DEBUG 914 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 915 0, 0); 916 ehci_dump_sqtds(ex->ex_sqtdstart); 917 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 918 0); 919 #endif 920 return; 921 } 922 done: 923 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 924 callout_stop(&ex->ex_xfer.ux_callout); 925 ehci_idone(ex); 926 } 927 928 Static void 929 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 930 { 931 ehci_soft_itd_t *itd; 932 int i; 933 934 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 935 936 KASSERT(mutex_owned(&sc->sc_lock)); 937 938 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 939 return; 940 941 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 942 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 943 944 itd = ex->ex_itdend; 945 946 /* 947 * check no active transfers in last itd, meaning we're finished 948 */ 949 950 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 951 sizeof(itd->itd.itd_ctl), 952 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 953 954 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 955 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 956 break; 957 } 958 959 if (i == EHCI_ITD_NUFRAMES) { 960 goto done; /* All 8 descriptors inactive, it's done */ 961 } 962 963 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 964 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 965 966 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 967 ex->ex_itdstart, 0, 0); 968 return; 969 done: 970 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 971 callout_stop(&ex->ex_xfer.ux_callout); 972 ehci_idone(ex); 973 } 974 975 void 976 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 977 { 978 ehci_soft_sitd_t *sitd; 979 980 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 981 982 KASSERT(mutex_owned(&sc->sc_lock)); 983 984 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 985 return; 986 987 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 988 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 989 990 sitd = ex->ex_sitdend; 991 992 /* 993 * check no active transfers in last sitd, meaning we're finished 994 */ 995 996 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 997 sizeof(sitd->sitd.sitd_trans), 998 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 999 1000 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1001 1002 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1003 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1004 1005 if (active) 1006 return; 1007 1008 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1009 callout_stop(&(ex->ex_xfer.ux_callout)); 1010 ehci_idone(ex); 1011 } 1012 1013 1014 Static void 1015 ehci_idone(struct ehci_xfer *ex) 1016 { 1017 struct usbd_xfer *xfer = &ex->ex_xfer; 1018 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1019 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1020 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1021 uint32_t status = 0, nstatus = 0; 1022 int actlen = 0; 1023 1024 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1025 1026 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1027 1028 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1029 1030 #ifdef DIAGNOSTIC 1031 #ifdef EHCI_DEBUG 1032 if (ex->ex_isdone) { 1033 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1034 ehci_dump_exfer(ex); 1035 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1036 } 1037 #endif 1038 KASSERT(!ex->ex_isdone); 1039 ex->ex_isdone = true; 1040 #endif 1041 1042 if (xfer->ux_status == USBD_CANCELLED || 1043 xfer->ux_status == USBD_TIMEOUT) { 1044 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1045 return; 1046 } 1047 1048 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1049 1050 /* The transfer is done, compute actual length and status. */ 1051 if (ex->ex_type == EX_ISOC) { 1052 /* HS isoc transfer */ 1053 1054 struct ehci_soft_itd *itd; 1055 int i, nframes, len, uframes; 1056 1057 nframes = 0; 1058 1059 #ifdef EHCI_DEBUG 1060 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1061 ehci_dump_itds(ex->ex_itdstart); 1062 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1063 #endif 1064 1065 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1066 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1067 1068 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1069 usb_syncmem(&itd->dma, 1070 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1071 sizeof(itd->itd.itd_ctl), 1072 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1073 1074 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1075 /* 1076 * XXX - driver didn't fill in the frame full 1077 * of uframes. This leads to scheduling 1078 * inefficiencies, but working around 1079 * this doubles complexity of tracking 1080 * an xfer. 1081 */ 1082 if (nframes >= xfer->ux_nframes) 1083 break; 1084 1085 status = le32toh(itd->itd.itd_ctl[i]); 1086 len = EHCI_ITD_GET_LEN(status); 1087 if (EHCI_ITD_GET_STATUS(status) != 0) 1088 len = 0; /*No valid data on error*/ 1089 1090 xfer->ux_frlengths[nframes++] = len; 1091 actlen += len; 1092 } 1093 usb_syncmem(&itd->dma, 1094 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1095 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1096 1097 if (nframes >= xfer->ux_nframes) 1098 break; 1099 } 1100 1101 xfer->ux_actlen = actlen; 1102 xfer->ux_status = USBD_NORMAL_COMPLETION; 1103 goto end; 1104 } else if (ex->ex_type == EX_FS_ISOC) { 1105 /* FS isoc transfer */ 1106 struct ehci_soft_sitd *sitd; 1107 int nframes, len; 1108 1109 nframes = 0; 1110 1111 for (sitd = ex->ex_sitdstart; sitd != NULL; 1112 sitd = sitd->xfer_next) { 1113 usb_syncmem(&sitd->dma, 1114 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1115 sizeof(sitd->sitd.sitd_trans), 1116 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1117 1118 /* 1119 * XXX - driver didn't fill in the frame full 1120 * of uframes. This leads to scheduling 1121 * inefficiencies, but working around 1122 * this doubles complexity of tracking 1123 * an xfer. 1124 */ 1125 if (nframes >= xfer->ux_nframes) 1126 break; 1127 1128 status = le32toh(sitd->sitd.sitd_trans); 1129 usb_syncmem(&sitd->dma, 1130 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1131 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1132 1133 len = EHCI_SITD_GET_LEN(status); 1134 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1135 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1136 /* No valid data on error */ 1137 len = xfer->ux_frlengths[nframes]; 1138 } 1139 1140 /* 1141 * frlengths[i]: # of bytes to send 1142 * len: # of bytes host didn't send 1143 */ 1144 xfer->ux_frlengths[nframes] -= len; 1145 /* frlengths[i]: # of bytes host sent */ 1146 actlen += xfer->ux_frlengths[nframes++]; 1147 1148 if (nframes >= xfer->ux_nframes) 1149 break; 1150 } 1151 1152 xfer->ux_actlen = actlen; 1153 xfer->ux_status = USBD_NORMAL_COMPLETION; 1154 goto end; 1155 } 1156 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1157 ex->ex_type == EX_BULK); 1158 1159 /* Continue processing xfers using queue heads */ 1160 if (ex->ex_type == EX_CTRL) { 1161 fsqtd = ex->ex_setup; 1162 lsqtd = ex->ex_status; 1163 } else { 1164 fsqtd = ex->ex_sqtdstart; 1165 lsqtd = ex->ex_sqtdend; 1166 } 1167 #ifdef EHCI_DEBUG 1168 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1169 ehci_dump_sqtds(fsqtd); 1170 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1171 #endif 1172 1173 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1174 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1175 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1176 nstatus = le32toh(sqtd->qtd.qtd_status); 1177 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1178 BUS_DMASYNC_PREREAD); 1179 if (nstatus & EHCI_QTD_ACTIVE) 1180 break; 1181 1182 status = nstatus; 1183 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1184 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1185 } 1186 1187 /* 1188 * If there are left over TDs we need to update the toggle. 1189 * The default pipe doesn't need it since control transfers 1190 * start the toggle at 0 every time. 1191 * For a short transfer we need to update the toggle for the missing 1192 * packets within the qTD. 1193 */ 1194 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1195 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1196 USBHIST_LOG(ehcidebug, 1197 "toggle update status=0x%08x nstatus=0x%08x", 1198 status, nstatus, 0, 0); 1199 #if 0 1200 ehci_dump_sqh(epipe->sqh); 1201 ehci_dump_sqtds(ex->ex_sqtdstart); 1202 #endif 1203 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1204 } 1205 1206 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1207 actlen, status, 0); 1208 xfer->ux_actlen = actlen; 1209 if (status & EHCI_QTD_HALTED) { 1210 #ifdef EHCI_DEBUG 1211 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1212 xfer->ux_pipe->up_dev->ud_addr, 1213 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1214 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1215 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1216 0, 0); 1217 USBHIST_LOG(ehcidebug, 1218 "active =%d halted=%d buferr=%d babble=%d", 1219 status & EHCI_QTD_ACTIVE ? 1 : 0, 1220 status & EHCI_QTD_HALTED ? 1 : 0, 1221 status & EHCI_QTD_BUFERR ? 1 : 0, 1222 status & EHCI_QTD_BABBLE ? 1 : 0); 1223 1224 USBHIST_LOG(ehcidebug, 1225 "xacterr=%d missed=%d split =%d ping =%d", 1226 status & EHCI_QTD_XACTERR ? 1 : 0, 1227 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1228 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1229 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1230 1231 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1232 ehci_dump_sqh(epipe->sqh); 1233 ehci_dump_sqtds(ex->ex_sqtdstart); 1234 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1235 #endif 1236 /* low&full speed has an extra error flag */ 1237 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1238 EHCI_QH_SPEED_HIGH) 1239 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1240 else 1241 status &= EHCI_QTD_STATERRS; 1242 if (status == 0) /* no other errors means a stall */ { 1243 xfer->ux_status = USBD_STALLED; 1244 } else { 1245 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1246 } 1247 /* XXX need to reset TT on missed microframe */ 1248 if (status & EHCI_QTD_MISSEDMICRO) { 1249 printf("%s: missed microframe, TT reset not " 1250 "implemented, hub might be inoperational\n", 1251 device_xname(sc->sc_dev)); 1252 } 1253 } else { 1254 xfer->ux_status = USBD_NORMAL_COMPLETION; 1255 } 1256 1257 end: 1258 /* 1259 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1260 * during this call, before methods->done is called: dma sync required 1261 * beforehand? 1262 */ 1263 usb_transfer_complete(xfer); 1264 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1265 } 1266 1267 /* 1268 * Wait here until controller claims to have an interrupt. 1269 * Then call ehci_intr and return. Use timeout to avoid waiting 1270 * too long. 1271 */ 1272 Static void 1273 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1274 { 1275 int timo; 1276 uint32_t intrs; 1277 1278 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1279 1280 xfer->ux_status = USBD_IN_PROGRESS; 1281 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1282 usb_delay_ms(&sc->sc_bus, 1); 1283 if (sc->sc_dying) 1284 break; 1285 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1286 sc->sc_eintrs; 1287 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1288 #ifdef EHCI_DEBUG 1289 if (ehcidebug > 15) 1290 ehci_dump_regs(sc); 1291 #endif 1292 if (intrs) { 1293 mutex_spin_enter(&sc->sc_intr_lock); 1294 ehci_intr1(sc); 1295 mutex_spin_exit(&sc->sc_intr_lock); 1296 if (xfer->ux_status != USBD_IN_PROGRESS) 1297 return; 1298 } 1299 } 1300 1301 /* Timeout */ 1302 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1303 xfer->ux_status = USBD_TIMEOUT; 1304 mutex_enter(&sc->sc_lock); 1305 usb_transfer_complete(xfer); 1306 mutex_exit(&sc->sc_lock); 1307 } 1308 1309 Static void 1310 ehci_poll(struct usbd_bus *bus) 1311 { 1312 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1313 1314 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1315 1316 #ifdef EHCI_DEBUG 1317 static int last; 1318 int new; 1319 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1320 if (new != last) { 1321 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1322 last = new; 1323 } 1324 #endif 1325 1326 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1327 mutex_spin_enter(&sc->sc_intr_lock); 1328 ehci_intr1(sc); 1329 mutex_spin_exit(&sc->sc_intr_lock); 1330 } 1331 } 1332 1333 void 1334 ehci_childdet(device_t self, device_t child) 1335 { 1336 struct ehci_softc *sc = device_private(self); 1337 1338 KASSERT(sc->sc_child == child); 1339 sc->sc_child = NULL; 1340 } 1341 1342 int 1343 ehci_detach(struct ehci_softc *sc, int flags) 1344 { 1345 int rv = 0; 1346 1347 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1348 1349 if (sc->sc_child != NULL) 1350 rv = config_detach(sc->sc_child, flags); 1351 1352 if (rv != 0) 1353 return rv; 1354 1355 callout_halt(&sc->sc_tmo_intrlist, NULL); 1356 callout_destroy(&sc->sc_tmo_intrlist); 1357 1358 /* XXX free other data structures XXX */ 1359 if (sc->sc_softitds) 1360 kmem_free(sc->sc_softitds, 1361 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1362 cv_destroy(&sc->sc_doorbell); 1363 cv_destroy(&sc->sc_softwake_cv); 1364 1365 #if 0 1366 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1367 1368 softint_disestablish(sc->sc_doorbell_si); 1369 softint_disestablish(sc->sc_pcd_si); 1370 1371 mutex_destroy(&sc->sc_lock); 1372 mutex_destroy(&sc->sc_intr_lock); 1373 #endif 1374 1375 pool_cache_destroy(sc->sc_xferpool); 1376 1377 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1378 1379 return rv; 1380 } 1381 1382 1383 int 1384 ehci_activate(device_t self, enum devact act) 1385 { 1386 struct ehci_softc *sc = device_private(self); 1387 1388 switch (act) { 1389 case DVACT_DEACTIVATE: 1390 sc->sc_dying = 1; 1391 return 0; 1392 default: 1393 return EOPNOTSUPP; 1394 } 1395 } 1396 1397 /* 1398 * Handle suspend/resume. 1399 * 1400 * We need to switch to polling mode here, because this routine is 1401 * called from an interrupt context. This is all right since we 1402 * are almost suspended anyway. 1403 * 1404 * Note that this power handler isn't to be registered directly; the 1405 * bus glue needs to call out to it. 1406 */ 1407 bool 1408 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1409 { 1410 ehci_softc_t *sc = device_private(dv); 1411 int i; 1412 uint32_t cmd, hcr; 1413 1414 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1415 1416 mutex_spin_enter(&sc->sc_intr_lock); 1417 sc->sc_bus.ub_usepolling++; 1418 mutex_spin_exit(&sc->sc_intr_lock); 1419 1420 for (i = 1; i <= sc->sc_noport; i++) { 1421 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1422 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1423 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1424 } 1425 1426 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1427 1428 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1429 EOWRITE4(sc, EHCI_USBCMD, cmd); 1430 1431 for (i = 0; i < 100; i++) { 1432 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1433 if (hcr == 0) 1434 break; 1435 1436 usb_delay_ms(&sc->sc_bus, 1); 1437 } 1438 if (hcr != 0) 1439 printf("%s: reset timeout\n", device_xname(dv)); 1440 1441 cmd &= ~EHCI_CMD_RS; 1442 EOWRITE4(sc, EHCI_USBCMD, cmd); 1443 1444 for (i = 0; i < 100; i++) { 1445 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1446 if (hcr == EHCI_STS_HCH) 1447 break; 1448 1449 usb_delay_ms(&sc->sc_bus, 1); 1450 } 1451 if (hcr != EHCI_STS_HCH) 1452 printf("%s: config timeout\n", device_xname(dv)); 1453 1454 mutex_spin_enter(&sc->sc_intr_lock); 1455 sc->sc_bus.ub_usepolling--; 1456 mutex_spin_exit(&sc->sc_intr_lock); 1457 1458 return true; 1459 } 1460 1461 bool 1462 ehci_resume(device_t dv, const pmf_qual_t *qual) 1463 { 1464 ehci_softc_t *sc = device_private(dv); 1465 int i; 1466 uint32_t cmd, hcr; 1467 1468 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1469 1470 /* restore things in case the bios sucks */ 1471 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1472 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1473 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1474 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1475 1476 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1477 1478 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1479 1480 hcr = 0; 1481 for (i = 1; i <= sc->sc_noport; i++) { 1482 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1483 if ((cmd & EHCI_PS_PO) == 0 && 1484 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1485 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1486 hcr = 1; 1487 } 1488 } 1489 1490 if (hcr) { 1491 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1492 1493 for (i = 1; i <= sc->sc_noport; i++) { 1494 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1495 if ((cmd & EHCI_PS_PO) == 0 && 1496 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1497 EOWRITE4(sc, EHCI_PORTSC(i), 1498 cmd & ~EHCI_PS_FPR); 1499 } 1500 } 1501 1502 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1503 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1504 1505 for (i = 0; i < 100; i++) { 1506 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1507 if (hcr != EHCI_STS_HCH) 1508 break; 1509 1510 usb_delay_ms(&sc->sc_bus, 1); 1511 } 1512 if (hcr == EHCI_STS_HCH) 1513 printf("%s: config timeout\n", device_xname(dv)); 1514 1515 return true; 1516 } 1517 1518 /* 1519 * Shut down the controller when the system is going down. 1520 */ 1521 bool 1522 ehci_shutdown(device_t self, int flags) 1523 { 1524 ehci_softc_t *sc = device_private(self); 1525 1526 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1527 1528 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1529 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1530 return true; 1531 } 1532 1533 Static struct usbd_xfer * 1534 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1535 { 1536 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1537 struct usbd_xfer *xfer; 1538 1539 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1540 if (xfer != NULL) { 1541 memset(xfer, 0, sizeof(struct ehci_xfer)); 1542 #ifdef DIAGNOSTIC 1543 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1544 ex->ex_isdone = true; 1545 xfer->ux_state = XFER_BUSY; 1546 #endif 1547 } 1548 return xfer; 1549 } 1550 1551 Static void 1552 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1553 { 1554 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1555 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1556 1557 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1558 xfer->ux_state); 1559 KASSERT(ex->ex_isdone); 1560 1561 #ifdef DIAGNOSTIC 1562 xfer->ux_state = XFER_FREE; 1563 #endif 1564 1565 pool_cache_put(sc->sc_xferpool, xfer); 1566 } 1567 1568 Static void 1569 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1570 { 1571 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1572 1573 *lock = &sc->sc_lock; 1574 } 1575 1576 Static void 1577 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1578 { 1579 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1580 1581 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1582 1583 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1584 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1585 #ifdef EHCI_DEBUG 1586 if (ehcidebug) 1587 usbd_dump_pipe(pipe); 1588 #endif 1589 epipe->nexttoggle = 0; 1590 } 1591 1592 Static void 1593 ehci_noop(struct usbd_pipe *pipe) 1594 { 1595 } 1596 1597 #ifdef EHCI_DEBUG 1598 /* 1599 * Unused function - this is meant to be called from a kernel 1600 * debugger. 1601 */ 1602 void 1603 ehci_dump(void) 1604 { 1605 ehci_softc_t *sc = theehci; 1606 int i; 1607 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1608 EOREAD4(sc, EHCI_USBCMD), 1609 EOREAD4(sc, EHCI_USBSTS), 1610 EOREAD4(sc, EHCI_USBINTR)); 1611 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1612 EOREAD4(sc, EHCI_FRINDEX), 1613 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1614 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1615 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1616 for (i = 1; i <= sc->sc_noport; i++) 1617 printf("port %d status=0x%08x\n", i, 1618 EOREAD4(sc, EHCI_PORTSC(i))); 1619 } 1620 1621 Static void 1622 ehci_dump_regs(ehci_softc_t *sc) 1623 { 1624 int i; 1625 1626 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1627 1628 USBHIST_LOG(ehcidebug, 1629 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1630 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1631 EOREAD4(sc, EHCI_USBINTR), 0); 1632 USBHIST_LOG(ehcidebug, 1633 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1634 "async = 0x%08x", 1635 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1636 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1637 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1638 for (i = 1; i <= sc->sc_noport; i += 2) { 1639 if (i == sc->sc_noport) { 1640 USBHIST_LOG(ehcidebug, 1641 "port %d status = 0x%08x", i, 1642 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1643 } else { 1644 USBHIST_LOG(ehcidebug, 1645 "port %d status = 0x%08x port %d status = 0x%08x", 1646 i, EOREAD4(sc, EHCI_PORTSC(i)), 1647 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1648 } 1649 } 1650 } 1651 1652 #ifdef EHCI_DEBUG 1653 #define ehci_dump_link(link, type) do { \ 1654 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1655 link, \ 1656 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1657 if (type) { \ 1658 USBHIST_LOG(ehcidebug, \ 1659 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1660 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1661 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1662 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1663 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1664 } \ 1665 } while(0) 1666 #else 1667 #define ehci_dump_link(link, type) 1668 #endif 1669 1670 Static void 1671 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1672 { 1673 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1674 int i; 1675 uint32_t stop = 0; 1676 1677 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1678 ehci_dump_sqtd(sqtd); 1679 usb_syncmem(&sqtd->dma, 1680 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1681 sizeof(sqtd->qtd), 1682 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1683 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1684 usb_syncmem(&sqtd->dma, 1685 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1686 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1687 } 1688 if (!stop) 1689 USBHIST_LOG(ehcidebug, 1690 "dump aborted, too many TDs", 0, 0, 0, 0); 1691 } 1692 1693 Static void 1694 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1695 { 1696 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1697 1698 usb_syncmem(&sqtd->dma, sqtd->offs, 1699 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1700 1701 USBHIST_LOGN(ehcidebug, 10, 1702 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1703 ehci_dump_qtd(&sqtd->qtd); 1704 1705 usb_syncmem(&sqtd->dma, sqtd->offs, 1706 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1707 } 1708 1709 Static void 1710 ehci_dump_qtd(ehci_qtd_t *qtd) 1711 { 1712 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1713 1714 #ifdef USBHIST 1715 uint32_t s = le32toh(qtd->qtd_status); 1716 #endif 1717 1718 USBHIST_LOGN(ehcidebug, 10, 1719 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1720 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1721 USBHIST_LOGN(ehcidebug, 10, 1722 " toggle = %d ioc = %d bytes = %#x " 1723 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1724 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1725 USBHIST_LOGN(ehcidebug, 10, 1726 " cerr = %d pid = %d stat = %x", 1727 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1728 0); 1729 USBHIST_LOGN(ehcidebug, 10, 1730 "active =%d halted=%d buferr=%d babble=%d", 1731 s & EHCI_QTD_ACTIVE ? 1 : 0, 1732 s & EHCI_QTD_HALTED ? 1 : 0, 1733 s & EHCI_QTD_BUFERR ? 1 : 0, 1734 s & EHCI_QTD_BABBLE ? 1 : 0); 1735 USBHIST_LOGN(ehcidebug, 10, 1736 "xacterr=%d missed=%d split =%d ping =%d", 1737 s & EHCI_QTD_XACTERR ? 1 : 0, 1738 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1739 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1740 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1741 USBHIST_LOGN(ehcidebug, 10, 1742 "buffer[0] = %#x buffer[1] = %#x " 1743 "buffer[2] = %#x buffer[3] = %#x", 1744 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1745 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1746 USBHIST_LOGN(ehcidebug, 10, 1747 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1748 } 1749 1750 Static void 1751 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1752 { 1753 #ifdef USBHIST 1754 ehci_qh_t *qh = &sqh->qh; 1755 ehci_link_t link; 1756 #endif 1757 uint32_t endp, endphub; 1758 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1759 1760 usb_syncmem(&sqh->dma, sqh->offs, 1761 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1762 1763 USBHIST_LOGN(ehcidebug, 10, 1764 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1765 link = le32toh(qh->qh_link); 1766 ehci_dump_link(link, true); 1767 1768 endp = le32toh(qh->qh_endp); 1769 USBHIST_LOGN(ehcidebug, 10, 1770 " endp = %#x", endp, 0, 0, 0); 1771 USBHIST_LOGN(ehcidebug, 10, 1772 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1773 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1774 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1775 USBHIST_LOGN(ehcidebug, 10, 1776 " dtc = %d hrecl = %d", 1777 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1778 USBHIST_LOGN(ehcidebug, 10, 1779 " ctl = %d nrl = %d mpl = %#x(%d)", 1780 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1781 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1782 1783 endphub = le32toh(qh->qh_endphub); 1784 USBHIST_LOGN(ehcidebug, 10, 1785 " endphub = %#x", endphub, 0, 0, 0); 1786 USBHIST_LOGN(ehcidebug, 10, 1787 " smask = 0x%02x cmask = 0x%02x", 1788 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1789 USBHIST_LOGN(ehcidebug, 10, 1790 " huba = 0x%02x port = %d mult = %d", 1791 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1792 EHCI_QH_GET_MULT(endphub), 0); 1793 1794 link = le32toh(qh->qh_curqtd); 1795 ehci_dump_link(link, false); 1796 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1797 ehci_dump_qtd(&qh->qh_qtd); 1798 1799 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1800 BUS_DMASYNC_PREREAD); 1801 } 1802 1803 Static void 1804 ehci_dump_itds(ehci_soft_itd_t *itd) 1805 { 1806 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1807 int i; 1808 uint32_t stop = 0; 1809 1810 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1811 ehci_dump_itd(itd); 1812 usb_syncmem(&itd->dma, 1813 itd->offs + offsetof(ehci_itd_t, itd_next), 1814 sizeof(itd->itd), 1815 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1816 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1817 usb_syncmem(&itd->dma, 1818 itd->offs + offsetof(ehci_itd_t, itd_next), 1819 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1820 } 1821 if (!stop) 1822 USBHIST_LOG(ehcidebug, "dump aborted, too many TDs", 0, 0, 0, 0); 1823 } 1824 1825 Static void 1826 ehci_dump_itd(struct ehci_soft_itd *itd) 1827 { 1828 ehci_isoc_trans_t t; 1829 ehci_isoc_bufr_ptr_t b, b2, b3; 1830 int i; 1831 1832 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1833 1834 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1835 0, 0); 1836 1837 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1838 t = le32toh(itd->itd.itd_ctl[i]); 1839 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1840 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1841 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1842 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1843 EHCI_ITD_GET_OFFS(t), 0); 1844 } 1845 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1846 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1847 USBHIST_LOG(ehcidebug, " %x", 1848 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1849 1850 b = le32toh(itd->itd.itd_bufr[0]); 1851 b2 = le32toh(itd->itd.itd_bufr[1]); 1852 b3 = le32toh(itd->itd.itd_bufr[2]); 1853 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1854 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1855 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1856 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1857 } 1858 1859 Static void 1860 ehci_dump_sitd(struct ehci_soft_itd *itd) 1861 { 1862 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1863 1864 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1865 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1866 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1867 itd->xfer_next, itd->physaddr, itd->slot, 0); 1868 } 1869 1870 Static void 1871 ehci_dump_exfer(struct ehci_xfer *ex) 1872 { 1873 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1874 1875 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1876 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1877 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1878 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1879 } 1880 #endif 1881 1882 Static usbd_status 1883 ehci_open(struct usbd_pipe *pipe) 1884 { 1885 struct usbd_device *dev = pipe->up_dev; 1886 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1887 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1888 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1889 uint8_t addr = dev->ud_addr; 1890 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1891 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1892 ehci_soft_qh_t *sqh; 1893 usbd_status err; 1894 int ival, speed, naks; 1895 int hshubaddr, hshubport; 1896 1897 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1898 1899 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1900 pipe, addr, ed->bEndpointAddress, rhaddr); 1901 1902 if (dev->ud_myhsport) { 1903 /* 1904 * When directly attached FS/LS device while doing embedded 1905 * transaction translations and we are the hub, set the hub 1906 * address to 0 (us). 1907 */ 1908 if (!(sc->sc_flags & EHCIF_ETTF) 1909 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1910 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1911 } else { 1912 hshubaddr = 0; 1913 } 1914 hshubport = dev->ud_myhsport->up_portno; 1915 } else { 1916 hshubaddr = 0; 1917 hshubport = 0; 1918 } 1919 1920 if (sc->sc_dying) 1921 return USBD_IOERROR; 1922 1923 /* toggle state needed for bulk endpoints */ 1924 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1925 1926 if (addr == rhaddr) { 1927 switch (ed->bEndpointAddress) { 1928 case USB_CONTROL_ENDPOINT: 1929 pipe->up_methods = &roothub_ctrl_methods; 1930 break; 1931 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1932 pipe->up_methods = &ehci_root_intr_methods; 1933 break; 1934 default: 1935 USBHIST_LOG(ehcidebug, 1936 "bad bEndpointAddress 0x%02x", 1937 ed->bEndpointAddress, 0, 0, 0); 1938 return USBD_INVAL; 1939 } 1940 return USBD_NORMAL_COMPLETION; 1941 } 1942 1943 /* XXX All this stuff is only valid for async. */ 1944 switch (dev->ud_speed) { 1945 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1946 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1947 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1948 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1949 } 1950 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1951 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1952 hshubaddr, hshubport, 0, 0); 1953 return USBD_INVAL; 1954 } 1955 1956 /* 1957 * For interrupt transfer, nak throttling must be disabled, but for 1958 * the other transfer type, nak throttling should be enabled from the 1959 * viewpoint that avoids the memory thrashing. 1960 */ 1961 naks = (xfertype == UE_INTERRUPT) ? 0 1962 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1963 1964 /* Allocate sqh for everything, save isoc xfers */ 1965 if (xfertype != UE_ISOCHRONOUS) { 1966 sqh = ehci_alloc_sqh(sc); 1967 if (sqh == NULL) 1968 return USBD_NOMEM; 1969 /* qh_link filled when the QH is added */ 1970 sqh->qh.qh_endp = htole32( 1971 EHCI_QH_SET_ADDR(addr) | 1972 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1973 EHCI_QH_SET_EPS(speed) | 1974 EHCI_QH_DTC | 1975 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1976 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1977 EHCI_QH_CTL : 0) | 1978 EHCI_QH_SET_NRL(naks) 1979 ); 1980 sqh->qh.qh_endphub = htole32( 1981 EHCI_QH_SET_MULT(1) | 1982 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1983 ); 1984 if (speed != EHCI_QH_SPEED_HIGH) 1985 sqh->qh.qh_endphub |= htole32( 1986 EHCI_QH_SET_PORT(hshubport) | 1987 EHCI_QH_SET_HUBA(hshubaddr) | 1988 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1989 ); 1990 sqh->qh.qh_curqtd = EHCI_NULL; 1991 /* Fill the overlay qTD */ 1992 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1993 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1994 sqh->qh.qh_qtd.qtd_status = htole32(0); 1995 1996 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1997 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1998 epipe->sqh = sqh; 1999 } else { 2000 sqh = NULL; 2001 } /*xfertype == UE_ISOC*/ 2002 2003 switch (xfertype) { 2004 case UE_CONTROL: 2005 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2006 0, &epipe->ctrl.reqdma); 2007 #ifdef EHCI_DEBUG 2008 if (err) 2009 printf("ehci_open: usb_allocmem()=%d\n", err); 2010 #endif 2011 if (err) 2012 goto bad; 2013 pipe->up_methods = &ehci_device_ctrl_methods; 2014 mutex_enter(&sc->sc_lock); 2015 ehci_add_qh(sc, sqh, sc->sc_async_head); 2016 mutex_exit(&sc->sc_lock); 2017 break; 2018 case UE_BULK: 2019 pipe->up_methods = &ehci_device_bulk_methods; 2020 mutex_enter(&sc->sc_lock); 2021 ehci_add_qh(sc, sqh, sc->sc_async_head); 2022 mutex_exit(&sc->sc_lock); 2023 break; 2024 case UE_INTERRUPT: 2025 pipe->up_methods = &ehci_device_intr_methods; 2026 ival = pipe->up_interval; 2027 if (ival == USBD_DEFAULT_INTERVAL) { 2028 if (speed == EHCI_QH_SPEED_HIGH) { 2029 if (ed->bInterval > 16) { 2030 /* 2031 * illegal with high-speed, but there 2032 * were documentation bugs in the spec, 2033 * so be generous 2034 */ 2035 ival = 256; 2036 } else 2037 ival = (1 << (ed->bInterval - 1)) / 8; 2038 } else 2039 ival = ed->bInterval; 2040 } 2041 err = ehci_device_setintr(sc, sqh, ival); 2042 if (err) 2043 goto bad; 2044 break; 2045 case UE_ISOCHRONOUS: 2046 if (speed == EHCI_QH_SPEED_HIGH) 2047 pipe->up_methods = &ehci_device_isoc_methods; 2048 else 2049 pipe->up_methods = &ehci_device_fs_isoc_methods; 2050 if (ed->bInterval == 0 || ed->bInterval > 16) { 2051 printf("ehci: opening pipe with invalid bInterval\n"); 2052 err = USBD_INVAL; 2053 goto bad; 2054 } 2055 if (UGETW(ed->wMaxPacketSize) == 0) { 2056 printf("ehci: zero length endpoint open request\n"); 2057 err = USBD_INVAL; 2058 goto bad; 2059 } 2060 epipe->isoc.next_frame = 0; 2061 epipe->isoc.cur_xfers = 0; 2062 break; 2063 default: 2064 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2065 err = USBD_INVAL; 2066 goto bad; 2067 } 2068 return USBD_NORMAL_COMPLETION; 2069 2070 bad: 2071 if (sqh != NULL) { 2072 mutex_enter(&sc->sc_lock); 2073 ehci_free_sqh(sc, sqh); 2074 mutex_exit(&sc->sc_lock); 2075 } 2076 return err; 2077 } 2078 2079 /* 2080 * Add an ED to the schedule. Called with USB lock held. 2081 */ 2082 Static void 2083 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2084 { 2085 2086 KASSERT(mutex_owned(&sc->sc_lock)); 2087 2088 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2089 2090 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2091 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2092 2093 sqh->next = head->next; 2094 sqh->qh.qh_link = head->qh.qh_link; 2095 2096 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2097 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2098 2099 head->next = sqh; 2100 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2101 2102 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2103 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2104 2105 #ifdef EHCI_DEBUG 2106 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2107 ehci_dump_sqh(sqh); 2108 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2109 #endif 2110 } 2111 2112 /* 2113 * Remove an ED from the schedule. Called with USB lock held. 2114 */ 2115 Static void 2116 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2117 { 2118 ehci_soft_qh_t *p; 2119 2120 KASSERT(mutex_owned(&sc->sc_lock)); 2121 2122 /* XXX */ 2123 for (p = head; p != NULL && p->next != sqh; p = p->next) 2124 ; 2125 if (p == NULL) 2126 panic("ehci_rem_qh: ED not found"); 2127 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2128 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2129 p->next = sqh->next; 2130 p->qh.qh_link = sqh->qh.qh_link; 2131 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2132 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2133 2134 ehci_sync_hc(sc); 2135 } 2136 2137 Static void 2138 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2139 { 2140 int i; 2141 uint32_t status; 2142 2143 /* Save toggle bit and ping status. */ 2144 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2145 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2146 status = sqh->qh.qh_qtd.qtd_status & 2147 htole32(EHCI_QTD_TOGGLE_MASK | 2148 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2149 /* Set HALTED to make hw leave it alone. */ 2150 sqh->qh.qh_qtd.qtd_status = 2151 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2152 usb_syncmem(&sqh->dma, 2153 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2154 sizeof(sqh->qh.qh_qtd.qtd_status), 2155 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2156 sqh->qh.qh_curqtd = 0; 2157 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2158 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2159 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2160 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2161 sqh->sqtd = sqtd; 2162 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2163 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2164 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2165 sqh->qh.qh_qtd.qtd_status = status; 2166 usb_syncmem(&sqh->dma, 2167 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2168 sizeof(sqh->qh.qh_qtd.qtd_status), 2169 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2170 } 2171 2172 /* 2173 * Ensure that the HC has released all references to the QH. We do this 2174 * by asking for a Async Advance Doorbell interrupt and then we wait for 2175 * the interrupt. 2176 * To make this easier we first obtain exclusive use of the doorbell. 2177 */ 2178 Static void 2179 ehci_sync_hc(ehci_softc_t *sc) 2180 { 2181 int error __diagused; 2182 2183 KASSERT(mutex_owned(&sc->sc_lock)); 2184 2185 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2186 2187 if (sc->sc_dying) { 2188 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2189 return; 2190 } 2191 /* ask for doorbell */ 2192 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2193 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2194 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2195 2196 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2197 2198 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2199 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2200 #ifdef DIAGNOSTIC 2201 if (error) 2202 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2203 #endif 2204 } 2205 2206 Static void 2207 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2208 { 2209 2210 KASSERT(mutex_owned(&sc->sc_lock)); 2211 2212 for (; itd != NULL; itd = itd->xfer_next) { 2213 struct ehci_soft_itd *prev = itd->frame_list.prev; 2214 2215 /* Unlink itd from hardware chain, or frame array */ 2216 if (prev == NULL) { /* We're at the table head */ 2217 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2218 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2219 usb_syncmem(&sc->sc_fldma, 2220 sizeof(ehci_link_t) * itd->slot, 2221 sizeof(ehci_link_t), 2222 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2223 2224 if (itd->frame_list.next != NULL) 2225 itd->frame_list.next->frame_list.prev = NULL; 2226 } else { 2227 /* XXX this part is untested... */ 2228 prev->itd.itd_next = itd->itd.itd_next; 2229 usb_syncmem(&itd->dma, 2230 itd->offs + offsetof(ehci_itd_t, itd_next), 2231 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2232 2233 prev->frame_list.next = itd->frame_list.next; 2234 if (itd->frame_list.next != NULL) 2235 itd->frame_list.next->frame_list.prev = prev; 2236 } 2237 } 2238 } 2239 2240 Static void 2241 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2242 { 2243 struct ehci_soft_itd *next; 2244 2245 mutex_enter(&sc->sc_lock); 2246 next = NULL; 2247 for (; itd != NULL; itd = next) { 2248 next = itd->xfer_next; 2249 ehci_free_itd_locked(sc, itd); 2250 } 2251 mutex_exit(&sc->sc_lock); 2252 } 2253 2254 Static void 2255 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2256 { 2257 2258 KASSERT(mutex_owned(&sc->sc_lock)); 2259 2260 for (; sitd != NULL; sitd = sitd->xfer_next) { 2261 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2262 2263 /* Unlink sitd from hardware chain, or frame array */ 2264 if (prev == NULL) { /* We're at the table head */ 2265 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2266 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2267 usb_syncmem(&sc->sc_fldma, 2268 sizeof(ehci_link_t) * sitd->slot, 2269 sizeof(ehci_link_t), 2270 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2271 2272 if (sitd->frame_list.next != NULL) 2273 sitd->frame_list.next->frame_list.prev = NULL; 2274 } else { 2275 /* XXX this part is untested... */ 2276 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2277 usb_syncmem(&sitd->dma, 2278 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2279 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2280 2281 prev->frame_list.next = sitd->frame_list.next; 2282 if (sitd->frame_list.next != NULL) 2283 sitd->frame_list.next->frame_list.prev = prev; 2284 } 2285 } 2286 } 2287 2288 Static void 2289 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2290 { 2291 2292 mutex_enter(&sc->sc_lock); 2293 struct ehci_soft_sitd *next = NULL; 2294 for (; sitd != NULL; sitd = next) { 2295 next = sitd->xfer_next; 2296 ehci_free_sitd_locked(sc, sitd); 2297 } 2298 mutex_exit(&sc->sc_lock); 2299 } 2300 2301 /***********/ 2302 2303 Static int 2304 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2305 void *buf, int buflen) 2306 { 2307 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2308 usb_hub_descriptor_t hubd; 2309 usb_port_status_t ps; 2310 uint16_t len, value, index; 2311 int l, totlen = 0; 2312 int port, i; 2313 uint32_t v; 2314 2315 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2316 2317 if (sc->sc_dying) 2318 return -1; 2319 2320 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2321 req->bmRequestType, req->bRequest, 0, 0); 2322 2323 len = UGETW(req->wLength); 2324 value = UGETW(req->wValue); 2325 index = UGETW(req->wIndex); 2326 2327 #define C(x,y) ((x) | ((y) << 8)) 2328 switch (C(req->bRequest, req->bmRequestType)) { 2329 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2330 if (len == 0) 2331 break; 2332 switch (value) { 2333 case C(0, UDESC_DEVICE): { 2334 usb_device_descriptor_t devd; 2335 totlen = min(buflen, sizeof(devd)); 2336 memcpy(&devd, buf, totlen); 2337 USETW(devd.idVendor, sc->sc_id_vendor); 2338 memcpy(buf, &devd, totlen); 2339 break; 2340 2341 } 2342 #define sd ((usb_string_descriptor_t *)buf) 2343 case C(1, UDESC_STRING): 2344 /* Vendor */ 2345 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2346 break; 2347 case C(2, UDESC_STRING): 2348 /* Product */ 2349 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2350 break; 2351 #undef sd 2352 default: 2353 /* default from usbroothub */ 2354 return buflen; 2355 } 2356 break; 2357 2358 /* Hub requests */ 2359 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2360 break; 2361 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2362 USBHIST_LOG(ehcidebug, 2363 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2364 0, 0); 2365 if (index < 1 || index > sc->sc_noport) { 2366 return -1; 2367 } 2368 port = EHCI_PORTSC(index); 2369 v = EOREAD4(sc, port); 2370 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2371 v &= ~EHCI_PS_CLEAR; 2372 switch (value) { 2373 case UHF_PORT_ENABLE: 2374 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2375 break; 2376 case UHF_PORT_SUSPEND: 2377 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2378 break; 2379 v &= ~EHCI_PS_SUSP; 2380 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2381 /* see USB2 spec ch. 7.1.7.7 */ 2382 usb_delay_ms(&sc->sc_bus, 20); 2383 EOWRITE4(sc, port, v); 2384 usb_delay_ms(&sc->sc_bus, 2); 2385 #ifdef DEBUG 2386 v = EOREAD4(sc, port); 2387 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2388 printf("ehci: resume failed: %x\n", v); 2389 #endif 2390 break; 2391 case UHF_PORT_POWER: 2392 if (sc->sc_hasppc) 2393 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2394 break; 2395 case UHF_PORT_TEST: 2396 USBHIST_LOG(ehcidebug, "clear port test " 2397 "%d", index, 0, 0, 0); 2398 break; 2399 case UHF_PORT_INDICATOR: 2400 USBHIST_LOG(ehcidebug, "clear port ind " 2401 "%d", index, 0, 0, 0); 2402 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2403 break; 2404 case UHF_C_PORT_CONNECTION: 2405 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2406 break; 2407 case UHF_C_PORT_ENABLE: 2408 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2409 break; 2410 case UHF_C_PORT_SUSPEND: 2411 /* how? */ 2412 break; 2413 case UHF_C_PORT_OVER_CURRENT: 2414 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2415 break; 2416 case UHF_C_PORT_RESET: 2417 sc->sc_isreset[index] = 0; 2418 break; 2419 default: 2420 return -1; 2421 } 2422 #if 0 2423 switch(value) { 2424 case UHF_C_PORT_CONNECTION: 2425 case UHF_C_PORT_ENABLE: 2426 case UHF_C_PORT_SUSPEND: 2427 case UHF_C_PORT_OVER_CURRENT: 2428 case UHF_C_PORT_RESET: 2429 default: 2430 break; 2431 } 2432 #endif 2433 break; 2434 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2435 if (len == 0) 2436 break; 2437 if ((value & 0xff) != 0) { 2438 return -1; 2439 } 2440 totlen = min(buflen, sizeof(hubd)); 2441 memcpy(&hubd, buf, totlen); 2442 hubd.bNbrPorts = sc->sc_noport; 2443 v = EOREAD4(sc, EHCI_HCSPARAMS); 2444 USETW(hubd.wHubCharacteristics, 2445 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2446 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2447 ? UHD_PORT_IND : 0); 2448 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2449 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2450 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2451 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2452 totlen = min(totlen, hubd.bDescLength); 2453 memcpy(buf, &hubd, totlen); 2454 break; 2455 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2456 if (len != 4) { 2457 return -1; 2458 } 2459 memset(buf, 0, len); /* ? XXX */ 2460 totlen = len; 2461 break; 2462 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2463 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2464 if (index < 1 || index > sc->sc_noport) { 2465 return -1; 2466 } 2467 if (len != 4) { 2468 return -1; 2469 } 2470 v = EOREAD4(sc, EHCI_PORTSC(index)); 2471 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2472 2473 i = UPS_HIGH_SPEED; 2474 if (sc->sc_flags & EHCIF_ETTF) { 2475 /* 2476 * If we are doing embedded transaction translation, 2477 * then directly attached LS/FS devices are reset by 2478 * the EHCI controller itself. PSPD is encoded 2479 * the same way as in USBSTATUS. 2480 */ 2481 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2482 } 2483 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2484 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2485 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2486 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2487 if (v & EHCI_PS_PR) i |= UPS_RESET; 2488 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2489 if (sc->sc_vendor_port_status) 2490 i = sc->sc_vendor_port_status(sc, v, i); 2491 USETW(ps.wPortStatus, i); 2492 i = 0; 2493 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2494 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2495 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2496 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2497 USETW(ps.wPortChange, i); 2498 totlen = min(len, sizeof(ps)); 2499 memcpy(buf, &ps, totlen); 2500 break; 2501 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2502 return -1; 2503 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2504 break; 2505 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2506 if (index < 1 || index > sc->sc_noport) { 2507 return -1; 2508 } 2509 port = EHCI_PORTSC(index); 2510 v = EOREAD4(sc, port); 2511 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2512 v &= ~EHCI_PS_CLEAR; 2513 switch(value) { 2514 case UHF_PORT_ENABLE: 2515 EOWRITE4(sc, port, v | EHCI_PS_PE); 2516 break; 2517 case UHF_PORT_SUSPEND: 2518 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2519 break; 2520 case UHF_PORT_RESET: 2521 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2522 if (EHCI_PS_IS_LOWSPEED(v) 2523 && sc->sc_ncomp > 0 2524 && !(sc->sc_flags & EHCIF_ETTF)) { 2525 /* 2526 * Low speed device on non-ETTF controller or 2527 * unaccompanied controller, give up ownership. 2528 */ 2529 ehci_disown(sc, index, 1); 2530 break; 2531 } 2532 /* Start reset sequence. */ 2533 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2534 EOWRITE4(sc, port, v | EHCI_PS_PR); 2535 /* Wait for reset to complete. */ 2536 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2537 if (sc->sc_dying) { 2538 return -1; 2539 } 2540 /* 2541 * An embedded transaction translator will automatically 2542 * terminate the reset sequence so there's no need to 2543 * it. 2544 */ 2545 v = EOREAD4(sc, port); 2546 if (v & EHCI_PS_PR) { 2547 /* Terminate reset sequence. */ 2548 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2549 /* Wait for HC to complete reset. */ 2550 usb_delay_ms(&sc->sc_bus, 2551 EHCI_PORT_RESET_COMPLETE); 2552 if (sc->sc_dying) { 2553 return -1; 2554 } 2555 } 2556 2557 v = EOREAD4(sc, port); 2558 USBHIST_LOG(ehcidebug, 2559 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2560 if (v & EHCI_PS_PR) { 2561 printf("%s: port reset timeout\n", 2562 device_xname(sc->sc_dev)); 2563 return USBD_TIMEOUT; 2564 } 2565 if (!(v & EHCI_PS_PE)) { 2566 /* Not a high speed device, give up ownership.*/ 2567 ehci_disown(sc, index, 0); 2568 break; 2569 } 2570 sc->sc_isreset[index] = 1; 2571 USBHIST_LOG(ehcidebug, 2572 "ehci port %d reset, status = 0x%08x", index, v, 0, 2573 0); 2574 break; 2575 case UHF_PORT_POWER: 2576 USBHIST_LOG(ehcidebug, 2577 "set port power %d (has PPC = %d)", index, 2578 sc->sc_hasppc, 0, 0); 2579 if (sc->sc_hasppc) 2580 EOWRITE4(sc, port, v | EHCI_PS_PP); 2581 break; 2582 case UHF_PORT_TEST: 2583 USBHIST_LOG(ehcidebug, "set port test %d", 2584 index, 0, 0, 0); 2585 break; 2586 case UHF_PORT_INDICATOR: 2587 USBHIST_LOG(ehcidebug, "set port ind %d", 2588 index, 0, 0, 0); 2589 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2590 break; 2591 default: 2592 return -1; 2593 } 2594 break; 2595 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2596 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2597 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2598 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2599 break; 2600 default: 2601 /* default from usbroothub */ 2602 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2603 buflen, 0, 0, 0); 2604 2605 return buflen; 2606 } 2607 2608 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2609 2610 return totlen; 2611 } 2612 2613 Static void 2614 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2615 { 2616 int port; 2617 uint32_t v; 2618 2619 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2620 2621 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2622 #ifdef DIAGNOSTIC 2623 if (sc->sc_npcomp != 0) { 2624 int i = (index-1) / sc->sc_npcomp; 2625 if (i >= sc->sc_ncomp) 2626 printf("%s: strange port\n", 2627 device_xname(sc->sc_dev)); 2628 else 2629 printf("%s: handing over %s speed device on " 2630 "port %d to %s\n", 2631 device_xname(sc->sc_dev), 2632 lowspeed ? "low" : "full", 2633 index, device_xname(sc->sc_comps[i])); 2634 } else { 2635 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2636 } 2637 #endif 2638 port = EHCI_PORTSC(index); 2639 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2640 EOWRITE4(sc, port, v | EHCI_PS_PO); 2641 } 2642 2643 Static usbd_status 2644 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2645 { 2646 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2647 usbd_status err; 2648 2649 /* Insert last in queue. */ 2650 mutex_enter(&sc->sc_lock); 2651 err = usb_insert_transfer(xfer); 2652 mutex_exit(&sc->sc_lock); 2653 if (err) 2654 return err; 2655 2656 /* Pipe isn't running, start first */ 2657 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2658 } 2659 2660 Static usbd_status 2661 ehci_root_intr_start(struct usbd_xfer *xfer) 2662 { 2663 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2664 2665 if (sc->sc_dying) 2666 return USBD_IOERROR; 2667 2668 mutex_enter(&sc->sc_lock); 2669 sc->sc_intrxfer = xfer; 2670 mutex_exit(&sc->sc_lock); 2671 2672 return USBD_IN_PROGRESS; 2673 } 2674 2675 /* Abort a root interrupt request. */ 2676 Static void 2677 ehci_root_intr_abort(struct usbd_xfer *xfer) 2678 { 2679 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2680 2681 KASSERT(mutex_owned(&sc->sc_lock)); 2682 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2683 2684 sc->sc_intrxfer = NULL; 2685 2686 xfer->ux_status = USBD_CANCELLED; 2687 usb_transfer_complete(xfer); 2688 } 2689 2690 /* Close the root pipe. */ 2691 Static void 2692 ehci_root_intr_close(struct usbd_pipe *pipe) 2693 { 2694 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2695 2696 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2697 2698 KASSERT(mutex_owned(&sc->sc_lock)); 2699 2700 sc->sc_intrxfer = NULL; 2701 } 2702 2703 Static void 2704 ehci_root_intr_done(struct usbd_xfer *xfer) 2705 { 2706 xfer->ux_hcpriv = NULL; 2707 } 2708 2709 /************************/ 2710 2711 Static ehci_soft_qh_t * 2712 ehci_alloc_sqh(ehci_softc_t *sc) 2713 { 2714 ehci_soft_qh_t *sqh; 2715 usbd_status err; 2716 int i, offs; 2717 usb_dma_t dma; 2718 2719 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2720 2721 mutex_enter(&sc->sc_lock); 2722 if (sc->sc_freeqhs == NULL) { 2723 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2724 mutex_exit(&sc->sc_lock); 2725 2726 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2727 EHCI_PAGE_SIZE, &dma); 2728 #ifdef EHCI_DEBUG 2729 if (err) 2730 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2731 #endif 2732 if (err) 2733 return NULL; 2734 2735 mutex_enter(&sc->sc_lock); 2736 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2737 offs = i * EHCI_SQH_SIZE; 2738 sqh = KERNADDR(&dma, offs); 2739 sqh->physaddr = DMAADDR(&dma, offs); 2740 sqh->dma = dma; 2741 sqh->offs = offs; 2742 sqh->next = sc->sc_freeqhs; 2743 sc->sc_freeqhs = sqh; 2744 } 2745 } 2746 sqh = sc->sc_freeqhs; 2747 sc->sc_freeqhs = sqh->next; 2748 mutex_exit(&sc->sc_lock); 2749 2750 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2751 sqh->next = NULL; 2752 return sqh; 2753 } 2754 2755 Static void 2756 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2757 { 2758 KASSERT(mutex_owned(&sc->sc_lock)); 2759 2760 sqh->next = sc->sc_freeqhs; 2761 sc->sc_freeqhs = sqh; 2762 } 2763 2764 Static ehci_soft_qtd_t * 2765 ehci_alloc_sqtd(ehci_softc_t *sc) 2766 { 2767 ehci_soft_qtd_t *sqtd = NULL; 2768 usbd_status err; 2769 int i, offs; 2770 usb_dma_t dma; 2771 2772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2773 2774 mutex_enter(&sc->sc_lock); 2775 if (sc->sc_freeqtds == NULL) { 2776 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2777 mutex_exit(&sc->sc_lock); 2778 2779 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2780 EHCI_PAGE_SIZE, &dma); 2781 #ifdef EHCI_DEBUG 2782 if (err) 2783 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2784 #endif 2785 if (err) 2786 goto done; 2787 2788 mutex_enter(&sc->sc_lock); 2789 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2790 offs = i * EHCI_SQTD_SIZE; 2791 sqtd = KERNADDR(&dma, offs); 2792 sqtd->physaddr = DMAADDR(&dma, offs); 2793 sqtd->dma = dma; 2794 sqtd->offs = offs; 2795 2796 sqtd->nextqtd = sc->sc_freeqtds; 2797 sc->sc_freeqtds = sqtd; 2798 } 2799 } 2800 2801 sqtd = sc->sc_freeqtds; 2802 sc->sc_freeqtds = sqtd->nextqtd; 2803 mutex_exit(&sc->sc_lock); 2804 2805 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2806 sqtd->nextqtd = NULL; 2807 sqtd->xfer = NULL; 2808 2809 done: 2810 return sqtd; 2811 } 2812 2813 Static void 2814 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2815 { 2816 2817 mutex_enter(&sc->sc_lock); 2818 sqtd->nextqtd = sc->sc_freeqtds; 2819 sc->sc_freeqtds = sqtd; 2820 mutex_exit(&sc->sc_lock); 2821 } 2822 2823 Static usbd_status 2824 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2825 int alen, int rd, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2826 { 2827 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2828 ehci_soft_qtd_t *next, *cur; 2829 ehci_physaddr_t nextphys; 2830 uint32_t qtdstatus; 2831 int len, curlen, mps; 2832 int i, tog; 2833 int pages, pageoffs; 2834 size_t curoffs; 2835 vaddr_t va, va_offs; 2836 usb_dma_t *dma = &xfer->ux_dmabuf; 2837 uint16_t flags = xfer->ux_flags; 2838 paddr_t a; 2839 2840 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2841 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2842 2843 ASSERT_SLEEPABLE(); 2844 KASSERT(sp); 2845 KASSERT(alen != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2846 2847 len = alen; 2848 qtdstatus = EHCI_QTD_ACTIVE | 2849 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2850 EHCI_QTD_SET_CERR(3) 2851 ; 2852 2853 size_t nsqtd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 2854 nsqtd += ((len + EHCI_QTD_MAXTRANSFER - 1) / EHCI_QTD_MAXTRANSFER); 2855 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2856 KM_SLEEP); 2857 exfer->ex_nsqtd = nsqtd; 2858 2859 mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2860 cur = ehci_alloc_sqtd(sc); 2861 *sp = cur; 2862 if (cur == NULL) 2863 goto nomem; 2864 2865 curoffs = 0; 2866 for (size_t j = 0;;) { 2867 KASSERT(j < nsqtd); 2868 exfer->ex_sqtds[j++] = cur; 2869 2870 /* The EHCI hardware can handle at most 5 pages. */ 2871 va = (vaddr_t)KERNADDR(dma, curoffs); 2872 va_offs = EHCI_PAGE_OFFSET(va); 2873 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2874 /* we can handle it in this QTD */ 2875 curlen = len - curoffs; 2876 } else { 2877 /* must use multiple TDs, fill as much as possible. */ 2878 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2879 2880 /* the length must be a multiple of the max size */ 2881 curlen -= curlen % mps; 2882 USBHIST_LOG(ehcidebug, "multiple QTDs, curlen=%d", 2883 curlen, 0, 0, 0); 2884 KASSERT(curlen != 0); 2885 } 2886 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", len, 2887 curlen, curoffs, 0); 2888 2889 /* 2890 * Allocate another transfer if there's more data left, 2891 * or if force last short transfer flag is set and we're 2892 * allocating a multiple of the max packet size. 2893 */ 2894 2895 if (curoffs + curlen != len || 2896 ((curlen % mps) == 0 && !rd && curlen != 0 && 2897 (flags & USBD_FORCE_SHORT_XFER))) { 2898 next = ehci_alloc_sqtd(sc); 2899 if (next == NULL) 2900 goto nomem; 2901 nextphys = htole32(next->physaddr); 2902 } else { 2903 next = NULL; 2904 nextphys = EHCI_NULL; 2905 } 2906 2907 /* Find number of pages we'll be using, insert dma addresses */ 2908 pages = EHCI_NPAGES(curlen); 2909 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2910 pageoffs = EHCI_PAGE(curoffs); 2911 for (i = 0; i < pages; i++) { 2912 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2913 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2914 /* Cast up to avoid compiler warnings */ 2915 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2916 } 2917 2918 /* First buffer pointer requires a page offset to start at */ 2919 cur->qtd.qtd_buffer[0] |= htole32(va_offs); 2920 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2921 cur->qtd.qtd_status = htole32(qtdstatus); 2922 cur->nextqtd = next; 2923 cur->xfer = xfer; 2924 cur->bufoff = curoffs; 2925 cur->tdlen = curlen; 2926 cur->len = 0; 2927 2928 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2929 curoffs, curoffs + curlen, 0, 0); 2930 2931 /* 2932 * adjust the toggle based on the number of packets in this 2933 * qtd 2934 */ 2935 if (((curlen + mps - 1) / mps) & 1) { 2936 tog ^= 1; 2937 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2938 } 2939 if (next == NULL) 2940 break; 2941 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2942 if (len) 2943 curoffs += curlen; 2944 cur = next; 2945 } 2946 if (ep) 2947 *ep = cur; 2948 2949 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", *sp, cur, 0, 0); 2950 2951 return USBD_NORMAL_COMPLETION; 2952 2953 nomem: 2954 ehci_free_sqtds(sc, exfer); 2955 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2956 return USBD_NOMEM; 2957 } 2958 2959 Static void 2960 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2961 { 2962 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2963 USBHIST_LOG(ehcidebug, "exfer=%p", exfer, 0, 0, 0); 2964 2965 mutex_enter(&sc->sc_lock); 2966 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2967 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2968 2969 if (sqtd == NULL) 2970 break; 2971 2972 sqtd->nextqtd = sc->sc_freeqtds; 2973 sc->sc_freeqtds = sqtd->nextqtd; 2974 } 2975 mutex_exit(&sc->sc_lock); 2976 } 2977 2978 Static void 2979 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2980 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2981 { 2982 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2983 ehci_soft_qtd_t *sqtd, *prev; 2984 int tog = *toggle; 2985 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2986 int len = length; 2987 size_t i; 2988 2989 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2990 USBHIST_LOG(ehcidebug, "xfer=%p len %d isread %d toggle %d", xfer, 2991 len, isread, *toggle); 2992 2993 sqtd = prev = NULL; 2994 for (i = 0; i < exfer->ex_nsqtd; i++, prev = sqtd) { 2995 sqtd = exfer->ex_sqtds[i]; 2996 vaddr_t va = (vaddr_t)KERNADDR(&xfer->ux_dmabuf, sqtd->bufoff); 2997 sqtd->len = sqtd->tdlen; 2998 if (len < sqtd->len) { 2999 sqtd->len = len; 3000 } 3001 3002 USBHIST_LOG(ehcidebug, "sqtd[%d]=%p prev %p len %d", i, sqtd, 3003 prev, sqtd->len); 3004 3005 if (prev) { 3006 prev->nextqtd = sqtd; 3007 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3008 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3009 } 3010 usb_syncmem(&sqtd->dma, 3011 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3012 sizeof(sqtd->qtd.qtd_status), 3013 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3014 usb_syncmem(&sqtd->dma, 3015 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3016 sizeof(sqtd->qtd.qtd_buffer[0]), 3017 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3018 3019 sqtd->qtd.qtd_buffer[0] &= ~htole32(EHCI_PAGE_MASK); 3020 sqtd->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3021 /* Reset ... */ 3022 sqtd->qtd.qtd_status &= ~htole32( 3023 EHCI_QTD_STATUS_MASK | 3024 EHCI_QTD_PID_MASK | 3025 EHCI_QTD_CERR_MASK | 3026 EHCI_QTD_C_PAGE_MASK | 3027 EHCI_QTD_BYTES_MASK | 3028 EHCI_QTD_TOGGLE_MASK); 3029 sqtd->qtd.qtd_status |= htole32( 3030 EHCI_QTD_ACTIVE | 3031 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3032 EHCI_QTD_SET_BYTES(sqtd->len) | 3033 EHCI_QTD_SET_CERR(3) | 3034 EHCI_QTD_SET_TOGGLE(tog)); 3035 3036 usb_syncmem(&sqtd->dma, 3037 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3038 sizeof(sqtd->qtd.qtd_status), 3039 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3040 usb_syncmem(&sqtd->dma, 3041 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3042 sizeof(sqtd->qtd.qtd_buffer[0]), 3043 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3044 3045 if (((sqtd->len + mps - 1) / mps) & 1) { 3046 tog ^= 1; 3047 } 3048 3049 len -= sqtd->len; 3050 if (len == 0) 3051 break; 3052 } 3053 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu i %zu", 3054 xfer, length, len, mps, exfer->ex_nsqtd, i); 3055 3056 if (i < exfer->ex_nsqtd) { 3057 /* 3058 * The full allocation chain wasn't used, so we need to 3059 * terminate it. 3060 */ 3061 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3062 } 3063 *lsqtd = sqtd; 3064 *toggle = tog; 3065 } 3066 3067 Static ehci_soft_itd_t * 3068 ehci_alloc_itd(ehci_softc_t *sc) 3069 { 3070 struct ehci_soft_itd *itd, *freeitd; 3071 usbd_status err; 3072 usb_dma_t dma; 3073 3074 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3075 3076 mutex_enter(&sc->sc_lock); 3077 3078 freeitd = LIST_FIRST(&sc->sc_freeitds); 3079 if (freeitd == NULL) { 3080 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3081 mutex_exit(&sc->sc_lock); 3082 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3083 EHCI_PAGE_SIZE, &dma); 3084 3085 if (err) { 3086 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 0); 3087 return NULL; 3088 } 3089 mutex_enter(&sc->sc_lock); 3090 3091 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3092 int offs = i * EHCI_ITD_SIZE; 3093 itd = KERNADDR(&dma, offs); 3094 itd->physaddr = DMAADDR(&dma, offs); 3095 itd->dma = dma; 3096 itd->offs = offs; 3097 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3098 } 3099 freeitd = LIST_FIRST(&sc->sc_freeitds); 3100 } 3101 3102 itd = freeitd; 3103 LIST_REMOVE(itd, free_list); 3104 mutex_exit(&sc->sc_lock); 3105 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3106 3107 itd->frame_list.next = NULL; 3108 itd->frame_list.prev = NULL; 3109 itd->xfer_next = NULL; 3110 itd->slot = 0; 3111 3112 return itd; 3113 } 3114 3115 Static ehci_soft_sitd_t * 3116 ehci_alloc_sitd(ehci_softc_t *sc) 3117 { 3118 struct ehci_soft_sitd *sitd, *freesitd; 3119 usbd_status err; 3120 int i, offs; 3121 usb_dma_t dma; 3122 3123 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3124 3125 mutex_enter(&sc->sc_lock); 3126 freesitd = LIST_FIRST(&sc->sc_freesitds); 3127 if (freesitd == NULL) { 3128 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3129 mutex_exit(&sc->sc_lock); 3130 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3131 EHCI_PAGE_SIZE, &dma); 3132 3133 if (err) { 3134 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 3135 0); 3136 return NULL; 3137 } 3138 3139 mutex_enter(&sc->sc_lock); 3140 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3141 offs = i * EHCI_SITD_SIZE; 3142 sitd = KERNADDR(&dma, offs); 3143 sitd->physaddr = DMAADDR(&dma, offs); 3144 sitd->dma = dma; 3145 sitd->offs = offs; 3146 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3147 } 3148 freesitd = LIST_FIRST(&sc->sc_freesitds); 3149 } 3150 3151 sitd = freesitd; 3152 LIST_REMOVE(sitd, free_list); 3153 mutex_exit(&sc->sc_lock); 3154 3155 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3156 3157 sitd->frame_list.next = NULL; 3158 sitd->frame_list.prev = NULL; 3159 sitd->xfer_next = NULL; 3160 sitd->slot = 0; 3161 3162 return sitd; 3163 } 3164 3165 /****************/ 3166 3167 /* 3168 * Close a reqular pipe. 3169 * Assumes that there are no pending transactions. 3170 */ 3171 Static void 3172 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3173 { 3174 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3175 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3176 ehci_soft_qh_t *sqh = epipe->sqh; 3177 3178 KASSERT(mutex_owned(&sc->sc_lock)); 3179 3180 ehci_rem_qh(sc, sqh, head); 3181 ehci_free_sqh(sc, epipe->sqh); 3182 } 3183 3184 /* 3185 * Abort a device request. 3186 * If this routine is called at splusb() it guarantees that the request 3187 * will be removed from the hardware scheduling and that the callback 3188 * for it will be called with USBD_CANCELLED status. 3189 * It's impossible to guarantee that the requested transfer will not 3190 * have happened since the hardware runs concurrently. 3191 * If the transaction has already happened we rely on the ordinary 3192 * interrupt processing to process it. 3193 * XXX This is most probably wrong. 3194 * XXXMRG this doesn't make sense anymore. 3195 */ 3196 Static void 3197 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3198 { 3199 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3200 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3201 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3202 ehci_soft_qh_t *sqh = epipe->sqh; 3203 ehci_soft_qtd_t *sqtd; 3204 ehci_physaddr_t cur; 3205 uint32_t qhstatus; 3206 int hit; 3207 int wake; 3208 3209 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3210 3211 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3212 3213 KASSERT(mutex_owned(&sc->sc_lock)); 3214 ASSERT_SLEEPABLE(); 3215 3216 if (sc->sc_dying) { 3217 /* If we're dying, just do the software part. */ 3218 xfer->ux_status = status; /* make software ignore it */ 3219 callout_stop(&xfer->ux_callout); 3220 usb_transfer_complete(xfer); 3221 return; 3222 } 3223 3224 /* 3225 * If an abort is already in progress then just wait for it to 3226 * complete and return. 3227 */ 3228 if (xfer->ux_hcflags & UXFER_ABORTING) { 3229 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3230 #ifdef DIAGNOSTIC 3231 if (status == USBD_TIMEOUT) 3232 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3233 #endif 3234 /* Override the status which might be USBD_TIMEOUT. */ 3235 xfer->ux_status = status; 3236 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3237 0, 0, 0, 0); 3238 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3239 while (xfer->ux_hcflags & UXFER_ABORTING) 3240 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3241 return; 3242 } 3243 xfer->ux_hcflags |= UXFER_ABORTING; 3244 3245 /* 3246 * Step 1: Make interrupt routine and hardware ignore xfer. 3247 */ 3248 xfer->ux_status = status; /* make software ignore it */ 3249 callout_stop(&xfer->ux_callout); 3250 3251 usb_syncmem(&sqh->dma, 3252 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3253 sizeof(sqh->qh.qh_qtd.qtd_status), 3254 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3255 qhstatus = sqh->qh.qh_qtd.qtd_status; 3256 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3257 usb_syncmem(&sqh->dma, 3258 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3259 sizeof(sqh->qh.qh_qtd.qtd_status), 3260 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3261 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3262 usb_syncmem(&sqtd->dma, 3263 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3264 sizeof(sqtd->qtd.qtd_status), 3265 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3266 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3267 usb_syncmem(&sqtd->dma, 3268 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3269 sizeof(sqtd->qtd.qtd_status), 3270 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3271 if (sqtd == exfer->ex_sqtdend) 3272 break; 3273 } 3274 3275 /* 3276 * Step 2: Wait until we know hardware has finished any possible 3277 * use of the xfer. Also make sure the soft interrupt routine 3278 * has run. 3279 */ 3280 ehci_sync_hc(sc); 3281 sc->sc_softwake = 1; 3282 usb_schedsoftintr(&sc->sc_bus); 3283 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3284 3285 /* 3286 * Step 3: Remove any vestiges of the xfer from the hardware. 3287 * The complication here is that the hardware may have executed 3288 * beyond the xfer we're trying to abort. So as we're scanning 3289 * the TDs of this xfer we check if the hardware points to 3290 * any of them. 3291 */ 3292 3293 usb_syncmem(&sqh->dma, 3294 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3295 sizeof(sqh->qh.qh_curqtd), 3296 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3297 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3298 hit = 0; 3299 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3300 hit |= cur == sqtd->physaddr; 3301 if (sqtd == exfer->ex_sqtdend) 3302 break; 3303 } 3304 sqtd = sqtd->nextqtd; 3305 /* Zap curqtd register if hardware pointed inside the xfer. */ 3306 if (hit && sqtd != NULL) { 3307 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3308 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3309 usb_syncmem(&sqh->dma, 3310 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3311 sizeof(sqh->qh.qh_curqtd), 3312 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3313 sqh->qh.qh_qtd.qtd_status = qhstatus; 3314 usb_syncmem(&sqh->dma, 3315 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3316 sizeof(sqh->qh.qh_qtd.qtd_status), 3317 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3318 } else { 3319 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3320 usb_syncmem(&sqh->dma, 3321 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3322 sizeof(sqh->qh.qh_curqtd), 3323 BUS_DMASYNC_PREREAD); 3324 } 3325 3326 /* 3327 * Step 4: Execute callback. 3328 */ 3329 #ifdef DIAGNOSTIC 3330 exfer->ex_isdone = true; 3331 #endif 3332 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3333 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3334 usb_transfer_complete(xfer); 3335 if (wake) { 3336 cv_broadcast(&xfer->ux_hccv); 3337 } 3338 3339 KASSERT(mutex_owned(&sc->sc_lock)); 3340 } 3341 3342 Static void 3343 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3344 { 3345 ehci_isoc_trans_t trans_status; 3346 struct ehci_xfer *exfer; 3347 ehci_softc_t *sc; 3348 struct ehci_soft_itd *itd; 3349 struct ehci_soft_sitd *sitd; 3350 int i, wake; 3351 3352 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3353 3354 exfer = EHCI_XFER2EXFER(xfer); 3355 sc = EHCI_XFER2SC(xfer); 3356 3357 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3358 3359 KASSERT(mutex_owned(&sc->sc_lock)); 3360 3361 if (sc->sc_dying) { 3362 xfer->ux_status = status; 3363 callout_stop(&xfer->ux_callout); 3364 usb_transfer_complete(xfer); 3365 return; 3366 } 3367 3368 if (xfer->ux_hcflags & UXFER_ABORTING) { 3369 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3370 3371 #ifdef DIAGNOSTIC 3372 if (status == USBD_TIMEOUT) 3373 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3374 #endif 3375 3376 xfer->ux_status = status; 3377 USBHIST_LOG(ehcidebug, 3378 "waiting for abort to finish", 0, 0, 0, 0); 3379 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3380 while (xfer->ux_hcflags & UXFER_ABORTING) 3381 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3382 goto done; 3383 } 3384 xfer->ux_hcflags |= UXFER_ABORTING; 3385 3386 xfer->ux_status = status; 3387 callout_stop(&xfer->ux_callout); 3388 3389 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3390 for (itd = exfer->ex_itdstart; itd != NULL; 3391 itd = itd->xfer_next) { 3392 usb_syncmem(&itd->dma, 3393 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3394 sizeof(itd->itd.itd_ctl), 3395 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3396 3397 for (i = 0; i < 8; i++) { 3398 trans_status = le32toh(itd->itd.itd_ctl[i]); 3399 trans_status &= ~EHCI_ITD_ACTIVE; 3400 itd->itd.itd_ctl[i] = htole32(trans_status); 3401 } 3402 3403 usb_syncmem(&itd->dma, 3404 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3405 sizeof(itd->itd.itd_ctl), 3406 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3407 } 3408 } else { 3409 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3410 sitd = sitd->xfer_next) { 3411 usb_syncmem(&sitd->dma, 3412 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3413 sizeof(sitd->sitd.sitd_buffer), 3414 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3415 3416 trans_status = le32toh(sitd->sitd.sitd_trans); 3417 trans_status &= ~EHCI_SITD_ACTIVE; 3418 sitd->sitd.sitd_trans = htole32(trans_status); 3419 3420 usb_syncmem(&sitd->dma, 3421 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3422 sizeof(sitd->sitd.sitd_buffer), 3423 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3424 } 3425 } 3426 3427 sc->sc_softwake = 1; 3428 usb_schedsoftintr(&sc->sc_bus); 3429 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3430 3431 #ifdef DIAGNOSTIC 3432 exfer->ex_isdone = true; 3433 #endif 3434 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3435 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3436 usb_transfer_complete(xfer); 3437 if (wake) { 3438 cv_broadcast(&xfer->ux_hccv); 3439 } 3440 3441 done: 3442 KASSERT(mutex_owned(&sc->sc_lock)); 3443 return; 3444 } 3445 3446 Static void 3447 ehci_timeout(void *addr) 3448 { 3449 struct usbd_xfer *xfer = addr; 3450 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3451 struct usbd_pipe *pipe = xfer->ux_pipe; 3452 struct usbd_device *dev = pipe->up_dev; 3453 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3454 3455 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3456 3457 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3458 #ifdef EHCI_DEBUG 3459 if (ehcidebug > 1) 3460 usbd_dump_pipe(pipe); 3461 #endif 3462 3463 if (sc->sc_dying) { 3464 mutex_enter(&sc->sc_lock); 3465 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3466 mutex_exit(&sc->sc_lock); 3467 return; 3468 } 3469 3470 /* Execute the abort in a process context. */ 3471 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3472 USB_TASKQ_MPSAFE); 3473 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3474 } 3475 3476 Static void 3477 ehci_timeout_task(void *addr) 3478 { 3479 struct usbd_xfer *xfer = addr; 3480 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3481 3482 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3483 3484 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3485 3486 mutex_enter(&sc->sc_lock); 3487 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3488 mutex_exit(&sc->sc_lock); 3489 } 3490 3491 /************************/ 3492 3493 Static int 3494 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3495 { 3496 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3497 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3498 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3499 usb_device_request_t *req = &xfer->ux_request; 3500 ehci_soft_qtd_t *setup, *status, *next; 3501 int isread = req->bmRequestType & UT_READ; 3502 int len = xfer->ux_bufsize; 3503 int err; 3504 3505 exfer->ex_type = EX_CTRL; 3506 exfer->ex_status = NULL; 3507 exfer->ex_data = NULL; 3508 exfer->ex_setup = ehci_alloc_sqtd(sc); 3509 if (exfer->ex_setup == NULL) { 3510 err = ENOMEM; 3511 goto bad1; 3512 } 3513 exfer->ex_status = ehci_alloc_sqtd(sc); 3514 if (exfer->ex_status == NULL) { 3515 err = ENOMEM; 3516 goto bad2; 3517 } 3518 setup = exfer->ex_setup; 3519 status = exfer->ex_status; 3520 exfer->ex_nsqtd = 0; 3521 next = status; 3522 /* Set up data transaction */ 3523 if (len != 0) { 3524 ehci_soft_qtd_t *end; 3525 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3526 &exfer->ex_data, &end); 3527 if (err) 3528 goto bad3; 3529 next = exfer->ex_data; 3530 } 3531 3532 /* Clear toggle */ 3533 setup->qtd.qtd_status = htole32( 3534 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3535 EHCI_QTD_SET_TOGGLE(0) | 3536 EHCI_QTD_SET_BYTES(sizeof(*req)) 3537 ); 3538 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3539 setup->qtd.qtd_buffer_hi[0] = 0; 3540 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3541 setup->nextqtd = next; 3542 setup->xfer = xfer; 3543 setup->tdlen = setup->len = sizeof(*req); 3544 3545 status->qtd.qtd_status = htole32( 3546 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3547 EHCI_QTD_SET_TOGGLE(1) | 3548 EHCI_QTD_IOC 3549 ); 3550 status->qtd.qtd_buffer[0] = 0; 3551 status->qtd.qtd_buffer_hi[0] = 0; 3552 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3553 status->nextqtd = NULL; 3554 status->xfer = xfer; 3555 status->tdlen = status->len = 0; 3556 3557 return 0; 3558 bad3: 3559 ehci_free_sqtd(sc, exfer->ex_status); 3560 bad2: 3561 ehci_free_sqtd(sc, exfer->ex_setup); 3562 bad1: 3563 return err; 3564 } 3565 3566 Static void 3567 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3568 { 3569 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3570 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3571 3572 KASSERT(ex->ex_type == EX_CTRL); 3573 3574 ehci_free_sqtd(sc, ex->ex_setup); 3575 ehci_free_sqtd(sc, ex->ex_status); 3576 ehci_free_sqtds(sc, ex); 3577 if (ex->ex_nsqtd) 3578 kmem_free(ex->ex_sqtds, 3579 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3580 } 3581 3582 Static usbd_status 3583 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3584 { 3585 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3586 usbd_status err; 3587 3588 /* Insert last in queue. */ 3589 mutex_enter(&sc->sc_lock); 3590 err = usb_insert_transfer(xfer); 3591 mutex_exit(&sc->sc_lock); 3592 if (err) 3593 return err; 3594 3595 /* Pipe isn't running, start first */ 3596 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3597 } 3598 3599 Static usbd_status 3600 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3601 { 3602 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3603 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3604 usb_device_request_t *req = &xfer->ux_request; 3605 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3606 ehci_soft_qtd_t *setup, *status, *next; 3607 ehci_soft_qh_t *sqh; 3608 3609 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3610 3611 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3612 3613 if (sc->sc_dying) 3614 return USBD_IOERROR; 3615 3616 const int isread = req->bmRequestType & UT_READ; 3617 const int len = UGETW(req->wLength); 3618 3619 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3620 "wValue=0x%04x, wIndex=0x%04x", 3621 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3622 UGETW(req->wIndex)); 3623 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3624 len, epipe->pipe.up_dev->ud_addr, 3625 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3626 3627 sqh = epipe->sqh; 3628 3629 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3630 "address QH %" __PRIuBIT " pipe %d\n", 3631 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3632 epipe->pipe.up_dev->ud_addr); 3633 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3634 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3635 "MPS QH %" __PRIuBIT " pipe %d\n", 3636 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3637 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3638 3639 setup = exfer->ex_setup; 3640 status = exfer->ex_status; 3641 3642 USBHIST_LOG(ehcidebug, "setup %p status %p data %p", 3643 setup, status, exfer->ex_data, 0); 3644 KASSERTMSG(setup != NULL && status != NULL, 3645 "Failed memory allocation, setup %p status %p", 3646 setup, status); 3647 3648 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3649 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3650 3651 /* Clear toggle */ 3652 setup->qtd.qtd_status &= ~htole32( 3653 EHCI_QTD_STATUS_MASK | 3654 EHCI_QTD_BYTES_MASK | 3655 EHCI_QTD_TOGGLE_MASK | 3656 EHCI_QTD_CERR_MASK 3657 ); 3658 setup->qtd.qtd_status |= htole32( 3659 EHCI_QTD_ACTIVE | 3660 EHCI_QTD_SET_CERR(3) | 3661 EHCI_QTD_SET_TOGGLE(0) | 3662 EHCI_QTD_SET_BYTES(sizeof(*req)) 3663 ); 3664 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3665 setup->qtd.qtd_buffer_hi[0] = 0; 3666 3667 next = status; 3668 status->qtd.qtd_status &= ~htole32( 3669 EHCI_QTD_STATUS_MASK | 3670 EHCI_QTD_PID_MASK | 3671 EHCI_QTD_BYTES_MASK | 3672 EHCI_QTD_TOGGLE_MASK | 3673 EHCI_QTD_CERR_MASK 3674 ); 3675 status->qtd.qtd_status |= htole32( 3676 EHCI_QTD_ACTIVE | 3677 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3678 EHCI_QTD_SET_CERR(3) | 3679 EHCI_QTD_SET_TOGGLE(1) | 3680 EHCI_QTD_SET_BYTES(0) | 3681 EHCI_QTD_IOC 3682 ); 3683 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3684 3685 KASSERT(exfer->ex_isdone); 3686 #ifdef DIAGNOSTIC 3687 exfer->ex_isdone = false; 3688 #endif 3689 3690 /* Set up data transaction */ 3691 if (len != 0) { 3692 ehci_soft_qtd_t *end; 3693 3694 /* Start toggle at 1. */ 3695 int toggle = 1; 3696 next = exfer->ex_data; 3697 KASSERTMSG(next != NULL, "Failed memory allocation"); 3698 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3699 end->nextqtd = status; 3700 end->qtd.qtd_next = end->qtd.qtd_altnext = 3701 htole32(status->physaddr); 3702 3703 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3704 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3705 3706 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3707 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3708 } 3709 3710 setup->nextqtd = next; 3711 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3712 3713 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3714 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3715 3716 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3717 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3718 3719 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3720 3721 #ifdef EHCI_DEBUG 3722 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3723 ehci_dump_sqh(sqh); 3724 ehci_dump_sqtds(setup); 3725 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3726 #endif 3727 3728 mutex_enter(&sc->sc_lock); 3729 3730 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3731 ehci_set_qh_qtd(sqh, setup); 3732 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3733 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3734 ehci_timeout, xfer); 3735 } 3736 ehci_add_intr_list(sc, exfer); 3737 xfer->ux_status = USBD_IN_PROGRESS; 3738 mutex_exit(&sc->sc_lock); 3739 3740 #if 0 3741 #ifdef EHCI_DEBUG 3742 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3743 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3744 // delay(10000); 3745 ehci_dump_regs(sc); 3746 ehci_dump_sqh(sc->sc_async_head); 3747 ehci_dump_sqh(sqh); 3748 ehci_dump_sqtds(setup); 3749 #endif 3750 #endif 3751 3752 if (sc->sc_bus.ub_usepolling) 3753 ehci_waitintr(sc, xfer); 3754 3755 return USBD_IN_PROGRESS; 3756 } 3757 3758 Static void 3759 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3760 { 3761 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3762 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3763 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3764 usb_device_request_t *req = &xfer->ux_request; 3765 int len = UGETW(req->wLength); 3766 int rd = req->bmRequestType & UT_READ; 3767 3768 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3769 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3770 3771 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3772 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3773 3774 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3775 ehci_del_intr_list(sc, ex); /* remove from active list */ 3776 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3777 BUS_DMASYNC_POSTWRITE); 3778 if (len) 3779 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3780 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3781 } 3782 3783 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3784 } 3785 3786 /* Abort a device control request. */ 3787 Static void 3788 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3789 { 3790 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3791 3792 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3793 ehci_abort_xfer(xfer, USBD_CANCELLED); 3794 } 3795 3796 /* Close a device control pipe. */ 3797 Static void 3798 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3799 { 3800 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3801 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3802 3803 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3804 3805 KASSERT(mutex_owned(&sc->sc_lock)); 3806 3807 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3808 3809 ehci_close_pipe(pipe, sc->sc_async_head); 3810 } 3811 3812 /* 3813 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3814 * qTD status, or miss signalling occasionally under heavy load. If the host 3815 * machine is too fast, we we can miss transaction completion - when we scan 3816 * the active list the transaction still seems to be active. This generally 3817 * exhibits itself as a umass stall that never recovers. 3818 * 3819 * We work around this behaviour by setting up this callback after any softintr 3820 * that completes with transactions still pending, giving us another chance to 3821 * check for completion after the writeback has taken place. 3822 */ 3823 Static void 3824 ehci_intrlist_timeout(void *arg) 3825 { 3826 ehci_softc_t *sc = arg; 3827 3828 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3829 3830 usb_schedsoftintr(&sc->sc_bus); 3831 } 3832 3833 /************************/ 3834 3835 Static int 3836 ehci_device_bulk_init(struct usbd_xfer *xfer) 3837 { 3838 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3839 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3840 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3841 int endpt = ed->bEndpointAddress; 3842 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3843 int len = xfer->ux_bufsize; 3844 int err = 0; 3845 3846 exfer->ex_type = EX_BULK; 3847 exfer->ex_nsqtd = 0; 3848 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3849 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 3850 3851 return err; 3852 } 3853 3854 Static void 3855 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3856 { 3857 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3858 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3859 3860 KASSERT(ex->ex_type == EX_BULK); 3861 3862 ehci_free_sqtds(sc, ex); 3863 if (ex->ex_nsqtd) 3864 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3865 } 3866 3867 Static usbd_status 3868 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3869 { 3870 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3871 usbd_status err; 3872 3873 /* Insert last in queue. */ 3874 mutex_enter(&sc->sc_lock); 3875 err = usb_insert_transfer(xfer); 3876 mutex_exit(&sc->sc_lock); 3877 if (err) 3878 return err; 3879 3880 /* Pipe isn't running, start first */ 3881 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3882 } 3883 3884 Static usbd_status 3885 ehci_device_bulk_start(struct usbd_xfer *xfer) 3886 { 3887 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3888 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3889 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3890 ehci_soft_qh_t *sqh; 3891 ehci_soft_qtd_t *end; 3892 int len, isread, endpt; 3893 3894 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3895 3896 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3897 xfer, xfer->ux_length, xfer->ux_flags, 0); 3898 3899 if (sc->sc_dying) 3900 return USBD_IOERROR; 3901 3902 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3903 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3904 3905 len = xfer->ux_length; 3906 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3907 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3908 sqh = epipe->sqh; 3909 3910 KASSERT(exfer->ex_isdone); 3911 #ifdef DIAGNOSTIC 3912 exfer->ex_isdone = false; 3913 #endif 3914 3915 /* Take lock here to protect nexttoggle */ 3916 mutex_enter(&sc->sc_lock); 3917 3918 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3919 3920 exfer->ex_sqtdend = end; 3921 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3922 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3923 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3924 3925 #ifdef EHCI_DEBUG 3926 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3927 ehci_dump_sqh(sqh); 3928 ehci_dump_sqtds(exfer->ex_sqtdstart); 3929 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3930 #endif 3931 3932 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3933 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3934 3935 /* also does usb_syncmem(sqh) */ 3936 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3937 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3938 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3939 ehci_timeout, xfer); 3940 } 3941 ehci_add_intr_list(sc, exfer); 3942 xfer->ux_status = USBD_IN_PROGRESS; 3943 mutex_exit(&sc->sc_lock); 3944 3945 #if 0 3946 #ifdef EHCI_DEBUG 3947 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3948 // delay(10000); 3949 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3950 ehci_dump_regs(sc); 3951 #if 0 3952 printf("async_head:\n"); 3953 ehci_dump_sqh(sc->sc_async_head); 3954 #endif 3955 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3956 ehci_dump_sqh(sqh); 3957 ehci_dump_sqtds(exfer->ex_sqtdstart); 3958 #endif 3959 #endif 3960 3961 if (sc->sc_bus.ub_usepolling) 3962 ehci_waitintr(sc, xfer); 3963 3964 return USBD_IN_PROGRESS; 3965 } 3966 3967 Static void 3968 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3969 { 3970 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3971 3972 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3973 ehci_abort_xfer(xfer, USBD_CANCELLED); 3974 } 3975 3976 /* 3977 * Close a device bulk pipe. 3978 */ 3979 Static void 3980 ehci_device_bulk_close(struct usbd_pipe *pipe) 3981 { 3982 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3983 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3984 3985 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3986 3987 KASSERT(mutex_owned(&sc->sc_lock)); 3988 3989 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3990 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3991 ehci_close_pipe(pipe, sc->sc_async_head); 3992 } 3993 3994 Static void 3995 ehci_device_bulk_done(struct usbd_xfer *xfer) 3996 { 3997 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3998 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3999 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4000 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4001 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4002 4003 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4004 4005 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4006 0, 0); 4007 4008 KASSERT(mutex_owned(&sc->sc_lock)); 4009 4010 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4011 ehci_del_intr_list(sc, ex); /* remove from active list */ 4012 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4013 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4014 } 4015 4016 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 4017 } 4018 4019 /************************/ 4020 4021 Static usbd_status 4022 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4023 { 4024 struct ehci_soft_islot *isp; 4025 int islot, lev; 4026 4027 /* Find a poll rate that is large enough. */ 4028 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4029 if (EHCI_ILEV_IVAL(lev) <= ival) 4030 break; 4031 4032 /* Pick an interrupt slot at the right level. */ 4033 /* XXX could do better than picking at random */ 4034 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4035 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4036 4037 sqh->islot = islot; 4038 isp = &sc->sc_islots[islot]; 4039 mutex_enter(&sc->sc_lock); 4040 ehci_add_qh(sc, sqh, isp->sqh); 4041 mutex_exit(&sc->sc_lock); 4042 4043 return USBD_NORMAL_COMPLETION; 4044 } 4045 4046 4047 Static int 4048 ehci_device_intr_init(struct usbd_xfer *xfer) 4049 { 4050 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4051 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4052 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4053 int endpt = ed->bEndpointAddress; 4054 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4055 int len = xfer->ux_bufsize; 4056 int err; 4057 4058 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4059 4060 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4061 xfer->ux_flags, 0); 4062 4063 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4064 KASSERT(len != 0); 4065 4066 exfer->ex_type = EX_INTR; 4067 exfer->ex_nsqtd = 0; 4068 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4069 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 4070 4071 return err; 4072 } 4073 4074 Static void 4075 ehci_device_intr_fini(struct usbd_xfer *xfer) 4076 { 4077 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4078 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4079 4080 KASSERT(ex->ex_type == EX_BULK); 4081 4082 ehci_free_sqtds(sc, ex); 4083 if (ex->ex_nsqtd) 4084 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4085 } 4086 4087 Static usbd_status 4088 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4089 { 4090 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4091 usbd_status err; 4092 4093 /* Insert last in queue. */ 4094 mutex_enter(&sc->sc_lock); 4095 err = usb_insert_transfer(xfer); 4096 mutex_exit(&sc->sc_lock); 4097 if (err) 4098 return err; 4099 4100 /* 4101 * Pipe isn't running (otherwise err would be USBD_INPROG), 4102 * so start it first. 4103 */ 4104 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4105 } 4106 4107 Static usbd_status 4108 ehci_device_intr_start(struct usbd_xfer *xfer) 4109 { 4110 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4111 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4112 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4113 ehci_soft_qtd_t *end; 4114 ehci_soft_qh_t *sqh; 4115 int len, isread, endpt; 4116 4117 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4118 4119 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4120 xfer->ux_flags, 0); 4121 4122 if (sc->sc_dying) 4123 return USBD_IOERROR; 4124 4125 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4126 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4127 4128 len = xfer->ux_length; 4129 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4130 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4131 sqh = epipe->sqh; 4132 4133 KASSERT(exfer->ex_isdone); 4134 #ifdef DIAGNOSTIC 4135 exfer->ex_isdone = false; 4136 #endif 4137 4138 /* Take lock to protect nexttoggle */ 4139 mutex_enter(&sc->sc_lock); 4140 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4141 4142 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4143 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4144 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4145 exfer->ex_sqtdend = end; 4146 4147 #ifdef EHCI_DEBUG 4148 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 4149 ehci_dump_sqh(sqh); 4150 ehci_dump_sqtds(exfer->ex_sqtdstart); 4151 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 4152 #endif 4153 4154 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4155 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4156 4157 /* also does usb_syncmem(sqh) */ 4158 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4159 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4160 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4161 ehci_timeout, xfer); 4162 } 4163 ehci_add_intr_list(sc, exfer); 4164 xfer->ux_status = USBD_IN_PROGRESS; 4165 mutex_exit(&sc->sc_lock); 4166 4167 #if 0 4168 #ifdef EHCI_DEBUG 4169 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4170 // delay(10000); 4171 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4172 ehci_dump_regs(sc); 4173 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4174 ehci_dump_sqh(sqh); 4175 ehci_dump_sqtds(exfer->ex_sqtdstart); 4176 #endif 4177 #endif 4178 4179 if (sc->sc_bus.ub_usepolling) 4180 ehci_waitintr(sc, xfer); 4181 4182 return USBD_IN_PROGRESS; 4183 } 4184 4185 Static void 4186 ehci_device_intr_abort(struct usbd_xfer *xfer) 4187 { 4188 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4189 4190 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4191 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4192 4193 /* 4194 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4195 * async doorbell. That's dependent on the async list, wheras 4196 * intr xfers are periodic, should not use this? 4197 */ 4198 ehci_abort_xfer(xfer, USBD_CANCELLED); 4199 } 4200 4201 Static void 4202 ehci_device_intr_close(struct usbd_pipe *pipe) 4203 { 4204 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4205 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4206 struct ehci_soft_islot *isp; 4207 4208 KASSERT(mutex_owned(&sc->sc_lock)); 4209 4210 isp = &sc->sc_islots[epipe->sqh->islot]; 4211 ehci_close_pipe(pipe, isp->sqh); 4212 } 4213 4214 Static void 4215 ehci_device_intr_done(struct usbd_xfer *xfer) 4216 { 4217 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4218 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4219 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4220 ehci_soft_qh_t *sqh; 4221 int len, isread, endpt; 4222 4223 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4224 4225 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4226 0, 0); 4227 4228 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4229 4230 if (xfer->ux_pipe->up_repeat) { 4231 4232 KASSERT(exfer->ex_isdone); 4233 #ifdef DIAGNOSTIC 4234 exfer->ex_isdone = false; 4235 #endif 4236 4237 len = xfer->ux_length; 4238 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4239 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4240 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4241 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4242 sqh = epipe->sqh; 4243 4244 ehci_soft_qtd_t *end; 4245 ehci_reset_sqtd_chain(sc, xfer, len, isread, 4246 &epipe->nexttoggle, &end); 4247 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4248 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4249 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4250 4251 exfer->ex_sqtdend = end; 4252 4253 /* also does usb_syncmem(sqh) */ 4254 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4255 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4256 callout_reset(&xfer->ux_callout, 4257 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4258 } 4259 4260 xfer->ux_status = USBD_IN_PROGRESS; 4261 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4262 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4263 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4264 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4265 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4266 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4267 } 4268 } 4269 4270 /************************/ 4271 Static int 4272 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4273 { 4274 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4275 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4276 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4277 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4278 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4279 int i, k, frames; 4280 u_int huba, dir; 4281 int err; 4282 4283 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4284 4285 start = NULL; 4286 sitd = NULL; 4287 4288 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", xfer, xfer->ux_length, 4289 xfer->ux_flags, 0); 4290 4291 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4292 KASSERT(xfer->ux_nframes != 0); 4293 KASSERT(exfer->ex_isdone); 4294 4295 exfer->ex_type = EX_FS_ISOC; 4296 /* 4297 * Step 1: Allocate and initialize sitds. 4298 */ 4299 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4300 if (i > 16 || i == 0) { 4301 /* Spec page 271 says intervals > 16 are invalid */ 4302 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4303 4304 return EINVAL; 4305 } 4306 4307 frames = xfer->ux_nframes; 4308 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4309 sitd = ehci_alloc_sitd(sc); 4310 if (sitd == NULL) { 4311 err = ENOMEM; 4312 goto fail; 4313 } 4314 4315 if (prev) 4316 prev->xfer_next = sitd; 4317 else 4318 start = sitd; 4319 4320 huba = dev->ud_myhsport->up_parent->ud_addr; 4321 4322 #if 0 4323 if (sc->sc_flags & EHCIF_FREESCALE) { 4324 // Set hub address to 0 if embedded TT is used. 4325 if (huba == sc->sc_addr) 4326 huba = 0; 4327 } 4328 #endif 4329 4330 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4331 dir = UE_GET_DIR(k) ? 1 : 0; 4332 sitd->sitd.sitd_endp = 4333 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4334 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4335 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4336 EHCI_SITD_SET_HUBA(huba) | 4337 EHCI_SITD_SET_DIR(dir)); 4338 4339 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4340 } /* End of frame */ 4341 4342 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4343 4344 stop = sitd; 4345 stop->xfer_next = NULL; 4346 exfer->ex_sitdstart = start; 4347 exfer->ex_sitdend = stop; 4348 4349 return 0; 4350 4351 fail: 4352 mutex_enter(&sc->sc_lock); 4353 ehci_soft_sitd_t *next; 4354 for (sitd = start; sitd; sitd = next) { 4355 next = sitd->xfer_next; 4356 ehci_free_sitd_locked(sc, sitd); 4357 } 4358 mutex_exit(&sc->sc_lock); 4359 4360 return err; 4361 } 4362 4363 Static void 4364 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4365 { 4366 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4367 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4368 4369 KASSERT(ex->ex_type == EX_FS_ISOC); 4370 4371 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4372 } 4373 4374 Static usbd_status 4375 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4376 { 4377 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4378 usbd_status err; 4379 4380 mutex_enter(&sc->sc_lock); 4381 err = usb_insert_transfer(xfer); 4382 mutex_exit(&sc->sc_lock); 4383 4384 if (err && err != USBD_IN_PROGRESS) 4385 return err; 4386 4387 return ehci_device_fs_isoc_start(xfer); 4388 } 4389 4390 Static usbd_status 4391 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4392 { 4393 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4394 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4395 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4396 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4397 ehci_soft_sitd_t *sitd; 4398 usb_dma_t *dma_buf; 4399 int i, j, k, frames; 4400 int offs, total_length; 4401 int frindex; 4402 u_int dir; 4403 4404 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4405 4406 sitd = NULL; 4407 total_length = 0; 4408 4409 /* 4410 * To allow continuous transfers, above we start all transfers 4411 * immediately. However, we're still going to get usbd_start_next call 4412 * this when another xfer completes. So, check if this is already 4413 * in progress or not 4414 */ 4415 4416 if (exfer->ex_isrunning) { 4417 return USBD_IN_PROGRESS; 4418 } 4419 4420 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4421 xfer, xfer->ux_length, xfer->ux_flags, 0); 4422 4423 if (sc->sc_dying) 4424 return USBD_IOERROR; 4425 4426 /* 4427 * To avoid complication, don't allow a request right now that'll span 4428 * the entire frame table. To within 4 frames, to allow some leeway 4429 * on either side of where the hc currently is. 4430 */ 4431 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4432 xfer->ux_nframes >= sc->sc_flsize - 4) { 4433 printf("ehci: isoc descriptor requested that spans the entire" 4434 "frametable, too many frames\n"); 4435 return USBD_INVAL; 4436 } 4437 4438 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4439 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4440 KASSERT(exfer->ex_isdone); 4441 #ifdef DIAGNOSTIC 4442 exfer->ex_isdone = false; 4443 #endif 4444 4445 /* 4446 * Step 1: Initialize sitds. 4447 */ 4448 4449 frames = xfer->ux_nframes; 4450 dma_buf = &xfer->ux_dmabuf; 4451 offs = 0; 4452 4453 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4454 i++, sitd = sitd->xfer_next) { 4455 KASSERT(sitd != NULL); 4456 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4457 4458 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4459 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4460 4461 /* Set page0 index and offset - TP and T-offset are set below */ 4462 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4463 4464 total_length += xfer->ux_frlengths[i]; 4465 offs += xfer->ux_frlengths[i]; 4466 4467 sitd->sitd.sitd_buffer[1] = 4468 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4469 4470 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4471 4472 #if 0 4473 if (sc->sc_flags & EHCIF_FREESCALE) { 4474 // Set hub address to 0 if embedded TT is used. 4475 if (huba == sc->sc_addr) 4476 huba = 0; 4477 } 4478 #endif 4479 4480 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4481 dir = UE_GET_DIR(k) ? 1 : 0; 4482 KASSERT(sitd->sitd.sitd_endp == htole32( 4483 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4484 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4485 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4486 EHCI_SITD_SET_HUBA(huba) | 4487 EHCI_SITD_SET_DIR(dir))); 4488 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4489 4490 uint8_t sa = 0; 4491 uint8_t sb = 0; 4492 u_int temp, tlen; 4493 4494 if (dir == 0) { /* OUT */ 4495 temp = 0; 4496 tlen = xfer->ux_frlengths[i]; 4497 if (tlen <= 188) { 4498 temp |= 1; /* T-count = 1, TP = ALL */ 4499 tlen = 1; 4500 } else { 4501 tlen += 187; 4502 tlen /= 188; 4503 temp |= tlen; /* T-count = [1..6] */ 4504 temp |= 8; /* TP = Begin */ 4505 } 4506 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4507 4508 tlen += sa; 4509 4510 if (tlen >= 8) { 4511 sb = 0; 4512 } else { 4513 sb = (1 << tlen); 4514 } 4515 4516 sa = (1 << sa); 4517 sa = (sb - sa) & 0x3F; 4518 sb = 0; 4519 } else { 4520 sb = (-(4 << sa)) & 0xFE; 4521 sa = (1 << sa) & 0x3F; 4522 sa = 0x01; 4523 sb = 0xfc; 4524 } 4525 4526 sitd->sitd.sitd_sched = htole32( 4527 EHCI_SITD_SET_SMASK(sa) | 4528 EHCI_SITD_SET_CMASK(sb) 4529 ); 4530 4531 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4532 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4533 } /* End of frame */ 4534 4535 sitd = exfer->ex_sitdend; 4536 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4537 4538 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4539 sizeof(sitd->sitd.sitd_trans), 4540 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4541 4542 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4544 4545 /* 4546 * Part 2: Transfer descriptors have now been set up, now they must 4547 * be scheduled into the periodic frame list. Erk. Not wanting to 4548 * complicate matters, transfer is denied if the transfer spans 4549 * more than the period frame list. 4550 */ 4551 4552 mutex_enter(&sc->sc_lock); 4553 4554 /* Start inserting frames */ 4555 if (epipe->isoc.cur_xfers > 0) { 4556 frindex = epipe->isoc.next_frame; 4557 } else { 4558 frindex = EOREAD4(sc, EHCI_FRINDEX); 4559 frindex = frindex >> 3; /* Erase microframe index */ 4560 frindex += 2; 4561 } 4562 4563 if (frindex >= sc->sc_flsize) 4564 frindex &= (sc->sc_flsize - 1); 4565 4566 /* Whats the frame interval? */ 4567 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4568 4569 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4570 j++, sitd = sitd->xfer_next) { 4571 KASSERT(sitd); 4572 4573 usb_syncmem(&sc->sc_fldma, 4574 sizeof(ehci_link_t) * frindex, 4575 sizeof(ehci_link_t), 4576 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4577 4578 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4579 if (sitd->sitd.sitd_next == 0) 4580 /* 4581 * FIXME: frindex table gets initialized to NULL 4582 * or EHCI_NULL? 4583 */ 4584 sitd->sitd.sitd_next = EHCI_NULL; 4585 4586 usb_syncmem(&sitd->dma, 4587 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4588 sizeof(ehci_sitd_t), 4589 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4590 4591 sc->sc_flist[frindex] = 4592 htole32(EHCI_LINK_SITD | sitd->physaddr); 4593 4594 usb_syncmem(&sc->sc_fldma, 4595 sizeof(ehci_link_t) * frindex, 4596 sizeof(ehci_link_t), 4597 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4598 4599 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4600 sc->sc_softsitds[frindex] = sitd; 4601 if (sitd->frame_list.next != NULL) 4602 sitd->frame_list.next->frame_list.prev = sitd; 4603 sitd->slot = frindex; 4604 sitd->frame_list.prev = NULL; 4605 4606 frindex += i; 4607 if (frindex >= sc->sc_flsize) 4608 frindex -= sc->sc_flsize; 4609 } 4610 4611 epipe->isoc.cur_xfers++; 4612 epipe->isoc.next_frame = frindex; 4613 4614 exfer->ex_isrunning = true; 4615 4616 ehci_add_intr_list(sc, exfer); 4617 xfer->ux_status = USBD_IN_PROGRESS; 4618 4619 mutex_exit(&sc->sc_lock); 4620 4621 if (sc->sc_bus.ub_usepolling) { 4622 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4623 ehci_waitintr(sc, xfer); 4624 } 4625 4626 return USBD_IN_PROGRESS; 4627 } 4628 4629 Static void 4630 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4631 { 4632 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4633 4634 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4635 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4636 } 4637 4638 Static void 4639 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4640 { 4641 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4642 4643 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4644 } 4645 4646 Static void 4647 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4648 { 4649 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4650 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4651 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4652 4653 KASSERT(mutex_owned(&sc->sc_lock)); 4654 4655 epipe->isoc.cur_xfers--; 4656 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4657 ehci_del_intr_list(sc, exfer); 4658 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4659 exfer->ex_isrunning = false; 4660 } 4661 4662 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4663 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4664 } 4665 4666 4667 /************************/ 4668 4669 4670 Static int 4671 ehci_device_isoc_init(struct usbd_xfer *xfer) 4672 { 4673 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4674 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4675 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4676 ehci_soft_itd_t *itd, *prev, *start, *stop; 4677 int i, j, k; 4678 int frames, ufrperframe; 4679 int err; 4680 4681 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4682 4683 start = NULL; 4684 prev = NULL; 4685 itd = NULL; 4686 4687 KASSERT(xfer->ux_nframes != 0); 4688 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4689 KASSERT(exfer->ex_isdone); 4690 4691 exfer->ex_type = EX_ISOC; 4692 4693 /* 4694 * Step 1: Allocate and initialize itds, how many do we need? 4695 * One per transfer if interval >= 8 microframes, less if we use 4696 * multiple microframes per frame. 4697 */ 4698 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4699 if (i > 16 || i == 0) { 4700 /* Spec page 271 says intervals > 16 are invalid */ 4701 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4702 return USBD_INVAL; 4703 } 4704 4705 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4706 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4707 4708 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4709 itd = ehci_alloc_itd(sc); 4710 if (itd == NULL) { 4711 err = ENOMEM; 4712 goto fail; 4713 } 4714 4715 if (prev != NULL) { 4716 /* Maybe not as it's updated by the scheduling? */ 4717 prev->itd.itd_next = 4718 htole32(itd->physaddr | EHCI_LINK_ITD); 4719 4720 prev->xfer_next = itd; 4721 } else { 4722 start = itd; 4723 } 4724 4725 /* 4726 * Other special values 4727 */ 4728 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4729 itd->itd.itd_bufr[0] = htole32( 4730 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4731 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4732 4733 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4734 ? 1 : 0; 4735 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4736 itd->itd.itd_bufr[1] |= htole32( 4737 EHCI_ITD_SET_DIR(k) | 4738 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4739 4740 /* FIXME: handle invalid trans - should be done in openpipe */ 4741 itd->itd.itd_bufr[2] |= 4742 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4743 } /* End of frame */ 4744 4745 stop = itd; 4746 stop->xfer_next = NULL; 4747 4748 exfer->ex_itdstart = start; 4749 exfer->ex_itdend = stop; 4750 4751 return 0; 4752 fail: 4753 mutex_enter(&sc->sc_lock); 4754 ehci_soft_itd_t *next; 4755 for (itd = start; itd; itd = next) { 4756 next = itd->xfer_next; 4757 ehci_free_itd_locked(sc, itd); 4758 } 4759 mutex_exit(&sc->sc_lock); 4760 4761 return err; 4762 4763 } 4764 4765 Static void 4766 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4767 { 4768 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4769 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4770 4771 KASSERT(ex->ex_type == EX_ISOC); 4772 4773 ehci_free_itd_chain(sc, ex->ex_itdstart); 4774 } 4775 4776 Static usbd_status 4777 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4778 { 4779 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4780 usbd_status err; 4781 4782 mutex_enter(&sc->sc_lock); 4783 err = usb_insert_transfer(xfer); 4784 mutex_exit(&sc->sc_lock); 4785 if (err && err != USBD_IN_PROGRESS) 4786 return err; 4787 4788 return ehci_device_isoc_start(xfer); 4789 } 4790 4791 Static usbd_status 4792 ehci_device_isoc_start(struct usbd_xfer *xfer) 4793 { 4794 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4795 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4796 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4797 ehci_soft_itd_t *itd, *prev; 4798 usb_dma_t *dma_buf; 4799 int i, j; 4800 int frames, uframes, ufrperframe; 4801 int trans_count, offs, total_length; 4802 int frindex; 4803 4804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4805 4806 prev = NULL; 4807 itd = NULL; 4808 trans_count = 0; 4809 total_length = 0; 4810 4811 /* 4812 * To allow continuous transfers, above we start all transfers 4813 * immediately. However, we're still going to get usbd_start_next call 4814 * this when another xfer completes. So, check if this is already 4815 * in progress or not 4816 */ 4817 4818 if (exfer->ex_isrunning) { 4819 return USBD_IN_PROGRESS; 4820 } 4821 4822 USBHIST_LOG(ehcidebug, "xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4823 4824 if (sc->sc_dying) 4825 return USBD_IOERROR; 4826 4827 /* 4828 * To avoid complication, don't allow a request right now that'll span 4829 * the entire frame table. To within 4 frames, to allow some leeway 4830 * on either side of where the hc currently is. 4831 */ 4832 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4833 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4834 USBHIST_LOG(ehcidebug, 4835 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4836 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4837 return USBD_INVAL; 4838 } 4839 4840 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4841 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4842 KASSERT(exfer->ex_isdone); 4843 #ifdef DIAGNOSTIC 4844 exfer->ex_isdone = false; 4845 #endif 4846 4847 /* 4848 * Step 1: Re-Initialize itds 4849 */ 4850 4851 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4852 if (i > 16 || i == 0) { 4853 /* Spec page 271 says intervals > 16 are invalid */ 4854 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4855 return USBD_INVAL; 4856 } 4857 4858 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4859 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4860 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4861 4862 if (frames == 0) { 4863 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4864 return USBD_INVAL; 4865 } 4866 4867 dma_buf = &xfer->ux_dmabuf; 4868 offs = 0; 4869 4870 itd = exfer->ex_itdstart; 4871 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4872 int froffs = offs; 4873 4874 if (prev != NULL) { 4875 prev->itd.itd_next = 4876 htole32(itd->physaddr | EHCI_LINK_ITD); 4877 usb_syncmem(&prev->dma, 4878 prev->offs + offsetof(ehci_itd_t, itd_next), 4879 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4880 prev->xfer_next = itd; 4881 } 4882 4883 /* 4884 * Step 1.5, initialize uframes 4885 */ 4886 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4887 /* Calculate which page in the list this starts in */ 4888 int addr = DMAADDR(dma_buf, froffs); 4889 addr = EHCI_PAGE_OFFSET(addr); 4890 addr += (offs - froffs); 4891 addr = EHCI_PAGE(addr); 4892 addr /= EHCI_PAGE_SIZE; 4893 4894 /* 4895 * This gets the initial offset into the first page, 4896 * looks how far further along the current uframe 4897 * offset is. Works out how many pages that is. 4898 */ 4899 4900 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4901 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4902 EHCI_ITD_SET_PG(addr) | 4903 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4904 4905 total_length += xfer->ux_frlengths[trans_count]; 4906 offs += xfer->ux_frlengths[trans_count]; 4907 trans_count++; 4908 4909 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4910 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4911 break; 4912 } 4913 } 4914 4915 /* 4916 * Step 1.75, set buffer pointers. To simplify matters, all 4917 * pointers are filled out for the next 7 hardware pages in 4918 * the dma block, so no need to worry what pages to cover 4919 * and what to not. 4920 */ 4921 4922 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4923 /* 4924 * Don't try to lookup a page that's past the end 4925 * of buffer 4926 */ 4927 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4928 if (page_offs >= dma_buf->udma_block->size) 4929 break; 4930 4931 uint64_t page = DMAADDR(dma_buf, page_offs); 4932 page = EHCI_PAGE(page); 4933 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4934 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4935 } 4936 /* 4937 * Other special values 4938 */ 4939 4940 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4941 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4942 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4943 4944 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4945 ? 1 : 0; 4946 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4947 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4948 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4949 4950 /* FIXME: handle invalid trans */ 4951 itd->itd.itd_bufr[2] |= 4952 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4953 4954 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4955 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4956 4957 prev = itd; 4958 } /* End of frame */ 4959 4960 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4962 4963 /* 4964 * Part 2: Transfer descriptors have now been set up, now they must 4965 * be scheduled into the period frame list. Erk. Not wanting to 4966 * complicate matters, transfer is denied if the transfer spans 4967 * more than the period frame list. 4968 */ 4969 4970 mutex_enter(&sc->sc_lock); 4971 4972 /* Start inserting frames */ 4973 if (epipe->isoc.cur_xfers > 0) { 4974 frindex = epipe->isoc.next_frame; 4975 } else { 4976 frindex = EOREAD4(sc, EHCI_FRINDEX); 4977 frindex = frindex >> 3; /* Erase microframe index */ 4978 frindex += 2; 4979 } 4980 4981 if (frindex >= sc->sc_flsize) 4982 frindex &= (sc->sc_flsize - 1); 4983 4984 /* What's the frame interval? */ 4985 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4986 if (i / USB_UFRAMES_PER_FRAME == 0) 4987 i = 1; 4988 else 4989 i /= USB_UFRAMES_PER_FRAME; 4990 4991 itd = exfer->ex_itdstart; 4992 for (j = 0; j < frames; j++) { 4993 KASSERTMSG(itd != NULL, "frame %d\n", j); 4994 4995 usb_syncmem(&sc->sc_fldma, 4996 sizeof(ehci_link_t) * frindex, 4997 sizeof(ehci_link_t), 4998 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4999 5000 itd->itd.itd_next = sc->sc_flist[frindex]; 5001 if (itd->itd.itd_next == 0) 5002 /* 5003 * FIXME: frindex table gets initialized to NULL 5004 * or EHCI_NULL? 5005 */ 5006 itd->itd.itd_next = EHCI_NULL; 5007 5008 usb_syncmem(&itd->dma, 5009 itd->offs + offsetof(ehci_itd_t, itd_next), 5010 sizeof(itd->itd.itd_next), 5011 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5012 5013 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 5014 5015 usb_syncmem(&sc->sc_fldma, 5016 sizeof(ehci_link_t) * frindex, 5017 sizeof(ehci_link_t), 5018 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5019 5020 itd->frame_list.next = sc->sc_softitds[frindex]; 5021 sc->sc_softitds[frindex] = itd; 5022 if (itd->frame_list.next != NULL) 5023 itd->frame_list.next->frame_list.prev = itd; 5024 itd->slot = frindex; 5025 itd->frame_list.prev = NULL; 5026 5027 frindex += i; 5028 if (frindex >= sc->sc_flsize) 5029 frindex -= sc->sc_flsize; 5030 5031 itd = itd->xfer_next; 5032 } 5033 5034 epipe->isoc.cur_xfers++; 5035 epipe->isoc.next_frame = frindex; 5036 5037 exfer->ex_isrunning = true; 5038 5039 ehci_add_intr_list(sc, exfer); 5040 xfer->ux_status = USBD_IN_PROGRESS; 5041 5042 mutex_exit(&sc->sc_lock); 5043 5044 if (sc->sc_bus.ub_usepolling) { 5045 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 5046 ehci_waitintr(sc, xfer); 5047 } 5048 5049 return USBD_IN_PROGRESS; 5050 } 5051 5052 Static void 5053 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5054 { 5055 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5056 5057 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 5058 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5059 } 5060 5061 Static void 5062 ehci_device_isoc_close(struct usbd_pipe *pipe) 5063 { 5064 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5065 5066 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 5067 } 5068 5069 Static void 5070 ehci_device_isoc_done(struct usbd_xfer *xfer) 5071 { 5072 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5073 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5074 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5075 5076 KASSERT(mutex_owned(&sc->sc_lock)); 5077 5078 epipe->isoc.cur_xfers--; 5079 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 5080 ehci_del_intr_list(sc, exfer); 5081 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5082 exfer->ex_isrunning = false; 5083 } 5084 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5085 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5086 } 5087
Indexes created Thu Oct 02 01:09:59 GMT 2025