ehci.c revision 1.234.2.73
1 /* $NetBSD: ehci.c,v 1.234.2.73 2015/12/27 12:09:59 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.73 2015/12/27 12:09:59 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 /* Control pipe */ 136 struct { 137 usb_dma_t reqdma; 138 } ctrl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Iso pipe */ 144 struct { 145 u_int next_frame; 146 u_int cur_xfers; 147 } isoc; 148 }; 149 }; 150 151 Static usbd_status ehci_open(struct usbd_pipe *); 152 Static void ehci_poll(struct usbd_bus *); 153 Static void ehci_softintr(void *); 154 Static int ehci_intr1(ehci_softc_t *); 155 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 156 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 157 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 158 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 159 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 160 Static void ehci_idone(struct ehci_xfer *); 161 Static void ehci_timeout(void *); 162 Static void ehci_timeout_task(void *); 163 Static void ehci_intrlist_timeout(void *); 164 Static void ehci_doorbell(void *); 165 Static void ehci_pcd(void *); 166 167 Static struct usbd_xfer * 168 ehci_allocx(struct usbd_bus *, unsigned int); 169 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 170 171 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 172 Static int ehci_roothub_ctrl(struct usbd_bus *, 173 usb_device_request_t *, void *, int); 174 175 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 176 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 177 Static void ehci_root_intr_abort(struct usbd_xfer *); 178 Static void ehci_root_intr_close(struct usbd_pipe *); 179 Static void ehci_root_intr_done(struct usbd_xfer *); 180 181 Static int ehci_device_ctrl_init(struct usbd_xfer *); 182 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 183 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 185 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 186 Static void ehci_device_ctrl_close(struct usbd_pipe *); 187 Static void ehci_device_ctrl_done(struct usbd_xfer *); 188 189 Static int ehci_device_bulk_init(struct usbd_xfer *); 190 Static void ehci_device_bulk_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 193 Static void ehci_device_bulk_abort(struct usbd_xfer *); 194 Static void ehci_device_bulk_close(struct usbd_pipe *); 195 Static void ehci_device_bulk_done(struct usbd_xfer *); 196 197 Static int ehci_device_intr_init(struct usbd_xfer *); 198 Static void ehci_device_intr_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 201 Static void ehci_device_intr_abort(struct usbd_xfer *); 202 Static void ehci_device_intr_close(struct usbd_pipe *); 203 Static void ehci_device_intr_done(struct usbd_xfer *); 204 205 Static int ehci_device_isoc_init(struct usbd_xfer *); 206 Static void ehci_device_isoc_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 209 Static void ehci_device_isoc_abort(struct usbd_xfer *); 210 Static void ehci_device_isoc_close(struct usbd_pipe *); 211 Static void ehci_device_isoc_done(struct usbd_xfer *); 212 213 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 216 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 217 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 220 221 Static void ehci_device_clear_toggle(struct usbd_pipe *); 222 Static void ehci_noop(struct usbd_pipe *); 223 224 Static void ehci_disown(ehci_softc_t *, int, int); 225 226 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 227 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 228 229 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 230 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 231 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 232 int, int, ehci_soft_qtd_t **, ehci_soft_qtd_t **); 233 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 234 235 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 236 int, int, int *, ehci_soft_qtd_t **); 237 238 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 239 Static ehci_soft_sitd_t * 240 ehci_alloc_sitd(ehci_softc_t *); 241 242 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 243 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 244 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 245 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 246 247 static inline void 248 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 249 { 250 251 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 252 } 253 254 static inline void 255 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 259 } 260 261 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 262 263 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 264 int); 265 266 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 267 ehci_soft_qh_t *); 268 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 269 ehci_soft_qh_t *); 270 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 271 Static void ehci_sync_hc(ehci_softc_t *); 272 273 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 274 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 275 276 #ifdef EHCI_DEBUG 277 Static ehci_softc_t *theehci; 278 void ehci_dump(void); 279 #endif 280 281 #ifdef EHCI_DEBUG 282 Static void ehci_dump_regs(ehci_softc_t *); 283 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 284 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 285 Static void ehci_dump_qtd(ehci_qtd_t *); 286 Static void ehci_dump_sqh(ehci_soft_qh_t *); 287 Static void ehci_dump_sitd(struct ehci_soft_itd *); 288 Static void ehci_dump_itds(ehci_soft_itd_t *); 289 Static void ehci_dump_itd(struct ehci_soft_itd *); 290 Static void ehci_dump_exfer(struct ehci_xfer *); 291 #endif 292 293 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 294 295 #define ehci_add_intr_list(sc, ex) \ 296 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 297 #define ehci_del_intr_list(sc, ex) \ 298 do { \ 299 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 300 (ex)->ex_next.tqe_prev = NULL; \ 301 } while (0) 302 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 303 304 Static const struct usbd_bus_methods ehci_bus_methods = { 305 .ubm_open = ehci_open, 306 .ubm_softint = ehci_softintr, 307 .ubm_dopoll = ehci_poll, 308 .ubm_allocx = ehci_allocx, 309 .ubm_freex = ehci_freex, 310 .ubm_getlock = ehci_get_lock, 311 .ubm_rhctrl = ehci_roothub_ctrl, 312 }; 313 314 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 315 .upm_transfer = ehci_root_intr_transfer, 316 .upm_start = ehci_root_intr_start, 317 .upm_abort = ehci_root_intr_abort, 318 .upm_close = ehci_root_intr_close, 319 .upm_cleartoggle = ehci_noop, 320 .upm_done = ehci_root_intr_done, 321 }; 322 323 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 324 .upm_init = ehci_device_ctrl_init, 325 .upm_fini = ehci_device_ctrl_fini, 326 .upm_transfer = ehci_device_ctrl_transfer, 327 .upm_start = ehci_device_ctrl_start, 328 .upm_abort = ehci_device_ctrl_abort, 329 .upm_close = ehci_device_ctrl_close, 330 .upm_cleartoggle = ehci_noop, 331 .upm_done = ehci_device_ctrl_done, 332 }; 333 334 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 335 .upm_init = ehci_device_intr_init, 336 .upm_fini = ehci_device_intr_fini, 337 .upm_transfer = ehci_device_intr_transfer, 338 .upm_start = ehci_device_intr_start, 339 .upm_abort = ehci_device_intr_abort, 340 .upm_close = ehci_device_intr_close, 341 .upm_cleartoggle = ehci_device_clear_toggle, 342 .upm_done = ehci_device_intr_done, 343 }; 344 345 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 346 .upm_init = ehci_device_bulk_init, 347 .upm_fini = ehci_device_bulk_fini, 348 .upm_transfer = ehci_device_bulk_transfer, 349 .upm_start = ehci_device_bulk_start, 350 .upm_abort = ehci_device_bulk_abort, 351 .upm_close = ehci_device_bulk_close, 352 .upm_cleartoggle = ehci_device_clear_toggle, 353 .upm_done = ehci_device_bulk_done, 354 }; 355 356 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 357 .upm_init = ehci_device_isoc_init, 358 .upm_fini = ehci_device_isoc_fini, 359 .upm_transfer = ehci_device_isoc_transfer, 360 .upm_start = ehci_device_isoc_start, 361 .upm_abort = ehci_device_isoc_abort, 362 .upm_close = ehci_device_isoc_close, 363 .upm_cleartoggle = ehci_noop, 364 .upm_done = ehci_device_isoc_done, 365 }; 366 367 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 368 .upm_init = ehci_device_fs_isoc_init, 369 .upm_fini = ehci_device_fs_isoc_fini, 370 .upm_transfer = ehci_device_fs_isoc_transfer, 371 .upm_start = ehci_device_fs_isoc_start, 372 .upm_abort = ehci_device_fs_isoc_abort, 373 .upm_close = ehci_device_fs_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_fs_isoc_done, 376 }; 377 378 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 379 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 380 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 381 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 382 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 383 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 384 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 385 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 386 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 387 }; 388 389 int 390 ehci_init(ehci_softc_t *sc) 391 { 392 uint32_t vers, sparams, cparams, hcr; 393 u_int i; 394 usbd_status err; 395 ehci_soft_qh_t *sqh; 396 u_int ncomp; 397 398 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 399 #ifdef EHCI_DEBUG 400 theehci = sc; 401 #endif 402 403 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 404 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 405 cv_init(&sc->sc_softwake_cv, "ehciab"); 406 cv_init(&sc->sc_doorbell, "ehcidi"); 407 408 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 409 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 410 411 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 412 ehci_doorbell, sc); 413 KASSERT(sc->sc_doorbell_si != NULL); 414 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 415 ehci_pcd, sc); 416 KASSERT(sc->sc_pcd_si != NULL); 417 418 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 419 420 vers = EREAD2(sc, EHCI_HCIVERSION); 421 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 422 vers >> 8, vers & 0xff); 423 424 sparams = EREAD4(sc, EHCI_HCSPARAMS); 425 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 426 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 427 ncomp = EHCI_HCS_N_CC(sparams); 428 if (ncomp != sc->sc_ncomp) { 429 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 430 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 431 #if NOHCI == 0 || NUHCI == 0 432 aprint_error("%s: ohci or uhci probably not configured\n", 433 device_xname(sc->sc_dev)); 434 #endif 435 if (ncomp < sc->sc_ncomp) 436 sc->sc_ncomp = ncomp; 437 } 438 if (sc->sc_ncomp > 0) { 439 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 440 aprint_normal("%s: companion controller%s, %d port%s each:", 441 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 442 EHCI_HCS_N_PCC(sparams), 443 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 444 for (i = 0; i < sc->sc_ncomp; i++) 445 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 446 aprint_normal("\n"); 447 } 448 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 449 cparams = EREAD4(sc, EHCI_HCCPARAMS); 450 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 451 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 452 453 if (EHCI_HCC_64BIT(cparams)) { 454 /* MUST clear segment register if 64 bit capable. */ 455 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 456 } 457 458 sc->sc_bus.ub_revision = USBREV_2_0; 459 sc->sc_bus.ub_usedma = true; 460 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 461 462 /* Reset the controller */ 463 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 464 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 465 usb_delay_ms(&sc->sc_bus, 1); 466 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 467 for (i = 0; i < 100; i++) { 468 usb_delay_ms(&sc->sc_bus, 1); 469 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 470 if (!hcr) 471 break; 472 } 473 if (hcr) { 474 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 475 return EIO; 476 } 477 if (sc->sc_vendor_init) 478 sc->sc_vendor_init(sc); 479 480 /* XXX need proper intr scheduling */ 481 sc->sc_rand = 96; 482 483 /* frame list size at default, read back what we got and use that */ 484 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 485 case 0: sc->sc_flsize = 1024; break; 486 case 1: sc->sc_flsize = 512; break; 487 case 2: sc->sc_flsize = 256; break; 488 case 3: return EIO; 489 } 490 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 491 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 492 if (err) 493 return err; 494 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 495 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 496 497 for (i = 0; i < sc->sc_flsize; i++) { 498 sc->sc_flist[i] = EHCI_NULL; 499 } 500 501 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 502 503 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 504 KM_SLEEP); 505 if (sc->sc_softitds == NULL) 506 return ENOMEM; 507 LIST_INIT(&sc->sc_freeitds); 508 LIST_INIT(&sc->sc_freesitds); 509 TAILQ_INIT(&sc->sc_intrhead); 510 511 /* Set up the bus struct. */ 512 sc->sc_bus.ub_methods = &ehci_bus_methods; 513 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 514 515 sc->sc_eintrs = EHCI_NORMAL_INTRS; 516 517 /* 518 * Allocate the interrupt dummy QHs. These are arranged to give poll 519 * intervals that are powers of 2 times 1ms. 520 */ 521 for (i = 0; i < EHCI_INTRQHS; i++) { 522 sqh = ehci_alloc_sqh(sc); 523 if (sqh == NULL) { 524 err = ENOMEM; 525 goto bad1; 526 } 527 sc->sc_islots[i].sqh = sqh; 528 } 529 for (i = 0; i < EHCI_INTRQHS; i++) { 530 sqh = sc->sc_islots[i].sqh; 531 if (i == 0) { 532 /* The last (1ms) QH terminates. */ 533 sqh->qh.qh_link = EHCI_NULL; 534 sqh->next = NULL; 535 } else { 536 /* Otherwise the next QH has half the poll interval */ 537 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 538 sqh->qh.qh_link = htole32(sqh->next->physaddr | 539 EHCI_LINK_QH); 540 } 541 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 542 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 543 sqh->qh.qh_curqtd = EHCI_NULL; 544 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 545 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 546 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 547 sqh->sqtd = NULL; 548 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 } 551 /* Point the frame list at the last level (128ms). */ 552 for (i = 0; i < sc->sc_flsize; i++) { 553 int j; 554 555 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 556 revbits[i & (EHCI_MAX_POLLRATE-1)]; 557 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 558 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 559 i)].sqh->physaddr); 560 } 561 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 562 BUS_DMASYNC_PREWRITE); 563 564 /* Allocate dummy QH that starts the async list. */ 565 sqh = ehci_alloc_sqh(sc); 566 if (sqh == NULL) { 567 err = ENOMEM; 568 goto bad1; 569 } 570 /* Fill the QH */ 571 sqh->qh.qh_endp = 572 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 573 sqh->qh.qh_link = 574 htole32(sqh->physaddr | EHCI_LINK_QH); 575 sqh->qh.qh_curqtd = EHCI_NULL; 576 sqh->next = NULL; 577 /* Fill the overlay qTD */ 578 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 579 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 580 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 581 sqh->sqtd = NULL; 582 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 584 #ifdef EHCI_DEBUG 585 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 586 ehci_dump_sqh(sqh); 587 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 588 #endif 589 590 /* Point to async list */ 591 sc->sc_async_head = sqh; 592 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 593 594 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 595 596 /* Turn on controller */ 597 EOWRITE4(sc, EHCI_USBCMD, 598 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 599 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 600 EHCI_CMD_ASE | 601 EHCI_CMD_PSE | 602 EHCI_CMD_RS); 603 604 /* Take over port ownership */ 605 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 606 607 for (i = 0; i < 100; i++) { 608 usb_delay_ms(&sc->sc_bus, 1); 609 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 610 if (!hcr) 611 break; 612 } 613 if (hcr) { 614 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 615 return EIO; 616 } 617 618 /* Enable interrupts */ 619 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 620 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 621 622 return 0; 623 624 #if 0 625 bad2: 626 ehci_free_sqh(sc, sc->sc_async_head); 627 #endif 628 bad1: 629 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 630 return err; 631 } 632 633 int 634 ehci_intr(void *v) 635 { 636 ehci_softc_t *sc = v; 637 int ret = 0; 638 639 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 640 641 if (sc == NULL) 642 return 0; 643 644 mutex_spin_enter(&sc->sc_intr_lock); 645 646 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 647 goto done; 648 649 /* If we get an interrupt while polling, then just ignore it. */ 650 if (sc->sc_bus.ub_usepolling) { 651 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 652 653 if (intrs) 654 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 655 USBHIST_LOGN(ehcidebug, 16, 656 "ignored interrupt while polling", 0, 0, 0, 0); 657 goto done; 658 } 659 660 ret = ehci_intr1(sc); 661 662 done: 663 mutex_spin_exit(&sc->sc_intr_lock); 664 return ret; 665 } 666 667 Static int 668 ehci_intr1(ehci_softc_t *sc) 669 { 670 uint32_t intrs, eintrs; 671 672 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 673 674 /* In case the interrupt occurs before initialization has completed. */ 675 if (sc == NULL) { 676 #ifdef DIAGNOSTIC 677 printf("ehci_intr1: sc == NULL\n"); 678 #endif 679 return 0; 680 } 681 682 KASSERT(mutex_owned(&sc->sc_intr_lock)); 683 684 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 685 if (!intrs) 686 return 0; 687 688 eintrs = intrs & sc->sc_eintrs; 689 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 690 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 691 if (!eintrs) 692 return 0; 693 694 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 695 if (eintrs & EHCI_STS_IAA) { 696 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 697 kpreempt_disable(); 698 KASSERT(sc->sc_doorbell_si != NULL); 699 softint_schedule(sc->sc_doorbell_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_IAA; 702 } 703 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 704 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 705 eintrs & EHCI_STS_INT ? 1 : 0, 706 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 707 usb_schedsoftintr(&sc->sc_bus); 708 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 709 } 710 if (eintrs & EHCI_STS_HSE) { 711 printf("%s: unrecoverable error, controller halted\n", 712 device_xname(sc->sc_dev)); 713 /* XXX what else */ 714 } 715 if (eintrs & EHCI_STS_PCD) { 716 kpreempt_disable(); 717 KASSERT(sc->sc_pcd_si != NULL); 718 softint_schedule(sc->sc_pcd_si); 719 kpreempt_enable(); 720 eintrs &= ~EHCI_STS_PCD; 721 } 722 723 if (eintrs != 0) { 724 /* Block unprocessed interrupts. */ 725 sc->sc_eintrs &= ~eintrs; 726 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 727 printf("%s: blocking intrs 0x%x\n", 728 device_xname(sc->sc_dev), eintrs); 729 } 730 731 return 1; 732 } 733 734 Static void 735 ehci_doorbell(void *addr) 736 { 737 ehci_softc_t *sc = addr; 738 739 mutex_enter(&sc->sc_lock); 740 cv_broadcast(&sc->sc_doorbell); 741 mutex_exit(&sc->sc_lock); 742 } 743 744 Static void 745 ehci_pcd(void *addr) 746 { 747 ehci_softc_t *sc = addr; 748 struct usbd_xfer *xfer; 749 u_char *p; 750 int i, m; 751 752 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 753 754 mutex_enter(&sc->sc_lock); 755 xfer = sc->sc_intrxfer; 756 757 if (xfer == NULL) { 758 /* Just ignore the change. */ 759 goto done; 760 } 761 762 p = xfer->ux_buf; 763 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 764 memset(p, 0, xfer->ux_length); 765 for (i = 1; i <= m; i++) { 766 /* Pick out CHANGE bits from the status reg. */ 767 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 768 p[i/8] |= 1 << (i%8); 769 if (i % 8 == 7) 770 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 771 p[i/8], 0, 0); 772 } 773 xfer->ux_actlen = xfer->ux_length; 774 xfer->ux_status = USBD_NORMAL_COMPLETION; 775 776 usb_transfer_complete(xfer); 777 778 done: 779 mutex_exit(&sc->sc_lock); 780 } 781 782 Static void 783 ehci_softintr(void *v) 784 { 785 struct usbd_bus *bus = v; 786 ehci_softc_t *sc = EHCI_BUS2SC(bus); 787 struct ehci_xfer *ex, *nextex; 788 789 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 790 791 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 792 793 /* 794 * The only explanation I can think of for why EHCI is as brain dead 795 * as UHCI interrupt-wise is that Intel was involved in both. 796 * An interrupt just tells us that something is done, we have no 797 * clue what, so we need to scan through all active transfers. :-( 798 */ 799 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 800 nextex = TAILQ_NEXT(ex, ex_next); 801 ehci_check_intr(sc, ex); 802 } 803 804 /* Schedule a callout to catch any dropped transactions. */ 805 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 806 !TAILQ_EMPTY(&sc->sc_intrhead)) 807 callout_reset(&sc->sc_tmo_intrlist, 808 hz, ehci_intrlist_timeout, sc); 809 810 if (sc->sc_softwake) { 811 sc->sc_softwake = 0; 812 cv_broadcast(&sc->sc_softwake_cv); 813 } 814 } 815 816 /* Check for an interrupt. */ 817 Static void 818 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 819 { 820 821 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 822 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 823 824 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 825 826 switch (ex->ex_type) { 827 case EX_CTRL: 828 case EX_BULK: 829 case EX_INTR: 830 ehci_check_qh_intr(sc, ex); 831 break; 832 case EX_ISOC: 833 ehci_check_itd_intr(sc, ex); 834 break; 835 case EX_FS_ISOC: 836 ehci_check_sitd_intr(sc, ex); 837 break; 838 default: 839 KASSERT(false); 840 } 841 842 return; 843 } 844 845 Static void 846 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 847 { 848 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 849 uint32_t status; 850 851 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 852 853 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 854 855 if (ex->ex_type == EX_CTRL) { 856 fsqtd = ex->ex_setup; 857 lsqtd = ex->ex_status; 858 } else { 859 fsqtd = ex->ex_sqtdstart; 860 lsqtd = ex->ex_sqtdend; 861 } 862 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 863 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 864 865 /* 866 * If the last TD is still active we need to check whether there 867 * is an error somewhere in the middle, or whether there was a 868 * short packet (SPD and not ACTIVE). 869 */ 870 usb_syncmem(&lsqtd->dma, 871 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 872 sizeof(lsqtd->qtd.qtd_status), 873 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 874 status = le32toh(lsqtd->qtd.qtd_status); 875 usb_syncmem(&lsqtd->dma, 876 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 877 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 878 if (status & EHCI_QTD_ACTIVE) { 879 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 880 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 881 usb_syncmem(&sqtd->dma, 882 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 883 sizeof(sqtd->qtd.qtd_status), 884 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 885 status = le32toh(sqtd->qtd.qtd_status); 886 usb_syncmem(&sqtd->dma, 887 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 888 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 889 /* If there's an active QTD the xfer isn't done. */ 890 if (status & EHCI_QTD_ACTIVE) 891 break; 892 /* Any kind of error makes the xfer done. */ 893 if (status & EHCI_QTD_HALTED) 894 goto done; 895 /* Handle short packets */ 896 if (EHCI_QTD_GET_BYTES(status) != 0) { 897 /* 898 * If we get here for a control transfer then 899 * we need to let the hardware complete the 900 * status phase. That is, we're not done 901 * quite yet. 902 * 903 * Otherwise, we're done. 904 */ 905 if (ex->ex_type == EX_CTRL) { 906 break; 907 } 908 goto done; 909 } 910 } 911 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 912 ex, ex->ex_sqtdstart, 0, 0); 913 #ifdef EHCI_DEBUG 914 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 915 0, 0); 916 ehci_dump_sqtds(ex->ex_sqtdstart); 917 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 918 0); 919 #endif 920 return; 921 } 922 done: 923 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 924 callout_stop(&ex->ex_xfer.ux_callout); 925 ehci_idone(ex); 926 } 927 928 Static void 929 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 930 { 931 ehci_soft_itd_t *itd; 932 int i; 933 934 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 935 936 KASSERT(mutex_owned(&sc->sc_lock)); 937 938 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 939 return; 940 941 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 942 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 943 944 itd = ex->ex_itdend; 945 946 /* 947 * check no active transfers in last itd, meaning we're finished 948 */ 949 950 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 951 sizeof(itd->itd.itd_ctl), 952 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 953 954 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 955 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 956 break; 957 } 958 959 if (i == EHCI_ITD_NUFRAMES) { 960 goto done; /* All 8 descriptors inactive, it's done */ 961 } 962 963 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 964 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 965 966 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 967 ex->ex_itdstart, 0, 0); 968 return; 969 done: 970 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 971 callout_stop(&ex->ex_xfer.ux_callout); 972 ehci_idone(ex); 973 } 974 975 void 976 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 977 { 978 ehci_soft_sitd_t *sitd; 979 980 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 981 982 KASSERT(mutex_owned(&sc->sc_lock)); 983 984 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 985 return; 986 987 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 988 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 989 990 sitd = ex->ex_sitdend; 991 992 /* 993 * check no active transfers in last sitd, meaning we're finished 994 */ 995 996 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 997 sizeof(sitd->sitd.sitd_trans), 998 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 999 1000 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1001 1002 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1003 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1004 1005 if (active) 1006 return; 1007 1008 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1009 callout_stop(&(ex->ex_xfer.ux_callout)); 1010 ehci_idone(ex); 1011 } 1012 1013 1014 Static void 1015 ehci_idone(struct ehci_xfer *ex) 1016 { 1017 struct usbd_xfer *xfer = &ex->ex_xfer; 1018 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1019 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1020 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1021 uint32_t status = 0, nstatus = 0; 1022 int actlen = 0; 1023 1024 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1025 1026 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1027 1028 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1029 1030 #ifdef DIAGNOSTIC 1031 #ifdef EHCI_DEBUG 1032 if (ex->ex_isdone) { 1033 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1034 ehci_dump_exfer(ex); 1035 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1036 } 1037 #endif 1038 KASSERT(!ex->ex_isdone); 1039 ex->ex_isdone = true; 1040 #endif 1041 1042 if (xfer->ux_status == USBD_CANCELLED || 1043 xfer->ux_status == USBD_TIMEOUT) { 1044 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1045 return; 1046 } 1047 1048 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1049 1050 /* The transfer is done, compute actual length and status. */ 1051 if (ex->ex_type == EX_ISOC) { 1052 /* HS isoc transfer */ 1053 1054 struct ehci_soft_itd *itd; 1055 int i, nframes, len, uframes; 1056 1057 nframes = 0; 1058 1059 #ifdef EHCI_DEBUG 1060 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1061 ehci_dump_itds(ex->ex_itdstart); 1062 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1063 #endif 1064 1065 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1066 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1067 1068 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1069 usb_syncmem(&itd->dma, 1070 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1071 sizeof(itd->itd.itd_ctl), 1072 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1073 1074 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1075 /* 1076 * XXX - driver didn't fill in the frame full 1077 * of uframes. This leads to scheduling 1078 * inefficiencies, but working around 1079 * this doubles complexity of tracking 1080 * an xfer. 1081 */ 1082 if (nframes >= xfer->ux_nframes) 1083 break; 1084 1085 status = le32toh(itd->itd.itd_ctl[i]); 1086 len = EHCI_ITD_GET_LEN(status); 1087 if (EHCI_ITD_GET_STATUS(status) != 0) 1088 len = 0; /*No valid data on error*/ 1089 1090 xfer->ux_frlengths[nframes++] = len; 1091 actlen += len; 1092 } 1093 usb_syncmem(&itd->dma, 1094 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1095 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1096 1097 if (nframes >= xfer->ux_nframes) 1098 break; 1099 } 1100 1101 xfer->ux_actlen = actlen; 1102 xfer->ux_status = USBD_NORMAL_COMPLETION; 1103 goto end; 1104 } else if (ex->ex_type == EX_FS_ISOC) { 1105 /* FS isoc transfer */ 1106 struct ehci_soft_sitd *sitd; 1107 int nframes, len; 1108 1109 nframes = 0; 1110 1111 for (sitd = ex->ex_sitdstart; sitd != NULL; 1112 sitd = sitd->xfer_next) { 1113 usb_syncmem(&sitd->dma, 1114 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1115 sizeof(sitd->sitd.sitd_trans), 1116 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1117 1118 /* 1119 * XXX - driver didn't fill in the frame full 1120 * of uframes. This leads to scheduling 1121 * inefficiencies, but working around 1122 * this doubles complexity of tracking 1123 * an xfer. 1124 */ 1125 if (nframes >= xfer->ux_nframes) 1126 break; 1127 1128 status = le32toh(sitd->sitd.sitd_trans); 1129 usb_syncmem(&sitd->dma, 1130 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1131 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1132 1133 len = EHCI_SITD_GET_LEN(status); 1134 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1135 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1136 /* No valid data on error */ 1137 len = xfer->ux_frlengths[nframes]; 1138 } 1139 1140 /* 1141 * frlengths[i]: # of bytes to send 1142 * len: # of bytes host didn't send 1143 */ 1144 xfer->ux_frlengths[nframes] -= len; 1145 /* frlengths[i]: # of bytes host sent */ 1146 actlen += xfer->ux_frlengths[nframes++]; 1147 1148 if (nframes >= xfer->ux_nframes) 1149 break; 1150 } 1151 1152 xfer->ux_actlen = actlen; 1153 xfer->ux_status = USBD_NORMAL_COMPLETION; 1154 goto end; 1155 } 1156 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1157 ex->ex_type == EX_BULK); 1158 1159 /* Continue processing xfers using queue heads */ 1160 if (ex->ex_type == EX_CTRL) { 1161 fsqtd = ex->ex_setup; 1162 lsqtd = ex->ex_status; 1163 } else { 1164 fsqtd = ex->ex_sqtdstart; 1165 lsqtd = ex->ex_sqtdend; 1166 } 1167 #ifdef EHCI_DEBUG 1168 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1169 ehci_dump_sqtds(fsqtd); 1170 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1171 #endif 1172 1173 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1174 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1175 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1176 nstatus = le32toh(sqtd->qtd.qtd_status); 1177 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1178 BUS_DMASYNC_PREREAD); 1179 if (nstatus & EHCI_QTD_ACTIVE) 1180 break; 1181 1182 status = nstatus; 1183 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1184 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1185 } 1186 1187 /* 1188 * If there are left over TDs we need to update the toggle. 1189 * The default pipe doesn't need it since control transfers 1190 * start the toggle at 0 every time. 1191 * For a short transfer we need to update the toggle for the missing 1192 * packets within the qTD. 1193 */ 1194 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1195 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1196 USBHIST_LOG(ehcidebug, 1197 "toggle update status=0x%08x nstatus=0x%08x", 1198 status, nstatus, 0, 0); 1199 #if 0 1200 ehci_dump_sqh(epipe->sqh); 1201 ehci_dump_sqtds(ex->ex_sqtdstart); 1202 #endif 1203 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1204 } 1205 1206 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1207 actlen, status, 0); 1208 xfer->ux_actlen = actlen; 1209 if (status & EHCI_QTD_HALTED) { 1210 #ifdef EHCI_DEBUG 1211 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1212 xfer->ux_pipe->up_dev->ud_addr, 1213 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1214 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1215 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1216 0, 0); 1217 USBHIST_LOG(ehcidebug, 1218 "active =%d halted=%d buferr=%d babble=%d", 1219 status & EHCI_QTD_ACTIVE ? 1 : 0, 1220 status & EHCI_QTD_HALTED ? 1 : 0, 1221 status & EHCI_QTD_BUFERR ? 1 : 0, 1222 status & EHCI_QTD_BABBLE ? 1 : 0); 1223 1224 USBHIST_LOG(ehcidebug, 1225 "xacterr=%d missed=%d split =%d ping =%d", 1226 status & EHCI_QTD_XACTERR ? 1 : 0, 1227 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1228 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1229 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1230 1231 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1232 ehci_dump_sqh(epipe->sqh); 1233 ehci_dump_sqtds(ex->ex_sqtdstart); 1234 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1235 #endif 1236 /* low&full speed has an extra error flag */ 1237 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1238 EHCI_QH_SPEED_HIGH) 1239 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1240 else 1241 status &= EHCI_QTD_STATERRS; 1242 if (status == 0) /* no other errors means a stall */ { 1243 xfer->ux_status = USBD_STALLED; 1244 } else { 1245 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1246 } 1247 /* XXX need to reset TT on missed microframe */ 1248 if (status & EHCI_QTD_MISSEDMICRO) { 1249 printf("%s: missed microframe, TT reset not " 1250 "implemented, hub might be inoperational\n", 1251 device_xname(sc->sc_dev)); 1252 } 1253 } else { 1254 xfer->ux_status = USBD_NORMAL_COMPLETION; 1255 } 1256 1257 end: 1258 /* 1259 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1260 * during this call, before methods->done is called: dma sync required 1261 * beforehand? 1262 */ 1263 usb_transfer_complete(xfer); 1264 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1265 } 1266 1267 /* 1268 * Wait here until controller claims to have an interrupt. 1269 * Then call ehci_intr and return. Use timeout to avoid waiting 1270 * too long. 1271 */ 1272 Static void 1273 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1274 { 1275 int timo; 1276 uint32_t intrs; 1277 1278 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1279 1280 xfer->ux_status = USBD_IN_PROGRESS; 1281 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1282 usb_delay_ms(&sc->sc_bus, 1); 1283 if (sc->sc_dying) 1284 break; 1285 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1286 sc->sc_eintrs; 1287 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1288 #ifdef EHCI_DEBUG 1289 if (ehcidebug > 15) 1290 ehci_dump_regs(sc); 1291 #endif 1292 if (intrs) { 1293 mutex_spin_enter(&sc->sc_intr_lock); 1294 ehci_intr1(sc); 1295 mutex_spin_exit(&sc->sc_intr_lock); 1296 if (xfer->ux_status != USBD_IN_PROGRESS) 1297 return; 1298 } 1299 } 1300 1301 /* Timeout */ 1302 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1303 xfer->ux_status = USBD_TIMEOUT; 1304 mutex_enter(&sc->sc_lock); 1305 usb_transfer_complete(xfer); 1306 mutex_exit(&sc->sc_lock); 1307 } 1308 1309 Static void 1310 ehci_poll(struct usbd_bus *bus) 1311 { 1312 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1313 1314 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1315 1316 #ifdef EHCI_DEBUG 1317 static int last; 1318 int new; 1319 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1320 if (new != last) { 1321 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1322 last = new; 1323 } 1324 #endif 1325 1326 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1327 mutex_spin_enter(&sc->sc_intr_lock); 1328 ehci_intr1(sc); 1329 mutex_spin_exit(&sc->sc_intr_lock); 1330 } 1331 } 1332 1333 void 1334 ehci_childdet(device_t self, device_t child) 1335 { 1336 struct ehci_softc *sc = device_private(self); 1337 1338 KASSERT(sc->sc_child == child); 1339 sc->sc_child = NULL; 1340 } 1341 1342 int 1343 ehci_detach(struct ehci_softc *sc, int flags) 1344 { 1345 int rv = 0; 1346 1347 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1348 1349 if (sc->sc_child != NULL) 1350 rv = config_detach(sc->sc_child, flags); 1351 1352 if (rv != 0) 1353 return rv; 1354 1355 callout_halt(&sc->sc_tmo_intrlist, NULL); 1356 callout_destroy(&sc->sc_tmo_intrlist); 1357 1358 /* XXX free other data structures XXX */ 1359 if (sc->sc_softitds) 1360 kmem_free(sc->sc_softitds, 1361 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1362 cv_destroy(&sc->sc_doorbell); 1363 cv_destroy(&sc->sc_softwake_cv); 1364 1365 #if 0 1366 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1367 1368 softint_disestablish(sc->sc_doorbell_si); 1369 softint_disestablish(sc->sc_pcd_si); 1370 1371 mutex_destroy(&sc->sc_lock); 1372 mutex_destroy(&sc->sc_intr_lock); 1373 #endif 1374 1375 pool_cache_destroy(sc->sc_xferpool); 1376 1377 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1378 1379 return rv; 1380 } 1381 1382 1383 int 1384 ehci_activate(device_t self, enum devact act) 1385 { 1386 struct ehci_softc *sc = device_private(self); 1387 1388 switch (act) { 1389 case DVACT_DEACTIVATE: 1390 sc->sc_dying = 1; 1391 return 0; 1392 default: 1393 return EOPNOTSUPP; 1394 } 1395 } 1396 1397 /* 1398 * Handle suspend/resume. 1399 * 1400 * We need to switch to polling mode here, because this routine is 1401 * called from an interrupt context. This is all right since we 1402 * are almost suspended anyway. 1403 * 1404 * Note that this power handler isn't to be registered directly; the 1405 * bus glue needs to call out to it. 1406 */ 1407 bool 1408 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1409 { 1410 ehci_softc_t *sc = device_private(dv); 1411 int i; 1412 uint32_t cmd, hcr; 1413 1414 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1415 1416 mutex_spin_enter(&sc->sc_intr_lock); 1417 sc->sc_bus.ub_usepolling++; 1418 mutex_spin_exit(&sc->sc_intr_lock); 1419 1420 for (i = 1; i <= sc->sc_noport; i++) { 1421 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1422 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1423 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1424 } 1425 1426 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1427 1428 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1429 EOWRITE4(sc, EHCI_USBCMD, cmd); 1430 1431 for (i = 0; i < 100; i++) { 1432 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1433 if (hcr == 0) 1434 break; 1435 1436 usb_delay_ms(&sc->sc_bus, 1); 1437 } 1438 if (hcr != 0) 1439 printf("%s: reset timeout\n", device_xname(dv)); 1440 1441 cmd &= ~EHCI_CMD_RS; 1442 EOWRITE4(sc, EHCI_USBCMD, cmd); 1443 1444 for (i = 0; i < 100; i++) { 1445 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1446 if (hcr == EHCI_STS_HCH) 1447 break; 1448 1449 usb_delay_ms(&sc->sc_bus, 1); 1450 } 1451 if (hcr != EHCI_STS_HCH) 1452 printf("%s: config timeout\n", device_xname(dv)); 1453 1454 mutex_spin_enter(&sc->sc_intr_lock); 1455 sc->sc_bus.ub_usepolling--; 1456 mutex_spin_exit(&sc->sc_intr_lock); 1457 1458 return true; 1459 } 1460 1461 bool 1462 ehci_resume(device_t dv, const pmf_qual_t *qual) 1463 { 1464 ehci_softc_t *sc = device_private(dv); 1465 int i; 1466 uint32_t cmd, hcr; 1467 1468 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1469 1470 /* restore things in case the bios sucks */ 1471 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1472 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1473 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1474 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1475 1476 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1477 1478 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1479 1480 hcr = 0; 1481 for (i = 1; i <= sc->sc_noport; i++) { 1482 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1483 if ((cmd & EHCI_PS_PO) == 0 && 1484 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1485 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1486 hcr = 1; 1487 } 1488 } 1489 1490 if (hcr) { 1491 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1492 1493 for (i = 1; i <= sc->sc_noport; i++) { 1494 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1495 if ((cmd & EHCI_PS_PO) == 0 && 1496 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1497 EOWRITE4(sc, EHCI_PORTSC(i), 1498 cmd & ~EHCI_PS_FPR); 1499 } 1500 } 1501 1502 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1503 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1504 1505 for (i = 0; i < 100; i++) { 1506 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1507 if (hcr != EHCI_STS_HCH) 1508 break; 1509 1510 usb_delay_ms(&sc->sc_bus, 1); 1511 } 1512 if (hcr == EHCI_STS_HCH) 1513 printf("%s: config timeout\n", device_xname(dv)); 1514 1515 return true; 1516 } 1517 1518 /* 1519 * Shut down the controller when the system is going down. 1520 */ 1521 bool 1522 ehci_shutdown(device_t self, int flags) 1523 { 1524 ehci_softc_t *sc = device_private(self); 1525 1526 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1527 1528 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1529 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1530 return true; 1531 } 1532 1533 Static struct usbd_xfer * 1534 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1535 { 1536 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1537 struct usbd_xfer *xfer; 1538 1539 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1540 if (xfer != NULL) { 1541 memset(xfer, 0, sizeof(struct ehci_xfer)); 1542 #ifdef DIAGNOSTIC 1543 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1544 ex->ex_isdone = true; 1545 xfer->ux_state = XFER_BUSY; 1546 #endif 1547 } 1548 return xfer; 1549 } 1550 1551 Static void 1552 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1553 { 1554 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1555 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1556 1557 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1558 xfer->ux_state); 1559 KASSERT(ex->ex_isdone); 1560 1561 #ifdef DIAGNOSTIC 1562 xfer->ux_state = XFER_FREE; 1563 #endif 1564 1565 pool_cache_put(sc->sc_xferpool, xfer); 1566 } 1567 1568 Static void 1569 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1570 { 1571 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1572 1573 *lock = &sc->sc_lock; 1574 } 1575 1576 Static void 1577 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1578 { 1579 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1580 1581 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1582 1583 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1584 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1585 #ifdef EHCI_DEBUG 1586 if (ehcidebug) 1587 usbd_dump_pipe(pipe); 1588 #endif 1589 epipe->nexttoggle = 0; 1590 } 1591 1592 Static void 1593 ehci_noop(struct usbd_pipe *pipe) 1594 { 1595 } 1596 1597 #ifdef EHCI_DEBUG 1598 /* 1599 * Unused function - this is meant to be called from a kernel 1600 * debugger. 1601 */ 1602 void 1603 ehci_dump(void) 1604 { 1605 ehci_softc_t *sc = theehci; 1606 int i; 1607 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1608 EOREAD4(sc, EHCI_USBCMD), 1609 EOREAD4(sc, EHCI_USBSTS), 1610 EOREAD4(sc, EHCI_USBINTR)); 1611 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1612 EOREAD4(sc, EHCI_FRINDEX), 1613 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1614 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1615 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1616 for (i = 1; i <= sc->sc_noport; i++) 1617 printf("port %d status=0x%08x\n", i, 1618 EOREAD4(sc, EHCI_PORTSC(i))); 1619 } 1620 1621 Static void 1622 ehci_dump_regs(ehci_softc_t *sc) 1623 { 1624 int i; 1625 1626 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1627 1628 USBHIST_LOG(ehcidebug, 1629 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1630 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1631 EOREAD4(sc, EHCI_USBINTR), 0); 1632 USBHIST_LOG(ehcidebug, 1633 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1634 "async = 0x%08x", 1635 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1636 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1637 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1638 for (i = 1; i <= sc->sc_noport; i += 2) { 1639 if (i == sc->sc_noport) { 1640 USBHIST_LOG(ehcidebug, 1641 "port %d status = 0x%08x", i, 1642 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1643 } else { 1644 USBHIST_LOG(ehcidebug, 1645 "port %d status = 0x%08x port %d status = 0x%08x", 1646 i, EOREAD4(sc, EHCI_PORTSC(i)), 1647 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1648 } 1649 } 1650 } 1651 1652 #define ehci_dump_link(link, type) do { \ 1653 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1654 link, \ 1655 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1656 if (type) { \ 1657 USBHIST_LOG(ehcidebug, \ 1658 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1659 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1660 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1661 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1662 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1663 } \ 1664 } while(0) 1665 1666 Static void 1667 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1668 { 1669 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1670 int i; 1671 uint32_t stop = 0; 1672 1673 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1674 ehci_dump_sqtd(sqtd); 1675 usb_syncmem(&sqtd->dma, 1676 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1677 sizeof(sqtd->qtd), 1678 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1679 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1680 usb_syncmem(&sqtd->dma, 1681 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1682 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1683 } 1684 if (!stop) 1685 USBHIST_LOG(ehcidebug, 1686 "dump aborted, too many TDs", 0, 0, 0, 0); 1687 } 1688 1689 Static void 1690 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1691 { 1692 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1693 1694 usb_syncmem(&sqtd->dma, sqtd->offs, 1695 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1696 1697 USBHIST_LOGN(ehcidebug, 10, 1698 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1699 ehci_dump_qtd(&sqtd->qtd); 1700 1701 usb_syncmem(&sqtd->dma, sqtd->offs, 1702 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1703 } 1704 1705 Static void 1706 ehci_dump_qtd(ehci_qtd_t *qtd) 1707 { 1708 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1709 uint32_t s = le32toh(qtd->qtd_status); 1710 1711 USBHIST_LOGN(ehcidebug, 10, 1712 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1713 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1714 USBHIST_LOGN(ehcidebug, 10, 1715 " toggle = %d ioc = %d bytes = %#x " 1716 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1717 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1718 USBHIST_LOGN(ehcidebug, 10, 1719 " cerr = %d pid = %d stat = %x", 1720 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1721 0); 1722 USBHIST_LOGN(ehcidebug, 10, 1723 "active =%d halted=%d buferr=%d babble=%d", 1724 s & EHCI_QTD_ACTIVE ? 1 : 0, 1725 s & EHCI_QTD_HALTED ? 1 : 0, 1726 s & EHCI_QTD_BUFERR ? 1 : 0, 1727 s & EHCI_QTD_BABBLE ? 1 : 0); 1728 USBHIST_LOGN(ehcidebug, 10, 1729 "xacterr=%d missed=%d split =%d ping =%d", 1730 s & EHCI_QTD_XACTERR ? 1 : 0, 1731 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1732 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1733 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1734 USBHIST_LOGN(ehcidebug, 10, 1735 "buffer[0] = %#x buffer[1] = %#x " 1736 "buffer[2] = %#x buffer[3] = %#x", 1737 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1738 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1739 USBHIST_LOGN(ehcidebug, 10, 1740 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1741 } 1742 1743 Static void 1744 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1745 { 1746 ehci_qh_t *qh = &sqh->qh; 1747 ehci_link_t link; 1748 uint32_t endp, endphub; 1749 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1750 1751 usb_syncmem(&sqh->dma, sqh->offs, 1752 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1753 1754 USBHIST_LOGN(ehcidebug, 10, 1755 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1756 link = le32toh(qh->qh_link); 1757 ehci_dump_link(link, true); 1758 1759 endp = le32toh(qh->qh_endp); 1760 USBHIST_LOGN(ehcidebug, 10, 1761 " endp = %#x", endp, 0, 0, 0); 1762 USBHIST_LOGN(ehcidebug, 10, 1763 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1764 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1765 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1766 USBHIST_LOGN(ehcidebug, 10, 1767 " dtc = %d hrecl = %d", 1768 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1769 USBHIST_LOGN(ehcidebug, 10, 1770 " ctl = %d nrl = %d mpl = %#x(%d)", 1771 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1772 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1773 1774 endphub = le32toh(qh->qh_endphub); 1775 USBHIST_LOGN(ehcidebug, 10, 1776 " endphub = %#x", endphub, 0, 0, 0); 1777 USBHIST_LOGN(ehcidebug, 10, 1778 " smask = 0x%02x cmask = 0x%02x", 1779 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1780 USBHIST_LOGN(ehcidebug, 10, 1781 " huba = 0x%02x port = %d mult = %d", 1782 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1783 EHCI_QH_GET_MULT(endphub), 0); 1784 1785 link = le32toh(qh->qh_curqtd); 1786 ehci_dump_link(link, false); 1787 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1788 ehci_dump_qtd(&qh->qh_qtd); 1789 1790 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1791 BUS_DMASYNC_PREREAD); 1792 } 1793 1794 Static void 1795 ehci_dump_itds(ehci_soft_itd_t *itd) 1796 { 1797 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1798 int i; 1799 uint32_t stop = 0; 1800 1801 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1802 ehci_dump_itd(itd); 1803 usb_syncmem(&itd->dma, 1804 itd->offs + offsetof(ehci_itd_t, itd_next), 1805 sizeof(itd->itd), 1806 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1807 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1808 usb_syncmem(&itd->dma, 1809 itd->offs + offsetof(ehci_itd_t, itd_next), 1810 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1811 } 1812 if (!stop) 1813 USBHIST_LOG(ehcidebug, "dump aborted, too many TDs", 0, 0, 0, 0); 1814 } 1815 1816 Static void 1817 ehci_dump_itd(struct ehci_soft_itd *itd) 1818 { 1819 ehci_isoc_trans_t t; 1820 ehci_isoc_bufr_ptr_t b, b2, b3; 1821 int i; 1822 1823 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1824 1825 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1826 0, 0); 1827 1828 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1829 t = le32toh(itd->itd.itd_ctl[i]); 1830 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1831 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1832 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1833 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1834 EHCI_ITD_GET_OFFS(t), 0); 1835 } 1836 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1837 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1838 USBHIST_LOG(ehcidebug, " %x", 1839 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1840 1841 b = le32toh(itd->itd.itd_bufr[0]); 1842 b2 = le32toh(itd->itd.itd_bufr[1]); 1843 b3 = le32toh(itd->itd.itd_bufr[2]); 1844 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1845 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1846 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1847 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1848 } 1849 1850 Static void 1851 ehci_dump_sitd(struct ehci_soft_itd *itd) 1852 { 1853 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1854 1855 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1856 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1857 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1858 itd->xfer_next, itd->physaddr, itd->slot, 0); 1859 } 1860 1861 Static void 1862 ehci_dump_exfer(struct ehci_xfer *ex) 1863 { 1864 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1865 1866 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1867 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1868 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1869 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1870 } 1871 #endif 1872 1873 Static usbd_status 1874 ehci_open(struct usbd_pipe *pipe) 1875 { 1876 struct usbd_device *dev = pipe->up_dev; 1877 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1878 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1879 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1880 uint8_t addr = dev->ud_addr; 1881 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1882 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1883 ehci_soft_qh_t *sqh; 1884 usbd_status err; 1885 int ival, speed, naks; 1886 int hshubaddr, hshubport; 1887 1888 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1889 1890 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1891 pipe, addr, ed->bEndpointAddress, rhaddr); 1892 1893 if (dev->ud_myhsport) { 1894 /* 1895 * When directly attached FS/LS device while doing embedded 1896 * transaction translations and we are the hub, set the hub 1897 * address to 0 (us). 1898 */ 1899 if (!(sc->sc_flags & EHCIF_ETTF) 1900 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1901 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1902 } else { 1903 hshubaddr = 0; 1904 } 1905 hshubport = dev->ud_myhsport->up_portno; 1906 } else { 1907 hshubaddr = 0; 1908 hshubport = 0; 1909 } 1910 1911 if (sc->sc_dying) 1912 return USBD_IOERROR; 1913 1914 /* toggle state needed for bulk endpoints */ 1915 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1916 1917 if (addr == rhaddr) { 1918 switch (ed->bEndpointAddress) { 1919 case USB_CONTROL_ENDPOINT: 1920 pipe->up_methods = &roothub_ctrl_methods; 1921 break; 1922 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1923 pipe->up_methods = &ehci_root_intr_methods; 1924 break; 1925 default: 1926 USBHIST_LOG(ehcidebug, 1927 "bad bEndpointAddress 0x%02x", 1928 ed->bEndpointAddress, 0, 0, 0); 1929 return USBD_INVAL; 1930 } 1931 return USBD_NORMAL_COMPLETION; 1932 } 1933 1934 /* XXX All this stuff is only valid for async. */ 1935 switch (dev->ud_speed) { 1936 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1937 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1938 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1939 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1940 } 1941 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1942 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1943 hshubaddr, hshubport, 0, 0); 1944 return USBD_INVAL; 1945 } 1946 1947 /* 1948 * For interrupt transfer, nak throttling must be disabled, but for 1949 * the other transfer type, nak throttling should be enabled from the 1950 * viewpoint that avoids the memory thrashing. 1951 */ 1952 naks = (xfertype == UE_INTERRUPT) ? 0 1953 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1954 1955 /* Allocate sqh for everything, save isoc xfers */ 1956 if (xfertype != UE_ISOCHRONOUS) { 1957 sqh = ehci_alloc_sqh(sc); 1958 if (sqh == NULL) 1959 return USBD_NOMEM; 1960 /* qh_link filled when the QH is added */ 1961 sqh->qh.qh_endp = htole32( 1962 EHCI_QH_SET_ADDR(addr) | 1963 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1964 EHCI_QH_SET_EPS(speed) | 1965 EHCI_QH_DTC | 1966 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1967 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1968 EHCI_QH_CTL : 0) | 1969 EHCI_QH_SET_NRL(naks) 1970 ); 1971 sqh->qh.qh_endphub = htole32( 1972 EHCI_QH_SET_MULT(1) | 1973 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1974 ); 1975 if (speed != EHCI_QH_SPEED_HIGH) 1976 sqh->qh.qh_endphub |= htole32( 1977 EHCI_QH_SET_PORT(hshubport) | 1978 EHCI_QH_SET_HUBA(hshubaddr) | 1979 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1980 ); 1981 sqh->qh.qh_curqtd = EHCI_NULL; 1982 /* Fill the overlay qTD */ 1983 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1984 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1985 sqh->qh.qh_qtd.qtd_status = htole32(0); 1986 1987 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1989 epipe->sqh = sqh; 1990 } else { 1991 sqh = NULL; 1992 } /*xfertype == UE_ISOC*/ 1993 1994 switch (xfertype) { 1995 case UE_CONTROL: 1996 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1997 0, &epipe->ctrl.reqdma); 1998 #ifdef EHCI_DEBUG 1999 if (err) 2000 printf("ehci_open: usb_allocmem()=%d\n", err); 2001 #endif 2002 if (err) 2003 goto bad; 2004 pipe->up_methods = &ehci_device_ctrl_methods; 2005 mutex_enter(&sc->sc_lock); 2006 ehci_add_qh(sc, sqh, sc->sc_async_head); 2007 mutex_exit(&sc->sc_lock); 2008 break; 2009 case UE_BULK: 2010 pipe->up_methods = &ehci_device_bulk_methods; 2011 mutex_enter(&sc->sc_lock); 2012 ehci_add_qh(sc, sqh, sc->sc_async_head); 2013 mutex_exit(&sc->sc_lock); 2014 break; 2015 case UE_INTERRUPT: 2016 pipe->up_methods = &ehci_device_intr_methods; 2017 ival = pipe->up_interval; 2018 if (ival == USBD_DEFAULT_INTERVAL) { 2019 if (speed == EHCI_QH_SPEED_HIGH) { 2020 if (ed->bInterval > 16) { 2021 /* 2022 * illegal with high-speed, but there 2023 * were documentation bugs in the spec, 2024 * so be generous 2025 */ 2026 ival = 256; 2027 } else 2028 ival = (1 << (ed->bInterval - 1)) / 8; 2029 } else 2030 ival = ed->bInterval; 2031 } 2032 err = ehci_device_setintr(sc, sqh, ival); 2033 if (err) 2034 goto bad; 2035 break; 2036 case UE_ISOCHRONOUS: 2037 if (speed == EHCI_QH_SPEED_HIGH) 2038 pipe->up_methods = &ehci_device_isoc_methods; 2039 else 2040 pipe->up_methods = &ehci_device_fs_isoc_methods; 2041 if (ed->bInterval == 0 || ed->bInterval > 16) { 2042 printf("ehci: opening pipe with invalid bInterval\n"); 2043 err = USBD_INVAL; 2044 goto bad; 2045 } 2046 if (UGETW(ed->wMaxPacketSize) == 0) { 2047 printf("ehci: zero length endpoint open request\n"); 2048 err = USBD_INVAL; 2049 goto bad; 2050 } 2051 epipe->isoc.next_frame = 0; 2052 epipe->isoc.cur_xfers = 0; 2053 break; 2054 default: 2055 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2056 err = USBD_INVAL; 2057 goto bad; 2058 } 2059 return USBD_NORMAL_COMPLETION; 2060 2061 bad: 2062 if (sqh != NULL) { 2063 mutex_enter(&sc->sc_lock); 2064 ehci_free_sqh(sc, sqh); 2065 mutex_exit(&sc->sc_lock); 2066 } 2067 return err; 2068 } 2069 2070 /* 2071 * Add an ED to the schedule. Called with USB lock held. 2072 */ 2073 Static void 2074 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2075 { 2076 2077 KASSERT(mutex_owned(&sc->sc_lock)); 2078 2079 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2080 2081 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2082 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2083 2084 sqh->next = head->next; 2085 sqh->qh.qh_link = head->qh.qh_link; 2086 2087 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2088 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2089 2090 head->next = sqh; 2091 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2092 2093 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2094 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2095 2096 #ifdef EHCI_DEBUG 2097 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2098 ehci_dump_sqh(sqh); 2099 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2100 #endif 2101 } 2102 2103 /* 2104 * Remove an ED from the schedule. Called with USB lock held. 2105 */ 2106 Static void 2107 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2108 { 2109 ehci_soft_qh_t *p; 2110 2111 KASSERT(mutex_owned(&sc->sc_lock)); 2112 2113 /* XXX */ 2114 for (p = head; p != NULL && p->next != sqh; p = p->next) 2115 ; 2116 if (p == NULL) 2117 panic("ehci_rem_qh: ED not found"); 2118 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2119 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2120 p->next = sqh->next; 2121 p->qh.qh_link = sqh->qh.qh_link; 2122 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2123 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2124 2125 ehci_sync_hc(sc); 2126 } 2127 2128 Static void 2129 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2130 { 2131 int i; 2132 uint32_t status; 2133 2134 /* Save toggle bit and ping status. */ 2135 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2136 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2137 status = sqh->qh.qh_qtd.qtd_status & 2138 htole32(EHCI_QTD_TOGGLE_MASK | 2139 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2140 /* Set HALTED to make hw leave it alone. */ 2141 sqh->qh.qh_qtd.qtd_status = 2142 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2143 usb_syncmem(&sqh->dma, 2144 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2145 sizeof(sqh->qh.qh_qtd.qtd_status), 2146 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2147 sqh->qh.qh_curqtd = 0; 2148 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2149 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2150 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2151 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2152 sqh->sqtd = sqtd; 2153 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2154 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2155 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2156 sqh->qh.qh_qtd.qtd_status = status; 2157 usb_syncmem(&sqh->dma, 2158 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2159 sizeof(sqh->qh.qh_qtd.qtd_status), 2160 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2161 } 2162 2163 /* 2164 * Ensure that the HC has released all references to the QH. We do this 2165 * by asking for a Async Advance Doorbell interrupt and then we wait for 2166 * the interrupt. 2167 * To make this easier we first obtain exclusive use of the doorbell. 2168 */ 2169 Static void 2170 ehci_sync_hc(ehci_softc_t *sc) 2171 { 2172 int error __diagused; 2173 2174 KASSERT(mutex_owned(&sc->sc_lock)); 2175 2176 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2177 2178 if (sc->sc_dying) { 2179 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2180 return; 2181 } 2182 /* ask for doorbell */ 2183 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2184 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2185 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2186 2187 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2188 2189 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2190 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2191 #ifdef DIAGNOSTIC 2192 if (error) 2193 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2194 #endif 2195 } 2196 2197 Static void 2198 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2199 { 2200 2201 KASSERT(mutex_owned(&sc->sc_lock)); 2202 2203 for (; itd != NULL; itd = itd->xfer_next) { 2204 struct ehci_soft_itd *prev = itd->frame_list.prev; 2205 2206 /* Unlink itd from hardware chain, or frame array */ 2207 if (prev == NULL) { /* We're at the table head */ 2208 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2209 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2210 usb_syncmem(&sc->sc_fldma, 2211 sizeof(ehci_link_t) * itd->slot, 2212 sizeof(ehci_link_t), 2213 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2214 2215 if (itd->frame_list.next != NULL) 2216 itd->frame_list.next->frame_list.prev = NULL; 2217 } else { 2218 /* XXX this part is untested... */ 2219 prev->itd.itd_next = itd->itd.itd_next; 2220 usb_syncmem(&itd->dma, 2221 itd->offs + offsetof(ehci_itd_t, itd_next), 2222 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2223 2224 prev->frame_list.next = itd->frame_list.next; 2225 if (itd->frame_list.next != NULL) 2226 itd->frame_list.next->frame_list.prev = prev; 2227 } 2228 } 2229 } 2230 2231 Static void 2232 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2233 { 2234 struct ehci_soft_itd *next; 2235 2236 mutex_enter(&sc->sc_lock); 2237 next = NULL; 2238 for (; itd != NULL; itd = next) { 2239 next = itd->xfer_next; 2240 ehci_free_itd_locked(sc, itd); 2241 } 2242 mutex_exit(&sc->sc_lock); 2243 } 2244 2245 Static void 2246 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2247 { 2248 2249 KASSERT(mutex_owned(&sc->sc_lock)); 2250 2251 for (; sitd != NULL; sitd = sitd->xfer_next) { 2252 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2253 2254 /* Unlink sitd from hardware chain, or frame array */ 2255 if (prev == NULL) { /* We're at the table head */ 2256 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2257 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2258 usb_syncmem(&sc->sc_fldma, 2259 sizeof(ehci_link_t) * sitd->slot, 2260 sizeof(ehci_link_t), 2261 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2262 2263 if (sitd->frame_list.next != NULL) 2264 sitd->frame_list.next->frame_list.prev = NULL; 2265 } else { 2266 /* XXX this part is untested... */ 2267 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2268 usb_syncmem(&sitd->dma, 2269 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2270 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2271 2272 prev->frame_list.next = sitd->frame_list.next; 2273 if (sitd->frame_list.next != NULL) 2274 sitd->frame_list.next->frame_list.prev = prev; 2275 } 2276 } 2277 } 2278 2279 Static void 2280 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2281 { 2282 2283 mutex_enter(&sc->sc_lock); 2284 struct ehci_soft_sitd *next = NULL; 2285 for (; sitd != NULL; sitd = next) { 2286 next = sitd->xfer_next; 2287 ehci_free_sitd_locked(sc, sitd); 2288 } 2289 mutex_exit(&sc->sc_lock); 2290 } 2291 2292 /***********/ 2293 2294 Static int 2295 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2296 void *buf, int buflen) 2297 { 2298 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2299 usb_hub_descriptor_t hubd; 2300 usb_port_status_t ps; 2301 uint16_t len, value, index; 2302 int l, totlen = 0; 2303 int port, i; 2304 uint32_t v; 2305 2306 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2307 2308 if (sc->sc_dying) 2309 return -1; 2310 2311 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2312 req->bmRequestType, req->bRequest, 0, 0); 2313 2314 len = UGETW(req->wLength); 2315 value = UGETW(req->wValue); 2316 index = UGETW(req->wIndex); 2317 2318 #define C(x,y) ((x) | ((y) << 8)) 2319 switch (C(req->bRequest, req->bmRequestType)) { 2320 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2321 if (len == 0) 2322 break; 2323 switch (value) { 2324 case C(0, UDESC_DEVICE): { 2325 usb_device_descriptor_t devd; 2326 totlen = min(buflen, sizeof(devd)); 2327 memcpy(&devd, buf, totlen); 2328 USETW(devd.idVendor, sc->sc_id_vendor); 2329 memcpy(buf, &devd, totlen); 2330 break; 2331 2332 } 2333 #define sd ((usb_string_descriptor_t *)buf) 2334 case C(1, UDESC_STRING): 2335 /* Vendor */ 2336 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2337 break; 2338 case C(2, UDESC_STRING): 2339 /* Product */ 2340 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2341 break; 2342 #undef sd 2343 default: 2344 /* default from usbroothub */ 2345 return buflen; 2346 } 2347 break; 2348 2349 /* Hub requests */ 2350 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2351 break; 2352 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2353 USBHIST_LOG(ehcidebug, 2354 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2355 0, 0); 2356 if (index < 1 || index > sc->sc_noport) { 2357 return -1; 2358 } 2359 port = EHCI_PORTSC(index); 2360 v = EOREAD4(sc, port); 2361 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2362 v &= ~EHCI_PS_CLEAR; 2363 switch (value) { 2364 case UHF_PORT_ENABLE: 2365 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2366 break; 2367 case UHF_PORT_SUSPEND: 2368 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2369 break; 2370 v &= ~EHCI_PS_SUSP; 2371 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2372 /* see USB2 spec ch. 7.1.7.7 */ 2373 usb_delay_ms(&sc->sc_bus, 20); 2374 EOWRITE4(sc, port, v); 2375 usb_delay_ms(&sc->sc_bus, 2); 2376 #ifdef DEBUG 2377 v = EOREAD4(sc, port); 2378 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2379 printf("ehci: resume failed: %x\n", v); 2380 #endif 2381 break; 2382 case UHF_PORT_POWER: 2383 if (sc->sc_hasppc) 2384 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2385 break; 2386 case UHF_PORT_TEST: 2387 USBHIST_LOG(ehcidebug, "clear port test " 2388 "%d", index, 0, 0, 0); 2389 break; 2390 case UHF_PORT_INDICATOR: 2391 USBHIST_LOG(ehcidebug, "clear port ind " 2392 "%d", index, 0, 0, 0); 2393 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2394 break; 2395 case UHF_C_PORT_CONNECTION: 2396 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2397 break; 2398 case UHF_C_PORT_ENABLE: 2399 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2400 break; 2401 case UHF_C_PORT_SUSPEND: 2402 /* how? */ 2403 break; 2404 case UHF_C_PORT_OVER_CURRENT: 2405 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2406 break; 2407 case UHF_C_PORT_RESET: 2408 sc->sc_isreset[index] = 0; 2409 break; 2410 default: 2411 return -1; 2412 } 2413 #if 0 2414 switch(value) { 2415 case UHF_C_PORT_CONNECTION: 2416 case UHF_C_PORT_ENABLE: 2417 case UHF_C_PORT_SUSPEND: 2418 case UHF_C_PORT_OVER_CURRENT: 2419 case UHF_C_PORT_RESET: 2420 default: 2421 break; 2422 } 2423 #endif 2424 break; 2425 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2426 if (len == 0) 2427 break; 2428 if ((value & 0xff) != 0) { 2429 return -1; 2430 } 2431 totlen = min(buflen, sizeof(hubd)); 2432 memcpy(&hubd, buf, totlen); 2433 hubd.bNbrPorts = sc->sc_noport; 2434 v = EOREAD4(sc, EHCI_HCSPARAMS); 2435 USETW(hubd.wHubCharacteristics, 2436 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2437 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2438 ? UHD_PORT_IND : 0); 2439 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2440 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2441 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2442 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2443 totlen = min(totlen, hubd.bDescLength); 2444 memcpy(buf, &hubd, totlen); 2445 break; 2446 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2447 if (len != 4) { 2448 return -1; 2449 } 2450 memset(buf, 0, len); /* ? XXX */ 2451 totlen = len; 2452 break; 2453 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2454 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2455 if (index < 1 || index > sc->sc_noport) { 2456 return -1; 2457 } 2458 if (len != 4) { 2459 return -1; 2460 } 2461 v = EOREAD4(sc, EHCI_PORTSC(index)); 2462 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2463 2464 i = UPS_HIGH_SPEED; 2465 if (sc->sc_flags & EHCIF_ETTF) { 2466 /* 2467 * If we are doing embedded transaction translation, 2468 * then directly attached LS/FS devices are reset by 2469 * the EHCI controller itself. PSPD is encoded 2470 * the same way as in USBSTATUS. 2471 */ 2472 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2473 } 2474 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2475 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2476 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2477 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2478 if (v & EHCI_PS_PR) i |= UPS_RESET; 2479 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2480 if (sc->sc_vendor_port_status) 2481 i = sc->sc_vendor_port_status(sc, v, i); 2482 USETW(ps.wPortStatus, i); 2483 i = 0; 2484 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2485 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2486 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2487 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2488 USETW(ps.wPortChange, i); 2489 totlen = min(len, sizeof(ps)); 2490 memcpy(buf, &ps, totlen); 2491 break; 2492 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2493 return -1; 2494 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2495 break; 2496 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2497 if (index < 1 || index > sc->sc_noport) { 2498 return -1; 2499 } 2500 port = EHCI_PORTSC(index); 2501 v = EOREAD4(sc, port); 2502 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2503 v &= ~EHCI_PS_CLEAR; 2504 switch(value) { 2505 case UHF_PORT_ENABLE: 2506 EOWRITE4(sc, port, v | EHCI_PS_PE); 2507 break; 2508 case UHF_PORT_SUSPEND: 2509 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2510 break; 2511 case UHF_PORT_RESET: 2512 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2513 if (EHCI_PS_IS_LOWSPEED(v) 2514 && sc->sc_ncomp > 0 2515 && !(sc->sc_flags & EHCIF_ETTF)) { 2516 /* 2517 * Low speed device on non-ETTF controller or 2518 * unaccompanied controller, give up ownership. 2519 */ 2520 ehci_disown(sc, index, 1); 2521 break; 2522 } 2523 /* Start reset sequence. */ 2524 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2525 EOWRITE4(sc, port, v | EHCI_PS_PR); 2526 /* Wait for reset to complete. */ 2527 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2528 if (sc->sc_dying) { 2529 return -1; 2530 } 2531 /* 2532 * An embedded transaction translator will automatically 2533 * terminate the reset sequence so there's no need to 2534 * it. 2535 */ 2536 v = EOREAD4(sc, port); 2537 if (v & EHCI_PS_PR) { 2538 /* Terminate reset sequence. */ 2539 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2540 /* Wait for HC to complete reset. */ 2541 usb_delay_ms(&sc->sc_bus, 2542 EHCI_PORT_RESET_COMPLETE); 2543 if (sc->sc_dying) { 2544 return -1; 2545 } 2546 } 2547 2548 v = EOREAD4(sc, port); 2549 USBHIST_LOG(ehcidebug, 2550 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2551 if (v & EHCI_PS_PR) { 2552 printf("%s: port reset timeout\n", 2553 device_xname(sc->sc_dev)); 2554 return USBD_TIMEOUT; 2555 } 2556 if (!(v & EHCI_PS_PE)) { 2557 /* Not a high speed device, give up ownership.*/ 2558 ehci_disown(sc, index, 0); 2559 break; 2560 } 2561 sc->sc_isreset[index] = 1; 2562 USBHIST_LOG(ehcidebug, 2563 "ehci port %d reset, status = 0x%08x", index, v, 0, 2564 0); 2565 break; 2566 case UHF_PORT_POWER: 2567 USBHIST_LOG(ehcidebug, 2568 "set port power %d (has PPC = %d)", index, 2569 sc->sc_hasppc, 0, 0); 2570 if (sc->sc_hasppc) 2571 EOWRITE4(sc, port, v | EHCI_PS_PP); 2572 break; 2573 case UHF_PORT_TEST: 2574 USBHIST_LOG(ehcidebug, "set port test %d", 2575 index, 0, 0, 0); 2576 break; 2577 case UHF_PORT_INDICATOR: 2578 USBHIST_LOG(ehcidebug, "set port ind %d", 2579 index, 0, 0, 0); 2580 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2581 break; 2582 default: 2583 return -1; 2584 } 2585 break; 2586 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2587 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2588 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2589 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2590 break; 2591 default: 2592 /* default from usbroothub */ 2593 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2594 buflen, 0, 0, 0); 2595 2596 return buflen; 2597 } 2598 2599 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2600 2601 return totlen; 2602 } 2603 2604 Static void 2605 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2606 { 2607 int port; 2608 uint32_t v; 2609 2610 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2611 2612 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2613 #ifdef DIAGNOSTIC 2614 if (sc->sc_npcomp != 0) { 2615 int i = (index-1) / sc->sc_npcomp; 2616 if (i >= sc->sc_ncomp) 2617 printf("%s: strange port\n", 2618 device_xname(sc->sc_dev)); 2619 else 2620 printf("%s: handing over %s speed device on " 2621 "port %d to %s\n", 2622 device_xname(sc->sc_dev), 2623 lowspeed ? "low" : "full", 2624 index, device_xname(sc->sc_comps[i])); 2625 } else { 2626 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2627 } 2628 #endif 2629 port = EHCI_PORTSC(index); 2630 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2631 EOWRITE4(sc, port, v | EHCI_PS_PO); 2632 } 2633 2634 Static usbd_status 2635 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2636 { 2637 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2638 usbd_status err; 2639 2640 /* Insert last in queue. */ 2641 mutex_enter(&sc->sc_lock); 2642 err = usb_insert_transfer(xfer); 2643 mutex_exit(&sc->sc_lock); 2644 if (err) 2645 return err; 2646 2647 /* Pipe isn't running, start first */ 2648 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2649 } 2650 2651 Static usbd_status 2652 ehci_root_intr_start(struct usbd_xfer *xfer) 2653 { 2654 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2655 2656 if (sc->sc_dying) 2657 return USBD_IOERROR; 2658 2659 mutex_enter(&sc->sc_lock); 2660 sc->sc_intrxfer = xfer; 2661 mutex_exit(&sc->sc_lock); 2662 2663 return USBD_IN_PROGRESS; 2664 } 2665 2666 /* Abort a root interrupt request. */ 2667 Static void 2668 ehci_root_intr_abort(struct usbd_xfer *xfer) 2669 { 2670 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2671 2672 KASSERT(mutex_owned(&sc->sc_lock)); 2673 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2674 2675 sc->sc_intrxfer = NULL; 2676 2677 xfer->ux_status = USBD_CANCELLED; 2678 usb_transfer_complete(xfer); 2679 } 2680 2681 /* Close the root pipe. */ 2682 Static void 2683 ehci_root_intr_close(struct usbd_pipe *pipe) 2684 { 2685 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2686 2687 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2688 2689 KASSERT(mutex_owned(&sc->sc_lock)); 2690 2691 sc->sc_intrxfer = NULL; 2692 } 2693 2694 Static void 2695 ehci_root_intr_done(struct usbd_xfer *xfer) 2696 { 2697 xfer->ux_hcpriv = NULL; 2698 } 2699 2700 /************************/ 2701 2702 Static ehci_soft_qh_t * 2703 ehci_alloc_sqh(ehci_softc_t *sc) 2704 { 2705 ehci_soft_qh_t *sqh; 2706 usbd_status err; 2707 int i, offs; 2708 usb_dma_t dma; 2709 2710 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2711 2712 mutex_enter(&sc->sc_lock); 2713 if (sc->sc_freeqhs == NULL) { 2714 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2715 mutex_exit(&sc->sc_lock); 2716 2717 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2718 EHCI_PAGE_SIZE, &dma); 2719 #ifdef EHCI_DEBUG 2720 if (err) 2721 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2722 #endif 2723 if (err) 2724 return NULL; 2725 2726 mutex_enter(&sc->sc_lock); 2727 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2728 offs = i * EHCI_SQH_SIZE; 2729 sqh = KERNADDR(&dma, offs); 2730 sqh->physaddr = DMAADDR(&dma, offs); 2731 sqh->dma = dma; 2732 sqh->offs = offs; 2733 sqh->next = sc->sc_freeqhs; 2734 sc->sc_freeqhs = sqh; 2735 } 2736 } 2737 sqh = sc->sc_freeqhs; 2738 sc->sc_freeqhs = sqh->next; 2739 mutex_exit(&sc->sc_lock); 2740 2741 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2742 sqh->next = NULL; 2743 return sqh; 2744 } 2745 2746 Static void 2747 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2748 { 2749 KASSERT(mutex_owned(&sc->sc_lock)); 2750 2751 sqh->next = sc->sc_freeqhs; 2752 sc->sc_freeqhs = sqh; 2753 } 2754 2755 Static ehci_soft_qtd_t * 2756 ehci_alloc_sqtd(ehci_softc_t *sc) 2757 { 2758 ehci_soft_qtd_t *sqtd = NULL; 2759 usbd_status err; 2760 int i, offs; 2761 usb_dma_t dma; 2762 2763 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2764 2765 mutex_enter(&sc->sc_lock); 2766 if (sc->sc_freeqtds == NULL) { 2767 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2768 mutex_exit(&sc->sc_lock); 2769 2770 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2771 EHCI_PAGE_SIZE, &dma); 2772 #ifdef EHCI_DEBUG 2773 if (err) 2774 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2775 #endif 2776 if (err) 2777 goto done; 2778 2779 mutex_enter(&sc->sc_lock); 2780 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2781 offs = i * EHCI_SQTD_SIZE; 2782 sqtd = KERNADDR(&dma, offs); 2783 sqtd->physaddr = DMAADDR(&dma, offs); 2784 sqtd->dma = dma; 2785 sqtd->offs = offs; 2786 2787 sqtd->nextqtd = sc->sc_freeqtds; 2788 sc->sc_freeqtds = sqtd; 2789 } 2790 } 2791 2792 sqtd = sc->sc_freeqtds; 2793 sc->sc_freeqtds = sqtd->nextqtd; 2794 mutex_exit(&sc->sc_lock); 2795 2796 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2797 sqtd->nextqtd = NULL; 2798 sqtd->xfer = NULL; 2799 2800 done: 2801 return sqtd; 2802 } 2803 2804 Static void 2805 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2806 { 2807 2808 mutex_enter(&sc->sc_lock); 2809 sqtd->nextqtd = sc->sc_freeqtds; 2810 sc->sc_freeqtds = sqtd; 2811 mutex_exit(&sc->sc_lock); 2812 } 2813 2814 Static usbd_status 2815 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2816 int alen, int rd, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2817 { 2818 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2819 ehci_soft_qtd_t *next, *cur; 2820 ehci_physaddr_t nextphys; 2821 uint32_t qtdstatus; 2822 int len, curlen, mps; 2823 int i, tog; 2824 int pages, pageoffs; 2825 size_t curoffs; 2826 vaddr_t va, va_offs; 2827 usb_dma_t *dma = &xfer->ux_dmabuf; 2828 uint16_t flags = xfer->ux_flags; 2829 paddr_t a; 2830 2831 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2832 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2833 2834 ASSERT_SLEEPABLE(); 2835 KASSERT(sp); 2836 KASSERT(alen != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2837 2838 len = alen; 2839 qtdstatus = EHCI_QTD_ACTIVE | 2840 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2841 EHCI_QTD_SET_CERR(3) 2842 ; 2843 2844 size_t nsqtd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 2845 nsqtd += ((len + EHCI_QTD_MAXTRANSFER - 1) / EHCI_QTD_MAXTRANSFER); 2846 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2847 KM_SLEEP); 2848 exfer->ex_nsqtd = nsqtd; 2849 2850 mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2851 cur = ehci_alloc_sqtd(sc); 2852 *sp = cur; 2853 if (cur == NULL) 2854 goto nomem; 2855 2856 curoffs = 0; 2857 for (size_t j = 0;;) { 2858 KASSERT(j < nsqtd); 2859 exfer->ex_sqtds[j++] = cur; 2860 2861 /* The EHCI hardware can handle at most 5 pages. */ 2862 va = (vaddr_t)KERNADDR(dma, curoffs); 2863 va_offs = EHCI_PAGE_OFFSET(va); 2864 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2865 /* we can handle it in this QTD */ 2866 curlen = len - curoffs; 2867 } else { 2868 /* must use multiple TDs, fill as much as possible. */ 2869 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2870 2871 /* the length must be a multiple of the max size */ 2872 curlen -= curlen % mps; 2873 USBHIST_LOG(ehcidebug, "multiple QTDs, curlen=%d", 2874 curlen, 0, 0, 0); 2875 KASSERT(curlen != 0); 2876 } 2877 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", len, 2878 curlen, curoffs, 0); 2879 2880 /* 2881 * Allocate another transfer if there's more data left, 2882 * or if force last short transfer flag is set and we're 2883 * allocating a multiple of the max packet size. 2884 */ 2885 2886 if (curoffs + curlen != len || 2887 ((curlen % mps) == 0 && !rd && curlen != 0 && 2888 (flags & USBD_FORCE_SHORT_XFER))) { 2889 next = ehci_alloc_sqtd(sc); 2890 if (next == NULL) 2891 goto nomem; 2892 nextphys = htole32(next->physaddr); 2893 } else { 2894 next = NULL; 2895 nextphys = EHCI_NULL; 2896 } 2897 2898 /* Find number of pages we'll be using, insert dma addresses */ 2899 pages = EHCI_NPAGES(curlen); 2900 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2901 pageoffs = EHCI_PAGE(curoffs); 2902 for (i = 0; i < pages; i++) { 2903 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2904 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2905 /* Cast up to avoid compiler warnings */ 2906 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2907 } 2908 2909 /* First buffer pointer requires a page offset to start at */ 2910 cur->qtd.qtd_buffer[0] |= htole32(va_offs); 2911 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2912 cur->qtd.qtd_status = htole32(qtdstatus); 2913 cur->nextqtd = next; 2914 cur->xfer = xfer; 2915 cur->bufoff = curoffs; 2916 cur->tdlen = curlen; 2917 cur->len = 0; 2918 2919 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2920 curoffs, curoffs + curlen, 0, 0); 2921 2922 /* 2923 * adjust the toggle based on the number of packets in this 2924 * qtd 2925 */ 2926 if (((curlen + mps - 1) / mps) & 1) { 2927 tog ^= 1; 2928 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2929 } 2930 if (next == NULL) 2931 break; 2932 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2933 if (len) 2934 curoffs += curlen; 2935 cur = next; 2936 } 2937 if (ep) 2938 *ep = cur; 2939 2940 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", *sp, cur, 0, 0); 2941 2942 return USBD_NORMAL_COMPLETION; 2943 2944 nomem: 2945 ehci_free_sqtds(sc, exfer); 2946 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2947 return USBD_NOMEM; 2948 } 2949 2950 Static void 2951 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2952 { 2953 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2954 USBHIST_LOG(ehcidebug, "exfer=%p", exfer, 0, 0, 0); 2955 2956 mutex_enter(&sc->sc_lock); 2957 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2958 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2959 2960 if (sqtd == NULL) 2961 break; 2962 2963 sqtd->nextqtd = sc->sc_freeqtds; 2964 sc->sc_freeqtds = sqtd->nextqtd; 2965 } 2966 mutex_exit(&sc->sc_lock); 2967 } 2968 2969 Static void 2970 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2971 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2972 { 2973 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2974 ehci_soft_qtd_t *sqtd, *prev; 2975 int tog = *toggle; 2976 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2977 int len = length; 2978 size_t i; 2979 2980 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2981 USBHIST_LOG(ehcidebug, "xfer=%p len %d isread %d toggle %d", xfer, 2982 len, isread, *toggle); 2983 2984 sqtd = prev = NULL; 2985 for (i = 0; i < exfer->ex_nsqtd; i++, prev = sqtd) { 2986 sqtd = exfer->ex_sqtds[i]; 2987 vaddr_t va = (vaddr_t)KERNADDR(&xfer->ux_dmabuf, sqtd->bufoff); 2988 sqtd->len = sqtd->tdlen; 2989 if (len < sqtd->len) { 2990 sqtd->len = len; 2991 } 2992 2993 USBHIST_LOG(ehcidebug, "sqtd[%d]=%p prev %p len %d", i, sqtd, 2994 prev, sqtd->len); 2995 2996 if (prev) { 2997 prev->nextqtd = sqtd; 2998 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2999 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3000 } 3001 usb_syncmem(&sqtd->dma, 3002 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3003 sizeof(sqtd->qtd.qtd_status), 3004 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3005 usb_syncmem(&sqtd->dma, 3006 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3007 sizeof(sqtd->qtd.qtd_buffer[0]), 3008 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3009 3010 sqtd->qtd.qtd_buffer[0] &= ~htole32(EHCI_PAGE_MASK); 3011 sqtd->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3012 /* Reset ... */ 3013 sqtd->qtd.qtd_status &= ~htole32( 3014 EHCI_QTD_STATUS_MASK | 3015 EHCI_QTD_PID_MASK | 3016 EHCI_QTD_CERR_MASK | 3017 EHCI_QTD_C_PAGE_MASK | 3018 EHCI_QTD_BYTES_MASK | 3019 EHCI_QTD_TOGGLE_MASK); 3020 sqtd->qtd.qtd_status |= htole32( 3021 EHCI_QTD_ACTIVE | 3022 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3023 EHCI_QTD_SET_BYTES(sqtd->len) | 3024 EHCI_QTD_SET_CERR(3) | 3025 EHCI_QTD_SET_TOGGLE(tog)); 3026 3027 usb_syncmem(&sqtd->dma, 3028 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3029 sizeof(sqtd->qtd.qtd_status), 3030 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3031 usb_syncmem(&sqtd->dma, 3032 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3033 sizeof(sqtd->qtd.qtd_buffer[0]), 3034 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3035 3036 if (((sqtd->len + mps - 1) / mps) & 1) { 3037 tog ^= 1; 3038 } 3039 3040 len -= sqtd->len; 3041 if (len == 0) 3042 break; 3043 } 3044 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu i %zu", 3045 xfer, length, len, mps, exfer->ex_nsqtd, i); 3046 3047 if (i < exfer->ex_nsqtd) { 3048 /* 3049 * The full allocation chain wasn't used, so we need to 3050 * terminate it. 3051 */ 3052 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3053 } 3054 *lsqtd = sqtd; 3055 *toggle = tog; 3056 } 3057 3058 Static ehci_soft_itd_t * 3059 ehci_alloc_itd(ehci_softc_t *sc) 3060 { 3061 struct ehci_soft_itd *itd, *freeitd; 3062 usbd_status err; 3063 usb_dma_t dma; 3064 3065 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3066 3067 mutex_enter(&sc->sc_lock); 3068 3069 freeitd = LIST_FIRST(&sc->sc_freeitds); 3070 if (freeitd == NULL) { 3071 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3072 mutex_exit(&sc->sc_lock); 3073 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3074 EHCI_PAGE_SIZE, &dma); 3075 3076 if (err) { 3077 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 0); 3078 return NULL; 3079 } 3080 mutex_enter(&sc->sc_lock); 3081 3082 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3083 int offs = i * EHCI_ITD_SIZE; 3084 itd = KERNADDR(&dma, offs); 3085 itd->physaddr = DMAADDR(&dma, offs); 3086 itd->dma = dma; 3087 itd->offs = offs; 3088 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3089 } 3090 freeitd = LIST_FIRST(&sc->sc_freeitds); 3091 } 3092 3093 itd = freeitd; 3094 LIST_REMOVE(itd, free_list); 3095 mutex_exit(&sc->sc_lock); 3096 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3097 3098 itd->frame_list.next = NULL; 3099 itd->frame_list.prev = NULL; 3100 itd->xfer_next = NULL; 3101 itd->slot = 0; 3102 3103 return itd; 3104 } 3105 3106 Static ehci_soft_sitd_t * 3107 ehci_alloc_sitd(ehci_softc_t *sc) 3108 { 3109 struct ehci_soft_sitd *sitd, *freesitd; 3110 usbd_status err; 3111 int i, offs; 3112 usb_dma_t dma; 3113 3114 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3115 3116 mutex_enter(&sc->sc_lock); 3117 freesitd = LIST_FIRST(&sc->sc_freesitds); 3118 if (freesitd == NULL) { 3119 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3120 mutex_exit(&sc->sc_lock); 3121 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3122 EHCI_PAGE_SIZE, &dma); 3123 3124 if (err) { 3125 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 3126 0); 3127 return NULL; 3128 } 3129 3130 mutex_enter(&sc->sc_lock); 3131 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3132 offs = i * EHCI_SITD_SIZE; 3133 sitd = KERNADDR(&dma, offs); 3134 sitd->physaddr = DMAADDR(&dma, offs); 3135 sitd->dma = dma; 3136 sitd->offs = offs; 3137 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3138 } 3139 freesitd = LIST_FIRST(&sc->sc_freesitds); 3140 } 3141 3142 sitd = freesitd; 3143 LIST_REMOVE(sitd, free_list); 3144 mutex_exit(&sc->sc_lock); 3145 3146 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3147 3148 sitd->frame_list.next = NULL; 3149 sitd->frame_list.prev = NULL; 3150 sitd->xfer_next = NULL; 3151 sitd->slot = 0; 3152 3153 return sitd; 3154 } 3155 3156 /****************/ 3157 3158 /* 3159 * Close a reqular pipe. 3160 * Assumes that there are no pending transactions. 3161 */ 3162 Static void 3163 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3164 { 3165 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3166 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3167 ehci_soft_qh_t *sqh = epipe->sqh; 3168 3169 KASSERT(mutex_owned(&sc->sc_lock)); 3170 3171 ehci_rem_qh(sc, sqh, head); 3172 ehci_free_sqh(sc, epipe->sqh); 3173 } 3174 3175 /* 3176 * Abort a device request. 3177 * If this routine is called at splusb() it guarantees that the request 3178 * will be removed from the hardware scheduling and that the callback 3179 * for it will be called with USBD_CANCELLED status. 3180 * It's impossible to guarantee that the requested transfer will not 3181 * have happened since the hardware runs concurrently. 3182 * If the transaction has already happened we rely on the ordinary 3183 * interrupt processing to process it. 3184 * XXX This is most probably wrong. 3185 * XXXMRG this doesn't make sense anymore. 3186 */ 3187 Static void 3188 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3189 { 3190 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3191 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3192 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3193 ehci_soft_qh_t *sqh = epipe->sqh; 3194 ehci_soft_qtd_t *sqtd; 3195 ehci_physaddr_t cur; 3196 uint32_t qhstatus; 3197 int hit; 3198 int wake; 3199 3200 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3201 3202 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3203 3204 KASSERT(mutex_owned(&sc->sc_lock)); 3205 ASSERT_SLEEPABLE(); 3206 3207 if (sc->sc_dying) { 3208 /* If we're dying, just do the software part. */ 3209 xfer->ux_status = status; /* make software ignore it */ 3210 callout_stop(&xfer->ux_callout); 3211 usb_transfer_complete(xfer); 3212 return; 3213 } 3214 3215 /* 3216 * If an abort is already in progress then just wait for it to 3217 * complete and return. 3218 */ 3219 if (xfer->ux_hcflags & UXFER_ABORTING) { 3220 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3221 #ifdef DIAGNOSTIC 3222 if (status == USBD_TIMEOUT) 3223 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3224 #endif 3225 /* Override the status which might be USBD_TIMEOUT. */ 3226 xfer->ux_status = status; 3227 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3228 0, 0, 0, 0); 3229 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3230 while (xfer->ux_hcflags & UXFER_ABORTING) 3231 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3232 return; 3233 } 3234 xfer->ux_hcflags |= UXFER_ABORTING; 3235 3236 /* 3237 * Step 1: Make interrupt routine and hardware ignore xfer. 3238 */ 3239 xfer->ux_status = status; /* make software ignore it */ 3240 callout_stop(&xfer->ux_callout); 3241 3242 usb_syncmem(&sqh->dma, 3243 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3244 sizeof(sqh->qh.qh_qtd.qtd_status), 3245 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3246 qhstatus = sqh->qh.qh_qtd.qtd_status; 3247 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3248 usb_syncmem(&sqh->dma, 3249 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3250 sizeof(sqh->qh.qh_qtd.qtd_status), 3251 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3252 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3253 usb_syncmem(&sqtd->dma, 3254 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3255 sizeof(sqtd->qtd.qtd_status), 3256 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3257 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3258 usb_syncmem(&sqtd->dma, 3259 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3260 sizeof(sqtd->qtd.qtd_status), 3261 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3262 if (sqtd == exfer->ex_sqtdend) 3263 break; 3264 } 3265 3266 /* 3267 * Step 2: Wait until we know hardware has finished any possible 3268 * use of the xfer. Also make sure the soft interrupt routine 3269 * has run. 3270 */ 3271 ehci_sync_hc(sc); 3272 sc->sc_softwake = 1; 3273 usb_schedsoftintr(&sc->sc_bus); 3274 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3275 3276 /* 3277 * Step 3: Remove any vestiges of the xfer from the hardware. 3278 * The complication here is that the hardware may have executed 3279 * beyond the xfer we're trying to abort. So as we're scanning 3280 * the TDs of this xfer we check if the hardware points to 3281 * any of them. 3282 */ 3283 3284 usb_syncmem(&sqh->dma, 3285 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3286 sizeof(sqh->qh.qh_curqtd), 3287 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3288 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3289 hit = 0; 3290 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3291 hit |= cur == sqtd->physaddr; 3292 if (sqtd == exfer->ex_sqtdend) 3293 break; 3294 } 3295 sqtd = sqtd->nextqtd; 3296 /* Zap curqtd register if hardware pointed inside the xfer. */ 3297 if (hit && sqtd != NULL) { 3298 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3299 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3300 usb_syncmem(&sqh->dma, 3301 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3302 sizeof(sqh->qh.qh_curqtd), 3303 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3304 sqh->qh.qh_qtd.qtd_status = qhstatus; 3305 usb_syncmem(&sqh->dma, 3306 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3307 sizeof(sqh->qh.qh_qtd.qtd_status), 3308 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3309 } else { 3310 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3311 usb_syncmem(&sqh->dma, 3312 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3313 sizeof(sqh->qh.qh_curqtd), 3314 BUS_DMASYNC_PREREAD); 3315 } 3316 3317 /* 3318 * Step 4: Execute callback. 3319 */ 3320 #ifdef DIAGNOSTIC 3321 exfer->ex_isdone = true; 3322 #endif 3323 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3324 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3325 usb_transfer_complete(xfer); 3326 if (wake) { 3327 cv_broadcast(&xfer->ux_hccv); 3328 } 3329 3330 KASSERT(mutex_owned(&sc->sc_lock)); 3331 } 3332 3333 Static void 3334 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3335 { 3336 ehci_isoc_trans_t trans_status; 3337 struct ehci_xfer *exfer; 3338 ehci_softc_t *sc; 3339 struct ehci_soft_itd *itd; 3340 struct ehci_soft_sitd *sitd; 3341 int i, wake; 3342 3343 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3344 3345 exfer = EHCI_XFER2EXFER(xfer); 3346 sc = EHCI_XFER2SC(xfer); 3347 3348 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3349 3350 KASSERT(mutex_owned(&sc->sc_lock)); 3351 3352 if (sc->sc_dying) { 3353 xfer->ux_status = status; 3354 callout_stop(&xfer->ux_callout); 3355 usb_transfer_complete(xfer); 3356 return; 3357 } 3358 3359 if (xfer->ux_hcflags & UXFER_ABORTING) { 3360 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3361 3362 #ifdef DIAGNOSTIC 3363 if (status == USBD_TIMEOUT) 3364 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3365 #endif 3366 3367 xfer->ux_status = status; 3368 USBHIST_LOG(ehcidebug, 3369 "waiting for abort to finish", 0, 0, 0, 0); 3370 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3371 while (xfer->ux_hcflags & UXFER_ABORTING) 3372 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3373 goto done; 3374 } 3375 xfer->ux_hcflags |= UXFER_ABORTING; 3376 3377 xfer->ux_status = status; 3378 callout_stop(&xfer->ux_callout); 3379 3380 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3381 for (itd = exfer->ex_itdstart; itd != NULL; 3382 itd = itd->xfer_next) { 3383 usb_syncmem(&itd->dma, 3384 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3385 sizeof(itd->itd.itd_ctl), 3386 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3387 3388 for (i = 0; i < 8; i++) { 3389 trans_status = le32toh(itd->itd.itd_ctl[i]); 3390 trans_status &= ~EHCI_ITD_ACTIVE; 3391 itd->itd.itd_ctl[i] = htole32(trans_status); 3392 } 3393 3394 usb_syncmem(&itd->dma, 3395 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3396 sizeof(itd->itd.itd_ctl), 3397 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3398 } 3399 } else { 3400 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3401 sitd = sitd->xfer_next) { 3402 usb_syncmem(&sitd->dma, 3403 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3404 sizeof(sitd->sitd.sitd_buffer), 3405 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3406 3407 trans_status = le32toh(sitd->sitd.sitd_trans); 3408 trans_status &= ~EHCI_SITD_ACTIVE; 3409 sitd->sitd.sitd_trans = htole32(trans_status); 3410 3411 usb_syncmem(&sitd->dma, 3412 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3413 sizeof(sitd->sitd.sitd_buffer), 3414 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3415 } 3416 } 3417 3418 sc->sc_softwake = 1; 3419 usb_schedsoftintr(&sc->sc_bus); 3420 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3421 3422 #ifdef DIAGNOSTIC 3423 exfer->ex_isdone = true; 3424 #endif 3425 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3426 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3427 usb_transfer_complete(xfer); 3428 if (wake) { 3429 cv_broadcast(&xfer->ux_hccv); 3430 } 3431 3432 done: 3433 KASSERT(mutex_owned(&sc->sc_lock)); 3434 return; 3435 } 3436 3437 Static void 3438 ehci_timeout(void *addr) 3439 { 3440 struct usbd_xfer *xfer = addr; 3441 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3442 struct usbd_pipe *pipe = xfer->ux_pipe; 3443 struct usbd_device *dev = pipe->up_dev; 3444 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3445 3446 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3447 3448 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3449 #ifdef EHCI_DEBUG 3450 if (ehcidebug > 1) 3451 usbd_dump_pipe(pipe); 3452 #endif 3453 3454 if (sc->sc_dying) { 3455 mutex_enter(&sc->sc_lock); 3456 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3457 mutex_exit(&sc->sc_lock); 3458 return; 3459 } 3460 3461 /* Execute the abort in a process context. */ 3462 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3463 USB_TASKQ_MPSAFE); 3464 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3465 } 3466 3467 Static void 3468 ehci_timeout_task(void *addr) 3469 { 3470 struct usbd_xfer *xfer = addr; 3471 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3472 3473 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3474 3475 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3476 3477 mutex_enter(&sc->sc_lock); 3478 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3479 mutex_exit(&sc->sc_lock); 3480 } 3481 3482 /************************/ 3483 3484 Static int 3485 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3486 { 3487 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3488 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3489 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3490 usb_device_request_t *req = &xfer->ux_request; 3491 ehci_soft_qtd_t *setup, *status, *next; 3492 int isread = req->bmRequestType & UT_READ; 3493 int len = xfer->ux_bufsize; 3494 int err; 3495 3496 exfer->ex_type = EX_CTRL; 3497 exfer->ex_status = NULL; 3498 exfer->ex_data = NULL; 3499 exfer->ex_setup = ehci_alloc_sqtd(sc); 3500 if (exfer->ex_setup == NULL) { 3501 err = ENOMEM; 3502 goto bad1; 3503 } 3504 exfer->ex_status = ehci_alloc_sqtd(sc); 3505 if (exfer->ex_status == NULL) { 3506 err = ENOMEM; 3507 goto bad2; 3508 } 3509 setup = exfer->ex_setup; 3510 status = exfer->ex_status; 3511 exfer->ex_nsqtd = 0; 3512 next = status; 3513 /* Set up data transaction */ 3514 if (len != 0) { 3515 ehci_soft_qtd_t *end; 3516 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3517 &exfer->ex_data, &end); 3518 if (err) 3519 goto bad3; 3520 next = exfer->ex_data; 3521 } 3522 3523 /* Clear toggle */ 3524 setup->qtd.qtd_status = htole32( 3525 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3526 EHCI_QTD_SET_TOGGLE(0) | 3527 EHCI_QTD_SET_BYTES(sizeof(*req)) 3528 ); 3529 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3530 setup->qtd.qtd_buffer_hi[0] = 0; 3531 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3532 setup->nextqtd = next; 3533 setup->xfer = xfer; 3534 setup->tdlen = setup->len = sizeof(*req); 3535 3536 status->qtd.qtd_status = htole32( 3537 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3538 EHCI_QTD_SET_TOGGLE(1) | 3539 EHCI_QTD_IOC 3540 ); 3541 status->qtd.qtd_buffer[0] = 0; 3542 status->qtd.qtd_buffer_hi[0] = 0; 3543 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3544 status->nextqtd = NULL; 3545 status->xfer = xfer; 3546 status->tdlen = status->len = 0; 3547 3548 return 0; 3549 bad3: 3550 ehci_free_sqtd(sc, exfer->ex_status); 3551 bad2: 3552 ehci_free_sqtd(sc, exfer->ex_setup); 3553 bad1: 3554 return err; 3555 } 3556 3557 Static void 3558 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3559 { 3560 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3561 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3562 3563 KASSERT(ex->ex_type == EX_CTRL); 3564 3565 ehci_free_sqtd(sc, ex->ex_setup); 3566 ehci_free_sqtd(sc, ex->ex_status); 3567 ehci_free_sqtds(sc, ex); 3568 if (ex->ex_nsqtd) 3569 kmem_free(ex->ex_sqtds, 3570 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3571 } 3572 3573 Static usbd_status 3574 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3575 { 3576 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3577 usbd_status err; 3578 3579 /* Insert last in queue. */ 3580 mutex_enter(&sc->sc_lock); 3581 err = usb_insert_transfer(xfer); 3582 mutex_exit(&sc->sc_lock); 3583 if (err) 3584 return err; 3585 3586 /* Pipe isn't running, start first */ 3587 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3588 } 3589 3590 Static usbd_status 3591 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3592 { 3593 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3594 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3595 usb_device_request_t *req = &xfer->ux_request; 3596 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3597 ehci_soft_qtd_t *setup, *status, *next; 3598 ehci_soft_qh_t *sqh; 3599 3600 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3601 3602 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3603 3604 if (sc->sc_dying) 3605 return USBD_IOERROR; 3606 3607 const int isread = req->bmRequestType & UT_READ; 3608 const int len = UGETW(req->wLength); 3609 3610 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3611 "wValue=0x%04x, wIndex=0x%04x", 3612 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3613 UGETW(req->wIndex)); 3614 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3615 len, epipe->pipe.up_dev->ud_addr, 3616 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3617 3618 sqh = epipe->sqh; 3619 3620 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3621 "address QH %" __PRIuBIT " pipe %d\n", 3622 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3623 epipe->pipe.up_dev->ud_addr); 3624 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3625 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3626 "MPS QH %" __PRIuBIT " pipe %d\n", 3627 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3628 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3629 3630 setup = exfer->ex_setup; 3631 status = exfer->ex_status; 3632 3633 USBHIST_LOG(ehcidebug, "setup %p status %p data %p", 3634 setup, status, exfer->ex_data, 0); 3635 KASSERTMSG(setup != NULL && status != NULL, 3636 "Failed memory allocation, setup %p status %p", 3637 setup, status); 3638 3639 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3640 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3641 3642 /* Clear toggle */ 3643 setup->qtd.qtd_status &= ~htole32( 3644 EHCI_QTD_STATUS_MASK | 3645 EHCI_QTD_BYTES_MASK | 3646 EHCI_QTD_TOGGLE_MASK | 3647 EHCI_QTD_CERR_MASK 3648 ); 3649 setup->qtd.qtd_status |= htole32( 3650 EHCI_QTD_ACTIVE | 3651 EHCI_QTD_SET_CERR(3) | 3652 EHCI_QTD_SET_TOGGLE(0) | 3653 EHCI_QTD_SET_BYTES(sizeof(*req)) 3654 ); 3655 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3656 setup->qtd.qtd_buffer_hi[0] = 0; 3657 3658 next = status; 3659 status->qtd.qtd_status &= ~htole32( 3660 EHCI_QTD_STATUS_MASK | 3661 EHCI_QTD_PID_MASK | 3662 EHCI_QTD_BYTES_MASK | 3663 EHCI_QTD_TOGGLE_MASK | 3664 EHCI_QTD_CERR_MASK 3665 ); 3666 status->qtd.qtd_status |= htole32( 3667 EHCI_QTD_ACTIVE | 3668 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3669 EHCI_QTD_SET_CERR(3) | 3670 EHCI_QTD_SET_TOGGLE(1) | 3671 EHCI_QTD_SET_BYTES(0) | 3672 EHCI_QTD_IOC 3673 ); 3674 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3675 3676 KASSERT(exfer->ex_isdone); 3677 #ifdef DIAGNOSTIC 3678 exfer->ex_isdone = false; 3679 #endif 3680 3681 /* Set up data transaction */ 3682 if (len != 0) { 3683 ehci_soft_qtd_t *end; 3684 3685 /* Start toggle at 1. */ 3686 int toggle = 1; 3687 next = exfer->ex_data; 3688 KASSERTMSG(next != NULL, "Failed memory allocation"); 3689 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3690 end->nextqtd = status; 3691 end->qtd.qtd_next = end->qtd.qtd_altnext = 3692 htole32(status->physaddr); 3693 3694 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3695 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3696 3697 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3698 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3699 } 3700 3701 setup->nextqtd = next; 3702 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3703 3704 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3705 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3706 3707 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3708 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3709 3710 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3711 3712 #ifdef EHCI_DEBUG 3713 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3714 ehci_dump_sqh(sqh); 3715 ehci_dump_sqtds(setup); 3716 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3717 #endif 3718 3719 mutex_enter(&sc->sc_lock); 3720 3721 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3722 ehci_set_qh_qtd(sqh, setup); 3723 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3724 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3725 ehci_timeout, xfer); 3726 } 3727 ehci_add_intr_list(sc, exfer); 3728 xfer->ux_status = USBD_IN_PROGRESS; 3729 mutex_exit(&sc->sc_lock); 3730 3731 #if 0 3732 #ifdef EHCI_DEBUG 3733 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3734 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3735 // delay(10000); 3736 ehci_dump_regs(sc); 3737 ehci_dump_sqh(sc->sc_async_head); 3738 ehci_dump_sqh(sqh); 3739 ehci_dump_sqtds(setup); 3740 #endif 3741 #endif 3742 3743 if (sc->sc_bus.ub_usepolling) 3744 ehci_waitintr(sc, xfer); 3745 3746 return USBD_IN_PROGRESS; 3747 } 3748 3749 Static void 3750 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3751 { 3752 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3753 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3754 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3755 usb_device_request_t *req = &xfer->ux_request; 3756 int len = UGETW(req->wLength); 3757 int rd = req->bmRequestType & UT_READ; 3758 3759 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3760 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3761 3762 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3763 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3764 3765 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3766 ehci_del_intr_list(sc, ex); /* remove from active list */ 3767 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3768 BUS_DMASYNC_POSTWRITE); 3769 if (len) 3770 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3771 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3772 } 3773 3774 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3775 } 3776 3777 /* Abort a device control request. */ 3778 Static void 3779 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3780 { 3781 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3782 3783 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3784 ehci_abort_xfer(xfer, USBD_CANCELLED); 3785 } 3786 3787 /* Close a device control pipe. */ 3788 Static void 3789 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3790 { 3791 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3792 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3793 3794 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3795 3796 KASSERT(mutex_owned(&sc->sc_lock)); 3797 3798 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3799 3800 ehci_close_pipe(pipe, sc->sc_async_head); 3801 } 3802 3803 /* 3804 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3805 * qTD status, or miss signalling occasionally under heavy load. If the host 3806 * machine is too fast, we we can miss transaction completion - when we scan 3807 * the active list the transaction still seems to be active. This generally 3808 * exhibits itself as a umass stall that never recovers. 3809 * 3810 * We work around this behaviour by setting up this callback after any softintr 3811 * that completes with transactions still pending, giving us another chance to 3812 * check for completion after the writeback has taken place. 3813 */ 3814 Static void 3815 ehci_intrlist_timeout(void *arg) 3816 { 3817 ehci_softc_t *sc = arg; 3818 3819 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3820 3821 usb_schedsoftintr(&sc->sc_bus); 3822 } 3823 3824 /************************/ 3825 3826 Static int 3827 ehci_device_bulk_init(struct usbd_xfer *xfer) 3828 { 3829 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3830 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3831 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3832 int endpt = ed->bEndpointAddress; 3833 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3834 int len = xfer->ux_bufsize; 3835 int err = 0; 3836 3837 exfer->ex_type = EX_BULK; 3838 exfer->ex_nsqtd = 0; 3839 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3840 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 3841 3842 return err; 3843 } 3844 3845 Static void 3846 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3847 { 3848 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3849 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3850 3851 KASSERT(ex->ex_type == EX_BULK); 3852 3853 ehci_free_sqtds(sc, ex); 3854 if (ex->ex_nsqtd) 3855 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3856 } 3857 3858 Static usbd_status 3859 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3860 { 3861 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3862 usbd_status err; 3863 3864 /* Insert last in queue. */ 3865 mutex_enter(&sc->sc_lock); 3866 err = usb_insert_transfer(xfer); 3867 mutex_exit(&sc->sc_lock); 3868 if (err) 3869 return err; 3870 3871 /* Pipe isn't running, start first */ 3872 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3873 } 3874 3875 Static usbd_status 3876 ehci_device_bulk_start(struct usbd_xfer *xfer) 3877 { 3878 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3879 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3880 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3881 ehci_soft_qh_t *sqh; 3882 ehci_soft_qtd_t *end; 3883 int len, isread, endpt; 3884 3885 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3886 3887 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3888 xfer, xfer->ux_length, xfer->ux_flags, 0); 3889 3890 if (sc->sc_dying) 3891 return USBD_IOERROR; 3892 3893 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3894 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3895 3896 len = xfer->ux_length; 3897 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3898 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3899 sqh = epipe->sqh; 3900 3901 KASSERT(exfer->ex_isdone); 3902 #ifdef DIAGNOSTIC 3903 exfer->ex_isdone = false; 3904 #endif 3905 3906 /* Take lock here to protect nexttoggle */ 3907 mutex_enter(&sc->sc_lock); 3908 3909 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3910 3911 exfer->ex_sqtdend = end; 3912 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3913 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3914 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3915 3916 #ifdef EHCI_DEBUG 3917 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3918 ehci_dump_sqh(sqh); 3919 ehci_dump_sqtds(exfer->ex_sqtdstart); 3920 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3921 #endif 3922 3923 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3924 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3925 3926 /* also does usb_syncmem(sqh) */ 3927 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3928 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3929 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3930 ehci_timeout, xfer); 3931 } 3932 ehci_add_intr_list(sc, exfer); 3933 xfer->ux_status = USBD_IN_PROGRESS; 3934 mutex_exit(&sc->sc_lock); 3935 3936 #if 0 3937 #ifdef EHCI_DEBUG 3938 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3939 // delay(10000); 3940 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3941 ehci_dump_regs(sc); 3942 #if 0 3943 printf("async_head:\n"); 3944 ehci_dump_sqh(sc->sc_async_head); 3945 #endif 3946 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3947 ehci_dump_sqh(sqh); 3948 ehci_dump_sqtds(exfer->ex_sqtdstart); 3949 #endif 3950 #endif 3951 3952 if (sc->sc_bus.ub_usepolling) 3953 ehci_waitintr(sc, xfer); 3954 3955 return USBD_IN_PROGRESS; 3956 } 3957 3958 Static void 3959 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3960 { 3961 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3962 3963 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3964 ehci_abort_xfer(xfer, USBD_CANCELLED); 3965 } 3966 3967 /* 3968 * Close a device bulk pipe. 3969 */ 3970 Static void 3971 ehci_device_bulk_close(struct usbd_pipe *pipe) 3972 { 3973 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3974 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3975 3976 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3977 3978 KASSERT(mutex_owned(&sc->sc_lock)); 3979 3980 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3981 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3982 ehci_close_pipe(pipe, sc->sc_async_head); 3983 } 3984 3985 Static void 3986 ehci_device_bulk_done(struct usbd_xfer *xfer) 3987 { 3988 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3989 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3990 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3991 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3992 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3993 3994 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3995 3996 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 3997 0, 0); 3998 3999 KASSERT(mutex_owned(&sc->sc_lock)); 4000 4001 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4002 ehci_del_intr_list(sc, ex); /* remove from active list */ 4003 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4004 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4005 } 4006 4007 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 4008 } 4009 4010 /************************/ 4011 4012 Static usbd_status 4013 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4014 { 4015 struct ehci_soft_islot *isp; 4016 int islot, lev; 4017 4018 /* Find a poll rate that is large enough. */ 4019 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4020 if (EHCI_ILEV_IVAL(lev) <= ival) 4021 break; 4022 4023 /* Pick an interrupt slot at the right level. */ 4024 /* XXX could do better than picking at random */ 4025 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4026 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4027 4028 sqh->islot = islot; 4029 isp = &sc->sc_islots[islot]; 4030 mutex_enter(&sc->sc_lock); 4031 ehci_add_qh(sc, sqh, isp->sqh); 4032 mutex_exit(&sc->sc_lock); 4033 4034 return USBD_NORMAL_COMPLETION; 4035 } 4036 4037 4038 Static int 4039 ehci_device_intr_init(struct usbd_xfer *xfer) 4040 { 4041 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4042 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4043 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4044 int endpt = ed->bEndpointAddress; 4045 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4046 int len = xfer->ux_bufsize; 4047 int err; 4048 4049 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4050 4051 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4052 xfer->ux_flags, 0); 4053 4054 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4055 KASSERT(len != 0); 4056 4057 exfer->ex_type = EX_INTR; 4058 exfer->ex_nsqtd = 0; 4059 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4060 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 4061 4062 return err; 4063 } 4064 4065 Static void 4066 ehci_device_intr_fini(struct usbd_xfer *xfer) 4067 { 4068 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4069 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4070 4071 KASSERT(ex->ex_type == EX_BULK); 4072 4073 ehci_free_sqtds(sc, ex); 4074 if (ex->ex_nsqtd) 4075 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4076 } 4077 4078 Static usbd_status 4079 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4080 { 4081 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4082 usbd_status err; 4083 4084 /* Insert last in queue. */ 4085 mutex_enter(&sc->sc_lock); 4086 err = usb_insert_transfer(xfer); 4087 mutex_exit(&sc->sc_lock); 4088 if (err) 4089 return err; 4090 4091 /* 4092 * Pipe isn't running (otherwise err would be USBD_INPROG), 4093 * so start it first. 4094 */ 4095 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4096 } 4097 4098 Static usbd_status 4099 ehci_device_intr_start(struct usbd_xfer *xfer) 4100 { 4101 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4102 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4103 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4104 ehci_soft_qtd_t *end; 4105 ehci_soft_qh_t *sqh; 4106 int len, isread, endpt; 4107 4108 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4109 4110 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4111 xfer->ux_flags, 0); 4112 4113 if (sc->sc_dying) 4114 return USBD_IOERROR; 4115 4116 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4117 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4118 4119 len = xfer->ux_length; 4120 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4121 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4122 sqh = epipe->sqh; 4123 4124 KASSERT(exfer->ex_isdone); 4125 #ifdef DIAGNOSTIC 4126 exfer->ex_isdone = false; 4127 #endif 4128 4129 /* Take lock to protect nexttoggle */ 4130 mutex_enter(&sc->sc_lock); 4131 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4132 4133 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4134 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4135 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4136 exfer->ex_sqtdend = end; 4137 4138 #ifdef EHCI_DEBUG 4139 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 4140 ehci_dump_sqh(sqh); 4141 ehci_dump_sqtds(exfer->ex_sqtdstart); 4142 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 4143 #endif 4144 4145 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4146 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4147 4148 /* also does usb_syncmem(sqh) */ 4149 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4150 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4151 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4152 ehci_timeout, xfer); 4153 } 4154 ehci_add_intr_list(sc, exfer); 4155 xfer->ux_status = USBD_IN_PROGRESS; 4156 mutex_exit(&sc->sc_lock); 4157 4158 #if 0 4159 #ifdef EHCI_DEBUG 4160 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4161 // delay(10000); 4162 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4163 ehci_dump_regs(sc); 4164 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4165 ehci_dump_sqh(sqh); 4166 ehci_dump_sqtds(exfer->ex_sqtdstart); 4167 #endif 4168 #endif 4169 4170 if (sc->sc_bus.ub_usepolling) 4171 ehci_waitintr(sc, xfer); 4172 4173 return USBD_IN_PROGRESS; 4174 } 4175 4176 Static void 4177 ehci_device_intr_abort(struct usbd_xfer *xfer) 4178 { 4179 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4180 4181 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4182 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4183 4184 /* 4185 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4186 * async doorbell. That's dependent on the async list, wheras 4187 * intr xfers are periodic, should not use this? 4188 */ 4189 ehci_abort_xfer(xfer, USBD_CANCELLED); 4190 } 4191 4192 Static void 4193 ehci_device_intr_close(struct usbd_pipe *pipe) 4194 { 4195 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4196 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4197 struct ehci_soft_islot *isp; 4198 4199 KASSERT(mutex_owned(&sc->sc_lock)); 4200 4201 isp = &sc->sc_islots[epipe->sqh->islot]; 4202 ehci_close_pipe(pipe, isp->sqh); 4203 } 4204 4205 Static void 4206 ehci_device_intr_done(struct usbd_xfer *xfer) 4207 { 4208 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4209 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4210 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4211 ehci_soft_qh_t *sqh; 4212 int len, isread, endpt; 4213 4214 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4215 4216 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4217 0, 0); 4218 4219 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4220 4221 if (xfer->ux_pipe->up_repeat) { 4222 4223 KASSERT(exfer->ex_isdone); 4224 #ifdef DIAGNOSTIC 4225 exfer->ex_isdone = false; 4226 #endif 4227 4228 len = xfer->ux_length; 4229 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4230 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4231 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4232 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4233 sqh = epipe->sqh; 4234 4235 ehci_soft_qtd_t *end; 4236 ehci_reset_sqtd_chain(sc, xfer, len, isread, 4237 &epipe->nexttoggle, &end); 4238 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4239 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4240 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4241 4242 exfer->ex_sqtdend = end; 4243 4244 /* also does usb_syncmem(sqh) */ 4245 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4246 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4247 callout_reset(&xfer->ux_callout, 4248 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4249 } 4250 4251 xfer->ux_status = USBD_IN_PROGRESS; 4252 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4253 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4254 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4255 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4256 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4257 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4258 } 4259 } 4260 4261 /************************/ 4262 Static int 4263 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4264 { 4265 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4266 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4267 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4268 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4269 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4270 int i, k, frames; 4271 u_int huba, dir; 4272 int err; 4273 4274 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4275 4276 start = NULL; 4277 sitd = NULL; 4278 4279 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", xfer, xfer->ux_length, 4280 xfer->ux_flags, 0); 4281 4282 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4283 KASSERT(xfer->ux_nframes != 0); 4284 KASSERT(exfer->ex_isdone); 4285 4286 exfer->ex_type = EX_FS_ISOC; 4287 /* 4288 * Step 1: Allocate and initialize sitds. 4289 */ 4290 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4291 if (i > 16 || i == 0) { 4292 /* Spec page 271 says intervals > 16 are invalid */ 4293 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4294 4295 return EINVAL; 4296 } 4297 4298 frames = xfer->ux_nframes; 4299 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4300 sitd = ehci_alloc_sitd(sc); 4301 if (sitd == NULL) { 4302 err = ENOMEM; 4303 goto fail; 4304 } 4305 4306 if (prev) 4307 prev->xfer_next = sitd; 4308 else 4309 start = sitd; 4310 4311 huba = dev->ud_myhsport->up_parent->ud_addr; 4312 4313 #if 0 4314 if (sc->sc_flags & EHCIF_FREESCALE) { 4315 // Set hub address to 0 if embedded TT is used. 4316 if (huba == sc->sc_addr) 4317 huba = 0; 4318 } 4319 #endif 4320 4321 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4322 dir = UE_GET_DIR(k) ? 1 : 0; 4323 sitd->sitd.sitd_endp = 4324 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4325 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4326 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4327 EHCI_SITD_SET_HUBA(huba) | 4328 EHCI_SITD_SET_DIR(dir)); 4329 4330 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4331 } /* End of frame */ 4332 4333 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4334 4335 stop = sitd; 4336 stop->xfer_next = NULL; 4337 exfer->ex_sitdstart = start; 4338 exfer->ex_sitdend = stop; 4339 4340 return 0; 4341 4342 fail: 4343 mutex_enter(&sc->sc_lock); 4344 ehci_soft_sitd_t *next; 4345 for (sitd = start; sitd; sitd = next) { 4346 next = sitd->xfer_next; 4347 ehci_free_sitd_locked(sc, sitd); 4348 } 4349 mutex_exit(&sc->sc_lock); 4350 4351 return err; 4352 } 4353 4354 Static void 4355 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4356 { 4357 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4358 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4359 4360 KASSERT(ex->ex_type == EX_FS_ISOC); 4361 4362 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4363 } 4364 4365 Static usbd_status 4366 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4367 { 4368 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4369 usbd_status err; 4370 4371 mutex_enter(&sc->sc_lock); 4372 err = usb_insert_transfer(xfer); 4373 mutex_exit(&sc->sc_lock); 4374 4375 if (err && err != USBD_IN_PROGRESS) 4376 return err; 4377 4378 return ehci_device_fs_isoc_start(xfer); 4379 } 4380 4381 Static usbd_status 4382 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4383 { 4384 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4385 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4386 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4387 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4388 ehci_soft_sitd_t *sitd; 4389 usb_dma_t *dma_buf; 4390 int i, j, k, frames; 4391 int offs, total_length; 4392 int frindex; 4393 u_int dir; 4394 4395 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4396 4397 sitd = NULL; 4398 total_length = 0; 4399 4400 /* 4401 * To allow continuous transfers, above we start all transfers 4402 * immediately. However, we're still going to get usbd_start_next call 4403 * this when another xfer completes. So, check if this is already 4404 * in progress or not 4405 */ 4406 4407 if (exfer->ex_isrunning) { 4408 return USBD_IN_PROGRESS; 4409 } 4410 4411 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4412 xfer, xfer->ux_length, xfer->ux_flags, 0); 4413 4414 if (sc->sc_dying) 4415 return USBD_IOERROR; 4416 4417 /* 4418 * To avoid complication, don't allow a request right now that'll span 4419 * the entire frame table. To within 4 frames, to allow some leeway 4420 * on either side of where the hc currently is. 4421 */ 4422 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4423 xfer->ux_nframes >= sc->sc_flsize - 4) { 4424 printf("ehci: isoc descriptor requested that spans the entire" 4425 "frametable, too many frames\n"); 4426 return USBD_INVAL; 4427 } 4428 4429 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4430 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4431 KASSERT(exfer->ex_isdone); 4432 #ifdef DIAGNOSTIC 4433 exfer->ex_isdone = false; 4434 #endif 4435 4436 /* 4437 * Step 1: Initialize sitds. 4438 */ 4439 4440 frames = xfer->ux_nframes; 4441 dma_buf = &xfer->ux_dmabuf; 4442 offs = 0; 4443 4444 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4445 i++, sitd = sitd->xfer_next) { 4446 KASSERT(sitd != NULL); 4447 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4448 4449 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4450 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4451 4452 /* Set page0 index and offset - TP and T-offset are set below */ 4453 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4454 4455 total_length += xfer->ux_frlengths[i]; 4456 offs += xfer->ux_frlengths[i]; 4457 4458 sitd->sitd.sitd_buffer[1] = 4459 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4460 4461 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4462 4463 #if 0 4464 if (sc->sc_flags & EHCIF_FREESCALE) { 4465 // Set hub address to 0 if embedded TT is used. 4466 if (huba == sc->sc_addr) 4467 huba = 0; 4468 } 4469 #endif 4470 4471 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4472 dir = UE_GET_DIR(k) ? 1 : 0; 4473 KASSERT(sitd->sitd.sitd_endp == htole32( 4474 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4475 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4476 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4477 EHCI_SITD_SET_HUBA(huba) | 4478 EHCI_SITD_SET_DIR(dir))); 4479 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4480 4481 uint8_t sa = 0; 4482 uint8_t sb = 0; 4483 u_int temp, tlen; 4484 4485 if (dir == 0) { /* OUT */ 4486 temp = 0; 4487 tlen = xfer->ux_frlengths[i]; 4488 if (tlen <= 188) { 4489 temp |= 1; /* T-count = 1, TP = ALL */ 4490 tlen = 1; 4491 } else { 4492 tlen += 187; 4493 tlen /= 188; 4494 temp |= tlen; /* T-count = [1..6] */ 4495 temp |= 8; /* TP = Begin */ 4496 } 4497 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4498 4499 tlen += sa; 4500 4501 if (tlen >= 8) { 4502 sb = 0; 4503 } else { 4504 sb = (1 << tlen); 4505 } 4506 4507 sa = (1 << sa); 4508 sa = (sb - sa) & 0x3F; 4509 sb = 0; 4510 } else { 4511 sb = (-(4 << sa)) & 0xFE; 4512 sa = (1 << sa) & 0x3F; 4513 sa = 0x01; 4514 sb = 0xfc; 4515 } 4516 4517 sitd->sitd.sitd_sched = htole32( 4518 EHCI_SITD_SET_SMASK(sa) | 4519 EHCI_SITD_SET_CMASK(sb) 4520 ); 4521 4522 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4523 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4524 } /* End of frame */ 4525 4526 sitd = exfer->ex_sitdend; 4527 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4528 4529 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4530 sizeof(sitd->sitd.sitd_trans), 4531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4532 4533 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4534 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4535 4536 /* 4537 * Part 2: Transfer descriptors have now been set up, now they must 4538 * be scheduled into the periodic frame list. Erk. Not wanting to 4539 * complicate matters, transfer is denied if the transfer spans 4540 * more than the period frame list. 4541 */ 4542 4543 mutex_enter(&sc->sc_lock); 4544 4545 /* Start inserting frames */ 4546 if (epipe->isoc.cur_xfers > 0) { 4547 frindex = epipe->isoc.next_frame; 4548 } else { 4549 frindex = EOREAD4(sc, EHCI_FRINDEX); 4550 frindex = frindex >> 3; /* Erase microframe index */ 4551 frindex += 2; 4552 } 4553 4554 if (frindex >= sc->sc_flsize) 4555 frindex &= (sc->sc_flsize - 1); 4556 4557 /* Whats the frame interval? */ 4558 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4559 4560 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4561 j++, sitd = sitd->xfer_next) { 4562 KASSERT(sitd); 4563 4564 usb_syncmem(&sc->sc_fldma, 4565 sizeof(ehci_link_t) * frindex, 4566 sizeof(ehci_link_t), 4567 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4568 4569 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4570 if (sitd->sitd.sitd_next == 0) 4571 /* 4572 * FIXME: frindex table gets initialized to NULL 4573 * or EHCI_NULL? 4574 */ 4575 sitd->sitd.sitd_next = EHCI_NULL; 4576 4577 usb_syncmem(&sitd->dma, 4578 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4579 sizeof(ehci_sitd_t), 4580 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4581 4582 sc->sc_flist[frindex] = 4583 htole32(EHCI_LINK_SITD | sitd->physaddr); 4584 4585 usb_syncmem(&sc->sc_fldma, 4586 sizeof(ehci_link_t) * frindex, 4587 sizeof(ehci_link_t), 4588 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4589 4590 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4591 sc->sc_softsitds[frindex] = sitd; 4592 if (sitd->frame_list.next != NULL) 4593 sitd->frame_list.next->frame_list.prev = sitd; 4594 sitd->slot = frindex; 4595 sitd->frame_list.prev = NULL; 4596 4597 frindex += i; 4598 if (frindex >= sc->sc_flsize) 4599 frindex -= sc->sc_flsize; 4600 } 4601 4602 epipe->isoc.cur_xfers++; 4603 epipe->isoc.next_frame = frindex; 4604 4605 exfer->ex_isrunning = true; 4606 4607 ehci_add_intr_list(sc, exfer); 4608 xfer->ux_status = USBD_IN_PROGRESS; 4609 4610 mutex_exit(&sc->sc_lock); 4611 4612 if (sc->sc_bus.ub_usepolling) { 4613 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4614 ehci_waitintr(sc, xfer); 4615 } 4616 4617 return USBD_IN_PROGRESS; 4618 } 4619 4620 Static void 4621 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4622 { 4623 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4624 4625 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4626 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4627 } 4628 4629 Static void 4630 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4631 { 4632 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4633 4634 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4635 } 4636 4637 Static void 4638 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4639 { 4640 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4641 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4642 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4643 4644 KASSERT(mutex_owned(&sc->sc_lock)); 4645 4646 epipe->isoc.cur_xfers--; 4647 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4648 ehci_del_intr_list(sc, exfer); 4649 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4650 exfer->ex_isrunning = false; 4651 } 4652 4653 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4654 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4655 } 4656 4657 4658 /************************/ 4659 4660 4661 Static int 4662 ehci_device_isoc_init(struct usbd_xfer *xfer) 4663 { 4664 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4665 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4666 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4667 ehci_soft_itd_t *itd, *prev, *start, *stop; 4668 int i, j, k; 4669 int frames, ufrperframe; 4670 int err; 4671 4672 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4673 4674 start = NULL; 4675 prev = NULL; 4676 itd = NULL; 4677 4678 KASSERT(xfer->ux_nframes != 0); 4679 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4680 KASSERT(exfer->ex_isdone); 4681 4682 exfer->ex_type = EX_ISOC; 4683 4684 /* 4685 * Step 1: Allocate and initialize itds, how many do we need? 4686 * One per transfer if interval >= 8 microframes, less if we use 4687 * multiple microframes per frame. 4688 */ 4689 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4690 if (i > 16 || i == 0) { 4691 /* Spec page 271 says intervals > 16 are invalid */ 4692 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4693 return USBD_INVAL; 4694 } 4695 4696 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4697 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4698 4699 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4700 itd = ehci_alloc_itd(sc); 4701 if (itd == NULL) { 4702 err = ENOMEM; 4703 goto fail; 4704 } 4705 4706 if (prev != NULL) { 4707 /* Maybe not as it's updated by the scheduling? */ 4708 prev->itd.itd_next = 4709 htole32(itd->physaddr | EHCI_LINK_ITD); 4710 4711 prev->xfer_next = itd; 4712 } else { 4713 start = itd; 4714 } 4715 4716 /* 4717 * Other special values 4718 */ 4719 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4720 itd->itd.itd_bufr[0] = htole32( 4721 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4722 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4723 4724 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4725 ? 1 : 0; 4726 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4727 itd->itd.itd_bufr[1] |= htole32( 4728 EHCI_ITD_SET_DIR(k) | 4729 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4730 4731 /* FIXME: handle invalid trans - should be done in openpipe */ 4732 itd->itd.itd_bufr[2] |= 4733 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4734 } /* End of frame */ 4735 4736 stop = itd; 4737 stop->xfer_next = NULL; 4738 4739 exfer->ex_itdstart = start; 4740 exfer->ex_itdend = stop; 4741 4742 return 0; 4743 fail: 4744 mutex_enter(&sc->sc_lock); 4745 ehci_soft_itd_t *next; 4746 for (itd = start; itd; itd = next) { 4747 next = itd->xfer_next; 4748 ehci_free_itd_locked(sc, itd); 4749 } 4750 mutex_exit(&sc->sc_lock); 4751 4752 return err; 4753 4754 } 4755 4756 Static void 4757 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4758 { 4759 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4760 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4761 4762 KASSERT(ex->ex_type == EX_ISOC); 4763 4764 ehci_free_itd_chain(sc, ex->ex_itdstart); 4765 } 4766 4767 Static usbd_status 4768 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4769 { 4770 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4771 usbd_status err; 4772 4773 mutex_enter(&sc->sc_lock); 4774 err = usb_insert_transfer(xfer); 4775 mutex_exit(&sc->sc_lock); 4776 if (err && err != USBD_IN_PROGRESS) 4777 return err; 4778 4779 return ehci_device_isoc_start(xfer); 4780 } 4781 4782 Static usbd_status 4783 ehci_device_isoc_start(struct usbd_xfer *xfer) 4784 { 4785 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4786 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4787 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4788 ehci_soft_itd_t *itd, *prev; 4789 usb_dma_t *dma_buf; 4790 int i, j; 4791 int frames, uframes, ufrperframe; 4792 int trans_count, offs, total_length; 4793 int frindex; 4794 4795 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4796 4797 prev = NULL; 4798 itd = NULL; 4799 trans_count = 0; 4800 total_length = 0; 4801 4802 /* 4803 * To allow continuous transfers, above we start all transfers 4804 * immediately. However, we're still going to get usbd_start_next call 4805 * this when another xfer completes. So, check if this is already 4806 * in progress or not 4807 */ 4808 4809 if (exfer->ex_isrunning) { 4810 return USBD_IN_PROGRESS; 4811 } 4812 4813 USBHIST_LOG(ehcidebug, "xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4814 4815 if (sc->sc_dying) 4816 return USBD_IOERROR; 4817 4818 /* 4819 * To avoid complication, don't allow a request right now that'll span 4820 * the entire frame table. To within 4 frames, to allow some leeway 4821 * on either side of where the hc currently is. 4822 */ 4823 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4824 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4825 USBHIST_LOG(ehcidebug, 4826 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4827 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4828 return USBD_INVAL; 4829 } 4830 4831 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4832 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4833 KASSERT(exfer->ex_isdone); 4834 #ifdef DIAGNOSTIC 4835 exfer->ex_isdone = false; 4836 #endif 4837 4838 /* 4839 * Step 1: Re-Initialize itds 4840 */ 4841 4842 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4843 if (i > 16 || i == 0) { 4844 /* Spec page 271 says intervals > 16 are invalid */ 4845 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4846 return USBD_INVAL; 4847 } 4848 4849 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4850 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4851 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4852 4853 if (frames == 0) { 4854 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4855 return USBD_INVAL; 4856 } 4857 4858 dma_buf = &xfer->ux_dmabuf; 4859 offs = 0; 4860 4861 itd = exfer->ex_itdstart; 4862 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4863 int froffs = offs; 4864 4865 if (prev != NULL) { 4866 prev->itd.itd_next = 4867 htole32(itd->physaddr | EHCI_LINK_ITD); 4868 usb_syncmem(&prev->dma, 4869 prev->offs + offsetof(ehci_itd_t, itd_next), 4870 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4871 prev->xfer_next = itd; 4872 } 4873 4874 /* 4875 * Step 1.5, initialize uframes 4876 */ 4877 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4878 /* Calculate which page in the list this starts in */ 4879 int addr = DMAADDR(dma_buf, froffs); 4880 addr = EHCI_PAGE_OFFSET(addr); 4881 addr += (offs - froffs); 4882 addr = EHCI_PAGE(addr); 4883 addr /= EHCI_PAGE_SIZE; 4884 4885 /* 4886 * This gets the initial offset into the first page, 4887 * looks how far further along the current uframe 4888 * offset is. Works out how many pages that is. 4889 */ 4890 4891 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4892 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4893 EHCI_ITD_SET_PG(addr) | 4894 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4895 4896 total_length += xfer->ux_frlengths[trans_count]; 4897 offs += xfer->ux_frlengths[trans_count]; 4898 trans_count++; 4899 4900 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4901 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4902 break; 4903 } 4904 } 4905 4906 /* 4907 * Step 1.75, set buffer pointers. To simplify matters, all 4908 * pointers are filled out for the next 7 hardware pages in 4909 * the dma block, so no need to worry what pages to cover 4910 * and what to not. 4911 */ 4912 4913 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4914 /* 4915 * Don't try to lookup a page that's past the end 4916 * of buffer 4917 */ 4918 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4919 if (page_offs >= dma_buf->udma_block->size) 4920 break; 4921 4922 uint64_t page = DMAADDR(dma_buf, page_offs); 4923 page = EHCI_PAGE(page); 4924 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4925 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4926 } 4927 /* 4928 * Other special values 4929 */ 4930 4931 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4932 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4933 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4934 4935 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4936 ? 1 : 0; 4937 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4938 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4939 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4940 4941 /* FIXME: handle invalid trans */ 4942 itd->itd.itd_bufr[2] |= 4943 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4944 4945 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4946 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4947 4948 prev = itd; 4949 } /* End of frame */ 4950 4951 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4952 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4953 4954 /* 4955 * Part 2: Transfer descriptors have now been set up, now they must 4956 * be scheduled into the period frame list. Erk. Not wanting to 4957 * complicate matters, transfer is denied if the transfer spans 4958 * more than the period frame list. 4959 */ 4960 4961 mutex_enter(&sc->sc_lock); 4962 4963 /* Start inserting frames */ 4964 if (epipe->isoc.cur_xfers > 0) { 4965 frindex = epipe->isoc.next_frame; 4966 } else { 4967 frindex = EOREAD4(sc, EHCI_FRINDEX); 4968 frindex = frindex >> 3; /* Erase microframe index */ 4969 frindex += 2; 4970 } 4971 4972 if (frindex >= sc->sc_flsize) 4973 frindex &= (sc->sc_flsize - 1); 4974 4975 /* What's the frame interval? */ 4976 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4977 if (i / USB_UFRAMES_PER_FRAME == 0) 4978 i = 1; 4979 else 4980 i /= USB_UFRAMES_PER_FRAME; 4981 4982 itd = exfer->ex_itdstart; 4983 for (j = 0; j < frames; j++) { 4984 KASSERTMSG(itd != NULL, "frame %d\n", j); 4985 4986 usb_syncmem(&sc->sc_fldma, 4987 sizeof(ehci_link_t) * frindex, 4988 sizeof(ehci_link_t), 4989 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4990 4991 itd->itd.itd_next = sc->sc_flist[frindex]; 4992 if (itd->itd.itd_next == 0) 4993 /* 4994 * FIXME: frindex table gets initialized to NULL 4995 * or EHCI_NULL? 4996 */ 4997 itd->itd.itd_next = EHCI_NULL; 4998 4999 usb_syncmem(&itd->dma, 5000 itd->offs + offsetof(ehci_itd_t, itd_next), 5001 sizeof(itd->itd.itd_next), 5002 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5003 5004 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 5005 5006 usb_syncmem(&sc->sc_fldma, 5007 sizeof(ehci_link_t) * frindex, 5008 sizeof(ehci_link_t), 5009 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5010 5011 itd->frame_list.next = sc->sc_softitds[frindex]; 5012 sc->sc_softitds[frindex] = itd; 5013 if (itd->frame_list.next != NULL) 5014 itd->frame_list.next->frame_list.prev = itd; 5015 itd->slot = frindex; 5016 itd->frame_list.prev = NULL; 5017 5018 frindex += i; 5019 if (frindex >= sc->sc_flsize) 5020 frindex -= sc->sc_flsize; 5021 5022 itd = itd->xfer_next; 5023 } 5024 5025 epipe->isoc.cur_xfers++; 5026 epipe->isoc.next_frame = frindex; 5027 5028 exfer->ex_isrunning = true; 5029 5030 ehci_add_intr_list(sc, exfer); 5031 xfer->ux_status = USBD_IN_PROGRESS; 5032 5033 mutex_exit(&sc->sc_lock); 5034 5035 if (sc->sc_bus.ub_usepolling) { 5036 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 5037 ehci_waitintr(sc, xfer); 5038 } 5039 5040 return USBD_IN_PROGRESS; 5041 } 5042 5043 Static void 5044 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5045 { 5046 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5047 5048 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 5049 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5050 } 5051 5052 Static void 5053 ehci_device_isoc_close(struct usbd_pipe *pipe) 5054 { 5055 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5056 5057 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 5058 } 5059 5060 Static void 5061 ehci_device_isoc_done(struct usbd_xfer *xfer) 5062 { 5063 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5064 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5065 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5066 5067 KASSERT(mutex_owned(&sc->sc_lock)); 5068 5069 epipe->isoc.cur_xfers--; 5070 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 5071 ehci_del_intr_list(sc, exfer); 5072 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5073 exfer->ex_isrunning = false; 5074 } 5075 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5076 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5077 } 5078
Indexes created Wed Oct 01 19:09:53 GMT 2025