ehci.c revision 1.234.2.78
1 /* $NetBSD: ehci.c,v 1.234.2.78 2016/01/10 16:06:07 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.78 2016/01/10 16:06:07 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 /* Control pipe */ 136 struct { 137 usb_dma_t reqdma; 138 } ctrl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Iso pipe */ 144 struct { 145 u_int next_frame; 146 u_int cur_xfers; 147 } isoc; 148 }; 149 }; 150 151 Static usbd_status ehci_open(struct usbd_pipe *); 152 Static void ehci_poll(struct usbd_bus *); 153 Static void ehci_softintr(void *); 154 Static int ehci_intr1(ehci_softc_t *); 155 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 156 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 157 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 158 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 159 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 160 Static void ehci_idone(struct ehci_xfer *); 161 Static void ehci_timeout(void *); 162 Static void ehci_timeout_task(void *); 163 Static void ehci_intrlist_timeout(void *); 164 Static void ehci_doorbell(void *); 165 Static void ehci_pcd(void *); 166 167 Static struct usbd_xfer * 168 ehci_allocx(struct usbd_bus *, unsigned int); 169 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 170 171 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 172 Static int ehci_roothub_ctrl(struct usbd_bus *, 173 usb_device_request_t *, void *, int); 174 175 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 176 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 177 Static void ehci_root_intr_abort(struct usbd_xfer *); 178 Static void ehci_root_intr_close(struct usbd_pipe *); 179 Static void ehci_root_intr_done(struct usbd_xfer *); 180 181 Static int ehci_device_ctrl_init(struct usbd_xfer *); 182 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 183 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 185 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 186 Static void ehci_device_ctrl_close(struct usbd_pipe *); 187 Static void ehci_device_ctrl_done(struct usbd_xfer *); 188 189 Static int ehci_device_bulk_init(struct usbd_xfer *); 190 Static void ehci_device_bulk_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 193 Static void ehci_device_bulk_abort(struct usbd_xfer *); 194 Static void ehci_device_bulk_close(struct usbd_pipe *); 195 Static void ehci_device_bulk_done(struct usbd_xfer *); 196 197 Static int ehci_device_intr_init(struct usbd_xfer *); 198 Static void ehci_device_intr_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 201 Static void ehci_device_intr_abort(struct usbd_xfer *); 202 Static void ehci_device_intr_close(struct usbd_pipe *); 203 Static void ehci_device_intr_done(struct usbd_xfer *); 204 205 Static int ehci_device_isoc_init(struct usbd_xfer *); 206 Static void ehci_device_isoc_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 209 Static void ehci_device_isoc_abort(struct usbd_xfer *); 210 Static void ehci_device_isoc_close(struct usbd_pipe *); 211 Static void ehci_device_isoc_done(struct usbd_xfer *); 212 213 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 216 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 217 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 220 221 Static void ehci_device_clear_toggle(struct usbd_pipe *); 222 Static void ehci_noop(struct usbd_pipe *); 223 224 Static void ehci_disown(ehci_softc_t *, int, int); 225 226 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 227 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 228 229 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 230 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 231 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 232 int, int, ehci_soft_qtd_t **, ehci_soft_qtd_t **); 233 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 234 235 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 236 int, int, int *, ehci_soft_qtd_t **); 237 238 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 239 Static ehci_soft_sitd_t * 240 ehci_alloc_sitd(ehci_softc_t *); 241 242 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 243 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 244 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 245 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 246 247 static inline void 248 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 249 { 250 251 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 252 } 253 254 static inline void 255 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 259 } 260 261 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 262 263 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 264 int); 265 266 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 267 ehci_soft_qh_t *); 268 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 269 ehci_soft_qh_t *); 270 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 271 Static void ehci_sync_hc(ehci_softc_t *); 272 273 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 274 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 275 276 #ifdef EHCI_DEBUG 277 Static ehci_softc_t *theehci; 278 void ehci_dump(void); 279 #endif 280 281 #ifdef EHCI_DEBUG 282 Static void ehci_dump_regs(ehci_softc_t *); 283 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 284 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 285 Static void ehci_dump_qtd(ehci_qtd_t *); 286 Static void ehci_dump_sqh(ehci_soft_qh_t *); 287 Static void ehci_dump_sitd(struct ehci_soft_itd *); 288 Static void ehci_dump_itds(ehci_soft_itd_t *); 289 Static void ehci_dump_itd(struct ehci_soft_itd *); 290 Static void ehci_dump_exfer(struct ehci_xfer *); 291 #endif 292 293 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 294 295 #define ehci_add_intr_list(sc, ex) \ 296 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 297 #define ehci_del_intr_list(sc, ex) \ 298 do { \ 299 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 300 (ex)->ex_next.tqe_prev = NULL; \ 301 } while (0) 302 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 303 304 Static const struct usbd_bus_methods ehci_bus_methods = { 305 .ubm_open = ehci_open, 306 .ubm_softint = ehci_softintr, 307 .ubm_dopoll = ehci_poll, 308 .ubm_allocx = ehci_allocx, 309 .ubm_freex = ehci_freex, 310 .ubm_getlock = ehci_get_lock, 311 .ubm_rhctrl = ehci_roothub_ctrl, 312 }; 313 314 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 315 .upm_transfer = ehci_root_intr_transfer, 316 .upm_start = ehci_root_intr_start, 317 .upm_abort = ehci_root_intr_abort, 318 .upm_close = ehci_root_intr_close, 319 .upm_cleartoggle = ehci_noop, 320 .upm_done = ehci_root_intr_done, 321 }; 322 323 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 324 .upm_init = ehci_device_ctrl_init, 325 .upm_fini = ehci_device_ctrl_fini, 326 .upm_transfer = ehci_device_ctrl_transfer, 327 .upm_start = ehci_device_ctrl_start, 328 .upm_abort = ehci_device_ctrl_abort, 329 .upm_close = ehci_device_ctrl_close, 330 .upm_cleartoggle = ehci_noop, 331 .upm_done = ehci_device_ctrl_done, 332 }; 333 334 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 335 .upm_init = ehci_device_intr_init, 336 .upm_fini = ehci_device_intr_fini, 337 .upm_transfer = ehci_device_intr_transfer, 338 .upm_start = ehci_device_intr_start, 339 .upm_abort = ehci_device_intr_abort, 340 .upm_close = ehci_device_intr_close, 341 .upm_cleartoggle = ehci_device_clear_toggle, 342 .upm_done = ehci_device_intr_done, 343 }; 344 345 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 346 .upm_init = ehci_device_bulk_init, 347 .upm_fini = ehci_device_bulk_fini, 348 .upm_transfer = ehci_device_bulk_transfer, 349 .upm_start = ehci_device_bulk_start, 350 .upm_abort = ehci_device_bulk_abort, 351 .upm_close = ehci_device_bulk_close, 352 .upm_cleartoggle = ehci_device_clear_toggle, 353 .upm_done = ehci_device_bulk_done, 354 }; 355 356 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 357 .upm_init = ehci_device_isoc_init, 358 .upm_fini = ehci_device_isoc_fini, 359 .upm_transfer = ehci_device_isoc_transfer, 360 .upm_start = ehci_device_isoc_start, 361 .upm_abort = ehci_device_isoc_abort, 362 .upm_close = ehci_device_isoc_close, 363 .upm_cleartoggle = ehci_noop, 364 .upm_done = ehci_device_isoc_done, 365 }; 366 367 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 368 .upm_init = ehci_device_fs_isoc_init, 369 .upm_fini = ehci_device_fs_isoc_fini, 370 .upm_transfer = ehci_device_fs_isoc_transfer, 371 .upm_start = ehci_device_fs_isoc_start, 372 .upm_abort = ehci_device_fs_isoc_abort, 373 .upm_close = ehci_device_fs_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_fs_isoc_done, 376 }; 377 378 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 379 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 380 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 381 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 382 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 383 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 384 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 385 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 386 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 387 }; 388 389 int 390 ehci_init(ehci_softc_t *sc) 391 { 392 uint32_t vers, sparams, cparams, hcr; 393 u_int i; 394 usbd_status err; 395 ehci_soft_qh_t *sqh; 396 u_int ncomp; 397 398 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 399 #ifdef EHCI_DEBUG 400 theehci = sc; 401 #endif 402 403 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 404 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 405 cv_init(&sc->sc_softwake_cv, "ehciab"); 406 cv_init(&sc->sc_doorbell, "ehcidi"); 407 408 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 409 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 410 411 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 412 ehci_doorbell, sc); 413 KASSERT(sc->sc_doorbell_si != NULL); 414 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 415 ehci_pcd, sc); 416 KASSERT(sc->sc_pcd_si != NULL); 417 418 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 419 420 vers = EREAD2(sc, EHCI_HCIVERSION); 421 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 422 vers >> 8, vers & 0xff); 423 424 sparams = EREAD4(sc, EHCI_HCSPARAMS); 425 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 426 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 427 ncomp = EHCI_HCS_N_CC(sparams); 428 if (ncomp != sc->sc_ncomp) { 429 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 430 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 431 #if NOHCI == 0 || NUHCI == 0 432 aprint_error("%s: ohci or uhci probably not configured\n", 433 device_xname(sc->sc_dev)); 434 #endif 435 if (ncomp < sc->sc_ncomp) 436 sc->sc_ncomp = ncomp; 437 } 438 if (sc->sc_ncomp > 0) { 439 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 440 aprint_normal("%s: companion controller%s, %d port%s each:", 441 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 442 EHCI_HCS_N_PCC(sparams), 443 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 444 for (i = 0; i < sc->sc_ncomp; i++) 445 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 446 aprint_normal("\n"); 447 } 448 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 449 cparams = EREAD4(sc, EHCI_HCCPARAMS); 450 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 451 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 452 453 if (EHCI_HCC_64BIT(cparams)) { 454 /* MUST clear segment register if 64 bit capable. */ 455 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 456 } 457 458 sc->sc_bus.ub_revision = USBREV_2_0; 459 sc->sc_bus.ub_usedma = true; 460 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 461 462 /* Reset the controller */ 463 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 464 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 465 usb_delay_ms(&sc->sc_bus, 1); 466 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 467 for (i = 0; i < 100; i++) { 468 usb_delay_ms(&sc->sc_bus, 1); 469 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 470 if (!hcr) 471 break; 472 } 473 if (hcr) { 474 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 475 return EIO; 476 } 477 if (sc->sc_vendor_init) 478 sc->sc_vendor_init(sc); 479 480 /* XXX need proper intr scheduling */ 481 sc->sc_rand = 96; 482 483 /* frame list size at default, read back what we got and use that */ 484 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 485 case 0: sc->sc_flsize = 1024; break; 486 case 1: sc->sc_flsize = 512; break; 487 case 2: sc->sc_flsize = 256; break; 488 case 3: return EIO; 489 } 490 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 491 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 492 if (err) 493 return err; 494 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 495 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 496 497 for (i = 0; i < sc->sc_flsize; i++) { 498 sc->sc_flist[i] = EHCI_NULL; 499 } 500 501 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 502 503 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 504 KM_SLEEP); 505 if (sc->sc_softitds == NULL) 506 return ENOMEM; 507 LIST_INIT(&sc->sc_freeitds); 508 LIST_INIT(&sc->sc_freesitds); 509 TAILQ_INIT(&sc->sc_intrhead); 510 511 /* Set up the bus struct. */ 512 sc->sc_bus.ub_methods = &ehci_bus_methods; 513 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 514 515 sc->sc_eintrs = EHCI_NORMAL_INTRS; 516 517 /* 518 * Allocate the interrupt dummy QHs. These are arranged to give poll 519 * intervals that are powers of 2 times 1ms. 520 */ 521 for (i = 0; i < EHCI_INTRQHS; i++) { 522 sqh = ehci_alloc_sqh(sc); 523 if (sqh == NULL) { 524 err = ENOMEM; 525 goto bad1; 526 } 527 sc->sc_islots[i].sqh = sqh; 528 } 529 for (i = 0; i < EHCI_INTRQHS; i++) { 530 sqh = sc->sc_islots[i].sqh; 531 if (i == 0) { 532 /* The last (1ms) QH terminates. */ 533 sqh->qh.qh_link = EHCI_NULL; 534 sqh->next = NULL; 535 } else { 536 /* Otherwise the next QH has half the poll interval */ 537 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 538 sqh->qh.qh_link = htole32(sqh->next->physaddr | 539 EHCI_LINK_QH); 540 } 541 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 542 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 543 sqh->qh.qh_curqtd = EHCI_NULL; 544 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 545 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 546 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 547 sqh->sqtd = NULL; 548 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 } 551 /* Point the frame list at the last level (128ms). */ 552 for (i = 0; i < sc->sc_flsize; i++) { 553 int j; 554 555 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 556 revbits[i & (EHCI_MAX_POLLRATE-1)]; 557 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 558 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 559 i)].sqh->physaddr); 560 } 561 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 562 BUS_DMASYNC_PREWRITE); 563 564 /* Allocate dummy QH that starts the async list. */ 565 sqh = ehci_alloc_sqh(sc); 566 if (sqh == NULL) { 567 err = ENOMEM; 568 goto bad1; 569 } 570 /* Fill the QH */ 571 sqh->qh.qh_endp = 572 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 573 sqh->qh.qh_link = 574 htole32(sqh->physaddr | EHCI_LINK_QH); 575 sqh->qh.qh_curqtd = EHCI_NULL; 576 sqh->next = NULL; 577 /* Fill the overlay qTD */ 578 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 579 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 580 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 581 sqh->sqtd = NULL; 582 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 584 #ifdef EHCI_DEBUG 585 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 586 ehci_dump_sqh(sqh); 587 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 588 #endif 589 590 /* Point to async list */ 591 sc->sc_async_head = sqh; 592 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 593 594 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 595 596 /* Turn on controller */ 597 EOWRITE4(sc, EHCI_USBCMD, 598 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 599 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 600 EHCI_CMD_ASE | 601 EHCI_CMD_PSE | 602 EHCI_CMD_RS); 603 604 /* Take over port ownership */ 605 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 606 607 for (i = 0; i < 100; i++) { 608 usb_delay_ms(&sc->sc_bus, 1); 609 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 610 if (!hcr) 611 break; 612 } 613 if (hcr) { 614 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 615 return EIO; 616 } 617 618 /* Enable interrupts */ 619 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 620 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 621 622 return 0; 623 624 #if 0 625 bad2: 626 ehci_free_sqh(sc, sc->sc_async_head); 627 #endif 628 bad1: 629 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 630 return err; 631 } 632 633 int 634 ehci_intr(void *v) 635 { 636 ehci_softc_t *sc = v; 637 int ret = 0; 638 639 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 640 641 if (sc == NULL) 642 return 0; 643 644 mutex_spin_enter(&sc->sc_intr_lock); 645 646 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 647 goto done; 648 649 /* If we get an interrupt while polling, then just ignore it. */ 650 if (sc->sc_bus.ub_usepolling) { 651 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 652 653 if (intrs) 654 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 655 USBHIST_LOGN(ehcidebug, 16, 656 "ignored interrupt while polling", 0, 0, 0, 0); 657 goto done; 658 } 659 660 ret = ehci_intr1(sc); 661 662 done: 663 mutex_spin_exit(&sc->sc_intr_lock); 664 return ret; 665 } 666 667 Static int 668 ehci_intr1(ehci_softc_t *sc) 669 { 670 uint32_t intrs, eintrs; 671 672 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 673 674 /* In case the interrupt occurs before initialization has completed. */ 675 if (sc == NULL) { 676 #ifdef DIAGNOSTIC 677 printf("ehci_intr1: sc == NULL\n"); 678 #endif 679 return 0; 680 } 681 682 KASSERT(mutex_owned(&sc->sc_intr_lock)); 683 684 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 685 if (!intrs) 686 return 0; 687 688 eintrs = intrs & sc->sc_eintrs; 689 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 690 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 691 if (!eintrs) 692 return 0; 693 694 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 695 if (eintrs & EHCI_STS_IAA) { 696 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 697 kpreempt_disable(); 698 KASSERT(sc->sc_doorbell_si != NULL); 699 softint_schedule(sc->sc_doorbell_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_IAA; 702 } 703 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 704 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 705 eintrs & EHCI_STS_INT ? 1 : 0, 706 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 707 usb_schedsoftintr(&sc->sc_bus); 708 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 709 } 710 if (eintrs & EHCI_STS_HSE) { 711 printf("%s: unrecoverable error, controller halted\n", 712 device_xname(sc->sc_dev)); 713 /* XXX what else */ 714 } 715 if (eintrs & EHCI_STS_PCD) { 716 kpreempt_disable(); 717 KASSERT(sc->sc_pcd_si != NULL); 718 softint_schedule(sc->sc_pcd_si); 719 kpreempt_enable(); 720 eintrs &= ~EHCI_STS_PCD; 721 } 722 723 if (eintrs != 0) { 724 /* Block unprocessed interrupts. */ 725 sc->sc_eintrs &= ~eintrs; 726 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 727 printf("%s: blocking intrs 0x%x\n", 728 device_xname(sc->sc_dev), eintrs); 729 } 730 731 return 1; 732 } 733 734 Static void 735 ehci_doorbell(void *addr) 736 { 737 ehci_softc_t *sc = addr; 738 739 mutex_enter(&sc->sc_lock); 740 cv_broadcast(&sc->sc_doorbell); 741 mutex_exit(&sc->sc_lock); 742 } 743 744 Static void 745 ehci_pcd(void *addr) 746 { 747 ehci_softc_t *sc = addr; 748 struct usbd_xfer *xfer; 749 u_char *p; 750 int i, m; 751 752 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 753 754 mutex_enter(&sc->sc_lock); 755 xfer = sc->sc_intrxfer; 756 757 if (xfer == NULL) { 758 /* Just ignore the change. */ 759 goto done; 760 } 761 762 p = xfer->ux_buf; 763 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 764 memset(p, 0, xfer->ux_length); 765 for (i = 1; i <= m; i++) { 766 /* Pick out CHANGE bits from the status reg. */ 767 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 768 p[i/8] |= 1 << (i%8); 769 if (i % 8 == 7) 770 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 771 p[i/8], 0, 0); 772 } 773 xfer->ux_actlen = xfer->ux_length; 774 xfer->ux_status = USBD_NORMAL_COMPLETION; 775 776 usb_transfer_complete(xfer); 777 778 done: 779 mutex_exit(&sc->sc_lock); 780 } 781 782 Static void 783 ehci_softintr(void *v) 784 { 785 struct usbd_bus *bus = v; 786 ehci_softc_t *sc = EHCI_BUS2SC(bus); 787 struct ehci_xfer *ex, *nextex; 788 789 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 790 791 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 792 793 /* 794 * The only explanation I can think of for why EHCI is as brain dead 795 * as UHCI interrupt-wise is that Intel was involved in both. 796 * An interrupt just tells us that something is done, we have no 797 * clue what, so we need to scan through all active transfers. :-( 798 */ 799 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 800 nextex = TAILQ_NEXT(ex, ex_next); 801 ehci_check_intr(sc, ex); 802 } 803 804 /* Schedule a callout to catch any dropped transactions. */ 805 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 806 !TAILQ_EMPTY(&sc->sc_intrhead)) 807 callout_reset(&sc->sc_tmo_intrlist, 808 hz, ehci_intrlist_timeout, sc); 809 810 if (sc->sc_softwake) { 811 sc->sc_softwake = 0; 812 cv_broadcast(&sc->sc_softwake_cv); 813 } 814 } 815 816 /* Check for an interrupt. */ 817 Static void 818 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 819 { 820 821 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 822 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 823 824 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 825 826 switch (ex->ex_type) { 827 case EX_CTRL: 828 case EX_BULK: 829 case EX_INTR: 830 ehci_check_qh_intr(sc, ex); 831 break; 832 case EX_ISOC: 833 ehci_check_itd_intr(sc, ex); 834 break; 835 case EX_FS_ISOC: 836 ehci_check_sitd_intr(sc, ex); 837 break; 838 default: 839 KASSERT(false); 840 } 841 842 return; 843 } 844 845 Static void 846 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 847 { 848 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 849 uint32_t status; 850 851 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 852 853 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 854 855 if (ex->ex_type == EX_CTRL) { 856 fsqtd = ex->ex_setup; 857 lsqtd = ex->ex_status; 858 } else { 859 fsqtd = ex->ex_sqtdstart; 860 lsqtd = ex->ex_sqtdend; 861 } 862 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 863 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 864 865 /* 866 * If the last TD is still active we need to check whether there 867 * is an error somewhere in the middle, or whether there was a 868 * short packet (SPD and not ACTIVE). 869 */ 870 usb_syncmem(&lsqtd->dma, 871 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 872 sizeof(lsqtd->qtd.qtd_status), 873 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 874 status = le32toh(lsqtd->qtd.qtd_status); 875 usb_syncmem(&lsqtd->dma, 876 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 877 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 878 if (status & EHCI_QTD_ACTIVE) { 879 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 880 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 881 usb_syncmem(&sqtd->dma, 882 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 883 sizeof(sqtd->qtd.qtd_status), 884 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 885 status = le32toh(sqtd->qtd.qtd_status); 886 usb_syncmem(&sqtd->dma, 887 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 888 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 889 /* If there's an active QTD the xfer isn't done. */ 890 if (status & EHCI_QTD_ACTIVE) 891 break; 892 /* Any kind of error makes the xfer done. */ 893 if (status & EHCI_QTD_HALTED) 894 goto done; 895 /* Handle short packets */ 896 if (EHCI_QTD_GET_BYTES(status) != 0) { 897 /* 898 * If we get here for a control transfer then 899 * we need to let the hardware complete the 900 * status phase. That is, we're not done 901 * quite yet. 902 * 903 * Otherwise, we're done. 904 */ 905 if (ex->ex_type == EX_CTRL) { 906 break; 907 } 908 goto done; 909 } 910 } 911 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 912 ex, ex->ex_sqtdstart, 0, 0); 913 #ifdef EHCI_DEBUG 914 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 915 0, 0); 916 ehci_dump_sqtds(ex->ex_sqtdstart); 917 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 918 0); 919 #endif 920 return; 921 } 922 done: 923 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 924 callout_stop(&ex->ex_xfer.ux_callout); 925 ehci_idone(ex); 926 } 927 928 Static void 929 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 930 { 931 ehci_soft_itd_t *itd; 932 int i; 933 934 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 935 936 KASSERT(mutex_owned(&sc->sc_lock)); 937 938 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 939 return; 940 941 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 942 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 943 944 itd = ex->ex_itdend; 945 946 /* 947 * check no active transfers in last itd, meaning we're finished 948 */ 949 950 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 951 sizeof(itd->itd.itd_ctl), 952 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 953 954 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 955 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 956 break; 957 } 958 959 if (i == EHCI_ITD_NUFRAMES) { 960 goto done; /* All 8 descriptors inactive, it's done */ 961 } 962 963 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 964 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 965 966 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 967 ex->ex_itdstart, 0, 0); 968 return; 969 done: 970 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 971 callout_stop(&ex->ex_xfer.ux_callout); 972 ehci_idone(ex); 973 } 974 975 void 976 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 977 { 978 ehci_soft_sitd_t *sitd; 979 980 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 981 982 KASSERT(mutex_owned(&sc->sc_lock)); 983 984 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 985 return; 986 987 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 988 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 989 990 sitd = ex->ex_sitdend; 991 992 /* 993 * check no active transfers in last sitd, meaning we're finished 994 */ 995 996 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 997 sizeof(sitd->sitd.sitd_trans), 998 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 999 1000 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1001 1002 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1003 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1004 1005 if (active) 1006 return; 1007 1008 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1009 callout_stop(&(ex->ex_xfer.ux_callout)); 1010 ehci_idone(ex); 1011 } 1012 1013 1014 Static void 1015 ehci_idone(struct ehci_xfer *ex) 1016 { 1017 struct usbd_xfer *xfer = &ex->ex_xfer; 1018 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1019 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1020 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1021 uint32_t status = 0, nstatus = 0; 1022 int actlen = 0; 1023 1024 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1025 1026 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1027 1028 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1029 1030 if (xfer->ux_status == USBD_CANCELLED || 1031 xfer->ux_status == USBD_TIMEOUT) { 1032 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1033 return; 1034 } 1035 1036 #ifdef DIAGNOSTIC 1037 #ifdef EHCI_DEBUG 1038 if (ex->ex_isdone) { 1039 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1040 ehci_dump_exfer(ex); 1041 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1042 } 1043 #endif 1044 KASSERT(!ex->ex_isdone); 1045 ex->ex_isdone = true; 1046 #endif 1047 1048 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1049 1050 /* The transfer is done, compute actual length and status. */ 1051 if (ex->ex_type == EX_ISOC) { 1052 /* HS isoc transfer */ 1053 1054 struct ehci_soft_itd *itd; 1055 int i, nframes, len, uframes; 1056 1057 nframes = 0; 1058 1059 #ifdef EHCI_DEBUG 1060 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1061 ehci_dump_itds(ex->ex_itdstart); 1062 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1063 #endif 1064 1065 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1066 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1067 1068 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1069 usb_syncmem(&itd->dma, 1070 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1071 sizeof(itd->itd.itd_ctl), 1072 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1073 1074 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1075 /* 1076 * XXX - driver didn't fill in the frame full 1077 * of uframes. This leads to scheduling 1078 * inefficiencies, but working around 1079 * this doubles complexity of tracking 1080 * an xfer. 1081 */ 1082 if (nframes >= xfer->ux_nframes) 1083 break; 1084 1085 status = le32toh(itd->itd.itd_ctl[i]); 1086 len = EHCI_ITD_GET_LEN(status); 1087 if (EHCI_ITD_GET_STATUS(status) != 0) 1088 len = 0; /*No valid data on error*/ 1089 1090 xfer->ux_frlengths[nframes++] = len; 1091 actlen += len; 1092 } 1093 usb_syncmem(&itd->dma, 1094 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1095 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1096 1097 if (nframes >= xfer->ux_nframes) 1098 break; 1099 } 1100 1101 xfer->ux_actlen = actlen; 1102 xfer->ux_status = USBD_NORMAL_COMPLETION; 1103 goto end; 1104 } else if (ex->ex_type == EX_FS_ISOC) { 1105 /* FS isoc transfer */ 1106 struct ehci_soft_sitd *sitd; 1107 int nframes, len; 1108 1109 nframes = 0; 1110 1111 for (sitd = ex->ex_sitdstart; sitd != NULL; 1112 sitd = sitd->xfer_next) { 1113 usb_syncmem(&sitd->dma, 1114 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1115 sizeof(sitd->sitd.sitd_trans), 1116 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1117 1118 /* 1119 * XXX - driver didn't fill in the frame full 1120 * of uframes. This leads to scheduling 1121 * inefficiencies, but working around 1122 * this doubles complexity of tracking 1123 * an xfer. 1124 */ 1125 if (nframes >= xfer->ux_nframes) 1126 break; 1127 1128 status = le32toh(sitd->sitd.sitd_trans); 1129 usb_syncmem(&sitd->dma, 1130 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1131 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1132 1133 len = EHCI_SITD_GET_LEN(status); 1134 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1135 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1136 /* No valid data on error */ 1137 len = xfer->ux_frlengths[nframes]; 1138 } 1139 1140 /* 1141 * frlengths[i]: # of bytes to send 1142 * len: # of bytes host didn't send 1143 */ 1144 xfer->ux_frlengths[nframes] -= len; 1145 /* frlengths[i]: # of bytes host sent */ 1146 actlen += xfer->ux_frlengths[nframes++]; 1147 1148 if (nframes >= xfer->ux_nframes) 1149 break; 1150 } 1151 1152 xfer->ux_actlen = actlen; 1153 xfer->ux_status = USBD_NORMAL_COMPLETION; 1154 goto end; 1155 } 1156 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1157 ex->ex_type == EX_BULK); 1158 1159 /* Continue processing xfers using queue heads */ 1160 if (ex->ex_type == EX_CTRL) { 1161 fsqtd = ex->ex_setup; 1162 lsqtd = ex->ex_status; 1163 } else { 1164 fsqtd = ex->ex_sqtdstart; 1165 lsqtd = ex->ex_sqtdend; 1166 } 1167 #ifdef EHCI_DEBUG 1168 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1169 ehci_dump_sqtds(fsqtd); 1170 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1171 #endif 1172 1173 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1174 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1175 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1176 nstatus = le32toh(sqtd->qtd.qtd_status); 1177 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1178 BUS_DMASYNC_PREREAD); 1179 if (nstatus & EHCI_QTD_ACTIVE) 1180 break; 1181 1182 status = nstatus; 1183 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1184 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1185 } 1186 1187 /* 1188 * If there are left over TDs we need to update the toggle. 1189 * The default pipe doesn't need it since control transfers 1190 * start the toggle at 0 every time. 1191 * For a short transfer we need to update the toggle for the missing 1192 * packets within the qTD. 1193 */ 1194 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1195 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1196 USBHIST_LOG(ehcidebug, 1197 "toggle update status=0x%08x nstatus=0x%08x", 1198 status, nstatus, 0, 0); 1199 #if 0 1200 ehci_dump_sqh(epipe->sqh); 1201 ehci_dump_sqtds(ex->ex_sqtdstart); 1202 #endif 1203 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1204 } 1205 1206 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1207 actlen, status, 0); 1208 xfer->ux_actlen = actlen; 1209 if (status & EHCI_QTD_HALTED) { 1210 #ifdef EHCI_DEBUG 1211 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1212 xfer->ux_pipe->up_dev->ud_addr, 1213 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1214 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1215 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1216 0, 0); 1217 USBHIST_LOG(ehcidebug, 1218 "active =%d halted=%d buferr=%d babble=%d", 1219 status & EHCI_QTD_ACTIVE ? 1 : 0, 1220 status & EHCI_QTD_HALTED ? 1 : 0, 1221 status & EHCI_QTD_BUFERR ? 1 : 0, 1222 status & EHCI_QTD_BABBLE ? 1 : 0); 1223 1224 USBHIST_LOG(ehcidebug, 1225 "xacterr=%d missed=%d split =%d ping =%d", 1226 status & EHCI_QTD_XACTERR ? 1 : 0, 1227 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1228 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1229 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1230 1231 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1232 ehci_dump_sqh(epipe->sqh); 1233 ehci_dump_sqtds(ex->ex_sqtdstart); 1234 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1235 #endif 1236 /* low&full speed has an extra error flag */ 1237 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1238 EHCI_QH_SPEED_HIGH) 1239 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1240 else 1241 status &= EHCI_QTD_STATERRS; 1242 if (status == 0) /* no other errors means a stall */ { 1243 xfer->ux_status = USBD_STALLED; 1244 } else { 1245 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1246 } 1247 /* XXX need to reset TT on missed microframe */ 1248 if (status & EHCI_QTD_MISSEDMICRO) { 1249 printf("%s: missed microframe, TT reset not " 1250 "implemented, hub might be inoperational\n", 1251 device_xname(sc->sc_dev)); 1252 } 1253 } else { 1254 xfer->ux_status = USBD_NORMAL_COMPLETION; 1255 } 1256 1257 end: 1258 /* 1259 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1260 * during this call, before methods->done is called: dma sync required 1261 * beforehand? 1262 */ 1263 usb_transfer_complete(xfer); 1264 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1265 } 1266 1267 /* 1268 * Wait here until controller claims to have an interrupt. 1269 * Then call ehci_intr and return. Use timeout to avoid waiting 1270 * too long. 1271 */ 1272 Static void 1273 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1274 { 1275 int timo; 1276 uint32_t intrs; 1277 1278 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1279 1280 xfer->ux_status = USBD_IN_PROGRESS; 1281 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1282 usb_delay_ms(&sc->sc_bus, 1); 1283 if (sc->sc_dying) 1284 break; 1285 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1286 sc->sc_eintrs; 1287 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1288 #ifdef EHCI_DEBUG 1289 if (ehcidebug >= 15) 1290 ehci_dump_regs(sc); 1291 #endif 1292 if (intrs) { 1293 mutex_spin_enter(&sc->sc_intr_lock); 1294 ehci_intr1(sc); 1295 mutex_spin_exit(&sc->sc_intr_lock); 1296 if (xfer->ux_status != USBD_IN_PROGRESS) 1297 return; 1298 } 1299 } 1300 1301 /* Timeout */ 1302 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1303 xfer->ux_status = USBD_TIMEOUT; 1304 mutex_enter(&sc->sc_lock); 1305 usb_transfer_complete(xfer); 1306 mutex_exit(&sc->sc_lock); 1307 } 1308 1309 Static void 1310 ehci_poll(struct usbd_bus *bus) 1311 { 1312 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1313 1314 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1315 1316 #ifdef EHCI_DEBUG 1317 static int last; 1318 int new; 1319 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1320 if (new != last) { 1321 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1322 last = new; 1323 } 1324 #endif 1325 1326 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1327 mutex_spin_enter(&sc->sc_intr_lock); 1328 ehci_intr1(sc); 1329 mutex_spin_exit(&sc->sc_intr_lock); 1330 } 1331 } 1332 1333 void 1334 ehci_childdet(device_t self, device_t child) 1335 { 1336 struct ehci_softc *sc = device_private(self); 1337 1338 KASSERT(sc->sc_child == child); 1339 sc->sc_child = NULL; 1340 } 1341 1342 int 1343 ehci_detach(struct ehci_softc *sc, int flags) 1344 { 1345 int rv = 0; 1346 1347 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1348 1349 if (sc->sc_child != NULL) 1350 rv = config_detach(sc->sc_child, flags); 1351 1352 if (rv != 0) 1353 return rv; 1354 1355 callout_halt(&sc->sc_tmo_intrlist, NULL); 1356 callout_destroy(&sc->sc_tmo_intrlist); 1357 1358 /* XXX free other data structures XXX */ 1359 if (sc->sc_softitds) 1360 kmem_free(sc->sc_softitds, 1361 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1362 cv_destroy(&sc->sc_doorbell); 1363 cv_destroy(&sc->sc_softwake_cv); 1364 1365 #if 0 1366 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1367 1368 softint_disestablish(sc->sc_doorbell_si); 1369 softint_disestablish(sc->sc_pcd_si); 1370 1371 mutex_destroy(&sc->sc_lock); 1372 mutex_destroy(&sc->sc_intr_lock); 1373 #endif 1374 1375 pool_cache_destroy(sc->sc_xferpool); 1376 1377 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1378 1379 return rv; 1380 } 1381 1382 1383 int 1384 ehci_activate(device_t self, enum devact act) 1385 { 1386 struct ehci_softc *sc = device_private(self); 1387 1388 switch (act) { 1389 case DVACT_DEACTIVATE: 1390 sc->sc_dying = 1; 1391 return 0; 1392 default: 1393 return EOPNOTSUPP; 1394 } 1395 } 1396 1397 /* 1398 * Handle suspend/resume. 1399 * 1400 * We need to switch to polling mode here, because this routine is 1401 * called from an interrupt context. This is all right since we 1402 * are almost suspended anyway. 1403 * 1404 * Note that this power handler isn't to be registered directly; the 1405 * bus glue needs to call out to it. 1406 */ 1407 bool 1408 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1409 { 1410 ehci_softc_t *sc = device_private(dv); 1411 int i; 1412 uint32_t cmd, hcr; 1413 1414 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1415 1416 mutex_spin_enter(&sc->sc_intr_lock); 1417 sc->sc_bus.ub_usepolling++; 1418 mutex_spin_exit(&sc->sc_intr_lock); 1419 1420 for (i = 1; i <= sc->sc_noport; i++) { 1421 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1422 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1423 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1424 } 1425 1426 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1427 1428 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1429 EOWRITE4(sc, EHCI_USBCMD, cmd); 1430 1431 for (i = 0; i < 100; i++) { 1432 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1433 if (hcr == 0) 1434 break; 1435 1436 usb_delay_ms(&sc->sc_bus, 1); 1437 } 1438 if (hcr != 0) 1439 printf("%s: reset timeout\n", device_xname(dv)); 1440 1441 cmd &= ~EHCI_CMD_RS; 1442 EOWRITE4(sc, EHCI_USBCMD, cmd); 1443 1444 for (i = 0; i < 100; i++) { 1445 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1446 if (hcr == EHCI_STS_HCH) 1447 break; 1448 1449 usb_delay_ms(&sc->sc_bus, 1); 1450 } 1451 if (hcr != EHCI_STS_HCH) 1452 printf("%s: config timeout\n", device_xname(dv)); 1453 1454 mutex_spin_enter(&sc->sc_intr_lock); 1455 sc->sc_bus.ub_usepolling--; 1456 mutex_spin_exit(&sc->sc_intr_lock); 1457 1458 return true; 1459 } 1460 1461 bool 1462 ehci_resume(device_t dv, const pmf_qual_t *qual) 1463 { 1464 ehci_softc_t *sc = device_private(dv); 1465 int i; 1466 uint32_t cmd, hcr; 1467 1468 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1469 1470 /* restore things in case the bios sucks */ 1471 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1472 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1473 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1474 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1475 1476 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1477 1478 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1479 1480 hcr = 0; 1481 for (i = 1; i <= sc->sc_noport; i++) { 1482 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1483 if ((cmd & EHCI_PS_PO) == 0 && 1484 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1485 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1486 hcr = 1; 1487 } 1488 } 1489 1490 if (hcr) { 1491 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1492 1493 for (i = 1; i <= sc->sc_noport; i++) { 1494 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1495 if ((cmd & EHCI_PS_PO) == 0 && 1496 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1497 EOWRITE4(sc, EHCI_PORTSC(i), 1498 cmd & ~EHCI_PS_FPR); 1499 } 1500 } 1501 1502 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1503 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1504 1505 for (i = 0; i < 100; i++) { 1506 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1507 if (hcr != EHCI_STS_HCH) 1508 break; 1509 1510 usb_delay_ms(&sc->sc_bus, 1); 1511 } 1512 if (hcr == EHCI_STS_HCH) 1513 printf("%s: config timeout\n", device_xname(dv)); 1514 1515 return true; 1516 } 1517 1518 /* 1519 * Shut down the controller when the system is going down. 1520 */ 1521 bool 1522 ehci_shutdown(device_t self, int flags) 1523 { 1524 ehci_softc_t *sc = device_private(self); 1525 1526 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1527 1528 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1529 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1530 return true; 1531 } 1532 1533 Static struct usbd_xfer * 1534 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1535 { 1536 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1537 struct usbd_xfer *xfer; 1538 1539 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1540 if (xfer != NULL) { 1541 memset(xfer, 0, sizeof(struct ehci_xfer)); 1542 #ifdef DIAGNOSTIC 1543 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1544 ex->ex_isdone = true; 1545 xfer->ux_state = XFER_BUSY; 1546 #endif 1547 } 1548 return xfer; 1549 } 1550 1551 Static void 1552 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1553 { 1554 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1555 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1556 1557 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1558 xfer->ux_state); 1559 KASSERT(ex->ex_isdone); 1560 1561 #ifdef DIAGNOSTIC 1562 xfer->ux_state = XFER_FREE; 1563 #endif 1564 1565 pool_cache_put(sc->sc_xferpool, xfer); 1566 } 1567 1568 Static void 1569 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1570 { 1571 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1572 1573 *lock = &sc->sc_lock; 1574 } 1575 1576 Static void 1577 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1578 { 1579 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1580 1581 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1582 1583 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1584 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1585 #ifdef EHCI_DEBUG 1586 if (ehcidebug) 1587 usbd_dump_pipe(pipe); 1588 #endif 1589 epipe->nexttoggle = 0; 1590 } 1591 1592 Static void 1593 ehci_noop(struct usbd_pipe *pipe) 1594 { 1595 } 1596 1597 #ifdef EHCI_DEBUG 1598 /* 1599 * Unused function - this is meant to be called from a kernel 1600 * debugger. 1601 */ 1602 void 1603 ehci_dump(void) 1604 { 1605 ehci_softc_t *sc = theehci; 1606 int i; 1607 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1608 EOREAD4(sc, EHCI_USBCMD), 1609 EOREAD4(sc, EHCI_USBSTS), 1610 EOREAD4(sc, EHCI_USBINTR)); 1611 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1612 EOREAD4(sc, EHCI_FRINDEX), 1613 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1614 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1615 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1616 for (i = 1; i <= sc->sc_noport; i++) 1617 printf("port %d status=0x%08x\n", i, 1618 EOREAD4(sc, EHCI_PORTSC(i))); 1619 } 1620 1621 Static void 1622 ehci_dump_regs(ehci_softc_t *sc) 1623 { 1624 int i; 1625 1626 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1627 1628 USBHIST_LOG(ehcidebug, 1629 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1630 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1631 EOREAD4(sc, EHCI_USBINTR), 0); 1632 USBHIST_LOG(ehcidebug, 1633 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1634 "async = 0x%08x", 1635 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1636 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1637 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1638 for (i = 1; i <= sc->sc_noport; i += 2) { 1639 if (i == sc->sc_noport) { 1640 USBHIST_LOG(ehcidebug, 1641 "port %d status = 0x%08x", i, 1642 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1643 } else { 1644 USBHIST_LOG(ehcidebug, 1645 "port %d status = 0x%08x port %d status = 0x%08x", 1646 i, EOREAD4(sc, EHCI_PORTSC(i)), 1647 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1648 } 1649 } 1650 } 1651 1652 #define ehci_dump_link(link, type) do { \ 1653 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1654 link, \ 1655 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1656 if (type) { \ 1657 USBHIST_LOG(ehcidebug, \ 1658 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1659 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1660 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1661 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1662 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1663 } \ 1664 } while(0) 1665 1666 Static void 1667 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1668 { 1669 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1670 int i; 1671 uint32_t stop = 0; 1672 1673 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1674 ehci_dump_sqtd(sqtd); 1675 usb_syncmem(&sqtd->dma, 1676 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1677 sizeof(sqtd->qtd), 1678 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1679 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1680 usb_syncmem(&sqtd->dma, 1681 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1682 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1683 } 1684 if (!stop) 1685 USBHIST_LOG(ehcidebug, 1686 "dump aborted, too many TDs", 0, 0, 0, 0); 1687 } 1688 1689 Static void 1690 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1691 { 1692 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1693 1694 usb_syncmem(&sqtd->dma, sqtd->offs, 1695 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1696 1697 USBHIST_LOGN(ehcidebug, 10, 1698 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1699 ehci_dump_qtd(&sqtd->qtd); 1700 1701 usb_syncmem(&sqtd->dma, sqtd->offs, 1702 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1703 } 1704 1705 Static void 1706 ehci_dump_qtd(ehci_qtd_t *qtd) 1707 { 1708 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1709 uint32_t s = le32toh(qtd->qtd_status); 1710 1711 USBHIST_LOGN(ehcidebug, 10, 1712 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1713 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1714 USBHIST_LOGN(ehcidebug, 10, 1715 " toggle = %d ioc = %d bytes = %#x " 1716 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1717 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1718 USBHIST_LOGN(ehcidebug, 10, 1719 " cerr = %d pid = %d stat = %x", 1720 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1721 0); 1722 USBHIST_LOGN(ehcidebug, 10, 1723 "active =%d halted=%d buferr=%d babble=%d", 1724 s & EHCI_QTD_ACTIVE ? 1 : 0, 1725 s & EHCI_QTD_HALTED ? 1 : 0, 1726 s & EHCI_QTD_BUFERR ? 1 : 0, 1727 s & EHCI_QTD_BABBLE ? 1 : 0); 1728 USBHIST_LOGN(ehcidebug, 10, 1729 "xacterr=%d missed=%d split =%d ping =%d", 1730 s & EHCI_QTD_XACTERR ? 1 : 0, 1731 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1732 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1733 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1734 USBHIST_LOGN(ehcidebug, 10, 1735 "buffer[0] = %#x buffer[1] = %#x " 1736 "buffer[2] = %#x buffer[3] = %#x", 1737 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1738 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1739 USBHIST_LOGN(ehcidebug, 10, 1740 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1741 } 1742 1743 Static void 1744 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1745 { 1746 ehci_qh_t *qh = &sqh->qh; 1747 ehci_link_t link; 1748 uint32_t endp, endphub; 1749 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1750 1751 usb_syncmem(&sqh->dma, sqh->offs, 1752 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1753 1754 USBHIST_LOGN(ehcidebug, 10, 1755 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1756 link = le32toh(qh->qh_link); 1757 ehci_dump_link(link, true); 1758 1759 endp = le32toh(qh->qh_endp); 1760 USBHIST_LOGN(ehcidebug, 10, 1761 " endp = %#x", endp, 0, 0, 0); 1762 USBHIST_LOGN(ehcidebug, 10, 1763 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1764 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1765 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1766 USBHIST_LOGN(ehcidebug, 10, 1767 " dtc = %d hrecl = %d", 1768 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1769 USBHIST_LOGN(ehcidebug, 10, 1770 " ctl = %d nrl = %d mpl = %#x(%d)", 1771 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1772 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1773 1774 endphub = le32toh(qh->qh_endphub); 1775 USBHIST_LOGN(ehcidebug, 10, 1776 " endphub = %#x", endphub, 0, 0, 0); 1777 USBHIST_LOGN(ehcidebug, 10, 1778 " smask = 0x%02x cmask = 0x%02x", 1779 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1780 USBHIST_LOGN(ehcidebug, 10, 1781 " huba = 0x%02x port = %d mult = %d", 1782 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1783 EHCI_QH_GET_MULT(endphub), 0); 1784 1785 link = le32toh(qh->qh_curqtd); 1786 ehci_dump_link(link, false); 1787 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1788 ehci_dump_qtd(&qh->qh_qtd); 1789 1790 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1791 BUS_DMASYNC_PREREAD); 1792 } 1793 1794 Static void 1795 ehci_dump_itds(ehci_soft_itd_t *itd) 1796 { 1797 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1798 int i; 1799 uint32_t stop = 0; 1800 1801 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1802 ehci_dump_itd(itd); 1803 usb_syncmem(&itd->dma, 1804 itd->offs + offsetof(ehci_itd_t, itd_next), 1805 sizeof(itd->itd), 1806 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1807 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1808 usb_syncmem(&itd->dma, 1809 itd->offs + offsetof(ehci_itd_t, itd_next), 1810 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1811 } 1812 if (!stop) 1813 USBHIST_LOG(ehcidebug, "dump aborted, too many TDs", 0, 0, 0, 0); 1814 } 1815 1816 Static void 1817 ehci_dump_itd(struct ehci_soft_itd *itd) 1818 { 1819 ehci_isoc_trans_t t; 1820 ehci_isoc_bufr_ptr_t b, b2, b3; 1821 int i; 1822 1823 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1824 1825 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1826 0, 0); 1827 1828 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1829 t = le32toh(itd->itd.itd_ctl[i]); 1830 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1831 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1832 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1833 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1834 EHCI_ITD_GET_OFFS(t), 0); 1835 } 1836 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1837 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1838 USBHIST_LOG(ehcidebug, " %x", 1839 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1840 1841 b = le32toh(itd->itd.itd_bufr[0]); 1842 b2 = le32toh(itd->itd.itd_bufr[1]); 1843 b3 = le32toh(itd->itd.itd_bufr[2]); 1844 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1845 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1846 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1847 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1848 } 1849 1850 Static void 1851 ehci_dump_sitd(struct ehci_soft_itd *itd) 1852 { 1853 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1854 1855 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1856 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1857 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1858 itd->xfer_next, itd->physaddr, itd->slot, 0); 1859 } 1860 1861 Static void 1862 ehci_dump_exfer(struct ehci_xfer *ex) 1863 { 1864 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1865 1866 USBHIST_LOG(ehcidebug, "ex = %p type %d isdone", ex, ex->ex_type, 1867 ex->ex_isdone, 0); 1868 1869 switch (ex->ex_type) { 1870 case EX_CTRL: 1871 USBHIST_LOG(ehcidebug, " setup = %p data = %p status = %p", 1872 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1873 break; 1874 case EX_BULK: 1875 case EX_INTR: 1876 USBHIST_LOG(ehcidebug, " qtdstart = %p qtdend = %p", 1877 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1878 break; 1879 case EX_ISOC: 1880 USBHIST_LOG(ehcidebug, " itdstart = %p itdend = %p", 1881 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1882 break; 1883 case EX_FS_ISOC: 1884 USBHIST_LOG(ehcidebug, " sitdstart = %p sitdend = %p", 1885 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1886 break; 1887 default: 1888 USBHIST_LOG(ehcidebug, " unknown type", 0, 0, 0, 0); 1889 } 1890 } 1891 #endif 1892 1893 Static usbd_status 1894 ehci_open(struct usbd_pipe *pipe) 1895 { 1896 struct usbd_device *dev = pipe->up_dev; 1897 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1898 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1899 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1900 uint8_t addr = dev->ud_addr; 1901 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1902 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1903 ehci_soft_qh_t *sqh; 1904 usbd_status err; 1905 int ival, speed, naks; 1906 int hshubaddr, hshubport; 1907 1908 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1909 1910 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1911 pipe, addr, ed->bEndpointAddress, rhaddr); 1912 1913 if (dev->ud_myhsport) { 1914 /* 1915 * When directly attached FS/LS device while doing embedded 1916 * transaction translations and we are the hub, set the hub 1917 * address to 0 (us). 1918 */ 1919 if (!(sc->sc_flags & EHCIF_ETTF) 1920 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1921 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1922 } else { 1923 hshubaddr = 0; 1924 } 1925 hshubport = dev->ud_myhsport->up_portno; 1926 } else { 1927 hshubaddr = 0; 1928 hshubport = 0; 1929 } 1930 1931 if (sc->sc_dying) 1932 return USBD_IOERROR; 1933 1934 /* toggle state needed for bulk endpoints */ 1935 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1936 1937 if (addr == rhaddr) { 1938 switch (ed->bEndpointAddress) { 1939 case USB_CONTROL_ENDPOINT: 1940 pipe->up_methods = &roothub_ctrl_methods; 1941 break; 1942 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1943 pipe->up_methods = &ehci_root_intr_methods; 1944 break; 1945 default: 1946 USBHIST_LOG(ehcidebug, 1947 "bad bEndpointAddress 0x%02x", 1948 ed->bEndpointAddress, 0, 0, 0); 1949 return USBD_INVAL; 1950 } 1951 return USBD_NORMAL_COMPLETION; 1952 } 1953 1954 /* XXX All this stuff is only valid for async. */ 1955 switch (dev->ud_speed) { 1956 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1957 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1958 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1959 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1960 } 1961 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1962 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1963 hshubaddr, hshubport, 0, 0); 1964 return USBD_INVAL; 1965 } 1966 1967 /* 1968 * For interrupt transfer, nak throttling must be disabled, but for 1969 * the other transfer type, nak throttling should be enabled from the 1970 * viewpoint that avoids the memory thrashing. 1971 */ 1972 naks = (xfertype == UE_INTERRUPT) ? 0 1973 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1974 1975 /* Allocate sqh for everything, save isoc xfers */ 1976 if (xfertype != UE_ISOCHRONOUS) { 1977 sqh = ehci_alloc_sqh(sc); 1978 if (sqh == NULL) 1979 return USBD_NOMEM; 1980 /* qh_link filled when the QH is added */ 1981 sqh->qh.qh_endp = htole32( 1982 EHCI_QH_SET_ADDR(addr) | 1983 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1984 EHCI_QH_SET_EPS(speed) | 1985 EHCI_QH_DTC | 1986 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1987 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1988 EHCI_QH_CTL : 0) | 1989 EHCI_QH_SET_NRL(naks) 1990 ); 1991 sqh->qh.qh_endphub = htole32( 1992 EHCI_QH_SET_MULT(1) | 1993 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1994 ); 1995 if (speed != EHCI_QH_SPEED_HIGH) 1996 sqh->qh.qh_endphub |= htole32( 1997 EHCI_QH_SET_PORT(hshubport) | 1998 EHCI_QH_SET_HUBA(hshubaddr) | 1999 EHCI_QH_SET_CMASK(0x08) /* XXX */ 2000 ); 2001 sqh->qh.qh_curqtd = EHCI_NULL; 2002 /* Fill the overlay qTD */ 2003 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2004 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2005 sqh->qh.qh_qtd.qtd_status = htole32(0); 2006 2007 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2008 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2009 epipe->sqh = sqh; 2010 } else { 2011 sqh = NULL; 2012 } /*xfertype == UE_ISOC*/ 2013 2014 switch (xfertype) { 2015 case UE_CONTROL: 2016 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2017 0, &epipe->ctrl.reqdma); 2018 #ifdef EHCI_DEBUG 2019 if (err) 2020 printf("ehci_open: usb_allocmem()=%d\n", err); 2021 #endif 2022 if (err) 2023 goto bad; 2024 pipe->up_methods = &ehci_device_ctrl_methods; 2025 mutex_enter(&sc->sc_lock); 2026 ehci_add_qh(sc, sqh, sc->sc_async_head); 2027 mutex_exit(&sc->sc_lock); 2028 break; 2029 case UE_BULK: 2030 pipe->up_methods = &ehci_device_bulk_methods; 2031 mutex_enter(&sc->sc_lock); 2032 ehci_add_qh(sc, sqh, sc->sc_async_head); 2033 mutex_exit(&sc->sc_lock); 2034 break; 2035 case UE_INTERRUPT: 2036 pipe->up_methods = &ehci_device_intr_methods; 2037 ival = pipe->up_interval; 2038 if (ival == USBD_DEFAULT_INTERVAL) { 2039 if (speed == EHCI_QH_SPEED_HIGH) { 2040 if (ed->bInterval > 16) { 2041 /* 2042 * illegal with high-speed, but there 2043 * were documentation bugs in the spec, 2044 * so be generous 2045 */ 2046 ival = 256; 2047 } else 2048 ival = (1 << (ed->bInterval - 1)) / 8; 2049 } else 2050 ival = ed->bInterval; 2051 } 2052 err = ehci_device_setintr(sc, sqh, ival); 2053 if (err) 2054 goto bad; 2055 break; 2056 case UE_ISOCHRONOUS: 2057 if (speed == EHCI_QH_SPEED_HIGH) 2058 pipe->up_methods = &ehci_device_isoc_methods; 2059 else 2060 pipe->up_methods = &ehci_device_fs_isoc_methods; 2061 if (ed->bInterval == 0 || ed->bInterval > 16) { 2062 printf("ehci: opening pipe with invalid bInterval\n"); 2063 err = USBD_INVAL; 2064 goto bad; 2065 } 2066 if (UGETW(ed->wMaxPacketSize) == 0) { 2067 printf("ehci: zero length endpoint open request\n"); 2068 err = USBD_INVAL; 2069 goto bad; 2070 } 2071 epipe->isoc.next_frame = 0; 2072 epipe->isoc.cur_xfers = 0; 2073 break; 2074 default: 2075 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2076 err = USBD_INVAL; 2077 goto bad; 2078 } 2079 return USBD_NORMAL_COMPLETION; 2080 2081 bad: 2082 if (sqh != NULL) { 2083 mutex_enter(&sc->sc_lock); 2084 ehci_free_sqh(sc, sqh); 2085 mutex_exit(&sc->sc_lock); 2086 } 2087 return err; 2088 } 2089 2090 /* 2091 * Add an ED to the schedule. Called with USB lock held. 2092 */ 2093 Static void 2094 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2095 { 2096 2097 KASSERT(mutex_owned(&sc->sc_lock)); 2098 2099 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2100 2101 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2102 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2103 2104 sqh->next = head->next; 2105 sqh->qh.qh_link = head->qh.qh_link; 2106 2107 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2108 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2109 2110 head->next = sqh; 2111 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2112 2113 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2114 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2115 2116 #ifdef EHCI_DEBUG 2117 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2118 ehci_dump_sqh(sqh); 2119 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2120 #endif 2121 } 2122 2123 /* 2124 * Remove an ED from the schedule. Called with USB lock held. 2125 */ 2126 Static void 2127 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2128 { 2129 ehci_soft_qh_t *p; 2130 2131 KASSERT(mutex_owned(&sc->sc_lock)); 2132 2133 /* XXX */ 2134 for (p = head; p != NULL && p->next != sqh; p = p->next) 2135 ; 2136 if (p == NULL) 2137 panic("ehci_rem_qh: ED not found"); 2138 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2139 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2140 p->next = sqh->next; 2141 p->qh.qh_link = sqh->qh.qh_link; 2142 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2143 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2144 2145 ehci_sync_hc(sc); 2146 } 2147 2148 Static void 2149 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2150 { 2151 int i; 2152 uint32_t status; 2153 2154 /* Save toggle bit and ping status. */ 2155 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2156 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2157 status = sqh->qh.qh_qtd.qtd_status & 2158 htole32(EHCI_QTD_TOGGLE_MASK | 2159 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2160 /* Set HALTED to make hw leave it alone. */ 2161 sqh->qh.qh_qtd.qtd_status = 2162 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2163 usb_syncmem(&sqh->dma, 2164 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2165 sizeof(sqh->qh.qh_qtd.qtd_status), 2166 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2167 sqh->qh.qh_curqtd = 0; 2168 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2169 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2170 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2171 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2172 sqh->sqtd = sqtd; 2173 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2175 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2176 sqh->qh.qh_qtd.qtd_status = status; 2177 usb_syncmem(&sqh->dma, 2178 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2179 sizeof(sqh->qh.qh_qtd.qtd_status), 2180 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2181 } 2182 2183 /* 2184 * Ensure that the HC has released all references to the QH. We do this 2185 * by asking for a Async Advance Doorbell interrupt and then we wait for 2186 * the interrupt. 2187 * To make this easier we first obtain exclusive use of the doorbell. 2188 */ 2189 Static void 2190 ehci_sync_hc(ehci_softc_t *sc) 2191 { 2192 int error __diagused; 2193 2194 KASSERT(mutex_owned(&sc->sc_lock)); 2195 2196 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2197 2198 if (sc->sc_dying) { 2199 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2200 return; 2201 } 2202 /* ask for doorbell */ 2203 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2204 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2205 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2206 2207 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2208 2209 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2210 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2211 #ifdef DIAGNOSTIC 2212 if (error) 2213 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2214 #endif 2215 } 2216 2217 Static void 2218 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2219 { 2220 2221 KASSERT(mutex_owned(&sc->sc_lock)); 2222 2223 for (; itd != NULL; itd = itd->xfer_next) { 2224 struct ehci_soft_itd *prev = itd->frame_list.prev; 2225 2226 /* Unlink itd from hardware chain, or frame array */ 2227 if (prev == NULL) { /* We're at the table head */ 2228 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2229 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2230 usb_syncmem(&sc->sc_fldma, 2231 sizeof(ehci_link_t) * itd->slot, 2232 sizeof(ehci_link_t), 2233 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2234 2235 if (itd->frame_list.next != NULL) 2236 itd->frame_list.next->frame_list.prev = NULL; 2237 } else { 2238 /* XXX this part is untested... */ 2239 prev->itd.itd_next = itd->itd.itd_next; 2240 usb_syncmem(&itd->dma, 2241 itd->offs + offsetof(ehci_itd_t, itd_next), 2242 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2243 2244 prev->frame_list.next = itd->frame_list.next; 2245 if (itd->frame_list.next != NULL) 2246 itd->frame_list.next->frame_list.prev = prev; 2247 } 2248 } 2249 } 2250 2251 Static void 2252 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2253 { 2254 struct ehci_soft_itd *next; 2255 2256 mutex_enter(&sc->sc_lock); 2257 next = NULL; 2258 for (; itd != NULL; itd = next) { 2259 next = itd->xfer_next; 2260 ehci_free_itd_locked(sc, itd); 2261 } 2262 mutex_exit(&sc->sc_lock); 2263 } 2264 2265 Static void 2266 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2267 { 2268 2269 KASSERT(mutex_owned(&sc->sc_lock)); 2270 2271 for (; sitd != NULL; sitd = sitd->xfer_next) { 2272 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2273 2274 /* Unlink sitd from hardware chain, or frame array */ 2275 if (prev == NULL) { /* We're at the table head */ 2276 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2277 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2278 usb_syncmem(&sc->sc_fldma, 2279 sizeof(ehci_link_t) * sitd->slot, 2280 sizeof(ehci_link_t), 2281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2282 2283 if (sitd->frame_list.next != NULL) 2284 sitd->frame_list.next->frame_list.prev = NULL; 2285 } else { 2286 /* XXX this part is untested... */ 2287 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2288 usb_syncmem(&sitd->dma, 2289 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2290 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2291 2292 prev->frame_list.next = sitd->frame_list.next; 2293 if (sitd->frame_list.next != NULL) 2294 sitd->frame_list.next->frame_list.prev = prev; 2295 } 2296 } 2297 } 2298 2299 Static void 2300 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2301 { 2302 2303 mutex_enter(&sc->sc_lock); 2304 struct ehci_soft_sitd *next = NULL; 2305 for (; sitd != NULL; sitd = next) { 2306 next = sitd->xfer_next; 2307 ehci_free_sitd_locked(sc, sitd); 2308 } 2309 mutex_exit(&sc->sc_lock); 2310 } 2311 2312 /***********/ 2313 2314 Static int 2315 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2316 void *buf, int buflen) 2317 { 2318 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2319 usb_hub_descriptor_t hubd; 2320 usb_port_status_t ps; 2321 uint16_t len, value, index; 2322 int l, totlen = 0; 2323 int port, i; 2324 uint32_t v; 2325 2326 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2327 2328 if (sc->sc_dying) 2329 return -1; 2330 2331 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2332 req->bmRequestType, req->bRequest, 0, 0); 2333 2334 len = UGETW(req->wLength); 2335 value = UGETW(req->wValue); 2336 index = UGETW(req->wIndex); 2337 2338 #define C(x,y) ((x) | ((y) << 8)) 2339 switch (C(req->bRequest, req->bmRequestType)) { 2340 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2341 if (len == 0) 2342 break; 2343 switch (value) { 2344 case C(0, UDESC_DEVICE): { 2345 usb_device_descriptor_t devd; 2346 totlen = min(buflen, sizeof(devd)); 2347 memcpy(&devd, buf, totlen); 2348 USETW(devd.idVendor, sc->sc_id_vendor); 2349 memcpy(buf, &devd, totlen); 2350 break; 2351 2352 } 2353 #define sd ((usb_string_descriptor_t *)buf) 2354 case C(1, UDESC_STRING): 2355 /* Vendor */ 2356 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2357 break; 2358 case C(2, UDESC_STRING): 2359 /* Product */ 2360 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2361 break; 2362 #undef sd 2363 default: 2364 /* default from usbroothub */ 2365 return buflen; 2366 } 2367 break; 2368 2369 /* Hub requests */ 2370 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2371 break; 2372 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2373 USBHIST_LOG(ehcidebug, 2374 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2375 0, 0); 2376 if (index < 1 || index > sc->sc_noport) { 2377 return -1; 2378 } 2379 port = EHCI_PORTSC(index); 2380 v = EOREAD4(sc, port); 2381 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2382 v &= ~EHCI_PS_CLEAR; 2383 switch (value) { 2384 case UHF_PORT_ENABLE: 2385 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2386 break; 2387 case UHF_PORT_SUSPEND: 2388 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2389 break; 2390 v &= ~EHCI_PS_SUSP; 2391 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2392 /* see USB2 spec ch. 7.1.7.7 */ 2393 usb_delay_ms(&sc->sc_bus, 20); 2394 EOWRITE4(sc, port, v); 2395 usb_delay_ms(&sc->sc_bus, 2); 2396 #ifdef DEBUG 2397 v = EOREAD4(sc, port); 2398 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2399 printf("ehci: resume failed: %x\n", v); 2400 #endif 2401 break; 2402 case UHF_PORT_POWER: 2403 if (sc->sc_hasppc) 2404 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2405 break; 2406 case UHF_PORT_TEST: 2407 USBHIST_LOG(ehcidebug, "clear port test " 2408 "%d", index, 0, 0, 0); 2409 break; 2410 case UHF_PORT_INDICATOR: 2411 USBHIST_LOG(ehcidebug, "clear port ind " 2412 "%d", index, 0, 0, 0); 2413 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2414 break; 2415 case UHF_C_PORT_CONNECTION: 2416 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2417 break; 2418 case UHF_C_PORT_ENABLE: 2419 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2420 break; 2421 case UHF_C_PORT_SUSPEND: 2422 /* how? */ 2423 break; 2424 case UHF_C_PORT_OVER_CURRENT: 2425 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2426 break; 2427 case UHF_C_PORT_RESET: 2428 sc->sc_isreset[index] = 0; 2429 break; 2430 default: 2431 return -1; 2432 } 2433 #if 0 2434 switch(value) { 2435 case UHF_C_PORT_CONNECTION: 2436 case UHF_C_PORT_ENABLE: 2437 case UHF_C_PORT_SUSPEND: 2438 case UHF_C_PORT_OVER_CURRENT: 2439 case UHF_C_PORT_RESET: 2440 default: 2441 break; 2442 } 2443 #endif 2444 break; 2445 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2446 if (len == 0) 2447 break; 2448 if ((value & 0xff) != 0) { 2449 return -1; 2450 } 2451 totlen = min(buflen, sizeof(hubd)); 2452 memcpy(&hubd, buf, totlen); 2453 hubd.bNbrPorts = sc->sc_noport; 2454 v = EOREAD4(sc, EHCI_HCSPARAMS); 2455 USETW(hubd.wHubCharacteristics, 2456 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2457 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2458 ? UHD_PORT_IND : 0); 2459 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2460 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2461 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2462 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2463 totlen = min(totlen, hubd.bDescLength); 2464 memcpy(buf, &hubd, totlen); 2465 break; 2466 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2467 if (len != 4) { 2468 return -1; 2469 } 2470 memset(buf, 0, len); /* ? XXX */ 2471 totlen = len; 2472 break; 2473 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2474 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2475 if (index < 1 || index > sc->sc_noport) { 2476 return -1; 2477 } 2478 if (len != 4) { 2479 return -1; 2480 } 2481 v = EOREAD4(sc, EHCI_PORTSC(index)); 2482 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2483 2484 i = UPS_HIGH_SPEED; 2485 if (sc->sc_flags & EHCIF_ETTF) { 2486 /* 2487 * If we are doing embedded transaction translation, 2488 * then directly attached LS/FS devices are reset by 2489 * the EHCI controller itself. PSPD is encoded 2490 * the same way as in USBSTATUS. 2491 */ 2492 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2493 } 2494 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2495 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2496 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2497 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2498 if (v & EHCI_PS_PR) i |= UPS_RESET; 2499 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2500 if (sc->sc_vendor_port_status) 2501 i = sc->sc_vendor_port_status(sc, v, i); 2502 USETW(ps.wPortStatus, i); 2503 i = 0; 2504 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2505 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2506 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2507 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2508 USETW(ps.wPortChange, i); 2509 totlen = min(len, sizeof(ps)); 2510 memcpy(buf, &ps, totlen); 2511 break; 2512 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2513 return -1; 2514 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2515 break; 2516 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2517 if (index < 1 || index > sc->sc_noport) { 2518 return -1; 2519 } 2520 port = EHCI_PORTSC(index); 2521 v = EOREAD4(sc, port); 2522 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2523 v &= ~EHCI_PS_CLEAR; 2524 switch(value) { 2525 case UHF_PORT_ENABLE: 2526 EOWRITE4(sc, port, v | EHCI_PS_PE); 2527 break; 2528 case UHF_PORT_SUSPEND: 2529 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2530 break; 2531 case UHF_PORT_RESET: 2532 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2533 if (EHCI_PS_IS_LOWSPEED(v) 2534 && sc->sc_ncomp > 0 2535 && !(sc->sc_flags & EHCIF_ETTF)) { 2536 /* 2537 * Low speed device on non-ETTF controller or 2538 * unaccompanied controller, give up ownership. 2539 */ 2540 ehci_disown(sc, index, 1); 2541 break; 2542 } 2543 /* Start reset sequence. */ 2544 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2545 EOWRITE4(sc, port, v | EHCI_PS_PR); 2546 /* Wait for reset to complete. */ 2547 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2548 if (sc->sc_dying) { 2549 return -1; 2550 } 2551 /* 2552 * An embedded transaction translator will automatically 2553 * terminate the reset sequence so there's no need to 2554 * it. 2555 */ 2556 v = EOREAD4(sc, port); 2557 if (v & EHCI_PS_PR) { 2558 /* Terminate reset sequence. */ 2559 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2560 /* Wait for HC to complete reset. */ 2561 usb_delay_ms(&sc->sc_bus, 2562 EHCI_PORT_RESET_COMPLETE); 2563 if (sc->sc_dying) { 2564 return -1; 2565 } 2566 } 2567 2568 v = EOREAD4(sc, port); 2569 USBHIST_LOG(ehcidebug, 2570 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2571 if (v & EHCI_PS_PR) { 2572 printf("%s: port reset timeout\n", 2573 device_xname(sc->sc_dev)); 2574 return USBD_TIMEOUT; 2575 } 2576 if (!(v & EHCI_PS_PE)) { 2577 /* Not a high speed device, give up ownership.*/ 2578 ehci_disown(sc, index, 0); 2579 break; 2580 } 2581 sc->sc_isreset[index] = 1; 2582 USBHIST_LOG(ehcidebug, 2583 "ehci port %d reset, status = 0x%08x", index, v, 0, 2584 0); 2585 break; 2586 case UHF_PORT_POWER: 2587 USBHIST_LOG(ehcidebug, 2588 "set port power %d (has PPC = %d)", index, 2589 sc->sc_hasppc, 0, 0); 2590 if (sc->sc_hasppc) 2591 EOWRITE4(sc, port, v | EHCI_PS_PP); 2592 break; 2593 case UHF_PORT_TEST: 2594 USBHIST_LOG(ehcidebug, "set port test %d", 2595 index, 0, 0, 0); 2596 break; 2597 case UHF_PORT_INDICATOR: 2598 USBHIST_LOG(ehcidebug, "set port ind %d", 2599 index, 0, 0, 0); 2600 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2601 break; 2602 default: 2603 return -1; 2604 } 2605 break; 2606 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2607 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2608 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2609 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2610 break; 2611 default: 2612 /* default from usbroothub */ 2613 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2614 buflen, 0, 0, 0); 2615 2616 return buflen; 2617 } 2618 2619 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2620 2621 return totlen; 2622 } 2623 2624 Static void 2625 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2626 { 2627 int port; 2628 uint32_t v; 2629 2630 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2631 2632 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2633 #ifdef DIAGNOSTIC 2634 if (sc->sc_npcomp != 0) { 2635 int i = (index-1) / sc->sc_npcomp; 2636 if (i >= sc->sc_ncomp) 2637 printf("%s: strange port\n", 2638 device_xname(sc->sc_dev)); 2639 else 2640 printf("%s: handing over %s speed device on " 2641 "port %d to %s\n", 2642 device_xname(sc->sc_dev), 2643 lowspeed ? "low" : "full", 2644 index, device_xname(sc->sc_comps[i])); 2645 } else { 2646 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2647 } 2648 #endif 2649 port = EHCI_PORTSC(index); 2650 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2651 EOWRITE4(sc, port, v | EHCI_PS_PO); 2652 } 2653 2654 Static usbd_status 2655 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2656 { 2657 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2658 usbd_status err; 2659 2660 /* Insert last in queue. */ 2661 mutex_enter(&sc->sc_lock); 2662 err = usb_insert_transfer(xfer); 2663 mutex_exit(&sc->sc_lock); 2664 if (err) 2665 return err; 2666 2667 /* Pipe isn't running, start first */ 2668 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2669 } 2670 2671 Static usbd_status 2672 ehci_root_intr_start(struct usbd_xfer *xfer) 2673 { 2674 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2675 2676 if (sc->sc_dying) 2677 return USBD_IOERROR; 2678 2679 mutex_enter(&sc->sc_lock); 2680 sc->sc_intrxfer = xfer; 2681 mutex_exit(&sc->sc_lock); 2682 2683 return USBD_IN_PROGRESS; 2684 } 2685 2686 /* Abort a root interrupt request. */ 2687 Static void 2688 ehci_root_intr_abort(struct usbd_xfer *xfer) 2689 { 2690 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2691 2692 KASSERT(mutex_owned(&sc->sc_lock)); 2693 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2694 2695 sc->sc_intrxfer = NULL; 2696 2697 xfer->ux_status = USBD_CANCELLED; 2698 usb_transfer_complete(xfer); 2699 } 2700 2701 /* Close the root pipe. */ 2702 Static void 2703 ehci_root_intr_close(struct usbd_pipe *pipe) 2704 { 2705 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2706 2707 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2708 2709 KASSERT(mutex_owned(&sc->sc_lock)); 2710 2711 sc->sc_intrxfer = NULL; 2712 } 2713 2714 Static void 2715 ehci_root_intr_done(struct usbd_xfer *xfer) 2716 { 2717 xfer->ux_hcpriv = NULL; 2718 } 2719 2720 /************************/ 2721 2722 Static ehci_soft_qh_t * 2723 ehci_alloc_sqh(ehci_softc_t *sc) 2724 { 2725 ehci_soft_qh_t *sqh; 2726 usbd_status err; 2727 int i, offs; 2728 usb_dma_t dma; 2729 2730 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2731 2732 mutex_enter(&sc->sc_lock); 2733 if (sc->sc_freeqhs == NULL) { 2734 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2735 mutex_exit(&sc->sc_lock); 2736 2737 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2738 EHCI_PAGE_SIZE, &dma); 2739 #ifdef EHCI_DEBUG 2740 if (err) 2741 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2742 #endif 2743 if (err) 2744 return NULL; 2745 2746 mutex_enter(&sc->sc_lock); 2747 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2748 offs = i * EHCI_SQH_SIZE; 2749 sqh = KERNADDR(&dma, offs); 2750 sqh->physaddr = DMAADDR(&dma, offs); 2751 sqh->dma = dma; 2752 sqh->offs = offs; 2753 sqh->next = sc->sc_freeqhs; 2754 sc->sc_freeqhs = sqh; 2755 } 2756 } 2757 sqh = sc->sc_freeqhs; 2758 sc->sc_freeqhs = sqh->next; 2759 mutex_exit(&sc->sc_lock); 2760 2761 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2762 sqh->next = NULL; 2763 return sqh; 2764 } 2765 2766 Static void 2767 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2768 { 2769 KASSERT(mutex_owned(&sc->sc_lock)); 2770 2771 sqh->next = sc->sc_freeqhs; 2772 sc->sc_freeqhs = sqh; 2773 } 2774 2775 Static ehci_soft_qtd_t * 2776 ehci_alloc_sqtd(ehci_softc_t *sc) 2777 { 2778 ehci_soft_qtd_t *sqtd = NULL; 2779 usbd_status err; 2780 int i, offs; 2781 usb_dma_t dma; 2782 2783 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2784 2785 mutex_enter(&sc->sc_lock); 2786 if (sc->sc_freeqtds == NULL) { 2787 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2788 mutex_exit(&sc->sc_lock); 2789 2790 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2791 EHCI_PAGE_SIZE, &dma); 2792 #ifdef EHCI_DEBUG 2793 if (err) 2794 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2795 #endif 2796 if (err) 2797 goto done; 2798 2799 mutex_enter(&sc->sc_lock); 2800 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2801 offs = i * EHCI_SQTD_SIZE; 2802 sqtd = KERNADDR(&dma, offs); 2803 sqtd->physaddr = DMAADDR(&dma, offs); 2804 sqtd->dma = dma; 2805 sqtd->offs = offs; 2806 2807 sqtd->nextqtd = sc->sc_freeqtds; 2808 sc->sc_freeqtds = sqtd; 2809 } 2810 } 2811 2812 sqtd = sc->sc_freeqtds; 2813 sc->sc_freeqtds = sqtd->nextqtd; 2814 mutex_exit(&sc->sc_lock); 2815 2816 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2817 sqtd->nextqtd = NULL; 2818 sqtd->xfer = NULL; 2819 2820 done: 2821 return sqtd; 2822 } 2823 2824 Static void 2825 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2826 { 2827 2828 mutex_enter(&sc->sc_lock); 2829 sqtd->nextqtd = sc->sc_freeqtds; 2830 sc->sc_freeqtds = sqtd; 2831 mutex_exit(&sc->sc_lock); 2832 } 2833 2834 Static usbd_status 2835 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2836 int alen, int rd, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2837 { 2838 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2839 ehci_soft_qtd_t *next, *cur; 2840 ehci_physaddr_t nextphys; 2841 uint32_t qtdstatus; 2842 int len, curlen, mps; 2843 int i, tog; 2844 int pages, pageoffs; 2845 size_t curoffs; 2846 vaddr_t va, va_offs; 2847 usb_dma_t *dma = &xfer->ux_dmabuf; 2848 uint16_t flags = xfer->ux_flags; 2849 paddr_t a; 2850 2851 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2852 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2853 2854 ASSERT_SLEEPABLE(); 2855 KASSERT(sp); 2856 KASSERT(alen != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2857 2858 len = alen; 2859 qtdstatus = EHCI_QTD_ACTIVE | 2860 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2861 EHCI_QTD_SET_CERR(3) 2862 ; 2863 2864 size_t nsqtd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 2865 nsqtd += ((len + EHCI_QTD_MAXTRANSFER - 1) / EHCI_QTD_MAXTRANSFER); 2866 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2867 KM_SLEEP); 2868 exfer->ex_nsqtd = nsqtd; 2869 2870 mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2871 cur = ehci_alloc_sqtd(sc); 2872 *sp = cur; 2873 if (cur == NULL) 2874 goto nomem; 2875 2876 curoffs = 0; 2877 for (size_t j = 0;;) { 2878 KASSERT(j < nsqtd); 2879 exfer->ex_sqtds[j++] = cur; 2880 2881 /* The EHCI hardware can handle at most 5 pages. */ 2882 va = (vaddr_t)KERNADDR(dma, curoffs); 2883 va_offs = EHCI_PAGE_OFFSET(va); 2884 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2885 /* we can handle it in this QTD */ 2886 curlen = len - curoffs; 2887 } else { 2888 /* must use multiple TDs, fill as much as possible. */ 2889 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2890 2891 /* the length must be a multiple of the max size */ 2892 curlen -= curlen % mps; 2893 USBHIST_LOG(ehcidebug, "multiple QTDs, curlen=%d", 2894 curlen, 0, 0, 0); 2895 KASSERT(curlen != 0); 2896 } 2897 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", len, 2898 curlen, curoffs, 0); 2899 2900 /* 2901 * Allocate another transfer if there's more data left, 2902 * or if force last short transfer flag is set and we're 2903 * allocating a multiple of the max packet size. 2904 */ 2905 2906 if (curoffs + curlen != len || 2907 ((curlen % mps) == 0 && !rd && curlen != 0 && 2908 (flags & USBD_FORCE_SHORT_XFER))) { 2909 next = ehci_alloc_sqtd(sc); 2910 if (next == NULL) 2911 goto nomem; 2912 nextphys = htole32(next->physaddr); 2913 } else { 2914 next = NULL; 2915 nextphys = EHCI_NULL; 2916 } 2917 2918 /* Find number of pages we'll be using, insert dma addresses */ 2919 pages = EHCI_NPAGES(curlen); 2920 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2921 pageoffs = EHCI_PAGE(curoffs); 2922 for (i = 0; i < pages; i++) { 2923 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2924 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2925 /* Cast up to avoid compiler warnings */ 2926 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2927 } 2928 2929 /* First buffer pointer requires a page offset to start at */ 2930 cur->qtd.qtd_buffer[0] |= htole32(va_offs); 2931 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2932 cur->qtd.qtd_status = htole32(qtdstatus); 2933 cur->nextqtd = next; 2934 cur->xfer = xfer; 2935 cur->bufoff = curoffs; 2936 cur->tdlen = curlen; 2937 cur->len = 0; 2938 2939 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2940 curoffs, curoffs + curlen, 0, 0); 2941 2942 /* 2943 * adjust the toggle based on the number of packets in this 2944 * qtd 2945 */ 2946 if (((curlen + mps - 1) / mps) & 1) { 2947 tog ^= 1; 2948 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2949 } 2950 if (next == NULL) 2951 break; 2952 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2953 if (len) 2954 curoffs += curlen; 2955 cur = next; 2956 } 2957 if (ep) 2958 *ep = cur; 2959 2960 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", *sp, cur, 0, 0); 2961 2962 return USBD_NORMAL_COMPLETION; 2963 2964 nomem: 2965 ehci_free_sqtds(sc, exfer); 2966 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2967 return USBD_NOMEM; 2968 } 2969 2970 Static void 2971 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2972 { 2973 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2974 USBHIST_LOG(ehcidebug, "exfer=%p", exfer, 0, 0, 0); 2975 2976 mutex_enter(&sc->sc_lock); 2977 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2978 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2979 2980 if (sqtd == NULL) 2981 break; 2982 2983 sqtd->nextqtd = sc->sc_freeqtds; 2984 sc->sc_freeqtds = sqtd; 2985 } 2986 mutex_exit(&sc->sc_lock); 2987 } 2988 2989 Static void 2990 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2991 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2992 { 2993 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2994 ehci_soft_qtd_t *sqtd, *prev; 2995 int tog = *toggle; 2996 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2997 int len = length; 2998 size_t i; 2999 3000 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3001 USBHIST_LOG(ehcidebug, "xfer=%p len %d isread %d toggle %d", xfer, 3002 len, isread, *toggle); 3003 USBHIST_LOG(ehcidebug, " VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 3004 0, 0, 0); 3005 3006 sqtd = prev = NULL; 3007 for (i = 0; i < exfer->ex_nsqtd; i++, prev = sqtd) { 3008 sqtd = exfer->ex_sqtds[i]; 3009 vaddr_t va = (vaddr_t)KERNADDR(&xfer->ux_dmabuf, sqtd->bufoff); 3010 sqtd->len = sqtd->tdlen; 3011 if (len < sqtd->len) { 3012 sqtd->len = len; 3013 } 3014 3015 USBHIST_LOG(ehcidebug, "sqtd[%d]=%p prev %p len %d", i, sqtd, 3016 prev, sqtd->len); 3017 USBHIST_LOG(ehcidebug, " va %p bufoff %d pa %p", va, sqtd->bufoff, 3018 DMAADDR(&xfer->ux_dmabuf, sqtd->bufoff), 0); 3019 3020 if (prev) { 3021 prev->nextqtd = sqtd; 3022 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3023 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3024 } 3025 usb_syncmem(&sqtd->dma, 3026 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3027 sizeof(sqtd->qtd.qtd_status), 3028 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3029 usb_syncmem(&sqtd->dma, 3030 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3031 sizeof(sqtd->qtd.qtd_buffer[0]), 3032 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3033 3034 sqtd->qtd.qtd_buffer[0] &= ~htole32(EHCI_PAGE_MASK); 3035 sqtd->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3036 /* Reset ... */ 3037 sqtd->qtd.qtd_status &= ~htole32( 3038 EHCI_QTD_STATUS_MASK | 3039 EHCI_QTD_PID_MASK | 3040 EHCI_QTD_CERR_MASK | 3041 EHCI_QTD_C_PAGE_MASK | 3042 EHCI_QTD_BYTES_MASK | 3043 EHCI_QTD_TOGGLE_MASK); 3044 sqtd->qtd.qtd_status |= htole32( 3045 EHCI_QTD_ACTIVE | 3046 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3047 EHCI_QTD_SET_BYTES(sqtd->len) | 3048 EHCI_QTD_SET_CERR(3) | 3049 EHCI_QTD_SET_TOGGLE(tog)); 3050 3051 usb_syncmem(&sqtd->dma, 3052 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3053 sizeof(sqtd->qtd.qtd_status), 3054 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3055 usb_syncmem(&sqtd->dma, 3056 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3057 sizeof(sqtd->qtd.qtd_buffer[0]), 3058 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3059 3060 if (((sqtd->len + mps - 1) / mps) & 1) { 3061 tog ^= 1; 3062 } 3063 3064 len -= sqtd->len; 3065 if (len == 0) 3066 break; 3067 } 3068 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu i %zu", 3069 xfer, length, len, mps, exfer->ex_nsqtd, i); 3070 3071 if (i < exfer->ex_nsqtd) { 3072 /* 3073 * The full allocation chain wasn't used, so we need to 3074 * terminate it. 3075 */ 3076 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3077 } 3078 *lsqtd = sqtd; 3079 *toggle = tog; 3080 } 3081 3082 Static ehci_soft_itd_t * 3083 ehci_alloc_itd(ehci_softc_t *sc) 3084 { 3085 struct ehci_soft_itd *itd, *freeitd; 3086 usbd_status err; 3087 usb_dma_t dma; 3088 3089 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3090 3091 mutex_enter(&sc->sc_lock); 3092 3093 freeitd = LIST_FIRST(&sc->sc_freeitds); 3094 if (freeitd == NULL) { 3095 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3096 mutex_exit(&sc->sc_lock); 3097 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3098 EHCI_PAGE_SIZE, &dma); 3099 3100 if (err) { 3101 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 0); 3102 return NULL; 3103 } 3104 mutex_enter(&sc->sc_lock); 3105 3106 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3107 int offs = i * EHCI_ITD_SIZE; 3108 itd = KERNADDR(&dma, offs); 3109 itd->physaddr = DMAADDR(&dma, offs); 3110 itd->dma = dma; 3111 itd->offs = offs; 3112 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3113 } 3114 freeitd = LIST_FIRST(&sc->sc_freeitds); 3115 } 3116 3117 itd = freeitd; 3118 LIST_REMOVE(itd, free_list); 3119 mutex_exit(&sc->sc_lock); 3120 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3121 3122 itd->frame_list.next = NULL; 3123 itd->frame_list.prev = NULL; 3124 itd->xfer_next = NULL; 3125 itd->slot = 0; 3126 3127 return itd; 3128 } 3129 3130 Static ehci_soft_sitd_t * 3131 ehci_alloc_sitd(ehci_softc_t *sc) 3132 { 3133 struct ehci_soft_sitd *sitd, *freesitd; 3134 usbd_status err; 3135 int i, offs; 3136 usb_dma_t dma; 3137 3138 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3139 3140 mutex_enter(&sc->sc_lock); 3141 freesitd = LIST_FIRST(&sc->sc_freesitds); 3142 if (freesitd == NULL) { 3143 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3144 mutex_exit(&sc->sc_lock); 3145 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3146 EHCI_PAGE_SIZE, &dma); 3147 3148 if (err) { 3149 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 3150 0); 3151 return NULL; 3152 } 3153 3154 mutex_enter(&sc->sc_lock); 3155 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3156 offs = i * EHCI_SITD_SIZE; 3157 sitd = KERNADDR(&dma, offs); 3158 sitd->physaddr = DMAADDR(&dma, offs); 3159 sitd->dma = dma; 3160 sitd->offs = offs; 3161 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3162 } 3163 freesitd = LIST_FIRST(&sc->sc_freesitds); 3164 } 3165 3166 sitd = freesitd; 3167 LIST_REMOVE(sitd, free_list); 3168 mutex_exit(&sc->sc_lock); 3169 3170 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3171 3172 sitd->frame_list.next = NULL; 3173 sitd->frame_list.prev = NULL; 3174 sitd->xfer_next = NULL; 3175 sitd->slot = 0; 3176 3177 return sitd; 3178 } 3179 3180 /****************/ 3181 3182 /* 3183 * Close a reqular pipe. 3184 * Assumes that there are no pending transactions. 3185 */ 3186 Static void 3187 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3188 { 3189 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3190 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3191 ehci_soft_qh_t *sqh = epipe->sqh; 3192 3193 KASSERT(mutex_owned(&sc->sc_lock)); 3194 3195 ehci_rem_qh(sc, sqh, head); 3196 ehci_free_sqh(sc, epipe->sqh); 3197 } 3198 3199 /* 3200 * Abort a device request. 3201 * If this routine is called at splusb() it guarantees that the request 3202 * will be removed from the hardware scheduling and that the callback 3203 * for it will be called with USBD_CANCELLED status. 3204 * It's impossible to guarantee that the requested transfer will not 3205 * have happened since the hardware runs concurrently. 3206 * If the transaction has already happened we rely on the ordinary 3207 * interrupt processing to process it. 3208 * XXX This is most probably wrong. 3209 * XXXMRG this doesn't make sense anymore. 3210 */ 3211 Static void 3212 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3213 { 3214 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3215 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3216 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3217 ehci_soft_qh_t *sqh = epipe->sqh; 3218 ehci_soft_qtd_t *sqtd; 3219 ehci_physaddr_t cur; 3220 uint32_t qhstatus; 3221 int hit; 3222 int wake; 3223 3224 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3225 3226 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3227 3228 KASSERT(mutex_owned(&sc->sc_lock)); 3229 ASSERT_SLEEPABLE(); 3230 3231 if (sc->sc_dying) { 3232 /* If we're dying, just do the software part. */ 3233 xfer->ux_status = status; /* make software ignore it */ 3234 callout_stop(&xfer->ux_callout); 3235 usb_transfer_complete(xfer); 3236 return; 3237 } 3238 3239 /* 3240 * If an abort is already in progress then just wait for it to 3241 * complete and return. 3242 */ 3243 if (xfer->ux_hcflags & UXFER_ABORTING) { 3244 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3245 #ifdef DIAGNOSTIC 3246 if (status == USBD_TIMEOUT) 3247 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3248 #endif 3249 /* Override the status which might be USBD_TIMEOUT. */ 3250 xfer->ux_status = status; 3251 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3252 0, 0, 0, 0); 3253 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3254 while (xfer->ux_hcflags & UXFER_ABORTING) 3255 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3256 return; 3257 } 3258 xfer->ux_hcflags |= UXFER_ABORTING; 3259 3260 /* 3261 * Step 1: Make interrupt routine and hardware ignore xfer. 3262 */ 3263 xfer->ux_status = status; /* make software ignore it */ 3264 callout_stop(&xfer->ux_callout); 3265 3266 usb_syncmem(&sqh->dma, 3267 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3268 sizeof(sqh->qh.qh_qtd.qtd_status), 3269 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3270 qhstatus = sqh->qh.qh_qtd.qtd_status; 3271 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3272 usb_syncmem(&sqh->dma, 3273 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3274 sizeof(sqh->qh.qh_qtd.qtd_status), 3275 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3276 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3277 usb_syncmem(&sqtd->dma, 3278 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3279 sizeof(sqtd->qtd.qtd_status), 3280 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3281 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3282 usb_syncmem(&sqtd->dma, 3283 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3284 sizeof(sqtd->qtd.qtd_status), 3285 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3286 if (sqtd == exfer->ex_sqtdend) 3287 break; 3288 } 3289 3290 /* 3291 * Step 2: Wait until we know hardware has finished any possible 3292 * use of the xfer. Also make sure the soft interrupt routine 3293 * has run. 3294 */ 3295 ehci_sync_hc(sc); 3296 sc->sc_softwake = 1; 3297 usb_schedsoftintr(&sc->sc_bus); 3298 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3299 3300 /* 3301 * Step 3: Remove any vestiges of the xfer from the hardware. 3302 * The complication here is that the hardware may have executed 3303 * beyond the xfer we're trying to abort. So as we're scanning 3304 * the TDs of this xfer we check if the hardware points to 3305 * any of them. 3306 */ 3307 3308 usb_syncmem(&sqh->dma, 3309 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3310 sizeof(sqh->qh.qh_curqtd), 3311 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3312 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3313 hit = 0; 3314 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3315 hit |= cur == sqtd->physaddr; 3316 if (sqtd == exfer->ex_sqtdend) 3317 break; 3318 } 3319 sqtd = sqtd->nextqtd; 3320 /* Zap curqtd register if hardware pointed inside the xfer. */ 3321 if (hit && sqtd != NULL) { 3322 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3323 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3324 usb_syncmem(&sqh->dma, 3325 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3326 sizeof(sqh->qh.qh_curqtd), 3327 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3328 sqh->qh.qh_qtd.qtd_status = qhstatus; 3329 usb_syncmem(&sqh->dma, 3330 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3331 sizeof(sqh->qh.qh_qtd.qtd_status), 3332 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3333 } else { 3334 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3335 usb_syncmem(&sqh->dma, 3336 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3337 sizeof(sqh->qh.qh_curqtd), 3338 BUS_DMASYNC_PREREAD); 3339 } 3340 3341 /* 3342 * Step 4: Execute callback. 3343 */ 3344 #ifdef DIAGNOSTIC 3345 exfer->ex_isdone = true; 3346 #endif 3347 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3348 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3349 usb_transfer_complete(xfer); 3350 if (wake) { 3351 cv_broadcast(&xfer->ux_hccv); 3352 } 3353 3354 KASSERT(mutex_owned(&sc->sc_lock)); 3355 } 3356 3357 Static void 3358 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3359 { 3360 ehci_isoc_trans_t trans_status; 3361 struct ehci_xfer *exfer; 3362 ehci_softc_t *sc; 3363 struct ehci_soft_itd *itd; 3364 struct ehci_soft_sitd *sitd; 3365 int i, wake; 3366 3367 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3368 3369 exfer = EHCI_XFER2EXFER(xfer); 3370 sc = EHCI_XFER2SC(xfer); 3371 3372 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3373 3374 KASSERT(mutex_owned(&sc->sc_lock)); 3375 3376 if (sc->sc_dying) { 3377 xfer->ux_status = status; 3378 callout_stop(&xfer->ux_callout); 3379 usb_transfer_complete(xfer); 3380 return; 3381 } 3382 3383 if (xfer->ux_hcflags & UXFER_ABORTING) { 3384 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3385 3386 #ifdef DIAGNOSTIC 3387 if (status == USBD_TIMEOUT) 3388 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3389 #endif 3390 3391 xfer->ux_status = status; 3392 USBHIST_LOG(ehcidebug, 3393 "waiting for abort to finish", 0, 0, 0, 0); 3394 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3395 while (xfer->ux_hcflags & UXFER_ABORTING) 3396 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3397 goto done; 3398 } 3399 xfer->ux_hcflags |= UXFER_ABORTING; 3400 3401 xfer->ux_status = status; 3402 callout_stop(&xfer->ux_callout); 3403 3404 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3405 for (itd = exfer->ex_itdstart; itd != NULL; 3406 itd = itd->xfer_next) { 3407 usb_syncmem(&itd->dma, 3408 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3409 sizeof(itd->itd.itd_ctl), 3410 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3411 3412 for (i = 0; i < 8; i++) { 3413 trans_status = le32toh(itd->itd.itd_ctl[i]); 3414 trans_status &= ~EHCI_ITD_ACTIVE; 3415 itd->itd.itd_ctl[i] = htole32(trans_status); 3416 } 3417 3418 usb_syncmem(&itd->dma, 3419 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3420 sizeof(itd->itd.itd_ctl), 3421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3422 } 3423 } else { 3424 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3425 sitd = sitd->xfer_next) { 3426 usb_syncmem(&sitd->dma, 3427 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3428 sizeof(sitd->sitd.sitd_buffer), 3429 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3430 3431 trans_status = le32toh(sitd->sitd.sitd_trans); 3432 trans_status &= ~EHCI_SITD_ACTIVE; 3433 sitd->sitd.sitd_trans = htole32(trans_status); 3434 3435 usb_syncmem(&sitd->dma, 3436 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3437 sizeof(sitd->sitd.sitd_buffer), 3438 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3439 } 3440 } 3441 3442 sc->sc_softwake = 1; 3443 usb_schedsoftintr(&sc->sc_bus); 3444 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3445 3446 #ifdef DIAGNOSTIC 3447 exfer->ex_isdone = true; 3448 #endif 3449 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3450 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3451 usb_transfer_complete(xfer); 3452 if (wake) { 3453 cv_broadcast(&xfer->ux_hccv); 3454 } 3455 3456 done: 3457 KASSERT(mutex_owned(&sc->sc_lock)); 3458 return; 3459 } 3460 3461 Static void 3462 ehci_timeout(void *addr) 3463 { 3464 struct usbd_xfer *xfer = addr; 3465 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3466 struct usbd_pipe *pipe = xfer->ux_pipe; 3467 struct usbd_device *dev = pipe->up_dev; 3468 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3469 3470 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3471 3472 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3473 #ifdef EHCI_DEBUG 3474 if (ehcidebug >= 2) 3475 usbd_dump_pipe(pipe); 3476 #endif 3477 3478 if (sc->sc_dying) { 3479 mutex_enter(&sc->sc_lock); 3480 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3481 mutex_exit(&sc->sc_lock); 3482 return; 3483 } 3484 3485 /* Execute the abort in a process context. */ 3486 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3487 USB_TASKQ_MPSAFE); 3488 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3489 } 3490 3491 Static void 3492 ehci_timeout_task(void *addr) 3493 { 3494 struct usbd_xfer *xfer = addr; 3495 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3496 3497 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3498 3499 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3500 3501 mutex_enter(&sc->sc_lock); 3502 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3503 mutex_exit(&sc->sc_lock); 3504 } 3505 3506 /************************/ 3507 3508 Static int 3509 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3510 { 3511 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3512 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3513 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3514 usb_device_request_t *req = &xfer->ux_request; 3515 ehci_soft_qtd_t *setup, *status, *next; 3516 int isread = req->bmRequestType & UT_READ; 3517 int len = xfer->ux_bufsize; 3518 int err; 3519 3520 exfer->ex_type = EX_CTRL; 3521 exfer->ex_status = NULL; 3522 exfer->ex_data = NULL; 3523 exfer->ex_setup = ehci_alloc_sqtd(sc); 3524 if (exfer->ex_setup == NULL) { 3525 err = ENOMEM; 3526 goto bad1; 3527 } 3528 exfer->ex_status = ehci_alloc_sqtd(sc); 3529 if (exfer->ex_status == NULL) { 3530 err = ENOMEM; 3531 goto bad2; 3532 } 3533 setup = exfer->ex_setup; 3534 status = exfer->ex_status; 3535 exfer->ex_nsqtd = 0; 3536 next = status; 3537 /* Set up data transaction */ 3538 if (len != 0) { 3539 ehci_soft_qtd_t *end; 3540 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3541 &exfer->ex_data, &end); 3542 if (err) 3543 goto bad3; 3544 next = exfer->ex_data; 3545 } 3546 3547 /* Clear toggle */ 3548 setup->qtd.qtd_status = htole32( 3549 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3550 EHCI_QTD_SET_TOGGLE(0) | 3551 EHCI_QTD_SET_BYTES(sizeof(*req)) 3552 ); 3553 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3554 setup->qtd.qtd_buffer_hi[0] = 0; 3555 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3556 setup->nextqtd = next; 3557 setup->xfer = xfer; 3558 setup->tdlen = setup->len = sizeof(*req); 3559 3560 status->qtd.qtd_status = htole32( 3561 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3562 EHCI_QTD_SET_TOGGLE(1) | 3563 EHCI_QTD_IOC 3564 ); 3565 status->qtd.qtd_buffer[0] = 0; 3566 status->qtd.qtd_buffer_hi[0] = 0; 3567 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3568 status->nextqtd = NULL; 3569 status->xfer = xfer; 3570 status->tdlen = status->len = 0; 3571 3572 return 0; 3573 bad3: 3574 ehci_free_sqtd(sc, exfer->ex_status); 3575 bad2: 3576 ehci_free_sqtd(sc, exfer->ex_setup); 3577 bad1: 3578 return err; 3579 } 3580 3581 Static void 3582 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3583 { 3584 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3585 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3586 3587 KASSERT(ex->ex_type == EX_CTRL); 3588 3589 ehci_free_sqtd(sc, ex->ex_setup); 3590 ehci_free_sqtd(sc, ex->ex_status); 3591 ehci_free_sqtds(sc, ex); 3592 if (ex->ex_nsqtd) 3593 kmem_free(ex->ex_sqtds, 3594 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3595 } 3596 3597 Static usbd_status 3598 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3599 { 3600 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3601 usbd_status err; 3602 3603 /* Insert last in queue. */ 3604 mutex_enter(&sc->sc_lock); 3605 err = usb_insert_transfer(xfer); 3606 mutex_exit(&sc->sc_lock); 3607 if (err) 3608 return err; 3609 3610 /* Pipe isn't running, start first */ 3611 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3612 } 3613 3614 Static usbd_status 3615 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3616 { 3617 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3618 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3619 usb_device_request_t *req = &xfer->ux_request; 3620 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3621 ehci_soft_qtd_t *setup, *status, *next; 3622 ehci_soft_qh_t *sqh; 3623 3624 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3625 3626 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3627 3628 if (sc->sc_dying) 3629 return USBD_IOERROR; 3630 3631 const int isread = req->bmRequestType & UT_READ; 3632 const int len = UGETW(req->wLength); 3633 3634 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3635 "wValue=0x%04x, wIndex=0x%04x", 3636 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3637 UGETW(req->wIndex)); 3638 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3639 len, epipe->pipe.up_dev->ud_addr, 3640 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3641 3642 sqh = epipe->sqh; 3643 3644 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3645 "address QH %" __PRIuBIT " pipe %d\n", 3646 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3647 epipe->pipe.up_dev->ud_addr); 3648 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3649 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3650 "MPS QH %" __PRIuBIT " pipe %d\n", 3651 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3652 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3653 3654 setup = exfer->ex_setup; 3655 status = exfer->ex_status; 3656 3657 USBHIST_LOG(ehcidebug, "setup %p status %p data %p", 3658 setup, status, exfer->ex_data, 0); 3659 KASSERTMSG(setup != NULL && status != NULL, 3660 "Failed memory allocation, setup %p status %p", 3661 setup, status); 3662 3663 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3664 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3665 3666 /* Clear toggle */ 3667 setup->qtd.qtd_status &= ~htole32( 3668 EHCI_QTD_STATUS_MASK | 3669 EHCI_QTD_BYTES_MASK | 3670 EHCI_QTD_TOGGLE_MASK | 3671 EHCI_QTD_CERR_MASK 3672 ); 3673 setup->qtd.qtd_status |= htole32( 3674 EHCI_QTD_ACTIVE | 3675 EHCI_QTD_SET_CERR(3) | 3676 EHCI_QTD_SET_TOGGLE(0) | 3677 EHCI_QTD_SET_BYTES(sizeof(*req)) 3678 ); 3679 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3680 setup->qtd.qtd_buffer_hi[0] = 0; 3681 3682 next = status; 3683 status->qtd.qtd_status &= ~htole32( 3684 EHCI_QTD_STATUS_MASK | 3685 EHCI_QTD_PID_MASK | 3686 EHCI_QTD_BYTES_MASK | 3687 EHCI_QTD_TOGGLE_MASK | 3688 EHCI_QTD_CERR_MASK 3689 ); 3690 status->qtd.qtd_status |= htole32( 3691 EHCI_QTD_ACTIVE | 3692 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3693 EHCI_QTD_SET_CERR(3) | 3694 EHCI_QTD_SET_TOGGLE(1) | 3695 EHCI_QTD_SET_BYTES(0) | 3696 EHCI_QTD_IOC 3697 ); 3698 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3699 3700 KASSERT(exfer->ex_isdone); 3701 #ifdef DIAGNOSTIC 3702 exfer->ex_isdone = false; 3703 #endif 3704 3705 /* Set up data transaction */ 3706 if (len != 0) { 3707 ehci_soft_qtd_t *end; 3708 3709 /* Start toggle at 1. */ 3710 int toggle = 1; 3711 next = exfer->ex_data; 3712 KASSERTMSG(next != NULL, "Failed memory allocation"); 3713 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3714 end->nextqtd = status; 3715 end->qtd.qtd_next = end->qtd.qtd_altnext = 3716 htole32(status->physaddr); 3717 3718 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3719 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3720 3721 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3722 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3723 } 3724 3725 setup->nextqtd = next; 3726 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3727 3728 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3729 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3730 3731 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3732 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3733 3734 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3735 3736 #ifdef EHCI_DEBUG 3737 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3738 ehci_dump_sqh(sqh); 3739 ehci_dump_sqtds(setup); 3740 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3741 #endif 3742 3743 mutex_enter(&sc->sc_lock); 3744 3745 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3746 ehci_set_qh_qtd(sqh, setup); 3747 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3748 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3749 ehci_timeout, xfer); 3750 } 3751 ehci_add_intr_list(sc, exfer); 3752 xfer->ux_status = USBD_IN_PROGRESS; 3753 mutex_exit(&sc->sc_lock); 3754 3755 #if 0 3756 #ifdef EHCI_DEBUG 3757 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3758 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3759 // delay(10000); 3760 ehci_dump_regs(sc); 3761 ehci_dump_sqh(sc->sc_async_head); 3762 ehci_dump_sqh(sqh); 3763 ehci_dump_sqtds(setup); 3764 #endif 3765 #endif 3766 3767 if (sc->sc_bus.ub_usepolling) 3768 ehci_waitintr(sc, xfer); 3769 3770 return USBD_IN_PROGRESS; 3771 } 3772 3773 Static void 3774 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3775 { 3776 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3777 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3778 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3779 usb_device_request_t *req = &xfer->ux_request; 3780 int len = UGETW(req->wLength); 3781 int rd = req->bmRequestType & UT_READ; 3782 3783 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3784 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3785 3786 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3787 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3788 3789 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3790 ehci_del_intr_list(sc, ex); /* remove from active list */ 3791 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3792 BUS_DMASYNC_POSTWRITE); 3793 if (len) 3794 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3795 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3796 } 3797 3798 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3799 } 3800 3801 /* Abort a device control request. */ 3802 Static void 3803 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3804 { 3805 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3806 3807 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3808 ehci_abort_xfer(xfer, USBD_CANCELLED); 3809 } 3810 3811 /* Close a device control pipe. */ 3812 Static void 3813 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3814 { 3815 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3816 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3817 3818 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3819 3820 KASSERT(mutex_owned(&sc->sc_lock)); 3821 3822 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3823 3824 ehci_close_pipe(pipe, sc->sc_async_head); 3825 } 3826 3827 /* 3828 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3829 * qTD status, or miss signalling occasionally under heavy load. If the host 3830 * machine is too fast, we we can miss transaction completion - when we scan 3831 * the active list the transaction still seems to be active. This generally 3832 * exhibits itself as a umass stall that never recovers. 3833 * 3834 * We work around this behaviour by setting up this callback after any softintr 3835 * that completes with transactions still pending, giving us another chance to 3836 * check for completion after the writeback has taken place. 3837 */ 3838 Static void 3839 ehci_intrlist_timeout(void *arg) 3840 { 3841 ehci_softc_t *sc = arg; 3842 3843 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3844 3845 usb_schedsoftintr(&sc->sc_bus); 3846 } 3847 3848 /************************/ 3849 3850 Static int 3851 ehci_device_bulk_init(struct usbd_xfer *xfer) 3852 { 3853 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3854 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3855 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3856 int endpt = ed->bEndpointAddress; 3857 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3858 int len = xfer->ux_bufsize; 3859 int err = 0; 3860 3861 exfer->ex_type = EX_BULK; 3862 exfer->ex_nsqtd = 0; 3863 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3864 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 3865 3866 return err; 3867 } 3868 3869 Static void 3870 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3871 { 3872 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3873 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3874 3875 KASSERT(ex->ex_type == EX_BULK); 3876 3877 ehci_free_sqtds(sc, ex); 3878 if (ex->ex_nsqtd) 3879 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3880 } 3881 3882 Static usbd_status 3883 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3884 { 3885 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3886 usbd_status err; 3887 3888 /* Insert last in queue. */ 3889 mutex_enter(&sc->sc_lock); 3890 err = usb_insert_transfer(xfer); 3891 mutex_exit(&sc->sc_lock); 3892 if (err) 3893 return err; 3894 3895 /* Pipe isn't running, start first */ 3896 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3897 } 3898 3899 Static usbd_status 3900 ehci_device_bulk_start(struct usbd_xfer *xfer) 3901 { 3902 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3903 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3904 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3905 ehci_soft_qh_t *sqh; 3906 ehci_soft_qtd_t *end; 3907 int len, isread, endpt; 3908 3909 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3910 3911 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3912 xfer, xfer->ux_length, xfer->ux_flags, 0); 3913 3914 if (sc->sc_dying) 3915 return USBD_IOERROR; 3916 3917 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3918 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3919 3920 len = xfer->ux_length; 3921 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3922 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3923 sqh = epipe->sqh; 3924 3925 KASSERT(exfer->ex_isdone); 3926 #ifdef DIAGNOSTIC 3927 exfer->ex_isdone = false; 3928 #endif 3929 3930 /* Take lock here to protect nexttoggle */ 3931 mutex_enter(&sc->sc_lock); 3932 3933 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3934 3935 exfer->ex_sqtdend = end; 3936 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3937 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3938 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3939 3940 #ifdef EHCI_DEBUG 3941 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3942 ehci_dump_sqh(sqh); 3943 ehci_dump_sqtds(exfer->ex_sqtdstart); 3944 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3945 #endif 3946 3947 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3948 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3949 3950 /* also does usb_syncmem(sqh) */ 3951 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3952 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3953 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3954 ehci_timeout, xfer); 3955 } 3956 ehci_add_intr_list(sc, exfer); 3957 xfer->ux_status = USBD_IN_PROGRESS; 3958 mutex_exit(&sc->sc_lock); 3959 3960 #if 0 3961 #ifdef EHCI_DEBUG 3962 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3963 // delay(10000); 3964 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3965 ehci_dump_regs(sc); 3966 #if 0 3967 printf("async_head:\n"); 3968 ehci_dump_sqh(sc->sc_async_head); 3969 #endif 3970 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3971 ehci_dump_sqh(sqh); 3972 ehci_dump_sqtds(exfer->ex_sqtdstart); 3973 #endif 3974 #endif 3975 3976 if (sc->sc_bus.ub_usepolling) 3977 ehci_waitintr(sc, xfer); 3978 3979 return USBD_IN_PROGRESS; 3980 } 3981 3982 Static void 3983 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3984 { 3985 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3986 3987 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3988 ehci_abort_xfer(xfer, USBD_CANCELLED); 3989 } 3990 3991 /* 3992 * Close a device bulk pipe. 3993 */ 3994 Static void 3995 ehci_device_bulk_close(struct usbd_pipe *pipe) 3996 { 3997 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3998 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3999 4000 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4001 4002 KASSERT(mutex_owned(&sc->sc_lock)); 4003 4004 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 4005 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4006 ehci_close_pipe(pipe, sc->sc_async_head); 4007 } 4008 4009 Static void 4010 ehci_device_bulk_done(struct usbd_xfer *xfer) 4011 { 4012 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4013 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4014 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4015 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4016 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4017 4018 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4019 4020 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4021 0, 0); 4022 4023 KASSERT(mutex_owned(&sc->sc_lock)); 4024 4025 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4026 ehci_del_intr_list(sc, ex); /* remove from active list */ 4027 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4028 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4029 } 4030 4031 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 4032 } 4033 4034 /************************/ 4035 4036 Static usbd_status 4037 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4038 { 4039 struct ehci_soft_islot *isp; 4040 int islot, lev; 4041 4042 /* Find a poll rate that is large enough. */ 4043 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4044 if (EHCI_ILEV_IVAL(lev) <= ival) 4045 break; 4046 4047 /* Pick an interrupt slot at the right level. */ 4048 /* XXX could do better than picking at random */ 4049 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4050 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4051 4052 sqh->islot = islot; 4053 isp = &sc->sc_islots[islot]; 4054 mutex_enter(&sc->sc_lock); 4055 ehci_add_qh(sc, sqh, isp->sqh); 4056 mutex_exit(&sc->sc_lock); 4057 4058 return USBD_NORMAL_COMPLETION; 4059 } 4060 4061 4062 Static int 4063 ehci_device_intr_init(struct usbd_xfer *xfer) 4064 { 4065 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4066 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4067 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4068 int endpt = ed->bEndpointAddress; 4069 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4070 int len = xfer->ux_bufsize; 4071 int err; 4072 4073 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4074 4075 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4076 xfer->ux_flags, 0); 4077 4078 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4079 KASSERT(len != 0); 4080 4081 exfer->ex_type = EX_INTR; 4082 exfer->ex_nsqtd = 0; 4083 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4084 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 4085 4086 return err; 4087 } 4088 4089 Static void 4090 ehci_device_intr_fini(struct usbd_xfer *xfer) 4091 { 4092 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4093 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4094 4095 KASSERT(ex->ex_type == EX_INTR); 4096 4097 ehci_free_sqtds(sc, ex); 4098 if (ex->ex_nsqtd) 4099 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4100 } 4101 4102 Static usbd_status 4103 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4104 { 4105 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4106 usbd_status err; 4107 4108 /* Insert last in queue. */ 4109 mutex_enter(&sc->sc_lock); 4110 err = usb_insert_transfer(xfer); 4111 mutex_exit(&sc->sc_lock); 4112 if (err) 4113 return err; 4114 4115 /* 4116 * Pipe isn't running (otherwise err would be USBD_INPROG), 4117 * so start it first. 4118 */ 4119 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4120 } 4121 4122 Static usbd_status 4123 ehci_device_intr_start(struct usbd_xfer *xfer) 4124 { 4125 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4126 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4127 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4128 ehci_soft_qtd_t *end; 4129 ehci_soft_qh_t *sqh; 4130 int len, isread, endpt; 4131 4132 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4133 4134 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4135 xfer->ux_flags, 0); 4136 4137 if (sc->sc_dying) 4138 return USBD_IOERROR; 4139 4140 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4141 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4142 4143 len = xfer->ux_length; 4144 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4145 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4146 sqh = epipe->sqh; 4147 4148 KASSERT(exfer->ex_isdone); 4149 #ifdef DIAGNOSTIC 4150 exfer->ex_isdone = false; 4151 #endif 4152 4153 /* Take lock to protect nexttoggle */ 4154 mutex_enter(&sc->sc_lock); 4155 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4156 4157 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4158 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4159 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4160 exfer->ex_sqtdend = end; 4161 4162 #ifdef EHCI_DEBUG 4163 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 4164 ehci_dump_sqh(sqh); 4165 ehci_dump_sqtds(exfer->ex_sqtdstart); 4166 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 4167 #endif 4168 4169 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4170 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4171 4172 /* also does usb_syncmem(sqh) */ 4173 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4174 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4175 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4176 ehci_timeout, xfer); 4177 } 4178 ehci_add_intr_list(sc, exfer); 4179 xfer->ux_status = USBD_IN_PROGRESS; 4180 mutex_exit(&sc->sc_lock); 4181 4182 #if 0 4183 #ifdef EHCI_DEBUG 4184 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4185 // delay(10000); 4186 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4187 ehci_dump_regs(sc); 4188 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4189 ehci_dump_sqh(sqh); 4190 ehci_dump_sqtds(exfer->ex_sqtdstart); 4191 #endif 4192 #endif 4193 4194 if (sc->sc_bus.ub_usepolling) 4195 ehci_waitintr(sc, xfer); 4196 4197 return USBD_IN_PROGRESS; 4198 } 4199 4200 Static void 4201 ehci_device_intr_abort(struct usbd_xfer *xfer) 4202 { 4203 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4204 4205 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4206 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4207 4208 /* 4209 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4210 * async doorbell. That's dependent on the async list, wheras 4211 * intr xfers are periodic, should not use this? 4212 */ 4213 ehci_abort_xfer(xfer, USBD_CANCELLED); 4214 } 4215 4216 Static void 4217 ehci_device_intr_close(struct usbd_pipe *pipe) 4218 { 4219 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4220 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4221 struct ehci_soft_islot *isp; 4222 4223 KASSERT(mutex_owned(&sc->sc_lock)); 4224 4225 isp = &sc->sc_islots[epipe->sqh->islot]; 4226 ehci_close_pipe(pipe, isp->sqh); 4227 } 4228 4229 Static void 4230 ehci_device_intr_done(struct usbd_xfer *xfer) 4231 { 4232 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4233 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4234 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4235 ehci_soft_qh_t *sqh; 4236 int len, isread, endpt; 4237 4238 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4239 4240 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4241 0, 0); 4242 4243 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4244 4245 if (xfer->ux_pipe->up_repeat) { 4246 4247 KASSERT(exfer->ex_isdone); 4248 #ifdef DIAGNOSTIC 4249 exfer->ex_isdone = false; 4250 #endif 4251 4252 len = xfer->ux_length; 4253 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4254 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4255 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4256 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4257 sqh = epipe->sqh; 4258 4259 ehci_soft_qtd_t *end; 4260 ehci_reset_sqtd_chain(sc, xfer, len, isread, 4261 &epipe->nexttoggle, &end); 4262 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4263 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4264 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4265 4266 exfer->ex_sqtdend = end; 4267 4268 /* also does usb_syncmem(sqh) */ 4269 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4270 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4271 callout_reset(&xfer->ux_callout, 4272 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4273 } 4274 4275 xfer->ux_status = USBD_IN_PROGRESS; 4276 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4277 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4278 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4279 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4280 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4281 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4282 } 4283 } 4284 4285 /************************/ 4286 Static int 4287 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4288 { 4289 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4290 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4291 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4292 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4293 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4294 int i, k, frames; 4295 u_int huba, dir; 4296 int err; 4297 4298 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4299 4300 start = NULL; 4301 sitd = NULL; 4302 4303 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", xfer, xfer->ux_length, 4304 xfer->ux_flags, 0); 4305 4306 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4307 KASSERT(xfer->ux_nframes != 0); 4308 KASSERT(exfer->ex_isdone); 4309 4310 exfer->ex_type = EX_FS_ISOC; 4311 /* 4312 * Step 1: Allocate and initialize sitds. 4313 */ 4314 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4315 if (i > 16 || i == 0) { 4316 /* Spec page 271 says intervals > 16 are invalid */ 4317 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4318 4319 return EINVAL; 4320 } 4321 4322 frames = xfer->ux_nframes; 4323 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4324 sitd = ehci_alloc_sitd(sc); 4325 if (sitd == NULL) { 4326 err = ENOMEM; 4327 goto fail; 4328 } 4329 4330 if (prev) 4331 prev->xfer_next = sitd; 4332 else 4333 start = sitd; 4334 4335 huba = dev->ud_myhsport->up_parent->ud_addr; 4336 4337 #if 0 4338 if (sc->sc_flags & EHCIF_FREESCALE) { 4339 // Set hub address to 0 if embedded TT is used. 4340 if (huba == sc->sc_addr) 4341 huba = 0; 4342 } 4343 #endif 4344 4345 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4346 dir = UE_GET_DIR(k) ? 1 : 0; 4347 sitd->sitd.sitd_endp = 4348 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4349 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4350 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4351 EHCI_SITD_SET_HUBA(huba) | 4352 EHCI_SITD_SET_DIR(dir)); 4353 4354 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4355 } /* End of frame */ 4356 4357 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4358 4359 stop = sitd; 4360 stop->xfer_next = NULL; 4361 exfer->ex_sitdstart = start; 4362 exfer->ex_sitdend = stop; 4363 4364 return 0; 4365 4366 fail: 4367 mutex_enter(&sc->sc_lock); 4368 ehci_soft_sitd_t *next; 4369 for (sitd = start; sitd; sitd = next) { 4370 next = sitd->xfer_next; 4371 ehci_free_sitd_locked(sc, sitd); 4372 } 4373 mutex_exit(&sc->sc_lock); 4374 4375 return err; 4376 } 4377 4378 Static void 4379 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4380 { 4381 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4382 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4383 4384 KASSERT(ex->ex_type == EX_FS_ISOC); 4385 4386 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4387 } 4388 4389 Static usbd_status 4390 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4391 { 4392 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4393 usbd_status err; 4394 4395 mutex_enter(&sc->sc_lock); 4396 err = usb_insert_transfer(xfer); 4397 mutex_exit(&sc->sc_lock); 4398 4399 if (err && err != USBD_IN_PROGRESS) 4400 return err; 4401 4402 return ehci_device_fs_isoc_start(xfer); 4403 } 4404 4405 Static usbd_status 4406 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4407 { 4408 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4409 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4410 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4411 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4412 ehci_soft_sitd_t *sitd; 4413 usb_dma_t *dma_buf; 4414 int i, j, k, frames; 4415 int offs, total_length; 4416 int frindex; 4417 u_int dir; 4418 4419 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4420 4421 sitd = NULL; 4422 total_length = 0; 4423 4424 /* 4425 * To allow continuous transfers, above we start all transfers 4426 * immediately. However, we're still going to get usbd_start_next call 4427 * this when another xfer completes. So, check if this is already 4428 * in progress or not 4429 */ 4430 4431 if (exfer->ex_isrunning) { 4432 return USBD_IN_PROGRESS; 4433 } 4434 4435 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4436 xfer, xfer->ux_length, xfer->ux_flags, 0); 4437 4438 if (sc->sc_dying) 4439 return USBD_IOERROR; 4440 4441 /* 4442 * To avoid complication, don't allow a request right now that'll span 4443 * the entire frame table. To within 4 frames, to allow some leeway 4444 * on either side of where the hc currently is. 4445 */ 4446 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4447 xfer->ux_nframes >= sc->sc_flsize - 4) { 4448 printf("ehci: isoc descriptor requested that spans the entire" 4449 "frametable, too many frames\n"); 4450 return USBD_INVAL; 4451 } 4452 4453 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4454 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4455 KASSERT(exfer->ex_isdone); 4456 #ifdef DIAGNOSTIC 4457 exfer->ex_isdone = false; 4458 #endif 4459 4460 /* 4461 * Step 1: Initialize sitds. 4462 */ 4463 4464 frames = xfer->ux_nframes; 4465 dma_buf = &xfer->ux_dmabuf; 4466 offs = 0; 4467 4468 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4469 i++, sitd = sitd->xfer_next) { 4470 KASSERT(sitd != NULL); 4471 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4472 4473 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4474 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4475 4476 /* Set page0 index and offset - TP and T-offset are set below */ 4477 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4478 4479 total_length += xfer->ux_frlengths[i]; 4480 offs += xfer->ux_frlengths[i]; 4481 4482 sitd->sitd.sitd_buffer[1] = 4483 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4484 4485 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4486 4487 #if 0 4488 if (sc->sc_flags & EHCIF_FREESCALE) { 4489 // Set hub address to 0 if embedded TT is used. 4490 if (huba == sc->sc_addr) 4491 huba = 0; 4492 } 4493 #endif 4494 4495 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4496 dir = UE_GET_DIR(k) ? 1 : 0; 4497 KASSERT(sitd->sitd.sitd_endp == htole32( 4498 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4499 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4500 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4501 EHCI_SITD_SET_HUBA(huba) | 4502 EHCI_SITD_SET_DIR(dir))); 4503 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4504 4505 uint8_t sa = 0; 4506 uint8_t sb = 0; 4507 u_int temp, tlen; 4508 4509 if (dir == 0) { /* OUT */ 4510 temp = 0; 4511 tlen = xfer->ux_frlengths[i]; 4512 if (tlen <= 188) { 4513 temp |= 1; /* T-count = 1, TP = ALL */ 4514 tlen = 1; 4515 } else { 4516 tlen += 187; 4517 tlen /= 188; 4518 temp |= tlen; /* T-count = [1..6] */ 4519 temp |= 8; /* TP = Begin */ 4520 } 4521 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4522 4523 tlen += sa; 4524 4525 if (tlen >= 8) { 4526 sb = 0; 4527 } else { 4528 sb = (1 << tlen); 4529 } 4530 4531 sa = (1 << sa); 4532 sa = (sb - sa) & 0x3F; 4533 sb = 0; 4534 } else { 4535 sb = (-(4 << sa)) & 0xFE; 4536 sa = (1 << sa) & 0x3F; 4537 sa = 0x01; 4538 sb = 0xfc; 4539 } 4540 4541 sitd->sitd.sitd_sched = htole32( 4542 EHCI_SITD_SET_SMASK(sa) | 4543 EHCI_SITD_SET_CMASK(sb) 4544 ); 4545 4546 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4547 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4548 } /* End of frame */ 4549 4550 sitd = exfer->ex_sitdend; 4551 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4552 4553 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4554 sizeof(sitd->sitd.sitd_trans), 4555 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4556 4557 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4558 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4559 4560 /* 4561 * Part 2: Transfer descriptors have now been set up, now they must 4562 * be scheduled into the periodic frame list. Erk. Not wanting to 4563 * complicate matters, transfer is denied if the transfer spans 4564 * more than the period frame list. 4565 */ 4566 4567 mutex_enter(&sc->sc_lock); 4568 4569 /* Start inserting frames */ 4570 if (epipe->isoc.cur_xfers > 0) { 4571 frindex = epipe->isoc.next_frame; 4572 } else { 4573 frindex = EOREAD4(sc, EHCI_FRINDEX); 4574 frindex = frindex >> 3; /* Erase microframe index */ 4575 frindex += 2; 4576 } 4577 4578 if (frindex >= sc->sc_flsize) 4579 frindex &= (sc->sc_flsize - 1); 4580 4581 /* Whats the frame interval? */ 4582 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4583 4584 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4585 j++, sitd = sitd->xfer_next) { 4586 KASSERT(sitd); 4587 4588 usb_syncmem(&sc->sc_fldma, 4589 sizeof(ehci_link_t) * frindex, 4590 sizeof(ehci_link_t), 4591 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4592 4593 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4594 if (sitd->sitd.sitd_next == 0) 4595 /* 4596 * FIXME: frindex table gets initialized to NULL 4597 * or EHCI_NULL? 4598 */ 4599 sitd->sitd.sitd_next = EHCI_NULL; 4600 4601 usb_syncmem(&sitd->dma, 4602 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4603 sizeof(ehci_sitd_t), 4604 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4605 4606 sc->sc_flist[frindex] = 4607 htole32(EHCI_LINK_SITD | sitd->physaddr); 4608 4609 usb_syncmem(&sc->sc_fldma, 4610 sizeof(ehci_link_t) * frindex, 4611 sizeof(ehci_link_t), 4612 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4613 4614 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4615 sc->sc_softsitds[frindex] = sitd; 4616 if (sitd->frame_list.next != NULL) 4617 sitd->frame_list.next->frame_list.prev = sitd; 4618 sitd->slot = frindex; 4619 sitd->frame_list.prev = NULL; 4620 4621 frindex += i; 4622 if (frindex >= sc->sc_flsize) 4623 frindex -= sc->sc_flsize; 4624 } 4625 4626 epipe->isoc.cur_xfers++; 4627 epipe->isoc.next_frame = frindex; 4628 4629 exfer->ex_isrunning = true; 4630 4631 ehci_add_intr_list(sc, exfer); 4632 xfer->ux_status = USBD_IN_PROGRESS; 4633 4634 mutex_exit(&sc->sc_lock); 4635 4636 if (sc->sc_bus.ub_usepolling) { 4637 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4638 ehci_waitintr(sc, xfer); 4639 } 4640 4641 return USBD_IN_PROGRESS; 4642 } 4643 4644 Static void 4645 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4646 { 4647 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4648 4649 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4650 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4651 } 4652 4653 Static void 4654 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4655 { 4656 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4657 4658 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4659 } 4660 4661 Static void 4662 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4663 { 4664 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4665 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4666 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4667 4668 KASSERT(mutex_owned(&sc->sc_lock)); 4669 4670 epipe->isoc.cur_xfers--; 4671 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4672 ehci_del_intr_list(sc, exfer); 4673 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4674 exfer->ex_isrunning = false; 4675 } 4676 4677 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4678 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4679 } 4680 4681 4682 /************************/ 4683 4684 4685 Static int 4686 ehci_device_isoc_init(struct usbd_xfer *xfer) 4687 { 4688 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4689 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4690 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4691 ehci_soft_itd_t *itd, *prev, *start, *stop; 4692 int i, j, k; 4693 int frames, ufrperframe; 4694 int err; 4695 4696 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4697 4698 start = NULL; 4699 prev = NULL; 4700 itd = NULL; 4701 4702 KASSERT(xfer->ux_nframes != 0); 4703 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4704 KASSERT(exfer->ex_isdone); 4705 4706 exfer->ex_type = EX_ISOC; 4707 4708 /* 4709 * Step 1: Allocate and initialize itds, how many do we need? 4710 * One per transfer if interval >= 8 microframes, less if we use 4711 * multiple microframes per frame. 4712 */ 4713 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4714 if (i > 16 || i == 0) { 4715 /* Spec page 271 says intervals > 16 are invalid */ 4716 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4717 return USBD_INVAL; 4718 } 4719 4720 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4721 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4722 4723 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4724 itd = ehci_alloc_itd(sc); 4725 if (itd == NULL) { 4726 err = ENOMEM; 4727 goto fail; 4728 } 4729 4730 if (prev != NULL) { 4731 /* Maybe not as it's updated by the scheduling? */ 4732 prev->itd.itd_next = 4733 htole32(itd->physaddr | EHCI_LINK_ITD); 4734 4735 prev->xfer_next = itd; 4736 } else { 4737 start = itd; 4738 } 4739 4740 /* 4741 * Other special values 4742 */ 4743 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4744 itd->itd.itd_bufr[0] = htole32( 4745 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4746 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4747 4748 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4749 ? 1 : 0; 4750 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4751 itd->itd.itd_bufr[1] |= htole32( 4752 EHCI_ITD_SET_DIR(k) | 4753 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4754 4755 /* FIXME: handle invalid trans - should be done in openpipe */ 4756 itd->itd.itd_bufr[2] |= 4757 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4758 } /* End of frame */ 4759 4760 stop = itd; 4761 stop->xfer_next = NULL; 4762 4763 exfer->ex_itdstart = start; 4764 exfer->ex_itdend = stop; 4765 4766 return 0; 4767 fail: 4768 mutex_enter(&sc->sc_lock); 4769 ehci_soft_itd_t *next; 4770 for (itd = start; itd; itd = next) { 4771 next = itd->xfer_next; 4772 ehci_free_itd_locked(sc, itd); 4773 } 4774 mutex_exit(&sc->sc_lock); 4775 4776 return err; 4777 4778 } 4779 4780 Static void 4781 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4782 { 4783 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4784 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4785 4786 KASSERT(ex->ex_type == EX_ISOC); 4787 4788 ehci_free_itd_chain(sc, ex->ex_itdstart); 4789 } 4790 4791 Static usbd_status 4792 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4793 { 4794 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4795 usbd_status err; 4796 4797 mutex_enter(&sc->sc_lock); 4798 err = usb_insert_transfer(xfer); 4799 mutex_exit(&sc->sc_lock); 4800 if (err && err != USBD_IN_PROGRESS) 4801 return err; 4802 4803 return ehci_device_isoc_start(xfer); 4804 } 4805 4806 Static usbd_status 4807 ehci_device_isoc_start(struct usbd_xfer *xfer) 4808 { 4809 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4810 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4811 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4812 ehci_soft_itd_t *itd, *prev; 4813 usb_dma_t *dma_buf; 4814 int i, j; 4815 int frames, uframes, ufrperframe; 4816 int trans_count, offs, total_length; 4817 int frindex; 4818 4819 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4820 4821 prev = NULL; 4822 itd = NULL; 4823 trans_count = 0; 4824 total_length = 0; 4825 4826 /* 4827 * To allow continuous transfers, above we start all transfers 4828 * immediately. However, we're still going to get usbd_start_next call 4829 * this when another xfer completes. So, check if this is already 4830 * in progress or not 4831 */ 4832 4833 if (exfer->ex_isrunning) { 4834 return USBD_IN_PROGRESS; 4835 } 4836 4837 USBHIST_LOG(ehcidebug, "xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4838 4839 if (sc->sc_dying) 4840 return USBD_IOERROR; 4841 4842 /* 4843 * To avoid complication, don't allow a request right now that'll span 4844 * the entire frame table. To within 4 frames, to allow some leeway 4845 * on either side of where the hc currently is. 4846 */ 4847 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4848 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4849 USBHIST_LOG(ehcidebug, 4850 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4851 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4852 return USBD_INVAL; 4853 } 4854 4855 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4856 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4857 KASSERT(exfer->ex_isdone); 4858 #ifdef DIAGNOSTIC 4859 exfer->ex_isdone = false; 4860 #endif 4861 4862 /* 4863 * Step 1: Re-Initialize itds 4864 */ 4865 4866 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4867 if (i > 16 || i == 0) { 4868 /* Spec page 271 says intervals > 16 are invalid */ 4869 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4870 return USBD_INVAL; 4871 } 4872 4873 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4874 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4875 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4876 4877 if (frames == 0) { 4878 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4879 return USBD_INVAL; 4880 } 4881 4882 dma_buf = &xfer->ux_dmabuf; 4883 offs = 0; 4884 4885 itd = exfer->ex_itdstart; 4886 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4887 int froffs = offs; 4888 4889 if (prev != NULL) { 4890 prev->itd.itd_next = 4891 htole32(itd->physaddr | EHCI_LINK_ITD); 4892 usb_syncmem(&prev->dma, 4893 prev->offs + offsetof(ehci_itd_t, itd_next), 4894 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4895 prev->xfer_next = itd; 4896 } 4897 4898 /* 4899 * Step 1.5, initialize uframes 4900 */ 4901 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4902 /* Calculate which page in the list this starts in */ 4903 int addr = DMAADDR(dma_buf, froffs); 4904 addr = EHCI_PAGE_OFFSET(addr); 4905 addr += (offs - froffs); 4906 addr = EHCI_PAGE(addr); 4907 addr /= EHCI_PAGE_SIZE; 4908 4909 /* 4910 * This gets the initial offset into the first page, 4911 * looks how far further along the current uframe 4912 * offset is. Works out how many pages that is. 4913 */ 4914 4915 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4916 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4917 EHCI_ITD_SET_PG(addr) | 4918 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4919 4920 total_length += xfer->ux_frlengths[trans_count]; 4921 offs += xfer->ux_frlengths[trans_count]; 4922 trans_count++; 4923 4924 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4925 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4926 break; 4927 } 4928 } 4929 4930 /* 4931 * Step 1.75, set buffer pointers. To simplify matters, all 4932 * pointers are filled out for the next 7 hardware pages in 4933 * the dma block, so no need to worry what pages to cover 4934 * and what to not. 4935 */ 4936 4937 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4938 /* 4939 * Don't try to lookup a page that's past the end 4940 * of buffer 4941 */ 4942 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4943 if (page_offs >= dma_buf->udma_block->size) 4944 break; 4945 4946 uint64_t page = DMAADDR(dma_buf, page_offs); 4947 page = EHCI_PAGE(page); 4948 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4949 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4950 } 4951 /* 4952 * Other special values 4953 */ 4954 4955 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4956 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4957 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4958 4959 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4960 ? 1 : 0; 4961 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4962 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4963 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4964 4965 /* FIXME: handle invalid trans */ 4966 itd->itd.itd_bufr[2] |= 4967 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4968 4969 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4970 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4971 4972 prev = itd; 4973 } /* End of frame */ 4974 4975 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4976 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4977 4978 /* 4979 * Part 2: Transfer descriptors have now been set up, now they must 4980 * be scheduled into the period frame list. Erk. Not wanting to 4981 * complicate matters, transfer is denied if the transfer spans 4982 * more than the period frame list. 4983 */ 4984 4985 mutex_enter(&sc->sc_lock); 4986 4987 /* Start inserting frames */ 4988 if (epipe->isoc.cur_xfers > 0) { 4989 frindex = epipe->isoc.next_frame; 4990 } else { 4991 frindex = EOREAD4(sc, EHCI_FRINDEX); 4992 frindex = frindex >> 3; /* Erase microframe index */ 4993 frindex += 2; 4994 } 4995 4996 if (frindex >= sc->sc_flsize) 4997 frindex &= (sc->sc_flsize - 1); 4998 4999 /* What's the frame interval? */ 5000 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 5001 if (i / USB_UFRAMES_PER_FRAME == 0) 5002 i = 1; 5003 else 5004 i /= USB_UFRAMES_PER_FRAME; 5005 5006 itd = exfer->ex_itdstart; 5007 for (j = 0; j < frames; j++) { 5008 KASSERTMSG(itd != NULL, "frame %d\n", j); 5009 5010 usb_syncmem(&sc->sc_fldma, 5011 sizeof(ehci_link_t) * frindex, 5012 sizeof(ehci_link_t), 5013 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5014 5015 itd->itd.itd_next = sc->sc_flist[frindex]; 5016 if (itd->itd.itd_next == 0) 5017 /* 5018 * FIXME: frindex table gets initialized to NULL 5019 * or EHCI_NULL? 5020 */ 5021 itd->itd.itd_next = EHCI_NULL; 5022 5023 usb_syncmem(&itd->dma, 5024 itd->offs + offsetof(ehci_itd_t, itd_next), 5025 sizeof(itd->itd.itd_next), 5026 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5027 5028 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 5029 5030 usb_syncmem(&sc->sc_fldma, 5031 sizeof(ehci_link_t) * frindex, 5032 sizeof(ehci_link_t), 5033 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5034 5035 itd->frame_list.next = sc->sc_softitds[frindex]; 5036 sc->sc_softitds[frindex] = itd; 5037 if (itd->frame_list.next != NULL) 5038 itd->frame_list.next->frame_list.prev = itd; 5039 itd->slot = frindex; 5040 itd->frame_list.prev = NULL; 5041 5042 frindex += i; 5043 if (frindex >= sc->sc_flsize) 5044 frindex -= sc->sc_flsize; 5045 5046 itd = itd->xfer_next; 5047 } 5048 5049 epipe->isoc.cur_xfers++; 5050 epipe->isoc.next_frame = frindex; 5051 5052 exfer->ex_isrunning = true; 5053 5054 ehci_add_intr_list(sc, exfer); 5055 xfer->ux_status = USBD_IN_PROGRESS; 5056 5057 mutex_exit(&sc->sc_lock); 5058 5059 if (sc->sc_bus.ub_usepolling) { 5060 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 5061 ehci_waitintr(sc, xfer); 5062 } 5063 5064 return USBD_IN_PROGRESS; 5065 } 5066 5067 Static void 5068 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5069 { 5070 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5071 5072 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 5073 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5074 } 5075 5076 Static void 5077 ehci_device_isoc_close(struct usbd_pipe *pipe) 5078 { 5079 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5080 5081 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 5082 } 5083 5084 Static void 5085 ehci_device_isoc_done(struct usbd_xfer *xfer) 5086 { 5087 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5088 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5089 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5090 5091 KASSERT(mutex_owned(&sc->sc_lock)); 5092 5093 epipe->isoc.cur_xfers--; 5094 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 5095 ehci_del_intr_list(sc, exfer); 5096 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5097 exfer->ex_isrunning = false; 5098 } 5099 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5100 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5101 } 5102
Indexes created Wed Oct 01 19:09:53 GMT 2025