ehci.c revision 1.234.2.8
1 /* $NetBSD: ehci.c,v 1.234.2.8 2014/12/03 12:52:07 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.8 2014/12/03 12:52:07 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 #include <dev/usb/usbroothub_subr.h> 85 86 #include <dev/usb/ehcireg.h> 87 #include <dev/usb/ehcivar.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 177 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 178 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 179 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 180 Static void ehci_root_ctrl_close(usbd_pipe_handle); 181 Static void ehci_root_ctrl_done(usbd_xfer_handle); 182 183 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 184 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 185 Static void ehci_root_intr_abort(usbd_xfer_handle); 186 Static void ehci_root_intr_close(usbd_pipe_handle); 187 Static void ehci_root_intr_done(usbd_xfer_handle); 188 189 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 190 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 191 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 192 Static void ehci_device_ctrl_close(usbd_pipe_handle); 193 Static void ehci_device_ctrl_done(usbd_xfer_handle); 194 195 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 196 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 197 Static void ehci_device_bulk_abort(usbd_xfer_handle); 198 Static void ehci_device_bulk_close(usbd_pipe_handle); 199 Static void ehci_device_bulk_done(usbd_xfer_handle); 200 201 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 202 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 203 Static void ehci_device_intr_abort(usbd_xfer_handle); 204 Static void ehci_device_intr_close(usbd_pipe_handle); 205 Static void ehci_device_intr_done(usbd_xfer_handle); 206 207 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 208 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 209 Static void ehci_device_isoc_abort(usbd_xfer_handle); 210 Static void ehci_device_isoc_close(usbd_pipe_handle); 211 Static void ehci_device_isoc_done(usbd_xfer_handle); 212 213 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 214 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 215 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 216 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 217 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 218 219 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 220 Static void ehci_noop(usbd_pipe_handle pipe); 221 222 Static void ehci_disown(ehci_softc_t *, int, int); 223 224 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 225 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 226 227 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 228 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 229 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 230 ehci_softc_t *, int, int, usbd_xfer_handle, 231 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 232 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 233 ehci_soft_qtd_t *); 234 235 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 236 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *sc); 237 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 238 Static void ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *); 239 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 240 struct ehci_xfer *exfer); 241 Static void ehci_rem_free_sitd_chain(ehci_softc_t *sc, 242 struct ehci_xfer *exfer); 243 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 244 usbd_status status); 245 246 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 247 248 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 249 int ival); 250 251 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 252 ehci_soft_qh_t *); 253 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 254 ehci_soft_qh_t *); 255 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 256 Static void ehci_sync_hc(ehci_softc_t *); 257 258 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 259 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 260 261 #ifdef EHCI_DEBUG 262 Static ehci_softc_t *theehci; 263 void ehci_dump(void); 264 #endif 265 266 #ifdef EHCI_DEBUG 267 Static void ehci_dump_regs(ehci_softc_t *); 268 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 269 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 270 Static void ehci_dump_qtd(ehci_qtd_t *); 271 Static void ehci_dump_sqh(ehci_soft_qh_t *); 272 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 273 Static void ehci_dump_itd(struct ehci_soft_itd *); 274 Static void ehci_dump_exfer(struct ehci_xfer *); 275 #endif 276 277 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 278 279 #define EHCI_INTR_ENDPT 1 280 281 #define ehci_add_intr_list(sc, ex) \ 282 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 283 #define ehci_del_intr_list(sc, ex) \ 284 do { \ 285 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 286 (ex)->inext.tqe_prev = NULL; \ 287 } while (0) 288 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 289 290 Static const struct usbd_bus_methods ehci_bus_methods = { 291 .ubm_open = ehci_open, 292 .ubm_softint = ehci_softintr, 293 .ubm_dopoll = ehci_poll, 294 .ubm_allocx = ehci_allocx, 295 .ubm_freex = ehci_freex, 296 .ubm_getlock = ehci_get_lock, 297 .ubm_newdev = NULL, 298 }; 299 300 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 301 .upm_transfer = ehci_root_ctrl_transfer, 302 .upm_start = ehci_root_ctrl_start, 303 .upm_abort = ehci_root_ctrl_abort, 304 .upm_close = ehci_root_ctrl_close, 305 .upm_cleartoggle = ehci_noop, 306 .upm_done = ehci_root_ctrl_done, 307 }; 308 309 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 310 .upm_transfer = ehci_root_intr_transfer, 311 .upm_start = ehci_root_intr_start, 312 .upm_abort = ehci_root_intr_abort, 313 .upm_close = ehci_root_intr_close, 314 .upm_cleartoggle = ehci_noop, 315 .upm_done = ehci_root_intr_done, 316 }; 317 318 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 319 .upm_transfer = ehci_device_ctrl_transfer, 320 .upm_start = ehci_device_ctrl_start, 321 .upm_abort = ehci_device_ctrl_abort, 322 .upm_close = ehci_device_ctrl_close, 323 .upm_cleartoggle = ehci_noop, 324 .upm_done = ehci_device_ctrl_done, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 328 .upm_transfer = ehci_device_intr_transfer, 329 .upm_start = ehci_device_intr_start, 330 .upm_abort = ehci_device_intr_abort, 331 .upm_close = ehci_device_intr_close, 332 .upm_cleartoggle = ehci_device_clear_toggle, 333 .upm_done = ehci_device_intr_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 337 .upm_transfer = ehci_device_bulk_transfer, 338 .upm_start = ehci_device_bulk_start, 339 .upm_abort = ehci_device_bulk_abort, 340 .upm_close = ehci_device_bulk_close, 341 .upm_cleartoggle = ehci_device_clear_toggle, 342 .upm_done = ehci_device_bulk_done, 343 }; 344 345 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 346 .upm_transfer = ehci_device_isoc_transfer, 347 .upm_start = ehci_device_isoc_start, 348 .upm_abort = ehci_device_isoc_abort, 349 .upm_close = ehci_device_isoc_close, 350 .upm_cleartoggle = ehci_noop, 351 .upm_done = ehci_device_isoc_done, 352 }; 353 354 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 355 .upm_transfer = ehci_device_fs_isoc_transfer, 356 .upm_start = ehci_device_fs_isoc_start, 357 .upm_abort = ehci_device_fs_isoc_abort, 358 .upm_close = ehci_device_fs_isoc_close, 359 .upm_cleartoggle = ehci_noop, 360 .upm_done = ehci_device_fs_isoc_done, 361 }; 362 363 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 364 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 365 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 366 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 367 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 368 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 369 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 370 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 371 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 372 }; 373 374 usbd_status 375 ehci_init(ehci_softc_t *sc) 376 { 377 uint32_t vers, sparams, cparams, hcr; 378 u_int i; 379 usbd_status err; 380 ehci_soft_qh_t *sqh; 381 u_int ncomp; 382 383 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 384 #ifdef EHCI_DEBUG 385 theehci = sc; 386 #endif 387 388 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 389 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 390 cv_init(&sc->sc_softwake_cv, "ehciab"); 391 cv_init(&sc->sc_doorbell, "ehcidi"); 392 393 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 394 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 395 396 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 397 ehci_doorbell, sc); 398 KASSERT(sc->sc_doorbell_si != NULL); 399 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 400 ehci_pcd, sc); 401 KASSERT(sc->sc_pcd_si != NULL); 402 403 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 404 405 vers = EREAD2(sc, EHCI_HCIVERSION); 406 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 407 vers >> 8, vers & 0xff); 408 409 sparams = EREAD4(sc, EHCI_HCSPARAMS); 410 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 411 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 412 ncomp = EHCI_HCS_N_CC(sparams); 413 if (ncomp != sc->sc_ncomp) { 414 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 415 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 416 #if NOHCI == 0 || NUHCI == 0 417 aprint_error("%s: ohci or uhci probably not configured\n", 418 device_xname(sc->sc_dev)); 419 #endif 420 if (ncomp < sc->sc_ncomp) 421 sc->sc_ncomp = ncomp; 422 } 423 if (sc->sc_ncomp > 0) { 424 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 425 aprint_normal("%s: companion controller%s, %d port%s each:", 426 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 427 EHCI_HCS_N_PCC(sparams), 428 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 429 for (i = 0; i < sc->sc_ncomp; i++) 430 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 431 aprint_normal("\n"); 432 } 433 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 434 cparams = EREAD4(sc, EHCI_HCCPARAMS); 435 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 436 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 437 438 if (EHCI_HCC_64BIT(cparams)) { 439 /* MUST clear segment register if 64 bit capable. */ 440 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 441 } 442 443 sc->sc_bus.ub_revision = USBREV_2_0; 444 sc->sc_bus.ub_usedma = true; 445 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 446 447 /* Reset the controller */ 448 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 449 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 450 usb_delay_ms(&sc->sc_bus, 1); 451 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 452 for (i = 0; i < 100; i++) { 453 usb_delay_ms(&sc->sc_bus, 1); 454 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 455 if (!hcr) 456 break; 457 } 458 if (hcr) { 459 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 460 return (USBD_IOERROR); 461 } 462 if (sc->sc_vendor_init) 463 sc->sc_vendor_init(sc); 464 465 /* 466 * If we are doing embedded transaction translation function, force 467 * the controller to host mode. 468 */ 469 if (sc->sc_flags & EHCIF_ETTF) { 470 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 471 usbmode &= ~EHCI_USBMODE_CM; 472 usbmode |= EHCI_USBMODE_CM_HOST; 473 EWRITE4(sc, EHCI_USBMODE, usbmode); 474 } 475 476 /* XXX need proper intr scheduling */ 477 sc->sc_rand = 96; 478 479 /* frame list size at default, read back what we got and use that */ 480 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 481 case 0: sc->sc_flsize = 1024; break; 482 case 1: sc->sc_flsize = 512; break; 483 case 2: sc->sc_flsize = 256; break; 484 case 3: return (USBD_IOERROR); 485 } 486 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 487 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 488 if (err) 489 return (err); 490 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 491 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 492 493 for (i = 0; i < sc->sc_flsize; i++) { 494 sc->sc_flist[i] = EHCI_NULL; 495 } 496 497 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 498 499 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 500 KM_SLEEP); 501 if (sc->sc_softitds == NULL) 502 return ENOMEM; 503 LIST_INIT(&sc->sc_freeitds); 504 LIST_INIT(&sc->sc_freesitds); 505 TAILQ_INIT(&sc->sc_intrhead); 506 507 /* Set up the bus struct. */ 508 sc->sc_bus.ub_methods = &ehci_bus_methods; 509 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 510 511 sc->sc_eintrs = EHCI_NORMAL_INTRS; 512 513 /* 514 * Allocate the interrupt dummy QHs. These are arranged to give poll 515 * intervals that are powers of 2 times 1ms. 516 */ 517 for (i = 0; i < EHCI_INTRQHS; i++) { 518 sqh = ehci_alloc_sqh(sc); 519 if (sqh == NULL) { 520 err = USBD_NOMEM; 521 goto bad1; 522 } 523 sc->sc_islots[i].sqh = sqh; 524 } 525 for (i = 0; i < EHCI_INTRQHS; i++) { 526 sqh = sc->sc_islots[i].sqh; 527 if (i == 0) { 528 /* The last (1ms) QH terminates. */ 529 sqh->qh.qh_link = EHCI_NULL; 530 sqh->next = NULL; 531 } else { 532 /* Otherwise the next QH has half the poll interval */ 533 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 534 sqh->qh.qh_link = htole32(sqh->next->physaddr | 535 EHCI_LINK_QH); 536 } 537 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 538 sqh->qh.qh_curqtd = EHCI_NULL; 539 sqh->next = NULL; 540 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 541 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 542 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 543 sqh->sqtd = NULL; 544 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 545 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 546 } 547 /* Point the frame list at the last level (128ms). */ 548 for (i = 0; i < sc->sc_flsize; i++) { 549 int j; 550 551 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 552 revbits[i & (EHCI_MAX_POLLRATE-1)]; 553 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 554 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 555 i)].sqh->physaddr); 556 } 557 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 558 BUS_DMASYNC_PREWRITE); 559 560 /* Allocate dummy QH that starts the async list. */ 561 sqh = ehci_alloc_sqh(sc); 562 if (sqh == NULL) { 563 err = USBD_NOMEM; 564 goto bad1; 565 } 566 /* Fill the QH */ 567 sqh->qh.qh_endp = 568 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 569 sqh->qh.qh_link = 570 htole32(sqh->physaddr | EHCI_LINK_QH); 571 sqh->qh.qh_curqtd = EHCI_NULL; 572 sqh->next = NULL; 573 /* Fill the overlay qTD */ 574 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 575 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 576 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 577 sqh->sqtd = NULL; 578 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 579 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 580 #ifdef EHCI_DEBUG 581 ehci_dump_sqh(sqh); 582 #endif 583 584 /* Point to async list */ 585 sc->sc_async_head = sqh; 586 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 587 588 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 589 590 /* Turn on controller */ 591 EOWRITE4(sc, EHCI_USBCMD, 592 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 593 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 594 EHCI_CMD_ASE | 595 EHCI_CMD_PSE | 596 EHCI_CMD_RS); 597 598 /* Take over port ownership */ 599 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 600 601 for (i = 0; i < 100; i++) { 602 usb_delay_ms(&sc->sc_bus, 1); 603 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 604 if (!hcr) 605 break; 606 } 607 if (hcr) { 608 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 609 return (USBD_IOERROR); 610 } 611 612 /* Enable interrupts */ 613 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 614 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 615 616 return (USBD_NORMAL_COMPLETION); 617 618 #if 0 619 bad2: 620 ehci_free_sqh(sc, sc->sc_async_head); 621 #endif 622 bad1: 623 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 624 return (err); 625 } 626 627 int 628 ehci_intr(void *v) 629 { 630 ehci_softc_t *sc = v; 631 int ret = 0; 632 633 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 634 635 if (sc == NULL) 636 return 0; 637 638 mutex_spin_enter(&sc->sc_intr_lock); 639 640 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 641 goto done; 642 643 /* If we get an interrupt while polling, then just ignore it. */ 644 if (sc->sc_bus.ub_usepolling) { 645 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 646 647 if (intrs) 648 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 649 #ifdef DIAGNOSTIC 650 USBHIST_LOGN(ehcidebug, 16, 651 "ignored interrupt while polling", 0, 0, 0, 0); 652 #endif 653 goto done; 654 } 655 656 ret = ehci_intr1(sc); 657 658 done: 659 mutex_spin_exit(&sc->sc_intr_lock); 660 return ret; 661 } 662 663 Static int 664 ehci_intr1(ehci_softc_t *sc) 665 { 666 uint32_t intrs, eintrs; 667 668 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 669 670 /* In case the interrupt occurs before initialization has completed. */ 671 if (sc == NULL) { 672 #ifdef DIAGNOSTIC 673 printf("ehci_intr1: sc == NULL\n"); 674 #endif 675 return (0); 676 } 677 678 KASSERT(mutex_owned(&sc->sc_intr_lock)); 679 680 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 681 if (!intrs) 682 return (0); 683 684 eintrs = intrs & sc->sc_eintrs; 685 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 686 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 687 if (!eintrs) 688 return (0); 689 690 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 691 if (eintrs & EHCI_STS_IAA) { 692 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 693 kpreempt_disable(); 694 KASSERT(sc->sc_doorbell_si != NULL); 695 softint_schedule(sc->sc_doorbell_si); 696 kpreempt_enable(); 697 eintrs &= ~EHCI_STS_IAA; 698 } 699 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 700 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 701 eintrs & EHCI_STS_INT ? 1 : 0, 702 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 703 usb_schedsoftintr(&sc->sc_bus); 704 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 705 } 706 if (eintrs & EHCI_STS_HSE) { 707 printf("%s: unrecoverable error, controller halted\n", 708 device_xname(sc->sc_dev)); 709 /* XXX what else */ 710 } 711 if (eintrs & EHCI_STS_PCD) { 712 kpreempt_disable(); 713 KASSERT(sc->sc_pcd_si != NULL); 714 softint_schedule(sc->sc_pcd_si); 715 kpreempt_enable(); 716 eintrs &= ~EHCI_STS_PCD; 717 } 718 719 if (eintrs != 0) { 720 /* Block unprocessed interrupts. */ 721 sc->sc_eintrs &= ~eintrs; 722 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 723 printf("%s: blocking intrs 0x%x\n", 724 device_xname(sc->sc_dev), eintrs); 725 } 726 727 return (1); 728 } 729 730 Static void 731 ehci_doorbell(void *addr) 732 { 733 ehci_softc_t *sc = addr; 734 735 mutex_enter(&sc->sc_lock); 736 cv_broadcast(&sc->sc_doorbell); 737 mutex_exit(&sc->sc_lock); 738 } 739 740 Static void 741 ehci_pcd(void *addr) 742 { 743 ehci_softc_t *sc = addr; 744 usbd_xfer_handle xfer; 745 u_char *p; 746 int i, m; 747 748 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 749 750 mutex_enter(&sc->sc_lock); 751 xfer = sc->sc_intrxfer; 752 753 if (xfer == NULL) { 754 /* Just ignore the change. */ 755 goto done; 756 } 757 758 p = xfer->ux_buf; 759 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 760 memset(p, 0, xfer->ux_length); 761 for (i = 1; i <= m; i++) { 762 /* Pick out CHANGE bits from the status reg. */ 763 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 764 p[i/8] |= 1 << (i%8); 765 if (i % 8 == 7) 766 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 767 p[i/8], 0, 0); 768 } 769 xfer->ux_actlen = xfer->ux_length; 770 xfer->ux_status = USBD_NORMAL_COMPLETION; 771 772 usb_transfer_complete(xfer); 773 774 done: 775 mutex_exit(&sc->sc_lock); 776 } 777 778 Static void 779 ehci_softintr(void *v) 780 { 781 struct usbd_bus *bus = v; 782 ehci_softc_t *sc = bus->ub_hcpriv; 783 struct ehci_xfer *ex, *nextex; 784 785 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 786 787 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 788 789 /* 790 * The only explanation I can think of for why EHCI is as brain dead 791 * as UHCI interrupt-wise is that Intel was involved in both. 792 * An interrupt just tells us that something is done, we have no 793 * clue what, so we need to scan through all active transfers. :-( 794 */ 795 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 796 nextex = TAILQ_NEXT(ex, inext); 797 ehci_check_intr(sc, ex); 798 } 799 800 /* Schedule a callout to catch any dropped transactions. */ 801 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 802 !TAILQ_EMPTY(&sc->sc_intrhead)) 803 callout_reset(&sc->sc_tmo_intrlist, 804 hz, ehci_intrlist_timeout, sc); 805 806 if (sc->sc_softwake) { 807 sc->sc_softwake = 0; 808 cv_broadcast(&sc->sc_softwake_cv); 809 } 810 } 811 812 /* Check for an interrupt. */ 813 Static void 814 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 815 { 816 usbd_device_handle dev = ex->xfer.ux_pipe->up_dev; 817 int attr; 818 819 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 820 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 821 822 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 823 824 attr = ex->xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 825 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 826 if (dev->ud_speed == USB_SPEED_HIGH) 827 ehci_check_itd_intr(sc, ex); 828 else 829 ehci_check_sitd_intr(sc, ex); 830 } else 831 ehci_check_qh_intr(sc, ex); 832 833 return; 834 } 835 836 Static void 837 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 838 { 839 ehci_soft_qtd_t *sqtd, *lsqtd; 840 uint32_t status; 841 842 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 843 844 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 845 846 if (ex->sqtdstart == NULL) { 847 printf("ehci_check_qh_intr: not valid sqtd\n"); 848 return; 849 } 850 851 lsqtd = ex->sqtdend; 852 #ifdef DIAGNOSTIC 853 if (lsqtd == NULL) { 854 printf("ehci_check_qh_intr: lsqtd==0\n"); 855 return; 856 } 857 #endif 858 /* 859 * If the last TD is still active we need to check whether there 860 * is an error somewhere in the middle, or whether there was a 861 * short packet (SPD and not ACTIVE). 862 */ 863 usb_syncmem(&lsqtd->dma, 864 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 865 sizeof(lsqtd->qtd.qtd_status), 866 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 867 status = le32toh(lsqtd->qtd.qtd_status); 868 usb_syncmem(&lsqtd->dma, 869 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 870 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 871 if (status & EHCI_QTD_ACTIVE) { 872 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 873 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 874 usb_syncmem(&sqtd->dma, 875 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 876 sizeof(sqtd->qtd.qtd_status), 877 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 878 status = le32toh(sqtd->qtd.qtd_status); 879 usb_syncmem(&sqtd->dma, 880 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 881 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 882 /* If there's an active QTD the xfer isn't done. */ 883 if (status & EHCI_QTD_ACTIVE) 884 break; 885 /* Any kind of error makes the xfer done. */ 886 if (status & EHCI_QTD_HALTED) 887 goto done; 888 /* Handle short packets */ 889 if (EHCI_QTD_GET_BYTES(status) != 0) { 890 usbd_pipe_handle pipe = ex->xfer.ux_pipe; 891 usb_endpoint_descriptor_t *ed = 892 pipe->up_endpoint->ue_edesc; 893 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 894 895 /* 896 * If we get here for a control transfer then 897 * we need to let the hardware complete the 898 * status phase. That is, we're not done 899 * quite yet. 900 * 901 * Otherwise, we're done. 902 */ 903 if (xt == UE_CONTROL) { 904 break; 905 } 906 goto done; 907 } 908 } 909 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 910 ex, ex->sqtdstart, 0, 0); 911 return; 912 } 913 done: 914 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 915 callout_stop(&ex->xfer.ux_callout); 916 ehci_idone(ex); 917 } 918 919 Static void 920 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 921 { 922 ehci_soft_itd_t *itd; 923 int i; 924 925 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 926 927 KASSERT(mutex_owned(&sc->sc_lock)); 928 929 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.ux_pipe->up_queue)) 930 return; 931 932 if (ex->itdstart == NULL) { 933 printf("ehci_check_itd_intr: not valid itd\n"); 934 return; 935 } 936 937 itd = ex->itdend; 938 #ifdef DIAGNOSTIC 939 if (itd == NULL) { 940 printf("ehci_check_itd_intr: itdend == 0\n"); 941 return; 942 } 943 #endif 944 945 /* 946 * check no active transfers in last itd, meaning we're finished 947 */ 948 949 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 950 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 951 BUS_DMASYNC_POSTREAD); 952 953 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 954 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 955 break; 956 } 957 958 if (i == EHCI_ITD_NUFRAMES) { 959 goto done; /* All 8 descriptors inactive, it's done */ 960 } 961 962 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 963 ex->itdstart, 0, 0); 964 return; 965 done: 966 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 967 callout_stop(&ex->xfer.ux_callout); 968 ehci_idone(ex); 969 } 970 971 void 972 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 973 { 974 ehci_soft_sitd_t *sitd; 975 976 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 977 978 KASSERT(mutex_owned(&sc->sc_lock)); 979 980 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.ux_pipe->up_queue)) 981 return; 982 983 if (ex->sitdstart == NULL) { 984 printf("ehci_check_sitd_intr: not valid sitd\n"); 985 return; 986 } 987 988 sitd = ex->sitdend; 989 #ifdef DIAGNOSTIC 990 if (sitd == NULL) { 991 printf("ehci_check_sitd_intr: sitdend == 0\n"); 992 return; 993 } 994 #endif 995 996 /* 997 * check no active transfers in last sitd, meaning we're finished 998 */ 999 1000 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1001 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1002 BUS_DMASYNC_POSTREAD); 1003 1004 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 1005 return; 1006 1007 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1008 callout_stop(&(ex->xfer.ux_callout)); 1009 ehci_idone(ex); 1010 } 1011 1012 1013 Static void 1014 ehci_idone(struct ehci_xfer *ex) 1015 { 1016 usbd_xfer_handle xfer = &ex->xfer; 1017 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1018 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1019 ehci_soft_qtd_t *sqtd, *lsqtd; 1020 uint32_t status = 0, nstatus = 0; 1021 int actlen; 1022 1023 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1024 1025 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1026 1027 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1028 1029 #ifdef DIAGNOSTIC 1030 if (ex->isdone) { 1031 printf("ehci_idone: ex=%p is done!\n", ex); 1032 #ifdef EHCI_DEBUG 1033 ehci_dump_exfer(ex); 1034 #endif 1035 return; 1036 } 1037 ex->isdone = 1; 1038 #endif 1039 1040 if (xfer->ux_status == USBD_CANCELLED || 1041 xfer->ux_status == USBD_TIMEOUT) { 1042 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1043 return; 1044 } 1045 1046 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1047 #ifdef EHCI_DEBUG 1048 ehci_dump_sqtds(ex->sqtdstart); 1049 #endif 1050 1051 /* The transfer is done, compute actual length and status. */ 1052 1053 u_int xfertype, speed; 1054 1055 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1056 speed = xfer->ux_pipe->up_dev->ud_speed; 1057 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1058 /* HS isoc transfer */ 1059 1060 struct ehci_soft_itd *itd; 1061 int i, nframes, len, uframes; 1062 1063 nframes = 0; 1064 actlen = 0; 1065 1066 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1067 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1068 1069 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1070 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1071 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1072 BUS_DMASYNC_POSTREAD); 1073 1074 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1075 /* XXX - driver didn't fill in the frame full 1076 * of uframes. This leads to scheduling 1077 * inefficiencies, but working around 1078 * this doubles complexity of tracking 1079 * an xfer. 1080 */ 1081 if (nframes >= xfer->ux_nframes) 1082 break; 1083 1084 status = le32toh(itd->itd.itd_ctl[i]); 1085 len = EHCI_ITD_GET_LEN(status); 1086 if (EHCI_ITD_GET_STATUS(status) != 0) 1087 len = 0; /*No valid data on error*/ 1088 1089 xfer->ux_frlengths[nframes++] = len; 1090 actlen += len; 1091 } 1092 1093 if (nframes >= xfer->ux_nframes) 1094 break; 1095 } 1096 1097 xfer->ux_actlen = actlen; 1098 xfer->ux_status = USBD_NORMAL_COMPLETION; 1099 goto end; 1100 } 1101 1102 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1103 /* FS isoc transfer */ 1104 struct ehci_soft_sitd *sitd; 1105 int nframes, len; 1106 1107 nframes = 0; 1108 actlen = 0; 1109 1110 for (sitd = ex->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1111 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1112 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1113 BUS_DMASYNC_POSTREAD); 1114 1115 /* XXX - driver didn't fill in the frame full 1116 * of uframes. This leads to scheduling 1117 * inefficiencies, but working around 1118 * this doubles complexity of tracking 1119 * an xfer. 1120 */ 1121 if (nframes >= xfer->ux_nframes) 1122 break; 1123 1124 status = le32toh(sitd->sitd.sitd_trans); 1125 len = EHCI_SITD_GET_LEN(status); 1126 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1127 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1128 /* No valid data on error */ 1129 len = xfer->ux_frlengths[nframes]; 1130 } 1131 1132 /* 1133 * frlengths[i]: # of bytes to send 1134 * len: # of bytes host didn't send 1135 */ 1136 xfer->ux_frlengths[nframes] -= len; 1137 /* frlengths[i]: # of bytes host sent */ 1138 actlen += xfer->ux_frlengths[nframes++]; 1139 1140 if (nframes >= xfer->ux_nframes) 1141 break; 1142 } 1143 1144 xfer->ux_actlen = actlen; 1145 xfer->ux_status = USBD_NORMAL_COMPLETION; 1146 goto end; 1147 } 1148 1149 /* Continue processing xfers using queue heads */ 1150 1151 lsqtd = ex->sqtdend; 1152 actlen = 0; 1153 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 1154 sqtd = sqtd->nextqtd) { 1155 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1156 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1157 nstatus = le32toh(sqtd->qtd.qtd_status); 1158 if (nstatus & EHCI_QTD_ACTIVE) 1159 break; 1160 1161 status = nstatus; 1162 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1163 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1164 } 1165 1166 1167 /* 1168 * If there are left over TDs we need to update the toggle. 1169 * The default pipe doesn't need it since control transfers 1170 * start the toggle at 0 every time. 1171 * For a short transfer we need to update the toggle for the missing 1172 * packets within the qTD. 1173 */ 1174 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1175 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1176 USBHIST_LOG(ehcidebug, 1177 "toggle update status=0x%08x nstatus=0x%08x", 1178 status, nstatus, 0, 0); 1179 #if 0 1180 ehci_dump_sqh(epipe->sqh); 1181 ehci_dump_sqtds(ex->sqtdstart); 1182 #endif 1183 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1184 } 1185 1186 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1187 actlen, status, 0); 1188 xfer->ux_actlen = actlen; 1189 if (status & EHCI_QTD_HALTED) { 1190 #ifdef EHCI_DEBUG 1191 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1192 xfer->ux_pipe->up_dev->ud_addr, 1193 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1194 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1195 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1196 status, 0); 1197 USBHIST_LOG(ehcidebug, 1198 "active =%d halted=%d buferr=%d babble=%d", 1199 status & EHCI_QTD_ACTIVE ? 1 : 0, 1200 status & EHCI_QTD_HALTED ? 1 : 0, 1201 status & EHCI_QTD_BUFERR ? 1 : 0, 1202 status & EHCI_QTD_BABBLE ? 1 : 0); 1203 1204 USBHIST_LOG(ehcidebug, 1205 "xacterr=%d missed=%d split =%d ping =%d", 1206 status & EHCI_QTD_XACTERR ? 1 : 0, 1207 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1208 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1209 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1210 1211 ehci_dump_sqh(epipe->sqh); 1212 ehci_dump_sqtds(ex->sqtdstart); 1213 #endif 1214 /* low&full speed has an extra error flag */ 1215 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1216 EHCI_QH_SPEED_HIGH) 1217 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1218 else 1219 status &= EHCI_QTD_STATERRS; 1220 if (status == 0) /* no other errors means a stall */ { 1221 xfer->ux_status = USBD_STALLED; 1222 } else { 1223 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1224 } 1225 /* XXX need to reset TT on missed microframe */ 1226 if (status & EHCI_QTD_MISSEDMICRO) { 1227 printf("%s: missed microframe, TT reset not " 1228 "implemented, hub might be inoperational\n", 1229 device_xname(sc->sc_dev)); 1230 } 1231 } else { 1232 xfer->ux_status = USBD_NORMAL_COMPLETION; 1233 } 1234 1235 end: 1236 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1237 * during this call, before methods->done is called: dma sync required 1238 * beforehand? */ 1239 usb_transfer_complete(xfer); 1240 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1241 } 1242 1243 /* 1244 * Wait here until controller claims to have an interrupt. 1245 * Then call ehci_intr and return. Use timeout to avoid waiting 1246 * too long. 1247 */ 1248 Static void 1249 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1250 { 1251 int timo; 1252 uint32_t intrs; 1253 1254 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1255 1256 xfer->ux_status = USBD_IN_PROGRESS; 1257 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1258 usb_delay_ms(&sc->sc_bus, 1); 1259 if (sc->sc_dying) 1260 break; 1261 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1262 sc->sc_eintrs; 1263 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1264 #ifdef EHCI_DEBUG 1265 if (ehcidebug > 15) 1266 ehci_dump_regs(sc); 1267 #endif 1268 if (intrs) { 1269 mutex_spin_enter(&sc->sc_intr_lock); 1270 ehci_intr1(sc); 1271 mutex_spin_exit(&sc->sc_intr_lock); 1272 if (xfer->ux_status != USBD_IN_PROGRESS) 1273 return; 1274 } 1275 } 1276 1277 /* Timeout */ 1278 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1279 xfer->ux_status = USBD_TIMEOUT; 1280 mutex_enter(&sc->sc_lock); 1281 usb_transfer_complete(xfer); 1282 mutex_exit(&sc->sc_lock); 1283 /* XXX should free TD */ 1284 } 1285 1286 Static void 1287 ehci_poll(struct usbd_bus *bus) 1288 { 1289 ehci_softc_t *sc = bus->ub_hcpriv; 1290 1291 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1292 1293 #ifdef EHCI_DEBUG 1294 static int last; 1295 int new; 1296 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1297 if (new != last) { 1298 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1299 last = new; 1300 } 1301 #endif 1302 1303 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1304 mutex_spin_enter(&sc->sc_intr_lock); 1305 ehci_intr1(sc); 1306 mutex_spin_exit(&sc->sc_intr_lock); 1307 } 1308 } 1309 1310 void 1311 ehci_childdet(device_t self, device_t child) 1312 { 1313 struct ehci_softc *sc = device_private(self); 1314 1315 KASSERT(sc->sc_child == child); 1316 sc->sc_child = NULL; 1317 } 1318 1319 int 1320 ehci_detach(struct ehci_softc *sc, int flags) 1321 { 1322 int rv = 0; 1323 1324 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1325 1326 if (sc->sc_child != NULL) 1327 rv = config_detach(sc->sc_child, flags); 1328 1329 if (rv != 0) 1330 return (rv); 1331 1332 callout_halt(&sc->sc_tmo_intrlist, NULL); 1333 callout_destroy(&sc->sc_tmo_intrlist); 1334 1335 /* XXX free other data structures XXX */ 1336 if (sc->sc_softitds) 1337 kmem_free(sc->sc_softitds, 1338 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1339 cv_destroy(&sc->sc_doorbell); 1340 cv_destroy(&sc->sc_softwake_cv); 1341 1342 #if 0 1343 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1344 1345 softint_disestablish(sc->sc_doorbell_si); 1346 softint_disestablish(sc->sc_pcd_si); 1347 1348 mutex_destroy(&sc->sc_lock); 1349 mutex_destroy(&sc->sc_intr_lock); 1350 #endif 1351 1352 pool_cache_destroy(sc->sc_xferpool); 1353 1354 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1355 1356 return (rv); 1357 } 1358 1359 1360 int 1361 ehci_activate(device_t self, enum devact act) 1362 { 1363 struct ehci_softc *sc = device_private(self); 1364 1365 switch (act) { 1366 case DVACT_DEACTIVATE: 1367 sc->sc_dying = 1; 1368 return 0; 1369 default: 1370 return EOPNOTSUPP; 1371 } 1372 } 1373 1374 /* 1375 * Handle suspend/resume. 1376 * 1377 * We need to switch to polling mode here, because this routine is 1378 * called from an interrupt context. This is all right since we 1379 * are almost suspended anyway. 1380 * 1381 * Note that this power handler isn't to be registered directly; the 1382 * bus glue needs to call out to it. 1383 */ 1384 bool 1385 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1386 { 1387 ehci_softc_t *sc = device_private(dv); 1388 int i; 1389 uint32_t cmd, hcr; 1390 1391 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1392 1393 mutex_spin_enter(&sc->sc_intr_lock); 1394 sc->sc_bus.ub_usepolling++; 1395 mutex_spin_exit(&sc->sc_intr_lock); 1396 1397 for (i = 1; i <= sc->sc_noport; i++) { 1398 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1399 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1400 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1401 } 1402 1403 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1404 1405 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1406 EOWRITE4(sc, EHCI_USBCMD, cmd); 1407 1408 for (i = 0; i < 100; i++) { 1409 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1410 if (hcr == 0) 1411 break; 1412 1413 usb_delay_ms(&sc->sc_bus, 1); 1414 } 1415 if (hcr != 0) 1416 printf("%s: reset timeout\n", device_xname(dv)); 1417 1418 cmd &= ~EHCI_CMD_RS; 1419 EOWRITE4(sc, EHCI_USBCMD, cmd); 1420 1421 for (i = 0; i < 100; i++) { 1422 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1423 if (hcr == EHCI_STS_HCH) 1424 break; 1425 1426 usb_delay_ms(&sc->sc_bus, 1); 1427 } 1428 if (hcr != EHCI_STS_HCH) 1429 printf("%s: config timeout\n", device_xname(dv)); 1430 1431 mutex_spin_enter(&sc->sc_intr_lock); 1432 sc->sc_bus.ub_usepolling--; 1433 mutex_spin_exit(&sc->sc_intr_lock); 1434 1435 return true; 1436 } 1437 1438 bool 1439 ehci_resume(device_t dv, const pmf_qual_t *qual) 1440 { 1441 ehci_softc_t *sc = device_private(dv); 1442 int i; 1443 uint32_t cmd, hcr; 1444 1445 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1446 1447 /* restore things in case the bios sucks */ 1448 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1449 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1450 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1451 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1452 1453 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1454 1455 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1456 1457 hcr = 0; 1458 for (i = 1; i <= sc->sc_noport; i++) { 1459 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1460 if ((cmd & EHCI_PS_PO) == 0 && 1461 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1462 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1463 hcr = 1; 1464 } 1465 } 1466 1467 if (hcr) { 1468 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1469 1470 for (i = 1; i <= sc->sc_noport; i++) { 1471 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1472 if ((cmd & EHCI_PS_PO) == 0 && 1473 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1474 EOWRITE4(sc, EHCI_PORTSC(i), 1475 cmd & ~EHCI_PS_FPR); 1476 } 1477 } 1478 1479 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1480 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1481 1482 for (i = 0; i < 100; i++) { 1483 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1484 if (hcr != EHCI_STS_HCH) 1485 break; 1486 1487 usb_delay_ms(&sc->sc_bus, 1); 1488 } 1489 if (hcr == EHCI_STS_HCH) 1490 printf("%s: config timeout\n", device_xname(dv)); 1491 1492 return true; 1493 } 1494 1495 /* 1496 * Shut down the controller when the system is going down. 1497 */ 1498 bool 1499 ehci_shutdown(device_t self, int flags) 1500 { 1501 ehci_softc_t *sc = device_private(self); 1502 1503 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1504 1505 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1506 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1507 return true; 1508 } 1509 1510 Static usbd_xfer_handle 1511 ehci_allocx(struct usbd_bus *bus) 1512 { 1513 struct ehci_softc *sc = bus->ub_hcpriv; 1514 usbd_xfer_handle xfer; 1515 1516 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1517 if (xfer != NULL) { 1518 memset(xfer, 0, sizeof(struct ehci_xfer)); 1519 #ifdef DIAGNOSTIC 1520 EXFER(xfer)->isdone = 1; 1521 xfer->ux_state = XFER_BUSY; 1522 #endif 1523 } 1524 return (xfer); 1525 } 1526 1527 Static void 1528 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1529 { 1530 struct ehci_softc *sc = bus->ub_hcpriv; 1531 1532 #ifdef DIAGNOSTIC 1533 if (xfer->ux_state != XFER_BUSY) { 1534 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1535 xfer->ux_state); 1536 } 1537 xfer->ux_state = XFER_FREE; 1538 if (!EXFER(xfer)->isdone) { 1539 printf("ehci_freex: !isdone\n"); 1540 } 1541 #endif 1542 pool_cache_put(sc->sc_xferpool, xfer); 1543 } 1544 1545 Static void 1546 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1547 { 1548 struct ehci_softc *sc = bus->ub_hcpriv; 1549 1550 *lock = &sc->sc_lock; 1551 } 1552 1553 Static void 1554 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1555 { 1556 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1557 1558 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1559 1560 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1561 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1562 #ifdef EHCI_DEBUG 1563 if (ehcidebug) 1564 usbd_dump_pipe(pipe); 1565 #endif 1566 epipe->nexttoggle = 0; 1567 } 1568 1569 Static void 1570 ehci_noop(usbd_pipe_handle pipe) 1571 { 1572 } 1573 1574 #ifdef EHCI_DEBUG 1575 /* 1576 * Unused function - this is meant to be called from a kernel 1577 * debugger. 1578 */ 1579 void 1580 ehci_dump(void) 1581 { 1582 ehci_softc_t *sc = theehci; 1583 int i; 1584 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1585 EOREAD4(sc, EHCI_USBCMD), 1586 EOREAD4(sc, EHCI_USBSTS), 1587 EOREAD4(sc, EHCI_USBINTR)); 1588 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1589 EOREAD4(sc, EHCI_FRINDEX), 1590 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1591 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1592 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1593 for (i = 1; i <= sc->sc_noport; i++) 1594 printf("port %d status=0x%08x\n", i, 1595 EOREAD4(sc, EHCI_PORTSC(i))); 1596 } 1597 1598 Static void 1599 ehci_dump_regs(ehci_softc_t *sc) 1600 { 1601 int i; 1602 1603 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1604 1605 USBHIST_LOG(ehcidebug, 1606 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1607 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1608 EOREAD4(sc, EHCI_USBINTR), 0); 1609 USBHIST_LOG(ehcidebug, 1610 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1611 "async = 0x%08x", 1612 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1613 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1614 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1615 for (i = 1; i <= sc->sc_noport; i += 2) { 1616 if (i == sc->sc_noport) { 1617 USBHIST_LOG(ehcidebug, 1618 "port %d status = 0x%08x", i, 1619 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1620 } else { 1621 USBHIST_LOG(ehcidebug, 1622 "port %d status = 0x%08x port %d status = 0x%08x", 1623 i, EOREAD4(sc, EHCI_PORTSC(i)), 1624 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1625 } 1626 } 1627 } 1628 1629 #ifdef EHCI_DEBUG 1630 #define ehci_dump_link(link, type) do { \ 1631 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1632 link, \ 1633 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1634 if (type) { \ 1635 USBHIST_LOG(ehcidebug, \ 1636 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1637 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1638 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1639 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1640 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1641 } \ 1642 } while(0) 1643 #else 1644 #define ehci_dump_link(link, type) 1645 #endif 1646 1647 Static void 1648 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1649 { 1650 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1651 int i; 1652 uint32_t stop = 0; 1653 1654 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1655 ehci_dump_sqtd(sqtd); 1656 usb_syncmem(&sqtd->dma, 1657 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1658 sizeof(sqtd->qtd), 1659 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1660 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1661 usb_syncmem(&sqtd->dma, 1662 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1663 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1664 } 1665 if (sqtd) 1666 USBHIST_LOG(ehcidebug, 1667 "dump aborted, too many TDs", 0, 0, 0, 0); 1668 } 1669 1670 Static void 1671 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1672 { 1673 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1674 1675 usb_syncmem(&sqtd->dma, sqtd->offs, 1676 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1677 1678 USBHIST_LOGN(ehcidebug, 10, 1679 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1680 ehci_dump_qtd(&sqtd->qtd); 1681 1682 usb_syncmem(&sqtd->dma, sqtd->offs, 1683 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1684 } 1685 1686 Static void 1687 ehci_dump_qtd(ehci_qtd_t *qtd) 1688 { 1689 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1690 1691 #ifdef USBHIST 1692 uint32_t s = le32toh(qtd->qtd_status); 1693 #endif 1694 1695 USBHIST_LOGN(ehcidebug, 10, 1696 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1697 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1698 USBHIST_LOGN(ehcidebug, 10, 1699 " toggle = %d ioc = %d bytes = %#x " 1700 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1701 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1702 USBHIST_LOGN(ehcidebug, 10, 1703 " cerr = %d pid = %d stat = %x", 1704 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1705 0); 1706 USBHIST_LOGN(ehcidebug, 10, 1707 "active =%d halted=%d buferr=%d babble=%d", 1708 s & EHCI_QTD_ACTIVE ? 1 : 0, 1709 s & EHCI_QTD_HALTED ? 1 : 0, 1710 s & EHCI_QTD_BUFERR ? 1 : 0, 1711 s & EHCI_QTD_BABBLE ? 1 : 0); 1712 USBHIST_LOGN(ehcidebug, 10, 1713 "xacterr=%d missed=%d split =%d ping =%d", 1714 s & EHCI_QTD_XACTERR ? 1 : 0, 1715 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1716 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1717 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1718 USBHIST_LOGN(ehcidebug, 10, 1719 "buffer[0] = %#x buffer[1] = %#x " 1720 "buffer[2] = %#x buffer[3] = %#x", 1721 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1722 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1723 USBHIST_LOGN(ehcidebug, 10, 1724 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1725 } 1726 1727 Static void 1728 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1729 { 1730 #ifdef USBHIST 1731 ehci_qh_t *qh = &sqh->qh; 1732 ehci_link_t link; 1733 #endif 1734 uint32_t endp, endphub; 1735 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1736 1737 usb_syncmem(&sqh->dma, sqh->offs, 1738 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1739 1740 USBHIST_LOGN(ehcidebug, 10, 1741 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1742 link = le32toh(qh->qh_link); 1743 ehci_dump_link(link, true); 1744 1745 endp = le32toh(qh->qh_endp); 1746 USBHIST_LOGN(ehcidebug, 10, 1747 " endp = %#x", endp, 0, 0, 0); 1748 USBHIST_LOGN(ehcidebug, 10, 1749 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1750 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1751 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1752 USBHIST_LOGN(ehcidebug, 10, 1753 " dtc = %d hrecl = %d", 1754 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1755 USBHIST_LOGN(ehcidebug, 10, 1756 " ctl = %d nrl = %d mpl = %#x(%d)", 1757 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1758 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1759 1760 endphub = le32toh(qh->qh_endphub); 1761 USBHIST_LOGN(ehcidebug, 10, 1762 " endphub = %#x", endphub, 0, 0, 0); 1763 USBHIST_LOGN(ehcidebug, 10, 1764 " smask = 0x%02x cmask = 0x%02x", 1765 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1766 USBHIST_LOGN(ehcidebug, 10, 1767 " huba = 0x%02x port = %d mult = %d", 1768 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1769 EHCI_QH_GET_MULT(endphub), 0); 1770 1771 link = le32toh(qh->qh_curqtd); 1772 ehci_dump_link(link, false); 1773 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1774 ehci_dump_qtd(&qh->qh_qtd); 1775 1776 usb_syncmem(&sqh->dma, sqh->offs, 1777 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1778 } 1779 1780 Static void 1781 ehci_dump_itd(struct ehci_soft_itd *itd) 1782 { 1783 ehci_isoc_trans_t t; 1784 ehci_isoc_bufr_ptr_t b, b2, b3; 1785 int i; 1786 1787 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1788 1789 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1790 0, 0); 1791 1792 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1793 t = le32toh(itd->itd.itd_ctl[i]); 1794 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1795 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1796 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1797 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1798 EHCI_ITD_GET_OFFS(t), 0); 1799 } 1800 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1801 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1802 USBHIST_LOG(ehcidebug, " %x", 1803 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1804 1805 b = le32toh(itd->itd.itd_bufr[0]); 1806 b2 = le32toh(itd->itd.itd_bufr[1]); 1807 b3 = le32toh(itd->itd.itd_bufr[2]); 1808 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1809 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1810 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1811 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1812 } 1813 1814 Static void 1815 ehci_dump_sitd(struct ehci_soft_itd *itd) 1816 { 1817 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1818 1819 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1820 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1821 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1822 itd->xfer_next, itd->physaddr, itd->slot, 0); 1823 } 1824 1825 Static void 1826 ehci_dump_exfer(struct ehci_xfer *ex) 1827 { 1828 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1829 1830 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1831 ex, ex->sqtdstart, ex->sqtdend, 0); 1832 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1833 ex->itdstart, ex->itdend, ex->isdone, 0); 1834 } 1835 #endif 1836 1837 Static usbd_status 1838 ehci_open(usbd_pipe_handle pipe) 1839 { 1840 usbd_device_handle dev = pipe->up_dev; 1841 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1842 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1843 uint8_t addr = dev->ud_addr; 1844 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1845 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1846 ehci_soft_qh_t *sqh; 1847 usbd_status err; 1848 int ival, speed, naks; 1849 int hshubaddr, hshubport; 1850 1851 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1852 1853 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1854 pipe, addr, ed->bEndpointAddress, sc->sc_addr); 1855 1856 if (dev->ud_myhsport) { 1857 /* 1858 * When directly attached FS/LS device while doing embedded 1859 * transaction translations and we are the hub, set the hub 1860 * address to 0 (us). 1861 */ 1862 if (!(sc->sc_flags & EHCIF_ETTF) 1863 || (dev->ud_myhsport->up_parent->ud_addr != sc->sc_addr)) { 1864 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1865 } else { 1866 hshubaddr = 0; 1867 } 1868 hshubport = dev->ud_myhsport->up_portno; 1869 } else { 1870 hshubaddr = 0; 1871 hshubport = 0; 1872 } 1873 1874 if (sc->sc_dying) 1875 return (USBD_IOERROR); 1876 1877 /* toggle state needed for bulk endpoints */ 1878 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1879 1880 if (addr == sc->sc_addr) { 1881 switch (ed->bEndpointAddress) { 1882 case USB_CONTROL_ENDPOINT: 1883 pipe->up_methods = &ehci_root_ctrl_methods; 1884 break; 1885 case UE_DIR_IN | EHCI_INTR_ENDPT: 1886 pipe->up_methods = &ehci_root_intr_methods; 1887 break; 1888 default: 1889 USBHIST_LOG(ehcidebug, 1890 "bad bEndpointAddress 0x%02x", 1891 ed->bEndpointAddress, 0, 0, 0); 1892 return (USBD_INVAL); 1893 } 1894 return (USBD_NORMAL_COMPLETION); 1895 } 1896 1897 /* XXX All this stuff is only valid for async. */ 1898 switch (dev->ud_speed) { 1899 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1900 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1901 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1902 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1903 } 1904 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1905 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1906 hshubaddr, hshubport, 0, 0); 1907 return USBD_INVAL; 1908 } 1909 1910 /* 1911 * For interrupt transfer, nak throttling must be disabled, but for 1912 * the other transfer type, nak throttling should be enabled from the 1913 * viewpoint that avoids the memory thrashing. 1914 */ 1915 naks = (xfertype == UE_INTERRUPT) ? 0 1916 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1917 1918 /* Allocate sqh for everything, save isoc xfers */ 1919 if (xfertype != UE_ISOCHRONOUS) { 1920 sqh = ehci_alloc_sqh(sc); 1921 if (sqh == NULL) 1922 return (USBD_NOMEM); 1923 /* qh_link filled when the QH is added */ 1924 sqh->qh.qh_endp = htole32( 1925 EHCI_QH_SET_ADDR(addr) | 1926 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1927 EHCI_QH_SET_EPS(speed) | 1928 EHCI_QH_DTC | 1929 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1930 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1931 EHCI_QH_CTL : 0) | 1932 EHCI_QH_SET_NRL(naks) 1933 ); 1934 sqh->qh.qh_endphub = htole32( 1935 EHCI_QH_SET_MULT(1) | 1936 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1937 ); 1938 if (speed != EHCI_QH_SPEED_HIGH) 1939 sqh->qh.qh_endphub |= htole32( 1940 EHCI_QH_SET_PORT(hshubport) | 1941 EHCI_QH_SET_HUBA(hshubaddr) | 1942 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1943 ); 1944 sqh->qh.qh_curqtd = EHCI_NULL; 1945 /* Fill the overlay qTD */ 1946 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1947 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1948 sqh->qh.qh_qtd.qtd_status = htole32(0); 1949 1950 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1951 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1952 epipe->sqh = sqh; 1953 } else { 1954 sqh = NULL; 1955 } /*xfertype == UE_ISOC*/ 1956 1957 switch (xfertype) { 1958 case UE_CONTROL: 1959 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1960 0, &epipe->u.ctl.reqdma); 1961 #ifdef EHCI_DEBUG 1962 if (err) 1963 printf("ehci_open: usb_allocmem()=%d\n", err); 1964 #endif 1965 if (err) 1966 goto bad; 1967 pipe->up_methods = &ehci_device_ctrl_methods; 1968 mutex_enter(&sc->sc_lock); 1969 ehci_add_qh(sc, sqh, sc->sc_async_head); 1970 mutex_exit(&sc->sc_lock); 1971 break; 1972 case UE_BULK: 1973 pipe->up_methods = &ehci_device_bulk_methods; 1974 mutex_enter(&sc->sc_lock); 1975 ehci_add_qh(sc, sqh, sc->sc_async_head); 1976 mutex_exit(&sc->sc_lock); 1977 break; 1978 case UE_INTERRUPT: 1979 pipe->up_methods = &ehci_device_intr_methods; 1980 ival = pipe->up_interval; 1981 if (ival == USBD_DEFAULT_INTERVAL) { 1982 if (speed == EHCI_QH_SPEED_HIGH) { 1983 if (ed->bInterval > 16) { 1984 /* 1985 * illegal with high-speed, but there 1986 * were documentation bugs in the spec, 1987 * so be generous 1988 */ 1989 ival = 256; 1990 } else 1991 ival = (1 << (ed->bInterval - 1)) / 8; 1992 } else 1993 ival = ed->bInterval; 1994 } 1995 err = ehci_device_setintr(sc, sqh, ival); 1996 if (err) 1997 goto bad; 1998 break; 1999 case UE_ISOCHRONOUS: 2000 if (speed == EHCI_QH_SPEED_HIGH) 2001 pipe->up_methods = &ehci_device_isoc_methods; 2002 else 2003 pipe->up_methods = &ehci_device_fs_isoc_methods; 2004 if (ed->bInterval == 0 || ed->bInterval > 16) { 2005 printf("ehci: opening pipe with invalid bInterval\n"); 2006 err = USBD_INVAL; 2007 goto bad; 2008 } 2009 if (UGETW(ed->wMaxPacketSize) == 0) { 2010 printf("ehci: zero length endpoint open request\n"); 2011 err = USBD_INVAL; 2012 goto bad; 2013 } 2014 epipe->u.isoc.next_frame = 0; 2015 epipe->u.isoc.cur_xfers = 0; 2016 break; 2017 default: 2018 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2019 err = USBD_INVAL; 2020 goto bad; 2021 } 2022 return (USBD_NORMAL_COMPLETION); 2023 2024 bad: 2025 if (sqh != NULL) 2026 ehci_free_sqh(sc, sqh); 2027 return (err); 2028 } 2029 2030 /* 2031 * Add an ED to the schedule. Called with USB lock held. 2032 */ 2033 Static void 2034 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2035 { 2036 2037 KASSERT(mutex_owned(&sc->sc_lock)); 2038 2039 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2040 2041 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2042 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2043 2044 sqh->next = head->next; 2045 sqh->qh.qh_link = head->qh.qh_link; 2046 2047 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2048 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2049 2050 head->next = sqh; 2051 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2052 2053 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2054 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2055 2056 #ifdef EHCI_DEBUG 2057 ehci_dump_sqh(sqh); 2058 #endif 2059 } 2060 2061 /* 2062 * Remove an ED from the schedule. Called with USB lock held. 2063 */ 2064 Static void 2065 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2066 { 2067 ehci_soft_qh_t *p; 2068 2069 KASSERT(mutex_owned(&sc->sc_lock)); 2070 2071 /* XXX */ 2072 for (p = head; p != NULL && p->next != sqh; p = p->next) 2073 ; 2074 if (p == NULL) 2075 panic("ehci_rem_qh: ED not found"); 2076 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2077 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2078 p->next = sqh->next; 2079 p->qh.qh_link = sqh->qh.qh_link; 2080 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2081 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2082 2083 ehci_sync_hc(sc); 2084 } 2085 2086 Static void 2087 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2088 { 2089 int i; 2090 uint32_t status; 2091 2092 /* Save toggle bit and ping status. */ 2093 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2094 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2095 status = sqh->qh.qh_qtd.qtd_status & 2096 htole32(EHCI_QTD_TOGGLE_MASK | 2097 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2098 /* Set HALTED to make hw leave it alone. */ 2099 sqh->qh.qh_qtd.qtd_status = 2100 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2101 usb_syncmem(&sqh->dma, 2102 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2103 sizeof(sqh->qh.qh_qtd.qtd_status), 2104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2105 sqh->qh.qh_curqtd = 0; 2106 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2107 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2108 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2109 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2110 sqh->sqtd = sqtd; 2111 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2112 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2113 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2114 sqh->qh.qh_qtd.qtd_status = status; 2115 usb_syncmem(&sqh->dma, 2116 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2117 sizeof(sqh->qh.qh_qtd.qtd_status), 2118 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2119 } 2120 2121 /* 2122 * Ensure that the HC has released all references to the QH. We do this 2123 * by asking for a Async Advance Doorbell interrupt and then we wait for 2124 * the interrupt. 2125 * To make this easier we first obtain exclusive use of the doorbell. 2126 */ 2127 Static void 2128 ehci_sync_hc(ehci_softc_t *sc) 2129 { 2130 int error __diagused; 2131 2132 KASSERT(mutex_owned(&sc->sc_lock)); 2133 2134 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2135 2136 if (sc->sc_dying) { 2137 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2138 return; 2139 } 2140 /* ask for doorbell */ 2141 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2142 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2143 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2144 2145 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2146 2147 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2148 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2149 #ifdef DIAGNOSTIC 2150 if (error) 2151 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2152 #endif 2153 } 2154 2155 Static void 2156 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2157 { 2158 struct ehci_soft_itd *itd, *prev; 2159 2160 prev = NULL; 2161 2162 if (exfer->itdstart == NULL || exfer->itdend == NULL) 2163 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2164 2165 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2166 prev = itd->u.frame_list.prev; 2167 /* Unlink itd from hardware chain, or frame array */ 2168 if (prev == NULL) { /* We're at the table head */ 2169 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2170 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2171 usb_syncmem(&sc->sc_fldma, 2172 sizeof(ehci_link_t) * itd->slot, 2173 sizeof(ehci_link_t), 2174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2175 2176 if (itd->u.frame_list.next != NULL) 2177 itd->u.frame_list.next->u.frame_list.prev = NULL; 2178 } else { 2179 /* XXX this part is untested... */ 2180 prev->itd.itd_next = itd->itd.itd_next; 2181 usb_syncmem(&itd->dma, 2182 itd->offs + offsetof(ehci_itd_t, itd_next), 2183 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2184 2185 prev->u.frame_list.next = itd->u.frame_list.next; 2186 if (itd->u.frame_list.next != NULL) 2187 itd->u.frame_list.next->u.frame_list.prev = prev; 2188 } 2189 } 2190 2191 prev = NULL; 2192 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2193 if (prev != NULL) 2194 ehci_free_itd(sc, prev); 2195 prev = itd; 2196 } 2197 if (prev) 2198 ehci_free_itd(sc, prev); 2199 exfer->itdstart = NULL; 2200 exfer->itdend = NULL; 2201 } 2202 2203 Static void 2204 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2205 { 2206 struct ehci_soft_sitd *sitd, *prev; 2207 2208 prev = NULL; 2209 2210 if (exfer->sitdstart == NULL || exfer->sitdend == NULL) 2211 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2212 2213 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2214 prev = sitd->u.frame_list.prev; 2215 /* Unlink sitd from hardware chain, or frame array */ 2216 if (prev == NULL) { /* We're at the table head */ 2217 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2218 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2219 usb_syncmem(&sc->sc_fldma, 2220 sizeof(ehci_link_t) * sitd->slot, 2221 sizeof(ehci_link_t), 2222 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2223 2224 if (sitd->u.frame_list.next != NULL) 2225 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2226 } else { 2227 /* XXX this part is untested... */ 2228 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2229 usb_syncmem(&sitd->dma, 2230 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2231 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2232 2233 prev->u.frame_list.next = sitd->u.frame_list.next; 2234 if (sitd->u.frame_list.next != NULL) 2235 sitd->u.frame_list.next->u.frame_list.prev = prev; 2236 } 2237 } 2238 2239 prev = NULL; 2240 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2241 if (prev != NULL) 2242 ehci_free_sitd(sc, prev); 2243 prev = sitd; 2244 } 2245 if (prev) 2246 ehci_free_sitd(sc, prev); 2247 exfer->sitdstart = NULL; 2248 exfer->sitdend = NULL; 2249 } 2250 2251 2252 /***********/ 2253 2254 /* 2255 * Data structures and routines to emulate the root hub. 2256 */ 2257 Static usb_device_descriptor_t ehci_devd = { 2258 USB_DEVICE_DESCRIPTOR_SIZE, 2259 UDESC_DEVICE, /* type */ 2260 {0x00, 0x02}, /* USB version */ 2261 UDCLASS_HUB, /* class */ 2262 UDSUBCLASS_HUB, /* subclass */ 2263 UDPROTO_HSHUBSTT, /* protocol */ 2264 64, /* max packet */ 2265 {0},{0},{0x00,0x01}, /* device id */ 2266 1,2,0, /* string indicies */ 2267 1 /* # of configurations */ 2268 }; 2269 2270 Static const usb_device_qualifier_t ehci_odevd = { 2271 USB_DEVICE_DESCRIPTOR_SIZE, 2272 UDESC_DEVICE_QUALIFIER, /* type */ 2273 {0x00, 0x02}, /* USB version */ 2274 UDCLASS_HUB, /* class */ 2275 UDSUBCLASS_HUB, /* subclass */ 2276 UDPROTO_FSHUB, /* protocol */ 2277 64, /* max packet */ 2278 1, /* # of configurations */ 2279 0 2280 }; 2281 2282 Static const usb_config_descriptor_t ehci_confd = { 2283 USB_CONFIG_DESCRIPTOR_SIZE, 2284 UDESC_CONFIG, 2285 {USB_CONFIG_DESCRIPTOR_SIZE + 2286 USB_INTERFACE_DESCRIPTOR_SIZE + 2287 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2288 1, 2289 1, 2290 0, 2291 UC_ATTR_MBO | UC_SELF_POWERED, 2292 0 /* max power */ 2293 }; 2294 2295 Static const usb_interface_descriptor_t ehci_ifcd = { 2296 USB_INTERFACE_DESCRIPTOR_SIZE, 2297 UDESC_INTERFACE, 2298 0, 2299 0, 2300 1, 2301 UICLASS_HUB, 2302 UISUBCLASS_HUB, 2303 UIPROTO_HSHUBSTT, 2304 0 2305 }; 2306 2307 Static const usb_endpoint_descriptor_t ehci_endpd = { 2308 USB_ENDPOINT_DESCRIPTOR_SIZE, 2309 UDESC_ENDPOINT, 2310 UE_DIR_IN | EHCI_INTR_ENDPT, 2311 UE_INTERRUPT, 2312 {8, 0}, /* max packet */ 2313 12 2314 }; 2315 2316 Static const usb_hub_descriptor_t ehci_hubd = { 2317 USB_HUB_DESCRIPTOR_SIZE, 2318 UDESC_HUB, 2319 0, 2320 {0,0}, 2321 0, 2322 0, 2323 {""}, 2324 {""}, 2325 }; 2326 2327 /* 2328 * Simulate a hardware hub by handling all the necessary requests. 2329 */ 2330 Static usbd_status 2331 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2332 { 2333 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2334 usbd_status err; 2335 2336 /* Insert last in queue. */ 2337 mutex_enter(&sc->sc_lock); 2338 err = usb_insert_transfer(xfer); 2339 mutex_exit(&sc->sc_lock); 2340 if (err) 2341 return (err); 2342 2343 /* Pipe isn't running, start first */ 2344 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2345 } 2346 2347 Static usbd_status 2348 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2349 { 2350 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2351 usb_device_request_t *req; 2352 void *buf = NULL; 2353 int port, i; 2354 int len, value, index, l, totlen = 0; 2355 usb_port_status_t ps; 2356 usb_hub_descriptor_t hubd; 2357 usbd_status err; 2358 uint32_t v; 2359 2360 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2361 2362 if (sc->sc_dying) 2363 return (USBD_IOERROR); 2364 2365 #ifdef DIAGNOSTIC 2366 if (!(xfer->ux_rqflags & URQ_REQUEST)) 2367 /* XXX panic */ 2368 return (USBD_INVAL); 2369 #endif 2370 req = &xfer->ux_request; 2371 2372 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2373 req->bmRequestType, req->bRequest, 0, 0); 2374 2375 len = UGETW(req->wLength); 2376 value = UGETW(req->wValue); 2377 index = UGETW(req->wIndex); 2378 2379 if (len != 0) 2380 buf = xfer->ux_buf; 2381 2382 #define C(x,y) ((x) | ((y) << 8)) 2383 switch(C(req->bRequest, req->bmRequestType)) { 2384 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2385 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2386 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2387 /* 2388 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2389 * for the integrated root hub. 2390 */ 2391 break; 2392 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2393 if (len > 0) { 2394 *(uint8_t *)buf = sc->sc_conf; 2395 totlen = 1; 2396 } 2397 break; 2398 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2399 USBHIST_LOG(ehcidebug, "wValue=0x%04x", value, 0, 0, 0); 2400 if (len == 0) 2401 break; 2402 switch(value >> 8) { 2403 case UDESC_DEVICE: 2404 if ((value & 0xff) != 0) { 2405 err = USBD_IOERROR; 2406 goto ret; 2407 } 2408 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2409 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2410 memcpy(buf, &ehci_devd, l); 2411 break; 2412 /* 2413 * We can't really operate at another speed, but the spec says 2414 * we need this descriptor. 2415 */ 2416 case UDESC_DEVICE_QUALIFIER: 2417 if ((value & 0xff) != 0) { 2418 err = USBD_IOERROR; 2419 goto ret; 2420 } 2421 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2422 memcpy(buf, &ehci_odevd, l); 2423 break; 2424 /* 2425 * We can't really operate at another speed, but the spec says 2426 * we need this descriptor. 2427 */ 2428 case UDESC_OTHER_SPEED_CONFIGURATION: 2429 case UDESC_CONFIG: 2430 if ((value & 0xff) != 0) { 2431 err = USBD_IOERROR; 2432 goto ret; 2433 } 2434 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2435 memcpy(buf, &ehci_confd, l); 2436 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2437 value >> 8; 2438 buf = (char *)buf + l; 2439 len -= l; 2440 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2441 totlen += l; 2442 memcpy(buf, &ehci_ifcd, l); 2443 buf = (char *)buf + l; 2444 len -= l; 2445 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2446 totlen += l; 2447 memcpy(buf, &ehci_endpd, l); 2448 break; 2449 case UDESC_STRING: 2450 #define sd ((usb_string_descriptor_t *)buf) 2451 switch (value & 0xff) { 2452 case 0: /* Language table */ 2453 totlen = usb_makelangtbl(sd, len); 2454 break; 2455 case 1: /* Vendor */ 2456 totlen = usb_makestrdesc(sd, len, 2457 sc->sc_vendor); 2458 break; 2459 case 2: /* Product */ 2460 totlen = usb_makestrdesc(sd, len, 2461 "EHCI root hub"); 2462 break; 2463 } 2464 #undef sd 2465 break; 2466 default: 2467 err = USBD_IOERROR; 2468 goto ret; 2469 } 2470 break; 2471 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2472 if (len > 0) { 2473 *(uint8_t *)buf = 0; 2474 totlen = 1; 2475 } 2476 break; 2477 case C(UR_GET_STATUS, UT_READ_DEVICE): 2478 if (len > 1) { 2479 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2480 totlen = 2; 2481 } 2482 break; 2483 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2484 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2485 if (len > 1) { 2486 USETW(((usb_status_t *)buf)->wStatus, 0); 2487 totlen = 2; 2488 } 2489 break; 2490 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2491 if (value >= USB_MAX_DEVICES) { 2492 err = USBD_IOERROR; 2493 goto ret; 2494 } 2495 sc->sc_addr = value; 2496 break; 2497 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2498 if (value != 0 && value != 1) { 2499 err = USBD_IOERROR; 2500 goto ret; 2501 } 2502 sc->sc_conf = value; 2503 break; 2504 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2505 break; 2506 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2507 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2508 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2509 err = USBD_IOERROR; 2510 goto ret; 2511 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2512 break; 2513 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2514 break; 2515 /* Hub requests */ 2516 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2517 break; 2518 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2519 USBHIST_LOG(ehcidebug, 2520 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2521 0, 0); 2522 if (index < 1 || index > sc->sc_noport) { 2523 err = USBD_IOERROR; 2524 goto ret; 2525 } 2526 port = EHCI_PORTSC(index); 2527 v = EOREAD4(sc, port); 2528 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2529 v &= ~EHCI_PS_CLEAR; 2530 switch(value) { 2531 case UHF_PORT_ENABLE: 2532 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2533 break; 2534 case UHF_PORT_SUSPEND: 2535 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2536 break; 2537 v &= ~EHCI_PS_SUSP; 2538 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2539 /* see USB2 spec ch. 7.1.7.7 */ 2540 usb_delay_ms(&sc->sc_bus, 20); 2541 EOWRITE4(sc, port, v); 2542 usb_delay_ms(&sc->sc_bus, 2); 2543 #ifdef DEBUG 2544 v = EOREAD4(sc, port); 2545 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2546 printf("ehci: resume failed: %x\n", v); 2547 #endif 2548 break; 2549 case UHF_PORT_POWER: 2550 if (sc->sc_hasppc) 2551 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2552 break; 2553 case UHF_PORT_TEST: 2554 USBHIST_LOG(ehcidebug, "clear port test " 2555 "%d", index, 0, 0, 0); 2556 break; 2557 case UHF_PORT_INDICATOR: 2558 USBHIST_LOG(ehcidebug, "clear port ind " 2559 "%d", index, 0, 0, 0); 2560 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2561 break; 2562 case UHF_C_PORT_CONNECTION: 2563 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2564 break; 2565 case UHF_C_PORT_ENABLE: 2566 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2567 break; 2568 case UHF_C_PORT_SUSPEND: 2569 /* how? */ 2570 break; 2571 case UHF_C_PORT_OVER_CURRENT: 2572 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2573 break; 2574 case UHF_C_PORT_RESET: 2575 sc->sc_isreset[index] = 0; 2576 break; 2577 default: 2578 err = USBD_IOERROR; 2579 goto ret; 2580 } 2581 #if 0 2582 switch(value) { 2583 case UHF_C_PORT_CONNECTION: 2584 case UHF_C_PORT_ENABLE: 2585 case UHF_C_PORT_SUSPEND: 2586 case UHF_C_PORT_OVER_CURRENT: 2587 case UHF_C_PORT_RESET: 2588 default: 2589 break; 2590 } 2591 #endif 2592 break; 2593 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2594 if (len == 0) 2595 break; 2596 if ((value & 0xff) != 0) { 2597 err = USBD_IOERROR; 2598 goto ret; 2599 } 2600 hubd = ehci_hubd; 2601 hubd.bNbrPorts = sc->sc_noport; 2602 v = EOREAD4(sc, EHCI_HCSPARAMS); 2603 USETW(hubd.wHubCharacteristics, 2604 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2605 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2606 ? UHD_PORT_IND : 0); 2607 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2608 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2609 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2610 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2611 l = min(len, hubd.bDescLength); 2612 totlen = l; 2613 memcpy(buf, &hubd, l); 2614 break; 2615 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2616 if (len != 4) { 2617 err = USBD_IOERROR; 2618 goto ret; 2619 } 2620 memset(buf, 0, len); /* ? XXX */ 2621 totlen = len; 2622 break; 2623 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2624 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2625 if (index < 1 || index > sc->sc_noport) { 2626 err = USBD_IOERROR; 2627 goto ret; 2628 } 2629 if (len != 4) { 2630 err = USBD_IOERROR; 2631 goto ret; 2632 } 2633 v = EOREAD4(sc, EHCI_PORTSC(index)); 2634 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2635 2636 i = UPS_HIGH_SPEED; 2637 if (sc->sc_flags & EHCIF_ETTF) { 2638 /* 2639 * If we are doing embedded transaction translation, 2640 * then directly attached LS/FS devices are reset by 2641 * the EHCI controller itself. PSPD is encoded 2642 * the same way as in USBSTATUS. 2643 */ 2644 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2645 } 2646 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2647 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2648 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2649 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2650 if (v & EHCI_PS_PR) i |= UPS_RESET; 2651 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2652 if (sc->sc_vendor_port_status) 2653 i = sc->sc_vendor_port_status(sc, v, i); 2654 USETW(ps.wPortStatus, i); 2655 i = 0; 2656 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2657 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2658 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2659 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2660 USETW(ps.wPortChange, i); 2661 l = min(len, sizeof ps); 2662 memcpy(buf, &ps, l); 2663 totlen = l; 2664 break; 2665 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2666 err = USBD_IOERROR; 2667 goto ret; 2668 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2669 break; 2670 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2671 if (index < 1 || index > sc->sc_noport) { 2672 err = USBD_IOERROR; 2673 goto ret; 2674 } 2675 port = EHCI_PORTSC(index); 2676 v = EOREAD4(sc, port); 2677 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2678 v &= ~EHCI_PS_CLEAR; 2679 switch(value) { 2680 case UHF_PORT_ENABLE: 2681 EOWRITE4(sc, port, v | EHCI_PS_PE); 2682 break; 2683 case UHF_PORT_SUSPEND: 2684 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2685 break; 2686 case UHF_PORT_RESET: 2687 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2688 if (EHCI_PS_IS_LOWSPEED(v) 2689 && sc->sc_ncomp > 0 2690 && !(sc->sc_flags & EHCIF_ETTF)) { 2691 /* 2692 * Low speed device on non-ETTF controller or 2693 * unaccompanied controller, give up ownership. 2694 */ 2695 ehci_disown(sc, index, 1); 2696 break; 2697 } 2698 /* Start reset sequence. */ 2699 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2700 EOWRITE4(sc, port, v | EHCI_PS_PR); 2701 /* Wait for reset to complete. */ 2702 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2703 if (sc->sc_dying) { 2704 err = USBD_IOERROR; 2705 goto ret; 2706 } 2707 /* 2708 * An embedded transaction translator will automatically 2709 * terminate the reset sequence so there's no need to 2710 * it. 2711 */ 2712 v = EOREAD4(sc, port); 2713 if (v & EHCI_PS_PR) { 2714 /* Terminate reset sequence. */ 2715 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2716 /* Wait for HC to complete reset. */ 2717 usb_delay_ms(&sc->sc_bus, 2718 EHCI_PORT_RESET_COMPLETE); 2719 if (sc->sc_dying) { 2720 err = USBD_IOERROR; 2721 goto ret; 2722 } 2723 } 2724 2725 v = EOREAD4(sc, port); 2726 USBHIST_LOG(ehcidebug, 2727 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2728 if (v & EHCI_PS_PR) { 2729 printf("%s: port reset timeout\n", 2730 device_xname(sc->sc_dev)); 2731 return (USBD_TIMEOUT); 2732 } 2733 if (!(v & EHCI_PS_PE)) { 2734 /* Not a high speed device, give up ownership.*/ 2735 ehci_disown(sc, index, 0); 2736 break; 2737 } 2738 sc->sc_isreset[index] = 1; 2739 USBHIST_LOG(ehcidebug, 2740 "ehci port %d reset, status = 0x%08x", index, v, 0, 2741 0); 2742 break; 2743 case UHF_PORT_POWER: 2744 USBHIST_LOG(ehcidebug, 2745 "set port power %d (has PPC = %d)", index, 2746 sc->sc_hasppc, 0, 0); 2747 if (sc->sc_hasppc) 2748 EOWRITE4(sc, port, v | EHCI_PS_PP); 2749 break; 2750 case UHF_PORT_TEST: 2751 USBHIST_LOG(ehcidebug, "set port test %d", 2752 index, 0, 0, 0); 2753 break; 2754 case UHF_PORT_INDICATOR: 2755 USBHIST_LOG(ehcidebug, "set port ind %d", 2756 index, 0, 0, 0); 2757 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2758 break; 2759 default: 2760 err = USBD_IOERROR; 2761 goto ret; 2762 } 2763 break; 2764 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2765 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2766 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2767 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2768 break; 2769 default: 2770 err = USBD_IOERROR; 2771 goto ret; 2772 } 2773 xfer->ux_actlen = totlen; 2774 err = USBD_NORMAL_COMPLETION; 2775 ret: 2776 mutex_enter(&sc->sc_lock); 2777 xfer->ux_status = err; 2778 usb_transfer_complete(xfer); 2779 mutex_exit(&sc->sc_lock); 2780 return (USBD_IN_PROGRESS); 2781 } 2782 2783 Static void 2784 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2785 { 2786 int port; 2787 uint32_t v; 2788 2789 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2790 2791 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2792 #ifdef DIAGNOSTIC 2793 if (sc->sc_npcomp != 0) { 2794 int i = (index-1) / sc->sc_npcomp; 2795 if (i >= sc->sc_ncomp) 2796 printf("%s: strange port\n", 2797 device_xname(sc->sc_dev)); 2798 else 2799 printf("%s: handing over %s speed device on " 2800 "port %d to %s\n", 2801 device_xname(sc->sc_dev), 2802 lowspeed ? "low" : "full", 2803 index, device_xname(sc->sc_comps[i])); 2804 } else { 2805 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2806 } 2807 #endif 2808 port = EHCI_PORTSC(index); 2809 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2810 EOWRITE4(sc, port, v | EHCI_PS_PO); 2811 } 2812 2813 /* Abort a root control request. */ 2814 Static void 2815 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2816 { 2817 /* Nothing to do, all transfers are synchronous. */ 2818 } 2819 2820 /* Close the root pipe. */ 2821 Static void 2822 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2823 { 2824 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2825 /* Nothing to do. */ 2826 } 2827 2828 Static void 2829 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2830 { 2831 xfer->ux_hcpriv = NULL; 2832 } 2833 2834 Static usbd_status 2835 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2836 { 2837 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2838 usbd_status err; 2839 2840 /* Insert last in queue. */ 2841 mutex_enter(&sc->sc_lock); 2842 err = usb_insert_transfer(xfer); 2843 mutex_exit(&sc->sc_lock); 2844 if (err) 2845 return (err); 2846 2847 /* Pipe isn't running, start first */ 2848 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2849 } 2850 2851 Static usbd_status 2852 ehci_root_intr_start(usbd_xfer_handle xfer) 2853 { 2854 usbd_pipe_handle pipe = xfer->ux_pipe; 2855 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2856 2857 if (sc->sc_dying) 2858 return (USBD_IOERROR); 2859 2860 mutex_enter(&sc->sc_lock); 2861 sc->sc_intrxfer = xfer; 2862 mutex_exit(&sc->sc_lock); 2863 2864 return (USBD_IN_PROGRESS); 2865 } 2866 2867 /* Abort a root interrupt request. */ 2868 Static void 2869 ehci_root_intr_abort(usbd_xfer_handle xfer) 2870 { 2871 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2872 2873 KASSERT(mutex_owned(&sc->sc_lock)); 2874 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2875 2876 sc->sc_intrxfer = NULL; 2877 2878 xfer->ux_status = USBD_CANCELLED; 2879 usb_transfer_complete(xfer); 2880 } 2881 2882 /* Close the root pipe. */ 2883 Static void 2884 ehci_root_intr_close(usbd_pipe_handle pipe) 2885 { 2886 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2887 2888 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2889 2890 KASSERT(mutex_owned(&sc->sc_lock)); 2891 2892 sc->sc_intrxfer = NULL; 2893 } 2894 2895 Static void 2896 ehci_root_intr_done(usbd_xfer_handle xfer) 2897 { 2898 xfer->ux_hcpriv = NULL; 2899 } 2900 2901 /************************/ 2902 2903 Static ehci_soft_qh_t * 2904 ehci_alloc_sqh(ehci_softc_t *sc) 2905 { 2906 ehci_soft_qh_t *sqh; 2907 usbd_status err; 2908 int i, offs; 2909 usb_dma_t dma; 2910 2911 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2912 2913 if (sc->sc_freeqhs == NULL) { 2914 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2915 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2916 EHCI_PAGE_SIZE, &dma); 2917 #ifdef EHCI_DEBUG 2918 if (err) 2919 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2920 #endif 2921 if (err) 2922 return (NULL); 2923 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2924 offs = i * EHCI_SQH_SIZE; 2925 sqh = KERNADDR(&dma, offs); 2926 sqh->physaddr = DMAADDR(&dma, offs); 2927 sqh->dma = dma; 2928 sqh->offs = offs; 2929 sqh->next = sc->sc_freeqhs; 2930 sc->sc_freeqhs = sqh; 2931 } 2932 } 2933 sqh = sc->sc_freeqhs; 2934 sc->sc_freeqhs = sqh->next; 2935 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2936 sqh->next = NULL; 2937 return (sqh); 2938 } 2939 2940 Static void 2941 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2942 { 2943 sqh->next = sc->sc_freeqhs; 2944 sc->sc_freeqhs = sqh; 2945 } 2946 2947 Static ehci_soft_qtd_t * 2948 ehci_alloc_sqtd(ehci_softc_t *sc) 2949 { 2950 ehci_soft_qtd_t *sqtd = NULL; 2951 usbd_status err; 2952 int i, offs; 2953 usb_dma_t dma; 2954 2955 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2956 2957 if (sc->sc_freeqtds == NULL) { 2958 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2959 2960 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2961 EHCI_PAGE_SIZE, &dma); 2962 #ifdef EHCI_DEBUG 2963 if (err) 2964 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2965 #endif 2966 if (err) 2967 goto done; 2968 2969 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2970 offs = i * EHCI_SQTD_SIZE; 2971 sqtd = KERNADDR(&dma, offs); 2972 sqtd->physaddr = DMAADDR(&dma, offs); 2973 sqtd->dma = dma; 2974 sqtd->offs = offs; 2975 2976 sqtd->nextqtd = sc->sc_freeqtds; 2977 sc->sc_freeqtds = sqtd; 2978 } 2979 } 2980 2981 sqtd = sc->sc_freeqtds; 2982 sc->sc_freeqtds = sqtd->nextqtd; 2983 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2984 sqtd->nextqtd = NULL; 2985 sqtd->xfer = NULL; 2986 2987 done: 2988 return (sqtd); 2989 } 2990 2991 Static void 2992 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2993 { 2994 2995 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2996 2997 sqtd->nextqtd = sc->sc_freeqtds; 2998 sc->sc_freeqtds = sqtd; 2999 } 3000 3001 Static usbd_status 3002 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 3003 int alen, int rd, usbd_xfer_handle xfer, 3004 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 3005 { 3006 ehci_soft_qtd_t *next, *cur; 3007 ehci_physaddr_t nextphys; 3008 uint32_t qtdstatus; 3009 int len, curlen, mps; 3010 int i, tog; 3011 int pages, pageoffs; 3012 bus_size_t curoffs; 3013 vaddr_t va, va_offs; 3014 usb_dma_t *dma = &xfer->ux_dmabuf; 3015 uint16_t flags = xfer->ux_flags; 3016 paddr_t a; 3017 3018 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3019 3020 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 3021 3022 len = alen; 3023 qtdstatus = EHCI_QTD_ACTIVE | 3024 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3025 EHCI_QTD_SET_CERR(3) 3026 /* IOC set below */ 3027 /* BYTES set below */ 3028 ; 3029 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 3030 tog = epipe->nexttoggle; 3031 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 3032 3033 cur = ehci_alloc_sqtd(sc); 3034 *sp = cur; 3035 if (cur == NULL) 3036 goto nomem; 3037 3038 usb_syncmem(dma, 0, alen, 3039 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3040 curoffs = 0; 3041 for (;;) { 3042 /* The EHCI hardware can handle at most 5 pages. */ 3043 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 3044 va_offs = EHCI_PAGE_OFFSET(va_offs); 3045 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 3046 /* we can handle it in this QTD */ 3047 curlen = len - curoffs; 3048 } else { 3049 /* must use multiple TDs, fill as much as possible. */ 3050 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 3051 3052 /* the length must be a multiple of the max size */ 3053 curlen -= curlen % mps; 3054 USBHIST_LOG(ehcidebug, "multiple QTDs, " 3055 "curlen=%d", curlen, 0, 0, 0); 3056 #ifdef DIAGNOSTIC 3057 if (curlen == 0) 3058 panic("ehci_alloc_sqtd_chain: curlen == 0"); 3059 #endif 3060 } 3061 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 3062 len, curlen, (size_t)curoffs, 0); 3063 3064 /* 3065 * Allocate another transfer if there's more data left, 3066 * or if force last short transfer flag is set and we're 3067 * allocating a multiple of the max packet size. 3068 */ 3069 3070 if (curoffs + curlen != len || 3071 ((curlen % mps) == 0 && !rd && curlen != 0 && 3072 (flags & USBD_FORCE_SHORT_XFER))) { 3073 next = ehci_alloc_sqtd(sc); 3074 if (next == NULL) 3075 goto nomem; 3076 nextphys = htole32(next->physaddr); 3077 } else { 3078 next = NULL; 3079 nextphys = EHCI_NULL; 3080 } 3081 3082 /* Find number of pages we'll be using, insert dma addresses */ 3083 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 3084 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3085 pageoffs = EHCI_PAGE(curoffs); 3086 for (i = 0; i < pages; i++) { 3087 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 3088 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 3089 /* Cast up to avoid compiler warnings */ 3090 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 3091 } 3092 3093 /* First buffer pointer requires a page offset to start at */ 3094 va = (vaddr_t)KERNADDR(dma, curoffs); 3095 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3096 3097 cur->nextqtd = next; 3098 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 3099 cur->qtd.qtd_status = 3100 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 3101 cur->xfer = xfer; 3102 cur->len = curlen; 3103 3104 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 3105 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 3106 3107 /* adjust the toggle based on the number of packets in this 3108 qtd */ 3109 if (((curlen + mps - 1) / mps) & 1) { 3110 tog ^= 1; 3111 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 3112 } 3113 if (next == NULL) 3114 break; 3115 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 3116 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3117 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 3118 if (len) 3119 curoffs += curlen; 3120 cur = next; 3121 } 3122 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3123 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 3124 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3125 *ep = cur; 3126 epipe->nexttoggle = tog; 3127 3128 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 3129 *sp, *ep, 0, 0); 3130 3131 return (USBD_NORMAL_COMPLETION); 3132 3133 nomem: 3134 /* XXX free chain */ 3135 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3136 return (USBD_NOMEM); 3137 } 3138 3139 Static void 3140 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 3141 ehci_soft_qtd_t *sqtdend) 3142 { 3143 ehci_soft_qtd_t *p; 3144 int i; 3145 3146 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3147 3148 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 3149 sqtd, sqtdend, 0, 0); 3150 3151 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 3152 p = sqtd->nextqtd; 3153 ehci_free_sqtd(sc, sqtd); 3154 } 3155 } 3156 3157 Static ehci_soft_itd_t * 3158 ehci_alloc_itd(ehci_softc_t *sc) 3159 { 3160 struct ehci_soft_itd *itd, *freeitd; 3161 usbd_status err; 3162 int i, offs, frindex, previndex; 3163 usb_dma_t dma; 3164 3165 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3166 3167 mutex_enter(&sc->sc_lock); 3168 3169 /* Find an itd that wasn't freed this frame or last frame. This can 3170 * discard itds that were freed before frindex wrapped around 3171 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3172 * interrupt and fiddling with list when that happens */ 3173 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3174 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3175 3176 freeitd = NULL; 3177 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 3178 if (itd == NULL) 3179 break; 3180 if (itd->slot != frindex && itd->slot != previndex) { 3181 freeitd = itd; 3182 break; 3183 } 3184 } 3185 3186 if (freeitd == NULL) { 3187 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3188 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3189 EHCI_PAGE_SIZE, &dma); 3190 3191 if (err) { 3192 USBHIST_LOG(ehcidebug, 3193 "alloc returned %d", err, 0, 0, 0); 3194 mutex_exit(&sc->sc_lock); 3195 return NULL; 3196 } 3197 3198 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 3199 offs = i * EHCI_ITD_SIZE; 3200 itd = KERNADDR(&dma, offs); 3201 itd->physaddr = DMAADDR(&dma, offs); 3202 itd->dma = dma; 3203 itd->offs = offs; 3204 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3205 } 3206 freeitd = LIST_FIRST(&sc->sc_freeitds); 3207 } 3208 3209 itd = freeitd; 3210 LIST_REMOVE(itd, u.free_list); 3211 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3212 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 3213 sizeof(itd->itd.itd_next), 3214 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3215 3216 itd->u.frame_list.next = NULL; 3217 itd->u.frame_list.prev = NULL; 3218 itd->xfer_next = NULL; 3219 itd->slot = 0; 3220 3221 mutex_exit(&sc->sc_lock); 3222 3223 return itd; 3224 } 3225 3226 Static ehci_soft_sitd_t * 3227 ehci_alloc_sitd(ehci_softc_t *sc) 3228 { 3229 struct ehci_soft_sitd *sitd, *freesitd; 3230 usbd_status err; 3231 int i, offs, frindex, previndex; 3232 usb_dma_t dma; 3233 3234 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3235 3236 mutex_enter(&sc->sc_lock); 3237 3238 /* Find an sitd that wasn't freed this frame or last frame. This can 3239 * discard sitds that were freed before frindex wrapped around 3240 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3241 * interrupt and fiddling with list when that happens */ 3242 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3243 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3244 3245 freesitd = NULL; 3246 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 3247 if (sitd == NULL) 3248 break; 3249 if (sitd->slot != frindex && sitd->slot != previndex) { 3250 freesitd = sitd; 3251 break; 3252 } 3253 } 3254 3255 if (freesitd == NULL) { 3256 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3257 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3258 EHCI_PAGE_SIZE, &dma); 3259 3260 if (err) { 3261 USBHIST_LOG(ehcidebug, 3262 "alloc returned %d", err, 0, 0, 0); 3263 mutex_exit(&sc->sc_lock); 3264 return NULL; 3265 } 3266 3267 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3268 offs = i * EHCI_SITD_SIZE; 3269 sitd = KERNADDR(&dma, offs); 3270 sitd->physaddr = DMAADDR(&dma, offs); 3271 sitd->dma = dma; 3272 sitd->offs = offs; 3273 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3274 } 3275 freesitd = LIST_FIRST(&sc->sc_freesitds); 3276 } 3277 3278 sitd = freesitd; 3279 LIST_REMOVE(sitd, u.free_list); 3280 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3281 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3282 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3283 BUS_DMASYNC_PREREAD); 3284 3285 sitd->u.frame_list.next = NULL; 3286 sitd->u.frame_list.prev = NULL; 3287 sitd->xfer_next = NULL; 3288 sitd->slot = 0; 3289 3290 mutex_exit(&sc->sc_lock); 3291 3292 return sitd; 3293 } 3294 3295 Static void 3296 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3297 { 3298 3299 KASSERT(mutex_owned(&sc->sc_lock)); 3300 3301 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3302 } 3303 3304 Static void 3305 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3306 { 3307 3308 KASSERT(mutex_owned(&sc->sc_lock)); 3309 3310 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3311 } 3312 3313 /****************/ 3314 3315 /* 3316 * Close a reqular pipe. 3317 * Assumes that there are no pending transactions. 3318 */ 3319 Static void 3320 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3321 { 3322 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3323 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3324 ehci_soft_qh_t *sqh = epipe->sqh; 3325 3326 KASSERT(mutex_owned(&sc->sc_lock)); 3327 3328 ehci_rem_qh(sc, sqh, head); 3329 ehci_free_sqh(sc, epipe->sqh); 3330 } 3331 3332 /* 3333 * Abort a device request. 3334 * If this routine is called at splusb() it guarantees that the request 3335 * will be removed from the hardware scheduling and that the callback 3336 * for it will be called with USBD_CANCELLED status. 3337 * It's impossible to guarantee that the requested transfer will not 3338 * have happened since the hardware runs concurrently. 3339 * If the transaction has already happened we rely on the ordinary 3340 * interrupt processing to process it. 3341 * XXX This is most probably wrong. 3342 * XXXMRG this doesn't make sense anymore. 3343 */ 3344 Static void 3345 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3346 { 3347 #define exfer EXFER(xfer) 3348 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3349 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3350 ehci_soft_qh_t *sqh = epipe->sqh; 3351 ehci_soft_qtd_t *sqtd; 3352 ehci_physaddr_t cur; 3353 uint32_t qhstatus; 3354 int hit; 3355 int wake; 3356 3357 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3358 3359 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3360 3361 KASSERT(mutex_owned(&sc->sc_lock)); 3362 ASSERT_SLEEPABLE(); 3363 3364 if (sc->sc_dying) { 3365 /* If we're dying, just do the software part. */ 3366 xfer->ux_status = status; /* make software ignore it */ 3367 callout_stop(&xfer->ux_callout); 3368 usb_transfer_complete(xfer); 3369 return; 3370 } 3371 3372 /* 3373 * If an abort is already in progress then just wait for it to 3374 * complete and return. 3375 */ 3376 if (xfer->ux_hcflags & UXFER_ABORTING) { 3377 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3378 #ifdef DIAGNOSTIC 3379 if (status == USBD_TIMEOUT) 3380 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3381 #endif 3382 /* Override the status which might be USBD_TIMEOUT. */ 3383 xfer->ux_status = status; 3384 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3385 0, 0, 0, 0); 3386 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3387 while (xfer->ux_hcflags & UXFER_ABORTING) 3388 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3389 return; 3390 } 3391 xfer->ux_hcflags |= UXFER_ABORTING; 3392 3393 /* 3394 * Step 1: Make interrupt routine and hardware ignore xfer. 3395 */ 3396 xfer->ux_status = status; /* make software ignore it */ 3397 callout_stop(&xfer->ux_callout); 3398 3399 usb_syncmem(&sqh->dma, 3400 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3401 sizeof(sqh->qh.qh_qtd.qtd_status), 3402 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3403 qhstatus = sqh->qh.qh_qtd.qtd_status; 3404 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3405 usb_syncmem(&sqh->dma, 3406 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3407 sizeof(sqh->qh.qh_qtd.qtd_status), 3408 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3409 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3410 usb_syncmem(&sqtd->dma, 3411 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3412 sizeof(sqtd->qtd.qtd_status), 3413 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3414 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3415 usb_syncmem(&sqtd->dma, 3416 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3417 sizeof(sqtd->qtd.qtd_status), 3418 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3419 if (sqtd == exfer->sqtdend) 3420 break; 3421 } 3422 3423 /* 3424 * Step 2: Wait until we know hardware has finished any possible 3425 * use of the xfer. Also make sure the soft interrupt routine 3426 * has run. 3427 */ 3428 ehci_sync_hc(sc); 3429 sc->sc_softwake = 1; 3430 usb_schedsoftintr(&sc->sc_bus); 3431 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3432 3433 /* 3434 * Step 3: Remove any vestiges of the xfer from the hardware. 3435 * The complication here is that the hardware may have executed 3436 * beyond the xfer we're trying to abort. So as we're scanning 3437 * the TDs of this xfer we check if the hardware points to 3438 * any of them. 3439 */ 3440 3441 usb_syncmem(&sqh->dma, 3442 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3443 sizeof(sqh->qh.qh_curqtd), 3444 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3445 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3446 hit = 0; 3447 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3448 hit |= cur == sqtd->physaddr; 3449 if (sqtd == exfer->sqtdend) 3450 break; 3451 } 3452 sqtd = sqtd->nextqtd; 3453 /* Zap curqtd register if hardware pointed inside the xfer. */ 3454 if (hit && sqtd != NULL) { 3455 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3456 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3457 usb_syncmem(&sqh->dma, 3458 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3459 sizeof(sqh->qh.qh_curqtd), 3460 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3461 sqh->qh.qh_qtd.qtd_status = qhstatus; 3462 usb_syncmem(&sqh->dma, 3463 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3464 sizeof(sqh->qh.qh_qtd.qtd_status), 3465 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3466 } else { 3467 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3468 } 3469 3470 /* 3471 * Step 4: Execute callback. 3472 */ 3473 #ifdef DIAGNOSTIC 3474 exfer->isdone = 1; 3475 #endif 3476 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3477 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3478 usb_transfer_complete(xfer); 3479 if (wake) { 3480 cv_broadcast(&xfer->ux_hccv); 3481 } 3482 3483 KASSERT(mutex_owned(&sc->sc_lock)); 3484 #undef exfer 3485 } 3486 3487 Static void 3488 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3489 { 3490 ehci_isoc_trans_t trans_status; 3491 struct ehci_pipe *epipe; 3492 struct ehci_xfer *exfer; 3493 ehci_softc_t *sc; 3494 struct ehci_soft_itd *itd; 3495 struct ehci_soft_sitd *sitd; 3496 int i, wake; 3497 3498 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3499 3500 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3501 exfer = EXFER(xfer); 3502 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3503 3504 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3505 3506 KASSERT(mutex_owned(&sc->sc_lock)); 3507 3508 if (sc->sc_dying) { 3509 xfer->ux_status = status; 3510 callout_stop(&xfer->ux_callout); 3511 usb_transfer_complete(xfer); 3512 return; 3513 } 3514 3515 if (xfer->ux_hcflags & UXFER_ABORTING) { 3516 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3517 3518 #ifdef DIAGNOSTIC 3519 if (status == USBD_TIMEOUT) 3520 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3521 #endif 3522 3523 xfer->ux_status = status; 3524 USBHIST_LOG(ehcidebug, 3525 "waiting for abort to finish", 0, 0, 0, 0); 3526 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3527 while (xfer->ux_hcflags & UXFER_ABORTING) 3528 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3529 goto done; 3530 } 3531 xfer->ux_hcflags |= UXFER_ABORTING; 3532 3533 xfer->ux_status = status; 3534 callout_stop(&xfer->ux_callout); 3535 3536 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3537 usb_syncmem(&itd->dma, 3538 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3539 sizeof(itd->itd.itd_ctl), 3540 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3541 3542 for (i = 0; i < 8; i++) { 3543 trans_status = le32toh(itd->itd.itd_ctl[i]); 3544 trans_status &= ~EHCI_ITD_ACTIVE; 3545 itd->itd.itd_ctl[i] = htole32(trans_status); 3546 } 3547 3548 usb_syncmem(&itd->dma, 3549 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3550 sizeof(itd->itd.itd_ctl), 3551 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3552 } 3553 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 3554 usb_syncmem(&sitd->dma, 3555 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3556 sizeof(sitd->sitd.sitd_buffer), 3557 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3558 3559 trans_status = le32toh(sitd->sitd.sitd_trans); 3560 trans_status &= ~EHCI_SITD_ACTIVE; 3561 sitd->sitd.sitd_trans = htole32(trans_status); 3562 3563 usb_syncmem(&sitd->dma, 3564 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3565 sizeof(sitd->sitd.sitd_buffer), 3566 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3567 } 3568 3569 sc->sc_softwake = 1; 3570 usb_schedsoftintr(&sc->sc_bus); 3571 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3572 3573 #ifdef DIAGNOSTIC 3574 exfer->isdone = 1; 3575 #endif 3576 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3577 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3578 usb_transfer_complete(xfer); 3579 if (wake) { 3580 cv_broadcast(&xfer->ux_hccv); 3581 } 3582 3583 done: 3584 KASSERT(mutex_owned(&sc->sc_lock)); 3585 return; 3586 } 3587 3588 Static void 3589 ehci_timeout(void *addr) 3590 { 3591 struct ehci_xfer *exfer = addr; 3592 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.ux_pipe; 3593 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3594 3595 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3596 3597 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3598 #ifdef EHCI_DEBUG 3599 if (ehcidebug > 1) 3600 usbd_dump_pipe(exfer->xfer.ux_pipe); 3601 #endif 3602 3603 if (sc->sc_dying) { 3604 mutex_enter(&sc->sc_lock); 3605 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3606 mutex_exit(&sc->sc_lock); 3607 return; 3608 } 3609 3610 /* Execute the abort in a process context. */ 3611 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3612 USB_TASKQ_MPSAFE); 3613 usb_add_task(exfer->xfer.ux_pipe->up_dev, &exfer->abort_task, 3614 USB_TASKQ_HC); 3615 } 3616 3617 Static void 3618 ehci_timeout_task(void *addr) 3619 { 3620 usbd_xfer_handle xfer = addr; 3621 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3622 3623 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3624 3625 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3626 3627 mutex_enter(&sc->sc_lock); 3628 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3629 mutex_exit(&sc->sc_lock); 3630 } 3631 3632 /************************/ 3633 3634 Static usbd_status 3635 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3636 { 3637 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3638 usbd_status err; 3639 3640 /* Insert last in queue. */ 3641 mutex_enter(&sc->sc_lock); 3642 err = usb_insert_transfer(xfer); 3643 mutex_exit(&sc->sc_lock); 3644 if (err) 3645 return (err); 3646 3647 /* Pipe isn't running, start first */ 3648 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 3649 } 3650 3651 Static usbd_status 3652 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3653 { 3654 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3655 usbd_status err; 3656 3657 if (sc->sc_dying) 3658 return (USBD_IOERROR); 3659 3660 #ifdef DIAGNOSTIC 3661 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3662 /* XXX panic */ 3663 printf("ehci_device_ctrl_transfer: not a request\n"); 3664 return (USBD_INVAL); 3665 } 3666 #endif 3667 3668 err = ehci_device_request(xfer); 3669 if (err) { 3670 return (err); 3671 } 3672 3673 if (sc->sc_bus.ub_usepolling) 3674 ehci_waitintr(sc, xfer); 3675 3676 return (USBD_IN_PROGRESS); 3677 } 3678 3679 Static void 3680 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3681 { 3682 struct ehci_xfer *ex = EXFER(xfer); 3683 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3684 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3685 usb_device_request_t *req = &xfer->ux_request; 3686 int len = UGETW(req->wLength); 3687 int rd = req->bmRequestType & UT_READ; 3688 3689 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3690 3691 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3692 3693 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3694 3695 #ifdef DIAGNOSTIC 3696 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3697 panic("ehci_ctrl_done: not a request"); 3698 } 3699 #endif 3700 3701 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3702 ehci_del_intr_list(sc, ex); /* remove from active list */ 3703 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3704 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3705 BUS_DMASYNC_POSTWRITE); 3706 if (len) 3707 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3708 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3709 } 3710 3711 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3712 } 3713 3714 /* Abort a device control request. */ 3715 Static void 3716 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3717 { 3718 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3719 3720 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3721 ehci_abort_xfer(xfer, USBD_CANCELLED); 3722 } 3723 3724 /* Close a device control pipe. */ 3725 Static void 3726 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3727 { 3728 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3729 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3730 3731 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3732 3733 KASSERT(mutex_owned(&sc->sc_lock)); 3734 3735 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3736 3737 ehci_close_pipe(pipe, sc->sc_async_head); 3738 } 3739 3740 Static usbd_status 3741 ehci_device_request(usbd_xfer_handle xfer) 3742 { 3743 #define exfer EXFER(xfer) 3744 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3745 usb_device_request_t *req = &xfer->ux_request; 3746 usbd_device_handle dev = epipe->pipe.up_dev; 3747 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3748 ehci_soft_qtd_t *setup, *stat, *next; 3749 ehci_soft_qh_t *sqh; 3750 int isread; 3751 int len; 3752 usbd_status err; 3753 3754 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3755 3756 isread = req->bmRequestType & UT_READ; 3757 len = UGETW(req->wLength); 3758 3759 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3760 "wValue=0x%04x, wIndex=0x%04x", 3761 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3762 UGETW(req->wIndex)); 3763 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3764 len, dev->ud_addr, 3765 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3766 3767 setup = ehci_alloc_sqtd(sc); 3768 if (setup == NULL) { 3769 err = USBD_NOMEM; 3770 goto bad1; 3771 } 3772 stat = ehci_alloc_sqtd(sc); 3773 if (stat == NULL) { 3774 err = USBD_NOMEM; 3775 goto bad2; 3776 } 3777 3778 mutex_enter(&sc->sc_lock); 3779 3780 sqh = epipe->sqh; 3781 3782 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3783 "address QH %d pipe %d\n", 3784 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3785 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3786 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3787 "MPS QH %d pipe %d\n", 3788 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3789 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3790 3791 /* Set up data transaction */ 3792 if (len != 0) { 3793 ehci_soft_qtd_t *end; 3794 3795 /* Start toggle at 1. */ 3796 epipe->nexttoggle = 1; 3797 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3798 &next, &end); 3799 if (err) 3800 goto bad3; 3801 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3802 end->nextqtd = stat; 3803 end->qtd.qtd_next = end->qtd.qtd_altnext = 3804 htole32(stat->physaddr); 3805 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3806 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3807 } else { 3808 next = stat; 3809 } 3810 3811 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3812 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3813 3814 /* Clear toggle */ 3815 setup->qtd.qtd_status = htole32( 3816 EHCI_QTD_ACTIVE | 3817 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3818 EHCI_QTD_SET_CERR(3) | 3819 EHCI_QTD_SET_TOGGLE(0) | 3820 EHCI_QTD_SET_BYTES(sizeof *req) 3821 ); 3822 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3823 setup->qtd.qtd_buffer_hi[0] = 0; 3824 setup->nextqtd = next; 3825 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3826 setup->xfer = xfer; 3827 setup->len = sizeof *req; 3828 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3829 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3830 3831 stat->qtd.qtd_status = htole32( 3832 EHCI_QTD_ACTIVE | 3833 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3834 EHCI_QTD_SET_CERR(3) | 3835 EHCI_QTD_SET_TOGGLE(1) | 3836 EHCI_QTD_IOC 3837 ); 3838 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3839 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3840 stat->nextqtd = NULL; 3841 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3842 stat->xfer = xfer; 3843 stat->len = 0; 3844 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3845 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3846 3847 #ifdef EHCI_DEBUG 3848 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3849 ehci_dump_sqh(sqh); 3850 ehci_dump_sqtds(setup); 3851 #endif 3852 3853 exfer->sqtdstart = setup; 3854 exfer->sqtdend = stat; 3855 #ifdef DIAGNOSTIC 3856 if (!exfer->isdone) { 3857 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3858 } 3859 exfer->isdone = 0; 3860 #endif 3861 3862 /* Insert qTD in QH list. */ 3863 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3864 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3865 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3866 ehci_timeout, xfer); 3867 } 3868 ehci_add_intr_list(sc, exfer); 3869 xfer->ux_status = USBD_IN_PROGRESS; 3870 mutex_exit(&sc->sc_lock); 3871 3872 #ifdef EHCI_DEBUG 3873 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3874 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3875 // delay(10000); 3876 ehci_dump_regs(sc); 3877 ehci_dump_sqh(sc->sc_async_head); 3878 ehci_dump_sqh(sqh); 3879 ehci_dump_sqtds(setup); 3880 #endif 3881 3882 return (USBD_NORMAL_COMPLETION); 3883 3884 bad3: 3885 mutex_exit(&sc->sc_lock); 3886 ehci_free_sqtd(sc, stat); 3887 bad2: 3888 ehci_free_sqtd(sc, setup); 3889 bad1: 3890 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3891 mutex_enter(&sc->sc_lock); 3892 xfer->ux_status = err; 3893 usb_transfer_complete(xfer); 3894 mutex_exit(&sc->sc_lock); 3895 return (err); 3896 #undef exfer 3897 } 3898 3899 /* 3900 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3901 * qTD status, or miss signalling occasionally under heavy load. If the host 3902 * machine is too fast, we we can miss transaction completion - when we scan 3903 * the active list the transaction still seems to be active. This generally 3904 * exhibits itself as a umass stall that never recovers. 3905 * 3906 * We work around this behaviour by setting up this callback after any softintr 3907 * that completes with transactions still pending, giving us another chance to 3908 * check for completion after the writeback has taken place. 3909 */ 3910 Static void 3911 ehci_intrlist_timeout(void *arg) 3912 { 3913 ehci_softc_t *sc = arg; 3914 3915 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3916 3917 usb_schedsoftintr(&sc->sc_bus); 3918 } 3919 3920 /************************/ 3921 3922 Static usbd_status 3923 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3924 { 3925 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3926 usbd_status err; 3927 3928 /* Insert last in queue. */ 3929 mutex_enter(&sc->sc_lock); 3930 err = usb_insert_transfer(xfer); 3931 mutex_exit(&sc->sc_lock); 3932 if (err) 3933 return (err); 3934 3935 /* Pipe isn't running, start first */ 3936 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 3937 } 3938 3939 Static usbd_status 3940 ehci_device_bulk_start(usbd_xfer_handle xfer) 3941 { 3942 #define exfer EXFER(xfer) 3943 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3944 usbd_device_handle dev = epipe->pipe.up_dev; 3945 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3946 ehci_soft_qtd_t *data, *dataend; 3947 ehci_soft_qh_t *sqh; 3948 usbd_status err; 3949 int len, isread, endpt; 3950 3951 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3952 3953 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3954 xfer, xfer->ux_length, xfer->ux_flags, 0); 3955 3956 if (sc->sc_dying) 3957 return (USBD_IOERROR); 3958 3959 #ifdef DIAGNOSTIC 3960 if (xfer->ux_rqflags & URQ_REQUEST) 3961 panic("ehci_device_bulk_start: a request"); 3962 #endif 3963 3964 mutex_enter(&sc->sc_lock); 3965 3966 len = xfer->ux_length; 3967 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3968 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3969 sqh = epipe->sqh; 3970 3971 epipe->u.bulk.length = len; 3972 3973 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3974 &dataend); 3975 if (err) { 3976 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3977 xfer->ux_status = err; 3978 usb_transfer_complete(xfer); 3979 mutex_exit(&sc->sc_lock); 3980 return (err); 3981 } 3982 3983 #ifdef EHCI_DEBUG 3984 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 3985 ehci_dump_sqh(sqh); 3986 ehci_dump_sqtds(data); 3987 #endif 3988 3989 /* Set up interrupt info. */ 3990 exfer->sqtdstart = data; 3991 exfer->sqtdend = dataend; 3992 #ifdef DIAGNOSTIC 3993 if (!exfer->isdone) { 3994 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3995 } 3996 exfer->isdone = 0; 3997 #endif 3998 3999 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4000 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4001 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4002 ehci_timeout, xfer); 4003 } 4004 ehci_add_intr_list(sc, exfer); 4005 xfer->ux_status = USBD_IN_PROGRESS; 4006 mutex_exit(&sc->sc_lock); 4007 4008 #ifdef EHCI_DEBUG 4009 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4010 // delay(10000); 4011 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4012 ehci_dump_regs(sc); 4013 #if 0 4014 printf("async_head:\n"); 4015 ehci_dump_sqh(sc->sc_async_head); 4016 #endif 4017 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 4018 ehci_dump_sqh(sqh); 4019 ehci_dump_sqtds(data); 4020 #endif 4021 4022 if (sc->sc_bus.ub_usepolling) 4023 ehci_waitintr(sc, xfer); 4024 4025 return (USBD_IN_PROGRESS); 4026 #undef exfer 4027 } 4028 4029 Static void 4030 ehci_device_bulk_abort(usbd_xfer_handle xfer) 4031 { 4032 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4033 4034 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 4035 ehci_abort_xfer(xfer, USBD_CANCELLED); 4036 } 4037 4038 /* 4039 * Close a device bulk pipe. 4040 */ 4041 Static void 4042 ehci_device_bulk_close(usbd_pipe_handle pipe) 4043 { 4044 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 4045 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 4046 4047 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4048 4049 KASSERT(mutex_owned(&sc->sc_lock)); 4050 4051 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 4052 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4053 ehci_close_pipe(pipe, sc->sc_async_head); 4054 } 4055 4056 Static void 4057 ehci_device_bulk_done(usbd_xfer_handle xfer) 4058 { 4059 struct ehci_xfer *ex = EXFER(xfer); 4060 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4061 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4062 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4063 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4064 4065 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4066 4067 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4068 xfer, xfer->ux_actlen, 0, 0); 4069 4070 KASSERT(mutex_owned(&sc->sc_lock)); 4071 4072 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4073 ehci_del_intr_list(sc, ex); /* remove from active list */ 4074 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4075 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4076 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4077 } 4078 4079 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 4080 } 4081 4082 /************************/ 4083 4084 Static usbd_status 4085 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4086 { 4087 struct ehci_soft_islot *isp; 4088 int islot, lev; 4089 4090 /* Find a poll rate that is large enough. */ 4091 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4092 if (EHCI_ILEV_IVAL(lev) <= ival) 4093 break; 4094 4095 /* Pick an interrupt slot at the right level. */ 4096 /* XXX could do better than picking at random */ 4097 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4098 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4099 4100 sqh->islot = islot; 4101 isp = &sc->sc_islots[islot]; 4102 mutex_enter(&sc->sc_lock); 4103 ehci_add_qh(sc, sqh, isp->sqh); 4104 mutex_exit(&sc->sc_lock); 4105 4106 return (USBD_NORMAL_COMPLETION); 4107 } 4108 4109 Static usbd_status 4110 ehci_device_intr_transfer(usbd_xfer_handle xfer) 4111 { 4112 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4113 usbd_status err; 4114 4115 /* Insert last in queue. */ 4116 mutex_enter(&sc->sc_lock); 4117 err = usb_insert_transfer(xfer); 4118 mutex_exit(&sc->sc_lock); 4119 if (err) 4120 return (err); 4121 4122 /* 4123 * Pipe isn't running (otherwise err would be USBD_INPROG), 4124 * so start it first. 4125 */ 4126 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 4127 } 4128 4129 Static usbd_status 4130 ehci_device_intr_start(usbd_xfer_handle xfer) 4131 { 4132 #define exfer EXFER(xfer) 4133 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4134 usbd_device_handle dev = xfer->ux_pipe->up_dev; 4135 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 4136 ehci_soft_qtd_t *data, *dataend; 4137 ehci_soft_qh_t *sqh; 4138 usbd_status err; 4139 int len, isread, endpt; 4140 4141 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4142 4143 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 4144 xfer, xfer->ux_length, xfer->ux_flags, 0); 4145 4146 if (sc->sc_dying) 4147 return (USBD_IOERROR); 4148 4149 #ifdef DIAGNOSTIC 4150 if (xfer->ux_rqflags & URQ_REQUEST) 4151 panic("ehci_device_intr_start: a request"); 4152 #endif 4153 4154 mutex_enter(&sc->sc_lock); 4155 4156 len = xfer->ux_length; 4157 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4158 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4159 sqh = epipe->sqh; 4160 4161 epipe->u.intr.length = len; 4162 4163 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 4164 &dataend); 4165 if (err) { 4166 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4167 xfer->ux_status = err; 4168 usb_transfer_complete(xfer); 4169 mutex_exit(&sc->sc_lock); 4170 return (err); 4171 } 4172 4173 #ifdef EHCI_DEBUG 4174 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 4175 ehci_dump_sqh(sqh); 4176 ehci_dump_sqtds(data); 4177 #endif 4178 4179 /* Set up interrupt info. */ 4180 exfer->sqtdstart = data; 4181 exfer->sqtdend = dataend; 4182 #ifdef DIAGNOSTIC 4183 if (!exfer->isdone) { 4184 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 4185 } 4186 exfer->isdone = 0; 4187 #endif 4188 4189 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4190 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4191 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4192 ehci_timeout, xfer); 4193 } 4194 ehci_add_intr_list(sc, exfer); 4195 xfer->ux_status = USBD_IN_PROGRESS; 4196 mutex_exit(&sc->sc_lock); 4197 4198 #ifdef EHCI_DEBUG 4199 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4200 // delay(10000); 4201 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4202 ehci_dump_regs(sc); 4203 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4204 ehci_dump_sqh(sqh); 4205 ehci_dump_sqtds(data); 4206 #endif 4207 4208 if (sc->sc_bus.ub_usepolling) 4209 ehci_waitintr(sc, xfer); 4210 4211 return (USBD_IN_PROGRESS); 4212 #undef exfer 4213 } 4214 4215 Static void 4216 ehci_device_intr_abort(usbd_xfer_handle xfer) 4217 { 4218 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4219 4220 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4221 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4222 4223 /* 4224 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4225 * async doorbell. That's dependent on the async list, wheras 4226 * intr xfers are periodic, should not use this? 4227 */ 4228 ehci_abort_xfer(xfer, USBD_CANCELLED); 4229 } 4230 4231 Static void 4232 ehci_device_intr_close(usbd_pipe_handle pipe) 4233 { 4234 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 4235 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 4236 struct ehci_soft_islot *isp; 4237 4238 KASSERT(mutex_owned(&sc->sc_lock)); 4239 4240 isp = &sc->sc_islots[epipe->sqh->islot]; 4241 ehci_close_pipe(pipe, isp->sqh); 4242 } 4243 4244 Static void 4245 ehci_device_intr_done(usbd_xfer_handle xfer) 4246 { 4247 #define exfer EXFER(xfer) 4248 struct ehci_xfer *ex = EXFER(xfer); 4249 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4250 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4251 ehci_soft_qtd_t *data, *dataend; 4252 ehci_soft_qh_t *sqh; 4253 usbd_status err; 4254 int len, isread, endpt; 4255 4256 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4257 4258 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4259 xfer, xfer->ux_actlen, 0, 0); 4260 4261 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4262 4263 if (xfer->ux_pipe->up_repeat) { 4264 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4265 4266 len = epipe->u.intr.length; 4267 xfer->ux_length = len; 4268 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4269 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4270 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4271 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4272 sqh = epipe->sqh; 4273 4274 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4275 &data, &dataend); 4276 if (err) { 4277 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4278 xfer->ux_status = err; 4279 return; 4280 } 4281 4282 /* Set up interrupt info. */ 4283 exfer->sqtdstart = data; 4284 exfer->sqtdend = dataend; 4285 #ifdef DIAGNOSTIC 4286 if (!exfer->isdone) { 4287 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4288 exfer, 0, 0, 0); 4289 printf("ehci_device_intr_done: not done, ex=%p\n", 4290 exfer); 4291 } 4292 exfer->isdone = 0; 4293 #endif 4294 4295 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4296 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4297 callout_reset(&xfer->ux_callout, 4298 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4299 } 4300 4301 xfer->ux_status = USBD_IN_PROGRESS; 4302 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4303 ehci_del_intr_list(sc, ex); /* remove from active list */ 4304 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4305 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4306 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4307 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4308 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4309 } 4310 #undef exfer 4311 } 4312 4313 /************************/ 4314 4315 Static usbd_status 4316 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4317 { 4318 usbd_status err; 4319 4320 err = usb_insert_transfer(xfer); 4321 if (err && err != USBD_IN_PROGRESS) 4322 return err; 4323 4324 return ehci_device_fs_isoc_start(xfer); 4325 } 4326 4327 Static usbd_status 4328 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4329 { 4330 struct ehci_pipe *epipe; 4331 usbd_device_handle dev; 4332 ehci_softc_t *sc; 4333 struct ehci_xfer *exfer; 4334 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4335 usb_dma_t *dma_buf; 4336 int i, j, k, frames; 4337 int offs, total_length; 4338 int frindex; 4339 u_int huba, dir; 4340 4341 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4342 4343 start = NULL; 4344 prev = NULL; 4345 sitd = NULL; 4346 total_length = 0; 4347 exfer = (struct ehci_xfer *) xfer; 4348 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4349 dev = xfer->ux_pipe->up_dev; 4350 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4351 4352 /* 4353 * To allow continuous transfers, above we start all transfers 4354 * immediately. However, we're still going to get usbd_start_next call 4355 * this when another xfer completes. So, check if this is already 4356 * in progress or not 4357 */ 4358 4359 if (exfer->sitdstart != NULL) 4360 return USBD_IN_PROGRESS; 4361 4362 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4363 xfer, xfer->ux_length, xfer->ux_flags, 0); 4364 4365 if (sc->sc_dying) 4366 return USBD_IOERROR; 4367 4368 /* 4369 * To avoid complication, don't allow a request right now that'll span 4370 * the entire frame table. To within 4 frames, to allow some leeway 4371 * on either side of where the hc currently is. 4372 */ 4373 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4374 xfer->ux_nframes >= sc->sc_flsize - 4) { 4375 printf("ehci: isoc descriptor requested that spans the entire" 4376 "frametable, too many frames\n"); 4377 return USBD_INVAL; 4378 } 4379 4380 #ifdef DIAGNOSTIC 4381 if (xfer->ux_rqflags & URQ_REQUEST) 4382 panic("ehci_device_fs_isoc_start: request\n"); 4383 4384 if (!exfer->isdone) 4385 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4386 exfer->isdone = 0; 4387 #endif 4388 4389 /* 4390 * Step 1: Allocate and initialize sitds. 4391 */ 4392 4393 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4394 if (i > 16 || i == 0) { 4395 /* Spec page 271 says intervals > 16 are invalid */ 4396 USBHIST_LOG(ehcidebug, "bInverval %d invalid\n", 0, 0, 0, 0); 4397 4398 return USBD_INVAL; 4399 } 4400 4401 frames = xfer->ux_nframes; 4402 4403 if (frames == 0) { 4404 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4405 4406 return USBD_INVAL; 4407 } 4408 4409 dma_buf = &xfer->ux_dmabuf; 4410 offs = 0; 4411 4412 for (i = 0; i < frames; i++) { 4413 sitd = ehci_alloc_sitd(sc); 4414 4415 if (prev) 4416 prev->xfer_next = sitd; 4417 else 4418 start = sitd; 4419 4420 #ifdef DIAGNOSTIC 4421 if (xfer->ux_frlengths[i] > 0x3ff) { 4422 printf("ehci: invalid frame length\n"); 4423 xfer->ux_frlengths[i] = 0x3ff; 4424 } 4425 #endif 4426 4427 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4428 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4429 4430 /* Set page0 index and offset. */ 4431 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4432 4433 total_length += xfer->ux_frlengths[i]; 4434 offs += xfer->ux_frlengths[i]; 4435 4436 sitd->sitd.sitd_buffer[1] = 4437 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4438 4439 huba = dev->ud_myhsport->up_parent->ud_addr; 4440 4441 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4442 // Set hub address to 0 if embedded TT is used. 4443 if (huba == sc->sc_addr) 4444 huba = 0; 4445 } 4446 */ 4447 4448 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4449 dir = UE_GET_DIR(k) ? 1 : 0; 4450 sitd->sitd.sitd_endp = 4451 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4452 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4453 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4454 EHCI_SITD_SET_HUBA(huba) | 4455 EHCI_SITD_SET_DIR(dir)); 4456 4457 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4458 4459 /* XXX */ 4460 u_char sa, sb; 4461 u_int temp, tlen; 4462 sa = 0; 4463 4464 if (dir == 0) { /* OUT */ 4465 temp = 0; 4466 tlen = xfer->ux_frlengths[i]; 4467 if (tlen <= 188) { 4468 temp |= 1; /* T-count = 1, TP = ALL */ 4469 tlen = 1; 4470 } else { 4471 tlen += 187; 4472 tlen /= 188; 4473 temp |= tlen; /* T-count = [1..6] */ 4474 temp |= 8; /* TP = Begin */ 4475 } 4476 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4477 4478 tlen += sa; 4479 4480 if (tlen >= 8) { 4481 sb = 0; 4482 } else { 4483 sb = (1 << tlen); 4484 } 4485 4486 sa = (1 << sa); 4487 sa = (sb - sa) & 0x3F; 4488 sb = 0; 4489 } else { 4490 sb = (-(4 << sa)) & 0xFE; 4491 sa = (1 << sa) & 0x3F; 4492 sa = 0x01; 4493 sb = 0xfc; 4494 } 4495 4496 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4497 EHCI_SITD_SET_CMASK(sb)); 4498 4499 prev = sitd; 4500 } /* End of frame */ 4501 4502 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4503 4504 stop = sitd; 4505 stop->xfer_next = NULL; 4506 exfer->isoc_len = total_length; 4507 4508 usb_syncmem(&exfer->xfer.ux_dmabuf, 0, total_length, 4509 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4510 4511 /* 4512 * Part 2: Transfer descriptors have now been set up, now they must 4513 * be scheduled into the periodic frame list. Erk. Not wanting to 4514 * complicate matters, transfer is denied if the transfer spans 4515 * more than the period frame list. 4516 */ 4517 4518 mutex_enter(&sc->sc_lock); 4519 4520 /* Start inserting frames */ 4521 if (epipe->u.isoc.cur_xfers > 0) { 4522 frindex = epipe->u.isoc.next_frame; 4523 } else { 4524 frindex = EOREAD4(sc, EHCI_FRINDEX); 4525 frindex = frindex >> 3; /* Erase microframe index */ 4526 frindex += 2; 4527 } 4528 4529 if (frindex >= sc->sc_flsize) 4530 frindex &= (sc->sc_flsize - 1); 4531 4532 /* Whats the frame interval? */ 4533 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4534 4535 sitd = start; 4536 for (j = 0; j < frames; j++) { 4537 if (sitd == NULL) 4538 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4539 4540 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4541 if (sitd->sitd.sitd_next == 0) 4542 /* FIXME: frindex table gets initialized to NULL 4543 * or EHCI_NULL? */ 4544 sitd->sitd.sitd_next = EHCI_NULL; 4545 4546 usb_syncmem(&sitd->dma, 4547 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4548 sizeof(ehci_sitd_t), 4549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4550 4551 sc->sc_flist[frindex] = 4552 htole32(EHCI_LINK_SITD | sitd->physaddr); 4553 4554 usb_syncmem(&sc->sc_fldma, 4555 sizeof(ehci_link_t) * frindex, 4556 sizeof(ehci_link_t), 4557 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4558 4559 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4560 sc->sc_softsitds[frindex] = sitd; 4561 if (sitd->u.frame_list.next != NULL) 4562 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4563 sitd->slot = frindex; 4564 sitd->u.frame_list.prev = NULL; 4565 4566 frindex += i; 4567 if (frindex >= sc->sc_flsize) 4568 frindex -= sc->sc_flsize; 4569 4570 sitd = sitd->xfer_next; 4571 } 4572 4573 epipe->u.isoc.cur_xfers++; 4574 epipe->u.isoc.next_frame = frindex; 4575 4576 exfer->sitdstart = start; 4577 exfer->sitdend = stop; 4578 exfer->sqtdstart = NULL; 4579 exfer->sqtdstart = NULL; 4580 4581 ehci_add_intr_list(sc, exfer); 4582 xfer->ux_status = USBD_IN_PROGRESS; 4583 xfer->ux_done = 0; 4584 4585 mutex_exit(&sc->sc_lock); 4586 4587 if (sc->sc_bus.ub_usepolling) { 4588 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4589 ehci_waitintr(sc, xfer); 4590 } 4591 4592 return USBD_IN_PROGRESS; 4593 } 4594 4595 Static void 4596 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4597 { 4598 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4599 4600 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4601 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4602 } 4603 4604 Static void 4605 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4606 { 4607 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4608 4609 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4610 } 4611 4612 Static void 4613 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4614 { 4615 struct ehci_xfer *exfer; 4616 ehci_softc_t *sc; 4617 struct ehci_pipe *epipe; 4618 4619 exfer = EXFER(xfer); 4620 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4621 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4622 4623 KASSERT(mutex_owned(&sc->sc_lock)); 4624 4625 epipe->u.isoc.cur_xfers--; 4626 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4627 ehci_del_intr_list(sc, exfer); 4628 ehci_rem_free_sitd_chain(sc, exfer); 4629 } 4630 4631 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4632 BUS_DMASYNC_POSTREAD); 4633 } 4634 Static usbd_status 4635 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4636 { 4637 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4638 usbd_status err; 4639 4640 mutex_enter(&sc->sc_lock); 4641 err = usb_insert_transfer(xfer); 4642 mutex_exit(&sc->sc_lock); 4643 if (err && err != USBD_IN_PROGRESS) 4644 return err; 4645 4646 return ehci_device_isoc_start(xfer); 4647 } 4648 4649 Static usbd_status 4650 ehci_device_isoc_start(usbd_xfer_handle xfer) 4651 { 4652 struct ehci_pipe *epipe; 4653 ehci_softc_t *sc; 4654 struct ehci_xfer *exfer; 4655 ehci_soft_itd_t *itd, *prev, *start, *stop; 4656 usb_dma_t *dma_buf; 4657 int i, j, k, frames, uframes, ufrperframe; 4658 int trans_count, offs, total_length; 4659 int frindex; 4660 4661 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4662 4663 start = NULL; 4664 prev = NULL; 4665 itd = NULL; 4666 trans_count = 0; 4667 total_length = 0; 4668 exfer = (struct ehci_xfer *) xfer; 4669 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4670 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4671 4672 /* 4673 * To allow continuous transfers, above we start all transfers 4674 * immediately. However, we're still going to get usbd_start_next call 4675 * this when another xfer completes. So, check if this is already 4676 * in progress or not 4677 */ 4678 4679 if (exfer->itdstart != NULL) 4680 return USBD_IN_PROGRESS; 4681 4682 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4683 xfer, xfer->ux_length, xfer->ux_flags, 0); 4684 4685 if (sc->sc_dying) 4686 return USBD_IOERROR; 4687 4688 /* 4689 * To avoid complication, don't allow a request right now that'll span 4690 * the entire frame table. To within 4 frames, to allow some leeway 4691 * on either side of where the hc currently is. 4692 */ 4693 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4694 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4695 USBHIST_LOG(ehcidebug, 4696 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4697 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4698 return USBD_INVAL; 4699 } 4700 4701 #ifdef DIAGNOSTIC 4702 if (xfer->ux_rqflags & URQ_REQUEST) 4703 panic("ehci_device_isoc_start: request\n"); 4704 4705 if (!exfer->isdone) { 4706 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4707 0, 0, 0); 4708 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4709 } 4710 exfer->isdone = 0; 4711 #endif 4712 4713 /* 4714 * Step 1: Allocate and initialize itds, how many do we need? 4715 * One per transfer if interval >= 8 microframes, fewer if we use 4716 * multiple microframes per frame. 4717 */ 4718 4719 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4720 if (i > 16 || i == 0) { 4721 /* Spec page 271 says intervals > 16 are invalid */ 4722 USBHIST_LOG(ehcidebug, "bInvertal %d invalid", i, 0, 0, 0); 4723 return USBD_INVAL; 4724 } 4725 4726 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4727 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4728 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4729 4730 if (frames == 0) { 4731 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4732 return USBD_INVAL; 4733 } 4734 4735 dma_buf = &xfer->ux_dmabuf; 4736 offs = 0; 4737 4738 for (i = 0; i < frames; i++) { 4739 int froffs = offs; 4740 itd = ehci_alloc_itd(sc); 4741 4742 if (prev != NULL) { 4743 prev->itd.itd_next = 4744 htole32(itd->physaddr | EHCI_LINK_ITD); 4745 usb_syncmem(&itd->dma, 4746 itd->offs + offsetof(ehci_itd_t, itd_next), 4747 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4748 4749 prev->xfer_next = itd; 4750 } else { 4751 start = itd; 4752 } 4753 4754 /* 4755 * Step 1.5, initialize uframes 4756 */ 4757 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4758 /* Calculate which page in the list this starts in */ 4759 int addr = DMAADDR(dma_buf, froffs); 4760 addr = EHCI_PAGE_OFFSET(addr); 4761 addr += (offs - froffs); 4762 addr = EHCI_PAGE(addr); 4763 addr /= EHCI_PAGE_SIZE; 4764 4765 /* This gets the initial offset into the first page, 4766 * looks how far further along the current uframe 4767 * offset is. Works out how many pages that is. 4768 */ 4769 4770 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4771 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4772 EHCI_ITD_SET_PG(addr) | 4773 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4774 4775 total_length += xfer->ux_frlengths[trans_count]; 4776 offs += xfer->ux_frlengths[trans_count]; 4777 trans_count++; 4778 4779 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4780 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4781 break; 4782 } 4783 } 4784 4785 /* Step 1.75, set buffer pointers. To simplify matters, all 4786 * pointers are filled out for the next 7 hardware pages in 4787 * the dma block, so no need to worry what pages to cover 4788 * and what to not. 4789 */ 4790 4791 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4792 /* 4793 * Don't try to lookup a page that's past the end 4794 * of buffer 4795 */ 4796 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4797 if (page_offs >= dma_buf->udma_block->size) 4798 break; 4799 4800 unsigned long long page = DMAADDR(dma_buf, page_offs); 4801 page = EHCI_PAGE(page); 4802 itd->itd.itd_bufr[j] = 4803 htole32(EHCI_ITD_SET_BPTR(page)); 4804 itd->itd.itd_bufr_hi[j] = 4805 htole32(page >> 32); 4806 } 4807 4808 /* 4809 * Other special values 4810 */ 4811 4812 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4813 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4814 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4815 4816 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4817 ? 1 : 0; 4818 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4819 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4820 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4821 4822 /* FIXME: handle invalid trans */ 4823 itd->itd.itd_bufr[2] |= 4824 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4825 4826 usb_syncmem(&itd->dma, 4827 itd->offs + offsetof(ehci_itd_t, itd_next), 4828 sizeof(ehci_itd_t), 4829 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4830 4831 prev = itd; 4832 } /* End of frame */ 4833 4834 stop = itd; 4835 stop->xfer_next = NULL; 4836 exfer->isoc_len = total_length; 4837 4838 usb_syncmem(&exfer->xfer.ux_dmabuf, 0, total_length, 4839 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4840 4841 /* 4842 * Part 2: Transfer descriptors have now been set up, now they must 4843 * be scheduled into the period frame list. Erk. Not wanting to 4844 * complicate matters, transfer is denied if the transfer spans 4845 * more than the period frame list. 4846 */ 4847 4848 mutex_enter(&sc->sc_lock); 4849 4850 /* Start inserting frames */ 4851 if (epipe->u.isoc.cur_xfers > 0) { 4852 frindex = epipe->u.isoc.next_frame; 4853 } else { 4854 frindex = EOREAD4(sc, EHCI_FRINDEX); 4855 frindex = frindex >> 3; /* Erase microframe index */ 4856 frindex += 2; 4857 } 4858 4859 if (frindex >= sc->sc_flsize) 4860 frindex &= (sc->sc_flsize - 1); 4861 4862 /* What's the frame interval? */ 4863 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4864 if (i / USB_UFRAMES_PER_FRAME == 0) 4865 i = 1; 4866 else 4867 i /= USB_UFRAMES_PER_FRAME; 4868 4869 itd = start; 4870 for (j = 0; j < frames; j++) { 4871 if (itd == NULL) 4872 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4873 4874 itd->itd.itd_next = sc->sc_flist[frindex]; 4875 if (itd->itd.itd_next == 0) 4876 /* FIXME: frindex table gets initialized to NULL 4877 * or EHCI_NULL? */ 4878 itd->itd.itd_next = EHCI_NULL; 4879 4880 usb_syncmem(&itd->dma, 4881 itd->offs + offsetof(ehci_itd_t, itd_next), 4882 sizeof(itd->itd.itd_next), 4883 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4884 4885 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4886 4887 usb_syncmem(&sc->sc_fldma, 4888 sizeof(ehci_link_t) * frindex, 4889 sizeof(ehci_link_t), 4890 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4891 4892 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4893 sc->sc_softitds[frindex] = itd; 4894 if (itd->u.frame_list.next != NULL) 4895 itd->u.frame_list.next->u.frame_list.prev = itd; 4896 itd->slot = frindex; 4897 itd->u.frame_list.prev = NULL; 4898 4899 frindex += i; 4900 if (frindex >= sc->sc_flsize) 4901 frindex -= sc->sc_flsize; 4902 4903 itd = itd->xfer_next; 4904 } 4905 4906 epipe->u.isoc.cur_xfers++; 4907 epipe->u.isoc.next_frame = frindex; 4908 4909 exfer->itdstart = start; 4910 exfer->itdend = stop; 4911 exfer->sqtdstart = NULL; 4912 exfer->sqtdend = NULL; 4913 4914 ehci_add_intr_list(sc, exfer); 4915 xfer->ux_status = USBD_IN_PROGRESS; 4916 xfer->ux_done = 0; 4917 mutex_exit(&sc->sc_lock); 4918 4919 if (sc->sc_bus.ub_usepolling) { 4920 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4921 ehci_waitintr(sc, xfer); 4922 } 4923 4924 return USBD_IN_PROGRESS; 4925 } 4926 4927 Static void 4928 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4929 { 4930 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4931 4932 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4933 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4934 } 4935 4936 Static void 4937 ehci_device_isoc_close(usbd_pipe_handle pipe) 4938 { 4939 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4940 4941 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4942 } 4943 4944 Static void 4945 ehci_device_isoc_done(usbd_xfer_handle xfer) 4946 { 4947 struct ehci_xfer *exfer; 4948 ehci_softc_t *sc; 4949 struct ehci_pipe *epipe; 4950 4951 exfer = EXFER(xfer); 4952 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4953 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4954 4955 KASSERT(mutex_owned(&sc->sc_lock)); 4956 4957 epipe->u.isoc.cur_xfers--; 4958 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4959 ehci_del_intr_list(sc, exfer); 4960 ehci_rem_free_itd_chain(sc, exfer); 4961 } 4962 4963 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4964 BUS_DMASYNC_POSTREAD); 4965 4966 } 4967
Indexes created Wed Oct 01 19:09:53 GMT 2025