ehci.c revision 1.234.2.80
1 /* $NetBSD: ehci.c,v 1.234.2.80 2016/02/06 08:47:06 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.80 2016/02/06 08:47:06 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 /* Control pipe */ 136 struct { 137 usb_dma_t reqdma; 138 } ctrl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Iso pipe */ 144 struct { 145 u_int next_frame; 146 u_int cur_xfers; 147 } isoc; 148 }; 149 }; 150 151 Static usbd_status ehci_open(struct usbd_pipe *); 152 Static void ehci_poll(struct usbd_bus *); 153 Static void ehci_softintr(void *); 154 Static int ehci_intr1(ehci_softc_t *); 155 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 156 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 157 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 158 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 159 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 160 Static void ehci_idone(struct ehci_xfer *); 161 Static void ehci_timeout(void *); 162 Static void ehci_timeout_task(void *); 163 Static void ehci_intrlist_timeout(void *); 164 Static void ehci_doorbell(void *); 165 Static void ehci_pcd(void *); 166 167 Static struct usbd_xfer * 168 ehci_allocx(struct usbd_bus *, unsigned int); 169 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 170 171 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 172 Static int ehci_roothub_ctrl(struct usbd_bus *, 173 usb_device_request_t *, void *, int); 174 175 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 176 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 177 Static void ehci_root_intr_abort(struct usbd_xfer *); 178 Static void ehci_root_intr_close(struct usbd_pipe *); 179 Static void ehci_root_intr_done(struct usbd_xfer *); 180 181 Static int ehci_device_ctrl_init(struct usbd_xfer *); 182 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 183 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 185 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 186 Static void ehci_device_ctrl_close(struct usbd_pipe *); 187 Static void ehci_device_ctrl_done(struct usbd_xfer *); 188 189 Static int ehci_device_bulk_init(struct usbd_xfer *); 190 Static void ehci_device_bulk_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 193 Static void ehci_device_bulk_abort(struct usbd_xfer *); 194 Static void ehci_device_bulk_close(struct usbd_pipe *); 195 Static void ehci_device_bulk_done(struct usbd_xfer *); 196 197 Static int ehci_device_intr_init(struct usbd_xfer *); 198 Static void ehci_device_intr_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 201 Static void ehci_device_intr_abort(struct usbd_xfer *); 202 Static void ehci_device_intr_close(struct usbd_pipe *); 203 Static void ehci_device_intr_done(struct usbd_xfer *); 204 205 Static int ehci_device_isoc_init(struct usbd_xfer *); 206 Static void ehci_device_isoc_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 209 Static void ehci_device_isoc_abort(struct usbd_xfer *); 210 Static void ehci_device_isoc_close(struct usbd_pipe *); 211 Static void ehci_device_isoc_done(struct usbd_xfer *); 212 213 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 216 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 217 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 220 221 Static void ehci_device_clear_toggle(struct usbd_pipe *); 222 Static void ehci_noop(struct usbd_pipe *); 223 224 Static void ehci_disown(ehci_softc_t *, int, int); 225 226 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 227 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 228 229 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 230 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 231 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 232 int, int, ehci_soft_qtd_t **, ehci_soft_qtd_t **); 233 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 234 235 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 236 int, int, int *, ehci_soft_qtd_t **); 237 238 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 239 Static ehci_soft_sitd_t * 240 ehci_alloc_sitd(ehci_softc_t *); 241 242 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 243 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 244 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 245 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 246 247 static inline void 248 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 249 { 250 251 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 252 } 253 254 static inline void 255 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 259 } 260 261 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 262 263 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 264 int); 265 266 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 267 ehci_soft_qh_t *); 268 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 269 ehci_soft_qh_t *); 270 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 271 Static void ehci_sync_hc(ehci_softc_t *); 272 273 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 274 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 275 276 #ifdef EHCI_DEBUG 277 Static ehci_softc_t *theehci; 278 void ehci_dump(void); 279 #endif 280 281 #ifdef EHCI_DEBUG 282 Static void ehci_dump_regs(ehci_softc_t *); 283 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 284 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 285 Static void ehci_dump_qtd(ehci_qtd_t *); 286 Static void ehci_dump_sqh(ehci_soft_qh_t *); 287 Static void ehci_dump_sitd(struct ehci_soft_itd *); 288 Static void ehci_dump_itds(ehci_soft_itd_t *); 289 Static void ehci_dump_itd(struct ehci_soft_itd *); 290 Static void ehci_dump_exfer(struct ehci_xfer *); 291 #endif 292 293 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 294 295 #define ehci_add_intr_list(sc, ex) \ 296 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 297 #define ehci_del_intr_list(sc, ex) \ 298 do { \ 299 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 300 (ex)->ex_next.tqe_prev = NULL; \ 301 } while (0) 302 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 303 304 Static const struct usbd_bus_methods ehci_bus_methods = { 305 .ubm_open = ehci_open, 306 .ubm_softint = ehci_softintr, 307 .ubm_dopoll = ehci_poll, 308 .ubm_allocx = ehci_allocx, 309 .ubm_freex = ehci_freex, 310 .ubm_getlock = ehci_get_lock, 311 .ubm_rhctrl = ehci_roothub_ctrl, 312 }; 313 314 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 315 .upm_transfer = ehci_root_intr_transfer, 316 .upm_start = ehci_root_intr_start, 317 .upm_abort = ehci_root_intr_abort, 318 .upm_close = ehci_root_intr_close, 319 .upm_cleartoggle = ehci_noop, 320 .upm_done = ehci_root_intr_done, 321 }; 322 323 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 324 .upm_init = ehci_device_ctrl_init, 325 .upm_fini = ehci_device_ctrl_fini, 326 .upm_transfer = ehci_device_ctrl_transfer, 327 .upm_start = ehci_device_ctrl_start, 328 .upm_abort = ehci_device_ctrl_abort, 329 .upm_close = ehci_device_ctrl_close, 330 .upm_cleartoggle = ehci_noop, 331 .upm_done = ehci_device_ctrl_done, 332 }; 333 334 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 335 .upm_init = ehci_device_intr_init, 336 .upm_fini = ehci_device_intr_fini, 337 .upm_transfer = ehci_device_intr_transfer, 338 .upm_start = ehci_device_intr_start, 339 .upm_abort = ehci_device_intr_abort, 340 .upm_close = ehci_device_intr_close, 341 .upm_cleartoggle = ehci_device_clear_toggle, 342 .upm_done = ehci_device_intr_done, 343 }; 344 345 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 346 .upm_init = ehci_device_bulk_init, 347 .upm_fini = ehci_device_bulk_fini, 348 .upm_transfer = ehci_device_bulk_transfer, 349 .upm_start = ehci_device_bulk_start, 350 .upm_abort = ehci_device_bulk_abort, 351 .upm_close = ehci_device_bulk_close, 352 .upm_cleartoggle = ehci_device_clear_toggle, 353 .upm_done = ehci_device_bulk_done, 354 }; 355 356 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 357 .upm_init = ehci_device_isoc_init, 358 .upm_fini = ehci_device_isoc_fini, 359 .upm_transfer = ehci_device_isoc_transfer, 360 .upm_start = ehci_device_isoc_start, 361 .upm_abort = ehci_device_isoc_abort, 362 .upm_close = ehci_device_isoc_close, 363 .upm_cleartoggle = ehci_noop, 364 .upm_done = ehci_device_isoc_done, 365 }; 366 367 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 368 .upm_init = ehci_device_fs_isoc_init, 369 .upm_fini = ehci_device_fs_isoc_fini, 370 .upm_transfer = ehci_device_fs_isoc_transfer, 371 .upm_start = ehci_device_fs_isoc_start, 372 .upm_abort = ehci_device_fs_isoc_abort, 373 .upm_close = ehci_device_fs_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_fs_isoc_done, 376 }; 377 378 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 379 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 380 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 381 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 382 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 383 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 384 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 385 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 386 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 387 }; 388 389 int 390 ehci_init(ehci_softc_t *sc) 391 { 392 uint32_t vers, sparams, cparams, hcr; 393 u_int i; 394 usbd_status err; 395 ehci_soft_qh_t *sqh; 396 u_int ncomp; 397 398 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 399 #ifdef EHCI_DEBUG 400 theehci = sc; 401 #endif 402 403 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 404 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 405 cv_init(&sc->sc_softwake_cv, "ehciab"); 406 cv_init(&sc->sc_doorbell, "ehcidi"); 407 408 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 409 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 410 411 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 412 ehci_doorbell, sc); 413 KASSERT(sc->sc_doorbell_si != NULL); 414 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 415 ehci_pcd, sc); 416 KASSERT(sc->sc_pcd_si != NULL); 417 418 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 419 420 vers = EREAD2(sc, EHCI_HCIVERSION); 421 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 422 vers >> 8, vers & 0xff); 423 424 sparams = EREAD4(sc, EHCI_HCSPARAMS); 425 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 426 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 427 ncomp = EHCI_HCS_N_CC(sparams); 428 if (ncomp != sc->sc_ncomp) { 429 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 430 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 431 #if NOHCI == 0 || NUHCI == 0 432 aprint_error("%s: ohci or uhci probably not configured\n", 433 device_xname(sc->sc_dev)); 434 #endif 435 if (ncomp < sc->sc_ncomp) 436 sc->sc_ncomp = ncomp; 437 } 438 if (sc->sc_ncomp > 0) { 439 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 440 aprint_normal("%s: companion controller%s, %d port%s each:", 441 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 442 EHCI_HCS_N_PCC(sparams), 443 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 444 for (i = 0; i < sc->sc_ncomp; i++) 445 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 446 aprint_normal("\n"); 447 } 448 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 449 cparams = EREAD4(sc, EHCI_HCCPARAMS); 450 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 451 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 452 453 if (EHCI_HCC_64BIT(cparams)) { 454 /* MUST clear segment register if 64 bit capable. */ 455 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 456 } 457 458 sc->sc_bus.ub_revision = USBREV_2_0; 459 sc->sc_bus.ub_usedma = true; 460 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 461 462 /* Reset the controller */ 463 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 464 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 465 usb_delay_ms(&sc->sc_bus, 1); 466 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 467 for (i = 0; i < 100; i++) { 468 usb_delay_ms(&sc->sc_bus, 1); 469 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 470 if (!hcr) 471 break; 472 } 473 if (hcr) { 474 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 475 return EIO; 476 } 477 if (sc->sc_vendor_init) 478 sc->sc_vendor_init(sc); 479 480 /* XXX need proper intr scheduling */ 481 sc->sc_rand = 96; 482 483 /* frame list size at default, read back what we got and use that */ 484 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 485 case 0: sc->sc_flsize = 1024; break; 486 case 1: sc->sc_flsize = 512; break; 487 case 2: sc->sc_flsize = 256; break; 488 case 3: return EIO; 489 } 490 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 491 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 492 if (err) 493 return err; 494 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 495 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 496 497 for (i = 0; i < sc->sc_flsize; i++) { 498 sc->sc_flist[i] = EHCI_NULL; 499 } 500 501 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 502 503 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 504 KM_SLEEP); 505 if (sc->sc_softitds == NULL) 506 return ENOMEM; 507 LIST_INIT(&sc->sc_freeitds); 508 LIST_INIT(&sc->sc_freesitds); 509 TAILQ_INIT(&sc->sc_intrhead); 510 511 /* Set up the bus struct. */ 512 sc->sc_bus.ub_methods = &ehci_bus_methods; 513 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 514 515 sc->sc_eintrs = EHCI_NORMAL_INTRS; 516 517 /* 518 * Allocate the interrupt dummy QHs. These are arranged to give poll 519 * intervals that are powers of 2 times 1ms. 520 */ 521 for (i = 0; i < EHCI_INTRQHS; i++) { 522 sqh = ehci_alloc_sqh(sc); 523 if (sqh == NULL) { 524 err = ENOMEM; 525 goto bad1; 526 } 527 sc->sc_islots[i].sqh = sqh; 528 } 529 for (i = 0; i < EHCI_INTRQHS; i++) { 530 sqh = sc->sc_islots[i].sqh; 531 if (i == 0) { 532 /* The last (1ms) QH terminates. */ 533 sqh->qh.qh_link = EHCI_NULL; 534 sqh->next = NULL; 535 } else { 536 /* Otherwise the next QH has half the poll interval */ 537 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 538 sqh->qh.qh_link = htole32(sqh->next->physaddr | 539 EHCI_LINK_QH); 540 } 541 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 542 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 543 sqh->qh.qh_curqtd = EHCI_NULL; 544 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 545 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 546 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 547 sqh->sqtd = NULL; 548 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 } 551 /* Point the frame list at the last level (128ms). */ 552 for (i = 0; i < sc->sc_flsize; i++) { 553 int j; 554 555 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 556 revbits[i & (EHCI_MAX_POLLRATE-1)]; 557 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 558 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 559 i)].sqh->physaddr); 560 } 561 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 562 BUS_DMASYNC_PREWRITE); 563 564 /* Allocate dummy QH that starts the async list. */ 565 sqh = ehci_alloc_sqh(sc); 566 if (sqh == NULL) { 567 err = ENOMEM; 568 goto bad1; 569 } 570 /* Fill the QH */ 571 sqh->qh.qh_endp = 572 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 573 sqh->qh.qh_link = 574 htole32(sqh->physaddr | EHCI_LINK_QH); 575 sqh->qh.qh_curqtd = EHCI_NULL; 576 sqh->next = NULL; 577 /* Fill the overlay qTD */ 578 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 579 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 580 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 581 sqh->sqtd = NULL; 582 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 584 #ifdef EHCI_DEBUG 585 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 586 ehci_dump_sqh(sqh); 587 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 588 #endif 589 590 /* Point to async list */ 591 sc->sc_async_head = sqh; 592 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 593 594 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 595 596 /* Turn on controller */ 597 EOWRITE4(sc, EHCI_USBCMD, 598 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 599 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 600 EHCI_CMD_ASE | 601 EHCI_CMD_PSE | 602 EHCI_CMD_RS); 603 604 /* Take over port ownership */ 605 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 606 607 for (i = 0; i < 100; i++) { 608 usb_delay_ms(&sc->sc_bus, 1); 609 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 610 if (!hcr) 611 break; 612 } 613 if (hcr) { 614 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 615 return EIO; 616 } 617 618 /* Enable interrupts */ 619 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 620 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 621 622 return 0; 623 624 #if 0 625 bad2: 626 ehci_free_sqh(sc, sc->sc_async_head); 627 #endif 628 bad1: 629 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 630 return err; 631 } 632 633 int 634 ehci_intr(void *v) 635 { 636 ehci_softc_t *sc = v; 637 int ret = 0; 638 639 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 640 641 if (sc == NULL) 642 return 0; 643 644 mutex_spin_enter(&sc->sc_intr_lock); 645 646 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 647 goto done; 648 649 /* If we get an interrupt while polling, then just ignore it. */ 650 if (sc->sc_bus.ub_usepolling) { 651 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 652 653 if (intrs) 654 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 655 USBHIST_LOGN(ehcidebug, 16, 656 "ignored interrupt while polling", 0, 0, 0, 0); 657 goto done; 658 } 659 660 ret = ehci_intr1(sc); 661 662 done: 663 mutex_spin_exit(&sc->sc_intr_lock); 664 return ret; 665 } 666 667 Static int 668 ehci_intr1(ehci_softc_t *sc) 669 { 670 uint32_t intrs, eintrs; 671 672 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 673 674 /* In case the interrupt occurs before initialization has completed. */ 675 if (sc == NULL) { 676 #ifdef DIAGNOSTIC 677 printf("ehci_intr1: sc == NULL\n"); 678 #endif 679 return 0; 680 } 681 682 KASSERT(mutex_owned(&sc->sc_intr_lock)); 683 684 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 685 if (!intrs) 686 return 0; 687 688 eintrs = intrs & sc->sc_eintrs; 689 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 690 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 691 if (!eintrs) 692 return 0; 693 694 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 695 if (eintrs & EHCI_STS_IAA) { 696 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 697 kpreempt_disable(); 698 KASSERT(sc->sc_doorbell_si != NULL); 699 softint_schedule(sc->sc_doorbell_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_IAA; 702 } 703 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 704 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 705 eintrs & EHCI_STS_INT ? 1 : 0, 706 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 707 usb_schedsoftintr(&sc->sc_bus); 708 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 709 } 710 if (eintrs & EHCI_STS_HSE) { 711 printf("%s: unrecoverable error, controller halted\n", 712 device_xname(sc->sc_dev)); 713 /* XXX what else */ 714 } 715 if (eintrs & EHCI_STS_PCD) { 716 kpreempt_disable(); 717 KASSERT(sc->sc_pcd_si != NULL); 718 softint_schedule(sc->sc_pcd_si); 719 kpreempt_enable(); 720 eintrs &= ~EHCI_STS_PCD; 721 } 722 723 if (eintrs != 0) { 724 /* Block unprocessed interrupts. */ 725 sc->sc_eintrs &= ~eintrs; 726 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 727 printf("%s: blocking intrs 0x%x\n", 728 device_xname(sc->sc_dev), eintrs); 729 } 730 731 return 1; 732 } 733 734 Static void 735 ehci_doorbell(void *addr) 736 { 737 ehci_softc_t *sc = addr; 738 739 mutex_enter(&sc->sc_lock); 740 cv_broadcast(&sc->sc_doorbell); 741 mutex_exit(&sc->sc_lock); 742 } 743 744 Static void 745 ehci_pcd(void *addr) 746 { 747 ehci_softc_t *sc = addr; 748 struct usbd_xfer *xfer; 749 u_char *p; 750 int i, m; 751 752 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 753 754 mutex_enter(&sc->sc_lock); 755 xfer = sc->sc_intrxfer; 756 757 if (xfer == NULL) { 758 /* Just ignore the change. */ 759 goto done; 760 } 761 762 p = xfer->ux_buf; 763 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 764 memset(p, 0, xfer->ux_length); 765 for (i = 1; i <= m; i++) { 766 /* Pick out CHANGE bits from the status reg. */ 767 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 768 p[i/8] |= 1 << (i%8); 769 if (i % 8 == 7) 770 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 771 p[i/8], 0, 0); 772 } 773 xfer->ux_actlen = xfer->ux_length; 774 xfer->ux_status = USBD_NORMAL_COMPLETION; 775 776 usb_transfer_complete(xfer); 777 778 done: 779 mutex_exit(&sc->sc_lock); 780 } 781 782 Static void 783 ehci_softintr(void *v) 784 { 785 struct usbd_bus *bus = v; 786 ehci_softc_t *sc = EHCI_BUS2SC(bus); 787 struct ehci_xfer *ex, *nextex; 788 789 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 790 791 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 792 793 /* 794 * The only explanation I can think of for why EHCI is as brain dead 795 * as UHCI interrupt-wise is that Intel was involved in both. 796 * An interrupt just tells us that something is done, we have no 797 * clue what, so we need to scan through all active transfers. :-( 798 */ 799 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 800 nextex = TAILQ_NEXT(ex, ex_next); 801 ehci_check_intr(sc, ex); 802 } 803 804 /* Schedule a callout to catch any dropped transactions. */ 805 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 806 !TAILQ_EMPTY(&sc->sc_intrhead)) 807 callout_reset(&sc->sc_tmo_intrlist, 808 hz, ehci_intrlist_timeout, sc); 809 810 if (sc->sc_softwake) { 811 sc->sc_softwake = 0; 812 cv_broadcast(&sc->sc_softwake_cv); 813 } 814 } 815 816 /* Check for an interrupt. */ 817 Static void 818 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 819 { 820 821 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 822 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 823 824 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 825 826 switch (ex->ex_type) { 827 case EX_CTRL: 828 case EX_BULK: 829 case EX_INTR: 830 ehci_check_qh_intr(sc, ex); 831 break; 832 case EX_ISOC: 833 ehci_check_itd_intr(sc, ex); 834 break; 835 case EX_FS_ISOC: 836 ehci_check_sitd_intr(sc, ex); 837 break; 838 default: 839 KASSERT(false); 840 } 841 842 return; 843 } 844 845 Static void 846 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 847 { 848 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 849 uint32_t status; 850 851 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 852 853 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 854 855 if (ex->ex_type == EX_CTRL) { 856 fsqtd = ex->ex_setup; 857 lsqtd = ex->ex_status; 858 } else { 859 fsqtd = ex->ex_sqtdstart; 860 lsqtd = ex->ex_sqtdend; 861 } 862 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 863 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 864 865 /* 866 * If the last TD is still active we need to check whether there 867 * is an error somewhere in the middle, or whether there was a 868 * short packet (SPD and not ACTIVE). 869 */ 870 usb_syncmem(&lsqtd->dma, 871 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 872 sizeof(lsqtd->qtd.qtd_status), 873 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 874 status = le32toh(lsqtd->qtd.qtd_status); 875 usb_syncmem(&lsqtd->dma, 876 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 877 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 878 if (status & EHCI_QTD_ACTIVE) { 879 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 880 881 /* last qTD has already been checked */ 882 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 883 usb_syncmem(&sqtd->dma, 884 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 885 sizeof(sqtd->qtd.qtd_status), 886 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 887 status = le32toh(sqtd->qtd.qtd_status); 888 usb_syncmem(&sqtd->dma, 889 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 890 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 891 /* If there's an active QTD the xfer isn't done. */ 892 if (status & EHCI_QTD_ACTIVE) 893 break; 894 /* Any kind of error makes the xfer done. */ 895 if (status & EHCI_QTD_HALTED) 896 goto done; 897 /* Handle short packets */ 898 if (EHCI_QTD_GET_BYTES(status) != 0) { 899 /* 900 * If we get here for a control transfer then 901 * we need to let the hardware complete the 902 * status phase. That is, we're not done 903 * quite yet. 904 * 905 * Otherwise, we're done. 906 */ 907 if (ex->ex_type == EX_CTRL) { 908 break; 909 } 910 goto done; 911 } 912 } 913 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 914 ex, ex->ex_sqtdstart, 0, 0); 915 #ifdef EHCI_DEBUG 916 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 917 0, 0); 918 ehci_dump_sqtds(ex->ex_sqtdstart); 919 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 920 0); 921 #endif 922 return; 923 } 924 done: 925 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 926 callout_stop(&ex->ex_xfer.ux_callout); 927 ehci_idone(ex); 928 } 929 930 Static void 931 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 932 { 933 ehci_soft_itd_t *itd; 934 int i; 935 936 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 937 938 KASSERT(mutex_owned(&sc->sc_lock)); 939 940 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 941 return; 942 943 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 944 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 945 946 itd = ex->ex_itdend; 947 948 /* 949 * check no active transfers in last itd, meaning we're finished 950 */ 951 952 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 953 sizeof(itd->itd.itd_ctl), 954 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 955 956 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 957 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 958 break; 959 } 960 961 if (i == EHCI_ITD_NUFRAMES) { 962 goto done; /* All 8 descriptors inactive, it's done */ 963 } 964 965 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 966 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 967 968 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 969 ex->ex_itdstart, 0, 0); 970 return; 971 done: 972 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 973 callout_stop(&ex->ex_xfer.ux_callout); 974 ehci_idone(ex); 975 } 976 977 void 978 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 979 { 980 ehci_soft_sitd_t *sitd; 981 982 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 983 984 KASSERT(mutex_owned(&sc->sc_lock)); 985 986 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 987 return; 988 989 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 990 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 991 992 sitd = ex->ex_sitdend; 993 994 /* 995 * check no active transfers in last sitd, meaning we're finished 996 */ 997 998 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 999 sizeof(sitd->sitd.sitd_trans), 1000 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1001 1002 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1003 1004 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1005 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1006 1007 if (active) 1008 return; 1009 1010 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1011 callout_stop(&(ex->ex_xfer.ux_callout)); 1012 ehci_idone(ex); 1013 } 1014 1015 1016 Static void 1017 ehci_idone(struct ehci_xfer *ex) 1018 { 1019 struct usbd_xfer *xfer = &ex->ex_xfer; 1020 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1021 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1022 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1023 uint32_t status = 0, nstatus = 0; 1024 int actlen = 0; 1025 1026 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1027 1028 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1029 1030 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1031 1032 if (xfer->ux_status == USBD_CANCELLED || 1033 xfer->ux_status == USBD_TIMEOUT) { 1034 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1035 return; 1036 } 1037 1038 #ifdef DIAGNOSTIC 1039 #ifdef EHCI_DEBUG 1040 if (ex->ex_isdone) { 1041 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1042 ehci_dump_exfer(ex); 1043 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1044 } 1045 #endif 1046 KASSERT(!ex->ex_isdone); 1047 ex->ex_isdone = true; 1048 #endif 1049 1050 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1051 1052 /* The transfer is done, compute actual length and status. */ 1053 if (ex->ex_type == EX_ISOC) { 1054 /* HS isoc transfer */ 1055 1056 struct ehci_soft_itd *itd; 1057 int i, nframes, len, uframes; 1058 1059 nframes = 0; 1060 1061 #ifdef EHCI_DEBUG 1062 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1063 ehci_dump_itds(ex->ex_itdstart); 1064 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1065 #endif 1066 1067 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1068 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1069 1070 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1071 usb_syncmem(&itd->dma, 1072 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1073 sizeof(itd->itd.itd_ctl), 1074 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1075 1076 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1077 /* 1078 * XXX - driver didn't fill in the frame full 1079 * of uframes. This leads to scheduling 1080 * inefficiencies, but working around 1081 * this doubles complexity of tracking 1082 * an xfer. 1083 */ 1084 if (nframes >= xfer->ux_nframes) 1085 break; 1086 1087 status = le32toh(itd->itd.itd_ctl[i]); 1088 len = EHCI_ITD_GET_LEN(status); 1089 if (EHCI_ITD_GET_STATUS(status) != 0) 1090 len = 0; /*No valid data on error*/ 1091 1092 xfer->ux_frlengths[nframes++] = len; 1093 actlen += len; 1094 } 1095 usb_syncmem(&itd->dma, 1096 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1097 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1098 1099 if (nframes >= xfer->ux_nframes) 1100 break; 1101 } 1102 1103 xfer->ux_actlen = actlen; 1104 xfer->ux_status = USBD_NORMAL_COMPLETION; 1105 goto end; 1106 } else if (ex->ex_type == EX_FS_ISOC) { 1107 /* FS isoc transfer */ 1108 struct ehci_soft_sitd *sitd; 1109 int nframes, len; 1110 1111 nframes = 0; 1112 1113 for (sitd = ex->ex_sitdstart; sitd != NULL; 1114 sitd = sitd->xfer_next) { 1115 usb_syncmem(&sitd->dma, 1116 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1117 sizeof(sitd->sitd.sitd_trans), 1118 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1119 1120 /* 1121 * XXX - driver didn't fill in the frame full 1122 * of uframes. This leads to scheduling 1123 * inefficiencies, but working around 1124 * this doubles complexity of tracking 1125 * an xfer. 1126 */ 1127 if (nframes >= xfer->ux_nframes) 1128 break; 1129 1130 status = le32toh(sitd->sitd.sitd_trans); 1131 usb_syncmem(&sitd->dma, 1132 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1133 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1134 1135 len = EHCI_SITD_GET_LEN(status); 1136 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1137 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1138 /* No valid data on error */ 1139 len = xfer->ux_frlengths[nframes]; 1140 } 1141 1142 /* 1143 * frlengths[i]: # of bytes to send 1144 * len: # of bytes host didn't send 1145 */ 1146 xfer->ux_frlengths[nframes] -= len; 1147 /* frlengths[i]: # of bytes host sent */ 1148 actlen += xfer->ux_frlengths[nframes++]; 1149 1150 if (nframes >= xfer->ux_nframes) 1151 break; 1152 } 1153 1154 xfer->ux_actlen = actlen; 1155 xfer->ux_status = USBD_NORMAL_COMPLETION; 1156 goto end; 1157 } 1158 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1159 ex->ex_type == EX_BULK); 1160 1161 /* Continue processing xfers using queue heads */ 1162 if (ex->ex_type == EX_CTRL) { 1163 fsqtd = ex->ex_setup; 1164 lsqtd = ex->ex_status; 1165 } else { 1166 fsqtd = ex->ex_sqtdstart; 1167 lsqtd = ex->ex_sqtdend; 1168 } 1169 #ifdef EHCI_DEBUG 1170 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1171 ehci_dump_sqtds(fsqtd); 1172 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1173 #endif 1174 1175 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1176 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1177 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1178 nstatus = le32toh(sqtd->qtd.qtd_status); 1179 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1180 BUS_DMASYNC_PREREAD); 1181 if (nstatus & EHCI_QTD_ACTIVE) 1182 break; 1183 1184 status = nstatus; 1185 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1186 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1187 } 1188 1189 /* 1190 * If there are left over TDs we need to update the toggle. 1191 * The default pipe doesn't need it since control transfers 1192 * start the toggle at 0 every time. 1193 * For a short transfer we need to update the toggle for the missing 1194 * packets within the qTD. 1195 */ 1196 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1197 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1198 USBHIST_LOG(ehcidebug, 1199 "toggle update status=0x%08x nstatus=0x%08x", 1200 status, nstatus, 0, 0); 1201 #if 0 1202 ehci_dump_sqh(epipe->sqh); 1203 ehci_dump_sqtds(ex->ex_sqtdstart); 1204 #endif 1205 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1206 } 1207 1208 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1209 actlen, status, 0); 1210 xfer->ux_actlen = actlen; 1211 if (status & EHCI_QTD_HALTED) { 1212 #ifdef EHCI_DEBUG 1213 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1214 xfer->ux_pipe->up_dev->ud_addr, 1215 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1216 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1217 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1218 0, 0); 1219 USBHIST_LOG(ehcidebug, 1220 "active =%d halted=%d buferr=%d babble=%d", 1221 status & EHCI_QTD_ACTIVE ? 1 : 0, 1222 status & EHCI_QTD_HALTED ? 1 : 0, 1223 status & EHCI_QTD_BUFERR ? 1 : 0, 1224 status & EHCI_QTD_BABBLE ? 1 : 0); 1225 1226 USBHIST_LOG(ehcidebug, 1227 "xacterr=%d missed=%d split =%d ping =%d", 1228 status & EHCI_QTD_XACTERR ? 1 : 0, 1229 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1230 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1231 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1232 1233 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1234 ehci_dump_sqh(epipe->sqh); 1235 ehci_dump_sqtds(ex->ex_sqtdstart); 1236 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1237 #endif 1238 /* low&full speed has an extra error flag */ 1239 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1240 EHCI_QH_SPEED_HIGH) 1241 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1242 else 1243 status &= EHCI_QTD_STATERRS; 1244 if (status == 0) /* no other errors means a stall */ { 1245 xfer->ux_status = USBD_STALLED; 1246 } else { 1247 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1248 } 1249 /* XXX need to reset TT on missed microframe */ 1250 if (status & EHCI_QTD_MISSEDMICRO) { 1251 printf("%s: missed microframe, TT reset not " 1252 "implemented, hub might be inoperational\n", 1253 device_xname(sc->sc_dev)); 1254 } 1255 } else { 1256 xfer->ux_status = USBD_NORMAL_COMPLETION; 1257 } 1258 1259 end: 1260 /* 1261 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1262 * during this call, before methods->done is called: dma sync required 1263 * beforehand? 1264 */ 1265 usb_transfer_complete(xfer); 1266 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1267 } 1268 1269 /* 1270 * Wait here until controller claims to have an interrupt. 1271 * Then call ehci_intr and return. Use timeout to avoid waiting 1272 * too long. 1273 */ 1274 Static void 1275 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1276 { 1277 int timo; 1278 uint32_t intrs; 1279 1280 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1281 1282 xfer->ux_status = USBD_IN_PROGRESS; 1283 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1284 usb_delay_ms(&sc->sc_bus, 1); 1285 if (sc->sc_dying) 1286 break; 1287 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1288 sc->sc_eintrs; 1289 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1290 #ifdef EHCI_DEBUG 1291 if (ehcidebug >= 15) 1292 ehci_dump_regs(sc); 1293 #endif 1294 if (intrs) { 1295 mutex_spin_enter(&sc->sc_intr_lock); 1296 ehci_intr1(sc); 1297 mutex_spin_exit(&sc->sc_intr_lock); 1298 if (xfer->ux_status != USBD_IN_PROGRESS) 1299 return; 1300 } 1301 } 1302 1303 /* Timeout */ 1304 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1305 xfer->ux_status = USBD_TIMEOUT; 1306 mutex_enter(&sc->sc_lock); 1307 usb_transfer_complete(xfer); 1308 mutex_exit(&sc->sc_lock); 1309 } 1310 1311 Static void 1312 ehci_poll(struct usbd_bus *bus) 1313 { 1314 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1315 1316 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1317 1318 #ifdef EHCI_DEBUG 1319 static int last; 1320 int new; 1321 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1322 if (new != last) { 1323 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1324 last = new; 1325 } 1326 #endif 1327 1328 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1329 mutex_spin_enter(&sc->sc_intr_lock); 1330 ehci_intr1(sc); 1331 mutex_spin_exit(&sc->sc_intr_lock); 1332 } 1333 } 1334 1335 void 1336 ehci_childdet(device_t self, device_t child) 1337 { 1338 struct ehci_softc *sc = device_private(self); 1339 1340 KASSERT(sc->sc_child == child); 1341 sc->sc_child = NULL; 1342 } 1343 1344 int 1345 ehci_detach(struct ehci_softc *sc, int flags) 1346 { 1347 int rv = 0; 1348 1349 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1350 1351 if (sc->sc_child != NULL) 1352 rv = config_detach(sc->sc_child, flags); 1353 1354 if (rv != 0) 1355 return rv; 1356 1357 callout_halt(&sc->sc_tmo_intrlist, NULL); 1358 callout_destroy(&sc->sc_tmo_intrlist); 1359 1360 /* XXX free other data structures XXX */ 1361 if (sc->sc_softitds) 1362 kmem_free(sc->sc_softitds, 1363 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1364 cv_destroy(&sc->sc_doorbell); 1365 cv_destroy(&sc->sc_softwake_cv); 1366 1367 #if 0 1368 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1369 1370 softint_disestablish(sc->sc_doorbell_si); 1371 softint_disestablish(sc->sc_pcd_si); 1372 1373 mutex_destroy(&sc->sc_lock); 1374 mutex_destroy(&sc->sc_intr_lock); 1375 #endif 1376 1377 pool_cache_destroy(sc->sc_xferpool); 1378 1379 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1380 1381 return rv; 1382 } 1383 1384 1385 int 1386 ehci_activate(device_t self, enum devact act) 1387 { 1388 struct ehci_softc *sc = device_private(self); 1389 1390 switch (act) { 1391 case DVACT_DEACTIVATE: 1392 sc->sc_dying = 1; 1393 return 0; 1394 default: 1395 return EOPNOTSUPP; 1396 } 1397 } 1398 1399 /* 1400 * Handle suspend/resume. 1401 * 1402 * We need to switch to polling mode here, because this routine is 1403 * called from an interrupt context. This is all right since we 1404 * are almost suspended anyway. 1405 * 1406 * Note that this power handler isn't to be registered directly; the 1407 * bus glue needs to call out to it. 1408 */ 1409 bool 1410 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1411 { 1412 ehci_softc_t *sc = device_private(dv); 1413 int i; 1414 uint32_t cmd, hcr; 1415 1416 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1417 1418 mutex_spin_enter(&sc->sc_intr_lock); 1419 sc->sc_bus.ub_usepolling++; 1420 mutex_spin_exit(&sc->sc_intr_lock); 1421 1422 for (i = 1; i <= sc->sc_noport; i++) { 1423 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1424 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1425 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1426 } 1427 1428 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1429 1430 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1431 EOWRITE4(sc, EHCI_USBCMD, cmd); 1432 1433 for (i = 0; i < 100; i++) { 1434 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1435 if (hcr == 0) 1436 break; 1437 1438 usb_delay_ms(&sc->sc_bus, 1); 1439 } 1440 if (hcr != 0) 1441 printf("%s: reset timeout\n", device_xname(dv)); 1442 1443 cmd &= ~EHCI_CMD_RS; 1444 EOWRITE4(sc, EHCI_USBCMD, cmd); 1445 1446 for (i = 0; i < 100; i++) { 1447 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1448 if (hcr == EHCI_STS_HCH) 1449 break; 1450 1451 usb_delay_ms(&sc->sc_bus, 1); 1452 } 1453 if (hcr != EHCI_STS_HCH) 1454 printf("%s: config timeout\n", device_xname(dv)); 1455 1456 mutex_spin_enter(&sc->sc_intr_lock); 1457 sc->sc_bus.ub_usepolling--; 1458 mutex_spin_exit(&sc->sc_intr_lock); 1459 1460 return true; 1461 } 1462 1463 bool 1464 ehci_resume(device_t dv, const pmf_qual_t *qual) 1465 { 1466 ehci_softc_t *sc = device_private(dv); 1467 int i; 1468 uint32_t cmd, hcr; 1469 1470 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1471 1472 /* restore things in case the bios sucks */ 1473 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1474 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1475 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1476 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1477 1478 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1479 1480 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1481 1482 hcr = 0; 1483 for (i = 1; i <= sc->sc_noport; i++) { 1484 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1485 if ((cmd & EHCI_PS_PO) == 0 && 1486 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1487 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1488 hcr = 1; 1489 } 1490 } 1491 1492 if (hcr) { 1493 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1494 1495 for (i = 1; i <= sc->sc_noport; i++) { 1496 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1497 if ((cmd & EHCI_PS_PO) == 0 && 1498 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1499 EOWRITE4(sc, EHCI_PORTSC(i), 1500 cmd & ~EHCI_PS_FPR); 1501 } 1502 } 1503 1504 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1505 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1506 1507 for (i = 0; i < 100; i++) { 1508 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1509 if (hcr != EHCI_STS_HCH) 1510 break; 1511 1512 usb_delay_ms(&sc->sc_bus, 1); 1513 } 1514 if (hcr == EHCI_STS_HCH) 1515 printf("%s: config timeout\n", device_xname(dv)); 1516 1517 return true; 1518 } 1519 1520 /* 1521 * Shut down the controller when the system is going down. 1522 */ 1523 bool 1524 ehci_shutdown(device_t self, int flags) 1525 { 1526 ehci_softc_t *sc = device_private(self); 1527 1528 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1529 1530 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1531 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1532 return true; 1533 } 1534 1535 Static struct usbd_xfer * 1536 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1537 { 1538 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1539 struct usbd_xfer *xfer; 1540 1541 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1542 if (xfer != NULL) { 1543 memset(xfer, 0, sizeof(struct ehci_xfer)); 1544 #ifdef DIAGNOSTIC 1545 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1546 ex->ex_isdone = true; 1547 xfer->ux_state = XFER_BUSY; 1548 #endif 1549 } 1550 return xfer; 1551 } 1552 1553 Static void 1554 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1555 { 1556 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1557 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1558 1559 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1560 xfer->ux_state); 1561 KASSERT(ex->ex_isdone); 1562 1563 #ifdef DIAGNOSTIC 1564 xfer->ux_state = XFER_FREE; 1565 #endif 1566 1567 pool_cache_put(sc->sc_xferpool, xfer); 1568 } 1569 1570 Static void 1571 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1572 { 1573 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1574 1575 *lock = &sc->sc_lock; 1576 } 1577 1578 Static void 1579 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1580 { 1581 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1582 1583 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1584 1585 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1586 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1587 #ifdef EHCI_DEBUG 1588 if (ehcidebug) 1589 usbd_dump_pipe(pipe); 1590 #endif 1591 epipe->nexttoggle = 0; 1592 } 1593 1594 Static void 1595 ehci_noop(struct usbd_pipe *pipe) 1596 { 1597 } 1598 1599 #ifdef EHCI_DEBUG 1600 /* 1601 * Unused function - this is meant to be called from a kernel 1602 * debugger. 1603 */ 1604 void 1605 ehci_dump(void) 1606 { 1607 ehci_softc_t *sc = theehci; 1608 int i; 1609 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1610 EOREAD4(sc, EHCI_USBCMD), 1611 EOREAD4(sc, EHCI_USBSTS), 1612 EOREAD4(sc, EHCI_USBINTR)); 1613 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1614 EOREAD4(sc, EHCI_FRINDEX), 1615 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1616 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1617 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1618 for (i = 1; i <= sc->sc_noport; i++) 1619 printf("port %d status=0x%08x\n", i, 1620 EOREAD4(sc, EHCI_PORTSC(i))); 1621 } 1622 1623 Static void 1624 ehci_dump_regs(ehci_softc_t *sc) 1625 { 1626 int i; 1627 1628 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1629 1630 USBHIST_LOG(ehcidebug, 1631 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1632 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1633 EOREAD4(sc, EHCI_USBINTR), 0); 1634 USBHIST_LOG(ehcidebug, 1635 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1636 "async = 0x%08x", 1637 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1638 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1639 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1640 for (i = 1; i <= sc->sc_noport; i += 2) { 1641 if (i == sc->sc_noport) { 1642 USBHIST_LOG(ehcidebug, 1643 "port %d status = 0x%08x", i, 1644 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1645 } else { 1646 USBHIST_LOG(ehcidebug, 1647 "port %d status = 0x%08x port %d status = 0x%08x", 1648 i, EOREAD4(sc, EHCI_PORTSC(i)), 1649 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1650 } 1651 } 1652 } 1653 1654 #define ehci_dump_link(link, type) do { \ 1655 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1656 link, \ 1657 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1658 if (type) { \ 1659 USBHIST_LOG(ehcidebug, \ 1660 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1661 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1662 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1663 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1664 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1665 } \ 1666 } while(0) 1667 1668 Static void 1669 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1670 { 1671 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1672 int i; 1673 uint32_t stop = 0; 1674 1675 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1676 ehci_dump_sqtd(sqtd); 1677 usb_syncmem(&sqtd->dma, 1678 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1679 sizeof(sqtd->qtd), 1680 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1681 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1682 usb_syncmem(&sqtd->dma, 1683 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1684 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1685 } 1686 if (!stop) 1687 USBHIST_LOG(ehcidebug, 1688 "dump aborted, too many TDs", 0, 0, 0, 0); 1689 } 1690 1691 Static void 1692 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1693 { 1694 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1695 1696 usb_syncmem(&sqtd->dma, sqtd->offs, 1697 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1698 1699 USBHIST_LOGN(ehcidebug, 10, 1700 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1701 ehci_dump_qtd(&sqtd->qtd); 1702 1703 usb_syncmem(&sqtd->dma, sqtd->offs, 1704 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1705 } 1706 1707 Static void 1708 ehci_dump_qtd(ehci_qtd_t *qtd) 1709 { 1710 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1711 uint32_t s = le32toh(qtd->qtd_status); 1712 1713 USBHIST_LOGN(ehcidebug, 10, 1714 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1715 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1716 USBHIST_LOGN(ehcidebug, 10, 1717 " toggle = %d ioc = %d bytes = %#x " 1718 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1719 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1720 USBHIST_LOGN(ehcidebug, 10, 1721 " cerr = %d pid = %d stat = %x", 1722 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1723 0); 1724 USBHIST_LOGN(ehcidebug, 10, 1725 "active =%d halted=%d buferr=%d babble=%d", 1726 s & EHCI_QTD_ACTIVE ? 1 : 0, 1727 s & EHCI_QTD_HALTED ? 1 : 0, 1728 s & EHCI_QTD_BUFERR ? 1 : 0, 1729 s & EHCI_QTD_BABBLE ? 1 : 0); 1730 USBHIST_LOGN(ehcidebug, 10, 1731 "xacterr=%d missed=%d split =%d ping =%d", 1732 s & EHCI_QTD_XACTERR ? 1 : 0, 1733 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1734 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1735 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1736 USBHIST_LOGN(ehcidebug, 10, 1737 "buffer[0] = %#x buffer[1] = %#x " 1738 "buffer[2] = %#x buffer[3] = %#x", 1739 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1740 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1741 USBHIST_LOGN(ehcidebug, 10, 1742 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1743 } 1744 1745 Static void 1746 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1747 { 1748 ehci_qh_t *qh = &sqh->qh; 1749 ehci_link_t link; 1750 uint32_t endp, endphub; 1751 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1752 1753 usb_syncmem(&sqh->dma, sqh->offs, 1754 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1755 1756 USBHIST_LOGN(ehcidebug, 10, 1757 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1758 link = le32toh(qh->qh_link); 1759 ehci_dump_link(link, true); 1760 1761 endp = le32toh(qh->qh_endp); 1762 USBHIST_LOGN(ehcidebug, 10, 1763 " endp = %#x", endp, 0, 0, 0); 1764 USBHIST_LOGN(ehcidebug, 10, 1765 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1766 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1767 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1768 USBHIST_LOGN(ehcidebug, 10, 1769 " dtc = %d hrecl = %d", 1770 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1771 USBHIST_LOGN(ehcidebug, 10, 1772 " ctl = %d nrl = %d mpl = %#x(%d)", 1773 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1774 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1775 1776 endphub = le32toh(qh->qh_endphub); 1777 USBHIST_LOGN(ehcidebug, 10, 1778 " endphub = %#x", endphub, 0, 0, 0); 1779 USBHIST_LOGN(ehcidebug, 10, 1780 " smask = 0x%02x cmask = 0x%02x", 1781 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1782 USBHIST_LOGN(ehcidebug, 10, 1783 " huba = 0x%02x port = %d mult = %d", 1784 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1785 EHCI_QH_GET_MULT(endphub), 0); 1786 1787 link = le32toh(qh->qh_curqtd); 1788 ehci_dump_link(link, false); 1789 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1790 ehci_dump_qtd(&qh->qh_qtd); 1791 1792 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1793 BUS_DMASYNC_PREREAD); 1794 } 1795 1796 Static void 1797 ehci_dump_itds(ehci_soft_itd_t *itd) 1798 { 1799 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1800 int i; 1801 uint32_t stop = 0; 1802 1803 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1804 ehci_dump_itd(itd); 1805 usb_syncmem(&itd->dma, 1806 itd->offs + offsetof(ehci_itd_t, itd_next), 1807 sizeof(itd->itd), 1808 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1809 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1810 usb_syncmem(&itd->dma, 1811 itd->offs + offsetof(ehci_itd_t, itd_next), 1812 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1813 } 1814 if (!stop) 1815 USBHIST_LOG(ehcidebug, "dump aborted, too many TDs", 0, 0, 0, 0); 1816 } 1817 1818 Static void 1819 ehci_dump_itd(struct ehci_soft_itd *itd) 1820 { 1821 ehci_isoc_trans_t t; 1822 ehci_isoc_bufr_ptr_t b, b2, b3; 1823 int i; 1824 1825 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1826 1827 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1828 0, 0); 1829 1830 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1831 t = le32toh(itd->itd.itd_ctl[i]); 1832 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1833 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1834 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1835 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1836 EHCI_ITD_GET_OFFS(t), 0); 1837 } 1838 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1839 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1840 USBHIST_LOG(ehcidebug, " %x", 1841 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1842 1843 b = le32toh(itd->itd.itd_bufr[0]); 1844 b2 = le32toh(itd->itd.itd_bufr[1]); 1845 b3 = le32toh(itd->itd.itd_bufr[2]); 1846 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1847 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1848 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1849 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1850 } 1851 1852 Static void 1853 ehci_dump_sitd(struct ehci_soft_itd *itd) 1854 { 1855 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1856 1857 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1858 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1859 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1860 itd->xfer_next, itd->physaddr, itd->slot, 0); 1861 } 1862 1863 Static void 1864 ehci_dump_exfer(struct ehci_xfer *ex) 1865 { 1866 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1867 1868 USBHIST_LOG(ehcidebug, "ex = %p type %d isdone", ex, ex->ex_type, 1869 ex->ex_isdone, 0); 1870 1871 switch (ex->ex_type) { 1872 case EX_CTRL: 1873 USBHIST_LOG(ehcidebug, " setup = %p data = %p status = %p", 1874 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1875 break; 1876 case EX_BULK: 1877 case EX_INTR: 1878 USBHIST_LOG(ehcidebug, " qtdstart = %p qtdend = %p", 1879 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1880 break; 1881 case EX_ISOC: 1882 USBHIST_LOG(ehcidebug, " itdstart = %p itdend = %p", 1883 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1884 break; 1885 case EX_FS_ISOC: 1886 USBHIST_LOG(ehcidebug, " sitdstart = %p sitdend = %p", 1887 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1888 break; 1889 default: 1890 USBHIST_LOG(ehcidebug, " unknown type", 0, 0, 0, 0); 1891 } 1892 } 1893 #endif 1894 1895 Static usbd_status 1896 ehci_open(struct usbd_pipe *pipe) 1897 { 1898 struct usbd_device *dev = pipe->up_dev; 1899 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1900 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1901 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1902 uint8_t addr = dev->ud_addr; 1903 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1904 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1905 ehci_soft_qh_t *sqh; 1906 usbd_status err; 1907 int ival, speed, naks; 1908 int hshubaddr, hshubport; 1909 1910 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1911 1912 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1913 pipe, addr, ed->bEndpointAddress, rhaddr); 1914 1915 if (dev->ud_myhsport) { 1916 /* 1917 * When directly attached FS/LS device while doing embedded 1918 * transaction translations and we are the hub, set the hub 1919 * address to 0 (us). 1920 */ 1921 if (!(sc->sc_flags & EHCIF_ETTF) 1922 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1923 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1924 } else { 1925 hshubaddr = 0; 1926 } 1927 hshubport = dev->ud_myhsport->up_portno; 1928 } else { 1929 hshubaddr = 0; 1930 hshubport = 0; 1931 } 1932 1933 if (sc->sc_dying) 1934 return USBD_IOERROR; 1935 1936 /* toggle state needed for bulk endpoints */ 1937 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1938 1939 if (addr == rhaddr) { 1940 switch (ed->bEndpointAddress) { 1941 case USB_CONTROL_ENDPOINT: 1942 pipe->up_methods = &roothub_ctrl_methods; 1943 break; 1944 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1945 pipe->up_methods = &ehci_root_intr_methods; 1946 break; 1947 default: 1948 USBHIST_LOG(ehcidebug, 1949 "bad bEndpointAddress 0x%02x", 1950 ed->bEndpointAddress, 0, 0, 0); 1951 return USBD_INVAL; 1952 } 1953 return USBD_NORMAL_COMPLETION; 1954 } 1955 1956 /* XXX All this stuff is only valid for async. */ 1957 switch (dev->ud_speed) { 1958 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1959 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1960 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1961 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1962 } 1963 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1964 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1965 hshubaddr, hshubport, 0, 0); 1966 return USBD_INVAL; 1967 } 1968 1969 /* 1970 * For interrupt transfer, nak throttling must be disabled, but for 1971 * the other transfer type, nak throttling should be enabled from the 1972 * viewpoint that avoids the memory thrashing. 1973 */ 1974 naks = (xfertype == UE_INTERRUPT) ? 0 1975 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1976 1977 /* Allocate sqh for everything, save isoc xfers */ 1978 if (xfertype != UE_ISOCHRONOUS) { 1979 sqh = ehci_alloc_sqh(sc); 1980 if (sqh == NULL) 1981 return USBD_NOMEM; 1982 /* qh_link filled when the QH is added */ 1983 sqh->qh.qh_endp = htole32( 1984 EHCI_QH_SET_ADDR(addr) | 1985 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1986 EHCI_QH_SET_EPS(speed) | 1987 EHCI_QH_DTC | 1988 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1989 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1990 EHCI_QH_CTL : 0) | 1991 EHCI_QH_SET_NRL(naks) 1992 ); 1993 sqh->qh.qh_endphub = htole32( 1994 EHCI_QH_SET_MULT(1) | 1995 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1996 ); 1997 if (speed != EHCI_QH_SPEED_HIGH) 1998 sqh->qh.qh_endphub |= htole32( 1999 EHCI_QH_SET_PORT(hshubport) | 2000 EHCI_QH_SET_HUBA(hshubaddr) | 2001 EHCI_QH_SET_CMASK(0x08) /* XXX */ 2002 ); 2003 sqh->qh.qh_curqtd = EHCI_NULL; 2004 /* Fill the overlay qTD */ 2005 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2006 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2007 sqh->qh.qh_qtd.qtd_status = htole32(0); 2008 2009 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2010 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2011 epipe->sqh = sqh; 2012 } else { 2013 sqh = NULL; 2014 } /*xfertype == UE_ISOC*/ 2015 2016 switch (xfertype) { 2017 case UE_CONTROL: 2018 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2019 0, &epipe->ctrl.reqdma); 2020 #ifdef EHCI_DEBUG 2021 if (err) 2022 printf("ehci_open: usb_allocmem()=%d\n", err); 2023 #endif 2024 if (err) 2025 goto bad; 2026 pipe->up_methods = &ehci_device_ctrl_methods; 2027 mutex_enter(&sc->sc_lock); 2028 ehci_add_qh(sc, sqh, sc->sc_async_head); 2029 mutex_exit(&sc->sc_lock); 2030 break; 2031 case UE_BULK: 2032 pipe->up_methods = &ehci_device_bulk_methods; 2033 mutex_enter(&sc->sc_lock); 2034 ehci_add_qh(sc, sqh, sc->sc_async_head); 2035 mutex_exit(&sc->sc_lock); 2036 break; 2037 case UE_INTERRUPT: 2038 pipe->up_methods = &ehci_device_intr_methods; 2039 ival = pipe->up_interval; 2040 if (ival == USBD_DEFAULT_INTERVAL) { 2041 if (speed == EHCI_QH_SPEED_HIGH) { 2042 if (ed->bInterval > 16) { 2043 /* 2044 * illegal with high-speed, but there 2045 * were documentation bugs in the spec, 2046 * so be generous 2047 */ 2048 ival = 256; 2049 } else 2050 ival = (1 << (ed->bInterval - 1)) / 8; 2051 } else 2052 ival = ed->bInterval; 2053 } 2054 err = ehci_device_setintr(sc, sqh, ival); 2055 if (err) 2056 goto bad; 2057 break; 2058 case UE_ISOCHRONOUS: 2059 if (speed == EHCI_QH_SPEED_HIGH) 2060 pipe->up_methods = &ehci_device_isoc_methods; 2061 else 2062 pipe->up_methods = &ehci_device_fs_isoc_methods; 2063 if (ed->bInterval == 0 || ed->bInterval > 16) { 2064 printf("ehci: opening pipe with invalid bInterval\n"); 2065 err = USBD_INVAL; 2066 goto bad; 2067 } 2068 if (UGETW(ed->wMaxPacketSize) == 0) { 2069 printf("ehci: zero length endpoint open request\n"); 2070 err = USBD_INVAL; 2071 goto bad; 2072 } 2073 epipe->isoc.next_frame = 0; 2074 epipe->isoc.cur_xfers = 0; 2075 break; 2076 default: 2077 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2078 err = USBD_INVAL; 2079 goto bad; 2080 } 2081 return USBD_NORMAL_COMPLETION; 2082 2083 bad: 2084 if (sqh != NULL) { 2085 mutex_enter(&sc->sc_lock); 2086 ehci_free_sqh(sc, sqh); 2087 mutex_exit(&sc->sc_lock); 2088 } 2089 return err; 2090 } 2091 2092 /* 2093 * Add an ED to the schedule. Called with USB lock held. 2094 */ 2095 Static void 2096 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2097 { 2098 2099 KASSERT(mutex_owned(&sc->sc_lock)); 2100 2101 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2102 2103 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2104 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2105 2106 sqh->next = head->next; 2107 sqh->qh.qh_link = head->qh.qh_link; 2108 2109 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2110 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2111 2112 head->next = sqh; 2113 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2114 2115 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2116 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2117 2118 #ifdef EHCI_DEBUG 2119 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2120 ehci_dump_sqh(sqh); 2121 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2122 #endif 2123 } 2124 2125 /* 2126 * Remove an ED from the schedule. Called with USB lock held. 2127 */ 2128 Static void 2129 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2130 { 2131 ehci_soft_qh_t *p; 2132 2133 KASSERT(mutex_owned(&sc->sc_lock)); 2134 2135 /* XXX */ 2136 for (p = head; p != NULL && p->next != sqh; p = p->next) 2137 ; 2138 if (p == NULL) 2139 panic("ehci_rem_qh: ED not found"); 2140 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2141 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2142 p->next = sqh->next; 2143 p->qh.qh_link = sqh->qh.qh_link; 2144 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2145 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2146 2147 ehci_sync_hc(sc); 2148 } 2149 2150 Static void 2151 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2152 { 2153 int i; 2154 uint32_t status; 2155 2156 /* Save toggle bit and ping status. */ 2157 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2158 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2159 status = sqh->qh.qh_qtd.qtd_status & 2160 htole32(EHCI_QTD_TOGGLE_MASK | 2161 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2162 /* Set HALTED to make hw leave it alone. */ 2163 sqh->qh.qh_qtd.qtd_status = 2164 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2165 usb_syncmem(&sqh->dma, 2166 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2167 sizeof(sqh->qh.qh_qtd.qtd_status), 2168 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2169 sqh->qh.qh_curqtd = 0; 2170 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2171 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2172 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2173 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2174 sqh->sqtd = sqtd; 2175 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2177 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2178 sqh->qh.qh_qtd.qtd_status = status; 2179 usb_syncmem(&sqh->dma, 2180 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2181 sizeof(sqh->qh.qh_qtd.qtd_status), 2182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2183 } 2184 2185 /* 2186 * Ensure that the HC has released all references to the QH. We do this 2187 * by asking for a Async Advance Doorbell interrupt and then we wait for 2188 * the interrupt. 2189 * To make this easier we first obtain exclusive use of the doorbell. 2190 */ 2191 Static void 2192 ehci_sync_hc(ehci_softc_t *sc) 2193 { 2194 int error __diagused; 2195 2196 KASSERT(mutex_owned(&sc->sc_lock)); 2197 2198 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2199 2200 if (sc->sc_dying) { 2201 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2202 return; 2203 } 2204 /* ask for doorbell */ 2205 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2206 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2207 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2208 2209 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2210 2211 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2212 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2213 #ifdef DIAGNOSTIC 2214 if (error) 2215 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2216 #endif 2217 } 2218 2219 Static void 2220 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2221 { 2222 2223 KASSERT(mutex_owned(&sc->sc_lock)); 2224 2225 for (; itd != NULL; itd = itd->xfer_next) { 2226 struct ehci_soft_itd *prev = itd->frame_list.prev; 2227 2228 /* Unlink itd from hardware chain, or frame array */ 2229 if (prev == NULL) { /* We're at the table head */ 2230 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2231 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2232 usb_syncmem(&sc->sc_fldma, 2233 sizeof(ehci_link_t) * itd->slot, 2234 sizeof(ehci_link_t), 2235 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2236 2237 if (itd->frame_list.next != NULL) 2238 itd->frame_list.next->frame_list.prev = NULL; 2239 } else { 2240 /* XXX this part is untested... */ 2241 prev->itd.itd_next = itd->itd.itd_next; 2242 usb_syncmem(&itd->dma, 2243 itd->offs + offsetof(ehci_itd_t, itd_next), 2244 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2245 2246 prev->frame_list.next = itd->frame_list.next; 2247 if (itd->frame_list.next != NULL) 2248 itd->frame_list.next->frame_list.prev = prev; 2249 } 2250 } 2251 } 2252 2253 Static void 2254 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2255 { 2256 struct ehci_soft_itd *next; 2257 2258 mutex_enter(&sc->sc_lock); 2259 next = NULL; 2260 for (; itd != NULL; itd = next) { 2261 next = itd->xfer_next; 2262 ehci_free_itd_locked(sc, itd); 2263 } 2264 mutex_exit(&sc->sc_lock); 2265 } 2266 2267 Static void 2268 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2269 { 2270 2271 KASSERT(mutex_owned(&sc->sc_lock)); 2272 2273 for (; sitd != NULL; sitd = sitd->xfer_next) { 2274 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2275 2276 /* Unlink sitd from hardware chain, or frame array */ 2277 if (prev == NULL) { /* We're at the table head */ 2278 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2279 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2280 usb_syncmem(&sc->sc_fldma, 2281 sizeof(ehci_link_t) * sitd->slot, 2282 sizeof(ehci_link_t), 2283 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2284 2285 if (sitd->frame_list.next != NULL) 2286 sitd->frame_list.next->frame_list.prev = NULL; 2287 } else { 2288 /* XXX this part is untested... */ 2289 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2290 usb_syncmem(&sitd->dma, 2291 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2292 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2293 2294 prev->frame_list.next = sitd->frame_list.next; 2295 if (sitd->frame_list.next != NULL) 2296 sitd->frame_list.next->frame_list.prev = prev; 2297 } 2298 } 2299 } 2300 2301 Static void 2302 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2303 { 2304 2305 mutex_enter(&sc->sc_lock); 2306 struct ehci_soft_sitd *next = NULL; 2307 for (; sitd != NULL; sitd = next) { 2308 next = sitd->xfer_next; 2309 ehci_free_sitd_locked(sc, sitd); 2310 } 2311 mutex_exit(&sc->sc_lock); 2312 } 2313 2314 /***********/ 2315 2316 Static int 2317 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2318 void *buf, int buflen) 2319 { 2320 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2321 usb_hub_descriptor_t hubd; 2322 usb_port_status_t ps; 2323 uint16_t len, value, index; 2324 int l, totlen = 0; 2325 int port, i; 2326 uint32_t v; 2327 2328 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2329 2330 if (sc->sc_dying) 2331 return -1; 2332 2333 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2334 req->bmRequestType, req->bRequest, 0, 0); 2335 2336 len = UGETW(req->wLength); 2337 value = UGETW(req->wValue); 2338 index = UGETW(req->wIndex); 2339 2340 #define C(x,y) ((x) | ((y) << 8)) 2341 switch (C(req->bRequest, req->bmRequestType)) { 2342 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2343 if (len == 0) 2344 break; 2345 switch (value) { 2346 case C(0, UDESC_DEVICE): { 2347 usb_device_descriptor_t devd; 2348 totlen = min(buflen, sizeof(devd)); 2349 memcpy(&devd, buf, totlen); 2350 USETW(devd.idVendor, sc->sc_id_vendor); 2351 memcpy(buf, &devd, totlen); 2352 break; 2353 2354 } 2355 #define sd ((usb_string_descriptor_t *)buf) 2356 case C(1, UDESC_STRING): 2357 /* Vendor */ 2358 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2359 break; 2360 case C(2, UDESC_STRING): 2361 /* Product */ 2362 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2363 break; 2364 #undef sd 2365 default: 2366 /* default from usbroothub */ 2367 return buflen; 2368 } 2369 break; 2370 2371 /* Hub requests */ 2372 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2373 break; 2374 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2375 USBHIST_LOG(ehcidebug, 2376 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2377 0, 0); 2378 if (index < 1 || index > sc->sc_noport) { 2379 return -1; 2380 } 2381 port = EHCI_PORTSC(index); 2382 v = EOREAD4(sc, port); 2383 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2384 v &= ~EHCI_PS_CLEAR; 2385 switch (value) { 2386 case UHF_PORT_ENABLE: 2387 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2388 break; 2389 case UHF_PORT_SUSPEND: 2390 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2391 break; 2392 v &= ~EHCI_PS_SUSP; 2393 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2394 /* see USB2 spec ch. 7.1.7.7 */ 2395 usb_delay_ms(&sc->sc_bus, 20); 2396 EOWRITE4(sc, port, v); 2397 usb_delay_ms(&sc->sc_bus, 2); 2398 #ifdef DEBUG 2399 v = EOREAD4(sc, port); 2400 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2401 printf("ehci: resume failed: %x\n", v); 2402 #endif 2403 break; 2404 case UHF_PORT_POWER: 2405 if (sc->sc_hasppc) 2406 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2407 break; 2408 case UHF_PORT_TEST: 2409 USBHIST_LOG(ehcidebug, "clear port test " 2410 "%d", index, 0, 0, 0); 2411 break; 2412 case UHF_PORT_INDICATOR: 2413 USBHIST_LOG(ehcidebug, "clear port ind " 2414 "%d", index, 0, 0, 0); 2415 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2416 break; 2417 case UHF_C_PORT_CONNECTION: 2418 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2419 break; 2420 case UHF_C_PORT_ENABLE: 2421 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2422 break; 2423 case UHF_C_PORT_SUSPEND: 2424 /* how? */ 2425 break; 2426 case UHF_C_PORT_OVER_CURRENT: 2427 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2428 break; 2429 case UHF_C_PORT_RESET: 2430 sc->sc_isreset[index] = 0; 2431 break; 2432 default: 2433 return -1; 2434 } 2435 #if 0 2436 switch(value) { 2437 case UHF_C_PORT_CONNECTION: 2438 case UHF_C_PORT_ENABLE: 2439 case UHF_C_PORT_SUSPEND: 2440 case UHF_C_PORT_OVER_CURRENT: 2441 case UHF_C_PORT_RESET: 2442 default: 2443 break; 2444 } 2445 #endif 2446 break; 2447 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2448 if (len == 0) 2449 break; 2450 if ((value & 0xff) != 0) { 2451 return -1; 2452 } 2453 totlen = min(buflen, sizeof(hubd)); 2454 memcpy(&hubd, buf, totlen); 2455 hubd.bNbrPorts = sc->sc_noport; 2456 v = EOREAD4(sc, EHCI_HCSPARAMS); 2457 USETW(hubd.wHubCharacteristics, 2458 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2459 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2460 ? UHD_PORT_IND : 0); 2461 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2462 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2463 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2464 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2465 totlen = min(totlen, hubd.bDescLength); 2466 memcpy(buf, &hubd, totlen); 2467 break; 2468 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2469 if (len != 4) { 2470 return -1; 2471 } 2472 memset(buf, 0, len); /* ? XXX */ 2473 totlen = len; 2474 break; 2475 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2476 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2477 if (index < 1 || index > sc->sc_noport) { 2478 return -1; 2479 } 2480 if (len != 4) { 2481 return -1; 2482 } 2483 v = EOREAD4(sc, EHCI_PORTSC(index)); 2484 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2485 2486 i = UPS_HIGH_SPEED; 2487 if (sc->sc_flags & EHCIF_ETTF) { 2488 /* 2489 * If we are doing embedded transaction translation, 2490 * then directly attached LS/FS devices are reset by 2491 * the EHCI controller itself. PSPD is encoded 2492 * the same way as in USBSTATUS. 2493 */ 2494 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2495 } 2496 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2497 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2498 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2499 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2500 if (v & EHCI_PS_PR) i |= UPS_RESET; 2501 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2502 if (sc->sc_vendor_port_status) 2503 i = sc->sc_vendor_port_status(sc, v, i); 2504 USETW(ps.wPortStatus, i); 2505 i = 0; 2506 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2507 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2508 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2509 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2510 USETW(ps.wPortChange, i); 2511 totlen = min(len, sizeof(ps)); 2512 memcpy(buf, &ps, totlen); 2513 break; 2514 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2515 return -1; 2516 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2517 break; 2518 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2519 if (index < 1 || index > sc->sc_noport) { 2520 return -1; 2521 } 2522 port = EHCI_PORTSC(index); 2523 v = EOREAD4(sc, port); 2524 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2525 v &= ~EHCI_PS_CLEAR; 2526 switch(value) { 2527 case UHF_PORT_ENABLE: 2528 EOWRITE4(sc, port, v | EHCI_PS_PE); 2529 break; 2530 case UHF_PORT_SUSPEND: 2531 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2532 break; 2533 case UHF_PORT_RESET: 2534 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2535 if (EHCI_PS_IS_LOWSPEED(v) 2536 && sc->sc_ncomp > 0 2537 && !(sc->sc_flags & EHCIF_ETTF)) { 2538 /* 2539 * Low speed device on non-ETTF controller or 2540 * unaccompanied controller, give up ownership. 2541 */ 2542 ehci_disown(sc, index, 1); 2543 break; 2544 } 2545 /* Start reset sequence. */ 2546 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2547 EOWRITE4(sc, port, v | EHCI_PS_PR); 2548 /* Wait for reset to complete. */ 2549 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2550 if (sc->sc_dying) { 2551 return -1; 2552 } 2553 /* 2554 * An embedded transaction translator will automatically 2555 * terminate the reset sequence so there's no need to 2556 * it. 2557 */ 2558 v = EOREAD4(sc, port); 2559 if (v & EHCI_PS_PR) { 2560 /* Terminate reset sequence. */ 2561 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2562 /* Wait for HC to complete reset. */ 2563 usb_delay_ms(&sc->sc_bus, 2564 EHCI_PORT_RESET_COMPLETE); 2565 if (sc->sc_dying) { 2566 return -1; 2567 } 2568 } 2569 2570 v = EOREAD4(sc, port); 2571 USBHIST_LOG(ehcidebug, 2572 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2573 if (v & EHCI_PS_PR) { 2574 printf("%s: port reset timeout\n", 2575 device_xname(sc->sc_dev)); 2576 return USBD_TIMEOUT; 2577 } 2578 if (!(v & EHCI_PS_PE)) { 2579 /* Not a high speed device, give up ownership.*/ 2580 ehci_disown(sc, index, 0); 2581 break; 2582 } 2583 sc->sc_isreset[index] = 1; 2584 USBHIST_LOG(ehcidebug, 2585 "ehci port %d reset, status = 0x%08x", index, v, 0, 2586 0); 2587 break; 2588 case UHF_PORT_POWER: 2589 USBHIST_LOG(ehcidebug, 2590 "set port power %d (has PPC = %d)", index, 2591 sc->sc_hasppc, 0, 0); 2592 if (sc->sc_hasppc) 2593 EOWRITE4(sc, port, v | EHCI_PS_PP); 2594 break; 2595 case UHF_PORT_TEST: 2596 USBHIST_LOG(ehcidebug, "set port test %d", 2597 index, 0, 0, 0); 2598 break; 2599 case UHF_PORT_INDICATOR: 2600 USBHIST_LOG(ehcidebug, "set port ind %d", 2601 index, 0, 0, 0); 2602 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2603 break; 2604 default: 2605 return -1; 2606 } 2607 break; 2608 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2609 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2610 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2611 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2612 break; 2613 default: 2614 /* default from usbroothub */ 2615 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2616 buflen, 0, 0, 0); 2617 2618 return buflen; 2619 } 2620 2621 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2622 2623 return totlen; 2624 } 2625 2626 Static void 2627 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2628 { 2629 int port; 2630 uint32_t v; 2631 2632 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2633 2634 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2635 #ifdef DIAGNOSTIC 2636 if (sc->sc_npcomp != 0) { 2637 int i = (index-1) / sc->sc_npcomp; 2638 if (i >= sc->sc_ncomp) 2639 printf("%s: strange port\n", 2640 device_xname(sc->sc_dev)); 2641 else 2642 printf("%s: handing over %s speed device on " 2643 "port %d to %s\n", 2644 device_xname(sc->sc_dev), 2645 lowspeed ? "low" : "full", 2646 index, device_xname(sc->sc_comps[i])); 2647 } else { 2648 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2649 } 2650 #endif 2651 port = EHCI_PORTSC(index); 2652 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2653 EOWRITE4(sc, port, v | EHCI_PS_PO); 2654 } 2655 2656 Static usbd_status 2657 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2658 { 2659 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2660 usbd_status err; 2661 2662 /* Insert last in queue. */ 2663 mutex_enter(&sc->sc_lock); 2664 err = usb_insert_transfer(xfer); 2665 mutex_exit(&sc->sc_lock); 2666 if (err) 2667 return err; 2668 2669 /* Pipe isn't running, start first */ 2670 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2671 } 2672 2673 Static usbd_status 2674 ehci_root_intr_start(struct usbd_xfer *xfer) 2675 { 2676 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2677 2678 if (sc->sc_dying) 2679 return USBD_IOERROR; 2680 2681 mutex_enter(&sc->sc_lock); 2682 sc->sc_intrxfer = xfer; 2683 mutex_exit(&sc->sc_lock); 2684 2685 return USBD_IN_PROGRESS; 2686 } 2687 2688 /* Abort a root interrupt request. */ 2689 Static void 2690 ehci_root_intr_abort(struct usbd_xfer *xfer) 2691 { 2692 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2693 2694 KASSERT(mutex_owned(&sc->sc_lock)); 2695 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2696 2697 sc->sc_intrxfer = NULL; 2698 2699 xfer->ux_status = USBD_CANCELLED; 2700 usb_transfer_complete(xfer); 2701 } 2702 2703 /* Close the root pipe. */ 2704 Static void 2705 ehci_root_intr_close(struct usbd_pipe *pipe) 2706 { 2707 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2708 2709 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2710 2711 KASSERT(mutex_owned(&sc->sc_lock)); 2712 2713 sc->sc_intrxfer = NULL; 2714 } 2715 2716 Static void 2717 ehci_root_intr_done(struct usbd_xfer *xfer) 2718 { 2719 xfer->ux_hcpriv = NULL; 2720 } 2721 2722 /************************/ 2723 2724 Static ehci_soft_qh_t * 2725 ehci_alloc_sqh(ehci_softc_t *sc) 2726 { 2727 ehci_soft_qh_t *sqh; 2728 usbd_status err; 2729 int i, offs; 2730 usb_dma_t dma; 2731 2732 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2733 2734 mutex_enter(&sc->sc_lock); 2735 if (sc->sc_freeqhs == NULL) { 2736 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2737 mutex_exit(&sc->sc_lock); 2738 2739 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2740 EHCI_PAGE_SIZE, &dma); 2741 #ifdef EHCI_DEBUG 2742 if (err) 2743 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2744 #endif 2745 if (err) 2746 return NULL; 2747 2748 mutex_enter(&sc->sc_lock); 2749 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2750 offs = i * EHCI_SQH_SIZE; 2751 sqh = KERNADDR(&dma, offs); 2752 sqh->physaddr = DMAADDR(&dma, offs); 2753 sqh->dma = dma; 2754 sqh->offs = offs; 2755 sqh->next = sc->sc_freeqhs; 2756 sc->sc_freeqhs = sqh; 2757 } 2758 } 2759 sqh = sc->sc_freeqhs; 2760 sc->sc_freeqhs = sqh->next; 2761 mutex_exit(&sc->sc_lock); 2762 2763 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2764 sqh->next = NULL; 2765 return sqh; 2766 } 2767 2768 Static void 2769 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2770 { 2771 KASSERT(mutex_owned(&sc->sc_lock)); 2772 2773 sqh->next = sc->sc_freeqhs; 2774 sc->sc_freeqhs = sqh; 2775 } 2776 2777 Static ehci_soft_qtd_t * 2778 ehci_alloc_sqtd(ehci_softc_t *sc) 2779 { 2780 ehci_soft_qtd_t *sqtd = NULL; 2781 usbd_status err; 2782 int i, offs; 2783 usb_dma_t dma; 2784 2785 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2786 2787 mutex_enter(&sc->sc_lock); 2788 if (sc->sc_freeqtds == NULL) { 2789 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2790 mutex_exit(&sc->sc_lock); 2791 2792 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2793 EHCI_PAGE_SIZE, &dma); 2794 #ifdef EHCI_DEBUG 2795 if (err) 2796 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2797 #endif 2798 if (err) 2799 goto done; 2800 2801 mutex_enter(&sc->sc_lock); 2802 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2803 offs = i * EHCI_SQTD_SIZE; 2804 sqtd = KERNADDR(&dma, offs); 2805 sqtd->physaddr = DMAADDR(&dma, offs); 2806 sqtd->dma = dma; 2807 sqtd->offs = offs; 2808 2809 sqtd->nextqtd = sc->sc_freeqtds; 2810 sc->sc_freeqtds = sqtd; 2811 } 2812 } 2813 2814 sqtd = sc->sc_freeqtds; 2815 sc->sc_freeqtds = sqtd->nextqtd; 2816 mutex_exit(&sc->sc_lock); 2817 2818 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2819 sqtd->nextqtd = NULL; 2820 sqtd->xfer = NULL; 2821 2822 done: 2823 return sqtd; 2824 } 2825 2826 Static void 2827 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2828 { 2829 2830 mutex_enter(&sc->sc_lock); 2831 sqtd->nextqtd = sc->sc_freeqtds; 2832 sc->sc_freeqtds = sqtd; 2833 mutex_exit(&sc->sc_lock); 2834 } 2835 2836 Static usbd_status 2837 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2838 int alen, int rd, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2839 { 2840 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2841 ehci_soft_qtd_t *next, *cur; 2842 ehci_physaddr_t nextphys; 2843 uint32_t qtdstatus; 2844 int len, curlen, mps; 2845 int i, tog; 2846 int pages, pageoffs; 2847 size_t curoffs; 2848 vaddr_t va, va_offs; 2849 usb_dma_t *dma = &xfer->ux_dmabuf; 2850 uint16_t flags = xfer->ux_flags; 2851 paddr_t a; 2852 2853 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2854 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2855 2856 ASSERT_SLEEPABLE(); 2857 KASSERT(sp); 2858 KASSERT(alen != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2859 2860 len = alen; 2861 qtdstatus = EHCI_QTD_ACTIVE | 2862 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2863 EHCI_QTD_SET_CERR(3) 2864 ; 2865 2866 size_t nsqtd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 2867 nsqtd += ((len + EHCI_QTD_MAXTRANSFER - 1) / EHCI_QTD_MAXTRANSFER); 2868 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2869 KM_SLEEP); 2870 exfer->ex_nsqtd = nsqtd; 2871 2872 mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2873 cur = ehci_alloc_sqtd(sc); 2874 *sp = cur; 2875 if (cur == NULL) 2876 goto nomem; 2877 2878 curoffs = 0; 2879 for (size_t j = 0;;) { 2880 KASSERT(j < nsqtd); 2881 exfer->ex_sqtds[j++] = cur; 2882 2883 /* The EHCI hardware can handle at most 5 pages. */ 2884 va = (vaddr_t)KERNADDR(dma, curoffs); 2885 va_offs = EHCI_PAGE_OFFSET(va); 2886 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2887 /* we can handle it in this QTD */ 2888 curlen = len - curoffs; 2889 } else { 2890 /* must use multiple TDs, fill as much as possible. */ 2891 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2892 2893 /* the length must be a multiple of the max size */ 2894 curlen -= curlen % mps; 2895 USBHIST_LOG(ehcidebug, "multiple QTDs, curlen=%d", 2896 curlen, 0, 0, 0); 2897 KASSERT(curlen != 0); 2898 } 2899 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", len, 2900 curlen, curoffs, 0); 2901 2902 /* 2903 * Allocate another transfer if there's more data left, 2904 * or if force last short transfer flag is set and we're 2905 * allocating a multiple of the max packet size. 2906 */ 2907 2908 if (curoffs + curlen != len || 2909 ((curlen % mps) == 0 && !rd && curlen != 0 && 2910 (flags & USBD_FORCE_SHORT_XFER))) { 2911 next = ehci_alloc_sqtd(sc); 2912 if (next == NULL) 2913 goto nomem; 2914 nextphys = htole32(next->physaddr); 2915 } else { 2916 next = NULL; 2917 nextphys = EHCI_NULL; 2918 } 2919 2920 /* Find number of pages we'll be using, insert dma addresses */ 2921 pages = EHCI_NPAGES(curlen); 2922 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2923 pageoffs = EHCI_PAGE(curoffs); 2924 for (i = 0; i < pages; i++) { 2925 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2926 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2927 /* Cast up to avoid compiler warnings */ 2928 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2929 } 2930 2931 /* First buffer pointer requires a page offset to start at */ 2932 cur->qtd.qtd_buffer[0] |= htole32(va_offs); 2933 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2934 cur->qtd.qtd_status = htole32(qtdstatus); 2935 cur->nextqtd = next; 2936 cur->xfer = xfer; 2937 cur->bufoff = curoffs; 2938 cur->tdlen = curlen; 2939 cur->len = 0; 2940 2941 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2942 curoffs, curoffs + curlen, 0, 0); 2943 2944 /* 2945 * adjust the toggle based on the number of packets in this 2946 * qtd 2947 */ 2948 if (((curlen + mps - 1) / mps) & 1) { 2949 tog ^= 1; 2950 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2951 } 2952 if (next == NULL) 2953 break; 2954 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2955 if (len) 2956 curoffs += curlen; 2957 cur = next; 2958 } 2959 if (ep) 2960 *ep = cur; 2961 2962 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", *sp, cur, 0, 0); 2963 2964 return USBD_NORMAL_COMPLETION; 2965 2966 nomem: 2967 ehci_free_sqtds(sc, exfer); 2968 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2969 return USBD_NOMEM; 2970 } 2971 2972 Static void 2973 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2974 { 2975 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2976 USBHIST_LOG(ehcidebug, "exfer=%p", exfer, 0, 0, 0); 2977 2978 mutex_enter(&sc->sc_lock); 2979 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2980 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2981 2982 if (sqtd == NULL) 2983 break; 2984 2985 sqtd->nextqtd = sc->sc_freeqtds; 2986 sc->sc_freeqtds = sqtd; 2987 } 2988 mutex_exit(&sc->sc_lock); 2989 } 2990 2991 Static void 2992 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2993 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2994 { 2995 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2996 ehci_soft_qtd_t *sqtd, *prev; 2997 int tog = *toggle; 2998 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2999 int len = length; 3000 size_t i; 3001 3002 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3003 USBHIST_LOG(ehcidebug, "xfer=%p len %d isread %d toggle %d", xfer, 3004 len, isread, *toggle); 3005 USBHIST_LOG(ehcidebug, " VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 3006 0, 0, 0); 3007 3008 sqtd = prev = NULL; 3009 for (i = 0; i < exfer->ex_nsqtd; i++, prev = sqtd) { 3010 sqtd = exfer->ex_sqtds[i]; 3011 vaddr_t va = (vaddr_t)KERNADDR(&xfer->ux_dmabuf, sqtd->bufoff); 3012 sqtd->len = sqtd->tdlen; 3013 if (len < sqtd->len) { 3014 sqtd->len = len; 3015 } 3016 3017 USBHIST_LOG(ehcidebug, "sqtd[%d]=%p prev %p len %d", i, sqtd, 3018 prev, sqtd->len); 3019 USBHIST_LOG(ehcidebug, " va %p bufoff %d pa %p", va, sqtd->bufoff, 3020 DMAADDR(&xfer->ux_dmabuf, sqtd->bufoff), 0); 3021 3022 if (prev) { 3023 prev->nextqtd = sqtd; 3024 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3025 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3026 } 3027 usb_syncmem(&sqtd->dma, 3028 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3029 sizeof(sqtd->qtd.qtd_status), 3030 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3031 usb_syncmem(&sqtd->dma, 3032 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3033 sizeof(sqtd->qtd.qtd_buffer[0]), 3034 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3035 3036 sqtd->qtd.qtd_buffer[0] &= ~htole32(EHCI_PAGE_MASK); 3037 sqtd->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3038 /* Reset ... */ 3039 sqtd->qtd.qtd_status &= ~htole32( 3040 EHCI_QTD_STATUS_MASK | 3041 EHCI_QTD_PID_MASK | 3042 EHCI_QTD_CERR_MASK | 3043 EHCI_QTD_C_PAGE_MASK | 3044 EHCI_QTD_BYTES_MASK | 3045 EHCI_QTD_TOGGLE_MASK); 3046 sqtd->qtd.qtd_status |= htole32( 3047 EHCI_QTD_ACTIVE | 3048 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3049 EHCI_QTD_SET_BYTES(sqtd->len) | 3050 EHCI_QTD_SET_CERR(3) | 3051 EHCI_QTD_SET_TOGGLE(tog)); 3052 3053 usb_syncmem(&sqtd->dma, 3054 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3055 sizeof(sqtd->qtd.qtd_status), 3056 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3057 usb_syncmem(&sqtd->dma, 3058 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3059 sizeof(sqtd->qtd.qtd_buffer[0]), 3060 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3061 3062 if (((sqtd->len + mps - 1) / mps) & 1) { 3063 tog ^= 1; 3064 } 3065 3066 len -= sqtd->len; 3067 if (len == 0) 3068 break; 3069 } 3070 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu i %zu", 3071 xfer, length, len, mps, exfer->ex_nsqtd, i); 3072 3073 if (i < exfer->ex_nsqtd) { 3074 /* 3075 * The full allocation chain wasn't used, so we need to 3076 * terminate it. 3077 */ 3078 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3079 } 3080 *lsqtd = sqtd; 3081 *toggle = tog; 3082 } 3083 3084 Static ehci_soft_itd_t * 3085 ehci_alloc_itd(ehci_softc_t *sc) 3086 { 3087 struct ehci_soft_itd *itd, *freeitd; 3088 usbd_status err; 3089 usb_dma_t dma; 3090 3091 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3092 3093 mutex_enter(&sc->sc_lock); 3094 3095 freeitd = LIST_FIRST(&sc->sc_freeitds); 3096 if (freeitd == NULL) { 3097 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3098 mutex_exit(&sc->sc_lock); 3099 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3100 EHCI_PAGE_SIZE, &dma); 3101 3102 if (err) { 3103 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 0); 3104 return NULL; 3105 } 3106 mutex_enter(&sc->sc_lock); 3107 3108 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3109 int offs = i * EHCI_ITD_SIZE; 3110 itd = KERNADDR(&dma, offs); 3111 itd->physaddr = DMAADDR(&dma, offs); 3112 itd->dma = dma; 3113 itd->offs = offs; 3114 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3115 } 3116 freeitd = LIST_FIRST(&sc->sc_freeitds); 3117 } 3118 3119 itd = freeitd; 3120 LIST_REMOVE(itd, free_list); 3121 mutex_exit(&sc->sc_lock); 3122 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3123 3124 itd->frame_list.next = NULL; 3125 itd->frame_list.prev = NULL; 3126 itd->xfer_next = NULL; 3127 itd->slot = 0; 3128 3129 return itd; 3130 } 3131 3132 Static ehci_soft_sitd_t * 3133 ehci_alloc_sitd(ehci_softc_t *sc) 3134 { 3135 struct ehci_soft_sitd *sitd, *freesitd; 3136 usbd_status err; 3137 int i, offs; 3138 usb_dma_t dma; 3139 3140 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3141 3142 mutex_enter(&sc->sc_lock); 3143 freesitd = LIST_FIRST(&sc->sc_freesitds); 3144 if (freesitd == NULL) { 3145 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3146 mutex_exit(&sc->sc_lock); 3147 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3148 EHCI_PAGE_SIZE, &dma); 3149 3150 if (err) { 3151 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 3152 0); 3153 return NULL; 3154 } 3155 3156 mutex_enter(&sc->sc_lock); 3157 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3158 offs = i * EHCI_SITD_SIZE; 3159 sitd = KERNADDR(&dma, offs); 3160 sitd->physaddr = DMAADDR(&dma, offs); 3161 sitd->dma = dma; 3162 sitd->offs = offs; 3163 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3164 } 3165 freesitd = LIST_FIRST(&sc->sc_freesitds); 3166 } 3167 3168 sitd = freesitd; 3169 LIST_REMOVE(sitd, free_list); 3170 mutex_exit(&sc->sc_lock); 3171 3172 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3173 3174 sitd->frame_list.next = NULL; 3175 sitd->frame_list.prev = NULL; 3176 sitd->xfer_next = NULL; 3177 sitd->slot = 0; 3178 3179 return sitd; 3180 } 3181 3182 /****************/ 3183 3184 /* 3185 * Close a reqular pipe. 3186 * Assumes that there are no pending transactions. 3187 */ 3188 Static void 3189 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3190 { 3191 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3192 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3193 ehci_soft_qh_t *sqh = epipe->sqh; 3194 3195 KASSERT(mutex_owned(&sc->sc_lock)); 3196 3197 ehci_rem_qh(sc, sqh, head); 3198 ehci_free_sqh(sc, epipe->sqh); 3199 } 3200 3201 /* 3202 * Abort a device request. 3203 * If this routine is called at splusb() it guarantees that the request 3204 * will be removed from the hardware scheduling and that the callback 3205 * for it will be called with USBD_CANCELLED status. 3206 * It's impossible to guarantee that the requested transfer will not 3207 * have happened since the hardware runs concurrently. 3208 * If the transaction has already happened we rely on the ordinary 3209 * interrupt processing to process it. 3210 * XXX This is most probably wrong. 3211 * XXXMRG this doesn't make sense anymore. 3212 */ 3213 Static void 3214 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3215 { 3216 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3217 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3218 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3219 ehci_soft_qh_t *sqh = epipe->sqh; 3220 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3221 ehci_physaddr_t cur; 3222 uint32_t qhstatus; 3223 int hit; 3224 int wake; 3225 3226 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3227 3228 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3229 3230 KASSERT(mutex_owned(&sc->sc_lock)); 3231 ASSERT_SLEEPABLE(); 3232 3233 if (sc->sc_dying) { 3234 /* If we're dying, just do the software part. */ 3235 xfer->ux_status = status; /* make software ignore it */ 3236 callout_stop(&xfer->ux_callout); 3237 usb_transfer_complete(xfer); 3238 return; 3239 } 3240 3241 /* 3242 * If an abort is already in progress then just wait for it to 3243 * complete and return. 3244 */ 3245 if (xfer->ux_hcflags & UXFER_ABORTING) { 3246 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3247 #ifdef DIAGNOSTIC 3248 if (status == USBD_TIMEOUT) 3249 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3250 #endif 3251 /* Override the status which might be USBD_TIMEOUT. */ 3252 xfer->ux_status = status; 3253 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3254 0, 0, 0, 0); 3255 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3256 while (xfer->ux_hcflags & UXFER_ABORTING) 3257 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3258 return; 3259 } 3260 xfer->ux_hcflags |= UXFER_ABORTING; 3261 3262 /* 3263 * Step 1: Make interrupt routine and hardware ignore xfer. 3264 */ 3265 xfer->ux_status = status; /* make software ignore it */ 3266 callout_stop(&xfer->ux_callout); 3267 3268 usb_syncmem(&sqh->dma, 3269 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3270 sizeof(sqh->qh.qh_qtd.qtd_status), 3271 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3272 qhstatus = sqh->qh.qh_qtd.qtd_status; 3273 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3274 usb_syncmem(&sqh->dma, 3275 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3276 sizeof(sqh->qh.qh_qtd.qtd_status), 3277 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3278 3279 if (exfer->ex_type == EX_CTRL) { 3280 fsqtd = exfer->ex_setup; 3281 lsqtd = exfer->ex_status; 3282 } else { 3283 fsqtd = exfer->ex_sqtdstart; 3284 lsqtd = exfer->ex_sqtdend; 3285 } 3286 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3287 usb_syncmem(&sqtd->dma, 3288 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3289 sizeof(sqtd->qtd.qtd_status), 3290 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3291 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3292 usb_syncmem(&sqtd->dma, 3293 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3294 sizeof(sqtd->qtd.qtd_status), 3295 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3296 if (sqtd == lsqtd) 3297 break; 3298 } 3299 3300 /* 3301 * Step 2: Wait until we know hardware has finished any possible 3302 * use of the xfer. Also make sure the soft interrupt routine 3303 * has run. 3304 */ 3305 ehci_sync_hc(sc); 3306 sc->sc_softwake = 1; 3307 usb_schedsoftintr(&sc->sc_bus); 3308 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3309 3310 /* 3311 * Step 3: Remove any vestiges of the xfer from the hardware. 3312 * The complication here is that the hardware may have executed 3313 * beyond the xfer we're trying to abort. So as we're scanning 3314 * the TDs of this xfer we check if the hardware points to 3315 * any of them. 3316 */ 3317 3318 usb_syncmem(&sqh->dma, 3319 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3320 sizeof(sqh->qh.qh_curqtd), 3321 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3322 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3323 hit = 0; 3324 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3325 hit |= cur == sqtd->physaddr; 3326 if (sqtd == lsqtd) 3327 break; 3328 } 3329 sqtd = sqtd->nextqtd; 3330 /* Zap curqtd register if hardware pointed inside the xfer. */ 3331 if (hit && sqtd != NULL) { 3332 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3333 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3334 usb_syncmem(&sqh->dma, 3335 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3336 sizeof(sqh->qh.qh_curqtd), 3337 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3338 sqh->qh.qh_qtd.qtd_status = qhstatus; 3339 usb_syncmem(&sqh->dma, 3340 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3341 sizeof(sqh->qh.qh_qtd.qtd_status), 3342 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3343 } else { 3344 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3345 usb_syncmem(&sqh->dma, 3346 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3347 sizeof(sqh->qh.qh_curqtd), 3348 BUS_DMASYNC_PREREAD); 3349 } 3350 3351 /* 3352 * Step 4: Execute callback. 3353 */ 3354 #ifdef DIAGNOSTIC 3355 exfer->ex_isdone = true; 3356 #endif 3357 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3358 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3359 usb_transfer_complete(xfer); 3360 if (wake) { 3361 cv_broadcast(&xfer->ux_hccv); 3362 } 3363 3364 KASSERT(mutex_owned(&sc->sc_lock)); 3365 } 3366 3367 Static void 3368 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3369 { 3370 ehci_isoc_trans_t trans_status; 3371 struct ehci_xfer *exfer; 3372 ehci_softc_t *sc; 3373 struct ehci_soft_itd *itd; 3374 struct ehci_soft_sitd *sitd; 3375 int i, wake; 3376 3377 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3378 3379 exfer = EHCI_XFER2EXFER(xfer); 3380 sc = EHCI_XFER2SC(xfer); 3381 3382 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3383 3384 KASSERT(mutex_owned(&sc->sc_lock)); 3385 3386 if (sc->sc_dying) { 3387 xfer->ux_status = status; 3388 callout_stop(&xfer->ux_callout); 3389 usb_transfer_complete(xfer); 3390 return; 3391 } 3392 3393 if (xfer->ux_hcflags & UXFER_ABORTING) { 3394 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3395 3396 #ifdef DIAGNOSTIC 3397 if (status == USBD_TIMEOUT) 3398 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3399 #endif 3400 3401 xfer->ux_status = status; 3402 USBHIST_LOG(ehcidebug, 3403 "waiting for abort to finish", 0, 0, 0, 0); 3404 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3405 while (xfer->ux_hcflags & UXFER_ABORTING) 3406 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3407 goto done; 3408 } 3409 xfer->ux_hcflags |= UXFER_ABORTING; 3410 3411 xfer->ux_status = status; 3412 callout_stop(&xfer->ux_callout); 3413 3414 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3415 for (itd = exfer->ex_itdstart; itd != NULL; 3416 itd = itd->xfer_next) { 3417 usb_syncmem(&itd->dma, 3418 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3419 sizeof(itd->itd.itd_ctl), 3420 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3421 3422 for (i = 0; i < 8; i++) { 3423 trans_status = le32toh(itd->itd.itd_ctl[i]); 3424 trans_status &= ~EHCI_ITD_ACTIVE; 3425 itd->itd.itd_ctl[i] = htole32(trans_status); 3426 } 3427 3428 usb_syncmem(&itd->dma, 3429 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3430 sizeof(itd->itd.itd_ctl), 3431 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3432 } 3433 } else { 3434 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3435 sitd = sitd->xfer_next) { 3436 usb_syncmem(&sitd->dma, 3437 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3438 sizeof(sitd->sitd.sitd_buffer), 3439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3440 3441 trans_status = le32toh(sitd->sitd.sitd_trans); 3442 trans_status &= ~EHCI_SITD_ACTIVE; 3443 sitd->sitd.sitd_trans = htole32(trans_status); 3444 3445 usb_syncmem(&sitd->dma, 3446 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3447 sizeof(sitd->sitd.sitd_buffer), 3448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3449 } 3450 } 3451 3452 sc->sc_softwake = 1; 3453 usb_schedsoftintr(&sc->sc_bus); 3454 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3455 3456 #ifdef DIAGNOSTIC 3457 exfer->ex_isdone = true; 3458 #endif 3459 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3460 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3461 usb_transfer_complete(xfer); 3462 if (wake) { 3463 cv_broadcast(&xfer->ux_hccv); 3464 } 3465 3466 done: 3467 KASSERT(mutex_owned(&sc->sc_lock)); 3468 return; 3469 } 3470 3471 Static void 3472 ehci_timeout(void *addr) 3473 { 3474 struct usbd_xfer *xfer = addr; 3475 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3476 struct usbd_pipe *pipe = xfer->ux_pipe; 3477 struct usbd_device *dev = pipe->up_dev; 3478 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3479 3480 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3481 3482 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3483 #ifdef EHCI_DEBUG 3484 if (ehcidebug >= 2) 3485 usbd_dump_pipe(pipe); 3486 #endif 3487 3488 if (sc->sc_dying) { 3489 mutex_enter(&sc->sc_lock); 3490 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3491 mutex_exit(&sc->sc_lock); 3492 return; 3493 } 3494 3495 /* Execute the abort in a process context. */ 3496 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3497 USB_TASKQ_MPSAFE); 3498 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3499 } 3500 3501 Static void 3502 ehci_timeout_task(void *addr) 3503 { 3504 struct usbd_xfer *xfer = addr; 3505 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3506 3507 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3508 3509 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3510 3511 mutex_enter(&sc->sc_lock); 3512 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3513 mutex_exit(&sc->sc_lock); 3514 } 3515 3516 /************************/ 3517 3518 Static int 3519 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3520 { 3521 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3522 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3523 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3524 usb_device_request_t *req = &xfer->ux_request; 3525 ehci_soft_qtd_t *setup, *status, *next; 3526 int isread = req->bmRequestType & UT_READ; 3527 int len = xfer->ux_bufsize; 3528 int err; 3529 3530 exfer->ex_type = EX_CTRL; 3531 exfer->ex_status = NULL; 3532 exfer->ex_data = NULL; 3533 exfer->ex_setup = ehci_alloc_sqtd(sc); 3534 if (exfer->ex_setup == NULL) { 3535 err = ENOMEM; 3536 goto bad1; 3537 } 3538 exfer->ex_status = ehci_alloc_sqtd(sc); 3539 if (exfer->ex_status == NULL) { 3540 err = ENOMEM; 3541 goto bad2; 3542 } 3543 setup = exfer->ex_setup; 3544 status = exfer->ex_status; 3545 exfer->ex_nsqtd = 0; 3546 next = status; 3547 /* Set up data transaction */ 3548 if (len != 0) { 3549 ehci_soft_qtd_t *end; 3550 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3551 &exfer->ex_data, &end); 3552 if (err) 3553 goto bad3; 3554 next = exfer->ex_data; 3555 } 3556 3557 /* Clear toggle */ 3558 setup->qtd.qtd_status = htole32( 3559 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3560 EHCI_QTD_SET_TOGGLE(0) | 3561 EHCI_QTD_SET_BYTES(sizeof(*req)) 3562 ); 3563 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3564 setup->qtd.qtd_buffer_hi[0] = 0; 3565 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3566 setup->nextqtd = next; 3567 setup->xfer = xfer; 3568 setup->tdlen = setup->len = sizeof(*req); 3569 3570 status->qtd.qtd_status = htole32( 3571 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3572 EHCI_QTD_SET_TOGGLE(1) | 3573 EHCI_QTD_IOC 3574 ); 3575 status->qtd.qtd_buffer[0] = 0; 3576 status->qtd.qtd_buffer_hi[0] = 0; 3577 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3578 status->nextqtd = NULL; 3579 status->xfer = xfer; 3580 status->tdlen = status->len = 0; 3581 3582 return 0; 3583 bad3: 3584 ehci_free_sqtd(sc, exfer->ex_status); 3585 bad2: 3586 ehci_free_sqtd(sc, exfer->ex_setup); 3587 bad1: 3588 return err; 3589 } 3590 3591 Static void 3592 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3593 { 3594 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3595 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3596 3597 KASSERT(ex->ex_type == EX_CTRL); 3598 3599 ehci_free_sqtd(sc, ex->ex_setup); 3600 ehci_free_sqtd(sc, ex->ex_status); 3601 ehci_free_sqtds(sc, ex); 3602 if (ex->ex_nsqtd) 3603 kmem_free(ex->ex_sqtds, 3604 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3605 } 3606 3607 Static usbd_status 3608 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3609 { 3610 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3611 usbd_status err; 3612 3613 /* Insert last in queue. */ 3614 mutex_enter(&sc->sc_lock); 3615 err = usb_insert_transfer(xfer); 3616 mutex_exit(&sc->sc_lock); 3617 if (err) 3618 return err; 3619 3620 /* Pipe isn't running, start first */ 3621 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3622 } 3623 3624 Static usbd_status 3625 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3626 { 3627 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3628 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3629 usb_device_request_t *req = &xfer->ux_request; 3630 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3631 ehci_soft_qtd_t *setup, *status, *next; 3632 ehci_soft_qh_t *sqh; 3633 3634 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3635 3636 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3637 3638 if (sc->sc_dying) 3639 return USBD_IOERROR; 3640 3641 const int isread = req->bmRequestType & UT_READ; 3642 const int len = UGETW(req->wLength); 3643 3644 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3645 "wValue=0x%04x, wIndex=0x%04x", 3646 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3647 UGETW(req->wIndex)); 3648 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3649 len, epipe->pipe.up_dev->ud_addr, 3650 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3651 3652 sqh = epipe->sqh; 3653 3654 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3655 "address QH %" __PRIuBIT " pipe %d\n", 3656 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3657 epipe->pipe.up_dev->ud_addr); 3658 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3659 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3660 "MPS QH %" __PRIuBIT " pipe %d\n", 3661 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3662 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3663 3664 setup = exfer->ex_setup; 3665 status = exfer->ex_status; 3666 3667 USBHIST_LOG(ehcidebug, "setup %p status %p data %p", 3668 setup, status, exfer->ex_data, 0); 3669 KASSERTMSG(setup != NULL && status != NULL, 3670 "Failed memory allocation, setup %p status %p", 3671 setup, status); 3672 3673 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3674 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3675 3676 /* Clear toggle */ 3677 setup->qtd.qtd_status &= ~htole32( 3678 EHCI_QTD_STATUS_MASK | 3679 EHCI_QTD_BYTES_MASK | 3680 EHCI_QTD_TOGGLE_MASK | 3681 EHCI_QTD_CERR_MASK 3682 ); 3683 setup->qtd.qtd_status |= htole32( 3684 EHCI_QTD_ACTIVE | 3685 EHCI_QTD_SET_CERR(3) | 3686 EHCI_QTD_SET_TOGGLE(0) | 3687 EHCI_QTD_SET_BYTES(sizeof(*req)) 3688 ); 3689 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3690 setup->qtd.qtd_buffer_hi[0] = 0; 3691 3692 next = status; 3693 status->qtd.qtd_status &= ~htole32( 3694 EHCI_QTD_STATUS_MASK | 3695 EHCI_QTD_PID_MASK | 3696 EHCI_QTD_BYTES_MASK | 3697 EHCI_QTD_TOGGLE_MASK | 3698 EHCI_QTD_CERR_MASK 3699 ); 3700 status->qtd.qtd_status |= htole32( 3701 EHCI_QTD_ACTIVE | 3702 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3703 EHCI_QTD_SET_CERR(3) | 3704 EHCI_QTD_SET_TOGGLE(1) | 3705 EHCI_QTD_SET_BYTES(0) | 3706 EHCI_QTD_IOC 3707 ); 3708 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3709 3710 KASSERT(exfer->ex_isdone); 3711 #ifdef DIAGNOSTIC 3712 exfer->ex_isdone = false; 3713 #endif 3714 3715 /* Set up data transaction */ 3716 if (len != 0) { 3717 ehci_soft_qtd_t *end; 3718 3719 /* Start toggle at 1. */ 3720 int toggle = 1; 3721 next = exfer->ex_data; 3722 KASSERTMSG(next != NULL, "Failed memory allocation"); 3723 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3724 end->nextqtd = status; 3725 end->qtd.qtd_next = end->qtd.qtd_altnext = 3726 htole32(status->physaddr); 3727 3728 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3729 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3730 3731 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3732 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3733 } 3734 3735 setup->nextqtd = next; 3736 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3737 3738 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3739 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3740 3741 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3742 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3743 3744 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3745 3746 #ifdef EHCI_DEBUG 3747 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3748 ehci_dump_sqh(sqh); 3749 ehci_dump_sqtds(setup); 3750 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3751 #endif 3752 3753 mutex_enter(&sc->sc_lock); 3754 3755 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3756 ehci_set_qh_qtd(sqh, setup); 3757 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3758 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3759 ehci_timeout, xfer); 3760 } 3761 ehci_add_intr_list(sc, exfer); 3762 xfer->ux_status = USBD_IN_PROGRESS; 3763 mutex_exit(&sc->sc_lock); 3764 3765 #if 0 3766 #ifdef EHCI_DEBUG 3767 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3768 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3769 // delay(10000); 3770 ehci_dump_regs(sc); 3771 ehci_dump_sqh(sc->sc_async_head); 3772 ehci_dump_sqh(sqh); 3773 ehci_dump_sqtds(setup); 3774 #endif 3775 #endif 3776 3777 if (sc->sc_bus.ub_usepolling) 3778 ehci_waitintr(sc, xfer); 3779 3780 return USBD_IN_PROGRESS; 3781 } 3782 3783 Static void 3784 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3785 { 3786 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3787 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3788 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3789 usb_device_request_t *req = &xfer->ux_request; 3790 int len = UGETW(req->wLength); 3791 int rd = req->bmRequestType & UT_READ; 3792 3793 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3794 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3795 3796 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3797 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3798 3799 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3800 ehci_del_intr_list(sc, ex); /* remove from active list */ 3801 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3802 BUS_DMASYNC_POSTWRITE); 3803 if (len) 3804 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3805 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3806 } 3807 3808 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3809 } 3810 3811 /* Abort a device control request. */ 3812 Static void 3813 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3814 { 3815 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3816 3817 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3818 ehci_abort_xfer(xfer, USBD_CANCELLED); 3819 } 3820 3821 /* Close a device control pipe. */ 3822 Static void 3823 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3824 { 3825 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3826 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3827 3828 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3829 3830 KASSERT(mutex_owned(&sc->sc_lock)); 3831 3832 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3833 3834 ehci_close_pipe(pipe, sc->sc_async_head); 3835 } 3836 3837 /* 3838 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3839 * qTD status, or miss signalling occasionally under heavy load. If the host 3840 * machine is too fast, we we can miss transaction completion - when we scan 3841 * the active list the transaction still seems to be active. This generally 3842 * exhibits itself as a umass stall that never recovers. 3843 * 3844 * We work around this behaviour by setting up this callback after any softintr 3845 * that completes with transactions still pending, giving us another chance to 3846 * check for completion after the writeback has taken place. 3847 */ 3848 Static void 3849 ehci_intrlist_timeout(void *arg) 3850 { 3851 ehci_softc_t *sc = arg; 3852 3853 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3854 3855 usb_schedsoftintr(&sc->sc_bus); 3856 } 3857 3858 /************************/ 3859 3860 Static int 3861 ehci_device_bulk_init(struct usbd_xfer *xfer) 3862 { 3863 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3864 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3865 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3866 int endpt = ed->bEndpointAddress; 3867 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3868 int len = xfer->ux_bufsize; 3869 int err = 0; 3870 3871 exfer->ex_type = EX_BULK; 3872 exfer->ex_nsqtd = 0; 3873 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3874 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 3875 3876 return err; 3877 } 3878 3879 Static void 3880 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3881 { 3882 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3883 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3884 3885 KASSERT(ex->ex_type == EX_BULK); 3886 3887 ehci_free_sqtds(sc, ex); 3888 if (ex->ex_nsqtd) 3889 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3890 } 3891 3892 Static usbd_status 3893 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3894 { 3895 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3896 usbd_status err; 3897 3898 /* Insert last in queue. */ 3899 mutex_enter(&sc->sc_lock); 3900 err = usb_insert_transfer(xfer); 3901 mutex_exit(&sc->sc_lock); 3902 if (err) 3903 return err; 3904 3905 /* Pipe isn't running, start first */ 3906 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3907 } 3908 3909 Static usbd_status 3910 ehci_device_bulk_start(struct usbd_xfer *xfer) 3911 { 3912 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3913 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3914 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3915 ehci_soft_qh_t *sqh; 3916 ehci_soft_qtd_t *end; 3917 int len, isread, endpt; 3918 3919 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3920 3921 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3922 xfer, xfer->ux_length, xfer->ux_flags, 0); 3923 3924 if (sc->sc_dying) 3925 return USBD_IOERROR; 3926 3927 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3928 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3929 3930 len = xfer->ux_length; 3931 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3932 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3933 sqh = epipe->sqh; 3934 3935 KASSERT(exfer->ex_isdone); 3936 #ifdef DIAGNOSTIC 3937 exfer->ex_isdone = false; 3938 #endif 3939 3940 /* Take lock here to protect nexttoggle */ 3941 mutex_enter(&sc->sc_lock); 3942 3943 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3944 3945 exfer->ex_sqtdend = end; 3946 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3947 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3948 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3949 3950 #ifdef EHCI_DEBUG 3951 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3952 ehci_dump_sqh(sqh); 3953 ehci_dump_sqtds(exfer->ex_sqtdstart); 3954 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3955 #endif 3956 3957 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3958 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3959 3960 /* also does usb_syncmem(sqh) */ 3961 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3962 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3963 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3964 ehci_timeout, xfer); 3965 } 3966 ehci_add_intr_list(sc, exfer); 3967 xfer->ux_status = USBD_IN_PROGRESS; 3968 mutex_exit(&sc->sc_lock); 3969 3970 #if 0 3971 #ifdef EHCI_DEBUG 3972 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3973 // delay(10000); 3974 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3975 ehci_dump_regs(sc); 3976 #if 0 3977 printf("async_head:\n"); 3978 ehci_dump_sqh(sc->sc_async_head); 3979 #endif 3980 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3981 ehci_dump_sqh(sqh); 3982 ehci_dump_sqtds(exfer->ex_sqtdstart); 3983 #endif 3984 #endif 3985 3986 if (sc->sc_bus.ub_usepolling) 3987 ehci_waitintr(sc, xfer); 3988 3989 return USBD_IN_PROGRESS; 3990 } 3991 3992 Static void 3993 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3994 { 3995 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3996 3997 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3998 ehci_abort_xfer(xfer, USBD_CANCELLED); 3999 } 4000 4001 /* 4002 * Close a device bulk pipe. 4003 */ 4004 Static void 4005 ehci_device_bulk_close(struct usbd_pipe *pipe) 4006 { 4007 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4008 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4009 4010 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4011 4012 KASSERT(mutex_owned(&sc->sc_lock)); 4013 4014 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 4015 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4016 ehci_close_pipe(pipe, sc->sc_async_head); 4017 } 4018 4019 Static void 4020 ehci_device_bulk_done(struct usbd_xfer *xfer) 4021 { 4022 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4023 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4024 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4025 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4026 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4027 4028 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4029 4030 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4031 0, 0); 4032 4033 KASSERT(mutex_owned(&sc->sc_lock)); 4034 4035 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4036 ehci_del_intr_list(sc, ex); /* remove from active list */ 4037 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4038 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4039 } 4040 4041 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 4042 } 4043 4044 /************************/ 4045 4046 Static usbd_status 4047 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4048 { 4049 struct ehci_soft_islot *isp; 4050 int islot, lev; 4051 4052 /* Find a poll rate that is large enough. */ 4053 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4054 if (EHCI_ILEV_IVAL(lev) <= ival) 4055 break; 4056 4057 /* Pick an interrupt slot at the right level. */ 4058 /* XXX could do better than picking at random */ 4059 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4060 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4061 4062 sqh->islot = islot; 4063 isp = &sc->sc_islots[islot]; 4064 mutex_enter(&sc->sc_lock); 4065 ehci_add_qh(sc, sqh, isp->sqh); 4066 mutex_exit(&sc->sc_lock); 4067 4068 return USBD_NORMAL_COMPLETION; 4069 } 4070 4071 4072 Static int 4073 ehci_device_intr_init(struct usbd_xfer *xfer) 4074 { 4075 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4076 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4077 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4078 int endpt = ed->bEndpointAddress; 4079 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4080 int len = xfer->ux_bufsize; 4081 int err; 4082 4083 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4084 4085 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4086 xfer->ux_flags, 0); 4087 4088 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4089 KASSERT(len != 0); 4090 4091 exfer->ex_type = EX_INTR; 4092 exfer->ex_nsqtd = 0; 4093 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4094 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 4095 4096 return err; 4097 } 4098 4099 Static void 4100 ehci_device_intr_fini(struct usbd_xfer *xfer) 4101 { 4102 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4103 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4104 4105 KASSERT(ex->ex_type == EX_INTR); 4106 4107 ehci_free_sqtds(sc, ex); 4108 if (ex->ex_nsqtd) 4109 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4110 } 4111 4112 Static usbd_status 4113 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4114 { 4115 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4116 usbd_status err; 4117 4118 /* Insert last in queue. */ 4119 mutex_enter(&sc->sc_lock); 4120 err = usb_insert_transfer(xfer); 4121 mutex_exit(&sc->sc_lock); 4122 if (err) 4123 return err; 4124 4125 /* 4126 * Pipe isn't running (otherwise err would be USBD_INPROG), 4127 * so start it first. 4128 */ 4129 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4130 } 4131 4132 Static usbd_status 4133 ehci_device_intr_start(struct usbd_xfer *xfer) 4134 { 4135 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4136 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4137 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4138 ehci_soft_qtd_t *end; 4139 ehci_soft_qh_t *sqh; 4140 int len, isread, endpt; 4141 4142 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4143 4144 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4145 xfer->ux_flags, 0); 4146 4147 if (sc->sc_dying) 4148 return USBD_IOERROR; 4149 4150 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4151 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4152 4153 len = xfer->ux_length; 4154 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4155 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4156 sqh = epipe->sqh; 4157 4158 KASSERT(exfer->ex_isdone); 4159 #ifdef DIAGNOSTIC 4160 exfer->ex_isdone = false; 4161 #endif 4162 4163 /* Take lock to protect nexttoggle */ 4164 mutex_enter(&sc->sc_lock); 4165 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4166 4167 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4168 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4169 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4170 exfer->ex_sqtdend = end; 4171 4172 #ifdef EHCI_DEBUG 4173 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 4174 ehci_dump_sqh(sqh); 4175 ehci_dump_sqtds(exfer->ex_sqtdstart); 4176 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 4177 #endif 4178 4179 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4180 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4181 4182 /* also does usb_syncmem(sqh) */ 4183 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4184 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4185 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4186 ehci_timeout, xfer); 4187 } 4188 ehci_add_intr_list(sc, exfer); 4189 xfer->ux_status = USBD_IN_PROGRESS; 4190 mutex_exit(&sc->sc_lock); 4191 4192 #if 0 4193 #ifdef EHCI_DEBUG 4194 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4195 // delay(10000); 4196 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4197 ehci_dump_regs(sc); 4198 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4199 ehci_dump_sqh(sqh); 4200 ehci_dump_sqtds(exfer->ex_sqtdstart); 4201 #endif 4202 #endif 4203 4204 if (sc->sc_bus.ub_usepolling) 4205 ehci_waitintr(sc, xfer); 4206 4207 return USBD_IN_PROGRESS; 4208 } 4209 4210 Static void 4211 ehci_device_intr_abort(struct usbd_xfer *xfer) 4212 { 4213 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4214 4215 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4216 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4217 4218 /* 4219 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4220 * async doorbell. That's dependent on the async list, wheras 4221 * intr xfers are periodic, should not use this? 4222 */ 4223 ehci_abort_xfer(xfer, USBD_CANCELLED); 4224 } 4225 4226 Static void 4227 ehci_device_intr_close(struct usbd_pipe *pipe) 4228 { 4229 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4230 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4231 struct ehci_soft_islot *isp; 4232 4233 KASSERT(mutex_owned(&sc->sc_lock)); 4234 4235 isp = &sc->sc_islots[epipe->sqh->islot]; 4236 ehci_close_pipe(pipe, isp->sqh); 4237 } 4238 4239 Static void 4240 ehci_device_intr_done(struct usbd_xfer *xfer) 4241 { 4242 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4243 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4244 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4245 ehci_soft_qh_t *sqh; 4246 int len, isread, endpt; 4247 4248 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4249 4250 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4251 0, 0); 4252 4253 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4254 4255 if (xfer->ux_pipe->up_repeat) { 4256 4257 KASSERT(exfer->ex_isdone); 4258 #ifdef DIAGNOSTIC 4259 exfer->ex_isdone = false; 4260 #endif 4261 4262 len = xfer->ux_length; 4263 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4264 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4265 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4266 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4267 sqh = epipe->sqh; 4268 4269 ehci_soft_qtd_t *end; 4270 ehci_reset_sqtd_chain(sc, xfer, len, isread, 4271 &epipe->nexttoggle, &end); 4272 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4273 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4274 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4275 4276 exfer->ex_sqtdend = end; 4277 4278 /* also does usb_syncmem(sqh) */ 4279 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4280 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4281 callout_reset(&xfer->ux_callout, 4282 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4283 } 4284 4285 xfer->ux_status = USBD_IN_PROGRESS; 4286 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4287 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4288 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4289 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4290 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4291 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4292 } 4293 } 4294 4295 /************************/ 4296 Static int 4297 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4298 { 4299 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4300 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4301 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4302 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4303 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4304 int i, k, frames; 4305 u_int huba, dir; 4306 int err; 4307 4308 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4309 4310 start = NULL; 4311 sitd = NULL; 4312 4313 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", xfer, xfer->ux_length, 4314 xfer->ux_flags, 0); 4315 4316 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4317 KASSERT(xfer->ux_nframes != 0); 4318 KASSERT(exfer->ex_isdone); 4319 4320 exfer->ex_type = EX_FS_ISOC; 4321 /* 4322 * Step 1: Allocate and initialize sitds. 4323 */ 4324 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4325 if (i > 16 || i == 0) { 4326 /* Spec page 271 says intervals > 16 are invalid */ 4327 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4328 4329 return EINVAL; 4330 } 4331 4332 frames = xfer->ux_nframes; 4333 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4334 sitd = ehci_alloc_sitd(sc); 4335 if (sitd == NULL) { 4336 err = ENOMEM; 4337 goto fail; 4338 } 4339 4340 if (prev) 4341 prev->xfer_next = sitd; 4342 else 4343 start = sitd; 4344 4345 huba = dev->ud_myhsport->up_parent->ud_addr; 4346 4347 #if 0 4348 if (sc->sc_flags & EHCIF_FREESCALE) { 4349 // Set hub address to 0 if embedded TT is used. 4350 if (huba == sc->sc_addr) 4351 huba = 0; 4352 } 4353 #endif 4354 4355 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4356 dir = UE_GET_DIR(k) ? 1 : 0; 4357 sitd->sitd.sitd_endp = 4358 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4359 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4360 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4361 EHCI_SITD_SET_HUBA(huba) | 4362 EHCI_SITD_SET_DIR(dir)); 4363 4364 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4365 } /* End of frame */ 4366 4367 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4368 4369 stop = sitd; 4370 stop->xfer_next = NULL; 4371 exfer->ex_sitdstart = start; 4372 exfer->ex_sitdend = stop; 4373 4374 return 0; 4375 4376 fail: 4377 mutex_enter(&sc->sc_lock); 4378 ehci_soft_sitd_t *next; 4379 for (sitd = start; sitd; sitd = next) { 4380 next = sitd->xfer_next; 4381 ehci_free_sitd_locked(sc, sitd); 4382 } 4383 mutex_exit(&sc->sc_lock); 4384 4385 return err; 4386 } 4387 4388 Static void 4389 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4390 { 4391 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4392 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4393 4394 KASSERT(ex->ex_type == EX_FS_ISOC); 4395 4396 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4397 } 4398 4399 Static usbd_status 4400 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4401 { 4402 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4403 usbd_status err; 4404 4405 mutex_enter(&sc->sc_lock); 4406 err = usb_insert_transfer(xfer); 4407 mutex_exit(&sc->sc_lock); 4408 4409 if (err && err != USBD_IN_PROGRESS) 4410 return err; 4411 4412 return ehci_device_fs_isoc_start(xfer); 4413 } 4414 4415 Static usbd_status 4416 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4417 { 4418 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4419 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4420 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4421 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4422 ehci_soft_sitd_t *sitd; 4423 usb_dma_t *dma_buf; 4424 int i, j, k, frames; 4425 int offs, total_length; 4426 int frindex; 4427 u_int dir; 4428 4429 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4430 4431 sitd = NULL; 4432 total_length = 0; 4433 4434 /* 4435 * To allow continuous transfers, above we start all transfers 4436 * immediately. However, we're still going to get usbd_start_next call 4437 * this when another xfer completes. So, check if this is already 4438 * in progress or not 4439 */ 4440 4441 if (exfer->ex_isrunning) { 4442 return USBD_IN_PROGRESS; 4443 } 4444 4445 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4446 xfer, xfer->ux_length, xfer->ux_flags, 0); 4447 4448 if (sc->sc_dying) 4449 return USBD_IOERROR; 4450 4451 /* 4452 * To avoid complication, don't allow a request right now that'll span 4453 * the entire frame table. To within 4 frames, to allow some leeway 4454 * on either side of where the hc currently is. 4455 */ 4456 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4457 xfer->ux_nframes >= sc->sc_flsize - 4) { 4458 printf("ehci: isoc descriptor requested that spans the entire" 4459 "frametable, too many frames\n"); 4460 return USBD_INVAL; 4461 } 4462 4463 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4464 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4465 KASSERT(exfer->ex_isdone); 4466 #ifdef DIAGNOSTIC 4467 exfer->ex_isdone = false; 4468 #endif 4469 4470 /* 4471 * Step 1: Initialize sitds. 4472 */ 4473 4474 frames = xfer->ux_nframes; 4475 dma_buf = &xfer->ux_dmabuf; 4476 offs = 0; 4477 4478 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4479 i++, sitd = sitd->xfer_next) { 4480 KASSERT(sitd != NULL); 4481 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4482 4483 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4484 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4485 4486 /* Set page0 index and offset - TP and T-offset are set below */ 4487 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4488 4489 total_length += xfer->ux_frlengths[i]; 4490 offs += xfer->ux_frlengths[i]; 4491 4492 sitd->sitd.sitd_buffer[1] = 4493 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4494 4495 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4496 4497 #if 0 4498 if (sc->sc_flags & EHCIF_FREESCALE) { 4499 // Set hub address to 0 if embedded TT is used. 4500 if (huba == sc->sc_addr) 4501 huba = 0; 4502 } 4503 #endif 4504 4505 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4506 dir = UE_GET_DIR(k) ? 1 : 0; 4507 KASSERT(sitd->sitd.sitd_endp == htole32( 4508 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4509 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4510 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4511 EHCI_SITD_SET_HUBA(huba) | 4512 EHCI_SITD_SET_DIR(dir))); 4513 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4514 4515 uint8_t sa = 0; 4516 uint8_t sb = 0; 4517 u_int temp, tlen; 4518 4519 if (dir == 0) { /* OUT */ 4520 temp = 0; 4521 tlen = xfer->ux_frlengths[i]; 4522 if (tlen <= 188) { 4523 temp |= 1; /* T-count = 1, TP = ALL */ 4524 tlen = 1; 4525 } else { 4526 tlen += 187; 4527 tlen /= 188; 4528 temp |= tlen; /* T-count = [1..6] */ 4529 temp |= 8; /* TP = Begin */ 4530 } 4531 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4532 4533 tlen += sa; 4534 4535 if (tlen >= 8) { 4536 sb = 0; 4537 } else { 4538 sb = (1 << tlen); 4539 } 4540 4541 sa = (1 << sa); 4542 sa = (sb - sa) & 0x3F; 4543 sb = 0; 4544 } else { 4545 sb = (-(4 << sa)) & 0xFE; 4546 sa = (1 << sa) & 0x3F; 4547 sa = 0x01; 4548 sb = 0xfc; 4549 } 4550 4551 sitd->sitd.sitd_sched = htole32( 4552 EHCI_SITD_SET_SMASK(sa) | 4553 EHCI_SITD_SET_CMASK(sb) 4554 ); 4555 4556 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4557 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4558 } /* End of frame */ 4559 4560 sitd = exfer->ex_sitdend; 4561 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4562 4563 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4564 sizeof(sitd->sitd.sitd_trans), 4565 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4566 4567 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4568 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4569 4570 /* 4571 * Part 2: Transfer descriptors have now been set up, now they must 4572 * be scheduled into the periodic frame list. Erk. Not wanting to 4573 * complicate matters, transfer is denied if the transfer spans 4574 * more than the period frame list. 4575 */ 4576 4577 mutex_enter(&sc->sc_lock); 4578 4579 /* Start inserting frames */ 4580 if (epipe->isoc.cur_xfers > 0) { 4581 frindex = epipe->isoc.next_frame; 4582 } else { 4583 frindex = EOREAD4(sc, EHCI_FRINDEX); 4584 frindex = frindex >> 3; /* Erase microframe index */ 4585 frindex += 2; 4586 } 4587 4588 if (frindex >= sc->sc_flsize) 4589 frindex &= (sc->sc_flsize - 1); 4590 4591 /* Whats the frame interval? */ 4592 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4593 4594 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4595 j++, sitd = sitd->xfer_next) { 4596 KASSERT(sitd); 4597 4598 usb_syncmem(&sc->sc_fldma, 4599 sizeof(ehci_link_t) * frindex, 4600 sizeof(ehci_link_t), 4601 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4602 4603 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4604 if (sitd->sitd.sitd_next == 0) 4605 /* 4606 * FIXME: frindex table gets initialized to NULL 4607 * or EHCI_NULL? 4608 */ 4609 sitd->sitd.sitd_next = EHCI_NULL; 4610 4611 usb_syncmem(&sitd->dma, 4612 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4613 sizeof(ehci_sitd_t), 4614 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4615 4616 sc->sc_flist[frindex] = 4617 htole32(EHCI_LINK_SITD | sitd->physaddr); 4618 4619 usb_syncmem(&sc->sc_fldma, 4620 sizeof(ehci_link_t) * frindex, 4621 sizeof(ehci_link_t), 4622 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4623 4624 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4625 sc->sc_softsitds[frindex] = sitd; 4626 if (sitd->frame_list.next != NULL) 4627 sitd->frame_list.next->frame_list.prev = sitd; 4628 sitd->slot = frindex; 4629 sitd->frame_list.prev = NULL; 4630 4631 frindex += i; 4632 if (frindex >= sc->sc_flsize) 4633 frindex -= sc->sc_flsize; 4634 } 4635 4636 epipe->isoc.cur_xfers++; 4637 epipe->isoc.next_frame = frindex; 4638 4639 exfer->ex_isrunning = true; 4640 4641 ehci_add_intr_list(sc, exfer); 4642 xfer->ux_status = USBD_IN_PROGRESS; 4643 4644 mutex_exit(&sc->sc_lock); 4645 4646 if (sc->sc_bus.ub_usepolling) { 4647 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4648 ehci_waitintr(sc, xfer); 4649 } 4650 4651 return USBD_IN_PROGRESS; 4652 } 4653 4654 Static void 4655 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4656 { 4657 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4658 4659 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4660 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4661 } 4662 4663 Static void 4664 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4665 { 4666 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4667 4668 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4669 } 4670 4671 Static void 4672 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4673 { 4674 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4675 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4676 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4677 4678 KASSERT(mutex_owned(&sc->sc_lock)); 4679 4680 epipe->isoc.cur_xfers--; 4681 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4682 ehci_del_intr_list(sc, exfer); 4683 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4684 exfer->ex_isrunning = false; 4685 } 4686 4687 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4688 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4689 } 4690 4691 4692 /************************/ 4693 4694 4695 Static int 4696 ehci_device_isoc_init(struct usbd_xfer *xfer) 4697 { 4698 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4699 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4700 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4701 ehci_soft_itd_t *itd, *prev, *start, *stop; 4702 int i, j, k; 4703 int frames, ufrperframe; 4704 int err; 4705 4706 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4707 4708 start = NULL; 4709 prev = NULL; 4710 itd = NULL; 4711 4712 KASSERT(xfer->ux_nframes != 0); 4713 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4714 KASSERT(exfer->ex_isdone); 4715 4716 exfer->ex_type = EX_ISOC; 4717 4718 /* 4719 * Step 1: Allocate and initialize itds, how many do we need? 4720 * One per transfer if interval >= 8 microframes, less if we use 4721 * multiple microframes per frame. 4722 */ 4723 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4724 if (i > 16 || i == 0) { 4725 /* Spec page 271 says intervals > 16 are invalid */ 4726 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4727 return USBD_INVAL; 4728 } 4729 4730 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4731 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4732 4733 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4734 itd = ehci_alloc_itd(sc); 4735 if (itd == NULL) { 4736 err = ENOMEM; 4737 goto fail; 4738 } 4739 4740 if (prev != NULL) { 4741 /* Maybe not as it's updated by the scheduling? */ 4742 prev->itd.itd_next = 4743 htole32(itd->physaddr | EHCI_LINK_ITD); 4744 4745 prev->xfer_next = itd; 4746 } else { 4747 start = itd; 4748 } 4749 4750 /* 4751 * Other special values 4752 */ 4753 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4754 itd->itd.itd_bufr[0] = htole32( 4755 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4756 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4757 4758 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4759 ? 1 : 0; 4760 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4761 itd->itd.itd_bufr[1] |= htole32( 4762 EHCI_ITD_SET_DIR(k) | 4763 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4764 4765 /* FIXME: handle invalid trans - should be done in openpipe */ 4766 itd->itd.itd_bufr[2] |= 4767 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4768 } /* End of frame */ 4769 4770 stop = itd; 4771 stop->xfer_next = NULL; 4772 4773 exfer->ex_itdstart = start; 4774 exfer->ex_itdend = stop; 4775 4776 return 0; 4777 fail: 4778 mutex_enter(&sc->sc_lock); 4779 ehci_soft_itd_t *next; 4780 for (itd = start; itd; itd = next) { 4781 next = itd->xfer_next; 4782 ehci_free_itd_locked(sc, itd); 4783 } 4784 mutex_exit(&sc->sc_lock); 4785 4786 return err; 4787 4788 } 4789 4790 Static void 4791 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4792 { 4793 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4794 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4795 4796 KASSERT(ex->ex_type == EX_ISOC); 4797 4798 ehci_free_itd_chain(sc, ex->ex_itdstart); 4799 } 4800 4801 Static usbd_status 4802 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4803 { 4804 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4805 usbd_status err; 4806 4807 mutex_enter(&sc->sc_lock); 4808 err = usb_insert_transfer(xfer); 4809 mutex_exit(&sc->sc_lock); 4810 if (err && err != USBD_IN_PROGRESS) 4811 return err; 4812 4813 return ehci_device_isoc_start(xfer); 4814 } 4815 4816 Static usbd_status 4817 ehci_device_isoc_start(struct usbd_xfer *xfer) 4818 { 4819 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4820 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4821 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4822 ehci_soft_itd_t *itd, *prev; 4823 usb_dma_t *dma_buf; 4824 int i, j; 4825 int frames, uframes, ufrperframe; 4826 int trans_count, offs, total_length; 4827 int frindex; 4828 4829 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4830 4831 prev = NULL; 4832 itd = NULL; 4833 trans_count = 0; 4834 total_length = 0; 4835 4836 /* 4837 * To allow continuous transfers, above we start all transfers 4838 * immediately. However, we're still going to get usbd_start_next call 4839 * this when another xfer completes. So, check if this is already 4840 * in progress or not 4841 */ 4842 4843 if (exfer->ex_isrunning) { 4844 return USBD_IN_PROGRESS; 4845 } 4846 4847 USBHIST_LOG(ehcidebug, "xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4848 4849 if (sc->sc_dying) 4850 return USBD_IOERROR; 4851 4852 /* 4853 * To avoid complication, don't allow a request right now that'll span 4854 * the entire frame table. To within 4 frames, to allow some leeway 4855 * on either side of where the hc currently is. 4856 */ 4857 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4858 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4859 USBHIST_LOG(ehcidebug, 4860 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4861 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4862 return USBD_INVAL; 4863 } 4864 4865 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4866 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4867 KASSERT(exfer->ex_isdone); 4868 #ifdef DIAGNOSTIC 4869 exfer->ex_isdone = false; 4870 #endif 4871 4872 /* 4873 * Step 1: Re-Initialize itds 4874 */ 4875 4876 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4877 if (i > 16 || i == 0) { 4878 /* Spec page 271 says intervals > 16 are invalid */ 4879 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4880 return USBD_INVAL; 4881 } 4882 4883 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4884 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4885 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4886 4887 if (frames == 0) { 4888 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4889 return USBD_INVAL; 4890 } 4891 4892 dma_buf = &xfer->ux_dmabuf; 4893 offs = 0; 4894 4895 itd = exfer->ex_itdstart; 4896 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4897 int froffs = offs; 4898 4899 if (prev != NULL) { 4900 prev->itd.itd_next = 4901 htole32(itd->physaddr | EHCI_LINK_ITD); 4902 usb_syncmem(&prev->dma, 4903 prev->offs + offsetof(ehci_itd_t, itd_next), 4904 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4905 prev->xfer_next = itd; 4906 } 4907 4908 /* 4909 * Step 1.5, initialize uframes 4910 */ 4911 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4912 /* Calculate which page in the list this starts in */ 4913 int addr = DMAADDR(dma_buf, froffs); 4914 addr = EHCI_PAGE_OFFSET(addr); 4915 addr += (offs - froffs); 4916 addr = EHCI_PAGE(addr); 4917 addr /= EHCI_PAGE_SIZE; 4918 4919 /* 4920 * This gets the initial offset into the first page, 4921 * looks how far further along the current uframe 4922 * offset is. Works out how many pages that is. 4923 */ 4924 4925 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4926 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4927 EHCI_ITD_SET_PG(addr) | 4928 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4929 4930 total_length += xfer->ux_frlengths[trans_count]; 4931 offs += xfer->ux_frlengths[trans_count]; 4932 trans_count++; 4933 4934 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4935 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4936 break; 4937 } 4938 } 4939 4940 /* 4941 * Step 1.75, set buffer pointers. To simplify matters, all 4942 * pointers are filled out for the next 7 hardware pages in 4943 * the dma block, so no need to worry what pages to cover 4944 * and what to not. 4945 */ 4946 4947 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4948 /* 4949 * Don't try to lookup a page that's past the end 4950 * of buffer 4951 */ 4952 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4953 if (page_offs >= dma_buf->udma_block->size) 4954 break; 4955 4956 uint64_t page = DMAADDR(dma_buf, page_offs); 4957 page = EHCI_PAGE(page); 4958 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4959 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4960 } 4961 /* 4962 * Other special values 4963 */ 4964 4965 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4966 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4967 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4968 4969 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4970 ? 1 : 0; 4971 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4972 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4973 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4974 4975 /* FIXME: handle invalid trans */ 4976 itd->itd.itd_bufr[2] |= 4977 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4978 4979 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4980 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4981 4982 prev = itd; 4983 } /* End of frame */ 4984 4985 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4986 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4987 4988 /* 4989 * Part 2: Transfer descriptors have now been set up, now they must 4990 * be scheduled into the period frame list. Erk. Not wanting to 4991 * complicate matters, transfer is denied if the transfer spans 4992 * more than the period frame list. 4993 */ 4994 4995 mutex_enter(&sc->sc_lock); 4996 4997 /* Start inserting frames */ 4998 if (epipe->isoc.cur_xfers > 0) { 4999 frindex = epipe->isoc.next_frame; 5000 } else { 5001 frindex = EOREAD4(sc, EHCI_FRINDEX); 5002 frindex = frindex >> 3; /* Erase microframe index */ 5003 frindex += 2; 5004 } 5005 5006 if (frindex >= sc->sc_flsize) 5007 frindex &= (sc->sc_flsize - 1); 5008 5009 /* What's the frame interval? */ 5010 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 5011 if (i / USB_UFRAMES_PER_FRAME == 0) 5012 i = 1; 5013 else 5014 i /= USB_UFRAMES_PER_FRAME; 5015 5016 itd = exfer->ex_itdstart; 5017 for (j = 0; j < frames; j++) { 5018 KASSERTMSG(itd != NULL, "frame %d\n", j); 5019 5020 usb_syncmem(&sc->sc_fldma, 5021 sizeof(ehci_link_t) * frindex, 5022 sizeof(ehci_link_t), 5023 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5024 5025 itd->itd.itd_next = sc->sc_flist[frindex]; 5026 if (itd->itd.itd_next == 0) 5027 /* 5028 * FIXME: frindex table gets initialized to NULL 5029 * or EHCI_NULL? 5030 */ 5031 itd->itd.itd_next = EHCI_NULL; 5032 5033 usb_syncmem(&itd->dma, 5034 itd->offs + offsetof(ehci_itd_t, itd_next), 5035 sizeof(itd->itd.itd_next), 5036 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5037 5038 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 5039 5040 usb_syncmem(&sc->sc_fldma, 5041 sizeof(ehci_link_t) * frindex, 5042 sizeof(ehci_link_t), 5043 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5044 5045 itd->frame_list.next = sc->sc_softitds[frindex]; 5046 sc->sc_softitds[frindex] = itd; 5047 if (itd->frame_list.next != NULL) 5048 itd->frame_list.next->frame_list.prev = itd; 5049 itd->slot = frindex; 5050 itd->frame_list.prev = NULL; 5051 5052 frindex += i; 5053 if (frindex >= sc->sc_flsize) 5054 frindex -= sc->sc_flsize; 5055 5056 itd = itd->xfer_next; 5057 } 5058 5059 epipe->isoc.cur_xfers++; 5060 epipe->isoc.next_frame = frindex; 5061 5062 exfer->ex_isrunning = true; 5063 5064 ehci_add_intr_list(sc, exfer); 5065 xfer->ux_status = USBD_IN_PROGRESS; 5066 5067 mutex_exit(&sc->sc_lock); 5068 5069 if (sc->sc_bus.ub_usepolling) { 5070 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 5071 ehci_waitintr(sc, xfer); 5072 } 5073 5074 return USBD_IN_PROGRESS; 5075 } 5076 5077 Static void 5078 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5079 { 5080 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5081 5082 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 5083 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5084 } 5085 5086 Static void 5087 ehci_device_isoc_close(struct usbd_pipe *pipe) 5088 { 5089 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5090 5091 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 5092 } 5093 5094 Static void 5095 ehci_device_isoc_done(struct usbd_xfer *xfer) 5096 { 5097 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5098 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5099 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5100 5101 KASSERT(mutex_owned(&sc->sc_lock)); 5102 5103 epipe->isoc.cur_xfers--; 5104 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 5105 ehci_del_intr_list(sc, exfer); 5106 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5107 exfer->ex_isrunning = false; 5108 } 5109 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5110 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5111 } 5112
Indexes created Wed Oct 01 19:09:53 GMT 2025