ehci.c revision 1.234.2.83
1 /* $NetBSD: ehci.c,v 1.234.2.83 2016/02/06 10:21:45 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.83 2016/02/06 10:21:45 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 /* Control pipe */ 136 struct { 137 usb_dma_t reqdma; 138 } ctrl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Iso pipe */ 144 struct { 145 u_int next_frame; 146 u_int cur_xfers; 147 } isoc; 148 }; 149 }; 150 151 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 152 153 Static usbd_status ehci_open(struct usbd_pipe *); 154 Static void ehci_poll(struct usbd_bus *); 155 Static void ehci_softintr(void *); 156 Static int ehci_intr1(ehci_softc_t *); 157 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 158 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 159 ex_completeq_t *); 160 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 161 ex_completeq_t *); 162 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 165 Static void ehci_timeout(void *); 166 Static void ehci_timeout_task(void *); 167 Static void ehci_intrlist_timeout(void *); 168 Static void ehci_doorbell(void *); 169 Static void ehci_pcd(void *); 170 171 Static struct usbd_xfer * 172 ehci_allocx(struct usbd_bus *, unsigned int); 173 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 174 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 180 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 181 Static void ehci_root_intr_abort(struct usbd_xfer *); 182 Static void ehci_root_intr_close(struct usbd_pipe *); 183 Static void ehci_root_intr_done(struct usbd_xfer *); 184 185 Static int ehci_device_ctrl_init(struct usbd_xfer *); 186 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 187 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 188 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 189 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 190 Static void ehci_device_ctrl_close(struct usbd_pipe *); 191 Static void ehci_device_ctrl_done(struct usbd_xfer *); 192 193 Static int ehci_device_bulk_init(struct usbd_xfer *); 194 Static void ehci_device_bulk_fini(struct usbd_xfer *); 195 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 196 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 197 Static void ehci_device_bulk_abort(struct usbd_xfer *); 198 Static void ehci_device_bulk_close(struct usbd_pipe *); 199 Static void ehci_device_bulk_done(struct usbd_xfer *); 200 201 Static int ehci_device_intr_init(struct usbd_xfer *); 202 Static void ehci_device_intr_fini(struct usbd_xfer *); 203 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 204 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 205 Static void ehci_device_intr_abort(struct usbd_xfer *); 206 Static void ehci_device_intr_close(struct usbd_pipe *); 207 Static void ehci_device_intr_done(struct usbd_xfer *); 208 209 Static int ehci_device_isoc_init(struct usbd_xfer *); 210 Static void ehci_device_isoc_fini(struct usbd_xfer *); 211 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 212 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 213 Static void ehci_device_isoc_abort(struct usbd_xfer *); 214 Static void ehci_device_isoc_close(struct usbd_pipe *); 215 Static void ehci_device_isoc_done(struct usbd_xfer *); 216 217 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 218 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 219 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 220 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 223 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 224 225 Static void ehci_device_clear_toggle(struct usbd_pipe *); 226 Static void ehci_noop(struct usbd_pipe *); 227 228 Static void ehci_disown(ehci_softc_t *, int, int); 229 230 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 231 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 232 233 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 234 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 235 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 236 int, int, ehci_soft_qtd_t **, ehci_soft_qtd_t **); 237 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 238 239 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 240 int, int, int *, ehci_soft_qtd_t **); 241 242 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 243 Static ehci_soft_sitd_t * 244 ehci_alloc_sitd(ehci_softc_t *); 245 246 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 247 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 248 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 249 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 250 251 static inline void 252 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 253 { 254 255 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 256 } 257 258 static inline void 259 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 260 { 261 262 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 263 } 264 265 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 266 267 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 268 int); 269 270 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 271 ehci_soft_qh_t *); 272 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 273 ehci_soft_qh_t *); 274 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 275 Static void ehci_sync_hc(ehci_softc_t *); 276 277 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 278 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 279 280 #ifdef EHCI_DEBUG 281 Static ehci_softc_t *theehci; 282 void ehci_dump(void); 283 #endif 284 285 #ifdef EHCI_DEBUG 286 Static void ehci_dump_regs(ehci_softc_t *); 287 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 288 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 289 Static void ehci_dump_qtd(ehci_qtd_t *); 290 Static void ehci_dump_sqh(ehci_soft_qh_t *); 291 Static void ehci_dump_sitd(struct ehci_soft_itd *); 292 Static void ehci_dump_itds(ehci_soft_itd_t *); 293 Static void ehci_dump_itd(struct ehci_soft_itd *); 294 Static void ehci_dump_exfer(struct ehci_xfer *); 295 #endif 296 297 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 298 299 static inline void 300 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 301 { 302 303 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 304 } 305 306 static inline void 307 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 308 { 309 310 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 311 } 312 313 Static const struct usbd_bus_methods ehci_bus_methods = { 314 .ubm_open = ehci_open, 315 .ubm_softint = ehci_softintr, 316 .ubm_dopoll = ehci_poll, 317 .ubm_allocx = ehci_allocx, 318 .ubm_freex = ehci_freex, 319 .ubm_getlock = ehci_get_lock, 320 .ubm_rhctrl = ehci_roothub_ctrl, 321 }; 322 323 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 324 .upm_transfer = ehci_root_intr_transfer, 325 .upm_start = ehci_root_intr_start, 326 .upm_abort = ehci_root_intr_abort, 327 .upm_close = ehci_root_intr_close, 328 .upm_cleartoggle = ehci_noop, 329 .upm_done = ehci_root_intr_done, 330 }; 331 332 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 333 .upm_init = ehci_device_ctrl_init, 334 .upm_fini = ehci_device_ctrl_fini, 335 .upm_transfer = ehci_device_ctrl_transfer, 336 .upm_start = ehci_device_ctrl_start, 337 .upm_abort = ehci_device_ctrl_abort, 338 .upm_close = ehci_device_ctrl_close, 339 .upm_cleartoggle = ehci_noop, 340 .upm_done = ehci_device_ctrl_done, 341 }; 342 343 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 344 .upm_init = ehci_device_intr_init, 345 .upm_fini = ehci_device_intr_fini, 346 .upm_transfer = ehci_device_intr_transfer, 347 .upm_start = ehci_device_intr_start, 348 .upm_abort = ehci_device_intr_abort, 349 .upm_close = ehci_device_intr_close, 350 .upm_cleartoggle = ehci_device_clear_toggle, 351 .upm_done = ehci_device_intr_done, 352 }; 353 354 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 355 .upm_init = ehci_device_bulk_init, 356 .upm_fini = ehci_device_bulk_fini, 357 .upm_transfer = ehci_device_bulk_transfer, 358 .upm_start = ehci_device_bulk_start, 359 .upm_abort = ehci_device_bulk_abort, 360 .upm_close = ehci_device_bulk_close, 361 .upm_cleartoggle = ehci_device_clear_toggle, 362 .upm_done = ehci_device_bulk_done, 363 }; 364 365 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 366 .upm_init = ehci_device_isoc_init, 367 .upm_fini = ehci_device_isoc_fini, 368 .upm_transfer = ehci_device_isoc_transfer, 369 .upm_start = ehci_device_isoc_start, 370 .upm_abort = ehci_device_isoc_abort, 371 .upm_close = ehci_device_isoc_close, 372 .upm_cleartoggle = ehci_noop, 373 .upm_done = ehci_device_isoc_done, 374 }; 375 376 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 377 .upm_init = ehci_device_fs_isoc_init, 378 .upm_fini = ehci_device_fs_isoc_fini, 379 .upm_transfer = ehci_device_fs_isoc_transfer, 380 .upm_start = ehci_device_fs_isoc_start, 381 .upm_abort = ehci_device_fs_isoc_abort, 382 .upm_close = ehci_device_fs_isoc_close, 383 .upm_cleartoggle = ehci_noop, 384 .upm_done = ehci_device_fs_isoc_done, 385 }; 386 387 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 388 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 389 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 390 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 391 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 392 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 393 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 394 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 395 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 396 }; 397 398 int 399 ehci_init(ehci_softc_t *sc) 400 { 401 uint32_t vers, sparams, cparams, hcr; 402 u_int i; 403 usbd_status err; 404 ehci_soft_qh_t *sqh; 405 u_int ncomp; 406 407 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 408 #ifdef EHCI_DEBUG 409 theehci = sc; 410 #endif 411 412 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 413 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 414 cv_init(&sc->sc_softwake_cv, "ehciab"); 415 cv_init(&sc->sc_doorbell, "ehcidi"); 416 417 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 418 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 419 420 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 421 ehci_doorbell, sc); 422 KASSERT(sc->sc_doorbell_si != NULL); 423 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 424 ehci_pcd, sc); 425 KASSERT(sc->sc_pcd_si != NULL); 426 427 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 428 429 vers = EREAD2(sc, EHCI_HCIVERSION); 430 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 431 vers >> 8, vers & 0xff); 432 433 sparams = EREAD4(sc, EHCI_HCSPARAMS); 434 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 435 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 436 ncomp = EHCI_HCS_N_CC(sparams); 437 if (ncomp != sc->sc_ncomp) { 438 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 439 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 440 #if NOHCI == 0 || NUHCI == 0 441 aprint_error("%s: ohci or uhci probably not configured\n", 442 device_xname(sc->sc_dev)); 443 #endif 444 if (ncomp < sc->sc_ncomp) 445 sc->sc_ncomp = ncomp; 446 } 447 if (sc->sc_ncomp > 0) { 448 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 449 aprint_normal("%s: companion controller%s, %d port%s each:", 450 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 451 EHCI_HCS_N_PCC(sparams), 452 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 453 for (i = 0; i < sc->sc_ncomp; i++) 454 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 455 aprint_normal("\n"); 456 } 457 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 458 cparams = EREAD4(sc, EHCI_HCCPARAMS); 459 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 460 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 461 462 if (EHCI_HCC_64BIT(cparams)) { 463 /* MUST clear segment register if 64 bit capable. */ 464 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 465 } 466 467 sc->sc_bus.ub_revision = USBREV_2_0; 468 sc->sc_bus.ub_usedma = true; 469 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 470 471 /* Reset the controller */ 472 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 473 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 474 usb_delay_ms(&sc->sc_bus, 1); 475 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 476 for (i = 0; i < 100; i++) { 477 usb_delay_ms(&sc->sc_bus, 1); 478 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 479 if (!hcr) 480 break; 481 } 482 if (hcr) { 483 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 484 return EIO; 485 } 486 if (sc->sc_vendor_init) 487 sc->sc_vendor_init(sc); 488 489 /* XXX need proper intr scheduling */ 490 sc->sc_rand = 96; 491 492 /* frame list size at default, read back what we got and use that */ 493 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 494 case 0: sc->sc_flsize = 1024; break; 495 case 1: sc->sc_flsize = 512; break; 496 case 2: sc->sc_flsize = 256; break; 497 case 3: return EIO; 498 } 499 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 500 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 501 if (err) 502 return err; 503 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 504 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 505 506 for (i = 0; i < sc->sc_flsize; i++) { 507 sc->sc_flist[i] = EHCI_NULL; 508 } 509 510 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 511 512 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 513 KM_SLEEP); 514 if (sc->sc_softitds == NULL) 515 return ENOMEM; 516 LIST_INIT(&sc->sc_freeitds); 517 LIST_INIT(&sc->sc_freesitds); 518 TAILQ_INIT(&sc->sc_intrhead); 519 520 /* Set up the bus struct. */ 521 sc->sc_bus.ub_methods = &ehci_bus_methods; 522 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 523 524 sc->sc_eintrs = EHCI_NORMAL_INTRS; 525 526 /* 527 * Allocate the interrupt dummy QHs. These are arranged to give poll 528 * intervals that are powers of 2 times 1ms. 529 */ 530 for (i = 0; i < EHCI_INTRQHS; i++) { 531 sqh = ehci_alloc_sqh(sc); 532 if (sqh == NULL) { 533 err = ENOMEM; 534 goto bad1; 535 } 536 sc->sc_islots[i].sqh = sqh; 537 } 538 for (i = 0; i < EHCI_INTRQHS; i++) { 539 sqh = sc->sc_islots[i].sqh; 540 if (i == 0) { 541 /* The last (1ms) QH terminates. */ 542 sqh->qh.qh_link = EHCI_NULL; 543 sqh->next = NULL; 544 } else { 545 /* Otherwise the next QH has half the poll interval */ 546 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 547 sqh->qh.qh_link = htole32(sqh->next->physaddr | 548 EHCI_LINK_QH); 549 } 550 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 551 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 552 sqh->qh.qh_curqtd = EHCI_NULL; 553 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 554 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 555 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 556 sqh->sqtd = NULL; 557 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 559 } 560 /* Point the frame list at the last level (128ms). */ 561 for (i = 0; i < sc->sc_flsize; i++) { 562 int j; 563 564 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 565 revbits[i & (EHCI_MAX_POLLRATE-1)]; 566 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 567 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 568 i)].sqh->physaddr); 569 } 570 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 571 BUS_DMASYNC_PREWRITE); 572 573 /* Allocate dummy QH that starts the async list. */ 574 sqh = ehci_alloc_sqh(sc); 575 if (sqh == NULL) { 576 err = ENOMEM; 577 goto bad1; 578 } 579 /* Fill the QH */ 580 sqh->qh.qh_endp = 581 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 582 sqh->qh.qh_link = 583 htole32(sqh->physaddr | EHCI_LINK_QH); 584 sqh->qh.qh_curqtd = EHCI_NULL; 585 sqh->next = NULL; 586 /* Fill the overlay qTD */ 587 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 588 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 589 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 590 sqh->sqtd = NULL; 591 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 592 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 593 #ifdef EHCI_DEBUG 594 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 595 ehci_dump_sqh(sqh); 596 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 597 #endif 598 599 /* Point to async list */ 600 sc->sc_async_head = sqh; 601 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 602 603 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 604 605 /* Turn on controller */ 606 EOWRITE4(sc, EHCI_USBCMD, 607 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 608 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 609 EHCI_CMD_ASE | 610 EHCI_CMD_PSE | 611 EHCI_CMD_RS); 612 613 /* Take over port ownership */ 614 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 615 616 for (i = 0; i < 100; i++) { 617 usb_delay_ms(&sc->sc_bus, 1); 618 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 619 if (!hcr) 620 break; 621 } 622 if (hcr) { 623 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 624 return EIO; 625 } 626 627 /* Enable interrupts */ 628 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 629 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 630 631 return 0; 632 633 #if 0 634 bad2: 635 ehci_free_sqh(sc, sc->sc_async_head); 636 #endif 637 bad1: 638 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 639 return err; 640 } 641 642 int 643 ehci_intr(void *v) 644 { 645 ehci_softc_t *sc = v; 646 int ret = 0; 647 648 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 649 650 if (sc == NULL) 651 return 0; 652 653 mutex_spin_enter(&sc->sc_intr_lock); 654 655 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 656 goto done; 657 658 /* If we get an interrupt while polling, then just ignore it. */ 659 if (sc->sc_bus.ub_usepolling) { 660 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 661 662 if (intrs) 663 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 664 USBHIST_LOGN(ehcidebug, 16, 665 "ignored interrupt while polling", 0, 0, 0, 0); 666 goto done; 667 } 668 669 ret = ehci_intr1(sc); 670 671 done: 672 mutex_spin_exit(&sc->sc_intr_lock); 673 return ret; 674 } 675 676 Static int 677 ehci_intr1(ehci_softc_t *sc) 678 { 679 uint32_t intrs, eintrs; 680 681 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 682 683 /* In case the interrupt occurs before initialization has completed. */ 684 if (sc == NULL) { 685 #ifdef DIAGNOSTIC 686 printf("ehci_intr1: sc == NULL\n"); 687 #endif 688 return 0; 689 } 690 691 KASSERT(mutex_owned(&sc->sc_intr_lock)); 692 693 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 694 if (!intrs) 695 return 0; 696 697 eintrs = intrs & sc->sc_eintrs; 698 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 699 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 700 if (!eintrs) 701 return 0; 702 703 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 704 if (eintrs & EHCI_STS_IAA) { 705 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 706 kpreempt_disable(); 707 KASSERT(sc->sc_doorbell_si != NULL); 708 softint_schedule(sc->sc_doorbell_si); 709 kpreempt_enable(); 710 eintrs &= ~EHCI_STS_IAA; 711 } 712 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 713 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 714 eintrs & EHCI_STS_INT ? 1 : 0, 715 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 716 usb_schedsoftintr(&sc->sc_bus); 717 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 718 } 719 if (eintrs & EHCI_STS_HSE) { 720 printf("%s: unrecoverable error, controller halted\n", 721 device_xname(sc->sc_dev)); 722 /* XXX what else */ 723 } 724 if (eintrs & EHCI_STS_PCD) { 725 kpreempt_disable(); 726 KASSERT(sc->sc_pcd_si != NULL); 727 softint_schedule(sc->sc_pcd_si); 728 kpreempt_enable(); 729 eintrs &= ~EHCI_STS_PCD; 730 } 731 732 if (eintrs != 0) { 733 /* Block unprocessed interrupts. */ 734 sc->sc_eintrs &= ~eintrs; 735 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 736 printf("%s: blocking intrs 0x%x\n", 737 device_xname(sc->sc_dev), eintrs); 738 } 739 740 return 1; 741 } 742 743 Static void 744 ehci_doorbell(void *addr) 745 { 746 ehci_softc_t *sc = addr; 747 748 mutex_enter(&sc->sc_lock); 749 cv_broadcast(&sc->sc_doorbell); 750 mutex_exit(&sc->sc_lock); 751 } 752 753 Static void 754 ehci_pcd(void *addr) 755 { 756 ehci_softc_t *sc = addr; 757 struct usbd_xfer *xfer; 758 u_char *p; 759 int i, m; 760 761 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 762 763 mutex_enter(&sc->sc_lock); 764 xfer = sc->sc_intrxfer; 765 766 if (xfer == NULL) { 767 /* Just ignore the change. */ 768 goto done; 769 } 770 771 p = xfer->ux_buf; 772 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 773 memset(p, 0, xfer->ux_length); 774 for (i = 1; i <= m; i++) { 775 /* Pick out CHANGE bits from the status reg. */ 776 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 777 p[i/8] |= 1 << (i%8); 778 if (i % 8 == 7) 779 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 780 p[i/8], 0, 0); 781 } 782 xfer->ux_actlen = xfer->ux_length; 783 xfer->ux_status = USBD_NORMAL_COMPLETION; 784 785 usb_transfer_complete(xfer); 786 787 done: 788 mutex_exit(&sc->sc_lock); 789 } 790 791 Static void 792 ehci_softintr(void *v) 793 { 794 struct usbd_bus *bus = v; 795 ehci_softc_t *sc = EHCI_BUS2SC(bus); 796 struct ehci_xfer *ex, *nextex; 797 798 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 799 800 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 801 802 ex_completeq_t cq; 803 TAILQ_INIT(&cq); 804 805 /* 806 * The only explanation I can think of for why EHCI is as brain dead 807 * as UHCI interrupt-wise is that Intel was involved in both. 808 * An interrupt just tells us that something is done, we have no 809 * clue what, so we need to scan through all active transfers. :-( 810 */ 811 812 /* 813 * ehci_idone will remove transfer from sc->sc_intrhead if it's 814 * complete and add to our cq list 815 * */ 816 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 817 switch (ex->ex_type) { 818 case EX_CTRL: 819 case EX_BULK: 820 case EX_INTR: 821 ehci_check_qh_intr(sc, ex, &cq); 822 break; 823 case EX_ISOC: 824 ehci_check_itd_intr(sc, ex, &cq); 825 break; 826 case EX_FS_ISOC: 827 ehci_check_sitd_intr(sc, ex, &cq); 828 break; 829 default: 830 KASSERT(false); 831 } 832 833 } 834 835 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 836 /* 837 * XXX transfer_complete memcpys out transfer data (for in 838 * endpoints) during this call, before methods->done is called. 839 * A dma sync required beforehand. 840 */ 841 usb_transfer_complete(&ex->ex_xfer); 842 } 843 844 /* Schedule a callout to catch any dropped transactions. */ 845 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 846 !TAILQ_EMPTY(&sc->sc_intrhead)) 847 callout_reset(&sc->sc_tmo_intrlist, 848 hz, ehci_intrlist_timeout, sc); 849 850 if (sc->sc_softwake) { 851 sc->sc_softwake = 0; 852 cv_broadcast(&sc->sc_softwake_cv); 853 } 854 } 855 856 Static void 857 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 858 { 859 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 860 uint32_t status; 861 862 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 863 864 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 865 866 if (ex->ex_type == EX_CTRL) { 867 fsqtd = ex->ex_setup; 868 lsqtd = ex->ex_status; 869 } else { 870 fsqtd = ex->ex_sqtdstart; 871 lsqtd = ex->ex_sqtdend; 872 } 873 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 874 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 875 876 /* 877 * If the last TD is still active we need to check whether there 878 * is an error somewhere in the middle, or whether there was a 879 * short packet (SPD and not ACTIVE). 880 */ 881 usb_syncmem(&lsqtd->dma, 882 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 883 sizeof(lsqtd->qtd.qtd_status), 884 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 885 status = le32toh(lsqtd->qtd.qtd_status); 886 usb_syncmem(&lsqtd->dma, 887 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 888 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 889 if (status & EHCI_QTD_ACTIVE) { 890 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 891 892 /* last qTD has already been checked */ 893 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 894 usb_syncmem(&sqtd->dma, 895 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 896 sizeof(sqtd->qtd.qtd_status), 897 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 898 status = le32toh(sqtd->qtd.qtd_status); 899 usb_syncmem(&sqtd->dma, 900 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 901 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 902 /* If there's an active QTD the xfer isn't done. */ 903 if (status & EHCI_QTD_ACTIVE) 904 break; 905 /* Any kind of error makes the xfer done. */ 906 if (status & EHCI_QTD_HALTED) 907 goto done; 908 /* Handle short packets */ 909 if (EHCI_QTD_GET_BYTES(status) != 0) { 910 /* 911 * If we get here for a control transfer then 912 * we need to let the hardware complete the 913 * status phase. That is, we're not done 914 * quite yet. 915 * 916 * Otherwise, we're done. 917 */ 918 if (ex->ex_type == EX_CTRL) { 919 break; 920 } 921 goto done; 922 } 923 } 924 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 925 ex, ex->ex_sqtdstart, 0, 0); 926 #ifdef EHCI_DEBUG 927 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 928 0, 0); 929 ehci_dump_sqtds(ex->ex_sqtdstart); 930 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 931 0); 932 #endif 933 return; 934 } 935 done: 936 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 937 callout_stop(&ex->ex_xfer.ux_callout); 938 ehci_idone(ex, cq); 939 } 940 941 Static void 942 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 943 { 944 ehci_soft_itd_t *itd; 945 int i; 946 947 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 948 949 KASSERT(mutex_owned(&sc->sc_lock)); 950 951 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 952 return; 953 954 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 955 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 956 957 itd = ex->ex_itdend; 958 959 /* 960 * check no active transfers in last itd, meaning we're finished 961 */ 962 963 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 964 sizeof(itd->itd.itd_ctl), 965 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 966 967 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 968 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 969 break; 970 } 971 972 if (i == EHCI_ITD_NUFRAMES) { 973 goto done; /* All 8 descriptors inactive, it's done */ 974 } 975 976 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 977 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 978 979 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 980 ex->ex_itdstart, 0, 0); 981 return; 982 done: 983 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 984 callout_stop(&ex->ex_xfer.ux_callout); 985 ehci_idone(ex, cq); 986 } 987 988 void 989 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 990 { 991 ehci_soft_sitd_t *sitd; 992 993 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 994 995 KASSERT(mutex_owned(&sc->sc_lock)); 996 997 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 998 return; 999 1000 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1001 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1002 1003 sitd = ex->ex_sitdend; 1004 1005 /* 1006 * check no active transfers in last sitd, meaning we're finished 1007 */ 1008 1009 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1010 sizeof(sitd->sitd.sitd_trans), 1011 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1012 1013 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1014 1015 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1016 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1017 1018 if (active) 1019 return; 1020 1021 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1022 callout_stop(&(ex->ex_xfer.ux_callout)); 1023 ehci_idone(ex, cq); 1024 } 1025 1026 1027 Static void 1028 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1029 { 1030 struct usbd_xfer *xfer = &ex->ex_xfer; 1031 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1032 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1033 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1034 uint32_t status = 0, nstatus = 0; 1035 int actlen = 0; 1036 1037 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1038 1039 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1040 1041 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1042 1043 if (xfer->ux_status == USBD_CANCELLED || 1044 xfer->ux_status == USBD_TIMEOUT) { 1045 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1046 return; 1047 } 1048 1049 #ifdef DIAGNOSTIC 1050 #ifdef EHCI_DEBUG 1051 if (ex->ex_isdone) { 1052 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1053 ehci_dump_exfer(ex); 1054 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1055 } 1056 #endif 1057 KASSERT(!ex->ex_isdone); 1058 ex->ex_isdone = true; 1059 #endif 1060 1061 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1062 1063 /* The transfer is done, compute actual length and status. */ 1064 if (ex->ex_type == EX_ISOC) { 1065 /* HS isoc transfer */ 1066 1067 struct ehci_soft_itd *itd; 1068 int i, nframes, len, uframes; 1069 1070 nframes = 0; 1071 1072 #ifdef EHCI_DEBUG 1073 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1074 ehci_dump_itds(ex->ex_itdstart); 1075 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1076 #endif 1077 1078 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1079 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1080 1081 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1082 usb_syncmem(&itd->dma, 1083 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1084 sizeof(itd->itd.itd_ctl), 1085 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1086 1087 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1088 /* 1089 * XXX - driver didn't fill in the frame full 1090 * of uframes. This leads to scheduling 1091 * inefficiencies, but working around 1092 * this doubles complexity of tracking 1093 * an xfer. 1094 */ 1095 if (nframes >= xfer->ux_nframes) 1096 break; 1097 1098 status = le32toh(itd->itd.itd_ctl[i]); 1099 len = EHCI_ITD_GET_LEN(status); 1100 if (EHCI_ITD_GET_STATUS(status) != 0) 1101 len = 0; /*No valid data on error*/ 1102 1103 xfer->ux_frlengths[nframes++] = len; 1104 actlen += len; 1105 } 1106 usb_syncmem(&itd->dma, 1107 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1108 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1109 1110 if (nframes >= xfer->ux_nframes) 1111 break; 1112 } 1113 1114 xfer->ux_actlen = actlen; 1115 xfer->ux_status = USBD_NORMAL_COMPLETION; 1116 goto end; 1117 } else if (ex->ex_type == EX_FS_ISOC) { 1118 /* FS isoc transfer */ 1119 struct ehci_soft_sitd *sitd; 1120 int nframes, len; 1121 1122 nframes = 0; 1123 1124 for (sitd = ex->ex_sitdstart; sitd != NULL; 1125 sitd = sitd->xfer_next) { 1126 usb_syncmem(&sitd->dma, 1127 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1128 sizeof(sitd->sitd.sitd_trans), 1129 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1130 1131 /* 1132 * XXX - driver didn't fill in the frame full 1133 * of uframes. This leads to scheduling 1134 * inefficiencies, but working around 1135 * this doubles complexity of tracking 1136 * an xfer. 1137 */ 1138 if (nframes >= xfer->ux_nframes) 1139 break; 1140 1141 status = le32toh(sitd->sitd.sitd_trans); 1142 usb_syncmem(&sitd->dma, 1143 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1144 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1145 1146 len = EHCI_SITD_GET_LEN(status); 1147 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1148 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1149 /* No valid data on error */ 1150 len = xfer->ux_frlengths[nframes]; 1151 } 1152 1153 /* 1154 * frlengths[i]: # of bytes to send 1155 * len: # of bytes host didn't send 1156 */ 1157 xfer->ux_frlengths[nframes] -= len; 1158 /* frlengths[i]: # of bytes host sent */ 1159 actlen += xfer->ux_frlengths[nframes++]; 1160 1161 if (nframes >= xfer->ux_nframes) 1162 break; 1163 } 1164 1165 xfer->ux_actlen = actlen; 1166 xfer->ux_status = USBD_NORMAL_COMPLETION; 1167 goto end; 1168 } 1169 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1170 ex->ex_type == EX_BULK); 1171 1172 /* Continue processing xfers using queue heads */ 1173 if (ex->ex_type == EX_CTRL) { 1174 fsqtd = ex->ex_setup; 1175 lsqtd = ex->ex_status; 1176 } else { 1177 fsqtd = ex->ex_sqtdstart; 1178 lsqtd = ex->ex_sqtdend; 1179 } 1180 #ifdef EHCI_DEBUG 1181 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1182 ehci_dump_sqtds(fsqtd); 1183 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1184 #endif 1185 1186 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1187 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1188 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1189 nstatus = le32toh(sqtd->qtd.qtd_status); 1190 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1191 BUS_DMASYNC_PREREAD); 1192 if (nstatus & EHCI_QTD_ACTIVE) 1193 break; 1194 1195 status = nstatus; 1196 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1197 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1198 } 1199 1200 /* 1201 * If there are left over TDs we need to update the toggle. 1202 * The default pipe doesn't need it since control transfers 1203 * start the toggle at 0 every time. 1204 * For a short transfer we need to update the toggle for the missing 1205 * packets within the qTD. 1206 */ 1207 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1208 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1209 USBHIST_LOG(ehcidebug, 1210 "toggle update status=0x%08x nstatus=0x%08x", 1211 status, nstatus, 0, 0); 1212 #if 0 1213 ehci_dump_sqh(epipe->sqh); 1214 ehci_dump_sqtds(ex->ex_sqtdstart); 1215 #endif 1216 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1217 } 1218 1219 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1220 actlen, status, 0); 1221 xfer->ux_actlen = actlen; 1222 if (status & EHCI_QTD_HALTED) { 1223 #ifdef EHCI_DEBUG 1224 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1225 xfer->ux_pipe->up_dev->ud_addr, 1226 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1227 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1228 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1229 0, 0); 1230 USBHIST_LOG(ehcidebug, 1231 "active =%d halted=%d buferr=%d babble=%d", 1232 status & EHCI_QTD_ACTIVE ? 1 : 0, 1233 status & EHCI_QTD_HALTED ? 1 : 0, 1234 status & EHCI_QTD_BUFERR ? 1 : 0, 1235 status & EHCI_QTD_BABBLE ? 1 : 0); 1236 1237 USBHIST_LOG(ehcidebug, 1238 "xacterr=%d missed=%d split =%d ping =%d", 1239 status & EHCI_QTD_XACTERR ? 1 : 0, 1240 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1241 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1242 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1243 1244 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1245 ehci_dump_sqh(epipe->sqh); 1246 ehci_dump_sqtds(ex->ex_sqtdstart); 1247 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1248 #endif 1249 /* low&full speed has an extra error flag */ 1250 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1251 EHCI_QH_SPEED_HIGH) 1252 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1253 else 1254 status &= EHCI_QTD_STATERRS; 1255 if (status == 0) /* no other errors means a stall */ { 1256 xfer->ux_status = USBD_STALLED; 1257 } else { 1258 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1259 } 1260 /* XXX need to reset TT on missed microframe */ 1261 if (status & EHCI_QTD_MISSEDMICRO) { 1262 printf("%s: missed microframe, TT reset not " 1263 "implemented, hub might be inoperational\n", 1264 device_xname(sc->sc_dev)); 1265 } 1266 } else { 1267 xfer->ux_status = USBD_NORMAL_COMPLETION; 1268 } 1269 1270 end: 1271 /* 1272 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1273 * during this call, before methods->done is called: dma sync required 1274 * beforehand? 1275 */ 1276 usb_transfer_complete(xfer); 1277 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1278 } 1279 1280 /* 1281 * Wait here until controller claims to have an interrupt. 1282 * Then call ehci_intr and return. Use timeout to avoid waiting 1283 * too long. 1284 */ 1285 Static void 1286 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1287 { 1288 int timo; 1289 uint32_t intrs; 1290 1291 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1292 1293 xfer->ux_status = USBD_IN_PROGRESS; 1294 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1295 usb_delay_ms(&sc->sc_bus, 1); 1296 if (sc->sc_dying) 1297 break; 1298 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1299 sc->sc_eintrs; 1300 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1301 #ifdef EHCI_DEBUG 1302 if (ehcidebug >= 15) 1303 ehci_dump_regs(sc); 1304 #endif 1305 if (intrs) { 1306 mutex_spin_enter(&sc->sc_intr_lock); 1307 ehci_intr1(sc); 1308 mutex_spin_exit(&sc->sc_intr_lock); 1309 if (xfer->ux_status != USBD_IN_PROGRESS) 1310 return; 1311 } 1312 } 1313 1314 /* Timeout */ 1315 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1316 xfer->ux_status = USBD_TIMEOUT; 1317 mutex_enter(&sc->sc_lock); 1318 usb_transfer_complete(xfer); 1319 mutex_exit(&sc->sc_lock); 1320 } 1321 1322 Static void 1323 ehci_poll(struct usbd_bus *bus) 1324 { 1325 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1326 1327 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1328 1329 #ifdef EHCI_DEBUG 1330 static int last; 1331 int new; 1332 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1333 if (new != last) { 1334 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1335 last = new; 1336 } 1337 #endif 1338 1339 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1340 mutex_spin_enter(&sc->sc_intr_lock); 1341 ehci_intr1(sc); 1342 mutex_spin_exit(&sc->sc_intr_lock); 1343 } 1344 } 1345 1346 void 1347 ehci_childdet(device_t self, device_t child) 1348 { 1349 struct ehci_softc *sc = device_private(self); 1350 1351 KASSERT(sc->sc_child == child); 1352 sc->sc_child = NULL; 1353 } 1354 1355 int 1356 ehci_detach(struct ehci_softc *sc, int flags) 1357 { 1358 int rv = 0; 1359 1360 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1361 1362 if (sc->sc_child != NULL) 1363 rv = config_detach(sc->sc_child, flags); 1364 1365 if (rv != 0) 1366 return rv; 1367 1368 callout_halt(&sc->sc_tmo_intrlist, NULL); 1369 callout_destroy(&sc->sc_tmo_intrlist); 1370 1371 /* XXX free other data structures XXX */ 1372 if (sc->sc_softitds) 1373 kmem_free(sc->sc_softitds, 1374 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1375 cv_destroy(&sc->sc_doorbell); 1376 cv_destroy(&sc->sc_softwake_cv); 1377 1378 #if 0 1379 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1380 1381 softint_disestablish(sc->sc_doorbell_si); 1382 softint_disestablish(sc->sc_pcd_si); 1383 1384 mutex_destroy(&sc->sc_lock); 1385 mutex_destroy(&sc->sc_intr_lock); 1386 #endif 1387 1388 pool_cache_destroy(sc->sc_xferpool); 1389 1390 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1391 1392 return rv; 1393 } 1394 1395 1396 int 1397 ehci_activate(device_t self, enum devact act) 1398 { 1399 struct ehci_softc *sc = device_private(self); 1400 1401 switch (act) { 1402 case DVACT_DEACTIVATE: 1403 sc->sc_dying = 1; 1404 return 0; 1405 default: 1406 return EOPNOTSUPP; 1407 } 1408 } 1409 1410 /* 1411 * Handle suspend/resume. 1412 * 1413 * We need to switch to polling mode here, because this routine is 1414 * called from an interrupt context. This is all right since we 1415 * are almost suspended anyway. 1416 * 1417 * Note that this power handler isn't to be registered directly; the 1418 * bus glue needs to call out to it. 1419 */ 1420 bool 1421 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1422 { 1423 ehci_softc_t *sc = device_private(dv); 1424 int i; 1425 uint32_t cmd, hcr; 1426 1427 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1428 1429 mutex_spin_enter(&sc->sc_intr_lock); 1430 sc->sc_bus.ub_usepolling++; 1431 mutex_spin_exit(&sc->sc_intr_lock); 1432 1433 for (i = 1; i <= sc->sc_noport; i++) { 1434 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1435 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1436 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1437 } 1438 1439 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1440 1441 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1442 EOWRITE4(sc, EHCI_USBCMD, cmd); 1443 1444 for (i = 0; i < 100; i++) { 1445 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1446 if (hcr == 0) 1447 break; 1448 1449 usb_delay_ms(&sc->sc_bus, 1); 1450 } 1451 if (hcr != 0) 1452 printf("%s: reset timeout\n", device_xname(dv)); 1453 1454 cmd &= ~EHCI_CMD_RS; 1455 EOWRITE4(sc, EHCI_USBCMD, cmd); 1456 1457 for (i = 0; i < 100; i++) { 1458 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1459 if (hcr == EHCI_STS_HCH) 1460 break; 1461 1462 usb_delay_ms(&sc->sc_bus, 1); 1463 } 1464 if (hcr != EHCI_STS_HCH) 1465 printf("%s: config timeout\n", device_xname(dv)); 1466 1467 mutex_spin_enter(&sc->sc_intr_lock); 1468 sc->sc_bus.ub_usepolling--; 1469 mutex_spin_exit(&sc->sc_intr_lock); 1470 1471 return true; 1472 } 1473 1474 bool 1475 ehci_resume(device_t dv, const pmf_qual_t *qual) 1476 { 1477 ehci_softc_t *sc = device_private(dv); 1478 int i; 1479 uint32_t cmd, hcr; 1480 1481 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1482 1483 /* restore things in case the bios sucks */ 1484 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1485 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1486 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1487 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1488 1489 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1490 1491 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1492 1493 hcr = 0; 1494 for (i = 1; i <= sc->sc_noport; i++) { 1495 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1496 if ((cmd & EHCI_PS_PO) == 0 && 1497 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1498 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1499 hcr = 1; 1500 } 1501 } 1502 1503 if (hcr) { 1504 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1505 1506 for (i = 1; i <= sc->sc_noport; i++) { 1507 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1508 if ((cmd & EHCI_PS_PO) == 0 && 1509 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1510 EOWRITE4(sc, EHCI_PORTSC(i), 1511 cmd & ~EHCI_PS_FPR); 1512 } 1513 } 1514 1515 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1516 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1517 1518 for (i = 0; i < 100; i++) { 1519 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1520 if (hcr != EHCI_STS_HCH) 1521 break; 1522 1523 usb_delay_ms(&sc->sc_bus, 1); 1524 } 1525 if (hcr == EHCI_STS_HCH) 1526 printf("%s: config timeout\n", device_xname(dv)); 1527 1528 return true; 1529 } 1530 1531 /* 1532 * Shut down the controller when the system is going down. 1533 */ 1534 bool 1535 ehci_shutdown(device_t self, int flags) 1536 { 1537 ehci_softc_t *sc = device_private(self); 1538 1539 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1540 1541 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1542 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1543 return true; 1544 } 1545 1546 Static struct usbd_xfer * 1547 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1548 { 1549 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1550 struct usbd_xfer *xfer; 1551 1552 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1553 if (xfer != NULL) { 1554 memset(xfer, 0, sizeof(struct ehci_xfer)); 1555 #ifdef DIAGNOSTIC 1556 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1557 ex->ex_isdone = true; 1558 xfer->ux_state = XFER_BUSY; 1559 #endif 1560 } 1561 return xfer; 1562 } 1563 1564 Static void 1565 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1566 { 1567 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1568 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1569 1570 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1571 xfer->ux_state); 1572 KASSERT(ex->ex_isdone); 1573 1574 #ifdef DIAGNOSTIC 1575 xfer->ux_state = XFER_FREE; 1576 #endif 1577 1578 pool_cache_put(sc->sc_xferpool, xfer); 1579 } 1580 1581 Static void 1582 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1583 { 1584 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1585 1586 *lock = &sc->sc_lock; 1587 } 1588 1589 Static void 1590 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1591 { 1592 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1593 1594 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1595 1596 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1597 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1598 #ifdef EHCI_DEBUG 1599 if (ehcidebug) 1600 usbd_dump_pipe(pipe); 1601 #endif 1602 epipe->nexttoggle = 0; 1603 } 1604 1605 Static void 1606 ehci_noop(struct usbd_pipe *pipe) 1607 { 1608 } 1609 1610 #ifdef EHCI_DEBUG 1611 /* 1612 * Unused function - this is meant to be called from a kernel 1613 * debugger. 1614 */ 1615 void 1616 ehci_dump(void) 1617 { 1618 ehci_softc_t *sc = theehci; 1619 int i; 1620 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1621 EOREAD4(sc, EHCI_USBCMD), 1622 EOREAD4(sc, EHCI_USBSTS), 1623 EOREAD4(sc, EHCI_USBINTR)); 1624 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1625 EOREAD4(sc, EHCI_FRINDEX), 1626 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1627 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1628 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1629 for (i = 1; i <= sc->sc_noport; i++) 1630 printf("port %d status=0x%08x\n", i, 1631 EOREAD4(sc, EHCI_PORTSC(i))); 1632 } 1633 1634 Static void 1635 ehci_dump_regs(ehci_softc_t *sc) 1636 { 1637 int i; 1638 1639 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1640 1641 USBHIST_LOG(ehcidebug, 1642 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1643 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1644 EOREAD4(sc, EHCI_USBINTR), 0); 1645 USBHIST_LOG(ehcidebug, 1646 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1647 "async = 0x%08x", 1648 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1649 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1650 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1651 for (i = 1; i <= sc->sc_noport; i += 2) { 1652 if (i == sc->sc_noport) { 1653 USBHIST_LOG(ehcidebug, 1654 "port %d status = 0x%08x", i, 1655 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1656 } else { 1657 USBHIST_LOG(ehcidebug, 1658 "port %d status = 0x%08x port %d status = 0x%08x", 1659 i, EOREAD4(sc, EHCI_PORTSC(i)), 1660 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1661 } 1662 } 1663 } 1664 1665 #define ehci_dump_link(link, type) do { \ 1666 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1667 link, \ 1668 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1669 if (type) { \ 1670 USBHIST_LOG(ehcidebug, \ 1671 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1672 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1673 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1674 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1675 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1676 } \ 1677 } while(0) 1678 1679 Static void 1680 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1681 { 1682 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1683 int i; 1684 uint32_t stop = 0; 1685 1686 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1687 ehci_dump_sqtd(sqtd); 1688 usb_syncmem(&sqtd->dma, 1689 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1690 sizeof(sqtd->qtd), 1691 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1692 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1693 usb_syncmem(&sqtd->dma, 1694 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1695 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1696 } 1697 if (!stop) 1698 USBHIST_LOG(ehcidebug, 1699 "dump aborted, too many TDs", 0, 0, 0, 0); 1700 } 1701 1702 Static void 1703 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1704 { 1705 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1706 1707 usb_syncmem(&sqtd->dma, sqtd->offs, 1708 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1709 1710 USBHIST_LOGN(ehcidebug, 10, 1711 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1712 ehci_dump_qtd(&sqtd->qtd); 1713 1714 usb_syncmem(&sqtd->dma, sqtd->offs, 1715 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1716 } 1717 1718 Static void 1719 ehci_dump_qtd(ehci_qtd_t *qtd) 1720 { 1721 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1722 uint32_t s = le32toh(qtd->qtd_status); 1723 1724 USBHIST_LOGN(ehcidebug, 10, 1725 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1726 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1727 USBHIST_LOGN(ehcidebug, 10, 1728 " toggle = %d ioc = %d bytes = %#x " 1729 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1730 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1731 USBHIST_LOGN(ehcidebug, 10, 1732 " cerr = %d pid = %d stat = %x", 1733 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1734 0); 1735 USBHIST_LOGN(ehcidebug, 10, 1736 "active =%d halted=%d buferr=%d babble=%d", 1737 s & EHCI_QTD_ACTIVE ? 1 : 0, 1738 s & EHCI_QTD_HALTED ? 1 : 0, 1739 s & EHCI_QTD_BUFERR ? 1 : 0, 1740 s & EHCI_QTD_BABBLE ? 1 : 0); 1741 USBHIST_LOGN(ehcidebug, 10, 1742 "xacterr=%d missed=%d split =%d ping =%d", 1743 s & EHCI_QTD_XACTERR ? 1 : 0, 1744 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1745 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1746 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1747 USBHIST_LOGN(ehcidebug, 10, 1748 "buffer[0] = %#x buffer[1] = %#x " 1749 "buffer[2] = %#x buffer[3] = %#x", 1750 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1751 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1752 USBHIST_LOGN(ehcidebug, 10, 1753 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1754 } 1755 1756 Static void 1757 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1758 { 1759 ehci_qh_t *qh = &sqh->qh; 1760 ehci_link_t link; 1761 uint32_t endp, endphub; 1762 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1763 1764 usb_syncmem(&sqh->dma, sqh->offs, 1765 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1766 1767 USBHIST_LOGN(ehcidebug, 10, 1768 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1769 link = le32toh(qh->qh_link); 1770 ehci_dump_link(link, true); 1771 1772 endp = le32toh(qh->qh_endp); 1773 USBHIST_LOGN(ehcidebug, 10, 1774 " endp = %#x", endp, 0, 0, 0); 1775 USBHIST_LOGN(ehcidebug, 10, 1776 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1777 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1778 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1779 USBHIST_LOGN(ehcidebug, 10, 1780 " dtc = %d hrecl = %d", 1781 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1782 USBHIST_LOGN(ehcidebug, 10, 1783 " ctl = %d nrl = %d mpl = %#x(%d)", 1784 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1785 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1786 1787 endphub = le32toh(qh->qh_endphub); 1788 USBHIST_LOGN(ehcidebug, 10, 1789 " endphub = %#x", endphub, 0, 0, 0); 1790 USBHIST_LOGN(ehcidebug, 10, 1791 " smask = 0x%02x cmask = 0x%02x", 1792 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1793 USBHIST_LOGN(ehcidebug, 10, 1794 " huba = 0x%02x port = %d mult = %d", 1795 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1796 EHCI_QH_GET_MULT(endphub), 0); 1797 1798 link = le32toh(qh->qh_curqtd); 1799 ehci_dump_link(link, false); 1800 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1801 ehci_dump_qtd(&qh->qh_qtd); 1802 1803 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1804 BUS_DMASYNC_PREREAD); 1805 } 1806 1807 Static void 1808 ehci_dump_itds(ehci_soft_itd_t *itd) 1809 { 1810 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1811 int i; 1812 uint32_t stop = 0; 1813 1814 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1815 ehci_dump_itd(itd); 1816 usb_syncmem(&itd->dma, 1817 itd->offs + offsetof(ehci_itd_t, itd_next), 1818 sizeof(itd->itd), 1819 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1820 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1821 usb_syncmem(&itd->dma, 1822 itd->offs + offsetof(ehci_itd_t, itd_next), 1823 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1824 } 1825 if (!stop) 1826 USBHIST_LOG(ehcidebug, "dump aborted, too many TDs", 0, 0, 0, 0); 1827 } 1828 1829 Static void 1830 ehci_dump_itd(struct ehci_soft_itd *itd) 1831 { 1832 ehci_isoc_trans_t t; 1833 ehci_isoc_bufr_ptr_t b, b2, b3; 1834 int i; 1835 1836 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1837 1838 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1839 0, 0); 1840 1841 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1842 t = le32toh(itd->itd.itd_ctl[i]); 1843 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1844 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1845 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1846 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1847 EHCI_ITD_GET_OFFS(t), 0); 1848 } 1849 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1850 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1851 USBHIST_LOG(ehcidebug, " %x", 1852 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1853 1854 b = le32toh(itd->itd.itd_bufr[0]); 1855 b2 = le32toh(itd->itd.itd_bufr[1]); 1856 b3 = le32toh(itd->itd.itd_bufr[2]); 1857 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1858 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1859 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1860 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1861 } 1862 1863 Static void 1864 ehci_dump_sitd(struct ehci_soft_itd *itd) 1865 { 1866 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1867 1868 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1869 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1870 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1871 itd->xfer_next, itd->physaddr, itd->slot, 0); 1872 } 1873 1874 Static void 1875 ehci_dump_exfer(struct ehci_xfer *ex) 1876 { 1877 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1878 1879 USBHIST_LOG(ehcidebug, "ex = %p type %d isdone", ex, ex->ex_type, 1880 ex->ex_isdone, 0); 1881 1882 switch (ex->ex_type) { 1883 case EX_CTRL: 1884 USBHIST_LOG(ehcidebug, " setup = %p data = %p status = %p", 1885 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1886 break; 1887 case EX_BULK: 1888 case EX_INTR: 1889 USBHIST_LOG(ehcidebug, " qtdstart = %p qtdend = %p", 1890 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1891 break; 1892 case EX_ISOC: 1893 USBHIST_LOG(ehcidebug, " itdstart = %p itdend = %p", 1894 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1895 break; 1896 case EX_FS_ISOC: 1897 USBHIST_LOG(ehcidebug, " sitdstart = %p sitdend = %p", 1898 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1899 break; 1900 default: 1901 USBHIST_LOG(ehcidebug, " unknown type", 0, 0, 0, 0); 1902 } 1903 } 1904 #endif 1905 1906 Static usbd_status 1907 ehci_open(struct usbd_pipe *pipe) 1908 { 1909 struct usbd_device *dev = pipe->up_dev; 1910 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1911 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1912 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1913 uint8_t addr = dev->ud_addr; 1914 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1915 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1916 ehci_soft_qh_t *sqh; 1917 usbd_status err; 1918 int ival, speed, naks; 1919 int hshubaddr, hshubport; 1920 1921 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1922 1923 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1924 pipe, addr, ed->bEndpointAddress, rhaddr); 1925 1926 if (dev->ud_myhsport) { 1927 /* 1928 * When directly attached FS/LS device while doing embedded 1929 * transaction translations and we are the hub, set the hub 1930 * address to 0 (us). 1931 */ 1932 if (!(sc->sc_flags & EHCIF_ETTF) 1933 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1934 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1935 } else { 1936 hshubaddr = 0; 1937 } 1938 hshubport = dev->ud_myhsport->up_portno; 1939 } else { 1940 hshubaddr = 0; 1941 hshubport = 0; 1942 } 1943 1944 if (sc->sc_dying) 1945 return USBD_IOERROR; 1946 1947 /* toggle state needed for bulk endpoints */ 1948 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1949 1950 if (addr == rhaddr) { 1951 switch (ed->bEndpointAddress) { 1952 case USB_CONTROL_ENDPOINT: 1953 pipe->up_methods = &roothub_ctrl_methods; 1954 break; 1955 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1956 pipe->up_methods = &ehci_root_intr_methods; 1957 break; 1958 default: 1959 USBHIST_LOG(ehcidebug, 1960 "bad bEndpointAddress 0x%02x", 1961 ed->bEndpointAddress, 0, 0, 0); 1962 return USBD_INVAL; 1963 } 1964 return USBD_NORMAL_COMPLETION; 1965 } 1966 1967 /* XXX All this stuff is only valid for async. */ 1968 switch (dev->ud_speed) { 1969 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1970 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1971 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1972 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1973 } 1974 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1975 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1976 hshubaddr, hshubport, 0, 0); 1977 return USBD_INVAL; 1978 } 1979 1980 /* 1981 * For interrupt transfer, nak throttling must be disabled, but for 1982 * the other transfer type, nak throttling should be enabled from the 1983 * viewpoint that avoids the memory thrashing. 1984 */ 1985 naks = (xfertype == UE_INTERRUPT) ? 0 1986 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1987 1988 /* Allocate sqh for everything, save isoc xfers */ 1989 if (xfertype != UE_ISOCHRONOUS) { 1990 sqh = ehci_alloc_sqh(sc); 1991 if (sqh == NULL) 1992 return USBD_NOMEM; 1993 /* qh_link filled when the QH is added */ 1994 sqh->qh.qh_endp = htole32( 1995 EHCI_QH_SET_ADDR(addr) | 1996 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1997 EHCI_QH_SET_EPS(speed) | 1998 EHCI_QH_DTC | 1999 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 2000 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 2001 EHCI_QH_CTL : 0) | 2002 EHCI_QH_SET_NRL(naks) 2003 ); 2004 sqh->qh.qh_endphub = htole32( 2005 EHCI_QH_SET_MULT(1) | 2006 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 2007 ); 2008 if (speed != EHCI_QH_SPEED_HIGH) 2009 sqh->qh.qh_endphub |= htole32( 2010 EHCI_QH_SET_PORT(hshubport) | 2011 EHCI_QH_SET_HUBA(hshubaddr) | 2012 EHCI_QH_SET_CMASK(0x08) /* XXX */ 2013 ); 2014 sqh->qh.qh_curqtd = EHCI_NULL; 2015 /* Fill the overlay qTD */ 2016 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2017 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2018 sqh->qh.qh_qtd.qtd_status = htole32(0); 2019 2020 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2021 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2022 epipe->sqh = sqh; 2023 } else { 2024 sqh = NULL; 2025 } /*xfertype == UE_ISOC*/ 2026 2027 switch (xfertype) { 2028 case UE_CONTROL: 2029 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2030 0, &epipe->ctrl.reqdma); 2031 #ifdef EHCI_DEBUG 2032 if (err) 2033 printf("ehci_open: usb_allocmem()=%d\n", err); 2034 #endif 2035 if (err) 2036 goto bad; 2037 pipe->up_methods = &ehci_device_ctrl_methods; 2038 mutex_enter(&sc->sc_lock); 2039 ehci_add_qh(sc, sqh, sc->sc_async_head); 2040 mutex_exit(&sc->sc_lock); 2041 break; 2042 case UE_BULK: 2043 pipe->up_methods = &ehci_device_bulk_methods; 2044 mutex_enter(&sc->sc_lock); 2045 ehci_add_qh(sc, sqh, sc->sc_async_head); 2046 mutex_exit(&sc->sc_lock); 2047 break; 2048 case UE_INTERRUPT: 2049 pipe->up_methods = &ehci_device_intr_methods; 2050 ival = pipe->up_interval; 2051 if (ival == USBD_DEFAULT_INTERVAL) { 2052 if (speed == EHCI_QH_SPEED_HIGH) { 2053 if (ed->bInterval > 16) { 2054 /* 2055 * illegal with high-speed, but there 2056 * were documentation bugs in the spec, 2057 * so be generous 2058 */ 2059 ival = 256; 2060 } else 2061 ival = (1 << (ed->bInterval - 1)) / 8; 2062 } else 2063 ival = ed->bInterval; 2064 } 2065 err = ehci_device_setintr(sc, sqh, ival); 2066 if (err) 2067 goto bad; 2068 break; 2069 case UE_ISOCHRONOUS: 2070 if (speed == EHCI_QH_SPEED_HIGH) 2071 pipe->up_methods = &ehci_device_isoc_methods; 2072 else 2073 pipe->up_methods = &ehci_device_fs_isoc_methods; 2074 if (ed->bInterval == 0 || ed->bInterval > 16) { 2075 printf("ehci: opening pipe with invalid bInterval\n"); 2076 err = USBD_INVAL; 2077 goto bad; 2078 } 2079 if (UGETW(ed->wMaxPacketSize) == 0) { 2080 printf("ehci: zero length endpoint open request\n"); 2081 err = USBD_INVAL; 2082 goto bad; 2083 } 2084 epipe->isoc.next_frame = 0; 2085 epipe->isoc.cur_xfers = 0; 2086 break; 2087 default: 2088 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2089 err = USBD_INVAL; 2090 goto bad; 2091 } 2092 return USBD_NORMAL_COMPLETION; 2093 2094 bad: 2095 if (sqh != NULL) { 2096 mutex_enter(&sc->sc_lock); 2097 ehci_free_sqh(sc, sqh); 2098 mutex_exit(&sc->sc_lock); 2099 } 2100 return err; 2101 } 2102 2103 /* 2104 * Add an ED to the schedule. Called with USB lock held. 2105 */ 2106 Static void 2107 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2108 { 2109 2110 KASSERT(mutex_owned(&sc->sc_lock)); 2111 2112 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2113 2114 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2115 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2116 2117 sqh->next = head->next; 2118 sqh->qh.qh_link = head->qh.qh_link; 2119 2120 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2121 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2122 2123 head->next = sqh; 2124 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2125 2126 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2127 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2128 2129 #ifdef EHCI_DEBUG 2130 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2131 ehci_dump_sqh(sqh); 2132 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2133 #endif 2134 } 2135 2136 /* 2137 * Remove an ED from the schedule. Called with USB lock held. 2138 */ 2139 Static void 2140 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2141 { 2142 ehci_soft_qh_t *p; 2143 2144 KASSERT(mutex_owned(&sc->sc_lock)); 2145 2146 /* XXX */ 2147 for (p = head; p != NULL && p->next != sqh; p = p->next) 2148 ; 2149 if (p == NULL) 2150 panic("ehci_rem_qh: ED not found"); 2151 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2152 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2153 p->next = sqh->next; 2154 p->qh.qh_link = sqh->qh.qh_link; 2155 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2156 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2157 2158 ehci_sync_hc(sc); 2159 } 2160 2161 Static void 2162 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2163 { 2164 int i; 2165 uint32_t status; 2166 2167 /* Save toggle bit and ping status. */ 2168 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2169 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2170 status = sqh->qh.qh_qtd.qtd_status & 2171 htole32(EHCI_QTD_TOGGLE_MASK | 2172 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2173 /* Set HALTED to make hw leave it alone. */ 2174 sqh->qh.qh_qtd.qtd_status = 2175 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2176 usb_syncmem(&sqh->dma, 2177 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2178 sizeof(sqh->qh.qh_qtd.qtd_status), 2179 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2180 sqh->qh.qh_curqtd = 0; 2181 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2182 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2183 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2184 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2185 sqh->sqtd = sqtd; 2186 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2187 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2188 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2189 sqh->qh.qh_qtd.qtd_status = status; 2190 usb_syncmem(&sqh->dma, 2191 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2192 sizeof(sqh->qh.qh_qtd.qtd_status), 2193 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2194 } 2195 2196 /* 2197 * Ensure that the HC has released all references to the QH. We do this 2198 * by asking for a Async Advance Doorbell interrupt and then we wait for 2199 * the interrupt. 2200 * To make this easier we first obtain exclusive use of the doorbell. 2201 */ 2202 Static void 2203 ehci_sync_hc(ehci_softc_t *sc) 2204 { 2205 int error __diagused; 2206 2207 KASSERT(mutex_owned(&sc->sc_lock)); 2208 2209 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2210 2211 if (sc->sc_dying) { 2212 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2213 return; 2214 } 2215 /* ask for doorbell */ 2216 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2217 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2218 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2219 2220 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2221 2222 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x ... done", 2223 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2224 #ifdef DIAGNOSTIC 2225 if (error) 2226 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2227 #endif 2228 } 2229 2230 Static void 2231 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2232 { 2233 2234 KASSERT(mutex_owned(&sc->sc_lock)); 2235 2236 for (; itd != NULL; itd = itd->xfer_next) { 2237 struct ehci_soft_itd *prev = itd->frame_list.prev; 2238 2239 /* Unlink itd from hardware chain, or frame array */ 2240 if (prev == NULL) { /* We're at the table head */ 2241 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2242 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2243 usb_syncmem(&sc->sc_fldma, 2244 sizeof(ehci_link_t) * itd->slot, 2245 sizeof(ehci_link_t), 2246 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2247 2248 if (itd->frame_list.next != NULL) 2249 itd->frame_list.next->frame_list.prev = NULL; 2250 } else { 2251 /* XXX this part is untested... */ 2252 prev->itd.itd_next = itd->itd.itd_next; 2253 usb_syncmem(&itd->dma, 2254 itd->offs + offsetof(ehci_itd_t, itd_next), 2255 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2256 2257 prev->frame_list.next = itd->frame_list.next; 2258 if (itd->frame_list.next != NULL) 2259 itd->frame_list.next->frame_list.prev = prev; 2260 } 2261 } 2262 } 2263 2264 Static void 2265 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2266 { 2267 struct ehci_soft_itd *next; 2268 2269 mutex_enter(&sc->sc_lock); 2270 next = NULL; 2271 for (; itd != NULL; itd = next) { 2272 next = itd->xfer_next; 2273 ehci_free_itd_locked(sc, itd); 2274 } 2275 mutex_exit(&sc->sc_lock); 2276 } 2277 2278 Static void 2279 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2280 { 2281 2282 KASSERT(mutex_owned(&sc->sc_lock)); 2283 2284 for (; sitd != NULL; sitd = sitd->xfer_next) { 2285 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2286 2287 /* Unlink sitd from hardware chain, or frame array */ 2288 if (prev == NULL) { /* We're at the table head */ 2289 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2290 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2291 usb_syncmem(&sc->sc_fldma, 2292 sizeof(ehci_link_t) * sitd->slot, 2293 sizeof(ehci_link_t), 2294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2295 2296 if (sitd->frame_list.next != NULL) 2297 sitd->frame_list.next->frame_list.prev = NULL; 2298 } else { 2299 /* XXX this part is untested... */ 2300 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2301 usb_syncmem(&sitd->dma, 2302 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2303 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2304 2305 prev->frame_list.next = sitd->frame_list.next; 2306 if (sitd->frame_list.next != NULL) 2307 sitd->frame_list.next->frame_list.prev = prev; 2308 } 2309 } 2310 } 2311 2312 Static void 2313 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2314 { 2315 2316 mutex_enter(&sc->sc_lock); 2317 struct ehci_soft_sitd *next = NULL; 2318 for (; sitd != NULL; sitd = next) { 2319 next = sitd->xfer_next; 2320 ehci_free_sitd_locked(sc, sitd); 2321 } 2322 mutex_exit(&sc->sc_lock); 2323 } 2324 2325 /***********/ 2326 2327 Static int 2328 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2329 void *buf, int buflen) 2330 { 2331 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2332 usb_hub_descriptor_t hubd; 2333 usb_port_status_t ps; 2334 uint16_t len, value, index; 2335 int l, totlen = 0; 2336 int port, i; 2337 uint32_t v; 2338 2339 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2340 2341 if (sc->sc_dying) 2342 return -1; 2343 2344 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2345 req->bmRequestType, req->bRequest, 0, 0); 2346 2347 len = UGETW(req->wLength); 2348 value = UGETW(req->wValue); 2349 index = UGETW(req->wIndex); 2350 2351 #define C(x,y) ((x) | ((y) << 8)) 2352 switch (C(req->bRequest, req->bmRequestType)) { 2353 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2354 if (len == 0) 2355 break; 2356 switch (value) { 2357 case C(0, UDESC_DEVICE): { 2358 usb_device_descriptor_t devd; 2359 totlen = min(buflen, sizeof(devd)); 2360 memcpy(&devd, buf, totlen); 2361 USETW(devd.idVendor, sc->sc_id_vendor); 2362 memcpy(buf, &devd, totlen); 2363 break; 2364 2365 } 2366 #define sd ((usb_string_descriptor_t *)buf) 2367 case C(1, UDESC_STRING): 2368 /* Vendor */ 2369 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2370 break; 2371 case C(2, UDESC_STRING): 2372 /* Product */ 2373 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2374 break; 2375 #undef sd 2376 default: 2377 /* default from usbroothub */ 2378 return buflen; 2379 } 2380 break; 2381 2382 /* Hub requests */ 2383 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2384 break; 2385 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2386 USBHIST_LOG(ehcidebug, 2387 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2388 0, 0); 2389 if (index < 1 || index > sc->sc_noport) { 2390 return -1; 2391 } 2392 port = EHCI_PORTSC(index); 2393 v = EOREAD4(sc, port); 2394 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2395 v &= ~EHCI_PS_CLEAR; 2396 switch (value) { 2397 case UHF_PORT_ENABLE: 2398 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2399 break; 2400 case UHF_PORT_SUSPEND: 2401 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2402 break; 2403 v &= ~EHCI_PS_SUSP; 2404 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2405 /* see USB2 spec ch. 7.1.7.7 */ 2406 usb_delay_ms(&sc->sc_bus, 20); 2407 EOWRITE4(sc, port, v); 2408 usb_delay_ms(&sc->sc_bus, 2); 2409 #ifdef DEBUG 2410 v = EOREAD4(sc, port); 2411 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2412 printf("ehci: resume failed: %x\n", v); 2413 #endif 2414 break; 2415 case UHF_PORT_POWER: 2416 if (sc->sc_hasppc) 2417 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2418 break; 2419 case UHF_PORT_TEST: 2420 USBHIST_LOG(ehcidebug, "clear port test " 2421 "%d", index, 0, 0, 0); 2422 break; 2423 case UHF_PORT_INDICATOR: 2424 USBHIST_LOG(ehcidebug, "clear port ind " 2425 "%d", index, 0, 0, 0); 2426 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2427 break; 2428 case UHF_C_PORT_CONNECTION: 2429 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2430 break; 2431 case UHF_C_PORT_ENABLE: 2432 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2433 break; 2434 case UHF_C_PORT_SUSPEND: 2435 /* how? */ 2436 break; 2437 case UHF_C_PORT_OVER_CURRENT: 2438 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2439 break; 2440 case UHF_C_PORT_RESET: 2441 sc->sc_isreset[index] = 0; 2442 break; 2443 default: 2444 return -1; 2445 } 2446 #if 0 2447 switch(value) { 2448 case UHF_C_PORT_CONNECTION: 2449 case UHF_C_PORT_ENABLE: 2450 case UHF_C_PORT_SUSPEND: 2451 case UHF_C_PORT_OVER_CURRENT: 2452 case UHF_C_PORT_RESET: 2453 default: 2454 break; 2455 } 2456 #endif 2457 break; 2458 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2459 if (len == 0) 2460 break; 2461 if ((value & 0xff) != 0) { 2462 return -1; 2463 } 2464 totlen = min(buflen, sizeof(hubd)); 2465 memcpy(&hubd, buf, totlen); 2466 hubd.bNbrPorts = sc->sc_noport; 2467 v = EOREAD4(sc, EHCI_HCSPARAMS); 2468 USETW(hubd.wHubCharacteristics, 2469 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2470 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2471 ? UHD_PORT_IND : 0); 2472 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2473 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2474 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2475 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2476 totlen = min(totlen, hubd.bDescLength); 2477 memcpy(buf, &hubd, totlen); 2478 break; 2479 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2480 if (len != 4) { 2481 return -1; 2482 } 2483 memset(buf, 0, len); /* ? XXX */ 2484 totlen = len; 2485 break; 2486 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2487 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2488 if (index < 1 || index > sc->sc_noport) { 2489 return -1; 2490 } 2491 if (len != 4) { 2492 return -1; 2493 } 2494 v = EOREAD4(sc, EHCI_PORTSC(index)); 2495 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2496 2497 i = UPS_HIGH_SPEED; 2498 if (sc->sc_flags & EHCIF_ETTF) { 2499 /* 2500 * If we are doing embedded transaction translation, 2501 * then directly attached LS/FS devices are reset by 2502 * the EHCI controller itself. PSPD is encoded 2503 * the same way as in USBSTATUS. 2504 */ 2505 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2506 } 2507 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2508 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2509 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2510 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2511 if (v & EHCI_PS_PR) i |= UPS_RESET; 2512 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2513 if (sc->sc_vendor_port_status) 2514 i = sc->sc_vendor_port_status(sc, v, i); 2515 USETW(ps.wPortStatus, i); 2516 i = 0; 2517 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2518 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2519 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2520 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2521 USETW(ps.wPortChange, i); 2522 totlen = min(len, sizeof(ps)); 2523 memcpy(buf, &ps, totlen); 2524 break; 2525 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2526 return -1; 2527 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2528 break; 2529 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2530 if (index < 1 || index > sc->sc_noport) { 2531 return -1; 2532 } 2533 port = EHCI_PORTSC(index); 2534 v = EOREAD4(sc, port); 2535 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2536 v &= ~EHCI_PS_CLEAR; 2537 switch(value) { 2538 case UHF_PORT_ENABLE: 2539 EOWRITE4(sc, port, v | EHCI_PS_PE); 2540 break; 2541 case UHF_PORT_SUSPEND: 2542 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2543 break; 2544 case UHF_PORT_RESET: 2545 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2546 if (EHCI_PS_IS_LOWSPEED(v) 2547 && sc->sc_ncomp > 0 2548 && !(sc->sc_flags & EHCIF_ETTF)) { 2549 /* 2550 * Low speed device on non-ETTF controller or 2551 * unaccompanied controller, give up ownership. 2552 */ 2553 ehci_disown(sc, index, 1); 2554 break; 2555 } 2556 /* Start reset sequence. */ 2557 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2558 EOWRITE4(sc, port, v | EHCI_PS_PR); 2559 /* Wait for reset to complete. */ 2560 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2561 if (sc->sc_dying) { 2562 return -1; 2563 } 2564 /* 2565 * An embedded transaction translator will automatically 2566 * terminate the reset sequence so there's no need to 2567 * it. 2568 */ 2569 v = EOREAD4(sc, port); 2570 if (v & EHCI_PS_PR) { 2571 /* Terminate reset sequence. */ 2572 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2573 /* Wait for HC to complete reset. */ 2574 usb_delay_ms(&sc->sc_bus, 2575 EHCI_PORT_RESET_COMPLETE); 2576 if (sc->sc_dying) { 2577 return -1; 2578 } 2579 } 2580 2581 v = EOREAD4(sc, port); 2582 USBHIST_LOG(ehcidebug, 2583 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2584 if (v & EHCI_PS_PR) { 2585 printf("%s: port reset timeout\n", 2586 device_xname(sc->sc_dev)); 2587 return USBD_TIMEOUT; 2588 } 2589 if (!(v & EHCI_PS_PE)) { 2590 /* Not a high speed device, give up ownership.*/ 2591 ehci_disown(sc, index, 0); 2592 break; 2593 } 2594 sc->sc_isreset[index] = 1; 2595 USBHIST_LOG(ehcidebug, 2596 "ehci port %d reset, status = 0x%08x", index, v, 0, 2597 0); 2598 break; 2599 case UHF_PORT_POWER: 2600 USBHIST_LOG(ehcidebug, 2601 "set port power %d (has PPC = %d)", index, 2602 sc->sc_hasppc, 0, 0); 2603 if (sc->sc_hasppc) 2604 EOWRITE4(sc, port, v | EHCI_PS_PP); 2605 break; 2606 case UHF_PORT_TEST: 2607 USBHIST_LOG(ehcidebug, "set port test %d", 2608 index, 0, 0, 0); 2609 break; 2610 case UHF_PORT_INDICATOR: 2611 USBHIST_LOG(ehcidebug, "set port ind %d", 2612 index, 0, 0, 0); 2613 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2614 break; 2615 default: 2616 return -1; 2617 } 2618 break; 2619 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2620 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2621 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2622 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2623 break; 2624 default: 2625 /* default from usbroothub */ 2626 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2627 buflen, 0, 0, 0); 2628 2629 return buflen; 2630 } 2631 2632 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2633 2634 return totlen; 2635 } 2636 2637 Static void 2638 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2639 { 2640 int port; 2641 uint32_t v; 2642 2643 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2644 2645 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2646 #ifdef DIAGNOSTIC 2647 if (sc->sc_npcomp != 0) { 2648 int i = (index-1) / sc->sc_npcomp; 2649 if (i >= sc->sc_ncomp) 2650 printf("%s: strange port\n", 2651 device_xname(sc->sc_dev)); 2652 else 2653 printf("%s: handing over %s speed device on " 2654 "port %d to %s\n", 2655 device_xname(sc->sc_dev), 2656 lowspeed ? "low" : "full", 2657 index, device_xname(sc->sc_comps[i])); 2658 } else { 2659 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2660 } 2661 #endif 2662 port = EHCI_PORTSC(index); 2663 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2664 EOWRITE4(sc, port, v | EHCI_PS_PO); 2665 } 2666 2667 Static usbd_status 2668 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2669 { 2670 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2671 usbd_status err; 2672 2673 /* Insert last in queue. */ 2674 mutex_enter(&sc->sc_lock); 2675 err = usb_insert_transfer(xfer); 2676 mutex_exit(&sc->sc_lock); 2677 if (err) 2678 return err; 2679 2680 /* Pipe isn't running, start first */ 2681 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2682 } 2683 2684 Static usbd_status 2685 ehci_root_intr_start(struct usbd_xfer *xfer) 2686 { 2687 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2688 2689 if (sc->sc_dying) 2690 return USBD_IOERROR; 2691 2692 mutex_enter(&sc->sc_lock); 2693 sc->sc_intrxfer = xfer; 2694 mutex_exit(&sc->sc_lock); 2695 2696 return USBD_IN_PROGRESS; 2697 } 2698 2699 /* Abort a root interrupt request. */ 2700 Static void 2701 ehci_root_intr_abort(struct usbd_xfer *xfer) 2702 { 2703 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2704 2705 KASSERT(mutex_owned(&sc->sc_lock)); 2706 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2707 2708 sc->sc_intrxfer = NULL; 2709 2710 xfer->ux_status = USBD_CANCELLED; 2711 usb_transfer_complete(xfer); 2712 } 2713 2714 /* Close the root pipe. */ 2715 Static void 2716 ehci_root_intr_close(struct usbd_pipe *pipe) 2717 { 2718 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2719 2720 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2721 2722 KASSERT(mutex_owned(&sc->sc_lock)); 2723 2724 sc->sc_intrxfer = NULL; 2725 } 2726 2727 Static void 2728 ehci_root_intr_done(struct usbd_xfer *xfer) 2729 { 2730 xfer->ux_hcpriv = NULL; 2731 } 2732 2733 /************************/ 2734 2735 Static ehci_soft_qh_t * 2736 ehci_alloc_sqh(ehci_softc_t *sc) 2737 { 2738 ehci_soft_qh_t *sqh; 2739 usbd_status err; 2740 int i, offs; 2741 usb_dma_t dma; 2742 2743 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2744 2745 mutex_enter(&sc->sc_lock); 2746 if (sc->sc_freeqhs == NULL) { 2747 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2748 mutex_exit(&sc->sc_lock); 2749 2750 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2751 EHCI_PAGE_SIZE, &dma); 2752 #ifdef EHCI_DEBUG 2753 if (err) 2754 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2755 #endif 2756 if (err) 2757 return NULL; 2758 2759 mutex_enter(&sc->sc_lock); 2760 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2761 offs = i * EHCI_SQH_SIZE; 2762 sqh = KERNADDR(&dma, offs); 2763 sqh->physaddr = DMAADDR(&dma, offs); 2764 sqh->dma = dma; 2765 sqh->offs = offs; 2766 sqh->next = sc->sc_freeqhs; 2767 sc->sc_freeqhs = sqh; 2768 } 2769 } 2770 sqh = sc->sc_freeqhs; 2771 sc->sc_freeqhs = sqh->next; 2772 mutex_exit(&sc->sc_lock); 2773 2774 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2775 sqh->next = NULL; 2776 return sqh; 2777 } 2778 2779 Static void 2780 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2781 { 2782 KASSERT(mutex_owned(&sc->sc_lock)); 2783 2784 sqh->next = sc->sc_freeqhs; 2785 sc->sc_freeqhs = sqh; 2786 } 2787 2788 Static ehci_soft_qtd_t * 2789 ehci_alloc_sqtd(ehci_softc_t *sc) 2790 { 2791 ehci_soft_qtd_t *sqtd = NULL; 2792 usbd_status err; 2793 int i, offs; 2794 usb_dma_t dma; 2795 2796 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2797 2798 mutex_enter(&sc->sc_lock); 2799 if (sc->sc_freeqtds == NULL) { 2800 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2801 mutex_exit(&sc->sc_lock); 2802 2803 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2804 EHCI_PAGE_SIZE, &dma); 2805 #ifdef EHCI_DEBUG 2806 if (err) 2807 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2808 #endif 2809 if (err) 2810 goto done; 2811 2812 mutex_enter(&sc->sc_lock); 2813 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2814 offs = i * EHCI_SQTD_SIZE; 2815 sqtd = KERNADDR(&dma, offs); 2816 sqtd->physaddr = DMAADDR(&dma, offs); 2817 sqtd->dma = dma; 2818 sqtd->offs = offs; 2819 2820 sqtd->nextqtd = sc->sc_freeqtds; 2821 sc->sc_freeqtds = sqtd; 2822 } 2823 } 2824 2825 sqtd = sc->sc_freeqtds; 2826 sc->sc_freeqtds = sqtd->nextqtd; 2827 mutex_exit(&sc->sc_lock); 2828 2829 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2830 sqtd->nextqtd = NULL; 2831 sqtd->xfer = NULL; 2832 2833 done: 2834 return sqtd; 2835 } 2836 2837 Static void 2838 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2839 { 2840 2841 mutex_enter(&sc->sc_lock); 2842 sqtd->nextqtd = sc->sc_freeqtds; 2843 sc->sc_freeqtds = sqtd; 2844 mutex_exit(&sc->sc_lock); 2845 } 2846 2847 Static usbd_status 2848 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2849 int alen, int rd, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2850 { 2851 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2852 ehci_soft_qtd_t *next, *cur; 2853 ehci_physaddr_t nextphys; 2854 uint32_t qtdstatus; 2855 int len, curlen, mps; 2856 int i, tog; 2857 int pages, pageoffs; 2858 size_t curoffs; 2859 vaddr_t va, va_offs; 2860 usb_dma_t *dma = &xfer->ux_dmabuf; 2861 uint16_t flags = xfer->ux_flags; 2862 paddr_t a; 2863 2864 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2865 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2866 2867 ASSERT_SLEEPABLE(); 2868 KASSERT(sp); 2869 KASSERT(alen != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2870 2871 len = alen; 2872 qtdstatus = EHCI_QTD_ACTIVE | 2873 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2874 EHCI_QTD_SET_CERR(3) 2875 ; 2876 2877 size_t nsqtd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 2878 nsqtd += ((len + EHCI_QTD_MAXTRANSFER - 1) / EHCI_QTD_MAXTRANSFER); 2879 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2880 KM_SLEEP); 2881 exfer->ex_nsqtd = nsqtd; 2882 2883 mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2884 cur = ehci_alloc_sqtd(sc); 2885 *sp = cur; 2886 if (cur == NULL) 2887 goto nomem; 2888 2889 curoffs = 0; 2890 for (size_t j = 0;;) { 2891 KASSERT(j < nsqtd); 2892 exfer->ex_sqtds[j++] = cur; 2893 2894 /* The EHCI hardware can handle at most 5 pages. */ 2895 va = (vaddr_t)KERNADDR(dma, curoffs); 2896 va_offs = EHCI_PAGE_OFFSET(va); 2897 if (len - curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2898 /* we can handle it in this QTD */ 2899 curlen = len - curoffs; 2900 } else { 2901 /* must use multiple TDs, fill as much as possible. */ 2902 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2903 2904 /* the length must be a multiple of the max size */ 2905 curlen -= curlen % mps; 2906 USBHIST_LOG(ehcidebug, "multiple QTDs, curlen=%d", 2907 curlen, 0, 0, 0); 2908 KASSERT(curlen != 0); 2909 } 2910 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", len, 2911 curlen, curoffs, 0); 2912 2913 /* 2914 * Allocate another transfer if there's more data left, 2915 * or if force last short transfer flag is set and we're 2916 * allocating a multiple of the max packet size. 2917 */ 2918 2919 if (curoffs + curlen != len || 2920 ((curlen % mps) == 0 && !rd && curlen != 0 && 2921 (flags & USBD_FORCE_SHORT_XFER))) { 2922 next = ehci_alloc_sqtd(sc); 2923 if (next == NULL) 2924 goto nomem; 2925 nextphys = htole32(next->physaddr); 2926 } else { 2927 next = NULL; 2928 nextphys = EHCI_NULL; 2929 } 2930 2931 /* Find number of pages we'll be using, insert dma addresses */ 2932 pages = EHCI_NPAGES(curlen); 2933 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2934 pageoffs = EHCI_PAGE(curoffs); 2935 for (i = 0; i < pages; i++) { 2936 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2937 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2938 /* Cast up to avoid compiler warnings */ 2939 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2940 } 2941 2942 /* First buffer pointer requires a page offset to start at */ 2943 cur->qtd.qtd_buffer[0] |= htole32(va_offs); 2944 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2945 cur->qtd.qtd_status = htole32(qtdstatus); 2946 cur->nextqtd = next; 2947 cur->xfer = xfer; 2948 cur->bufoff = curoffs; 2949 cur->tdlen = curlen; 2950 cur->len = 0; 2951 2952 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2953 curoffs, curoffs + curlen, 0, 0); 2954 2955 /* 2956 * adjust the toggle based on the number of packets in this 2957 * qtd 2958 */ 2959 if (((curlen + mps - 1) / mps) & 1) { 2960 tog ^= 1; 2961 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2962 } 2963 if (next == NULL) 2964 break; 2965 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2966 if (len) 2967 curoffs += curlen; 2968 cur = next; 2969 } 2970 if (ep) 2971 *ep = cur; 2972 2973 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", *sp, cur, 0, 0); 2974 2975 return USBD_NORMAL_COMPLETION; 2976 2977 nomem: 2978 ehci_free_sqtds(sc, exfer); 2979 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2980 return USBD_NOMEM; 2981 } 2982 2983 Static void 2984 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2985 { 2986 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2987 USBHIST_LOG(ehcidebug, "exfer=%p", exfer, 0, 0, 0); 2988 2989 mutex_enter(&sc->sc_lock); 2990 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2991 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2992 2993 if (sqtd == NULL) 2994 break; 2995 2996 sqtd->nextqtd = sc->sc_freeqtds; 2997 sc->sc_freeqtds = sqtd; 2998 } 2999 mutex_exit(&sc->sc_lock); 3000 } 3001 3002 Static void 3003 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3004 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3005 { 3006 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3007 ehci_soft_qtd_t *sqtd, *prev; 3008 int tog = *toggle; 3009 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3010 int len = length; 3011 size_t i; 3012 3013 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3014 USBHIST_LOG(ehcidebug, "xfer=%p len %d isread %d toggle %d", xfer, 3015 len, isread, *toggle); 3016 USBHIST_LOG(ehcidebug, " VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 3017 0, 0, 0); 3018 3019 sqtd = prev = NULL; 3020 for (i = 0; i < exfer->ex_nsqtd; i++, prev = sqtd) { 3021 sqtd = exfer->ex_sqtds[i]; 3022 vaddr_t va = (vaddr_t)KERNADDR(&xfer->ux_dmabuf, sqtd->bufoff); 3023 sqtd->len = sqtd->tdlen; 3024 if (len < sqtd->len) { 3025 sqtd->len = len; 3026 } 3027 3028 USBHIST_LOG(ehcidebug, "sqtd[%d]=%p prev %p len %d", i, sqtd, 3029 prev, sqtd->len); 3030 USBHIST_LOG(ehcidebug, " va %p bufoff %d pa %p", va, sqtd->bufoff, 3031 DMAADDR(&xfer->ux_dmabuf, sqtd->bufoff), 0); 3032 3033 if (prev) { 3034 prev->nextqtd = sqtd; 3035 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3036 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3037 } 3038 usb_syncmem(&sqtd->dma, 3039 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3040 sizeof(sqtd->qtd.qtd_status), 3041 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3042 usb_syncmem(&sqtd->dma, 3043 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3044 sizeof(sqtd->qtd.qtd_buffer[0]), 3045 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3046 3047 sqtd->qtd.qtd_buffer[0] &= ~htole32(EHCI_PAGE_MASK); 3048 sqtd->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3049 /* Reset ... */ 3050 sqtd->qtd.qtd_status &= ~htole32( 3051 EHCI_QTD_STATUS_MASK | 3052 EHCI_QTD_PID_MASK | 3053 EHCI_QTD_CERR_MASK | 3054 EHCI_QTD_C_PAGE_MASK | 3055 EHCI_QTD_BYTES_MASK | 3056 EHCI_QTD_TOGGLE_MASK); 3057 sqtd->qtd.qtd_status |= htole32( 3058 EHCI_QTD_ACTIVE | 3059 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3060 EHCI_QTD_SET_BYTES(sqtd->len) | 3061 EHCI_QTD_SET_CERR(3) | 3062 EHCI_QTD_SET_TOGGLE(tog)); 3063 3064 usb_syncmem(&sqtd->dma, 3065 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3066 sizeof(sqtd->qtd.qtd_status), 3067 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3068 usb_syncmem(&sqtd->dma, 3069 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3070 sizeof(sqtd->qtd.qtd_buffer[0]), 3071 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3072 3073 if (((sqtd->len + mps - 1) / mps) & 1) { 3074 tog ^= 1; 3075 } 3076 3077 len -= sqtd->len; 3078 if (len == 0) 3079 break; 3080 } 3081 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu i %zu", 3082 xfer, length, len, mps, exfer->ex_nsqtd, i); 3083 3084 if (i < exfer->ex_nsqtd) { 3085 /* 3086 * The full allocation chain wasn't used, so we need to 3087 * terminate it. 3088 */ 3089 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3090 } 3091 *lsqtd = sqtd; 3092 *toggle = tog; 3093 } 3094 3095 Static ehci_soft_itd_t * 3096 ehci_alloc_itd(ehci_softc_t *sc) 3097 { 3098 struct ehci_soft_itd *itd, *freeitd; 3099 usbd_status err; 3100 usb_dma_t dma; 3101 3102 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3103 3104 mutex_enter(&sc->sc_lock); 3105 3106 freeitd = LIST_FIRST(&sc->sc_freeitds); 3107 if (freeitd == NULL) { 3108 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3109 mutex_exit(&sc->sc_lock); 3110 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3111 EHCI_PAGE_SIZE, &dma); 3112 3113 if (err) { 3114 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 0); 3115 return NULL; 3116 } 3117 mutex_enter(&sc->sc_lock); 3118 3119 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3120 int offs = i * EHCI_ITD_SIZE; 3121 itd = KERNADDR(&dma, offs); 3122 itd->physaddr = DMAADDR(&dma, offs); 3123 itd->dma = dma; 3124 itd->offs = offs; 3125 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3126 } 3127 freeitd = LIST_FIRST(&sc->sc_freeitds); 3128 } 3129 3130 itd = freeitd; 3131 LIST_REMOVE(itd, free_list); 3132 mutex_exit(&sc->sc_lock); 3133 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3134 3135 itd->frame_list.next = NULL; 3136 itd->frame_list.prev = NULL; 3137 itd->xfer_next = NULL; 3138 itd->slot = 0; 3139 3140 return itd; 3141 } 3142 3143 Static ehci_soft_sitd_t * 3144 ehci_alloc_sitd(ehci_softc_t *sc) 3145 { 3146 struct ehci_soft_sitd *sitd, *freesitd; 3147 usbd_status err; 3148 int i, offs; 3149 usb_dma_t dma; 3150 3151 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3152 3153 mutex_enter(&sc->sc_lock); 3154 freesitd = LIST_FIRST(&sc->sc_freesitds); 3155 if (freesitd == NULL) { 3156 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3157 mutex_exit(&sc->sc_lock); 3158 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3159 EHCI_PAGE_SIZE, &dma); 3160 3161 if (err) { 3162 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 3163 0); 3164 return NULL; 3165 } 3166 3167 mutex_enter(&sc->sc_lock); 3168 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3169 offs = i * EHCI_SITD_SIZE; 3170 sitd = KERNADDR(&dma, offs); 3171 sitd->physaddr = DMAADDR(&dma, offs); 3172 sitd->dma = dma; 3173 sitd->offs = offs; 3174 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3175 } 3176 freesitd = LIST_FIRST(&sc->sc_freesitds); 3177 } 3178 3179 sitd = freesitd; 3180 LIST_REMOVE(sitd, free_list); 3181 mutex_exit(&sc->sc_lock); 3182 3183 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3184 3185 sitd->frame_list.next = NULL; 3186 sitd->frame_list.prev = NULL; 3187 sitd->xfer_next = NULL; 3188 sitd->slot = 0; 3189 3190 return sitd; 3191 } 3192 3193 /****************/ 3194 3195 /* 3196 * Close a reqular pipe. 3197 * Assumes that there are no pending transactions. 3198 */ 3199 Static void 3200 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3201 { 3202 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3203 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3204 ehci_soft_qh_t *sqh = epipe->sqh; 3205 3206 KASSERT(mutex_owned(&sc->sc_lock)); 3207 3208 ehci_rem_qh(sc, sqh, head); 3209 ehci_free_sqh(sc, epipe->sqh); 3210 } 3211 3212 /* 3213 * Abort a device request. 3214 * If this routine is called at splusb() it guarantees that the request 3215 * will be removed from the hardware scheduling and that the callback 3216 * for it will be called with USBD_CANCELLED status. 3217 * It's impossible to guarantee that the requested transfer will not 3218 * have happened since the hardware runs concurrently. 3219 * If the transaction has already happened we rely on the ordinary 3220 * interrupt processing to process it. 3221 * XXX This is most probably wrong. 3222 * XXXMRG this doesn't make sense anymore. 3223 */ 3224 Static void 3225 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3226 { 3227 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3228 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3229 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3230 ehci_soft_qh_t *sqh = epipe->sqh; 3231 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3232 ehci_physaddr_t cur; 3233 uint32_t qhstatus; 3234 int hit; 3235 int wake; 3236 3237 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3238 3239 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3240 3241 KASSERT(mutex_owned(&sc->sc_lock)); 3242 ASSERT_SLEEPABLE(); 3243 3244 if (sc->sc_dying) { 3245 /* If we're dying, just do the software part. */ 3246 xfer->ux_status = status; /* make software ignore it */ 3247 callout_stop(&xfer->ux_callout); 3248 usb_transfer_complete(xfer); 3249 return; 3250 } 3251 3252 /* 3253 * If an abort is already in progress then just wait for it to 3254 * complete and return. 3255 */ 3256 if (xfer->ux_hcflags & UXFER_ABORTING) { 3257 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3258 #ifdef DIAGNOSTIC 3259 if (status == USBD_TIMEOUT) 3260 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3261 #endif 3262 /* Override the status which might be USBD_TIMEOUT. */ 3263 xfer->ux_status = status; 3264 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3265 0, 0, 0, 0); 3266 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3267 while (xfer->ux_hcflags & UXFER_ABORTING) 3268 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3269 return; 3270 } 3271 xfer->ux_hcflags |= UXFER_ABORTING; 3272 3273 /* 3274 * Step 1: Make interrupt routine and hardware ignore xfer. 3275 */ 3276 xfer->ux_status = status; /* make software ignore it */ 3277 callout_stop(&xfer->ux_callout); 3278 ehci_del_intr_list(sc, exfer); 3279 3280 usb_syncmem(&sqh->dma, 3281 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3282 sizeof(sqh->qh.qh_qtd.qtd_status), 3283 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3284 qhstatus = sqh->qh.qh_qtd.qtd_status; 3285 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3286 usb_syncmem(&sqh->dma, 3287 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3288 sizeof(sqh->qh.qh_qtd.qtd_status), 3289 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3290 3291 if (exfer->ex_type == EX_CTRL) { 3292 fsqtd = exfer->ex_setup; 3293 lsqtd = exfer->ex_status; 3294 } else { 3295 fsqtd = exfer->ex_sqtdstart; 3296 lsqtd = exfer->ex_sqtdend; 3297 } 3298 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3299 usb_syncmem(&sqtd->dma, 3300 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3301 sizeof(sqtd->qtd.qtd_status), 3302 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3303 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3304 usb_syncmem(&sqtd->dma, 3305 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3306 sizeof(sqtd->qtd.qtd_status), 3307 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3308 if (sqtd == lsqtd) 3309 break; 3310 } 3311 3312 /* 3313 * Step 2: Wait until we know hardware has finished any possible 3314 * use of the xfer. Also make sure the soft interrupt routine 3315 * has run. 3316 */ 3317 ehci_sync_hc(sc); 3318 sc->sc_softwake = 1; 3319 usb_schedsoftintr(&sc->sc_bus); 3320 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3321 3322 /* 3323 * Step 3: Remove any vestiges of the xfer from the hardware. 3324 * The complication here is that the hardware may have executed 3325 * beyond the xfer we're trying to abort. So as we're scanning 3326 * the TDs of this xfer we check if the hardware points to 3327 * any of them. 3328 */ 3329 3330 usb_syncmem(&sqh->dma, 3331 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3332 sizeof(sqh->qh.qh_curqtd), 3333 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3334 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3335 hit = 0; 3336 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3337 hit |= cur == sqtd->physaddr; 3338 if (sqtd == lsqtd) 3339 break; 3340 } 3341 sqtd = sqtd->nextqtd; 3342 /* Zap curqtd register if hardware pointed inside the xfer. */ 3343 if (hit && sqtd != NULL) { 3344 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3345 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3346 usb_syncmem(&sqh->dma, 3347 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3348 sizeof(sqh->qh.qh_curqtd), 3349 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3350 sqh->qh.qh_qtd.qtd_status = qhstatus; 3351 usb_syncmem(&sqh->dma, 3352 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3353 sizeof(sqh->qh.qh_qtd.qtd_status), 3354 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3355 } else { 3356 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3357 usb_syncmem(&sqh->dma, 3358 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3359 sizeof(sqh->qh.qh_curqtd), 3360 BUS_DMASYNC_PREREAD); 3361 } 3362 3363 /* 3364 * Step 4: Execute callback. 3365 */ 3366 #ifdef DIAGNOSTIC 3367 exfer->ex_isdone = true; 3368 #endif 3369 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3370 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3371 usb_transfer_complete(xfer); 3372 if (wake) { 3373 cv_broadcast(&xfer->ux_hccv); 3374 } 3375 3376 KASSERT(mutex_owned(&sc->sc_lock)); 3377 } 3378 3379 Static void 3380 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3381 { 3382 ehci_isoc_trans_t trans_status; 3383 struct ehci_xfer *exfer; 3384 ehci_softc_t *sc; 3385 struct ehci_soft_itd *itd; 3386 struct ehci_soft_sitd *sitd; 3387 int i, wake; 3388 3389 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3390 3391 exfer = EHCI_XFER2EXFER(xfer); 3392 sc = EHCI_XFER2SC(xfer); 3393 3394 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3395 3396 KASSERT(mutex_owned(&sc->sc_lock)); 3397 3398 if (sc->sc_dying) { 3399 xfer->ux_status = status; 3400 callout_stop(&xfer->ux_callout); 3401 usb_transfer_complete(xfer); 3402 return; 3403 } 3404 3405 if (xfer->ux_hcflags & UXFER_ABORTING) { 3406 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3407 3408 #ifdef DIAGNOSTIC 3409 if (status == USBD_TIMEOUT) 3410 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3411 #endif 3412 3413 xfer->ux_status = status; 3414 USBHIST_LOG(ehcidebug, 3415 "waiting for abort to finish", 0, 0, 0, 0); 3416 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3417 while (xfer->ux_hcflags & UXFER_ABORTING) 3418 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3419 goto done; 3420 } 3421 xfer->ux_hcflags |= UXFER_ABORTING; 3422 3423 xfer->ux_status = status; 3424 callout_stop(&xfer->ux_callout); 3425 3426 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3427 for (itd = exfer->ex_itdstart; itd != NULL; 3428 itd = itd->xfer_next) { 3429 usb_syncmem(&itd->dma, 3430 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3431 sizeof(itd->itd.itd_ctl), 3432 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3433 3434 for (i = 0; i < 8; i++) { 3435 trans_status = le32toh(itd->itd.itd_ctl[i]); 3436 trans_status &= ~EHCI_ITD_ACTIVE; 3437 itd->itd.itd_ctl[i] = htole32(trans_status); 3438 } 3439 3440 usb_syncmem(&itd->dma, 3441 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3442 sizeof(itd->itd.itd_ctl), 3443 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3444 } 3445 } else { 3446 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3447 sitd = sitd->xfer_next) { 3448 usb_syncmem(&sitd->dma, 3449 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3450 sizeof(sitd->sitd.sitd_buffer), 3451 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3452 3453 trans_status = le32toh(sitd->sitd.sitd_trans); 3454 trans_status &= ~EHCI_SITD_ACTIVE; 3455 sitd->sitd.sitd_trans = htole32(trans_status); 3456 3457 usb_syncmem(&sitd->dma, 3458 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3459 sizeof(sitd->sitd.sitd_buffer), 3460 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3461 } 3462 } 3463 3464 sc->sc_softwake = 1; 3465 usb_schedsoftintr(&sc->sc_bus); 3466 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3467 3468 #ifdef DIAGNOSTIC 3469 exfer->ex_isdone = true; 3470 #endif 3471 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3472 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3473 usb_transfer_complete(xfer); 3474 if (wake) { 3475 cv_broadcast(&xfer->ux_hccv); 3476 } 3477 3478 done: 3479 KASSERT(mutex_owned(&sc->sc_lock)); 3480 return; 3481 } 3482 3483 Static void 3484 ehci_timeout(void *addr) 3485 { 3486 struct usbd_xfer *xfer = addr; 3487 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3488 struct usbd_pipe *pipe = xfer->ux_pipe; 3489 struct usbd_device *dev = pipe->up_dev; 3490 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3491 3492 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3493 3494 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3495 #ifdef EHCI_DEBUG 3496 if (ehcidebug >= 2) 3497 usbd_dump_pipe(pipe); 3498 #endif 3499 3500 if (sc->sc_dying) { 3501 mutex_enter(&sc->sc_lock); 3502 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3503 mutex_exit(&sc->sc_lock); 3504 return; 3505 } 3506 3507 /* Execute the abort in a process context. */ 3508 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3509 USB_TASKQ_MPSAFE); 3510 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3511 } 3512 3513 Static void 3514 ehci_timeout_task(void *addr) 3515 { 3516 struct usbd_xfer *xfer = addr; 3517 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3518 3519 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3520 3521 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3522 3523 mutex_enter(&sc->sc_lock); 3524 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3525 mutex_exit(&sc->sc_lock); 3526 } 3527 3528 /************************/ 3529 3530 Static int 3531 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3532 { 3533 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3534 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3535 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3536 usb_device_request_t *req = &xfer->ux_request; 3537 ehci_soft_qtd_t *setup, *status, *next; 3538 int isread = req->bmRequestType & UT_READ; 3539 int len = xfer->ux_bufsize; 3540 int err; 3541 3542 exfer->ex_type = EX_CTRL; 3543 exfer->ex_status = NULL; 3544 exfer->ex_data = NULL; 3545 exfer->ex_setup = ehci_alloc_sqtd(sc); 3546 if (exfer->ex_setup == NULL) { 3547 err = ENOMEM; 3548 goto bad1; 3549 } 3550 exfer->ex_status = ehci_alloc_sqtd(sc); 3551 if (exfer->ex_status == NULL) { 3552 err = ENOMEM; 3553 goto bad2; 3554 } 3555 setup = exfer->ex_setup; 3556 status = exfer->ex_status; 3557 exfer->ex_nsqtd = 0; 3558 next = status; 3559 /* Set up data transaction */ 3560 if (len != 0) { 3561 ehci_soft_qtd_t *end; 3562 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3563 &exfer->ex_data, &end); 3564 if (err) 3565 goto bad3; 3566 next = exfer->ex_data; 3567 } 3568 3569 /* Clear toggle */ 3570 setup->qtd.qtd_status = htole32( 3571 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3572 EHCI_QTD_SET_TOGGLE(0) | 3573 EHCI_QTD_SET_BYTES(sizeof(*req)) 3574 ); 3575 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3576 setup->qtd.qtd_buffer_hi[0] = 0; 3577 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3578 setup->nextqtd = next; 3579 setup->xfer = xfer; 3580 setup->tdlen = setup->len = sizeof(*req); 3581 3582 status->qtd.qtd_status = htole32( 3583 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3584 EHCI_QTD_SET_TOGGLE(1) | 3585 EHCI_QTD_IOC 3586 ); 3587 status->qtd.qtd_buffer[0] = 0; 3588 status->qtd.qtd_buffer_hi[0] = 0; 3589 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3590 status->nextqtd = NULL; 3591 status->xfer = xfer; 3592 status->tdlen = status->len = 0; 3593 3594 return 0; 3595 bad3: 3596 ehci_free_sqtd(sc, exfer->ex_status); 3597 bad2: 3598 ehci_free_sqtd(sc, exfer->ex_setup); 3599 bad1: 3600 return err; 3601 } 3602 3603 Static void 3604 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3605 { 3606 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3607 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3608 3609 KASSERT(ex->ex_type == EX_CTRL); 3610 3611 ehci_free_sqtd(sc, ex->ex_setup); 3612 ehci_free_sqtd(sc, ex->ex_status); 3613 ehci_free_sqtds(sc, ex); 3614 if (ex->ex_nsqtd) 3615 kmem_free(ex->ex_sqtds, 3616 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3617 } 3618 3619 Static usbd_status 3620 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3621 { 3622 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3623 usbd_status err; 3624 3625 /* Insert last in queue. */ 3626 mutex_enter(&sc->sc_lock); 3627 err = usb_insert_transfer(xfer); 3628 mutex_exit(&sc->sc_lock); 3629 if (err) 3630 return err; 3631 3632 /* Pipe isn't running, start first */ 3633 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3634 } 3635 3636 Static usbd_status 3637 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3638 { 3639 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3640 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3641 usb_device_request_t *req = &xfer->ux_request; 3642 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3643 ehci_soft_qtd_t *setup, *status, *next; 3644 ehci_soft_qh_t *sqh; 3645 3646 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3647 3648 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3649 3650 if (sc->sc_dying) 3651 return USBD_IOERROR; 3652 3653 const int isread = req->bmRequestType & UT_READ; 3654 const int len = UGETW(req->wLength); 3655 3656 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3657 "wValue=0x%04x, wIndex=0x%04x", 3658 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3659 UGETW(req->wIndex)); 3660 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3661 len, epipe->pipe.up_dev->ud_addr, 3662 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3663 3664 sqh = epipe->sqh; 3665 3666 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3667 "address QH %" __PRIuBIT " pipe %d\n", 3668 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3669 epipe->pipe.up_dev->ud_addr); 3670 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3671 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3672 "MPS QH %" __PRIuBIT " pipe %d\n", 3673 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3674 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3675 3676 setup = exfer->ex_setup; 3677 status = exfer->ex_status; 3678 3679 USBHIST_LOG(ehcidebug, "setup %p status %p data %p", 3680 setup, status, exfer->ex_data, 0); 3681 KASSERTMSG(setup != NULL && status != NULL, 3682 "Failed memory allocation, setup %p status %p", 3683 setup, status); 3684 3685 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3686 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3687 3688 /* Clear toggle */ 3689 setup->qtd.qtd_status &= ~htole32( 3690 EHCI_QTD_STATUS_MASK | 3691 EHCI_QTD_BYTES_MASK | 3692 EHCI_QTD_TOGGLE_MASK | 3693 EHCI_QTD_CERR_MASK 3694 ); 3695 setup->qtd.qtd_status |= htole32( 3696 EHCI_QTD_ACTIVE | 3697 EHCI_QTD_SET_CERR(3) | 3698 EHCI_QTD_SET_TOGGLE(0) | 3699 EHCI_QTD_SET_BYTES(sizeof(*req)) 3700 ); 3701 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3702 setup->qtd.qtd_buffer_hi[0] = 0; 3703 3704 next = status; 3705 status->qtd.qtd_status &= ~htole32( 3706 EHCI_QTD_STATUS_MASK | 3707 EHCI_QTD_PID_MASK | 3708 EHCI_QTD_BYTES_MASK | 3709 EHCI_QTD_TOGGLE_MASK | 3710 EHCI_QTD_CERR_MASK 3711 ); 3712 status->qtd.qtd_status |= htole32( 3713 EHCI_QTD_ACTIVE | 3714 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3715 EHCI_QTD_SET_CERR(3) | 3716 EHCI_QTD_SET_TOGGLE(1) | 3717 EHCI_QTD_SET_BYTES(0) | 3718 EHCI_QTD_IOC 3719 ); 3720 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3721 3722 KASSERT(exfer->ex_isdone); 3723 #ifdef DIAGNOSTIC 3724 exfer->ex_isdone = false; 3725 #endif 3726 3727 /* Set up data transaction */ 3728 if (len != 0) { 3729 ehci_soft_qtd_t *end; 3730 3731 /* Start toggle at 1. */ 3732 int toggle = 1; 3733 next = exfer->ex_data; 3734 KASSERTMSG(next != NULL, "Failed memory allocation"); 3735 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3736 end->nextqtd = status; 3737 end->qtd.qtd_next = end->qtd.qtd_altnext = 3738 htole32(status->physaddr); 3739 3740 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3741 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3742 3743 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3744 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3745 } 3746 3747 setup->nextqtd = next; 3748 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3749 3750 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3752 3753 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3754 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3755 3756 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3757 3758 #ifdef EHCI_DEBUG 3759 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3760 ehci_dump_sqh(sqh); 3761 ehci_dump_sqtds(setup); 3762 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3763 #endif 3764 3765 mutex_enter(&sc->sc_lock); 3766 3767 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3768 ehci_set_qh_qtd(sqh, setup); 3769 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3770 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3771 ehci_timeout, xfer); 3772 } 3773 ehci_add_intr_list(sc, exfer); 3774 xfer->ux_status = USBD_IN_PROGRESS; 3775 mutex_exit(&sc->sc_lock); 3776 3777 #if 0 3778 #ifdef EHCI_DEBUG 3779 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3780 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3781 // delay(10000); 3782 ehci_dump_regs(sc); 3783 ehci_dump_sqh(sc->sc_async_head); 3784 ehci_dump_sqh(sqh); 3785 ehci_dump_sqtds(setup); 3786 #endif 3787 #endif 3788 3789 if (sc->sc_bus.ub_usepolling) 3790 ehci_waitintr(sc, xfer); 3791 3792 return USBD_IN_PROGRESS; 3793 } 3794 3795 Static void 3796 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3797 { 3798 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3799 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3800 usb_device_request_t *req = &xfer->ux_request; 3801 int len = UGETW(req->wLength); 3802 int rd = req->bmRequestType & UT_READ; 3803 3804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3805 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3806 3807 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3808 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3809 3810 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3811 BUS_DMASYNC_POSTWRITE); 3812 if (len) 3813 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3814 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3815 3816 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3817 } 3818 3819 /* Abort a device control request. */ 3820 Static void 3821 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3822 { 3823 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3824 3825 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3826 ehci_abort_xfer(xfer, USBD_CANCELLED); 3827 } 3828 3829 /* Close a device control pipe. */ 3830 Static void 3831 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3832 { 3833 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3834 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3835 3836 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3837 3838 KASSERT(mutex_owned(&sc->sc_lock)); 3839 3840 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3841 3842 ehci_close_pipe(pipe, sc->sc_async_head); 3843 } 3844 3845 /* 3846 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3847 * qTD status, or miss signalling occasionally under heavy load. If the host 3848 * machine is too fast, we we can miss transaction completion - when we scan 3849 * the active list the transaction still seems to be active. This generally 3850 * exhibits itself as a umass stall that never recovers. 3851 * 3852 * We work around this behaviour by setting up this callback after any softintr 3853 * that completes with transactions still pending, giving us another chance to 3854 * check for completion after the writeback has taken place. 3855 */ 3856 Static void 3857 ehci_intrlist_timeout(void *arg) 3858 { 3859 ehci_softc_t *sc = arg; 3860 3861 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3862 3863 usb_schedsoftintr(&sc->sc_bus); 3864 } 3865 3866 /************************/ 3867 3868 Static int 3869 ehci_device_bulk_init(struct usbd_xfer *xfer) 3870 { 3871 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3872 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3873 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3874 int endpt = ed->bEndpointAddress; 3875 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3876 int len = xfer->ux_bufsize; 3877 int err = 0; 3878 3879 exfer->ex_type = EX_BULK; 3880 exfer->ex_nsqtd = 0; 3881 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3882 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 3883 3884 return err; 3885 } 3886 3887 Static void 3888 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3889 { 3890 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3891 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3892 3893 KASSERT(ex->ex_type == EX_BULK); 3894 3895 ehci_free_sqtds(sc, ex); 3896 if (ex->ex_nsqtd) 3897 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3898 } 3899 3900 Static usbd_status 3901 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3902 { 3903 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3904 usbd_status err; 3905 3906 /* Insert last in queue. */ 3907 mutex_enter(&sc->sc_lock); 3908 err = usb_insert_transfer(xfer); 3909 mutex_exit(&sc->sc_lock); 3910 if (err) 3911 return err; 3912 3913 /* Pipe isn't running, start first */ 3914 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3915 } 3916 3917 Static usbd_status 3918 ehci_device_bulk_start(struct usbd_xfer *xfer) 3919 { 3920 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3921 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3922 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3923 ehci_soft_qh_t *sqh; 3924 ehci_soft_qtd_t *end; 3925 int len, isread, endpt; 3926 3927 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3928 3929 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3930 xfer, xfer->ux_length, xfer->ux_flags, 0); 3931 3932 if (sc->sc_dying) 3933 return USBD_IOERROR; 3934 3935 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3936 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3937 3938 len = xfer->ux_length; 3939 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3940 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3941 sqh = epipe->sqh; 3942 3943 KASSERT(exfer->ex_isdone); 3944 #ifdef DIAGNOSTIC 3945 exfer->ex_isdone = false; 3946 #endif 3947 3948 /* Take lock here to protect nexttoggle */ 3949 mutex_enter(&sc->sc_lock); 3950 3951 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3952 3953 exfer->ex_sqtdend = end; 3954 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3955 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3956 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3957 3958 #ifdef EHCI_DEBUG 3959 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3960 ehci_dump_sqh(sqh); 3961 ehci_dump_sqtds(exfer->ex_sqtdstart); 3962 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3963 #endif 3964 3965 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3966 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3967 3968 /* also does usb_syncmem(sqh) */ 3969 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3970 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3971 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3972 ehci_timeout, xfer); 3973 } 3974 ehci_add_intr_list(sc, exfer); 3975 xfer->ux_status = USBD_IN_PROGRESS; 3976 mutex_exit(&sc->sc_lock); 3977 3978 #if 0 3979 #ifdef EHCI_DEBUG 3980 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3981 // delay(10000); 3982 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3983 ehci_dump_regs(sc); 3984 #if 0 3985 printf("async_head:\n"); 3986 ehci_dump_sqh(sc->sc_async_head); 3987 #endif 3988 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3989 ehci_dump_sqh(sqh); 3990 ehci_dump_sqtds(exfer->ex_sqtdstart); 3991 #endif 3992 #endif 3993 3994 if (sc->sc_bus.ub_usepolling) 3995 ehci_waitintr(sc, xfer); 3996 3997 return USBD_IN_PROGRESS; 3998 } 3999 4000 Static void 4001 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4002 { 4003 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4004 4005 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 4006 ehci_abort_xfer(xfer, USBD_CANCELLED); 4007 } 4008 4009 /* 4010 * Close a device bulk pipe. 4011 */ 4012 Static void 4013 ehci_device_bulk_close(struct usbd_pipe *pipe) 4014 { 4015 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4016 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4017 4018 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4019 4020 KASSERT(mutex_owned(&sc->sc_lock)); 4021 4022 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 4023 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4024 ehci_close_pipe(pipe, sc->sc_async_head); 4025 } 4026 4027 Static void 4028 ehci_device_bulk_done(struct usbd_xfer *xfer) 4029 { 4030 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4031 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4032 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4033 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4034 4035 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4036 4037 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4038 0, 0); 4039 4040 KASSERT(mutex_owned(&sc->sc_lock)); 4041 4042 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4043 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4044 4045 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 4046 } 4047 4048 /************************/ 4049 4050 Static usbd_status 4051 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4052 { 4053 struct ehci_soft_islot *isp; 4054 int islot, lev; 4055 4056 /* Find a poll rate that is large enough. */ 4057 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4058 if (EHCI_ILEV_IVAL(lev) <= ival) 4059 break; 4060 4061 /* Pick an interrupt slot at the right level. */ 4062 /* XXX could do better than picking at random */ 4063 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4064 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4065 4066 sqh->islot = islot; 4067 isp = &sc->sc_islots[islot]; 4068 mutex_enter(&sc->sc_lock); 4069 ehci_add_qh(sc, sqh, isp->sqh); 4070 mutex_exit(&sc->sc_lock); 4071 4072 return USBD_NORMAL_COMPLETION; 4073 } 4074 4075 4076 Static int 4077 ehci_device_intr_init(struct usbd_xfer *xfer) 4078 { 4079 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4080 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4081 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4082 int endpt = ed->bEndpointAddress; 4083 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4084 int len = xfer->ux_bufsize; 4085 int err; 4086 4087 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4088 4089 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4090 xfer->ux_flags, 0); 4091 4092 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4093 KASSERT(len != 0); 4094 4095 exfer->ex_type = EX_INTR; 4096 exfer->ex_nsqtd = 0; 4097 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4098 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 4099 4100 return err; 4101 } 4102 4103 Static void 4104 ehci_device_intr_fini(struct usbd_xfer *xfer) 4105 { 4106 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4107 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4108 4109 KASSERT(ex->ex_type == EX_INTR); 4110 4111 ehci_free_sqtds(sc, ex); 4112 if (ex->ex_nsqtd) 4113 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4114 } 4115 4116 Static usbd_status 4117 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4118 { 4119 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4120 usbd_status err; 4121 4122 /* Insert last in queue. */ 4123 mutex_enter(&sc->sc_lock); 4124 err = usb_insert_transfer(xfer); 4125 mutex_exit(&sc->sc_lock); 4126 if (err) 4127 return err; 4128 4129 /* 4130 * Pipe isn't running (otherwise err would be USBD_INPROG), 4131 * so start it first. 4132 */ 4133 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4134 } 4135 4136 Static usbd_status 4137 ehci_device_intr_start(struct usbd_xfer *xfer) 4138 { 4139 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4140 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4141 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4142 ehci_soft_qtd_t *end; 4143 ehci_soft_qh_t *sqh; 4144 int len, isread, endpt; 4145 4146 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4147 4148 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4149 xfer->ux_flags, 0); 4150 4151 if (sc->sc_dying) 4152 return USBD_IOERROR; 4153 4154 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4155 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4156 4157 len = xfer->ux_length; 4158 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4159 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4160 sqh = epipe->sqh; 4161 4162 KASSERT(exfer->ex_isdone); 4163 #ifdef DIAGNOSTIC 4164 exfer->ex_isdone = false; 4165 #endif 4166 4167 /* Take lock to protect nexttoggle */ 4168 mutex_enter(&sc->sc_lock); 4169 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4170 4171 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4172 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4173 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4174 exfer->ex_sqtdend = end; 4175 4176 #ifdef EHCI_DEBUG 4177 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 4178 ehci_dump_sqh(sqh); 4179 ehci_dump_sqtds(exfer->ex_sqtdstart); 4180 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 4181 #endif 4182 4183 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4184 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4185 4186 /* also does usb_syncmem(sqh) */ 4187 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4188 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4189 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4190 ehci_timeout, xfer); 4191 } 4192 ehci_add_intr_list(sc, exfer); 4193 xfer->ux_status = USBD_IN_PROGRESS; 4194 mutex_exit(&sc->sc_lock); 4195 4196 #if 0 4197 #ifdef EHCI_DEBUG 4198 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4199 // delay(10000); 4200 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4201 ehci_dump_regs(sc); 4202 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4203 ehci_dump_sqh(sqh); 4204 ehci_dump_sqtds(exfer->ex_sqtdstart); 4205 #endif 4206 #endif 4207 4208 if (sc->sc_bus.ub_usepolling) 4209 ehci_waitintr(sc, xfer); 4210 4211 return USBD_IN_PROGRESS; 4212 } 4213 4214 Static void 4215 ehci_device_intr_abort(struct usbd_xfer *xfer) 4216 { 4217 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4218 4219 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4220 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4221 4222 /* 4223 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4224 * async doorbell. That's dependent on the async list, wheras 4225 * intr xfers are periodic, should not use this? 4226 */ 4227 ehci_abort_xfer(xfer, USBD_CANCELLED); 4228 } 4229 4230 Static void 4231 ehci_device_intr_close(struct usbd_pipe *pipe) 4232 { 4233 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4234 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4235 struct ehci_soft_islot *isp; 4236 4237 KASSERT(mutex_owned(&sc->sc_lock)); 4238 4239 isp = &sc->sc_islots[epipe->sqh->islot]; 4240 ehci_close_pipe(pipe, isp->sqh); 4241 } 4242 4243 Static void 4244 ehci_device_intr_done(struct usbd_xfer *xfer) 4245 { 4246 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4247 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4248 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4249 ehci_soft_qh_t *sqh; 4250 int len, isread, endpt; 4251 4252 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4253 4254 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4255 0, 0); 4256 4257 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4258 4259 if (xfer->ux_pipe->up_repeat) { 4260 4261 KASSERT(exfer->ex_isdone); 4262 #ifdef DIAGNOSTIC 4263 exfer->ex_isdone = false; 4264 #endif 4265 4266 len = xfer->ux_length; 4267 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4268 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4269 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4270 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4271 sqh = epipe->sqh; 4272 4273 ehci_soft_qtd_t *end; 4274 ehci_reset_sqtd_chain(sc, xfer, len, isread, 4275 &epipe->nexttoggle, &end); 4276 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4277 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4278 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4279 4280 exfer->ex_sqtdend = end; 4281 4282 /* also does usb_syncmem(sqh) */ 4283 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4284 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4285 callout_reset(&xfer->ux_callout, 4286 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4287 } 4288 ehci_add_intr_list(sc, exfer); 4289 xfer->ux_status = USBD_IN_PROGRESS; 4290 } else { 4291 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4292 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4293 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4294 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4295 } 4296 } 4297 4298 /************************/ 4299 Static int 4300 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4301 { 4302 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4303 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4304 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4305 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4306 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4307 int i, k, frames; 4308 u_int huba, dir; 4309 int err; 4310 4311 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4312 4313 start = NULL; 4314 sitd = NULL; 4315 4316 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", xfer, xfer->ux_length, 4317 xfer->ux_flags, 0); 4318 4319 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4320 KASSERT(xfer->ux_nframes != 0); 4321 KASSERT(exfer->ex_isdone); 4322 4323 exfer->ex_type = EX_FS_ISOC; 4324 /* 4325 * Step 1: Allocate and initialize sitds. 4326 */ 4327 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4328 if (i > 16 || i == 0) { 4329 /* Spec page 271 says intervals > 16 are invalid */ 4330 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4331 4332 return EINVAL; 4333 } 4334 4335 frames = xfer->ux_nframes; 4336 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4337 sitd = ehci_alloc_sitd(sc); 4338 if (sitd == NULL) { 4339 err = ENOMEM; 4340 goto fail; 4341 } 4342 4343 if (prev) 4344 prev->xfer_next = sitd; 4345 else 4346 start = sitd; 4347 4348 huba = dev->ud_myhsport->up_parent->ud_addr; 4349 4350 #if 0 4351 if (sc->sc_flags & EHCIF_FREESCALE) { 4352 // Set hub address to 0 if embedded TT is used. 4353 if (huba == sc->sc_addr) 4354 huba = 0; 4355 } 4356 #endif 4357 4358 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4359 dir = UE_GET_DIR(k) ? 1 : 0; 4360 sitd->sitd.sitd_endp = 4361 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4362 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4363 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4364 EHCI_SITD_SET_HUBA(huba) | 4365 EHCI_SITD_SET_DIR(dir)); 4366 4367 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4368 } /* End of frame */ 4369 4370 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4371 4372 stop = sitd; 4373 stop->xfer_next = NULL; 4374 exfer->ex_sitdstart = start; 4375 exfer->ex_sitdend = stop; 4376 4377 return 0; 4378 4379 fail: 4380 mutex_enter(&sc->sc_lock); 4381 ehci_soft_sitd_t *next; 4382 for (sitd = start; sitd; sitd = next) { 4383 next = sitd->xfer_next; 4384 ehci_free_sitd_locked(sc, sitd); 4385 } 4386 mutex_exit(&sc->sc_lock); 4387 4388 return err; 4389 } 4390 4391 Static void 4392 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4393 { 4394 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4395 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4396 4397 KASSERT(ex->ex_type == EX_FS_ISOC); 4398 4399 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4400 } 4401 4402 Static usbd_status 4403 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4404 { 4405 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4406 usbd_status err; 4407 4408 mutex_enter(&sc->sc_lock); 4409 err = usb_insert_transfer(xfer); 4410 mutex_exit(&sc->sc_lock); 4411 4412 if (err && err != USBD_IN_PROGRESS) 4413 return err; 4414 4415 return ehci_device_fs_isoc_start(xfer); 4416 } 4417 4418 Static usbd_status 4419 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4420 { 4421 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4422 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4423 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4424 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4425 ehci_soft_sitd_t *sitd; 4426 usb_dma_t *dma_buf; 4427 int i, j, k, frames; 4428 int offs, total_length; 4429 int frindex; 4430 u_int dir; 4431 4432 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4433 4434 sitd = NULL; 4435 total_length = 0; 4436 4437 /* 4438 * To allow continuous transfers, above we start all transfers 4439 * immediately. However, we're still going to get usbd_start_next call 4440 * this when another xfer completes. So, check if this is already 4441 * in progress or not 4442 */ 4443 4444 if (exfer->ex_isrunning) { 4445 return USBD_IN_PROGRESS; 4446 } 4447 4448 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4449 xfer, xfer->ux_length, xfer->ux_flags, 0); 4450 4451 if (sc->sc_dying) 4452 return USBD_IOERROR; 4453 4454 /* 4455 * To avoid complication, don't allow a request right now that'll span 4456 * the entire frame table. To within 4 frames, to allow some leeway 4457 * on either side of where the hc currently is. 4458 */ 4459 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4460 xfer->ux_nframes >= sc->sc_flsize - 4) { 4461 printf("ehci: isoc descriptor requested that spans the entire" 4462 "frametable, too many frames\n"); 4463 return USBD_INVAL; 4464 } 4465 4466 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4467 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4468 KASSERT(exfer->ex_isdone); 4469 #ifdef DIAGNOSTIC 4470 exfer->ex_isdone = false; 4471 #endif 4472 4473 /* 4474 * Step 1: Initialize sitds. 4475 */ 4476 4477 frames = xfer->ux_nframes; 4478 dma_buf = &xfer->ux_dmabuf; 4479 offs = 0; 4480 4481 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4482 i++, sitd = sitd->xfer_next) { 4483 KASSERT(sitd != NULL); 4484 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4485 4486 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4487 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4488 4489 /* Set page0 index and offset - TP and T-offset are set below */ 4490 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4491 4492 total_length += xfer->ux_frlengths[i]; 4493 offs += xfer->ux_frlengths[i]; 4494 4495 sitd->sitd.sitd_buffer[1] = 4496 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4497 4498 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4499 4500 #if 0 4501 if (sc->sc_flags & EHCIF_FREESCALE) { 4502 // Set hub address to 0 if embedded TT is used. 4503 if (huba == sc->sc_addr) 4504 huba = 0; 4505 } 4506 #endif 4507 4508 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4509 dir = UE_GET_DIR(k) ? 1 : 0; 4510 KASSERT(sitd->sitd.sitd_endp == htole32( 4511 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4512 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4513 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4514 EHCI_SITD_SET_HUBA(huba) | 4515 EHCI_SITD_SET_DIR(dir))); 4516 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4517 4518 uint8_t sa = 0; 4519 uint8_t sb = 0; 4520 u_int temp, tlen; 4521 4522 if (dir == 0) { /* OUT */ 4523 temp = 0; 4524 tlen = xfer->ux_frlengths[i]; 4525 if (tlen <= 188) { 4526 temp |= 1; /* T-count = 1, TP = ALL */ 4527 tlen = 1; 4528 } else { 4529 tlen += 187; 4530 tlen /= 188; 4531 temp |= tlen; /* T-count = [1..6] */ 4532 temp |= 8; /* TP = Begin */ 4533 } 4534 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4535 4536 tlen += sa; 4537 4538 if (tlen >= 8) { 4539 sb = 0; 4540 } else { 4541 sb = (1 << tlen); 4542 } 4543 4544 sa = (1 << sa); 4545 sa = (sb - sa) & 0x3F; 4546 sb = 0; 4547 } else { 4548 sb = (-(4 << sa)) & 0xFE; 4549 sa = (1 << sa) & 0x3F; 4550 sa = 0x01; 4551 sb = 0xfc; 4552 } 4553 4554 sitd->sitd.sitd_sched = htole32( 4555 EHCI_SITD_SET_SMASK(sa) | 4556 EHCI_SITD_SET_CMASK(sb) 4557 ); 4558 4559 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4560 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4561 } /* End of frame */ 4562 4563 sitd = exfer->ex_sitdend; 4564 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4565 4566 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4567 sizeof(sitd->sitd.sitd_trans), 4568 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4569 4570 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4571 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4572 4573 /* 4574 * Part 2: Transfer descriptors have now been set up, now they must 4575 * be scheduled into the periodic frame list. Erk. Not wanting to 4576 * complicate matters, transfer is denied if the transfer spans 4577 * more than the period frame list. 4578 */ 4579 4580 mutex_enter(&sc->sc_lock); 4581 4582 /* Start inserting frames */ 4583 if (epipe->isoc.cur_xfers > 0) { 4584 frindex = epipe->isoc.next_frame; 4585 } else { 4586 frindex = EOREAD4(sc, EHCI_FRINDEX); 4587 frindex = frindex >> 3; /* Erase microframe index */ 4588 frindex += 2; 4589 } 4590 4591 if (frindex >= sc->sc_flsize) 4592 frindex &= (sc->sc_flsize - 1); 4593 4594 /* Whats the frame interval? */ 4595 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4596 4597 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4598 j++, sitd = sitd->xfer_next) { 4599 KASSERT(sitd); 4600 4601 usb_syncmem(&sc->sc_fldma, 4602 sizeof(ehci_link_t) * frindex, 4603 sizeof(ehci_link_t), 4604 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4605 4606 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4607 if (sitd->sitd.sitd_next == 0) 4608 /* 4609 * FIXME: frindex table gets initialized to NULL 4610 * or EHCI_NULL? 4611 */ 4612 sitd->sitd.sitd_next = EHCI_NULL; 4613 4614 usb_syncmem(&sitd->dma, 4615 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4616 sizeof(ehci_sitd_t), 4617 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4618 4619 sc->sc_flist[frindex] = 4620 htole32(EHCI_LINK_SITD | sitd->physaddr); 4621 4622 usb_syncmem(&sc->sc_fldma, 4623 sizeof(ehci_link_t) * frindex, 4624 sizeof(ehci_link_t), 4625 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4626 4627 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4628 sc->sc_softsitds[frindex] = sitd; 4629 if (sitd->frame_list.next != NULL) 4630 sitd->frame_list.next->frame_list.prev = sitd; 4631 sitd->slot = frindex; 4632 sitd->frame_list.prev = NULL; 4633 4634 frindex += i; 4635 if (frindex >= sc->sc_flsize) 4636 frindex -= sc->sc_flsize; 4637 } 4638 4639 epipe->isoc.cur_xfers++; 4640 epipe->isoc.next_frame = frindex; 4641 4642 exfer->ex_isrunning = true; 4643 4644 ehci_add_intr_list(sc, exfer); 4645 xfer->ux_status = USBD_IN_PROGRESS; 4646 4647 mutex_exit(&sc->sc_lock); 4648 4649 if (sc->sc_bus.ub_usepolling) { 4650 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4651 ehci_waitintr(sc, xfer); 4652 } 4653 4654 return USBD_IN_PROGRESS; 4655 } 4656 4657 Static void 4658 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4659 { 4660 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4661 4662 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4663 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4664 } 4665 4666 Static void 4667 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4668 { 4669 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4670 4671 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4672 } 4673 4674 Static void 4675 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4676 { 4677 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4678 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4679 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4680 4681 KASSERT(mutex_owned(&sc->sc_lock)); 4682 4683 epipe->isoc.cur_xfers--; 4684 if (exfer->ex_isrunning) { 4685 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4686 exfer->ex_isrunning = false; 4687 } 4688 4689 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4690 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4691 } 4692 4693 4694 /************************/ 4695 4696 4697 Static int 4698 ehci_device_isoc_init(struct usbd_xfer *xfer) 4699 { 4700 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4701 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4702 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4703 ehci_soft_itd_t *itd, *prev, *start, *stop; 4704 int i, j, k; 4705 int frames, ufrperframe; 4706 int err; 4707 4708 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4709 4710 start = NULL; 4711 prev = NULL; 4712 itd = NULL; 4713 4714 KASSERT(xfer->ux_nframes != 0); 4715 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4716 KASSERT(exfer->ex_isdone); 4717 4718 exfer->ex_type = EX_ISOC; 4719 4720 /* 4721 * Step 1: Allocate and initialize itds, how many do we need? 4722 * One per transfer if interval >= 8 microframes, less if we use 4723 * multiple microframes per frame. 4724 */ 4725 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4726 if (i > 16 || i == 0) { 4727 /* Spec page 271 says intervals > 16 are invalid */ 4728 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4729 return USBD_INVAL; 4730 } 4731 4732 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4733 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4734 4735 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4736 itd = ehci_alloc_itd(sc); 4737 if (itd == NULL) { 4738 err = ENOMEM; 4739 goto fail; 4740 } 4741 4742 if (prev != NULL) { 4743 /* Maybe not as it's updated by the scheduling? */ 4744 prev->itd.itd_next = 4745 htole32(itd->physaddr | EHCI_LINK_ITD); 4746 4747 prev->xfer_next = itd; 4748 } else { 4749 start = itd; 4750 } 4751 4752 /* 4753 * Other special values 4754 */ 4755 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4756 itd->itd.itd_bufr[0] = htole32( 4757 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4758 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4759 4760 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4761 ? 1 : 0; 4762 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4763 itd->itd.itd_bufr[1] |= htole32( 4764 EHCI_ITD_SET_DIR(k) | 4765 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4766 4767 /* FIXME: handle invalid trans - should be done in openpipe */ 4768 itd->itd.itd_bufr[2] |= 4769 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4770 } /* End of frame */ 4771 4772 stop = itd; 4773 stop->xfer_next = NULL; 4774 4775 exfer->ex_itdstart = start; 4776 exfer->ex_itdend = stop; 4777 4778 return 0; 4779 fail: 4780 mutex_enter(&sc->sc_lock); 4781 ehci_soft_itd_t *next; 4782 for (itd = start; itd; itd = next) { 4783 next = itd->xfer_next; 4784 ehci_free_itd_locked(sc, itd); 4785 } 4786 mutex_exit(&sc->sc_lock); 4787 4788 return err; 4789 4790 } 4791 4792 Static void 4793 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4794 { 4795 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4796 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4797 4798 KASSERT(ex->ex_type == EX_ISOC); 4799 4800 ehci_free_itd_chain(sc, ex->ex_itdstart); 4801 } 4802 4803 Static usbd_status 4804 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4805 { 4806 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4807 usbd_status err; 4808 4809 mutex_enter(&sc->sc_lock); 4810 err = usb_insert_transfer(xfer); 4811 mutex_exit(&sc->sc_lock); 4812 if (err && err != USBD_IN_PROGRESS) 4813 return err; 4814 4815 return ehci_device_isoc_start(xfer); 4816 } 4817 4818 Static usbd_status 4819 ehci_device_isoc_start(struct usbd_xfer *xfer) 4820 { 4821 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4822 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4823 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4824 ehci_soft_itd_t *itd, *prev; 4825 usb_dma_t *dma_buf; 4826 int i, j; 4827 int frames, uframes, ufrperframe; 4828 int trans_count, offs, total_length; 4829 int frindex; 4830 4831 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4832 4833 prev = NULL; 4834 itd = NULL; 4835 trans_count = 0; 4836 total_length = 0; 4837 4838 /* 4839 * To allow continuous transfers, above we start all transfers 4840 * immediately. However, we're still going to get usbd_start_next call 4841 * this when another xfer completes. So, check if this is already 4842 * in progress or not 4843 */ 4844 4845 if (exfer->ex_isrunning) { 4846 return USBD_IN_PROGRESS; 4847 } 4848 4849 USBHIST_LOG(ehcidebug, "xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4850 4851 if (sc->sc_dying) 4852 return USBD_IOERROR; 4853 4854 /* 4855 * To avoid complication, don't allow a request right now that'll span 4856 * the entire frame table. To within 4 frames, to allow some leeway 4857 * on either side of where the hc currently is. 4858 */ 4859 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4860 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4861 USBHIST_LOG(ehcidebug, 4862 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4863 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4864 return USBD_INVAL; 4865 } 4866 4867 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4868 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4869 KASSERT(exfer->ex_isdone); 4870 #ifdef DIAGNOSTIC 4871 exfer->ex_isdone = false; 4872 #endif 4873 4874 /* 4875 * Step 1: Re-Initialize itds 4876 */ 4877 4878 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4879 if (i > 16 || i == 0) { 4880 /* Spec page 271 says intervals > 16 are invalid */ 4881 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4882 return USBD_INVAL; 4883 } 4884 4885 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4886 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4887 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4888 4889 if (frames == 0) { 4890 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4891 return USBD_INVAL; 4892 } 4893 4894 dma_buf = &xfer->ux_dmabuf; 4895 offs = 0; 4896 4897 itd = exfer->ex_itdstart; 4898 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4899 int froffs = offs; 4900 4901 if (prev != NULL) { 4902 prev->itd.itd_next = 4903 htole32(itd->physaddr | EHCI_LINK_ITD); 4904 usb_syncmem(&prev->dma, 4905 prev->offs + offsetof(ehci_itd_t, itd_next), 4906 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4907 prev->xfer_next = itd; 4908 } 4909 4910 /* 4911 * Step 1.5, initialize uframes 4912 */ 4913 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4914 /* Calculate which page in the list this starts in */ 4915 int addr = DMAADDR(dma_buf, froffs); 4916 addr = EHCI_PAGE_OFFSET(addr); 4917 addr += (offs - froffs); 4918 addr = EHCI_PAGE(addr); 4919 addr /= EHCI_PAGE_SIZE; 4920 4921 /* 4922 * This gets the initial offset into the first page, 4923 * looks how far further along the current uframe 4924 * offset is. Works out how many pages that is. 4925 */ 4926 4927 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4928 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4929 EHCI_ITD_SET_PG(addr) | 4930 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4931 4932 total_length += xfer->ux_frlengths[trans_count]; 4933 offs += xfer->ux_frlengths[trans_count]; 4934 trans_count++; 4935 4936 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4937 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4938 break; 4939 } 4940 } 4941 4942 /* 4943 * Step 1.75, set buffer pointers. To simplify matters, all 4944 * pointers are filled out for the next 7 hardware pages in 4945 * the dma block, so no need to worry what pages to cover 4946 * and what to not. 4947 */ 4948 4949 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4950 /* 4951 * Don't try to lookup a page that's past the end 4952 * of buffer 4953 */ 4954 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4955 if (page_offs >= dma_buf->udma_block->size) 4956 break; 4957 4958 uint64_t page = DMAADDR(dma_buf, page_offs); 4959 page = EHCI_PAGE(page); 4960 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4961 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4962 } 4963 /* 4964 * Other special values 4965 */ 4966 4967 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4968 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4969 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4970 4971 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4972 ? 1 : 0; 4973 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4974 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4975 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4976 4977 /* FIXME: handle invalid trans */ 4978 itd->itd.itd_bufr[2] |= 4979 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4980 4981 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4982 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4983 4984 prev = itd; 4985 } /* End of frame */ 4986 4987 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4988 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4989 4990 /* 4991 * Part 2: Transfer descriptors have now been set up, now they must 4992 * be scheduled into the period frame list. Erk. Not wanting to 4993 * complicate matters, transfer is denied if the transfer spans 4994 * more than the period frame list. 4995 */ 4996 4997 mutex_enter(&sc->sc_lock); 4998 4999 /* Start inserting frames */ 5000 if (epipe->isoc.cur_xfers > 0) { 5001 frindex = epipe->isoc.next_frame; 5002 } else { 5003 frindex = EOREAD4(sc, EHCI_FRINDEX); 5004 frindex = frindex >> 3; /* Erase microframe index */ 5005 frindex += 2; 5006 } 5007 5008 if (frindex >= sc->sc_flsize) 5009 frindex &= (sc->sc_flsize - 1); 5010 5011 /* What's the frame interval? */ 5012 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 5013 if (i / USB_UFRAMES_PER_FRAME == 0) 5014 i = 1; 5015 else 5016 i /= USB_UFRAMES_PER_FRAME; 5017 5018 itd = exfer->ex_itdstart; 5019 for (j = 0; j < frames; j++) { 5020 KASSERTMSG(itd != NULL, "frame %d\n", j); 5021 5022 usb_syncmem(&sc->sc_fldma, 5023 sizeof(ehci_link_t) * frindex, 5024 sizeof(ehci_link_t), 5025 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5026 5027 itd->itd.itd_next = sc->sc_flist[frindex]; 5028 if (itd->itd.itd_next == 0) 5029 /* 5030 * FIXME: frindex table gets initialized to NULL 5031 * or EHCI_NULL? 5032 */ 5033 itd->itd.itd_next = EHCI_NULL; 5034 5035 usb_syncmem(&itd->dma, 5036 itd->offs + offsetof(ehci_itd_t, itd_next), 5037 sizeof(itd->itd.itd_next), 5038 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5039 5040 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 5041 5042 usb_syncmem(&sc->sc_fldma, 5043 sizeof(ehci_link_t) * frindex, 5044 sizeof(ehci_link_t), 5045 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5046 5047 itd->frame_list.next = sc->sc_softitds[frindex]; 5048 sc->sc_softitds[frindex] = itd; 5049 if (itd->frame_list.next != NULL) 5050 itd->frame_list.next->frame_list.prev = itd; 5051 itd->slot = frindex; 5052 itd->frame_list.prev = NULL; 5053 5054 frindex += i; 5055 if (frindex >= sc->sc_flsize) 5056 frindex -= sc->sc_flsize; 5057 5058 itd = itd->xfer_next; 5059 } 5060 5061 epipe->isoc.cur_xfers++; 5062 epipe->isoc.next_frame = frindex; 5063 5064 exfer->ex_isrunning = true; 5065 5066 ehci_add_intr_list(sc, exfer); 5067 xfer->ux_status = USBD_IN_PROGRESS; 5068 5069 mutex_exit(&sc->sc_lock); 5070 5071 if (sc->sc_bus.ub_usepolling) { 5072 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 5073 ehci_waitintr(sc, xfer); 5074 } 5075 5076 return USBD_IN_PROGRESS; 5077 } 5078 5079 Static void 5080 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5081 { 5082 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5083 5084 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 5085 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5086 } 5087 5088 Static void 5089 ehci_device_isoc_close(struct usbd_pipe *pipe) 5090 { 5091 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5092 5093 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 5094 } 5095 5096 Static void 5097 ehci_device_isoc_done(struct usbd_xfer *xfer) 5098 { 5099 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5100 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5101 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5102 5103 KASSERT(mutex_owned(&sc->sc_lock)); 5104 5105 epipe->isoc.cur_xfers--; 5106 if (exfer->ex_isrunning) { 5107 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5108 exfer->ex_isrunning = false; 5109 } 5110 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5111 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5112 } 5113
Indexes created Thu Oct 02 01:09:59 GMT 2025