ehci.c revision 1.234.2.86
1 /* $NetBSD: ehci.c,v 1.234.2.86 2016/02/07 13:58:19 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.86 2016/02/07 13:58:19 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 /* Control pipe */ 136 struct { 137 usb_dma_t reqdma; 138 } ctrl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Iso pipe */ 144 struct { 145 u_int next_frame; 146 u_int cur_xfers; 147 } isoc; 148 }; 149 }; 150 151 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 152 153 Static usbd_status ehci_open(struct usbd_pipe *); 154 Static void ehci_poll(struct usbd_bus *); 155 Static void ehci_softintr(void *); 156 Static int ehci_intr1(ehci_softc_t *); 157 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 158 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 159 ex_completeq_t *); 160 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 161 ex_completeq_t *); 162 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 165 Static void ehci_timeout(void *); 166 Static void ehci_timeout_task(void *); 167 Static void ehci_intrlist_timeout(void *); 168 Static void ehci_doorbell(void *); 169 Static void ehci_pcd(void *); 170 171 Static struct usbd_xfer * 172 ehci_allocx(struct usbd_bus *, unsigned int); 173 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 174 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 180 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 181 Static void ehci_root_intr_abort(struct usbd_xfer *); 182 Static void ehci_root_intr_close(struct usbd_pipe *); 183 Static void ehci_root_intr_done(struct usbd_xfer *); 184 185 Static int ehci_device_ctrl_init(struct usbd_xfer *); 186 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 187 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 188 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 189 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 190 Static void ehci_device_ctrl_close(struct usbd_pipe *); 191 Static void ehci_device_ctrl_done(struct usbd_xfer *); 192 193 Static int ehci_device_bulk_init(struct usbd_xfer *); 194 Static void ehci_device_bulk_fini(struct usbd_xfer *); 195 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 196 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 197 Static void ehci_device_bulk_abort(struct usbd_xfer *); 198 Static void ehci_device_bulk_close(struct usbd_pipe *); 199 Static void ehci_device_bulk_done(struct usbd_xfer *); 200 201 Static int ehci_device_intr_init(struct usbd_xfer *); 202 Static void ehci_device_intr_fini(struct usbd_xfer *); 203 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 204 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 205 Static void ehci_device_intr_abort(struct usbd_xfer *); 206 Static void ehci_device_intr_close(struct usbd_pipe *); 207 Static void ehci_device_intr_done(struct usbd_xfer *); 208 209 Static int ehci_device_isoc_init(struct usbd_xfer *); 210 Static void ehci_device_isoc_fini(struct usbd_xfer *); 211 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 212 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 213 Static void ehci_device_isoc_abort(struct usbd_xfer *); 214 Static void ehci_device_isoc_close(struct usbd_pipe *); 215 Static void ehci_device_isoc_done(struct usbd_xfer *); 216 217 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 218 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 219 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 220 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 223 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 224 225 Static void ehci_device_clear_toggle(struct usbd_pipe *); 226 Static void ehci_noop(struct usbd_pipe *); 227 228 Static void ehci_disown(ehci_softc_t *, int, int); 229 230 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 231 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 232 233 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 234 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 235 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 236 int, int, ehci_soft_qtd_t **, ehci_soft_qtd_t **); 237 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 238 239 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 240 int, int, int *, ehci_soft_qtd_t **); 241 242 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 243 Static ehci_soft_sitd_t * 244 ehci_alloc_sitd(ehci_softc_t *); 245 246 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 247 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 248 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 249 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 250 251 static inline void 252 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 253 { 254 255 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 256 } 257 258 static inline void 259 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 260 { 261 262 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 263 } 264 265 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 266 267 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 268 int); 269 270 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 271 ehci_soft_qh_t *); 272 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 273 ehci_soft_qh_t *); 274 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 275 Static void ehci_sync_hc(ehci_softc_t *); 276 277 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 278 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 279 280 #ifdef EHCI_DEBUG 281 Static ehci_softc_t *theehci; 282 void ehci_dump(void); 283 #endif 284 285 #ifdef EHCI_DEBUG 286 Static void ehci_dump_regs(ehci_softc_t *); 287 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 288 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 289 Static void ehci_dump_qtd(ehci_qtd_t *); 290 Static void ehci_dump_sqh(ehci_soft_qh_t *); 291 Static void ehci_dump_sitd(struct ehci_soft_itd *); 292 Static void ehci_dump_itds(ehci_soft_itd_t *); 293 Static void ehci_dump_itd(struct ehci_soft_itd *); 294 Static void ehci_dump_exfer(struct ehci_xfer *); 295 #endif 296 297 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 298 299 static inline void 300 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 301 { 302 303 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 304 } 305 306 static inline void 307 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 308 { 309 310 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 311 } 312 313 Static const struct usbd_bus_methods ehci_bus_methods = { 314 .ubm_open = ehci_open, 315 .ubm_softint = ehci_softintr, 316 .ubm_dopoll = ehci_poll, 317 .ubm_allocx = ehci_allocx, 318 .ubm_freex = ehci_freex, 319 .ubm_getlock = ehci_get_lock, 320 .ubm_rhctrl = ehci_roothub_ctrl, 321 }; 322 323 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 324 .upm_transfer = ehci_root_intr_transfer, 325 .upm_start = ehci_root_intr_start, 326 .upm_abort = ehci_root_intr_abort, 327 .upm_close = ehci_root_intr_close, 328 .upm_cleartoggle = ehci_noop, 329 .upm_done = ehci_root_intr_done, 330 }; 331 332 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 333 .upm_init = ehci_device_ctrl_init, 334 .upm_fini = ehci_device_ctrl_fini, 335 .upm_transfer = ehci_device_ctrl_transfer, 336 .upm_start = ehci_device_ctrl_start, 337 .upm_abort = ehci_device_ctrl_abort, 338 .upm_close = ehci_device_ctrl_close, 339 .upm_cleartoggle = ehci_noop, 340 .upm_done = ehci_device_ctrl_done, 341 }; 342 343 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 344 .upm_init = ehci_device_intr_init, 345 .upm_fini = ehci_device_intr_fini, 346 .upm_transfer = ehci_device_intr_transfer, 347 .upm_start = ehci_device_intr_start, 348 .upm_abort = ehci_device_intr_abort, 349 .upm_close = ehci_device_intr_close, 350 .upm_cleartoggle = ehci_device_clear_toggle, 351 .upm_done = ehci_device_intr_done, 352 }; 353 354 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 355 .upm_init = ehci_device_bulk_init, 356 .upm_fini = ehci_device_bulk_fini, 357 .upm_transfer = ehci_device_bulk_transfer, 358 .upm_start = ehci_device_bulk_start, 359 .upm_abort = ehci_device_bulk_abort, 360 .upm_close = ehci_device_bulk_close, 361 .upm_cleartoggle = ehci_device_clear_toggle, 362 .upm_done = ehci_device_bulk_done, 363 }; 364 365 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 366 .upm_init = ehci_device_isoc_init, 367 .upm_fini = ehci_device_isoc_fini, 368 .upm_transfer = ehci_device_isoc_transfer, 369 .upm_start = ehci_device_isoc_start, 370 .upm_abort = ehci_device_isoc_abort, 371 .upm_close = ehci_device_isoc_close, 372 .upm_cleartoggle = ehci_noop, 373 .upm_done = ehci_device_isoc_done, 374 }; 375 376 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 377 .upm_init = ehci_device_fs_isoc_init, 378 .upm_fini = ehci_device_fs_isoc_fini, 379 .upm_transfer = ehci_device_fs_isoc_transfer, 380 .upm_start = ehci_device_fs_isoc_start, 381 .upm_abort = ehci_device_fs_isoc_abort, 382 .upm_close = ehci_device_fs_isoc_close, 383 .upm_cleartoggle = ehci_noop, 384 .upm_done = ehci_device_fs_isoc_done, 385 }; 386 387 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 388 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 389 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 390 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 391 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 392 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 393 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 394 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 395 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 396 }; 397 398 int 399 ehci_init(ehci_softc_t *sc) 400 { 401 uint32_t vers, sparams, cparams, hcr; 402 u_int i; 403 usbd_status err; 404 ehci_soft_qh_t *sqh; 405 u_int ncomp; 406 407 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 408 #ifdef EHCI_DEBUG 409 theehci = sc; 410 #endif 411 412 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 413 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 414 cv_init(&sc->sc_softwake_cv, "ehciab"); 415 cv_init(&sc->sc_doorbell, "ehcidi"); 416 417 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 418 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 419 420 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 421 ehci_doorbell, sc); 422 KASSERT(sc->sc_doorbell_si != NULL); 423 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 424 ehci_pcd, sc); 425 KASSERT(sc->sc_pcd_si != NULL); 426 427 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 428 429 vers = EREAD2(sc, EHCI_HCIVERSION); 430 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 431 vers >> 8, vers & 0xff); 432 433 sparams = EREAD4(sc, EHCI_HCSPARAMS); 434 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 435 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 436 ncomp = EHCI_HCS_N_CC(sparams); 437 if (ncomp != sc->sc_ncomp) { 438 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 439 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 440 #if NOHCI == 0 || NUHCI == 0 441 aprint_error("%s: ohci or uhci probably not configured\n", 442 device_xname(sc->sc_dev)); 443 #endif 444 if (ncomp < sc->sc_ncomp) 445 sc->sc_ncomp = ncomp; 446 } 447 if (sc->sc_ncomp > 0) { 448 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 449 aprint_normal("%s: companion controller%s, %d port%s each:", 450 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 451 EHCI_HCS_N_PCC(sparams), 452 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 453 for (i = 0; i < sc->sc_ncomp; i++) 454 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 455 aprint_normal("\n"); 456 } 457 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 458 cparams = EREAD4(sc, EHCI_HCCPARAMS); 459 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 460 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 461 462 if (EHCI_HCC_64BIT(cparams)) { 463 /* MUST clear segment register if 64 bit capable. */ 464 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 465 } 466 467 sc->sc_bus.ub_revision = USBREV_2_0; 468 sc->sc_bus.ub_usedma = true; 469 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 470 471 /* Reset the controller */ 472 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 473 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 474 usb_delay_ms(&sc->sc_bus, 1); 475 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 476 for (i = 0; i < 100; i++) { 477 usb_delay_ms(&sc->sc_bus, 1); 478 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 479 if (!hcr) 480 break; 481 } 482 if (hcr) { 483 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 484 return EIO; 485 } 486 if (sc->sc_vendor_init) 487 sc->sc_vendor_init(sc); 488 489 /* XXX need proper intr scheduling */ 490 sc->sc_rand = 96; 491 492 /* frame list size at default, read back what we got and use that */ 493 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 494 case 0: sc->sc_flsize = 1024; break; 495 case 1: sc->sc_flsize = 512; break; 496 case 2: sc->sc_flsize = 256; break; 497 case 3: return EIO; 498 } 499 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 500 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 501 if (err) 502 return err; 503 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 504 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 505 506 for (i = 0; i < sc->sc_flsize; i++) { 507 sc->sc_flist[i] = EHCI_NULL; 508 } 509 510 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 511 512 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 513 KM_SLEEP); 514 if (sc->sc_softitds == NULL) 515 return ENOMEM; 516 LIST_INIT(&sc->sc_freeitds); 517 LIST_INIT(&sc->sc_freesitds); 518 TAILQ_INIT(&sc->sc_intrhead); 519 520 /* Set up the bus struct. */ 521 sc->sc_bus.ub_methods = &ehci_bus_methods; 522 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 523 524 sc->sc_eintrs = EHCI_NORMAL_INTRS; 525 526 /* 527 * Allocate the interrupt dummy QHs. These are arranged to give poll 528 * intervals that are powers of 2 times 1ms. 529 */ 530 for (i = 0; i < EHCI_INTRQHS; i++) { 531 sqh = ehci_alloc_sqh(sc); 532 if (sqh == NULL) { 533 err = ENOMEM; 534 goto bad1; 535 } 536 sc->sc_islots[i].sqh = sqh; 537 } 538 for (i = 0; i < EHCI_INTRQHS; i++) { 539 sqh = sc->sc_islots[i].sqh; 540 if (i == 0) { 541 /* The last (1ms) QH terminates. */ 542 sqh->qh.qh_link = EHCI_NULL; 543 sqh->next = NULL; 544 } else { 545 /* Otherwise the next QH has half the poll interval */ 546 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 547 sqh->qh.qh_link = htole32(sqh->next->physaddr | 548 EHCI_LINK_QH); 549 } 550 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 551 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 552 sqh->qh.qh_curqtd = EHCI_NULL; 553 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 554 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 555 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 556 sqh->sqtd = NULL; 557 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 559 } 560 /* Point the frame list at the last level (128ms). */ 561 for (i = 0; i < sc->sc_flsize; i++) { 562 int j; 563 564 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 565 revbits[i & (EHCI_MAX_POLLRATE-1)]; 566 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 567 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 568 i)].sqh->physaddr); 569 } 570 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 571 BUS_DMASYNC_PREWRITE); 572 573 /* Allocate dummy QH that starts the async list. */ 574 sqh = ehci_alloc_sqh(sc); 575 if (sqh == NULL) { 576 err = ENOMEM; 577 goto bad1; 578 } 579 /* Fill the QH */ 580 sqh->qh.qh_endp = 581 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 582 sqh->qh.qh_link = 583 htole32(sqh->physaddr | EHCI_LINK_QH); 584 sqh->qh.qh_curqtd = EHCI_NULL; 585 sqh->next = NULL; 586 /* Fill the overlay qTD */ 587 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 588 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 589 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 590 sqh->sqtd = NULL; 591 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 592 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 593 #ifdef EHCI_DEBUG 594 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 595 ehci_dump_sqh(sqh); 596 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 597 #endif 598 599 /* Point to async list */ 600 sc->sc_async_head = sqh; 601 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 602 603 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 604 605 /* Turn on controller */ 606 EOWRITE4(sc, EHCI_USBCMD, 607 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 608 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 609 EHCI_CMD_ASE | 610 EHCI_CMD_PSE | 611 EHCI_CMD_RS); 612 613 /* Take over port ownership */ 614 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 615 616 for (i = 0; i < 100; i++) { 617 usb_delay_ms(&sc->sc_bus, 1); 618 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 619 if (!hcr) 620 break; 621 } 622 if (hcr) { 623 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 624 return EIO; 625 } 626 627 /* Enable interrupts */ 628 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 629 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 630 631 return 0; 632 633 #if 0 634 bad2: 635 ehci_free_sqh(sc, sc->sc_async_head); 636 #endif 637 bad1: 638 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 639 return err; 640 } 641 642 int 643 ehci_intr(void *v) 644 { 645 ehci_softc_t *sc = v; 646 int ret = 0; 647 648 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 649 650 if (sc == NULL) 651 return 0; 652 653 mutex_spin_enter(&sc->sc_intr_lock); 654 655 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 656 goto done; 657 658 /* If we get an interrupt while polling, then just ignore it. */ 659 if (sc->sc_bus.ub_usepolling) { 660 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 661 662 if (intrs) 663 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 664 USBHIST_LOGN(ehcidebug, 16, 665 "ignored interrupt while polling", 0, 0, 0, 0); 666 goto done; 667 } 668 669 ret = ehci_intr1(sc); 670 671 done: 672 mutex_spin_exit(&sc->sc_intr_lock); 673 return ret; 674 } 675 676 Static int 677 ehci_intr1(ehci_softc_t *sc) 678 { 679 uint32_t intrs, eintrs; 680 681 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 682 683 /* In case the interrupt occurs before initialization has completed. */ 684 if (sc == NULL) { 685 #ifdef DIAGNOSTIC 686 printf("ehci_intr1: sc == NULL\n"); 687 #endif 688 return 0; 689 } 690 691 KASSERT(mutex_owned(&sc->sc_intr_lock)); 692 693 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 694 if (!intrs) 695 return 0; 696 697 eintrs = intrs & sc->sc_eintrs; 698 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 699 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 700 if (!eintrs) 701 return 0; 702 703 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 704 if (eintrs & EHCI_STS_IAA) { 705 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 706 kpreempt_disable(); 707 KASSERT(sc->sc_doorbell_si != NULL); 708 softint_schedule(sc->sc_doorbell_si); 709 kpreempt_enable(); 710 eintrs &= ~EHCI_STS_IAA; 711 } 712 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 713 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 714 eintrs & EHCI_STS_INT ? 1 : 0, 715 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 716 usb_schedsoftintr(&sc->sc_bus); 717 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 718 } 719 if (eintrs & EHCI_STS_HSE) { 720 printf("%s: unrecoverable error, controller halted\n", 721 device_xname(sc->sc_dev)); 722 /* XXX what else */ 723 } 724 if (eintrs & EHCI_STS_PCD) { 725 kpreempt_disable(); 726 KASSERT(sc->sc_pcd_si != NULL); 727 softint_schedule(sc->sc_pcd_si); 728 kpreempt_enable(); 729 eintrs &= ~EHCI_STS_PCD; 730 } 731 732 if (eintrs != 0) { 733 /* Block unprocessed interrupts. */ 734 sc->sc_eintrs &= ~eintrs; 735 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 736 printf("%s: blocking intrs 0x%x\n", 737 device_xname(sc->sc_dev), eintrs); 738 } 739 740 return 1; 741 } 742 743 Static void 744 ehci_doorbell(void *addr) 745 { 746 ehci_softc_t *sc = addr; 747 748 mutex_enter(&sc->sc_lock); 749 cv_broadcast(&sc->sc_doorbell); 750 mutex_exit(&sc->sc_lock); 751 } 752 753 Static void 754 ehci_pcd(void *addr) 755 { 756 ehci_softc_t *sc = addr; 757 struct usbd_xfer *xfer; 758 u_char *p; 759 int i, m; 760 761 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 762 763 mutex_enter(&sc->sc_lock); 764 xfer = sc->sc_intrxfer; 765 766 if (xfer == NULL) { 767 /* Just ignore the change. */ 768 goto done; 769 } 770 771 p = xfer->ux_buf; 772 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 773 memset(p, 0, xfer->ux_length); 774 for (i = 1; i <= m; i++) { 775 /* Pick out CHANGE bits from the status reg. */ 776 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 777 p[i/8] |= 1 << (i%8); 778 if (i % 8 == 7) 779 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 780 p[i/8], 0, 0); 781 } 782 xfer->ux_actlen = xfer->ux_length; 783 xfer->ux_status = USBD_NORMAL_COMPLETION; 784 785 usb_transfer_complete(xfer); 786 787 done: 788 mutex_exit(&sc->sc_lock); 789 } 790 791 Static void 792 ehci_softintr(void *v) 793 { 794 struct usbd_bus *bus = v; 795 ehci_softc_t *sc = EHCI_BUS2SC(bus); 796 struct ehci_xfer *ex, *nextex; 797 798 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 799 800 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 801 802 ex_completeq_t cq; 803 TAILQ_INIT(&cq); 804 805 /* 806 * The only explanation I can think of for why EHCI is as brain dead 807 * as UHCI interrupt-wise is that Intel was involved in both. 808 * An interrupt just tells us that something is done, we have no 809 * clue what, so we need to scan through all active transfers. :-( 810 */ 811 812 /* 813 * ehci_idone will remove transfer from sc->sc_intrhead if it's 814 * complete and add to our cq list 815 * */ 816 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 817 switch (ex->ex_type) { 818 case EX_CTRL: 819 case EX_BULK: 820 case EX_INTR: 821 ehci_check_qh_intr(sc, ex, &cq); 822 break; 823 case EX_ISOC: 824 ehci_check_itd_intr(sc, ex, &cq); 825 break; 826 case EX_FS_ISOC: 827 ehci_check_sitd_intr(sc, ex, &cq); 828 break; 829 default: 830 KASSERT(false); 831 } 832 833 } 834 835 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 836 /* 837 * XXX transfer_complete memcpys out transfer data (for in 838 * endpoints) during this call, before methods->done is called. 839 * A dma sync required beforehand. 840 */ 841 usb_transfer_complete(&ex->ex_xfer); 842 } 843 844 /* Schedule a callout to catch any dropped transactions. */ 845 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 846 !TAILQ_EMPTY(&sc->sc_intrhead)) 847 callout_reset(&sc->sc_tmo_intrlist, 848 hz, ehci_intrlist_timeout, sc); 849 850 if (sc->sc_softwake) { 851 sc->sc_softwake = 0; 852 cv_broadcast(&sc->sc_softwake_cv); 853 } 854 } 855 856 Static void 857 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 858 { 859 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 860 uint32_t status; 861 862 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 863 864 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 865 866 if (ex->ex_type == EX_CTRL) { 867 fsqtd = ex->ex_setup; 868 lsqtd = ex->ex_status; 869 } else { 870 fsqtd = ex->ex_sqtdstart; 871 lsqtd = ex->ex_sqtdend; 872 } 873 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 874 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 875 876 /* 877 * If the last TD is still active we need to check whether there 878 * is an error somewhere in the middle, or whether there was a 879 * short packet (SPD and not ACTIVE). 880 */ 881 usb_syncmem(&lsqtd->dma, 882 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 883 sizeof(lsqtd->qtd.qtd_status), 884 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 885 status = le32toh(lsqtd->qtd.qtd_status); 886 usb_syncmem(&lsqtd->dma, 887 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 888 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 889 if (status & EHCI_QTD_ACTIVE) { 890 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 891 892 /* last qTD has already been checked */ 893 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 894 usb_syncmem(&sqtd->dma, 895 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 896 sizeof(sqtd->qtd.qtd_status), 897 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 898 status = le32toh(sqtd->qtd.qtd_status); 899 usb_syncmem(&sqtd->dma, 900 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 901 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 902 /* If there's an active QTD the xfer isn't done. */ 903 if (status & EHCI_QTD_ACTIVE) 904 break; 905 /* Any kind of error makes the xfer done. */ 906 if (status & EHCI_QTD_HALTED) 907 goto done; 908 /* Handle short packets */ 909 if (EHCI_QTD_GET_BYTES(status) != 0) { 910 /* 911 * If we get here for a control transfer then 912 * we need to let the hardware complete the 913 * status phase. That is, we're not done 914 * quite yet. 915 * 916 * Otherwise, we're done. 917 */ 918 if (ex->ex_type == EX_CTRL) { 919 break; 920 } 921 goto done; 922 } 923 } 924 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 925 ex, ex->ex_sqtdstart, 0, 0); 926 #ifdef EHCI_DEBUG 927 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 928 0, 0); 929 ehci_dump_sqtds(ex->ex_sqtdstart); 930 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 931 0); 932 #endif 933 return; 934 } 935 done: 936 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 937 callout_stop(&ex->ex_xfer.ux_callout); 938 ehci_idone(ex, cq); 939 } 940 941 Static void 942 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 943 { 944 ehci_soft_itd_t *itd; 945 int i; 946 947 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 948 949 KASSERT(mutex_owned(&sc->sc_lock)); 950 951 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 952 return; 953 954 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 955 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 956 957 itd = ex->ex_itdend; 958 959 /* 960 * check no active transfers in last itd, meaning we're finished 961 */ 962 963 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 964 sizeof(itd->itd.itd_ctl), 965 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 966 967 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 968 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 969 break; 970 } 971 972 if (i == EHCI_ITD_NUFRAMES) { 973 goto done; /* All 8 descriptors inactive, it's done */ 974 } 975 976 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 977 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 978 979 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 980 ex->ex_itdstart, 0, 0); 981 return; 982 done: 983 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 984 callout_stop(&ex->ex_xfer.ux_callout); 985 ehci_idone(ex, cq); 986 } 987 988 void 989 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 990 { 991 ehci_soft_sitd_t *sitd; 992 993 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 994 995 KASSERT(mutex_owned(&sc->sc_lock)); 996 997 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 998 return; 999 1000 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1001 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1002 1003 sitd = ex->ex_sitdend; 1004 1005 /* 1006 * check no active transfers in last sitd, meaning we're finished 1007 */ 1008 1009 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1010 sizeof(sitd->sitd.sitd_trans), 1011 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1012 1013 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1014 1015 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1016 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1017 1018 if (active) 1019 return; 1020 1021 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1022 callout_stop(&(ex->ex_xfer.ux_callout)); 1023 ehci_idone(ex, cq); 1024 } 1025 1026 1027 Static void 1028 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1029 { 1030 struct usbd_xfer *xfer = &ex->ex_xfer; 1031 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1032 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1033 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1034 uint32_t status = 0, nstatus = 0; 1035 int actlen = 0; 1036 1037 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1038 1039 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1040 1041 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1042 1043 if (xfer->ux_status == USBD_CANCELLED || 1044 xfer->ux_status == USBD_TIMEOUT) { 1045 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1046 return; 1047 } 1048 1049 #ifdef DIAGNOSTIC 1050 #ifdef EHCI_DEBUG 1051 if (ex->ex_isdone) { 1052 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1053 ehci_dump_exfer(ex); 1054 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1055 } 1056 #endif 1057 KASSERT(!ex->ex_isdone); 1058 ex->ex_isdone = true; 1059 #endif 1060 1061 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1062 1063 /* The transfer is done, compute actual length and status. */ 1064 if (ex->ex_type == EX_ISOC) { 1065 /* HS isoc transfer */ 1066 1067 struct ehci_soft_itd *itd; 1068 int i, nframes, len, uframes; 1069 1070 nframes = 0; 1071 1072 #ifdef EHCI_DEBUG 1073 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1074 ehci_dump_itds(ex->ex_itdstart); 1075 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1076 #endif 1077 1078 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1079 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1080 1081 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1082 usb_syncmem(&itd->dma, 1083 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1084 sizeof(itd->itd.itd_ctl), 1085 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1086 1087 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1088 /* 1089 * XXX - driver didn't fill in the frame full 1090 * of uframes. This leads to scheduling 1091 * inefficiencies, but working around 1092 * this doubles complexity of tracking 1093 * an xfer. 1094 */ 1095 if (nframes >= xfer->ux_nframes) 1096 break; 1097 1098 status = le32toh(itd->itd.itd_ctl[i]); 1099 len = EHCI_ITD_GET_LEN(status); 1100 if (EHCI_ITD_GET_STATUS(status) != 0) 1101 len = 0; /*No valid data on error*/ 1102 1103 xfer->ux_frlengths[nframes++] = len; 1104 actlen += len; 1105 } 1106 usb_syncmem(&itd->dma, 1107 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1108 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1109 1110 if (nframes >= xfer->ux_nframes) 1111 break; 1112 } 1113 1114 xfer->ux_actlen = actlen; 1115 xfer->ux_status = USBD_NORMAL_COMPLETION; 1116 goto end; 1117 } else if (ex->ex_type == EX_FS_ISOC) { 1118 /* FS isoc transfer */ 1119 struct ehci_soft_sitd *sitd; 1120 int nframes, len; 1121 1122 nframes = 0; 1123 1124 for (sitd = ex->ex_sitdstart; sitd != NULL; 1125 sitd = sitd->xfer_next) { 1126 usb_syncmem(&sitd->dma, 1127 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1128 sizeof(sitd->sitd.sitd_trans), 1129 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1130 1131 /* 1132 * XXX - driver didn't fill in the frame full 1133 * of uframes. This leads to scheduling 1134 * inefficiencies, but working around 1135 * this doubles complexity of tracking 1136 * an xfer. 1137 */ 1138 if (nframes >= xfer->ux_nframes) 1139 break; 1140 1141 status = le32toh(sitd->sitd.sitd_trans); 1142 usb_syncmem(&sitd->dma, 1143 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1144 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1145 1146 len = EHCI_SITD_GET_LEN(status); 1147 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1148 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1149 /* No valid data on error */ 1150 len = xfer->ux_frlengths[nframes]; 1151 } 1152 1153 /* 1154 * frlengths[i]: # of bytes to send 1155 * len: # of bytes host didn't send 1156 */ 1157 xfer->ux_frlengths[nframes] -= len; 1158 /* frlengths[i]: # of bytes host sent */ 1159 actlen += xfer->ux_frlengths[nframes++]; 1160 1161 if (nframes >= xfer->ux_nframes) 1162 break; 1163 } 1164 1165 xfer->ux_actlen = actlen; 1166 xfer->ux_status = USBD_NORMAL_COMPLETION; 1167 goto end; 1168 } 1169 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1170 ex->ex_type == EX_BULK); 1171 1172 /* Continue processing xfers using queue heads */ 1173 if (ex->ex_type == EX_CTRL) { 1174 fsqtd = ex->ex_setup; 1175 lsqtd = ex->ex_status; 1176 } else { 1177 fsqtd = ex->ex_sqtdstart; 1178 lsqtd = ex->ex_sqtdend; 1179 } 1180 #ifdef EHCI_DEBUG 1181 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1182 ehci_dump_sqtds(fsqtd); 1183 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1184 #endif 1185 1186 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1187 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1188 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1189 nstatus = le32toh(sqtd->qtd.qtd_status); 1190 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1191 BUS_DMASYNC_PREREAD); 1192 if (nstatus & EHCI_QTD_ACTIVE) 1193 break; 1194 1195 status = nstatus; 1196 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1197 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1198 } 1199 1200 /* 1201 * If there are left over TDs we need to update the toggle. 1202 * The default pipe doesn't need it since control transfers 1203 * start the toggle at 0 every time. 1204 * For a short transfer we need to update the toggle for the missing 1205 * packets within the qTD. 1206 */ 1207 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1208 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1209 USBHIST_LOG(ehcidebug, 1210 "toggle update status=0x%08x nstatus=0x%08x", 1211 status, nstatus, 0, 0); 1212 #if 0 1213 ehci_dump_sqh(epipe->sqh); 1214 ehci_dump_sqtds(ex->ex_sqtdstart); 1215 #endif 1216 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1217 } 1218 1219 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1220 actlen, status, 0); 1221 xfer->ux_actlen = actlen; 1222 if (status & EHCI_QTD_HALTED) { 1223 #ifdef EHCI_DEBUG 1224 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1225 xfer->ux_pipe->up_dev->ud_addr, 1226 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1227 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1228 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1229 0, 0); 1230 USBHIST_LOG(ehcidebug, 1231 "active =%d halted=%d buferr=%d babble=%d", 1232 status & EHCI_QTD_ACTIVE ? 1 : 0, 1233 status & EHCI_QTD_HALTED ? 1 : 0, 1234 status & EHCI_QTD_BUFERR ? 1 : 0, 1235 status & EHCI_QTD_BABBLE ? 1 : 0); 1236 1237 USBHIST_LOG(ehcidebug, 1238 "xacterr=%d missed=%d split =%d ping =%d", 1239 status & EHCI_QTD_XACTERR ? 1 : 0, 1240 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1241 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1242 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1243 1244 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1245 ehci_dump_sqh(epipe->sqh); 1246 ehci_dump_sqtds(ex->ex_sqtdstart); 1247 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1248 #endif 1249 /* low&full speed has an extra error flag */ 1250 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1251 EHCI_QH_SPEED_HIGH) 1252 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1253 else 1254 status &= EHCI_QTD_STATERRS; 1255 if (status == 0) /* no other errors means a stall */ { 1256 xfer->ux_status = USBD_STALLED; 1257 } else { 1258 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1259 } 1260 /* XXX need to reset TT on missed microframe */ 1261 if (status & EHCI_QTD_MISSEDMICRO) { 1262 printf("%s: missed microframe, TT reset not " 1263 "implemented, hub might be inoperational\n", 1264 device_xname(sc->sc_dev)); 1265 } 1266 } else { 1267 xfer->ux_status = USBD_NORMAL_COMPLETION; 1268 } 1269 1270 end: 1271 1272 ehci_del_intr_list(sc, ex); 1273 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1274 1275 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1276 } 1277 1278 /* 1279 * Wait here until controller claims to have an interrupt. 1280 * Then call ehci_intr and return. Use timeout to avoid waiting 1281 * too long. 1282 */ 1283 Static void 1284 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1285 { 1286 int timo; 1287 uint32_t intrs; 1288 1289 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1290 1291 xfer->ux_status = USBD_IN_PROGRESS; 1292 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1293 usb_delay_ms(&sc->sc_bus, 1); 1294 if (sc->sc_dying) 1295 break; 1296 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1297 sc->sc_eintrs; 1298 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1299 #ifdef EHCI_DEBUG 1300 if (ehcidebug >= 15) 1301 ehci_dump_regs(sc); 1302 #endif 1303 if (intrs) { 1304 mutex_spin_enter(&sc->sc_intr_lock); 1305 ehci_intr1(sc); 1306 mutex_spin_exit(&sc->sc_intr_lock); 1307 if (xfer->ux_status != USBD_IN_PROGRESS) 1308 return; 1309 } 1310 } 1311 1312 /* Timeout */ 1313 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1314 xfer->ux_status = USBD_TIMEOUT; 1315 mutex_enter(&sc->sc_lock); 1316 usb_transfer_complete(xfer); 1317 mutex_exit(&sc->sc_lock); 1318 } 1319 1320 Static void 1321 ehci_poll(struct usbd_bus *bus) 1322 { 1323 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1324 1325 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1326 1327 #ifdef EHCI_DEBUG 1328 static int last; 1329 int new; 1330 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1331 if (new != last) { 1332 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1333 last = new; 1334 } 1335 #endif 1336 1337 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1338 mutex_spin_enter(&sc->sc_intr_lock); 1339 ehci_intr1(sc); 1340 mutex_spin_exit(&sc->sc_intr_lock); 1341 } 1342 } 1343 1344 void 1345 ehci_childdet(device_t self, device_t child) 1346 { 1347 struct ehci_softc *sc = device_private(self); 1348 1349 KASSERT(sc->sc_child == child); 1350 sc->sc_child = NULL; 1351 } 1352 1353 int 1354 ehci_detach(struct ehci_softc *sc, int flags) 1355 { 1356 int rv = 0; 1357 1358 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1359 1360 if (sc->sc_child != NULL) 1361 rv = config_detach(sc->sc_child, flags); 1362 1363 if (rv != 0) 1364 return rv; 1365 1366 callout_halt(&sc->sc_tmo_intrlist, NULL); 1367 callout_destroy(&sc->sc_tmo_intrlist); 1368 1369 /* XXX free other data structures XXX */ 1370 if (sc->sc_softitds) 1371 kmem_free(sc->sc_softitds, 1372 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1373 cv_destroy(&sc->sc_doorbell); 1374 cv_destroy(&sc->sc_softwake_cv); 1375 1376 #if 0 1377 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1378 1379 softint_disestablish(sc->sc_doorbell_si); 1380 softint_disestablish(sc->sc_pcd_si); 1381 1382 mutex_destroy(&sc->sc_lock); 1383 mutex_destroy(&sc->sc_intr_lock); 1384 #endif 1385 1386 pool_cache_destroy(sc->sc_xferpool); 1387 1388 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1389 1390 return rv; 1391 } 1392 1393 1394 int 1395 ehci_activate(device_t self, enum devact act) 1396 { 1397 struct ehci_softc *sc = device_private(self); 1398 1399 switch (act) { 1400 case DVACT_DEACTIVATE: 1401 sc->sc_dying = 1; 1402 return 0; 1403 default: 1404 return EOPNOTSUPP; 1405 } 1406 } 1407 1408 /* 1409 * Handle suspend/resume. 1410 * 1411 * We need to switch to polling mode here, because this routine is 1412 * called from an interrupt context. This is all right since we 1413 * are almost suspended anyway. 1414 * 1415 * Note that this power handler isn't to be registered directly; the 1416 * bus glue needs to call out to it. 1417 */ 1418 bool 1419 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1420 { 1421 ehci_softc_t *sc = device_private(dv); 1422 int i; 1423 uint32_t cmd, hcr; 1424 1425 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1426 1427 mutex_spin_enter(&sc->sc_intr_lock); 1428 sc->sc_bus.ub_usepolling++; 1429 mutex_spin_exit(&sc->sc_intr_lock); 1430 1431 for (i = 1; i <= sc->sc_noport; i++) { 1432 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1433 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1434 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1435 } 1436 1437 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1438 1439 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1440 EOWRITE4(sc, EHCI_USBCMD, cmd); 1441 1442 for (i = 0; i < 100; i++) { 1443 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1444 if (hcr == 0) 1445 break; 1446 1447 usb_delay_ms(&sc->sc_bus, 1); 1448 } 1449 if (hcr != 0) 1450 printf("%s: reset timeout\n", device_xname(dv)); 1451 1452 cmd &= ~EHCI_CMD_RS; 1453 EOWRITE4(sc, EHCI_USBCMD, cmd); 1454 1455 for (i = 0; i < 100; i++) { 1456 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1457 if (hcr == EHCI_STS_HCH) 1458 break; 1459 1460 usb_delay_ms(&sc->sc_bus, 1); 1461 } 1462 if (hcr != EHCI_STS_HCH) 1463 printf("%s: config timeout\n", device_xname(dv)); 1464 1465 mutex_spin_enter(&sc->sc_intr_lock); 1466 sc->sc_bus.ub_usepolling--; 1467 mutex_spin_exit(&sc->sc_intr_lock); 1468 1469 return true; 1470 } 1471 1472 bool 1473 ehci_resume(device_t dv, const pmf_qual_t *qual) 1474 { 1475 ehci_softc_t *sc = device_private(dv); 1476 int i; 1477 uint32_t cmd, hcr; 1478 1479 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1480 1481 /* restore things in case the bios sucks */ 1482 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1483 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1484 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1485 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1486 1487 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1488 1489 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1490 1491 hcr = 0; 1492 for (i = 1; i <= sc->sc_noport; i++) { 1493 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1494 if ((cmd & EHCI_PS_PO) == 0 && 1495 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1496 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1497 hcr = 1; 1498 } 1499 } 1500 1501 if (hcr) { 1502 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1503 1504 for (i = 1; i <= sc->sc_noport; i++) { 1505 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1506 if ((cmd & EHCI_PS_PO) == 0 && 1507 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1508 EOWRITE4(sc, EHCI_PORTSC(i), 1509 cmd & ~EHCI_PS_FPR); 1510 } 1511 } 1512 1513 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1514 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1515 1516 for (i = 0; i < 100; i++) { 1517 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1518 if (hcr != EHCI_STS_HCH) 1519 break; 1520 1521 usb_delay_ms(&sc->sc_bus, 1); 1522 } 1523 if (hcr == EHCI_STS_HCH) 1524 printf("%s: config timeout\n", device_xname(dv)); 1525 1526 return true; 1527 } 1528 1529 /* 1530 * Shut down the controller when the system is going down. 1531 */ 1532 bool 1533 ehci_shutdown(device_t self, int flags) 1534 { 1535 ehci_softc_t *sc = device_private(self); 1536 1537 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1538 1539 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1540 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1541 return true; 1542 } 1543 1544 Static struct usbd_xfer * 1545 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1546 { 1547 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1548 struct usbd_xfer *xfer; 1549 1550 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1551 if (xfer != NULL) { 1552 memset(xfer, 0, sizeof(struct ehci_xfer)); 1553 #ifdef DIAGNOSTIC 1554 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1555 ex->ex_isdone = true; 1556 xfer->ux_state = XFER_BUSY; 1557 #endif 1558 } 1559 return xfer; 1560 } 1561 1562 Static void 1563 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1564 { 1565 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1566 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1567 1568 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1569 xfer->ux_state); 1570 KASSERT(ex->ex_isdone); 1571 1572 #ifdef DIAGNOSTIC 1573 xfer->ux_state = XFER_FREE; 1574 #endif 1575 1576 pool_cache_put(sc->sc_xferpool, xfer); 1577 } 1578 1579 Static void 1580 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1581 { 1582 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1583 1584 *lock = &sc->sc_lock; 1585 } 1586 1587 Static void 1588 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1589 { 1590 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1591 1592 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1593 1594 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1595 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1596 #ifdef EHCI_DEBUG 1597 if (ehcidebug) 1598 usbd_dump_pipe(pipe); 1599 #endif 1600 epipe->nexttoggle = 0; 1601 } 1602 1603 Static void 1604 ehci_noop(struct usbd_pipe *pipe) 1605 { 1606 } 1607 1608 #ifdef EHCI_DEBUG 1609 /* 1610 * Unused function - this is meant to be called from a kernel 1611 * debugger. 1612 */ 1613 void 1614 ehci_dump(void) 1615 { 1616 ehci_softc_t *sc = theehci; 1617 int i; 1618 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1619 EOREAD4(sc, EHCI_USBCMD), 1620 EOREAD4(sc, EHCI_USBSTS), 1621 EOREAD4(sc, EHCI_USBINTR)); 1622 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1623 EOREAD4(sc, EHCI_FRINDEX), 1624 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1625 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1626 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1627 for (i = 1; i <= sc->sc_noport; i++) 1628 printf("port %d status=0x%08x\n", i, 1629 EOREAD4(sc, EHCI_PORTSC(i))); 1630 } 1631 1632 Static void 1633 ehci_dump_regs(ehci_softc_t *sc) 1634 { 1635 int i; 1636 1637 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1638 1639 USBHIST_LOG(ehcidebug, 1640 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1641 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1642 EOREAD4(sc, EHCI_USBINTR), 0); 1643 USBHIST_LOG(ehcidebug, 1644 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1645 "async = 0x%08x", 1646 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1647 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1648 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1649 for (i = 1; i <= sc->sc_noport; i += 2) { 1650 if (i == sc->sc_noport) { 1651 USBHIST_LOG(ehcidebug, 1652 "port %d status = 0x%08x", i, 1653 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1654 } else { 1655 USBHIST_LOG(ehcidebug, 1656 "port %d status = 0x%08x port %d status = 0x%08x", 1657 i, EOREAD4(sc, EHCI_PORTSC(i)), 1658 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1659 } 1660 } 1661 } 1662 1663 #define ehci_dump_link(link, type) do { \ 1664 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1665 link, \ 1666 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1667 if (type) { \ 1668 USBHIST_LOG(ehcidebug, \ 1669 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1670 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1671 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1672 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1673 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1674 } \ 1675 } while(0) 1676 1677 Static void 1678 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1679 { 1680 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1681 int i; 1682 uint32_t stop = 0; 1683 1684 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1685 ehci_dump_sqtd(sqtd); 1686 usb_syncmem(&sqtd->dma, 1687 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1688 sizeof(sqtd->qtd), 1689 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1690 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1691 usb_syncmem(&sqtd->dma, 1692 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1693 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1694 } 1695 if (!stop) 1696 USBHIST_LOG(ehcidebug, 1697 "dump aborted, too many TDs", 0, 0, 0, 0); 1698 } 1699 1700 Static void 1701 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1702 { 1703 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1704 1705 usb_syncmem(&sqtd->dma, sqtd->offs, 1706 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1707 1708 USBHIST_LOGN(ehcidebug, 10, 1709 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1710 ehci_dump_qtd(&sqtd->qtd); 1711 1712 usb_syncmem(&sqtd->dma, sqtd->offs, 1713 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1714 } 1715 1716 Static void 1717 ehci_dump_qtd(ehci_qtd_t *qtd) 1718 { 1719 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1720 uint32_t s = le32toh(qtd->qtd_status); 1721 1722 USBHIST_LOGN(ehcidebug, 10, 1723 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1724 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1725 USBHIST_LOGN(ehcidebug, 10, 1726 " toggle = %d ioc = %d bytes = %#x " 1727 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1728 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1729 USBHIST_LOGN(ehcidebug, 10, 1730 " cerr = %d pid = %d stat = %x", 1731 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1732 0); 1733 USBHIST_LOGN(ehcidebug, 10, 1734 "active =%d halted=%d buferr=%d babble=%d", 1735 s & EHCI_QTD_ACTIVE ? 1 : 0, 1736 s & EHCI_QTD_HALTED ? 1 : 0, 1737 s & EHCI_QTD_BUFERR ? 1 : 0, 1738 s & EHCI_QTD_BABBLE ? 1 : 0); 1739 USBHIST_LOGN(ehcidebug, 10, 1740 "xacterr=%d missed=%d split =%d ping =%d", 1741 s & EHCI_QTD_XACTERR ? 1 : 0, 1742 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1743 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1744 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1745 USBHIST_LOGN(ehcidebug, 10, 1746 "buffer[0] = %#x buffer[1] = %#x " 1747 "buffer[2] = %#x buffer[3] = %#x", 1748 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1749 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1750 USBHIST_LOGN(ehcidebug, 10, 1751 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1752 } 1753 1754 Static void 1755 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1756 { 1757 ehci_qh_t *qh = &sqh->qh; 1758 ehci_link_t link; 1759 uint32_t endp, endphub; 1760 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1761 1762 usb_syncmem(&sqh->dma, sqh->offs, 1763 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1764 1765 USBHIST_LOGN(ehcidebug, 10, 1766 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1767 link = le32toh(qh->qh_link); 1768 ehci_dump_link(link, true); 1769 1770 endp = le32toh(qh->qh_endp); 1771 USBHIST_LOGN(ehcidebug, 10, 1772 " endp = %#x", endp, 0, 0, 0); 1773 USBHIST_LOGN(ehcidebug, 10, 1774 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1775 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1776 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1777 USBHIST_LOGN(ehcidebug, 10, 1778 " dtc = %d hrecl = %d", 1779 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1780 USBHIST_LOGN(ehcidebug, 10, 1781 " ctl = %d nrl = %d mpl = %#x(%d)", 1782 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1783 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1784 1785 endphub = le32toh(qh->qh_endphub); 1786 USBHIST_LOGN(ehcidebug, 10, 1787 " endphub = %#x", endphub, 0, 0, 0); 1788 USBHIST_LOGN(ehcidebug, 10, 1789 " smask = 0x%02x cmask = 0x%02x", 1790 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1791 USBHIST_LOGN(ehcidebug, 10, 1792 " huba = 0x%02x port = %d mult = %d", 1793 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1794 EHCI_QH_GET_MULT(endphub), 0); 1795 1796 link = le32toh(qh->qh_curqtd); 1797 ehci_dump_link(link, false); 1798 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1799 ehci_dump_qtd(&qh->qh_qtd); 1800 1801 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1802 BUS_DMASYNC_PREREAD); 1803 } 1804 1805 Static void 1806 ehci_dump_itds(ehci_soft_itd_t *itd) 1807 { 1808 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1809 int i; 1810 uint32_t stop = 0; 1811 1812 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1813 ehci_dump_itd(itd); 1814 usb_syncmem(&itd->dma, 1815 itd->offs + offsetof(ehci_itd_t, itd_next), 1816 sizeof(itd->itd), 1817 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1818 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1819 usb_syncmem(&itd->dma, 1820 itd->offs + offsetof(ehci_itd_t, itd_next), 1821 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1822 } 1823 if (!stop) 1824 USBHIST_LOG(ehcidebug, "dump aborted, too many TDs", 0, 0, 0, 0); 1825 } 1826 1827 Static void 1828 ehci_dump_itd(struct ehci_soft_itd *itd) 1829 { 1830 ehci_isoc_trans_t t; 1831 ehci_isoc_bufr_ptr_t b, b2, b3; 1832 int i; 1833 1834 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1835 1836 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1837 0, 0); 1838 1839 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1840 t = le32toh(itd->itd.itd_ctl[i]); 1841 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1842 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1843 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1844 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1845 EHCI_ITD_GET_OFFS(t), 0); 1846 } 1847 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1848 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1849 USBHIST_LOG(ehcidebug, " %x", 1850 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1851 1852 b = le32toh(itd->itd.itd_bufr[0]); 1853 b2 = le32toh(itd->itd.itd_bufr[1]); 1854 b3 = le32toh(itd->itd.itd_bufr[2]); 1855 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1856 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1857 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1858 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1859 } 1860 1861 Static void 1862 ehci_dump_sitd(struct ehci_soft_itd *itd) 1863 { 1864 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1865 1866 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1867 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1868 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1869 itd->xfer_next, itd->physaddr, itd->slot, 0); 1870 } 1871 1872 Static void 1873 ehci_dump_exfer(struct ehci_xfer *ex) 1874 { 1875 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1876 1877 USBHIST_LOG(ehcidebug, "ex = %p type %d isdone", ex, ex->ex_type, 1878 ex->ex_isdone, 0); 1879 1880 switch (ex->ex_type) { 1881 case EX_CTRL: 1882 USBHIST_LOG(ehcidebug, " setup = %p data = %p status = %p", 1883 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1884 break; 1885 case EX_BULK: 1886 case EX_INTR: 1887 USBHIST_LOG(ehcidebug, " qtdstart = %p qtdend = %p", 1888 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1889 break; 1890 case EX_ISOC: 1891 USBHIST_LOG(ehcidebug, " itdstart = %p itdend = %p", 1892 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1893 break; 1894 case EX_FS_ISOC: 1895 USBHIST_LOG(ehcidebug, " sitdstart = %p sitdend = %p", 1896 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1897 break; 1898 default: 1899 USBHIST_LOG(ehcidebug, " unknown type", 0, 0, 0, 0); 1900 } 1901 } 1902 #endif 1903 1904 Static usbd_status 1905 ehci_open(struct usbd_pipe *pipe) 1906 { 1907 struct usbd_device *dev = pipe->up_dev; 1908 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1909 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1910 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1911 uint8_t addr = dev->ud_addr; 1912 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1913 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1914 ehci_soft_qh_t *sqh; 1915 usbd_status err; 1916 int ival, speed, naks; 1917 int hshubaddr, hshubport; 1918 1919 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1920 1921 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1922 pipe, addr, ed->bEndpointAddress, rhaddr); 1923 1924 if (dev->ud_myhsport) { 1925 /* 1926 * When directly attached FS/LS device while doing embedded 1927 * transaction translations and we are the hub, set the hub 1928 * address to 0 (us). 1929 */ 1930 if (!(sc->sc_flags & EHCIF_ETTF) 1931 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1932 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1933 } else { 1934 hshubaddr = 0; 1935 } 1936 hshubport = dev->ud_myhsport->up_portno; 1937 } else { 1938 hshubaddr = 0; 1939 hshubport = 0; 1940 } 1941 1942 if (sc->sc_dying) 1943 return USBD_IOERROR; 1944 1945 /* toggle state needed for bulk endpoints */ 1946 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1947 1948 if (addr == rhaddr) { 1949 switch (ed->bEndpointAddress) { 1950 case USB_CONTROL_ENDPOINT: 1951 pipe->up_methods = &roothub_ctrl_methods; 1952 break; 1953 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1954 pipe->up_methods = &ehci_root_intr_methods; 1955 break; 1956 default: 1957 USBHIST_LOG(ehcidebug, 1958 "bad bEndpointAddress 0x%02x", 1959 ed->bEndpointAddress, 0, 0, 0); 1960 return USBD_INVAL; 1961 } 1962 return USBD_NORMAL_COMPLETION; 1963 } 1964 1965 /* XXX All this stuff is only valid for async. */ 1966 switch (dev->ud_speed) { 1967 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1968 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1969 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1970 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1971 } 1972 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1973 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1974 hshubaddr, hshubport, 0, 0); 1975 return USBD_INVAL; 1976 } 1977 1978 /* 1979 * For interrupt transfer, nak throttling must be disabled, but for 1980 * the other transfer type, nak throttling should be enabled from the 1981 * viewpoint that avoids the memory thrashing. 1982 */ 1983 naks = (xfertype == UE_INTERRUPT) ? 0 1984 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1985 1986 /* Allocate sqh for everything, save isoc xfers */ 1987 if (xfertype != UE_ISOCHRONOUS) { 1988 sqh = ehci_alloc_sqh(sc); 1989 if (sqh == NULL) 1990 return USBD_NOMEM; 1991 /* qh_link filled when the QH is added */ 1992 sqh->qh.qh_endp = htole32( 1993 EHCI_QH_SET_ADDR(addr) | 1994 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1995 EHCI_QH_SET_EPS(speed) | 1996 EHCI_QH_DTC | 1997 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1998 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1999 EHCI_QH_CTL : 0) | 2000 EHCI_QH_SET_NRL(naks) 2001 ); 2002 sqh->qh.qh_endphub = htole32( 2003 EHCI_QH_SET_MULT(1) | 2004 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 2005 ); 2006 if (speed != EHCI_QH_SPEED_HIGH) 2007 sqh->qh.qh_endphub |= htole32( 2008 EHCI_QH_SET_PORT(hshubport) | 2009 EHCI_QH_SET_HUBA(hshubaddr) | 2010 EHCI_QH_SET_CMASK(0x08) /* XXX */ 2011 ); 2012 sqh->qh.qh_curqtd = EHCI_NULL; 2013 /* Fill the overlay qTD */ 2014 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2015 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2016 sqh->qh.qh_qtd.qtd_status = htole32(0); 2017 2018 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2019 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2020 epipe->sqh = sqh; 2021 } else { 2022 sqh = NULL; 2023 } /*xfertype == UE_ISOC*/ 2024 2025 switch (xfertype) { 2026 case UE_CONTROL: 2027 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2028 0, &epipe->ctrl.reqdma); 2029 #ifdef EHCI_DEBUG 2030 if (err) 2031 printf("ehci_open: usb_allocmem()=%d\n", err); 2032 #endif 2033 if (err) 2034 goto bad; 2035 pipe->up_methods = &ehci_device_ctrl_methods; 2036 mutex_enter(&sc->sc_lock); 2037 ehci_add_qh(sc, sqh, sc->sc_async_head); 2038 mutex_exit(&sc->sc_lock); 2039 break; 2040 case UE_BULK: 2041 pipe->up_methods = &ehci_device_bulk_methods; 2042 mutex_enter(&sc->sc_lock); 2043 ehci_add_qh(sc, sqh, sc->sc_async_head); 2044 mutex_exit(&sc->sc_lock); 2045 break; 2046 case UE_INTERRUPT: 2047 pipe->up_methods = &ehci_device_intr_methods; 2048 ival = pipe->up_interval; 2049 if (ival == USBD_DEFAULT_INTERVAL) { 2050 if (speed == EHCI_QH_SPEED_HIGH) { 2051 if (ed->bInterval > 16) { 2052 /* 2053 * illegal with high-speed, but there 2054 * were documentation bugs in the spec, 2055 * so be generous 2056 */ 2057 ival = 256; 2058 } else 2059 ival = (1 << (ed->bInterval - 1)) / 8; 2060 } else 2061 ival = ed->bInterval; 2062 } 2063 err = ehci_device_setintr(sc, sqh, ival); 2064 if (err) 2065 goto bad; 2066 break; 2067 case UE_ISOCHRONOUS: 2068 if (speed == EHCI_QH_SPEED_HIGH) 2069 pipe->up_methods = &ehci_device_isoc_methods; 2070 else 2071 pipe->up_methods = &ehci_device_fs_isoc_methods; 2072 if (ed->bInterval == 0 || ed->bInterval > 16) { 2073 printf("ehci: opening pipe with invalid bInterval\n"); 2074 err = USBD_INVAL; 2075 goto bad; 2076 } 2077 if (UGETW(ed->wMaxPacketSize) == 0) { 2078 printf("ehci: zero length endpoint open request\n"); 2079 err = USBD_INVAL; 2080 goto bad; 2081 } 2082 epipe->isoc.next_frame = 0; 2083 epipe->isoc.cur_xfers = 0; 2084 break; 2085 default: 2086 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2087 err = USBD_INVAL; 2088 goto bad; 2089 } 2090 return USBD_NORMAL_COMPLETION; 2091 2092 bad: 2093 if (sqh != NULL) { 2094 mutex_enter(&sc->sc_lock); 2095 ehci_free_sqh(sc, sqh); 2096 mutex_exit(&sc->sc_lock); 2097 } 2098 return err; 2099 } 2100 2101 /* 2102 * Add an ED to the schedule. Called with USB lock held. 2103 */ 2104 Static void 2105 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2106 { 2107 2108 KASSERT(mutex_owned(&sc->sc_lock)); 2109 2110 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2111 2112 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2113 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2114 2115 sqh->next = head->next; 2116 sqh->qh.qh_link = head->qh.qh_link; 2117 2118 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2119 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2120 2121 head->next = sqh; 2122 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2123 2124 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2125 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2126 2127 #ifdef EHCI_DEBUG 2128 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2129 ehci_dump_sqh(sqh); 2130 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2131 #endif 2132 } 2133 2134 /* 2135 * Remove an ED from the schedule. Called with USB lock held. 2136 */ 2137 Static void 2138 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2139 { 2140 ehci_soft_qh_t *p; 2141 2142 KASSERT(mutex_owned(&sc->sc_lock)); 2143 2144 /* XXX */ 2145 for (p = head; p != NULL && p->next != sqh; p = p->next) 2146 ; 2147 if (p == NULL) 2148 panic("ehci_rem_qh: ED not found"); 2149 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2150 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2151 p->next = sqh->next; 2152 p->qh.qh_link = sqh->qh.qh_link; 2153 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2154 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2155 2156 ehci_sync_hc(sc); 2157 } 2158 2159 Static void 2160 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2161 { 2162 int i; 2163 uint32_t status; 2164 2165 /* Save toggle bit and ping status. */ 2166 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2167 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2168 status = sqh->qh.qh_qtd.qtd_status & 2169 htole32(EHCI_QTD_TOGGLE_MASK | 2170 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2171 /* Set HALTED to make hw leave it alone. */ 2172 sqh->qh.qh_qtd.qtd_status = 2173 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2174 usb_syncmem(&sqh->dma, 2175 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2176 sizeof(sqh->qh.qh_qtd.qtd_status), 2177 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2178 sqh->qh.qh_curqtd = 0; 2179 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2180 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2181 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2182 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2183 sqh->sqtd = sqtd; 2184 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2185 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2186 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2187 sqh->qh.qh_qtd.qtd_status = status; 2188 usb_syncmem(&sqh->dma, 2189 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2190 sizeof(sqh->qh.qh_qtd.qtd_status), 2191 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2192 } 2193 2194 /* 2195 * Ensure that the HC has released all references to the QH. We do this 2196 * by asking for a Async Advance Doorbell interrupt and then we wait for 2197 * the interrupt. 2198 * To make this easier we first obtain exclusive use of the doorbell. 2199 */ 2200 Static void 2201 ehci_sync_hc(ehci_softc_t *sc) 2202 { 2203 int error __diagused; 2204 2205 KASSERT(mutex_owned(&sc->sc_lock)); 2206 2207 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2208 2209 if (sc->sc_dying) { 2210 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2211 return; 2212 } 2213 /* ask for doorbell */ 2214 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2215 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2216 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2217 2218 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2219 2220 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x ... done", 2221 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2222 #ifdef DIAGNOSTIC 2223 if (error) 2224 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2225 #endif 2226 } 2227 2228 Static void 2229 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2230 { 2231 2232 KASSERT(mutex_owned(&sc->sc_lock)); 2233 2234 for (; itd != NULL; itd = itd->xfer_next) { 2235 struct ehci_soft_itd *prev = itd->frame_list.prev; 2236 2237 /* Unlink itd from hardware chain, or frame array */ 2238 if (prev == NULL) { /* We're at the table head */ 2239 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2240 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2241 usb_syncmem(&sc->sc_fldma, 2242 sizeof(ehci_link_t) * itd->slot, 2243 sizeof(ehci_link_t), 2244 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2245 2246 if (itd->frame_list.next != NULL) 2247 itd->frame_list.next->frame_list.prev = NULL; 2248 } else { 2249 /* XXX this part is untested... */ 2250 prev->itd.itd_next = itd->itd.itd_next; 2251 usb_syncmem(&itd->dma, 2252 itd->offs + offsetof(ehci_itd_t, itd_next), 2253 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2254 2255 prev->frame_list.next = itd->frame_list.next; 2256 if (itd->frame_list.next != NULL) 2257 itd->frame_list.next->frame_list.prev = prev; 2258 } 2259 } 2260 } 2261 2262 Static void 2263 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2264 { 2265 struct ehci_soft_itd *next; 2266 2267 mutex_enter(&sc->sc_lock); 2268 next = NULL; 2269 for (; itd != NULL; itd = next) { 2270 next = itd->xfer_next; 2271 ehci_free_itd_locked(sc, itd); 2272 } 2273 mutex_exit(&sc->sc_lock); 2274 } 2275 2276 Static void 2277 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2278 { 2279 2280 KASSERT(mutex_owned(&sc->sc_lock)); 2281 2282 for (; sitd != NULL; sitd = sitd->xfer_next) { 2283 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2284 2285 /* Unlink sitd from hardware chain, or frame array */ 2286 if (prev == NULL) { /* We're at the table head */ 2287 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2288 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2289 usb_syncmem(&sc->sc_fldma, 2290 sizeof(ehci_link_t) * sitd->slot, 2291 sizeof(ehci_link_t), 2292 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2293 2294 if (sitd->frame_list.next != NULL) 2295 sitd->frame_list.next->frame_list.prev = NULL; 2296 } else { 2297 /* XXX this part is untested... */ 2298 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2299 usb_syncmem(&sitd->dma, 2300 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2301 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2302 2303 prev->frame_list.next = sitd->frame_list.next; 2304 if (sitd->frame_list.next != NULL) 2305 sitd->frame_list.next->frame_list.prev = prev; 2306 } 2307 } 2308 } 2309 2310 Static void 2311 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2312 { 2313 2314 mutex_enter(&sc->sc_lock); 2315 struct ehci_soft_sitd *next = NULL; 2316 for (; sitd != NULL; sitd = next) { 2317 next = sitd->xfer_next; 2318 ehci_free_sitd_locked(sc, sitd); 2319 } 2320 mutex_exit(&sc->sc_lock); 2321 } 2322 2323 /***********/ 2324 2325 Static int 2326 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2327 void *buf, int buflen) 2328 { 2329 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2330 usb_hub_descriptor_t hubd; 2331 usb_port_status_t ps; 2332 uint16_t len, value, index; 2333 int l, totlen = 0; 2334 int port, i; 2335 uint32_t v; 2336 2337 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2338 2339 if (sc->sc_dying) 2340 return -1; 2341 2342 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2343 req->bmRequestType, req->bRequest, 0, 0); 2344 2345 len = UGETW(req->wLength); 2346 value = UGETW(req->wValue); 2347 index = UGETW(req->wIndex); 2348 2349 #define C(x,y) ((x) | ((y) << 8)) 2350 switch (C(req->bRequest, req->bmRequestType)) { 2351 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2352 if (len == 0) 2353 break; 2354 switch (value) { 2355 case C(0, UDESC_DEVICE): { 2356 usb_device_descriptor_t devd; 2357 totlen = min(buflen, sizeof(devd)); 2358 memcpy(&devd, buf, totlen); 2359 USETW(devd.idVendor, sc->sc_id_vendor); 2360 memcpy(buf, &devd, totlen); 2361 break; 2362 2363 } 2364 #define sd ((usb_string_descriptor_t *)buf) 2365 case C(1, UDESC_STRING): 2366 /* Vendor */ 2367 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2368 break; 2369 case C(2, UDESC_STRING): 2370 /* Product */ 2371 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2372 break; 2373 #undef sd 2374 default: 2375 /* default from usbroothub */ 2376 return buflen; 2377 } 2378 break; 2379 2380 /* Hub requests */ 2381 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2382 break; 2383 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2384 USBHIST_LOG(ehcidebug, 2385 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2386 0, 0); 2387 if (index < 1 || index > sc->sc_noport) { 2388 return -1; 2389 } 2390 port = EHCI_PORTSC(index); 2391 v = EOREAD4(sc, port); 2392 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2393 v &= ~EHCI_PS_CLEAR; 2394 switch (value) { 2395 case UHF_PORT_ENABLE: 2396 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2397 break; 2398 case UHF_PORT_SUSPEND: 2399 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2400 break; 2401 v &= ~EHCI_PS_SUSP; 2402 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2403 /* see USB2 spec ch. 7.1.7.7 */ 2404 usb_delay_ms(&sc->sc_bus, 20); 2405 EOWRITE4(sc, port, v); 2406 usb_delay_ms(&sc->sc_bus, 2); 2407 #ifdef DEBUG 2408 v = EOREAD4(sc, port); 2409 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2410 printf("ehci: resume failed: %x\n", v); 2411 #endif 2412 break; 2413 case UHF_PORT_POWER: 2414 if (sc->sc_hasppc) 2415 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2416 break; 2417 case UHF_PORT_TEST: 2418 USBHIST_LOG(ehcidebug, "clear port test " 2419 "%d", index, 0, 0, 0); 2420 break; 2421 case UHF_PORT_INDICATOR: 2422 USBHIST_LOG(ehcidebug, "clear port ind " 2423 "%d", index, 0, 0, 0); 2424 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2425 break; 2426 case UHF_C_PORT_CONNECTION: 2427 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2428 break; 2429 case UHF_C_PORT_ENABLE: 2430 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2431 break; 2432 case UHF_C_PORT_SUSPEND: 2433 /* how? */ 2434 break; 2435 case UHF_C_PORT_OVER_CURRENT: 2436 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2437 break; 2438 case UHF_C_PORT_RESET: 2439 sc->sc_isreset[index] = 0; 2440 break; 2441 default: 2442 return -1; 2443 } 2444 #if 0 2445 switch(value) { 2446 case UHF_C_PORT_CONNECTION: 2447 case UHF_C_PORT_ENABLE: 2448 case UHF_C_PORT_SUSPEND: 2449 case UHF_C_PORT_OVER_CURRENT: 2450 case UHF_C_PORT_RESET: 2451 default: 2452 break; 2453 } 2454 #endif 2455 break; 2456 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2457 if (len == 0) 2458 break; 2459 if ((value & 0xff) != 0) { 2460 return -1; 2461 } 2462 totlen = min(buflen, sizeof(hubd)); 2463 memcpy(&hubd, buf, totlen); 2464 hubd.bNbrPorts = sc->sc_noport; 2465 v = EOREAD4(sc, EHCI_HCSPARAMS); 2466 USETW(hubd.wHubCharacteristics, 2467 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2468 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2469 ? UHD_PORT_IND : 0); 2470 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2471 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2472 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2473 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2474 totlen = min(totlen, hubd.bDescLength); 2475 memcpy(buf, &hubd, totlen); 2476 break; 2477 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2478 if (len != 4) { 2479 return -1; 2480 } 2481 memset(buf, 0, len); /* ? XXX */ 2482 totlen = len; 2483 break; 2484 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2485 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2486 if (index < 1 || index > sc->sc_noport) { 2487 return -1; 2488 } 2489 if (len != 4) { 2490 return -1; 2491 } 2492 v = EOREAD4(sc, EHCI_PORTSC(index)); 2493 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2494 2495 i = UPS_HIGH_SPEED; 2496 if (sc->sc_flags & EHCIF_ETTF) { 2497 /* 2498 * If we are doing embedded transaction translation, 2499 * then directly attached LS/FS devices are reset by 2500 * the EHCI controller itself. PSPD is encoded 2501 * the same way as in USBSTATUS. 2502 */ 2503 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2504 } 2505 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2506 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2507 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2508 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2509 if (v & EHCI_PS_PR) i |= UPS_RESET; 2510 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2511 if (sc->sc_vendor_port_status) 2512 i = sc->sc_vendor_port_status(sc, v, i); 2513 USETW(ps.wPortStatus, i); 2514 i = 0; 2515 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2516 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2517 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2518 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2519 USETW(ps.wPortChange, i); 2520 totlen = min(len, sizeof(ps)); 2521 memcpy(buf, &ps, totlen); 2522 break; 2523 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2524 return -1; 2525 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2526 break; 2527 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2528 if (index < 1 || index > sc->sc_noport) { 2529 return -1; 2530 } 2531 port = EHCI_PORTSC(index); 2532 v = EOREAD4(sc, port); 2533 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2534 v &= ~EHCI_PS_CLEAR; 2535 switch(value) { 2536 case UHF_PORT_ENABLE: 2537 EOWRITE4(sc, port, v | EHCI_PS_PE); 2538 break; 2539 case UHF_PORT_SUSPEND: 2540 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2541 break; 2542 case UHF_PORT_RESET: 2543 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2544 if (EHCI_PS_IS_LOWSPEED(v) 2545 && sc->sc_ncomp > 0 2546 && !(sc->sc_flags & EHCIF_ETTF)) { 2547 /* 2548 * Low speed device on non-ETTF controller or 2549 * unaccompanied controller, give up ownership. 2550 */ 2551 ehci_disown(sc, index, 1); 2552 break; 2553 } 2554 /* Start reset sequence. */ 2555 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2556 EOWRITE4(sc, port, v | EHCI_PS_PR); 2557 /* Wait for reset to complete. */ 2558 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2559 if (sc->sc_dying) { 2560 return -1; 2561 } 2562 /* 2563 * An embedded transaction translator will automatically 2564 * terminate the reset sequence so there's no need to 2565 * it. 2566 */ 2567 v = EOREAD4(sc, port); 2568 if (v & EHCI_PS_PR) { 2569 /* Terminate reset sequence. */ 2570 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2571 /* Wait for HC to complete reset. */ 2572 usb_delay_ms(&sc->sc_bus, 2573 EHCI_PORT_RESET_COMPLETE); 2574 if (sc->sc_dying) { 2575 return -1; 2576 } 2577 } 2578 2579 v = EOREAD4(sc, port); 2580 USBHIST_LOG(ehcidebug, 2581 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2582 if (v & EHCI_PS_PR) { 2583 printf("%s: port reset timeout\n", 2584 device_xname(sc->sc_dev)); 2585 return USBD_TIMEOUT; 2586 } 2587 if (!(v & EHCI_PS_PE)) { 2588 /* Not a high speed device, give up ownership.*/ 2589 ehci_disown(sc, index, 0); 2590 break; 2591 } 2592 sc->sc_isreset[index] = 1; 2593 USBHIST_LOG(ehcidebug, 2594 "ehci port %d reset, status = 0x%08x", index, v, 0, 2595 0); 2596 break; 2597 case UHF_PORT_POWER: 2598 USBHIST_LOG(ehcidebug, 2599 "set port power %d (has PPC = %d)", index, 2600 sc->sc_hasppc, 0, 0); 2601 if (sc->sc_hasppc) 2602 EOWRITE4(sc, port, v | EHCI_PS_PP); 2603 break; 2604 case UHF_PORT_TEST: 2605 USBHIST_LOG(ehcidebug, "set port test %d", 2606 index, 0, 0, 0); 2607 break; 2608 case UHF_PORT_INDICATOR: 2609 USBHIST_LOG(ehcidebug, "set port ind %d", 2610 index, 0, 0, 0); 2611 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2612 break; 2613 default: 2614 return -1; 2615 } 2616 break; 2617 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2618 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2619 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2620 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2621 break; 2622 default: 2623 /* default from usbroothub */ 2624 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2625 buflen, 0, 0, 0); 2626 2627 return buflen; 2628 } 2629 2630 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2631 2632 return totlen; 2633 } 2634 2635 Static void 2636 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2637 { 2638 int port; 2639 uint32_t v; 2640 2641 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2642 2643 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2644 #ifdef DIAGNOSTIC 2645 if (sc->sc_npcomp != 0) { 2646 int i = (index-1) / sc->sc_npcomp; 2647 if (i >= sc->sc_ncomp) 2648 printf("%s: strange port\n", 2649 device_xname(sc->sc_dev)); 2650 else 2651 printf("%s: handing over %s speed device on " 2652 "port %d to %s\n", 2653 device_xname(sc->sc_dev), 2654 lowspeed ? "low" : "full", 2655 index, device_xname(sc->sc_comps[i])); 2656 } else { 2657 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2658 } 2659 #endif 2660 port = EHCI_PORTSC(index); 2661 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2662 EOWRITE4(sc, port, v | EHCI_PS_PO); 2663 } 2664 2665 Static usbd_status 2666 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2667 { 2668 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2669 usbd_status err; 2670 2671 /* Insert last in queue. */ 2672 mutex_enter(&sc->sc_lock); 2673 err = usb_insert_transfer(xfer); 2674 mutex_exit(&sc->sc_lock); 2675 if (err) 2676 return err; 2677 2678 /* Pipe isn't running, start first */ 2679 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2680 } 2681 2682 Static usbd_status 2683 ehci_root_intr_start(struct usbd_xfer *xfer) 2684 { 2685 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2686 2687 if (sc->sc_dying) 2688 return USBD_IOERROR; 2689 2690 mutex_enter(&sc->sc_lock); 2691 sc->sc_intrxfer = xfer; 2692 mutex_exit(&sc->sc_lock); 2693 2694 return USBD_IN_PROGRESS; 2695 } 2696 2697 /* Abort a root interrupt request. */ 2698 Static void 2699 ehci_root_intr_abort(struct usbd_xfer *xfer) 2700 { 2701 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2702 2703 KASSERT(mutex_owned(&sc->sc_lock)); 2704 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2705 2706 sc->sc_intrxfer = NULL; 2707 2708 xfer->ux_status = USBD_CANCELLED; 2709 usb_transfer_complete(xfer); 2710 } 2711 2712 /* Close the root pipe. */ 2713 Static void 2714 ehci_root_intr_close(struct usbd_pipe *pipe) 2715 { 2716 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2717 2718 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2719 2720 KASSERT(mutex_owned(&sc->sc_lock)); 2721 2722 sc->sc_intrxfer = NULL; 2723 } 2724 2725 Static void 2726 ehci_root_intr_done(struct usbd_xfer *xfer) 2727 { 2728 xfer->ux_hcpriv = NULL; 2729 } 2730 2731 /************************/ 2732 2733 Static ehci_soft_qh_t * 2734 ehci_alloc_sqh(ehci_softc_t *sc) 2735 { 2736 ehci_soft_qh_t *sqh; 2737 usbd_status err; 2738 int i, offs; 2739 usb_dma_t dma; 2740 2741 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2742 2743 mutex_enter(&sc->sc_lock); 2744 if (sc->sc_freeqhs == NULL) { 2745 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2746 mutex_exit(&sc->sc_lock); 2747 2748 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2749 EHCI_PAGE_SIZE, &dma); 2750 #ifdef EHCI_DEBUG 2751 if (err) 2752 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2753 #endif 2754 if (err) 2755 return NULL; 2756 2757 mutex_enter(&sc->sc_lock); 2758 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2759 offs = i * EHCI_SQH_SIZE; 2760 sqh = KERNADDR(&dma, offs); 2761 sqh->physaddr = DMAADDR(&dma, offs); 2762 sqh->dma = dma; 2763 sqh->offs = offs; 2764 sqh->next = sc->sc_freeqhs; 2765 sc->sc_freeqhs = sqh; 2766 } 2767 } 2768 sqh = sc->sc_freeqhs; 2769 sc->sc_freeqhs = sqh->next; 2770 mutex_exit(&sc->sc_lock); 2771 2772 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2773 sqh->next = NULL; 2774 return sqh; 2775 } 2776 2777 Static void 2778 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2779 { 2780 KASSERT(mutex_owned(&sc->sc_lock)); 2781 2782 sqh->next = sc->sc_freeqhs; 2783 sc->sc_freeqhs = sqh; 2784 } 2785 2786 Static ehci_soft_qtd_t * 2787 ehci_alloc_sqtd(ehci_softc_t *sc) 2788 { 2789 ehci_soft_qtd_t *sqtd = NULL; 2790 usbd_status err; 2791 int i, offs; 2792 usb_dma_t dma; 2793 2794 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2795 2796 mutex_enter(&sc->sc_lock); 2797 if (sc->sc_freeqtds == NULL) { 2798 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2799 mutex_exit(&sc->sc_lock); 2800 2801 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2802 EHCI_PAGE_SIZE, &dma); 2803 #ifdef EHCI_DEBUG 2804 if (err) 2805 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2806 #endif 2807 if (err) 2808 goto done; 2809 2810 mutex_enter(&sc->sc_lock); 2811 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2812 offs = i * EHCI_SQTD_SIZE; 2813 sqtd = KERNADDR(&dma, offs); 2814 sqtd->physaddr = DMAADDR(&dma, offs); 2815 sqtd->dma = dma; 2816 sqtd->offs = offs; 2817 2818 sqtd->nextqtd = sc->sc_freeqtds; 2819 sc->sc_freeqtds = sqtd; 2820 } 2821 } 2822 2823 sqtd = sc->sc_freeqtds; 2824 sc->sc_freeqtds = sqtd->nextqtd; 2825 mutex_exit(&sc->sc_lock); 2826 2827 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2828 sqtd->nextqtd = NULL; 2829 sqtd->xfer = NULL; 2830 2831 done: 2832 return sqtd; 2833 } 2834 2835 Static void 2836 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2837 { 2838 2839 mutex_enter(&sc->sc_lock); 2840 sqtd->nextqtd = sc->sc_freeqtds; 2841 sc->sc_freeqtds = sqtd; 2842 mutex_exit(&sc->sc_lock); 2843 } 2844 2845 Static usbd_status 2846 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2847 int alen, int rd, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2848 { 2849 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2850 ehci_soft_qtd_t *next, *cur; 2851 ehci_physaddr_t nextphys; 2852 uint32_t qtdstatus; 2853 int len, curlen, mps; 2854 int i, tog; 2855 int pages, pageoffs; 2856 size_t curoffs; 2857 vaddr_t va, va_offs; 2858 usb_dma_t *dma = &xfer->ux_dmabuf; 2859 uint16_t flags = xfer->ux_flags; 2860 paddr_t a; 2861 2862 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2863 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2864 2865 ASSERT_SLEEPABLE(); 2866 KASSERT(sp); 2867 KASSERT(alen != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2868 2869 len = alen; 2870 qtdstatus = EHCI_QTD_ACTIVE | 2871 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2872 EHCI_QTD_SET_CERR(3) 2873 ; 2874 2875 size_t nsqtd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 2876 nsqtd += ((len + EHCI_QTD_MAXTRANSFER - 1) / EHCI_QTD_MAXTRANSFER); 2877 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2878 KM_SLEEP); 2879 exfer->ex_nsqtd = nsqtd; 2880 2881 mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2882 cur = ehci_alloc_sqtd(sc); 2883 *sp = cur; 2884 if (cur == NULL) 2885 goto nomem; 2886 2887 curoffs = 0; 2888 for (size_t j = 0;;) { 2889 KASSERT(j < nsqtd); 2890 exfer->ex_sqtds[j++] = cur; 2891 2892 /* The EHCI hardware can handle at most 5 pages. */ 2893 va = (vaddr_t)KERNADDR(dma, curoffs); 2894 va_offs = EHCI_PAGE_OFFSET(va); 2895 if (len - curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2896 /* we can handle it in this QTD */ 2897 curlen = len - curoffs; 2898 } else { 2899 /* must use multiple TDs, fill as much as possible. */ 2900 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2901 2902 /* the length must be a multiple of the max size */ 2903 curlen -= curlen % mps; 2904 USBHIST_LOG(ehcidebug, "multiple QTDs, curlen=%d", 2905 curlen, 0, 0, 0); 2906 KASSERT(curlen != 0); 2907 } 2908 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", len, 2909 curlen, curoffs, 0); 2910 2911 /* 2912 * Allocate another transfer if there's more data left, 2913 * or if force last short transfer flag is set and we're 2914 * allocating a multiple of the max packet size. 2915 */ 2916 2917 if (curoffs + curlen != len || 2918 ((curlen % mps) == 0 && !rd && curlen != 0 && 2919 (flags & USBD_FORCE_SHORT_XFER))) { 2920 next = ehci_alloc_sqtd(sc); 2921 if (next == NULL) 2922 goto nomem; 2923 nextphys = htole32(next->physaddr); 2924 } else { 2925 next = NULL; 2926 nextphys = EHCI_NULL; 2927 } 2928 2929 /* Find number of pages we'll be using, insert dma addresses */ 2930 pages = EHCI_NPAGES(curlen); 2931 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2932 pageoffs = EHCI_PAGE(curoffs); 2933 for (i = 0; i < pages; i++) { 2934 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2935 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2936 /* Cast up to avoid compiler warnings */ 2937 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2938 } 2939 2940 /* First buffer pointer requires a page offset to start at */ 2941 cur->qtd.qtd_buffer[0] |= htole32(va_offs); 2942 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2943 cur->qtd.qtd_status = htole32(qtdstatus); 2944 cur->nextqtd = next; 2945 cur->xfer = xfer; 2946 cur->bufoff = curoffs; 2947 cur->tdlen = curlen; 2948 cur->len = 0; 2949 2950 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2951 curoffs, curoffs + curlen, 0, 0); 2952 2953 /* 2954 * adjust the toggle based on the number of packets in this 2955 * qtd 2956 */ 2957 if (((curlen + mps - 1) / mps) & 1) { 2958 tog ^= 1; 2959 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2960 } 2961 if (next == NULL) 2962 break; 2963 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2964 if (len) 2965 curoffs += curlen; 2966 cur = next; 2967 } 2968 if (ep) 2969 *ep = cur; 2970 2971 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", *sp, cur, 0, 0); 2972 2973 return USBD_NORMAL_COMPLETION; 2974 2975 nomem: 2976 ehci_free_sqtds(sc, exfer); 2977 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2978 return USBD_NOMEM; 2979 } 2980 2981 Static void 2982 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2983 { 2984 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2985 USBHIST_LOG(ehcidebug, "exfer=%p", exfer, 0, 0, 0); 2986 2987 mutex_enter(&sc->sc_lock); 2988 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2989 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2990 2991 if (sqtd == NULL) 2992 break; 2993 2994 sqtd->nextqtd = sc->sc_freeqtds; 2995 sc->sc_freeqtds = sqtd; 2996 } 2997 mutex_exit(&sc->sc_lock); 2998 } 2999 3000 Static void 3001 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3002 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3003 { 3004 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3005 ehci_soft_qtd_t *sqtd, *prev; 3006 int tog = *toggle; 3007 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3008 int len = length; 3009 size_t i; 3010 3011 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3012 USBHIST_LOG(ehcidebug, "xfer=%p len %d isread %d toggle %d", xfer, 3013 len, isread, *toggle); 3014 USBHIST_LOG(ehcidebug, " VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 3015 0, 0, 0); 3016 3017 sqtd = prev = NULL; 3018 for (i = 0; i < exfer->ex_nsqtd; i++, prev = sqtd) { 3019 sqtd = exfer->ex_sqtds[i]; 3020 vaddr_t va = (vaddr_t)KERNADDR(&xfer->ux_dmabuf, sqtd->bufoff); 3021 sqtd->len = sqtd->tdlen; 3022 if (len < sqtd->len) { 3023 sqtd->len = len; 3024 } 3025 3026 USBHIST_LOG(ehcidebug, "sqtd[%d]=%p prev %p len %d", i, sqtd, 3027 prev, sqtd->len); 3028 USBHIST_LOG(ehcidebug, " va %p bufoff %d pa %p", va, sqtd->bufoff, 3029 DMAADDR(&xfer->ux_dmabuf, sqtd->bufoff), 0); 3030 3031 if (prev) { 3032 prev->nextqtd = sqtd; 3033 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3034 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3035 } 3036 usb_syncmem(&sqtd->dma, 3037 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3038 sizeof(sqtd->qtd.qtd_status), 3039 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3040 usb_syncmem(&sqtd->dma, 3041 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3042 sizeof(sqtd->qtd.qtd_buffer[0]), 3043 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3044 3045 sqtd->qtd.qtd_buffer[0] &= ~htole32(EHCI_PAGE_MASK); 3046 sqtd->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3047 /* Reset ... */ 3048 sqtd->qtd.qtd_status &= ~htole32( 3049 EHCI_QTD_STATUS_MASK | 3050 EHCI_QTD_PID_MASK | 3051 EHCI_QTD_CERR_MASK | 3052 EHCI_QTD_C_PAGE_MASK | 3053 EHCI_QTD_BYTES_MASK | 3054 EHCI_QTD_TOGGLE_MASK); 3055 sqtd->qtd.qtd_status |= htole32( 3056 EHCI_QTD_ACTIVE | 3057 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3058 EHCI_QTD_SET_BYTES(sqtd->len) | 3059 EHCI_QTD_SET_CERR(3) | 3060 EHCI_QTD_SET_TOGGLE(tog)); 3061 3062 usb_syncmem(&sqtd->dma, 3063 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3064 sizeof(sqtd->qtd.qtd_status), 3065 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3066 usb_syncmem(&sqtd->dma, 3067 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3068 sizeof(sqtd->qtd.qtd_buffer[0]), 3069 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3070 3071 if (((sqtd->len + mps - 1) / mps) & 1) { 3072 tog ^= 1; 3073 } 3074 3075 len -= sqtd->len; 3076 if (len == 0) 3077 break; 3078 } 3079 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu i %zu", 3080 xfer, length, len, mps, exfer->ex_nsqtd, i); 3081 3082 if (i < exfer->ex_nsqtd) { 3083 /* 3084 * The full allocation chain wasn't used, so we need to 3085 * terminate it. 3086 */ 3087 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3088 } 3089 *lsqtd = sqtd; 3090 *toggle = tog; 3091 } 3092 3093 Static ehci_soft_itd_t * 3094 ehci_alloc_itd(ehci_softc_t *sc) 3095 { 3096 struct ehci_soft_itd *itd, *freeitd; 3097 usbd_status err; 3098 usb_dma_t dma; 3099 3100 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3101 3102 mutex_enter(&sc->sc_lock); 3103 3104 freeitd = LIST_FIRST(&sc->sc_freeitds); 3105 if (freeitd == NULL) { 3106 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3107 mutex_exit(&sc->sc_lock); 3108 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3109 EHCI_PAGE_SIZE, &dma); 3110 3111 if (err) { 3112 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 0); 3113 return NULL; 3114 } 3115 mutex_enter(&sc->sc_lock); 3116 3117 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3118 int offs = i * EHCI_ITD_SIZE; 3119 itd = KERNADDR(&dma, offs); 3120 itd->physaddr = DMAADDR(&dma, offs); 3121 itd->dma = dma; 3122 itd->offs = offs; 3123 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3124 } 3125 freeitd = LIST_FIRST(&sc->sc_freeitds); 3126 } 3127 3128 itd = freeitd; 3129 LIST_REMOVE(itd, free_list); 3130 mutex_exit(&sc->sc_lock); 3131 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3132 3133 itd->frame_list.next = NULL; 3134 itd->frame_list.prev = NULL; 3135 itd->xfer_next = NULL; 3136 itd->slot = 0; 3137 3138 return itd; 3139 } 3140 3141 Static ehci_soft_sitd_t * 3142 ehci_alloc_sitd(ehci_softc_t *sc) 3143 { 3144 struct ehci_soft_sitd *sitd, *freesitd; 3145 usbd_status err; 3146 int i, offs; 3147 usb_dma_t dma; 3148 3149 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3150 3151 mutex_enter(&sc->sc_lock); 3152 freesitd = LIST_FIRST(&sc->sc_freesitds); 3153 if (freesitd == NULL) { 3154 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3155 mutex_exit(&sc->sc_lock); 3156 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3157 EHCI_PAGE_SIZE, &dma); 3158 3159 if (err) { 3160 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 3161 0); 3162 return NULL; 3163 } 3164 3165 mutex_enter(&sc->sc_lock); 3166 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3167 offs = i * EHCI_SITD_SIZE; 3168 sitd = KERNADDR(&dma, offs); 3169 sitd->physaddr = DMAADDR(&dma, offs); 3170 sitd->dma = dma; 3171 sitd->offs = offs; 3172 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3173 } 3174 freesitd = LIST_FIRST(&sc->sc_freesitds); 3175 } 3176 3177 sitd = freesitd; 3178 LIST_REMOVE(sitd, free_list); 3179 mutex_exit(&sc->sc_lock); 3180 3181 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3182 3183 sitd->frame_list.next = NULL; 3184 sitd->frame_list.prev = NULL; 3185 sitd->xfer_next = NULL; 3186 sitd->slot = 0; 3187 3188 return sitd; 3189 } 3190 3191 /****************/ 3192 3193 /* 3194 * Close a reqular pipe. 3195 * Assumes that there are no pending transactions. 3196 */ 3197 Static void 3198 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3199 { 3200 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3201 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3202 ehci_soft_qh_t *sqh = epipe->sqh; 3203 3204 KASSERT(mutex_owned(&sc->sc_lock)); 3205 3206 ehci_rem_qh(sc, sqh, head); 3207 ehci_free_sqh(sc, epipe->sqh); 3208 } 3209 3210 /* 3211 * Abort a device request. 3212 * If this routine is called at splusb() it guarantees that the request 3213 * will be removed from the hardware scheduling and that the callback 3214 * for it will be called with USBD_CANCELLED status. 3215 * It's impossible to guarantee that the requested transfer will not 3216 * have happened since the hardware runs concurrently. 3217 * If the transaction has already happened we rely on the ordinary 3218 * interrupt processing to process it. 3219 * XXX This is most probably wrong. 3220 * XXXMRG this doesn't make sense anymore. 3221 */ 3222 Static void 3223 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3224 { 3225 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3226 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3227 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3228 ehci_soft_qh_t *sqh = epipe->sqh; 3229 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3230 ehci_physaddr_t cur; 3231 uint32_t qhstatus; 3232 int hit; 3233 int wake; 3234 3235 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3236 3237 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3238 3239 KASSERT(mutex_owned(&sc->sc_lock)); 3240 ASSERT_SLEEPABLE(); 3241 3242 if (sc->sc_dying) { 3243 /* If we're dying, just do the software part. */ 3244 xfer->ux_status = status; /* make software ignore it */ 3245 callout_stop(&xfer->ux_callout); 3246 usb_transfer_complete(xfer); 3247 return; 3248 } 3249 3250 /* 3251 * If an abort is already in progress then just wait for it to 3252 * complete and return. 3253 */ 3254 if (xfer->ux_hcflags & UXFER_ABORTING) { 3255 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3256 #ifdef DIAGNOSTIC 3257 if (status == USBD_TIMEOUT) 3258 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3259 #endif 3260 /* Override the status which might be USBD_TIMEOUT. */ 3261 xfer->ux_status = status; 3262 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 0, 0, 0, 3263 0); 3264 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3265 while (xfer->ux_hcflags & UXFER_ABORTING) 3266 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3267 return; 3268 } 3269 xfer->ux_hcflags |= UXFER_ABORTING; 3270 3271 /* 3272 * Step 1: Make interrupt routine and hardware ignore xfer. 3273 */ 3274 xfer->ux_status = status; /* make software ignore it */ 3275 callout_stop(&xfer->ux_callout); 3276 ehci_del_intr_list(sc, exfer); 3277 3278 usb_syncmem(&sqh->dma, 3279 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3280 sizeof(sqh->qh.qh_qtd.qtd_status), 3281 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3282 qhstatus = sqh->qh.qh_qtd.qtd_status; 3283 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3284 usb_syncmem(&sqh->dma, 3285 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3286 sizeof(sqh->qh.qh_qtd.qtd_status), 3287 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3288 3289 if (exfer->ex_type == EX_CTRL) { 3290 fsqtd = exfer->ex_setup; 3291 lsqtd = exfer->ex_status; 3292 } else { 3293 fsqtd = exfer->ex_sqtdstart; 3294 lsqtd = exfer->ex_sqtdend; 3295 } 3296 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3297 usb_syncmem(&sqtd->dma, 3298 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3299 sizeof(sqtd->qtd.qtd_status), 3300 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3301 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3302 usb_syncmem(&sqtd->dma, 3303 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3304 sizeof(sqtd->qtd.qtd_status), 3305 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3306 if (sqtd == lsqtd) 3307 break; 3308 } 3309 3310 /* 3311 * Step 2: Wait until we know hardware has finished any possible 3312 * use of the xfer. Also make sure the soft interrupt routine 3313 * has run. 3314 */ 3315 ehci_sync_hc(sc); 3316 sc->sc_softwake = 1; 3317 usb_schedsoftintr(&sc->sc_bus); 3318 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3319 3320 /* 3321 * Step 3: Remove any vestiges of the xfer from the hardware. 3322 * The complication here is that the hardware may have executed 3323 * beyond the xfer we're trying to abort. So as we're scanning 3324 * the TDs of this xfer we check if the hardware points to 3325 * any of them. 3326 */ 3327 3328 usb_syncmem(&sqh->dma, 3329 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3330 sizeof(sqh->qh.qh_curqtd), 3331 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3332 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3333 hit = 0; 3334 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3335 hit |= cur == sqtd->physaddr; 3336 if (sqtd == lsqtd) 3337 break; 3338 } 3339 sqtd = sqtd->nextqtd; 3340 /* Zap curqtd register if hardware pointed inside the xfer. */ 3341 if (hit && sqtd != NULL) { 3342 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3343 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3344 usb_syncmem(&sqh->dma, 3345 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3346 sizeof(sqh->qh.qh_curqtd), 3347 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3348 sqh->qh.qh_qtd.qtd_status = qhstatus; 3349 usb_syncmem(&sqh->dma, 3350 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3351 sizeof(sqh->qh.qh_qtd.qtd_status), 3352 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3353 } else { 3354 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3355 usb_syncmem(&sqh->dma, 3356 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3357 sizeof(sqh->qh.qh_curqtd), 3358 BUS_DMASYNC_PREREAD); 3359 } 3360 3361 /* 3362 * Step 4: Execute callback. 3363 */ 3364 #ifdef DIAGNOSTIC 3365 exfer->ex_isdone = true; 3366 #endif 3367 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3368 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3369 usb_transfer_complete(xfer); 3370 if (wake) { 3371 cv_broadcast(&xfer->ux_hccv); 3372 } 3373 3374 KASSERT(mutex_owned(&sc->sc_lock)); 3375 } 3376 3377 Static void 3378 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3379 { 3380 ehci_isoc_trans_t trans_status; 3381 struct ehci_xfer *exfer; 3382 ehci_softc_t *sc; 3383 struct ehci_soft_itd *itd; 3384 struct ehci_soft_sitd *sitd; 3385 int i, wake; 3386 3387 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3388 3389 exfer = EHCI_XFER2EXFER(xfer); 3390 sc = EHCI_XFER2SC(xfer); 3391 3392 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3393 3394 KASSERT(mutex_owned(&sc->sc_lock)); 3395 3396 if (sc->sc_dying) { 3397 xfer->ux_status = status; 3398 callout_stop(&xfer->ux_callout); 3399 usb_transfer_complete(xfer); 3400 return; 3401 } 3402 3403 if (xfer->ux_hcflags & UXFER_ABORTING) { 3404 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3405 3406 #ifdef DIAGNOSTIC 3407 if (status == USBD_TIMEOUT) 3408 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3409 #endif 3410 3411 xfer->ux_status = status; 3412 USBHIST_LOG(ehcidebug, 3413 "waiting for abort to finish", 0, 0, 0, 0); 3414 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3415 while (xfer->ux_hcflags & UXFER_ABORTING) 3416 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3417 goto done; 3418 } 3419 xfer->ux_hcflags |= UXFER_ABORTING; 3420 3421 xfer->ux_status = status; 3422 callout_stop(&xfer->ux_callout); 3423 3424 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3425 for (itd = exfer->ex_itdstart; itd != NULL; 3426 itd = itd->xfer_next) { 3427 usb_syncmem(&itd->dma, 3428 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3429 sizeof(itd->itd.itd_ctl), 3430 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3431 3432 for (i = 0; i < 8; i++) { 3433 trans_status = le32toh(itd->itd.itd_ctl[i]); 3434 trans_status &= ~EHCI_ITD_ACTIVE; 3435 itd->itd.itd_ctl[i] = htole32(trans_status); 3436 } 3437 3438 usb_syncmem(&itd->dma, 3439 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3440 sizeof(itd->itd.itd_ctl), 3441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3442 } 3443 } else { 3444 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3445 sitd = sitd->xfer_next) { 3446 usb_syncmem(&sitd->dma, 3447 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3448 sizeof(sitd->sitd.sitd_buffer), 3449 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3450 3451 trans_status = le32toh(sitd->sitd.sitd_trans); 3452 trans_status &= ~EHCI_SITD_ACTIVE; 3453 sitd->sitd.sitd_trans = htole32(trans_status); 3454 3455 usb_syncmem(&sitd->dma, 3456 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3457 sizeof(sitd->sitd.sitd_buffer), 3458 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3459 } 3460 } 3461 3462 sc->sc_softwake = 1; 3463 usb_schedsoftintr(&sc->sc_bus); 3464 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3465 3466 #ifdef DIAGNOSTIC 3467 exfer->ex_isdone = true; 3468 #endif 3469 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3470 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3471 usb_transfer_complete(xfer); 3472 if (wake) { 3473 cv_broadcast(&xfer->ux_hccv); 3474 } 3475 3476 done: 3477 KASSERT(mutex_owned(&sc->sc_lock)); 3478 return; 3479 } 3480 3481 Static void 3482 ehci_timeout(void *addr) 3483 { 3484 struct usbd_xfer *xfer = addr; 3485 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3486 struct usbd_pipe *pipe = xfer->ux_pipe; 3487 struct usbd_device *dev = pipe->up_dev; 3488 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3489 3490 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3491 3492 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3493 #ifdef EHCI_DEBUG 3494 if (ehcidebug >= 2) 3495 usbd_dump_pipe(pipe); 3496 #endif 3497 3498 if (sc->sc_dying) { 3499 mutex_enter(&sc->sc_lock); 3500 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3501 mutex_exit(&sc->sc_lock); 3502 return; 3503 } 3504 3505 /* Execute the abort in a process context. */ 3506 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3507 USB_TASKQ_MPSAFE); 3508 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3509 } 3510 3511 Static void 3512 ehci_timeout_task(void *addr) 3513 { 3514 struct usbd_xfer *xfer = addr; 3515 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3516 3517 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3518 3519 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3520 3521 mutex_enter(&sc->sc_lock); 3522 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3523 mutex_exit(&sc->sc_lock); 3524 } 3525 3526 /************************/ 3527 3528 Static int 3529 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3530 { 3531 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3532 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3533 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3534 usb_device_request_t *req = &xfer->ux_request; 3535 ehci_soft_qtd_t *setup, *status, *next; 3536 int isread = req->bmRequestType & UT_READ; 3537 int len = xfer->ux_bufsize; 3538 int err; 3539 3540 exfer->ex_type = EX_CTRL; 3541 exfer->ex_status = NULL; 3542 exfer->ex_data = NULL; 3543 exfer->ex_setup = ehci_alloc_sqtd(sc); 3544 if (exfer->ex_setup == NULL) { 3545 err = ENOMEM; 3546 goto bad1; 3547 } 3548 exfer->ex_status = ehci_alloc_sqtd(sc); 3549 if (exfer->ex_status == NULL) { 3550 err = ENOMEM; 3551 goto bad2; 3552 } 3553 setup = exfer->ex_setup; 3554 status = exfer->ex_status; 3555 exfer->ex_nsqtd = 0; 3556 next = status; 3557 /* Set up data transaction */ 3558 if (len != 0) { 3559 ehci_soft_qtd_t *end; 3560 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3561 &exfer->ex_data, &end); 3562 if (err) 3563 goto bad3; 3564 next = exfer->ex_data; 3565 } 3566 3567 /* Clear toggle */ 3568 setup->qtd.qtd_status = htole32( 3569 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3570 EHCI_QTD_SET_TOGGLE(0) | 3571 EHCI_QTD_SET_BYTES(sizeof(*req)) 3572 ); 3573 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3574 setup->qtd.qtd_buffer_hi[0] = 0; 3575 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3576 setup->nextqtd = next; 3577 setup->xfer = xfer; 3578 setup->tdlen = setup->len = sizeof(*req); 3579 3580 status->qtd.qtd_status = htole32( 3581 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3582 EHCI_QTD_SET_TOGGLE(1) | 3583 EHCI_QTD_IOC 3584 ); 3585 status->qtd.qtd_buffer[0] = 0; 3586 status->qtd.qtd_buffer_hi[0] = 0; 3587 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3588 status->nextqtd = NULL; 3589 status->xfer = xfer; 3590 status->tdlen = status->len = 0; 3591 3592 return 0; 3593 bad3: 3594 ehci_free_sqtd(sc, exfer->ex_status); 3595 bad2: 3596 ehci_free_sqtd(sc, exfer->ex_setup); 3597 bad1: 3598 return err; 3599 } 3600 3601 Static void 3602 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3603 { 3604 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3605 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3606 3607 KASSERT(ex->ex_type == EX_CTRL); 3608 3609 ehci_free_sqtd(sc, ex->ex_setup); 3610 ehci_free_sqtd(sc, ex->ex_status); 3611 ehci_free_sqtds(sc, ex); 3612 if (ex->ex_nsqtd) 3613 kmem_free(ex->ex_sqtds, 3614 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3615 } 3616 3617 Static usbd_status 3618 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3619 { 3620 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3621 usbd_status err; 3622 3623 /* Insert last in queue. */ 3624 mutex_enter(&sc->sc_lock); 3625 err = usb_insert_transfer(xfer); 3626 mutex_exit(&sc->sc_lock); 3627 if (err) 3628 return err; 3629 3630 /* Pipe isn't running, start first */ 3631 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3632 } 3633 3634 Static usbd_status 3635 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3636 { 3637 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3638 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3639 usb_device_request_t *req = &xfer->ux_request; 3640 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3641 ehci_soft_qtd_t *setup, *status, *next; 3642 ehci_soft_qh_t *sqh; 3643 3644 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3645 3646 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3647 3648 if (sc->sc_dying) 3649 return USBD_IOERROR; 3650 3651 const int isread = req->bmRequestType & UT_READ; 3652 const int len = UGETW(req->wLength); 3653 3654 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3655 "wValue=0x%04x, wIndex=0x%04x", 3656 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3657 UGETW(req->wIndex)); 3658 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3659 len, epipe->pipe.up_dev->ud_addr, 3660 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3661 3662 sqh = epipe->sqh; 3663 3664 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3665 "address QH %" __PRIuBIT " pipe %d\n", 3666 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3667 epipe->pipe.up_dev->ud_addr); 3668 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3669 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3670 "MPS QH %" __PRIuBIT " pipe %d\n", 3671 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3672 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3673 3674 setup = exfer->ex_setup; 3675 status = exfer->ex_status; 3676 3677 USBHIST_LOG(ehcidebug, "setup %p status %p data %p", 3678 setup, status, exfer->ex_data, 0); 3679 KASSERTMSG(setup != NULL && status != NULL, 3680 "Failed memory allocation, setup %p status %p", 3681 setup, status); 3682 3683 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3684 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3685 3686 /* Clear toggle */ 3687 setup->qtd.qtd_status &= ~htole32( 3688 EHCI_QTD_STATUS_MASK | 3689 EHCI_QTD_BYTES_MASK | 3690 EHCI_QTD_TOGGLE_MASK | 3691 EHCI_QTD_CERR_MASK 3692 ); 3693 setup->qtd.qtd_status |= htole32( 3694 EHCI_QTD_ACTIVE | 3695 EHCI_QTD_SET_CERR(3) | 3696 EHCI_QTD_SET_TOGGLE(0) | 3697 EHCI_QTD_SET_BYTES(sizeof(*req)) 3698 ); 3699 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3700 setup->qtd.qtd_buffer_hi[0] = 0; 3701 3702 next = status; 3703 status->qtd.qtd_status &= ~htole32( 3704 EHCI_QTD_STATUS_MASK | 3705 EHCI_QTD_PID_MASK | 3706 EHCI_QTD_BYTES_MASK | 3707 EHCI_QTD_TOGGLE_MASK | 3708 EHCI_QTD_CERR_MASK 3709 ); 3710 status->qtd.qtd_status |= htole32( 3711 EHCI_QTD_ACTIVE | 3712 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3713 EHCI_QTD_SET_CERR(3) | 3714 EHCI_QTD_SET_TOGGLE(1) | 3715 EHCI_QTD_SET_BYTES(0) | 3716 EHCI_QTD_IOC 3717 ); 3718 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3719 3720 KASSERT(exfer->ex_isdone); 3721 #ifdef DIAGNOSTIC 3722 exfer->ex_isdone = false; 3723 #endif 3724 3725 /* Set up data transaction */ 3726 if (len != 0) { 3727 ehci_soft_qtd_t *end; 3728 3729 /* Start toggle at 1. */ 3730 int toggle = 1; 3731 next = exfer->ex_data; 3732 KASSERTMSG(next != NULL, "Failed memory allocation"); 3733 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3734 end->nextqtd = status; 3735 end->qtd.qtd_next = end->qtd.qtd_altnext = 3736 htole32(status->physaddr); 3737 3738 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3739 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3740 3741 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3742 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3743 } 3744 3745 setup->nextqtd = next; 3746 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3747 3748 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3749 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3750 3751 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3753 3754 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3755 3756 #ifdef EHCI_DEBUG 3757 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3758 ehci_dump_sqh(sqh); 3759 ehci_dump_sqtds(setup); 3760 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3761 #endif 3762 3763 mutex_enter(&sc->sc_lock); 3764 3765 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3766 ehci_set_qh_qtd(sqh, setup); 3767 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3768 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3769 ehci_timeout, xfer); 3770 } 3771 ehci_add_intr_list(sc, exfer); 3772 xfer->ux_status = USBD_IN_PROGRESS; 3773 mutex_exit(&sc->sc_lock); 3774 3775 #if 0 3776 #ifdef EHCI_DEBUG 3777 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3778 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3779 // delay(10000); 3780 ehci_dump_regs(sc); 3781 ehci_dump_sqh(sc->sc_async_head); 3782 ehci_dump_sqh(sqh); 3783 ehci_dump_sqtds(setup); 3784 #endif 3785 #endif 3786 3787 if (sc->sc_bus.ub_usepolling) 3788 ehci_waitintr(sc, xfer); 3789 3790 return USBD_IN_PROGRESS; 3791 } 3792 3793 Static void 3794 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3795 { 3796 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3797 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3798 usb_device_request_t *req = &xfer->ux_request; 3799 int len = UGETW(req->wLength); 3800 int rd = req->bmRequestType & UT_READ; 3801 3802 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3803 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3804 3805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3806 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3807 3808 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3809 BUS_DMASYNC_POSTWRITE); 3810 if (len) 3811 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3812 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3813 3814 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3815 } 3816 3817 /* Abort a device control request. */ 3818 Static void 3819 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3820 { 3821 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3822 3823 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3824 ehci_abort_xfer(xfer, USBD_CANCELLED); 3825 } 3826 3827 /* Close a device control pipe. */ 3828 Static void 3829 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3830 { 3831 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3832 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3833 3834 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3835 3836 KASSERT(mutex_owned(&sc->sc_lock)); 3837 3838 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3839 3840 ehci_close_pipe(pipe, sc->sc_async_head); 3841 } 3842 3843 /* 3844 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3845 * qTD status, or miss signalling occasionally under heavy load. If the host 3846 * machine is too fast, we we can miss transaction completion - when we scan 3847 * the active list the transaction still seems to be active. This generally 3848 * exhibits itself as a umass stall that never recovers. 3849 * 3850 * We work around this behaviour by setting up this callback after any softintr 3851 * that completes with transactions still pending, giving us another chance to 3852 * check for completion after the writeback has taken place. 3853 */ 3854 Static void 3855 ehci_intrlist_timeout(void *arg) 3856 { 3857 ehci_softc_t *sc = arg; 3858 3859 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3860 3861 usb_schedsoftintr(&sc->sc_bus); 3862 } 3863 3864 /************************/ 3865 3866 Static int 3867 ehci_device_bulk_init(struct usbd_xfer *xfer) 3868 { 3869 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3870 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3871 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3872 int endpt = ed->bEndpointAddress; 3873 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3874 int len = xfer->ux_bufsize; 3875 int err = 0; 3876 3877 exfer->ex_type = EX_BULK; 3878 exfer->ex_nsqtd = 0; 3879 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3880 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 3881 3882 return err; 3883 } 3884 3885 Static void 3886 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3887 { 3888 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3889 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3890 3891 KASSERT(ex->ex_type == EX_BULK); 3892 3893 ehci_free_sqtds(sc, ex); 3894 if (ex->ex_nsqtd) 3895 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3896 } 3897 3898 Static usbd_status 3899 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3900 { 3901 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3902 usbd_status err; 3903 3904 /* Insert last in queue. */ 3905 mutex_enter(&sc->sc_lock); 3906 err = usb_insert_transfer(xfer); 3907 mutex_exit(&sc->sc_lock); 3908 if (err) 3909 return err; 3910 3911 /* Pipe isn't running, start first */ 3912 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3913 } 3914 3915 Static usbd_status 3916 ehci_device_bulk_start(struct usbd_xfer *xfer) 3917 { 3918 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3919 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3920 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3921 ehci_soft_qh_t *sqh; 3922 ehci_soft_qtd_t *end; 3923 int len, isread, endpt; 3924 3925 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3926 3927 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3928 xfer, xfer->ux_length, xfer->ux_flags, 0); 3929 3930 if (sc->sc_dying) 3931 return USBD_IOERROR; 3932 3933 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3934 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3935 3936 len = xfer->ux_length; 3937 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3938 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3939 sqh = epipe->sqh; 3940 3941 KASSERT(exfer->ex_isdone); 3942 #ifdef DIAGNOSTIC 3943 exfer->ex_isdone = false; 3944 #endif 3945 3946 /* Take lock here to protect nexttoggle */ 3947 mutex_enter(&sc->sc_lock); 3948 3949 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3950 3951 exfer->ex_sqtdend = end; 3952 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3953 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3954 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3955 3956 #ifdef EHCI_DEBUG 3957 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3958 ehci_dump_sqh(sqh); 3959 ehci_dump_sqtds(exfer->ex_sqtdstart); 3960 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3961 #endif 3962 3963 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3964 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3965 3966 /* also does usb_syncmem(sqh) */ 3967 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3968 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3969 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3970 ehci_timeout, xfer); 3971 } 3972 ehci_add_intr_list(sc, exfer); 3973 xfer->ux_status = USBD_IN_PROGRESS; 3974 mutex_exit(&sc->sc_lock); 3975 3976 #if 0 3977 #ifdef EHCI_DEBUG 3978 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3979 // delay(10000); 3980 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3981 ehci_dump_regs(sc); 3982 #if 0 3983 printf("async_head:\n"); 3984 ehci_dump_sqh(sc->sc_async_head); 3985 #endif 3986 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3987 ehci_dump_sqh(sqh); 3988 ehci_dump_sqtds(exfer->ex_sqtdstart); 3989 #endif 3990 #endif 3991 3992 if (sc->sc_bus.ub_usepolling) 3993 ehci_waitintr(sc, xfer); 3994 3995 return USBD_IN_PROGRESS; 3996 } 3997 3998 Static void 3999 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4000 { 4001 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4002 4003 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 4004 ehci_abort_xfer(xfer, USBD_CANCELLED); 4005 } 4006 4007 /* 4008 * Close a device bulk pipe. 4009 */ 4010 Static void 4011 ehci_device_bulk_close(struct usbd_pipe *pipe) 4012 { 4013 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4014 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4015 4016 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4017 4018 KASSERT(mutex_owned(&sc->sc_lock)); 4019 4020 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 4021 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4022 ehci_close_pipe(pipe, sc->sc_async_head); 4023 } 4024 4025 Static void 4026 ehci_device_bulk_done(struct usbd_xfer *xfer) 4027 { 4028 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4029 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4030 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4031 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4032 4033 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4034 4035 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4036 0, 0); 4037 4038 KASSERT(mutex_owned(&sc->sc_lock)); 4039 4040 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4041 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4042 4043 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 4044 } 4045 4046 /************************/ 4047 4048 Static usbd_status 4049 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4050 { 4051 struct ehci_soft_islot *isp; 4052 int islot, lev; 4053 4054 /* Find a poll rate that is large enough. */ 4055 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4056 if (EHCI_ILEV_IVAL(lev) <= ival) 4057 break; 4058 4059 /* Pick an interrupt slot at the right level. */ 4060 /* XXX could do better than picking at random */ 4061 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4062 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4063 4064 sqh->islot = islot; 4065 isp = &sc->sc_islots[islot]; 4066 mutex_enter(&sc->sc_lock); 4067 ehci_add_qh(sc, sqh, isp->sqh); 4068 mutex_exit(&sc->sc_lock); 4069 4070 return USBD_NORMAL_COMPLETION; 4071 } 4072 4073 4074 Static int 4075 ehci_device_intr_init(struct usbd_xfer *xfer) 4076 { 4077 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4078 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4079 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4080 int endpt = ed->bEndpointAddress; 4081 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4082 int len = xfer->ux_bufsize; 4083 int err; 4084 4085 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4086 4087 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4088 xfer->ux_flags, 0); 4089 4090 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4091 KASSERT(len != 0); 4092 4093 exfer->ex_type = EX_INTR; 4094 exfer->ex_nsqtd = 0; 4095 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4096 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 4097 4098 return err; 4099 } 4100 4101 Static void 4102 ehci_device_intr_fini(struct usbd_xfer *xfer) 4103 { 4104 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4105 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4106 4107 KASSERT(ex->ex_type == EX_INTR); 4108 4109 ehci_free_sqtds(sc, ex); 4110 if (ex->ex_nsqtd) 4111 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4112 } 4113 4114 Static usbd_status 4115 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4116 { 4117 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4118 usbd_status err; 4119 4120 /* Insert last in queue. */ 4121 mutex_enter(&sc->sc_lock); 4122 err = usb_insert_transfer(xfer); 4123 mutex_exit(&sc->sc_lock); 4124 if (err) 4125 return err; 4126 4127 /* 4128 * Pipe isn't running (otherwise err would be USBD_INPROG), 4129 * so start it first. 4130 */ 4131 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4132 } 4133 4134 Static usbd_status 4135 ehci_device_intr_start(struct usbd_xfer *xfer) 4136 { 4137 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4138 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4139 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4140 ehci_soft_qtd_t *end; 4141 ehci_soft_qh_t *sqh; 4142 int len, isread, endpt; 4143 4144 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4145 4146 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4147 xfer->ux_flags, 0); 4148 4149 if (sc->sc_dying) 4150 return USBD_IOERROR; 4151 4152 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4153 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4154 4155 len = xfer->ux_length; 4156 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4157 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4158 sqh = epipe->sqh; 4159 4160 KASSERT(exfer->ex_isdone); 4161 #ifdef DIAGNOSTIC 4162 exfer->ex_isdone = false; 4163 #endif 4164 4165 /* Take lock to protect nexttoggle */ 4166 mutex_enter(&sc->sc_lock); 4167 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4168 4169 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4170 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4171 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4172 exfer->ex_sqtdend = end; 4173 4174 #ifdef EHCI_DEBUG 4175 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 4176 ehci_dump_sqh(sqh); 4177 ehci_dump_sqtds(exfer->ex_sqtdstart); 4178 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 4179 #endif 4180 4181 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4182 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4183 4184 /* also does usb_syncmem(sqh) */ 4185 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4186 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4187 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4188 ehci_timeout, xfer); 4189 } 4190 ehci_add_intr_list(sc, exfer); 4191 xfer->ux_status = USBD_IN_PROGRESS; 4192 mutex_exit(&sc->sc_lock); 4193 4194 #if 0 4195 #ifdef EHCI_DEBUG 4196 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4197 // delay(10000); 4198 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4199 ehci_dump_regs(sc); 4200 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4201 ehci_dump_sqh(sqh); 4202 ehci_dump_sqtds(exfer->ex_sqtdstart); 4203 #endif 4204 #endif 4205 4206 if (sc->sc_bus.ub_usepolling) 4207 ehci_waitintr(sc, xfer); 4208 4209 return USBD_IN_PROGRESS; 4210 } 4211 4212 Static void 4213 ehci_device_intr_abort(struct usbd_xfer *xfer) 4214 { 4215 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4216 4217 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4218 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4219 4220 /* 4221 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4222 * async doorbell. That's dependent on the async list, wheras 4223 * intr xfers are periodic, should not use this? 4224 */ 4225 ehci_abort_xfer(xfer, USBD_CANCELLED); 4226 } 4227 4228 Static void 4229 ehci_device_intr_close(struct usbd_pipe *pipe) 4230 { 4231 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4232 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4233 struct ehci_soft_islot *isp; 4234 4235 KASSERT(mutex_owned(&sc->sc_lock)); 4236 4237 isp = &sc->sc_islots[epipe->sqh->islot]; 4238 ehci_close_pipe(pipe, isp->sqh); 4239 } 4240 4241 Static void 4242 ehci_device_intr_done(struct usbd_xfer *xfer) 4243 { 4244 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4245 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4246 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4247 ehci_soft_qh_t *sqh; 4248 int len, isread, endpt; 4249 4250 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4251 4252 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4253 0, 0); 4254 4255 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4256 4257 if (xfer->ux_pipe->up_repeat) { 4258 4259 KASSERT(exfer->ex_isdone); 4260 #ifdef DIAGNOSTIC 4261 exfer->ex_isdone = false; 4262 #endif 4263 4264 len = xfer->ux_length; 4265 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4266 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4267 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4268 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4269 sqh = epipe->sqh; 4270 4271 ehci_soft_qtd_t *end; 4272 ehci_reset_sqtd_chain(sc, xfer, len, isread, 4273 &epipe->nexttoggle, &end); 4274 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4275 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4276 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4277 4278 exfer->ex_sqtdend = end; 4279 4280 /* also does usb_syncmem(sqh) */ 4281 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4282 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4283 callout_reset(&xfer->ux_callout, 4284 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4285 } 4286 ehci_add_intr_list(sc, exfer); 4287 xfer->ux_status = USBD_IN_PROGRESS; 4288 } else { 4289 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4290 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4291 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4292 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4293 } 4294 } 4295 4296 /************************/ 4297 Static int 4298 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4299 { 4300 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4301 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4302 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4303 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4304 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4305 int i, k, frames; 4306 u_int huba, dir; 4307 int err; 4308 4309 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4310 4311 start = NULL; 4312 sitd = NULL; 4313 4314 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", xfer, xfer->ux_length, 4315 xfer->ux_flags, 0); 4316 4317 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4318 KASSERT(xfer->ux_nframes != 0); 4319 KASSERT(exfer->ex_isdone); 4320 4321 exfer->ex_type = EX_FS_ISOC; 4322 /* 4323 * Step 1: Allocate and initialize sitds. 4324 */ 4325 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4326 if (i > 16 || i == 0) { 4327 /* Spec page 271 says intervals > 16 are invalid */ 4328 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4329 4330 return EINVAL; 4331 } 4332 4333 frames = xfer->ux_nframes; 4334 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4335 sitd = ehci_alloc_sitd(sc); 4336 if (sitd == NULL) { 4337 err = ENOMEM; 4338 goto fail; 4339 } 4340 4341 if (prev) 4342 prev->xfer_next = sitd; 4343 else 4344 start = sitd; 4345 4346 huba = dev->ud_myhsport->up_parent->ud_addr; 4347 4348 #if 0 4349 if (sc->sc_flags & EHCIF_FREESCALE) { 4350 // Set hub address to 0 if embedded TT is used. 4351 if (huba == sc->sc_addr) 4352 huba = 0; 4353 } 4354 #endif 4355 4356 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4357 dir = UE_GET_DIR(k) ? 1 : 0; 4358 sitd->sitd.sitd_endp = 4359 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4360 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4361 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4362 EHCI_SITD_SET_HUBA(huba) | 4363 EHCI_SITD_SET_DIR(dir)); 4364 4365 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4366 } /* End of frame */ 4367 4368 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4369 4370 stop = sitd; 4371 stop->xfer_next = NULL; 4372 exfer->ex_sitdstart = start; 4373 exfer->ex_sitdend = stop; 4374 4375 return 0; 4376 4377 fail: 4378 mutex_enter(&sc->sc_lock); 4379 ehci_soft_sitd_t *next; 4380 for (sitd = start; sitd; sitd = next) { 4381 next = sitd->xfer_next; 4382 ehci_free_sitd_locked(sc, sitd); 4383 } 4384 mutex_exit(&sc->sc_lock); 4385 4386 return err; 4387 } 4388 4389 Static void 4390 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4391 { 4392 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4393 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4394 4395 KASSERT(ex->ex_type == EX_FS_ISOC); 4396 4397 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4398 } 4399 4400 Static usbd_status 4401 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4402 { 4403 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4404 usbd_status err; 4405 4406 mutex_enter(&sc->sc_lock); 4407 err = usb_insert_transfer(xfer); 4408 mutex_exit(&sc->sc_lock); 4409 4410 if (err && err != USBD_IN_PROGRESS) 4411 return err; 4412 4413 return ehci_device_fs_isoc_start(xfer); 4414 } 4415 4416 Static usbd_status 4417 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4418 { 4419 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4420 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4421 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4422 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4423 ehci_soft_sitd_t *sitd; 4424 usb_dma_t *dma_buf; 4425 int i, j, k, frames; 4426 int offs, total_length; 4427 int frindex; 4428 u_int dir; 4429 4430 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4431 4432 sitd = NULL; 4433 total_length = 0; 4434 4435 /* 4436 * To allow continuous transfers, above we start all transfers 4437 * immediately. However, we're still going to get usbd_start_next call 4438 * this when another xfer completes. So, check if this is already 4439 * in progress or not 4440 */ 4441 4442 if (exfer->ex_isrunning) { 4443 return USBD_IN_PROGRESS; 4444 } 4445 4446 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4447 xfer, xfer->ux_length, xfer->ux_flags, 0); 4448 4449 if (sc->sc_dying) 4450 return USBD_IOERROR; 4451 4452 /* 4453 * To avoid complication, don't allow a request right now that'll span 4454 * the entire frame table. To within 4 frames, to allow some leeway 4455 * on either side of where the hc currently is. 4456 */ 4457 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4458 xfer->ux_nframes >= sc->sc_flsize - 4) { 4459 printf("ehci: isoc descriptor requested that spans the entire" 4460 "frametable, too many frames\n"); 4461 return USBD_INVAL; 4462 } 4463 4464 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4465 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4466 KASSERT(exfer->ex_isdone); 4467 #ifdef DIAGNOSTIC 4468 exfer->ex_isdone = false; 4469 #endif 4470 4471 /* 4472 * Step 1: Initialize sitds. 4473 */ 4474 4475 frames = xfer->ux_nframes; 4476 dma_buf = &xfer->ux_dmabuf; 4477 offs = 0; 4478 4479 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4480 i++, sitd = sitd->xfer_next) { 4481 KASSERT(sitd != NULL); 4482 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4483 4484 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4485 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4486 4487 /* Set page0 index and offset - TP and T-offset are set below */ 4488 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4489 4490 total_length += xfer->ux_frlengths[i]; 4491 offs += xfer->ux_frlengths[i]; 4492 4493 sitd->sitd.sitd_buffer[1] = 4494 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4495 4496 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4497 4498 #if 0 4499 if (sc->sc_flags & EHCIF_FREESCALE) { 4500 // Set hub address to 0 if embedded TT is used. 4501 if (huba == sc->sc_addr) 4502 huba = 0; 4503 } 4504 #endif 4505 4506 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4507 dir = UE_GET_DIR(k) ? 1 : 0; 4508 KASSERT(sitd->sitd.sitd_endp == htole32( 4509 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4510 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4511 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4512 EHCI_SITD_SET_HUBA(huba) | 4513 EHCI_SITD_SET_DIR(dir))); 4514 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4515 4516 uint8_t sa = 0; 4517 uint8_t sb = 0; 4518 u_int temp, tlen; 4519 4520 if (dir == 0) { /* OUT */ 4521 temp = 0; 4522 tlen = xfer->ux_frlengths[i]; 4523 if (tlen <= 188) { 4524 temp |= 1; /* T-count = 1, TP = ALL */ 4525 tlen = 1; 4526 } else { 4527 tlen += 187; 4528 tlen /= 188; 4529 temp |= tlen; /* T-count = [1..6] */ 4530 temp |= 8; /* TP = Begin */ 4531 } 4532 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4533 4534 tlen += sa; 4535 4536 if (tlen >= 8) { 4537 sb = 0; 4538 } else { 4539 sb = (1 << tlen); 4540 } 4541 4542 sa = (1 << sa); 4543 sa = (sb - sa) & 0x3F; 4544 sb = 0; 4545 } else { 4546 sb = (-(4 << sa)) & 0xFE; 4547 sa = (1 << sa) & 0x3F; 4548 sa = 0x01; 4549 sb = 0xfc; 4550 } 4551 4552 sitd->sitd.sitd_sched = htole32( 4553 EHCI_SITD_SET_SMASK(sa) | 4554 EHCI_SITD_SET_CMASK(sb) 4555 ); 4556 4557 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4559 } /* End of frame */ 4560 4561 sitd = exfer->ex_sitdend; 4562 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4563 4564 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4565 sizeof(sitd->sitd.sitd_trans), 4566 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4567 4568 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4570 4571 /* 4572 * Part 2: Transfer descriptors have now been set up, now they must 4573 * be scheduled into the periodic frame list. Erk. Not wanting to 4574 * complicate matters, transfer is denied if the transfer spans 4575 * more than the period frame list. 4576 */ 4577 4578 mutex_enter(&sc->sc_lock); 4579 4580 /* Start inserting frames */ 4581 if (epipe->isoc.cur_xfers > 0) { 4582 frindex = epipe->isoc.next_frame; 4583 } else { 4584 frindex = EOREAD4(sc, EHCI_FRINDEX); 4585 frindex = frindex >> 3; /* Erase microframe index */ 4586 frindex += 2; 4587 } 4588 4589 if (frindex >= sc->sc_flsize) 4590 frindex &= (sc->sc_flsize - 1); 4591 4592 /* Whats the frame interval? */ 4593 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4594 4595 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4596 j++, sitd = sitd->xfer_next) { 4597 KASSERT(sitd); 4598 4599 usb_syncmem(&sc->sc_fldma, 4600 sizeof(ehci_link_t) * frindex, 4601 sizeof(ehci_link_t), 4602 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4603 4604 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4605 if (sitd->sitd.sitd_next == 0) 4606 /* 4607 * FIXME: frindex table gets initialized to NULL 4608 * or EHCI_NULL? 4609 */ 4610 sitd->sitd.sitd_next = EHCI_NULL; 4611 4612 usb_syncmem(&sitd->dma, 4613 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4614 sizeof(ehci_sitd_t), 4615 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4616 4617 sc->sc_flist[frindex] = 4618 htole32(EHCI_LINK_SITD | sitd->physaddr); 4619 4620 usb_syncmem(&sc->sc_fldma, 4621 sizeof(ehci_link_t) * frindex, 4622 sizeof(ehci_link_t), 4623 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4624 4625 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4626 sc->sc_softsitds[frindex] = sitd; 4627 if (sitd->frame_list.next != NULL) 4628 sitd->frame_list.next->frame_list.prev = sitd; 4629 sitd->slot = frindex; 4630 sitd->frame_list.prev = NULL; 4631 4632 frindex += i; 4633 if (frindex >= sc->sc_flsize) 4634 frindex -= sc->sc_flsize; 4635 } 4636 4637 epipe->isoc.cur_xfers++; 4638 epipe->isoc.next_frame = frindex; 4639 4640 exfer->ex_isrunning = true; 4641 4642 ehci_add_intr_list(sc, exfer); 4643 xfer->ux_status = USBD_IN_PROGRESS; 4644 4645 mutex_exit(&sc->sc_lock); 4646 4647 if (sc->sc_bus.ub_usepolling) { 4648 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4649 ehci_waitintr(sc, xfer); 4650 } 4651 4652 return USBD_IN_PROGRESS; 4653 } 4654 4655 Static void 4656 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4657 { 4658 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4659 4660 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4661 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4662 } 4663 4664 Static void 4665 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4666 { 4667 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4668 4669 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4670 } 4671 4672 Static void 4673 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4674 { 4675 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4676 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4677 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4678 4679 KASSERT(mutex_owned(&sc->sc_lock)); 4680 4681 epipe->isoc.cur_xfers--; 4682 if (exfer->ex_isrunning) { 4683 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4684 exfer->ex_isrunning = false; 4685 } 4686 4687 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4688 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4689 } 4690 4691 4692 /************************/ 4693 4694 4695 Static int 4696 ehci_device_isoc_init(struct usbd_xfer *xfer) 4697 { 4698 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4699 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4700 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4701 ehci_soft_itd_t *itd, *prev, *start, *stop; 4702 int i, j, k; 4703 int frames, ufrperframe; 4704 int err; 4705 4706 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4707 4708 start = NULL; 4709 prev = NULL; 4710 itd = NULL; 4711 4712 KASSERT(xfer->ux_nframes != 0); 4713 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4714 KASSERT(exfer->ex_isdone); 4715 4716 exfer->ex_type = EX_ISOC; 4717 4718 /* 4719 * Step 1: Allocate and initialize itds, how many do we need? 4720 * One per transfer if interval >= 8 microframes, less if we use 4721 * multiple microframes per frame. 4722 */ 4723 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4724 if (i > 16 || i == 0) { 4725 /* Spec page 271 says intervals > 16 are invalid */ 4726 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4727 return USBD_INVAL; 4728 } 4729 4730 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4731 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4732 4733 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4734 itd = ehci_alloc_itd(sc); 4735 if (itd == NULL) { 4736 err = ENOMEM; 4737 goto fail; 4738 } 4739 4740 if (prev != NULL) { 4741 /* Maybe not as it's updated by the scheduling? */ 4742 prev->itd.itd_next = 4743 htole32(itd->physaddr | EHCI_LINK_ITD); 4744 4745 prev->xfer_next = itd; 4746 } else { 4747 start = itd; 4748 } 4749 4750 /* 4751 * Other special values 4752 */ 4753 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4754 itd->itd.itd_bufr[0] = htole32( 4755 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4756 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4757 4758 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4759 ? 1 : 0; 4760 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4761 itd->itd.itd_bufr[1] |= htole32( 4762 EHCI_ITD_SET_DIR(k) | 4763 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4764 4765 /* FIXME: handle invalid trans - should be done in openpipe */ 4766 itd->itd.itd_bufr[2] |= 4767 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4768 } /* End of frame */ 4769 4770 stop = itd; 4771 stop->xfer_next = NULL; 4772 4773 exfer->ex_itdstart = start; 4774 exfer->ex_itdend = stop; 4775 4776 return 0; 4777 fail: 4778 mutex_enter(&sc->sc_lock); 4779 ehci_soft_itd_t *next; 4780 for (itd = start; itd; itd = next) { 4781 next = itd->xfer_next; 4782 ehci_free_itd_locked(sc, itd); 4783 } 4784 mutex_exit(&sc->sc_lock); 4785 4786 return err; 4787 4788 } 4789 4790 Static void 4791 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4792 { 4793 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4794 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4795 4796 KASSERT(ex->ex_type == EX_ISOC); 4797 4798 ehci_free_itd_chain(sc, ex->ex_itdstart); 4799 } 4800 4801 Static usbd_status 4802 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4803 { 4804 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4805 usbd_status err; 4806 4807 mutex_enter(&sc->sc_lock); 4808 err = usb_insert_transfer(xfer); 4809 mutex_exit(&sc->sc_lock); 4810 if (err && err != USBD_IN_PROGRESS) 4811 return err; 4812 4813 return ehci_device_isoc_start(xfer); 4814 } 4815 4816 Static usbd_status 4817 ehci_device_isoc_start(struct usbd_xfer *xfer) 4818 { 4819 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4820 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4821 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4822 ehci_soft_itd_t *itd, *prev; 4823 usb_dma_t *dma_buf; 4824 int i, j; 4825 int frames, uframes, ufrperframe; 4826 int trans_count, offs, total_length; 4827 int frindex; 4828 4829 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4830 4831 prev = NULL; 4832 itd = NULL; 4833 trans_count = 0; 4834 total_length = 0; 4835 4836 /* 4837 * To allow continuous transfers, above we start all transfers 4838 * immediately. However, we're still going to get usbd_start_next call 4839 * this when another xfer completes. So, check if this is already 4840 * in progress or not 4841 */ 4842 4843 if (exfer->ex_isrunning) { 4844 return USBD_IN_PROGRESS; 4845 } 4846 4847 USBHIST_LOG(ehcidebug, "xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4848 4849 if (sc->sc_dying) 4850 return USBD_IOERROR; 4851 4852 /* 4853 * To avoid complication, don't allow a request right now that'll span 4854 * the entire frame table. To within 4 frames, to allow some leeway 4855 * on either side of where the hc currently is. 4856 */ 4857 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4858 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4859 USBHIST_LOG(ehcidebug, 4860 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4861 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4862 return USBD_INVAL; 4863 } 4864 4865 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4866 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4867 KASSERT(exfer->ex_isdone); 4868 #ifdef DIAGNOSTIC 4869 exfer->ex_isdone = false; 4870 #endif 4871 4872 /* 4873 * Step 1: Re-Initialize itds 4874 */ 4875 4876 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4877 if (i > 16 || i == 0) { 4878 /* Spec page 271 says intervals > 16 are invalid */ 4879 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4880 return USBD_INVAL; 4881 } 4882 4883 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4884 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4885 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4886 4887 if (frames == 0) { 4888 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4889 return USBD_INVAL; 4890 } 4891 4892 dma_buf = &xfer->ux_dmabuf; 4893 offs = 0; 4894 4895 itd = exfer->ex_itdstart; 4896 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4897 int froffs = offs; 4898 4899 if (prev != NULL) { 4900 prev->itd.itd_next = 4901 htole32(itd->physaddr | EHCI_LINK_ITD); 4902 usb_syncmem(&prev->dma, 4903 prev->offs + offsetof(ehci_itd_t, itd_next), 4904 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4905 prev->xfer_next = itd; 4906 } 4907 4908 /* 4909 * Step 1.5, initialize uframes 4910 */ 4911 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4912 /* Calculate which page in the list this starts in */ 4913 int addr = DMAADDR(dma_buf, froffs); 4914 addr = EHCI_PAGE_OFFSET(addr); 4915 addr += (offs - froffs); 4916 addr = EHCI_PAGE(addr); 4917 addr /= EHCI_PAGE_SIZE; 4918 4919 /* 4920 * This gets the initial offset into the first page, 4921 * looks how far further along the current uframe 4922 * offset is. Works out how many pages that is. 4923 */ 4924 4925 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4926 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4927 EHCI_ITD_SET_PG(addr) | 4928 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4929 4930 total_length += xfer->ux_frlengths[trans_count]; 4931 offs += xfer->ux_frlengths[trans_count]; 4932 trans_count++; 4933 4934 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4935 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4936 break; 4937 } 4938 } 4939 4940 /* 4941 * Step 1.75, set buffer pointers. To simplify matters, all 4942 * pointers are filled out for the next 7 hardware pages in 4943 * the dma block, so no need to worry what pages to cover 4944 * and what to not. 4945 */ 4946 4947 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4948 /* 4949 * Don't try to lookup a page that's past the end 4950 * of buffer 4951 */ 4952 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4953 if (page_offs >= dma_buf->udma_block->size) 4954 break; 4955 4956 uint64_t page = DMAADDR(dma_buf, page_offs); 4957 page = EHCI_PAGE(page); 4958 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4959 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4960 } 4961 /* 4962 * Other special values 4963 */ 4964 4965 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4966 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4967 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4968 4969 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4970 ? 1 : 0; 4971 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4972 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4973 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4974 4975 /* FIXME: handle invalid trans */ 4976 itd->itd.itd_bufr[2] |= 4977 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4978 4979 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4980 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4981 4982 prev = itd; 4983 } /* End of frame */ 4984 4985 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4986 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4987 4988 /* 4989 * Part 2: Transfer descriptors have now been set up, now they must 4990 * be scheduled into the period frame list. Erk. Not wanting to 4991 * complicate matters, transfer is denied if the transfer spans 4992 * more than the period frame list. 4993 */ 4994 4995 mutex_enter(&sc->sc_lock); 4996 4997 /* Start inserting frames */ 4998 if (epipe->isoc.cur_xfers > 0) { 4999 frindex = epipe->isoc.next_frame; 5000 } else { 5001 frindex = EOREAD4(sc, EHCI_FRINDEX); 5002 frindex = frindex >> 3; /* Erase microframe index */ 5003 frindex += 2; 5004 } 5005 5006 if (frindex >= sc->sc_flsize) 5007 frindex &= (sc->sc_flsize - 1); 5008 5009 /* What's the frame interval? */ 5010 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 5011 if (i / USB_UFRAMES_PER_FRAME == 0) 5012 i = 1; 5013 else 5014 i /= USB_UFRAMES_PER_FRAME; 5015 5016 itd = exfer->ex_itdstart; 5017 for (j = 0; j < frames; j++) { 5018 KASSERTMSG(itd != NULL, "frame %d\n", j); 5019 5020 usb_syncmem(&sc->sc_fldma, 5021 sizeof(ehci_link_t) * frindex, 5022 sizeof(ehci_link_t), 5023 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5024 5025 itd->itd.itd_next = sc->sc_flist[frindex]; 5026 if (itd->itd.itd_next == 0) 5027 /* 5028 * FIXME: frindex table gets initialized to NULL 5029 * or EHCI_NULL? 5030 */ 5031 itd->itd.itd_next = EHCI_NULL; 5032 5033 usb_syncmem(&itd->dma, 5034 itd->offs + offsetof(ehci_itd_t, itd_next), 5035 sizeof(itd->itd.itd_next), 5036 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5037 5038 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 5039 5040 usb_syncmem(&sc->sc_fldma, 5041 sizeof(ehci_link_t) * frindex, 5042 sizeof(ehci_link_t), 5043 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5044 5045 itd->frame_list.next = sc->sc_softitds[frindex]; 5046 sc->sc_softitds[frindex] = itd; 5047 if (itd->frame_list.next != NULL) 5048 itd->frame_list.next->frame_list.prev = itd; 5049 itd->slot = frindex; 5050 itd->frame_list.prev = NULL; 5051 5052 frindex += i; 5053 if (frindex >= sc->sc_flsize) 5054 frindex -= sc->sc_flsize; 5055 5056 itd = itd->xfer_next; 5057 } 5058 5059 epipe->isoc.cur_xfers++; 5060 epipe->isoc.next_frame = frindex; 5061 5062 exfer->ex_isrunning = true; 5063 5064 ehci_add_intr_list(sc, exfer); 5065 xfer->ux_status = USBD_IN_PROGRESS; 5066 5067 mutex_exit(&sc->sc_lock); 5068 5069 if (sc->sc_bus.ub_usepolling) { 5070 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 5071 ehci_waitintr(sc, xfer); 5072 } 5073 5074 return USBD_IN_PROGRESS; 5075 } 5076 5077 Static void 5078 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5079 { 5080 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5081 5082 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 5083 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5084 } 5085 5086 Static void 5087 ehci_device_isoc_close(struct usbd_pipe *pipe) 5088 { 5089 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5090 5091 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 5092 } 5093 5094 Static void 5095 ehci_device_isoc_done(struct usbd_xfer *xfer) 5096 { 5097 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5098 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5099 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5100 5101 KASSERT(mutex_owned(&sc->sc_lock)); 5102 5103 epipe->isoc.cur_xfers--; 5104 if (exfer->ex_isrunning) { 5105 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5106 exfer->ex_isrunning = false; 5107 } 5108 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5109 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5110 } 5111
Indexes created Wed Oct 01 19:09:53 GMT 2025