ehci.c revision 1.234.2.87
1 /* $NetBSD: ehci.c,v 1.234.2.87 2016/02/19 16:23:15 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.87 2016/02/19 16:23:15 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 /* Control pipe */ 136 struct { 137 usb_dma_t reqdma; 138 } ctrl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Iso pipe */ 144 struct { 145 u_int next_frame; 146 u_int cur_xfers; 147 } isoc; 148 }; 149 }; 150 151 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 152 153 Static usbd_status ehci_open(struct usbd_pipe *); 154 Static void ehci_poll(struct usbd_bus *); 155 Static void ehci_softintr(void *); 156 Static int ehci_intr1(ehci_softc_t *); 157 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 158 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 159 ex_completeq_t *); 160 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 161 ex_completeq_t *); 162 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 165 Static void ehci_timeout(void *); 166 Static void ehci_timeout_task(void *); 167 Static void ehci_intrlist_timeout(void *); 168 Static void ehci_doorbell(void *); 169 Static void ehci_pcd(void *); 170 171 Static struct usbd_xfer * 172 ehci_allocx(struct usbd_bus *, unsigned int); 173 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 174 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 180 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 181 Static void ehci_root_intr_abort(struct usbd_xfer *); 182 Static void ehci_root_intr_close(struct usbd_pipe *); 183 Static void ehci_root_intr_done(struct usbd_xfer *); 184 185 Static int ehci_device_ctrl_init(struct usbd_xfer *); 186 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 187 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 188 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 189 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 190 Static void ehci_device_ctrl_close(struct usbd_pipe *); 191 Static void ehci_device_ctrl_done(struct usbd_xfer *); 192 193 Static int ehci_device_bulk_init(struct usbd_xfer *); 194 Static void ehci_device_bulk_fini(struct usbd_xfer *); 195 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 196 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 197 Static void ehci_device_bulk_abort(struct usbd_xfer *); 198 Static void ehci_device_bulk_close(struct usbd_pipe *); 199 Static void ehci_device_bulk_done(struct usbd_xfer *); 200 201 Static int ehci_device_intr_init(struct usbd_xfer *); 202 Static void ehci_device_intr_fini(struct usbd_xfer *); 203 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 204 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 205 Static void ehci_device_intr_abort(struct usbd_xfer *); 206 Static void ehci_device_intr_close(struct usbd_pipe *); 207 Static void ehci_device_intr_done(struct usbd_xfer *); 208 209 Static int ehci_device_isoc_init(struct usbd_xfer *); 210 Static void ehci_device_isoc_fini(struct usbd_xfer *); 211 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 212 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 213 Static void ehci_device_isoc_abort(struct usbd_xfer *); 214 Static void ehci_device_isoc_close(struct usbd_pipe *); 215 Static void ehci_device_isoc_done(struct usbd_xfer *); 216 217 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 218 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 219 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 220 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 223 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 224 225 Static void ehci_device_clear_toggle(struct usbd_pipe *); 226 Static void ehci_noop(struct usbd_pipe *); 227 228 Static void ehci_disown(ehci_softc_t *, int, int); 229 230 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 231 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 232 233 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 234 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 235 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 236 int, int, ehci_soft_qtd_t **, ehci_soft_qtd_t **); 237 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 238 239 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 240 int, int, int *, ehci_soft_qtd_t **); 241 242 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 243 Static ehci_soft_sitd_t * 244 ehci_alloc_sitd(ehci_softc_t *); 245 246 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 247 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 248 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 249 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 250 251 static inline void 252 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 253 { 254 255 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 256 } 257 258 static inline void 259 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 260 { 261 262 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 263 } 264 265 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 266 267 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 268 int); 269 270 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 271 ehci_soft_qh_t *); 272 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 273 ehci_soft_qh_t *); 274 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 275 Static void ehci_sync_hc(ehci_softc_t *); 276 277 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 278 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 279 280 #ifdef EHCI_DEBUG 281 Static ehci_softc_t *theehci; 282 void ehci_dump(void); 283 #endif 284 285 #ifdef EHCI_DEBUG 286 Static void ehci_dump_regs(ehci_softc_t *); 287 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 288 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 289 Static void ehci_dump_qtd(ehci_qtd_t *); 290 Static void ehci_dump_sqh(ehci_soft_qh_t *); 291 Static void ehci_dump_sitd(struct ehci_soft_itd *); 292 Static void ehci_dump_itds(ehci_soft_itd_t *); 293 Static void ehci_dump_itd(struct ehci_soft_itd *); 294 Static void ehci_dump_exfer(struct ehci_xfer *); 295 #endif 296 297 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 298 299 static inline void 300 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 301 { 302 303 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 304 } 305 306 static inline void 307 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 308 { 309 310 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 311 } 312 313 Static const struct usbd_bus_methods ehci_bus_methods = { 314 .ubm_open = ehci_open, 315 .ubm_softint = ehci_softintr, 316 .ubm_dopoll = ehci_poll, 317 .ubm_allocx = ehci_allocx, 318 .ubm_freex = ehci_freex, 319 .ubm_getlock = ehci_get_lock, 320 .ubm_rhctrl = ehci_roothub_ctrl, 321 }; 322 323 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 324 .upm_transfer = ehci_root_intr_transfer, 325 .upm_start = ehci_root_intr_start, 326 .upm_abort = ehci_root_intr_abort, 327 .upm_close = ehci_root_intr_close, 328 .upm_cleartoggle = ehci_noop, 329 .upm_done = ehci_root_intr_done, 330 }; 331 332 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 333 .upm_init = ehci_device_ctrl_init, 334 .upm_fini = ehci_device_ctrl_fini, 335 .upm_transfer = ehci_device_ctrl_transfer, 336 .upm_start = ehci_device_ctrl_start, 337 .upm_abort = ehci_device_ctrl_abort, 338 .upm_close = ehci_device_ctrl_close, 339 .upm_cleartoggle = ehci_noop, 340 .upm_done = ehci_device_ctrl_done, 341 }; 342 343 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 344 .upm_init = ehci_device_intr_init, 345 .upm_fini = ehci_device_intr_fini, 346 .upm_transfer = ehci_device_intr_transfer, 347 .upm_start = ehci_device_intr_start, 348 .upm_abort = ehci_device_intr_abort, 349 .upm_close = ehci_device_intr_close, 350 .upm_cleartoggle = ehci_device_clear_toggle, 351 .upm_done = ehci_device_intr_done, 352 }; 353 354 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 355 .upm_init = ehci_device_bulk_init, 356 .upm_fini = ehci_device_bulk_fini, 357 .upm_transfer = ehci_device_bulk_transfer, 358 .upm_start = ehci_device_bulk_start, 359 .upm_abort = ehci_device_bulk_abort, 360 .upm_close = ehci_device_bulk_close, 361 .upm_cleartoggle = ehci_device_clear_toggle, 362 .upm_done = ehci_device_bulk_done, 363 }; 364 365 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 366 .upm_init = ehci_device_isoc_init, 367 .upm_fini = ehci_device_isoc_fini, 368 .upm_transfer = ehci_device_isoc_transfer, 369 .upm_start = ehci_device_isoc_start, 370 .upm_abort = ehci_device_isoc_abort, 371 .upm_close = ehci_device_isoc_close, 372 .upm_cleartoggle = ehci_noop, 373 .upm_done = ehci_device_isoc_done, 374 }; 375 376 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 377 .upm_init = ehci_device_fs_isoc_init, 378 .upm_fini = ehci_device_fs_isoc_fini, 379 .upm_transfer = ehci_device_fs_isoc_transfer, 380 .upm_start = ehci_device_fs_isoc_start, 381 .upm_abort = ehci_device_fs_isoc_abort, 382 .upm_close = ehci_device_fs_isoc_close, 383 .upm_cleartoggle = ehci_noop, 384 .upm_done = ehci_device_fs_isoc_done, 385 }; 386 387 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 388 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 389 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 390 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 391 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 392 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 393 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 394 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 395 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 396 }; 397 398 int 399 ehci_init(ehci_softc_t *sc) 400 { 401 uint32_t vers, sparams, cparams, hcr; 402 u_int i; 403 usbd_status err; 404 ehci_soft_qh_t *sqh; 405 u_int ncomp; 406 407 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 408 #ifdef EHCI_DEBUG 409 theehci = sc; 410 #endif 411 412 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 413 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 414 cv_init(&sc->sc_softwake_cv, "ehciab"); 415 cv_init(&sc->sc_doorbell, "ehcidi"); 416 417 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 418 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 419 420 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 421 ehci_doorbell, sc); 422 KASSERT(sc->sc_doorbell_si != NULL); 423 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 424 ehci_pcd, sc); 425 KASSERT(sc->sc_pcd_si != NULL); 426 427 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 428 429 vers = EREAD2(sc, EHCI_HCIVERSION); 430 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 431 vers >> 8, vers & 0xff); 432 433 sparams = EREAD4(sc, EHCI_HCSPARAMS); 434 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 435 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 436 ncomp = EHCI_HCS_N_CC(sparams); 437 if (ncomp != sc->sc_ncomp) { 438 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 439 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 440 #if NOHCI == 0 || NUHCI == 0 441 aprint_error("%s: ohci or uhci probably not configured\n", 442 device_xname(sc->sc_dev)); 443 #endif 444 if (ncomp < sc->sc_ncomp) 445 sc->sc_ncomp = ncomp; 446 } 447 if (sc->sc_ncomp > 0) { 448 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 449 aprint_normal("%s: companion controller%s, %d port%s each:", 450 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 451 EHCI_HCS_N_PCC(sparams), 452 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 453 for (i = 0; i < sc->sc_ncomp; i++) 454 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 455 aprint_normal("\n"); 456 } 457 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 458 cparams = EREAD4(sc, EHCI_HCCPARAMS); 459 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 460 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 461 462 if (EHCI_HCC_64BIT(cparams)) { 463 /* MUST clear segment register if 64 bit capable. */ 464 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 465 } 466 467 sc->sc_bus.ub_revision = USBREV_2_0; 468 sc->sc_bus.ub_usedma = true; 469 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 470 471 /* Reset the controller */ 472 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 473 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 474 usb_delay_ms(&sc->sc_bus, 1); 475 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 476 for (i = 0; i < 100; i++) { 477 usb_delay_ms(&sc->sc_bus, 1); 478 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 479 if (!hcr) 480 break; 481 } 482 if (hcr) { 483 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 484 return EIO; 485 } 486 if (sc->sc_vendor_init) 487 sc->sc_vendor_init(sc); 488 489 /* XXX need proper intr scheduling */ 490 sc->sc_rand = 96; 491 492 /* frame list size at default, read back what we got and use that */ 493 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 494 case 0: sc->sc_flsize = 1024; break; 495 case 1: sc->sc_flsize = 512; break; 496 case 2: sc->sc_flsize = 256; break; 497 case 3: return EIO; 498 } 499 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 500 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 501 if (err) 502 return err; 503 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 504 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 505 506 for (i = 0; i < sc->sc_flsize; i++) { 507 sc->sc_flist[i] = EHCI_NULL; 508 } 509 510 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 511 512 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 513 KM_SLEEP); 514 if (sc->sc_softitds == NULL) 515 return ENOMEM; 516 LIST_INIT(&sc->sc_freeitds); 517 LIST_INIT(&sc->sc_freesitds); 518 TAILQ_INIT(&sc->sc_intrhead); 519 520 /* Set up the bus struct. */ 521 sc->sc_bus.ub_methods = &ehci_bus_methods; 522 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 523 524 sc->sc_eintrs = EHCI_NORMAL_INTRS; 525 526 /* 527 * Allocate the interrupt dummy QHs. These are arranged to give poll 528 * intervals that are powers of 2 times 1ms. 529 */ 530 for (i = 0; i < EHCI_INTRQHS; i++) { 531 sqh = ehci_alloc_sqh(sc); 532 if (sqh == NULL) { 533 err = ENOMEM; 534 goto bad1; 535 } 536 sc->sc_islots[i].sqh = sqh; 537 } 538 for (i = 0; i < EHCI_INTRQHS; i++) { 539 sqh = sc->sc_islots[i].sqh; 540 if (i == 0) { 541 /* The last (1ms) QH terminates. */ 542 sqh->qh.qh_link = EHCI_NULL; 543 sqh->next = NULL; 544 } else { 545 /* Otherwise the next QH has half the poll interval */ 546 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 547 sqh->qh.qh_link = htole32(sqh->next->physaddr | 548 EHCI_LINK_QH); 549 } 550 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 551 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 552 sqh->qh.qh_curqtd = EHCI_NULL; 553 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 554 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 555 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 556 sqh->sqtd = NULL; 557 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 559 } 560 /* Point the frame list at the last level (128ms). */ 561 for (i = 0; i < sc->sc_flsize; i++) { 562 int j; 563 564 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 565 revbits[i & (EHCI_MAX_POLLRATE-1)]; 566 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 567 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 568 i)].sqh->physaddr); 569 } 570 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 571 BUS_DMASYNC_PREWRITE); 572 573 /* Allocate dummy QH that starts the async list. */ 574 sqh = ehci_alloc_sqh(sc); 575 if (sqh == NULL) { 576 err = ENOMEM; 577 goto bad1; 578 } 579 /* Fill the QH */ 580 sqh->qh.qh_endp = 581 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 582 sqh->qh.qh_link = 583 htole32(sqh->physaddr | EHCI_LINK_QH); 584 sqh->qh.qh_curqtd = EHCI_NULL; 585 sqh->next = NULL; 586 /* Fill the overlay qTD */ 587 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 588 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 589 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 590 sqh->sqtd = NULL; 591 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 592 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 593 #ifdef EHCI_DEBUG 594 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 595 ehci_dump_sqh(sqh); 596 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 597 #endif 598 599 /* Point to async list */ 600 sc->sc_async_head = sqh; 601 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 602 603 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 604 605 /* Turn on controller */ 606 EOWRITE4(sc, EHCI_USBCMD, 607 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 608 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 609 EHCI_CMD_ASE | 610 EHCI_CMD_PSE | 611 EHCI_CMD_RS); 612 613 /* Take over port ownership */ 614 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 615 616 for (i = 0; i < 100; i++) { 617 usb_delay_ms(&sc->sc_bus, 1); 618 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 619 if (!hcr) 620 break; 621 } 622 if (hcr) { 623 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 624 return EIO; 625 } 626 627 /* Enable interrupts */ 628 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 629 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 630 631 return 0; 632 633 #if 0 634 bad2: 635 ehci_free_sqh(sc, sc->sc_async_head); 636 #endif 637 bad1: 638 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 639 return err; 640 } 641 642 int 643 ehci_intr(void *v) 644 { 645 ehci_softc_t *sc = v; 646 int ret = 0; 647 648 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 649 650 if (sc == NULL) 651 return 0; 652 653 mutex_spin_enter(&sc->sc_intr_lock); 654 655 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 656 goto done; 657 658 /* If we get an interrupt while polling, then just ignore it. */ 659 if (sc->sc_bus.ub_usepolling) { 660 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 661 662 if (intrs) 663 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 664 USBHIST_LOGN(ehcidebug, 16, 665 "ignored interrupt while polling", 0, 0, 0, 0); 666 goto done; 667 } 668 669 ret = ehci_intr1(sc); 670 671 done: 672 mutex_spin_exit(&sc->sc_intr_lock); 673 return ret; 674 } 675 676 Static int 677 ehci_intr1(ehci_softc_t *sc) 678 { 679 uint32_t intrs, eintrs; 680 681 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 682 683 /* In case the interrupt occurs before initialization has completed. */ 684 if (sc == NULL) { 685 #ifdef DIAGNOSTIC 686 printf("ehci_intr1: sc == NULL\n"); 687 #endif 688 return 0; 689 } 690 691 KASSERT(mutex_owned(&sc->sc_intr_lock)); 692 693 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 694 if (!intrs) 695 return 0; 696 697 eintrs = intrs & sc->sc_eintrs; 698 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 699 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 700 if (!eintrs) 701 return 0; 702 703 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 704 if (eintrs & EHCI_STS_IAA) { 705 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 706 kpreempt_disable(); 707 KASSERT(sc->sc_doorbell_si != NULL); 708 softint_schedule(sc->sc_doorbell_si); 709 kpreempt_enable(); 710 eintrs &= ~EHCI_STS_IAA; 711 } 712 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 713 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 714 eintrs & EHCI_STS_INT ? 1 : 0, 715 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 716 usb_schedsoftintr(&sc->sc_bus); 717 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 718 } 719 if (eintrs & EHCI_STS_HSE) { 720 printf("%s: unrecoverable error, controller halted\n", 721 device_xname(sc->sc_dev)); 722 /* XXX what else */ 723 } 724 if (eintrs & EHCI_STS_PCD) { 725 kpreempt_disable(); 726 KASSERT(sc->sc_pcd_si != NULL); 727 softint_schedule(sc->sc_pcd_si); 728 kpreempt_enable(); 729 eintrs &= ~EHCI_STS_PCD; 730 } 731 732 if (eintrs != 0) { 733 /* Block unprocessed interrupts. */ 734 sc->sc_eintrs &= ~eintrs; 735 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 736 printf("%s: blocking intrs 0x%x\n", 737 device_xname(sc->sc_dev), eintrs); 738 } 739 740 return 1; 741 } 742 743 Static void 744 ehci_doorbell(void *addr) 745 { 746 ehci_softc_t *sc = addr; 747 748 mutex_enter(&sc->sc_lock); 749 cv_broadcast(&sc->sc_doorbell); 750 mutex_exit(&sc->sc_lock); 751 } 752 753 Static void 754 ehci_pcd(void *addr) 755 { 756 ehci_softc_t *sc = addr; 757 struct usbd_xfer *xfer; 758 u_char *p; 759 int i, m; 760 761 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 762 763 mutex_enter(&sc->sc_lock); 764 xfer = sc->sc_intrxfer; 765 766 if (xfer == NULL) { 767 /* Just ignore the change. */ 768 goto done; 769 } 770 771 p = xfer->ux_buf; 772 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 773 memset(p, 0, xfer->ux_length); 774 for (i = 1; i <= m; i++) { 775 /* Pick out CHANGE bits from the status reg. */ 776 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 777 p[i/8] |= 1 << (i%8); 778 if (i % 8 == 7) 779 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 780 p[i/8], 0, 0); 781 } 782 xfer->ux_actlen = xfer->ux_length; 783 xfer->ux_status = USBD_NORMAL_COMPLETION; 784 785 usb_transfer_complete(xfer); 786 787 done: 788 mutex_exit(&sc->sc_lock); 789 } 790 791 Static void 792 ehci_softintr(void *v) 793 { 794 struct usbd_bus *bus = v; 795 ehci_softc_t *sc = EHCI_BUS2SC(bus); 796 struct ehci_xfer *ex, *nextex; 797 798 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 799 800 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 801 802 ex_completeq_t cq; 803 TAILQ_INIT(&cq); 804 805 /* 806 * The only explanation I can think of for why EHCI is as brain dead 807 * as UHCI interrupt-wise is that Intel was involved in both. 808 * An interrupt just tells us that something is done, we have no 809 * clue what, so we need to scan through all active transfers. :-( 810 */ 811 812 /* 813 * ehci_idone will remove transfer from sc->sc_intrhead if it's 814 * complete and add to our cq list 815 * */ 816 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 817 switch (ex->ex_type) { 818 case EX_CTRL: 819 case EX_BULK: 820 case EX_INTR: 821 ehci_check_qh_intr(sc, ex, &cq); 822 break; 823 case EX_ISOC: 824 ehci_check_itd_intr(sc, ex, &cq); 825 break; 826 case EX_FS_ISOC: 827 ehci_check_sitd_intr(sc, ex, &cq); 828 break; 829 default: 830 KASSERT(false); 831 } 832 833 } 834 835 /* 836 * We abuse ex_next for the interrupt and complete lists and 837 * interrupt transfers will get re-added here so use 838 * the _SAFE version of TAILQ_FOREACH. 839 */ 840 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 841 /* 842 * XXX transfer_complete memcpys out transfer data (for in 843 * endpoints) during this call, before methods->done is called. 844 * A dma sync required beforehand. 845 */ 846 usb_transfer_complete(&ex->ex_xfer); 847 } 848 849 /* Schedule a callout to catch any dropped transactions. */ 850 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 851 !TAILQ_EMPTY(&sc->sc_intrhead)) 852 callout_reset(&sc->sc_tmo_intrlist, 853 hz, ehci_intrlist_timeout, sc); 854 855 if (sc->sc_softwake) { 856 sc->sc_softwake = 0; 857 cv_broadcast(&sc->sc_softwake_cv); 858 } 859 } 860 861 Static void 862 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 863 { 864 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 865 uint32_t status; 866 867 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 868 869 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 870 871 if (ex->ex_type == EX_CTRL) { 872 fsqtd = ex->ex_setup; 873 lsqtd = ex->ex_status; 874 } else { 875 fsqtd = ex->ex_sqtdstart; 876 lsqtd = ex->ex_sqtdend; 877 } 878 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 879 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 880 881 /* 882 * If the last TD is still active we need to check whether there 883 * is an error somewhere in the middle, or whether there was a 884 * short packet (SPD and not ACTIVE). 885 */ 886 usb_syncmem(&lsqtd->dma, 887 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 888 sizeof(lsqtd->qtd.qtd_status), 889 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 890 status = le32toh(lsqtd->qtd.qtd_status); 891 usb_syncmem(&lsqtd->dma, 892 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 893 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 894 if (status & EHCI_QTD_ACTIVE) { 895 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 896 897 /* last qTD has already been checked */ 898 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 899 usb_syncmem(&sqtd->dma, 900 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 901 sizeof(sqtd->qtd.qtd_status), 902 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 903 status = le32toh(sqtd->qtd.qtd_status); 904 usb_syncmem(&sqtd->dma, 905 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 906 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 907 /* If there's an active QTD the xfer isn't done. */ 908 if (status & EHCI_QTD_ACTIVE) 909 break; 910 /* Any kind of error makes the xfer done. */ 911 if (status & EHCI_QTD_HALTED) 912 goto done; 913 /* Handle short packets */ 914 if (EHCI_QTD_GET_BYTES(status) != 0) { 915 /* 916 * If we get here for a control transfer then 917 * we need to let the hardware complete the 918 * status phase. That is, we're not done 919 * quite yet. 920 * 921 * Otherwise, we're done. 922 */ 923 if (ex->ex_type == EX_CTRL) { 924 break; 925 } 926 goto done; 927 } 928 } 929 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 930 ex, ex->ex_sqtdstart, 0, 0); 931 #ifdef EHCI_DEBUG 932 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 933 0, 0); 934 ehci_dump_sqtds(ex->ex_sqtdstart); 935 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 936 0); 937 #endif 938 return; 939 } 940 done: 941 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 942 callout_stop(&ex->ex_xfer.ux_callout); 943 ehci_idone(ex, cq); 944 } 945 946 Static void 947 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 948 { 949 ehci_soft_itd_t *itd; 950 int i; 951 952 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 953 954 KASSERT(mutex_owned(&sc->sc_lock)); 955 956 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 957 return; 958 959 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 960 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 961 962 itd = ex->ex_itdend; 963 964 /* 965 * check no active transfers in last itd, meaning we're finished 966 */ 967 968 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 969 sizeof(itd->itd.itd_ctl), 970 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 971 972 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 973 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 974 break; 975 } 976 977 if (i == EHCI_ITD_NUFRAMES) { 978 goto done; /* All 8 descriptors inactive, it's done */ 979 } 980 981 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 982 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 983 984 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 985 ex->ex_itdstart, 0, 0); 986 return; 987 done: 988 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 989 callout_stop(&ex->ex_xfer.ux_callout); 990 ehci_idone(ex, cq); 991 } 992 993 void 994 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 995 { 996 ehci_soft_sitd_t *sitd; 997 998 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 999 1000 KASSERT(mutex_owned(&sc->sc_lock)); 1001 1002 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1003 return; 1004 1005 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1006 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1007 1008 sitd = ex->ex_sitdend; 1009 1010 /* 1011 * check no active transfers in last sitd, meaning we're finished 1012 */ 1013 1014 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1015 sizeof(sitd->sitd.sitd_trans), 1016 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1017 1018 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1019 1020 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1021 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1022 1023 if (active) 1024 return; 1025 1026 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1027 callout_stop(&(ex->ex_xfer.ux_callout)); 1028 ehci_idone(ex, cq); 1029 } 1030 1031 1032 Static void 1033 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1034 { 1035 struct usbd_xfer *xfer = &ex->ex_xfer; 1036 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1037 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1038 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1039 uint32_t status = 0, nstatus = 0; 1040 int actlen = 0; 1041 1042 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1043 1044 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1045 1046 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1047 1048 if (xfer->ux_status == USBD_CANCELLED || 1049 xfer->ux_status == USBD_TIMEOUT) { 1050 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1051 return; 1052 } 1053 1054 #ifdef DIAGNOSTIC 1055 #ifdef EHCI_DEBUG 1056 if (ex->ex_isdone) { 1057 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1058 ehci_dump_exfer(ex); 1059 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1060 } 1061 #endif 1062 KASSERT(!ex->ex_isdone); 1063 ex->ex_isdone = true; 1064 #endif 1065 1066 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1067 1068 /* The transfer is done, compute actual length and status. */ 1069 if (ex->ex_type == EX_ISOC) { 1070 /* HS isoc transfer */ 1071 1072 struct ehci_soft_itd *itd; 1073 int i, nframes, len, uframes; 1074 1075 nframes = 0; 1076 1077 #ifdef EHCI_DEBUG 1078 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1079 ehci_dump_itds(ex->ex_itdstart); 1080 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1081 #endif 1082 1083 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1084 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1085 1086 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1087 usb_syncmem(&itd->dma, 1088 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1089 sizeof(itd->itd.itd_ctl), 1090 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1091 1092 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1093 /* 1094 * XXX - driver didn't fill in the frame full 1095 * of uframes. This leads to scheduling 1096 * inefficiencies, but working around 1097 * this doubles complexity of tracking 1098 * an xfer. 1099 */ 1100 if (nframes >= xfer->ux_nframes) 1101 break; 1102 1103 status = le32toh(itd->itd.itd_ctl[i]); 1104 len = EHCI_ITD_GET_LEN(status); 1105 if (EHCI_ITD_GET_STATUS(status) != 0) 1106 len = 0; /*No valid data on error*/ 1107 1108 xfer->ux_frlengths[nframes++] = len; 1109 actlen += len; 1110 } 1111 usb_syncmem(&itd->dma, 1112 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1113 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1114 1115 if (nframes >= xfer->ux_nframes) 1116 break; 1117 } 1118 1119 xfer->ux_actlen = actlen; 1120 xfer->ux_status = USBD_NORMAL_COMPLETION; 1121 goto end; 1122 } else if (ex->ex_type == EX_FS_ISOC) { 1123 /* FS isoc transfer */ 1124 struct ehci_soft_sitd *sitd; 1125 int nframes, len; 1126 1127 nframes = 0; 1128 1129 for (sitd = ex->ex_sitdstart; sitd != NULL; 1130 sitd = sitd->xfer_next) { 1131 usb_syncmem(&sitd->dma, 1132 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1133 sizeof(sitd->sitd.sitd_trans), 1134 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1135 1136 /* 1137 * XXX - driver didn't fill in the frame full 1138 * of uframes. This leads to scheduling 1139 * inefficiencies, but working around 1140 * this doubles complexity of tracking 1141 * an xfer. 1142 */ 1143 if (nframes >= xfer->ux_nframes) 1144 break; 1145 1146 status = le32toh(sitd->sitd.sitd_trans); 1147 usb_syncmem(&sitd->dma, 1148 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1149 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1150 1151 len = EHCI_SITD_GET_LEN(status); 1152 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1153 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1154 /* No valid data on error */ 1155 len = xfer->ux_frlengths[nframes]; 1156 } 1157 1158 /* 1159 * frlengths[i]: # of bytes to send 1160 * len: # of bytes host didn't send 1161 */ 1162 xfer->ux_frlengths[nframes] -= len; 1163 /* frlengths[i]: # of bytes host sent */ 1164 actlen += xfer->ux_frlengths[nframes++]; 1165 1166 if (nframes >= xfer->ux_nframes) 1167 break; 1168 } 1169 1170 xfer->ux_actlen = actlen; 1171 xfer->ux_status = USBD_NORMAL_COMPLETION; 1172 goto end; 1173 } 1174 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1175 ex->ex_type == EX_BULK); 1176 1177 /* Continue processing xfers using queue heads */ 1178 if (ex->ex_type == EX_CTRL) { 1179 fsqtd = ex->ex_setup; 1180 lsqtd = ex->ex_status; 1181 } else { 1182 fsqtd = ex->ex_sqtdstart; 1183 lsqtd = ex->ex_sqtdend; 1184 } 1185 #ifdef EHCI_DEBUG 1186 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1187 ehci_dump_sqtds(fsqtd); 1188 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1189 #endif 1190 1191 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1192 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1193 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1194 nstatus = le32toh(sqtd->qtd.qtd_status); 1195 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1196 BUS_DMASYNC_PREREAD); 1197 if (nstatus & EHCI_QTD_ACTIVE) 1198 break; 1199 1200 status = nstatus; 1201 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1202 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1203 } 1204 1205 /* 1206 * If there are left over TDs we need to update the toggle. 1207 * The default pipe doesn't need it since control transfers 1208 * start the toggle at 0 every time. 1209 * For a short transfer we need to update the toggle for the missing 1210 * packets within the qTD. 1211 */ 1212 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1213 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1214 USBHIST_LOG(ehcidebug, 1215 "toggle update status=0x%08x nstatus=0x%08x", 1216 status, nstatus, 0, 0); 1217 #if 0 1218 ehci_dump_sqh(epipe->sqh); 1219 ehci_dump_sqtds(ex->ex_sqtdstart); 1220 #endif 1221 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1222 } 1223 1224 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1225 actlen, status, 0); 1226 xfer->ux_actlen = actlen; 1227 if (status & EHCI_QTD_HALTED) { 1228 #ifdef EHCI_DEBUG 1229 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1230 xfer->ux_pipe->up_dev->ud_addr, 1231 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1232 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1233 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1234 0, 0); 1235 USBHIST_LOG(ehcidebug, 1236 "active =%d halted=%d buferr=%d babble=%d", 1237 status & EHCI_QTD_ACTIVE ? 1 : 0, 1238 status & EHCI_QTD_HALTED ? 1 : 0, 1239 status & EHCI_QTD_BUFERR ? 1 : 0, 1240 status & EHCI_QTD_BABBLE ? 1 : 0); 1241 1242 USBHIST_LOG(ehcidebug, 1243 "xacterr=%d missed=%d split =%d ping =%d", 1244 status & EHCI_QTD_XACTERR ? 1 : 0, 1245 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1246 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1247 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1248 1249 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1250 ehci_dump_sqh(epipe->sqh); 1251 ehci_dump_sqtds(ex->ex_sqtdstart); 1252 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1253 #endif 1254 /* low&full speed has an extra error flag */ 1255 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1256 EHCI_QH_SPEED_HIGH) 1257 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1258 else 1259 status &= EHCI_QTD_STATERRS; 1260 if (status == 0) /* no other errors means a stall */ { 1261 xfer->ux_status = USBD_STALLED; 1262 } else { 1263 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1264 } 1265 /* XXX need to reset TT on missed microframe */ 1266 if (status & EHCI_QTD_MISSEDMICRO) { 1267 printf("%s: missed microframe, TT reset not " 1268 "implemented, hub might be inoperational\n", 1269 device_xname(sc->sc_dev)); 1270 } 1271 } else { 1272 xfer->ux_status = USBD_NORMAL_COMPLETION; 1273 } 1274 1275 end: 1276 1277 ehci_del_intr_list(sc, ex); 1278 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1279 1280 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1281 } 1282 1283 /* 1284 * Wait here until controller claims to have an interrupt. 1285 * Then call ehci_intr and return. Use timeout to avoid waiting 1286 * too long. 1287 */ 1288 Static void 1289 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1290 { 1291 int timo; 1292 uint32_t intrs; 1293 1294 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1295 1296 xfer->ux_status = USBD_IN_PROGRESS; 1297 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1298 usb_delay_ms(&sc->sc_bus, 1); 1299 if (sc->sc_dying) 1300 break; 1301 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1302 sc->sc_eintrs; 1303 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1304 #ifdef EHCI_DEBUG 1305 if (ehcidebug >= 15) 1306 ehci_dump_regs(sc); 1307 #endif 1308 if (intrs) { 1309 mutex_spin_enter(&sc->sc_intr_lock); 1310 ehci_intr1(sc); 1311 mutex_spin_exit(&sc->sc_intr_lock); 1312 if (xfer->ux_status != USBD_IN_PROGRESS) 1313 return; 1314 } 1315 } 1316 1317 /* Timeout */ 1318 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1319 xfer->ux_status = USBD_TIMEOUT; 1320 mutex_enter(&sc->sc_lock); 1321 usb_transfer_complete(xfer); 1322 mutex_exit(&sc->sc_lock); 1323 } 1324 1325 Static void 1326 ehci_poll(struct usbd_bus *bus) 1327 { 1328 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1329 1330 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1331 1332 #ifdef EHCI_DEBUG 1333 static int last; 1334 int new; 1335 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1336 if (new != last) { 1337 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1338 last = new; 1339 } 1340 #endif 1341 1342 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1343 mutex_spin_enter(&sc->sc_intr_lock); 1344 ehci_intr1(sc); 1345 mutex_spin_exit(&sc->sc_intr_lock); 1346 } 1347 } 1348 1349 void 1350 ehci_childdet(device_t self, device_t child) 1351 { 1352 struct ehci_softc *sc = device_private(self); 1353 1354 KASSERT(sc->sc_child == child); 1355 sc->sc_child = NULL; 1356 } 1357 1358 int 1359 ehci_detach(struct ehci_softc *sc, int flags) 1360 { 1361 int rv = 0; 1362 1363 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1364 1365 if (sc->sc_child != NULL) 1366 rv = config_detach(sc->sc_child, flags); 1367 1368 if (rv != 0) 1369 return rv; 1370 1371 callout_halt(&sc->sc_tmo_intrlist, NULL); 1372 callout_destroy(&sc->sc_tmo_intrlist); 1373 1374 /* XXX free other data structures XXX */ 1375 if (sc->sc_softitds) 1376 kmem_free(sc->sc_softitds, 1377 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1378 cv_destroy(&sc->sc_doorbell); 1379 cv_destroy(&sc->sc_softwake_cv); 1380 1381 #if 0 1382 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1383 1384 softint_disestablish(sc->sc_doorbell_si); 1385 softint_disestablish(sc->sc_pcd_si); 1386 1387 mutex_destroy(&sc->sc_lock); 1388 mutex_destroy(&sc->sc_intr_lock); 1389 #endif 1390 1391 pool_cache_destroy(sc->sc_xferpool); 1392 1393 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1394 1395 return rv; 1396 } 1397 1398 1399 int 1400 ehci_activate(device_t self, enum devact act) 1401 { 1402 struct ehci_softc *sc = device_private(self); 1403 1404 switch (act) { 1405 case DVACT_DEACTIVATE: 1406 sc->sc_dying = 1; 1407 return 0; 1408 default: 1409 return EOPNOTSUPP; 1410 } 1411 } 1412 1413 /* 1414 * Handle suspend/resume. 1415 * 1416 * We need to switch to polling mode here, because this routine is 1417 * called from an interrupt context. This is all right since we 1418 * are almost suspended anyway. 1419 * 1420 * Note that this power handler isn't to be registered directly; the 1421 * bus glue needs to call out to it. 1422 */ 1423 bool 1424 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1425 { 1426 ehci_softc_t *sc = device_private(dv); 1427 int i; 1428 uint32_t cmd, hcr; 1429 1430 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1431 1432 mutex_spin_enter(&sc->sc_intr_lock); 1433 sc->sc_bus.ub_usepolling++; 1434 mutex_spin_exit(&sc->sc_intr_lock); 1435 1436 for (i = 1; i <= sc->sc_noport; i++) { 1437 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1438 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1439 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1440 } 1441 1442 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1443 1444 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1445 EOWRITE4(sc, EHCI_USBCMD, cmd); 1446 1447 for (i = 0; i < 100; i++) { 1448 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1449 if (hcr == 0) 1450 break; 1451 1452 usb_delay_ms(&sc->sc_bus, 1); 1453 } 1454 if (hcr != 0) 1455 printf("%s: reset timeout\n", device_xname(dv)); 1456 1457 cmd &= ~EHCI_CMD_RS; 1458 EOWRITE4(sc, EHCI_USBCMD, cmd); 1459 1460 for (i = 0; i < 100; i++) { 1461 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1462 if (hcr == EHCI_STS_HCH) 1463 break; 1464 1465 usb_delay_ms(&sc->sc_bus, 1); 1466 } 1467 if (hcr != EHCI_STS_HCH) 1468 printf("%s: config timeout\n", device_xname(dv)); 1469 1470 mutex_spin_enter(&sc->sc_intr_lock); 1471 sc->sc_bus.ub_usepolling--; 1472 mutex_spin_exit(&sc->sc_intr_lock); 1473 1474 return true; 1475 } 1476 1477 bool 1478 ehci_resume(device_t dv, const pmf_qual_t *qual) 1479 { 1480 ehci_softc_t *sc = device_private(dv); 1481 int i; 1482 uint32_t cmd, hcr; 1483 1484 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1485 1486 /* restore things in case the bios sucks */ 1487 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1488 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1489 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1490 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1491 1492 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1493 1494 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1495 1496 hcr = 0; 1497 for (i = 1; i <= sc->sc_noport; i++) { 1498 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1499 if ((cmd & EHCI_PS_PO) == 0 && 1500 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1501 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1502 hcr = 1; 1503 } 1504 } 1505 1506 if (hcr) { 1507 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1508 1509 for (i = 1; i <= sc->sc_noport; i++) { 1510 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1511 if ((cmd & EHCI_PS_PO) == 0 && 1512 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1513 EOWRITE4(sc, EHCI_PORTSC(i), 1514 cmd & ~EHCI_PS_FPR); 1515 } 1516 } 1517 1518 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1519 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1520 1521 for (i = 0; i < 100; i++) { 1522 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1523 if (hcr != EHCI_STS_HCH) 1524 break; 1525 1526 usb_delay_ms(&sc->sc_bus, 1); 1527 } 1528 if (hcr == EHCI_STS_HCH) 1529 printf("%s: config timeout\n", device_xname(dv)); 1530 1531 return true; 1532 } 1533 1534 /* 1535 * Shut down the controller when the system is going down. 1536 */ 1537 bool 1538 ehci_shutdown(device_t self, int flags) 1539 { 1540 ehci_softc_t *sc = device_private(self); 1541 1542 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1543 1544 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1545 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1546 return true; 1547 } 1548 1549 Static struct usbd_xfer * 1550 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1551 { 1552 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1553 struct usbd_xfer *xfer; 1554 1555 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1556 if (xfer != NULL) { 1557 memset(xfer, 0, sizeof(struct ehci_xfer)); 1558 #ifdef DIAGNOSTIC 1559 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1560 ex->ex_isdone = true; 1561 xfer->ux_state = XFER_BUSY; 1562 #endif 1563 } 1564 return xfer; 1565 } 1566 1567 Static void 1568 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1569 { 1570 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1571 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1572 1573 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1574 xfer->ux_state); 1575 KASSERT(ex->ex_isdone); 1576 1577 #ifdef DIAGNOSTIC 1578 xfer->ux_state = XFER_FREE; 1579 #endif 1580 1581 pool_cache_put(sc->sc_xferpool, xfer); 1582 } 1583 1584 Static void 1585 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1586 { 1587 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1588 1589 *lock = &sc->sc_lock; 1590 } 1591 1592 Static void 1593 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1594 { 1595 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1596 1597 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1598 1599 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1600 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1601 #ifdef EHCI_DEBUG 1602 if (ehcidebug) 1603 usbd_dump_pipe(pipe); 1604 #endif 1605 epipe->nexttoggle = 0; 1606 } 1607 1608 Static void 1609 ehci_noop(struct usbd_pipe *pipe) 1610 { 1611 } 1612 1613 #ifdef EHCI_DEBUG 1614 /* 1615 * Unused function - this is meant to be called from a kernel 1616 * debugger. 1617 */ 1618 void 1619 ehci_dump(void) 1620 { 1621 ehci_softc_t *sc = theehci; 1622 int i; 1623 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1624 EOREAD4(sc, EHCI_USBCMD), 1625 EOREAD4(sc, EHCI_USBSTS), 1626 EOREAD4(sc, EHCI_USBINTR)); 1627 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1628 EOREAD4(sc, EHCI_FRINDEX), 1629 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1630 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1631 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1632 for (i = 1; i <= sc->sc_noport; i++) 1633 printf("port %d status=0x%08x\n", i, 1634 EOREAD4(sc, EHCI_PORTSC(i))); 1635 } 1636 1637 Static void 1638 ehci_dump_regs(ehci_softc_t *sc) 1639 { 1640 int i; 1641 1642 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1643 1644 USBHIST_LOG(ehcidebug, 1645 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1646 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1647 EOREAD4(sc, EHCI_USBINTR), 0); 1648 USBHIST_LOG(ehcidebug, 1649 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1650 "async = 0x%08x", 1651 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1652 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1653 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1654 for (i = 1; i <= sc->sc_noport; i += 2) { 1655 if (i == sc->sc_noport) { 1656 USBHIST_LOG(ehcidebug, 1657 "port %d status = 0x%08x", i, 1658 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1659 } else { 1660 USBHIST_LOG(ehcidebug, 1661 "port %d status = 0x%08x port %d status = 0x%08x", 1662 i, EOREAD4(sc, EHCI_PORTSC(i)), 1663 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1664 } 1665 } 1666 } 1667 1668 #define ehci_dump_link(link, type) do { \ 1669 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1670 link, \ 1671 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1672 if (type) { \ 1673 USBHIST_LOG(ehcidebug, \ 1674 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1675 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1676 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1677 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1678 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1679 } \ 1680 } while(0) 1681 1682 Static void 1683 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1684 { 1685 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1686 int i; 1687 uint32_t stop = 0; 1688 1689 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1690 ehci_dump_sqtd(sqtd); 1691 usb_syncmem(&sqtd->dma, 1692 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1693 sizeof(sqtd->qtd), 1694 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1695 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1696 usb_syncmem(&sqtd->dma, 1697 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1698 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1699 } 1700 if (!stop) 1701 USBHIST_LOG(ehcidebug, 1702 "dump aborted, too many TDs", 0, 0, 0, 0); 1703 } 1704 1705 Static void 1706 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1707 { 1708 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1709 1710 usb_syncmem(&sqtd->dma, sqtd->offs, 1711 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1712 1713 USBHIST_LOGN(ehcidebug, 10, 1714 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1715 ehci_dump_qtd(&sqtd->qtd); 1716 1717 usb_syncmem(&sqtd->dma, sqtd->offs, 1718 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1719 } 1720 1721 Static void 1722 ehci_dump_qtd(ehci_qtd_t *qtd) 1723 { 1724 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1725 uint32_t s = le32toh(qtd->qtd_status); 1726 1727 USBHIST_LOGN(ehcidebug, 10, 1728 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1729 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1730 USBHIST_LOGN(ehcidebug, 10, 1731 " toggle = %d ioc = %d bytes = %#x " 1732 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1733 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1734 USBHIST_LOGN(ehcidebug, 10, 1735 " cerr = %d pid = %d stat = %x", 1736 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1737 0); 1738 USBHIST_LOGN(ehcidebug, 10, 1739 "active =%d halted=%d buferr=%d babble=%d", 1740 s & EHCI_QTD_ACTIVE ? 1 : 0, 1741 s & EHCI_QTD_HALTED ? 1 : 0, 1742 s & EHCI_QTD_BUFERR ? 1 : 0, 1743 s & EHCI_QTD_BABBLE ? 1 : 0); 1744 USBHIST_LOGN(ehcidebug, 10, 1745 "xacterr=%d missed=%d split =%d ping =%d", 1746 s & EHCI_QTD_XACTERR ? 1 : 0, 1747 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1748 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1749 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1750 USBHIST_LOGN(ehcidebug, 10, 1751 "buffer[0] = %#x buffer[1] = %#x " 1752 "buffer[2] = %#x buffer[3] = %#x", 1753 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1754 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1755 USBHIST_LOGN(ehcidebug, 10, 1756 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1757 } 1758 1759 Static void 1760 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1761 { 1762 ehci_qh_t *qh = &sqh->qh; 1763 ehci_link_t link; 1764 uint32_t endp, endphub; 1765 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1766 1767 usb_syncmem(&sqh->dma, sqh->offs, 1768 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1769 1770 USBHIST_LOGN(ehcidebug, 10, 1771 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1772 link = le32toh(qh->qh_link); 1773 ehci_dump_link(link, true); 1774 1775 endp = le32toh(qh->qh_endp); 1776 USBHIST_LOGN(ehcidebug, 10, 1777 " endp = %#x", endp, 0, 0, 0); 1778 USBHIST_LOGN(ehcidebug, 10, 1779 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1780 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1781 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1782 USBHIST_LOGN(ehcidebug, 10, 1783 " dtc = %d hrecl = %d", 1784 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1785 USBHIST_LOGN(ehcidebug, 10, 1786 " ctl = %d nrl = %d mpl = %#x(%d)", 1787 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1788 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1789 1790 endphub = le32toh(qh->qh_endphub); 1791 USBHIST_LOGN(ehcidebug, 10, 1792 " endphub = %#x", endphub, 0, 0, 0); 1793 USBHIST_LOGN(ehcidebug, 10, 1794 " smask = 0x%02x cmask = 0x%02x", 1795 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1796 USBHIST_LOGN(ehcidebug, 10, 1797 " huba = 0x%02x port = %d mult = %d", 1798 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1799 EHCI_QH_GET_MULT(endphub), 0); 1800 1801 link = le32toh(qh->qh_curqtd); 1802 ehci_dump_link(link, false); 1803 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1804 ehci_dump_qtd(&qh->qh_qtd); 1805 1806 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1807 BUS_DMASYNC_PREREAD); 1808 } 1809 1810 Static void 1811 ehci_dump_itds(ehci_soft_itd_t *itd) 1812 { 1813 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1814 int i; 1815 uint32_t stop = 0; 1816 1817 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1818 ehci_dump_itd(itd); 1819 usb_syncmem(&itd->dma, 1820 itd->offs + offsetof(ehci_itd_t, itd_next), 1821 sizeof(itd->itd), 1822 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1823 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1824 usb_syncmem(&itd->dma, 1825 itd->offs + offsetof(ehci_itd_t, itd_next), 1826 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1827 } 1828 if (!stop) 1829 USBHIST_LOG(ehcidebug, "dump aborted, too many TDs", 0, 0, 0, 0); 1830 } 1831 1832 Static void 1833 ehci_dump_itd(struct ehci_soft_itd *itd) 1834 { 1835 ehci_isoc_trans_t t; 1836 ehci_isoc_bufr_ptr_t b, b2, b3; 1837 int i; 1838 1839 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1840 1841 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1842 0, 0); 1843 1844 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1845 t = le32toh(itd->itd.itd_ctl[i]); 1846 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1847 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1848 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1849 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1850 EHCI_ITD_GET_OFFS(t), 0); 1851 } 1852 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1853 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1854 USBHIST_LOG(ehcidebug, " %x", 1855 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1856 1857 b = le32toh(itd->itd.itd_bufr[0]); 1858 b2 = le32toh(itd->itd.itd_bufr[1]); 1859 b3 = le32toh(itd->itd.itd_bufr[2]); 1860 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1861 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1862 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1863 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1864 } 1865 1866 Static void 1867 ehci_dump_sitd(struct ehci_soft_itd *itd) 1868 { 1869 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1870 1871 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1872 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1873 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1874 itd->xfer_next, itd->physaddr, itd->slot, 0); 1875 } 1876 1877 Static void 1878 ehci_dump_exfer(struct ehci_xfer *ex) 1879 { 1880 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1881 1882 USBHIST_LOG(ehcidebug, "ex = %p type %d isdone", ex, ex->ex_type, 1883 ex->ex_isdone, 0); 1884 1885 switch (ex->ex_type) { 1886 case EX_CTRL: 1887 USBHIST_LOG(ehcidebug, " setup = %p data = %p status = %p", 1888 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1889 break; 1890 case EX_BULK: 1891 case EX_INTR: 1892 USBHIST_LOG(ehcidebug, " qtdstart = %p qtdend = %p", 1893 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1894 break; 1895 case EX_ISOC: 1896 USBHIST_LOG(ehcidebug, " itdstart = %p itdend = %p", 1897 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1898 break; 1899 case EX_FS_ISOC: 1900 USBHIST_LOG(ehcidebug, " sitdstart = %p sitdend = %p", 1901 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1902 break; 1903 default: 1904 USBHIST_LOG(ehcidebug, " unknown type", 0, 0, 0, 0); 1905 } 1906 } 1907 #endif 1908 1909 Static usbd_status 1910 ehci_open(struct usbd_pipe *pipe) 1911 { 1912 struct usbd_device *dev = pipe->up_dev; 1913 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1914 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1915 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1916 uint8_t addr = dev->ud_addr; 1917 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1918 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1919 ehci_soft_qh_t *sqh; 1920 usbd_status err; 1921 int ival, speed, naks; 1922 int hshubaddr, hshubport; 1923 1924 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1925 1926 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1927 pipe, addr, ed->bEndpointAddress, rhaddr); 1928 1929 if (dev->ud_myhsport) { 1930 /* 1931 * When directly attached FS/LS device while doing embedded 1932 * transaction translations and we are the hub, set the hub 1933 * address to 0 (us). 1934 */ 1935 if (!(sc->sc_flags & EHCIF_ETTF) 1936 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1937 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1938 } else { 1939 hshubaddr = 0; 1940 } 1941 hshubport = dev->ud_myhsport->up_portno; 1942 } else { 1943 hshubaddr = 0; 1944 hshubport = 0; 1945 } 1946 1947 if (sc->sc_dying) 1948 return USBD_IOERROR; 1949 1950 /* toggle state needed for bulk endpoints */ 1951 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1952 1953 if (addr == rhaddr) { 1954 switch (ed->bEndpointAddress) { 1955 case USB_CONTROL_ENDPOINT: 1956 pipe->up_methods = &roothub_ctrl_methods; 1957 break; 1958 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1959 pipe->up_methods = &ehci_root_intr_methods; 1960 break; 1961 default: 1962 USBHIST_LOG(ehcidebug, 1963 "bad bEndpointAddress 0x%02x", 1964 ed->bEndpointAddress, 0, 0, 0); 1965 return USBD_INVAL; 1966 } 1967 return USBD_NORMAL_COMPLETION; 1968 } 1969 1970 /* XXX All this stuff is only valid for async. */ 1971 switch (dev->ud_speed) { 1972 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1973 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1974 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1975 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1976 } 1977 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1978 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1979 hshubaddr, hshubport, 0, 0); 1980 return USBD_INVAL; 1981 } 1982 1983 /* 1984 * For interrupt transfer, nak throttling must be disabled, but for 1985 * the other transfer type, nak throttling should be enabled from the 1986 * viewpoint that avoids the memory thrashing. 1987 */ 1988 naks = (xfertype == UE_INTERRUPT) ? 0 1989 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1990 1991 /* Allocate sqh for everything, save isoc xfers */ 1992 if (xfertype != UE_ISOCHRONOUS) { 1993 sqh = ehci_alloc_sqh(sc); 1994 if (sqh == NULL) 1995 return USBD_NOMEM; 1996 /* qh_link filled when the QH is added */ 1997 sqh->qh.qh_endp = htole32( 1998 EHCI_QH_SET_ADDR(addr) | 1999 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 2000 EHCI_QH_SET_EPS(speed) | 2001 EHCI_QH_DTC | 2002 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 2003 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 2004 EHCI_QH_CTL : 0) | 2005 EHCI_QH_SET_NRL(naks) 2006 ); 2007 sqh->qh.qh_endphub = htole32( 2008 EHCI_QH_SET_MULT(1) | 2009 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 2010 ); 2011 if (speed != EHCI_QH_SPEED_HIGH) 2012 sqh->qh.qh_endphub |= htole32( 2013 EHCI_QH_SET_PORT(hshubport) | 2014 EHCI_QH_SET_HUBA(hshubaddr) | 2015 EHCI_QH_SET_CMASK(0x08) /* XXX */ 2016 ); 2017 sqh->qh.qh_curqtd = EHCI_NULL; 2018 /* Fill the overlay qTD */ 2019 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2020 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2021 sqh->qh.qh_qtd.qtd_status = htole32(0); 2022 2023 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2024 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2025 epipe->sqh = sqh; 2026 } else { 2027 sqh = NULL; 2028 } /*xfertype == UE_ISOC*/ 2029 2030 switch (xfertype) { 2031 case UE_CONTROL: 2032 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2033 0, &epipe->ctrl.reqdma); 2034 #ifdef EHCI_DEBUG 2035 if (err) 2036 printf("ehci_open: usb_allocmem()=%d\n", err); 2037 #endif 2038 if (err) 2039 goto bad; 2040 pipe->up_methods = &ehci_device_ctrl_methods; 2041 mutex_enter(&sc->sc_lock); 2042 ehci_add_qh(sc, sqh, sc->sc_async_head); 2043 mutex_exit(&sc->sc_lock); 2044 break; 2045 case UE_BULK: 2046 pipe->up_methods = &ehci_device_bulk_methods; 2047 mutex_enter(&sc->sc_lock); 2048 ehci_add_qh(sc, sqh, sc->sc_async_head); 2049 mutex_exit(&sc->sc_lock); 2050 break; 2051 case UE_INTERRUPT: 2052 pipe->up_methods = &ehci_device_intr_methods; 2053 ival = pipe->up_interval; 2054 if (ival == USBD_DEFAULT_INTERVAL) { 2055 if (speed == EHCI_QH_SPEED_HIGH) { 2056 if (ed->bInterval > 16) { 2057 /* 2058 * illegal with high-speed, but there 2059 * were documentation bugs in the spec, 2060 * so be generous 2061 */ 2062 ival = 256; 2063 } else 2064 ival = (1 << (ed->bInterval - 1)) / 8; 2065 } else 2066 ival = ed->bInterval; 2067 } 2068 err = ehci_device_setintr(sc, sqh, ival); 2069 if (err) 2070 goto bad; 2071 break; 2072 case UE_ISOCHRONOUS: 2073 if (speed == EHCI_QH_SPEED_HIGH) 2074 pipe->up_methods = &ehci_device_isoc_methods; 2075 else 2076 pipe->up_methods = &ehci_device_fs_isoc_methods; 2077 if (ed->bInterval == 0 || ed->bInterval > 16) { 2078 printf("ehci: opening pipe with invalid bInterval\n"); 2079 err = USBD_INVAL; 2080 goto bad; 2081 } 2082 if (UGETW(ed->wMaxPacketSize) == 0) { 2083 printf("ehci: zero length endpoint open request\n"); 2084 err = USBD_INVAL; 2085 goto bad; 2086 } 2087 epipe->isoc.next_frame = 0; 2088 epipe->isoc.cur_xfers = 0; 2089 break; 2090 default: 2091 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2092 err = USBD_INVAL; 2093 goto bad; 2094 } 2095 return USBD_NORMAL_COMPLETION; 2096 2097 bad: 2098 if (sqh != NULL) { 2099 mutex_enter(&sc->sc_lock); 2100 ehci_free_sqh(sc, sqh); 2101 mutex_exit(&sc->sc_lock); 2102 } 2103 return err; 2104 } 2105 2106 /* 2107 * Add an ED to the schedule. Called with USB lock held. 2108 */ 2109 Static void 2110 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2111 { 2112 2113 KASSERT(mutex_owned(&sc->sc_lock)); 2114 2115 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2116 2117 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2118 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2119 2120 sqh->next = head->next; 2121 sqh->qh.qh_link = head->qh.qh_link; 2122 2123 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2124 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2125 2126 head->next = sqh; 2127 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2128 2129 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2130 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2131 2132 #ifdef EHCI_DEBUG 2133 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2134 ehci_dump_sqh(sqh); 2135 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2136 #endif 2137 } 2138 2139 /* 2140 * Remove an ED from the schedule. Called with USB lock held. 2141 */ 2142 Static void 2143 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2144 { 2145 ehci_soft_qh_t *p; 2146 2147 KASSERT(mutex_owned(&sc->sc_lock)); 2148 2149 /* XXX */ 2150 for (p = head; p != NULL && p->next != sqh; p = p->next) 2151 ; 2152 if (p == NULL) 2153 panic("ehci_rem_qh: ED not found"); 2154 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2155 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2156 p->next = sqh->next; 2157 p->qh.qh_link = sqh->qh.qh_link; 2158 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2159 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2160 2161 ehci_sync_hc(sc); 2162 } 2163 2164 Static void 2165 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2166 { 2167 int i; 2168 uint32_t status; 2169 2170 /* Save toggle bit and ping status. */ 2171 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2172 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2173 status = sqh->qh.qh_qtd.qtd_status & 2174 htole32(EHCI_QTD_TOGGLE_MASK | 2175 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2176 /* Set HALTED to make hw leave it alone. */ 2177 sqh->qh.qh_qtd.qtd_status = 2178 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2179 usb_syncmem(&sqh->dma, 2180 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2181 sizeof(sqh->qh.qh_qtd.qtd_status), 2182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2183 sqh->qh.qh_curqtd = 0; 2184 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2185 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2186 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2187 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2188 sqh->sqtd = sqtd; 2189 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2190 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2191 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2192 sqh->qh.qh_qtd.qtd_status = status; 2193 usb_syncmem(&sqh->dma, 2194 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2195 sizeof(sqh->qh.qh_qtd.qtd_status), 2196 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2197 } 2198 2199 /* 2200 * Ensure that the HC has released all references to the QH. We do this 2201 * by asking for a Async Advance Doorbell interrupt and then we wait for 2202 * the interrupt. 2203 * To make this easier we first obtain exclusive use of the doorbell. 2204 */ 2205 Static void 2206 ehci_sync_hc(ehci_softc_t *sc) 2207 { 2208 int error __diagused; 2209 2210 KASSERT(mutex_owned(&sc->sc_lock)); 2211 2212 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2213 2214 if (sc->sc_dying) { 2215 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2216 return; 2217 } 2218 /* ask for doorbell */ 2219 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2220 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2221 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2222 2223 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2224 2225 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x ... done", 2226 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2227 #ifdef DIAGNOSTIC 2228 if (error) 2229 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2230 #endif 2231 } 2232 2233 Static void 2234 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2235 { 2236 2237 KASSERT(mutex_owned(&sc->sc_lock)); 2238 2239 for (; itd != NULL; itd = itd->xfer_next) { 2240 struct ehci_soft_itd *prev = itd->frame_list.prev; 2241 2242 /* Unlink itd from hardware chain, or frame array */ 2243 if (prev == NULL) { /* We're at the table head */ 2244 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2245 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2246 usb_syncmem(&sc->sc_fldma, 2247 sizeof(ehci_link_t) * itd->slot, 2248 sizeof(ehci_link_t), 2249 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2250 2251 if (itd->frame_list.next != NULL) 2252 itd->frame_list.next->frame_list.prev = NULL; 2253 } else { 2254 /* XXX this part is untested... */ 2255 prev->itd.itd_next = itd->itd.itd_next; 2256 usb_syncmem(&itd->dma, 2257 itd->offs + offsetof(ehci_itd_t, itd_next), 2258 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2259 2260 prev->frame_list.next = itd->frame_list.next; 2261 if (itd->frame_list.next != NULL) 2262 itd->frame_list.next->frame_list.prev = prev; 2263 } 2264 } 2265 } 2266 2267 Static void 2268 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2269 { 2270 struct ehci_soft_itd *next; 2271 2272 mutex_enter(&sc->sc_lock); 2273 next = NULL; 2274 for (; itd != NULL; itd = next) { 2275 next = itd->xfer_next; 2276 ehci_free_itd_locked(sc, itd); 2277 } 2278 mutex_exit(&sc->sc_lock); 2279 } 2280 2281 Static void 2282 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2283 { 2284 2285 KASSERT(mutex_owned(&sc->sc_lock)); 2286 2287 for (; sitd != NULL; sitd = sitd->xfer_next) { 2288 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2289 2290 /* Unlink sitd from hardware chain, or frame array */ 2291 if (prev == NULL) { /* We're at the table head */ 2292 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2293 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2294 usb_syncmem(&sc->sc_fldma, 2295 sizeof(ehci_link_t) * sitd->slot, 2296 sizeof(ehci_link_t), 2297 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2298 2299 if (sitd->frame_list.next != NULL) 2300 sitd->frame_list.next->frame_list.prev = NULL; 2301 } else { 2302 /* XXX this part is untested... */ 2303 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2304 usb_syncmem(&sitd->dma, 2305 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2306 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2307 2308 prev->frame_list.next = sitd->frame_list.next; 2309 if (sitd->frame_list.next != NULL) 2310 sitd->frame_list.next->frame_list.prev = prev; 2311 } 2312 } 2313 } 2314 2315 Static void 2316 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2317 { 2318 2319 mutex_enter(&sc->sc_lock); 2320 struct ehci_soft_sitd *next = NULL; 2321 for (; sitd != NULL; sitd = next) { 2322 next = sitd->xfer_next; 2323 ehci_free_sitd_locked(sc, sitd); 2324 } 2325 mutex_exit(&sc->sc_lock); 2326 } 2327 2328 /***********/ 2329 2330 Static int 2331 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2332 void *buf, int buflen) 2333 { 2334 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2335 usb_hub_descriptor_t hubd; 2336 usb_port_status_t ps; 2337 uint16_t len, value, index; 2338 int l, totlen = 0; 2339 int port, i; 2340 uint32_t v; 2341 2342 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2343 2344 if (sc->sc_dying) 2345 return -1; 2346 2347 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2348 req->bmRequestType, req->bRequest, 0, 0); 2349 2350 len = UGETW(req->wLength); 2351 value = UGETW(req->wValue); 2352 index = UGETW(req->wIndex); 2353 2354 #define C(x,y) ((x) | ((y) << 8)) 2355 switch (C(req->bRequest, req->bmRequestType)) { 2356 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2357 if (len == 0) 2358 break; 2359 switch (value) { 2360 case C(0, UDESC_DEVICE): { 2361 usb_device_descriptor_t devd; 2362 totlen = min(buflen, sizeof(devd)); 2363 memcpy(&devd, buf, totlen); 2364 USETW(devd.idVendor, sc->sc_id_vendor); 2365 memcpy(buf, &devd, totlen); 2366 break; 2367 2368 } 2369 #define sd ((usb_string_descriptor_t *)buf) 2370 case C(1, UDESC_STRING): 2371 /* Vendor */ 2372 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2373 break; 2374 case C(2, UDESC_STRING): 2375 /* Product */ 2376 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2377 break; 2378 #undef sd 2379 default: 2380 /* default from usbroothub */ 2381 return buflen; 2382 } 2383 break; 2384 2385 /* Hub requests */ 2386 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2387 break; 2388 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2389 USBHIST_LOG(ehcidebug, 2390 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2391 0, 0); 2392 if (index < 1 || index > sc->sc_noport) { 2393 return -1; 2394 } 2395 port = EHCI_PORTSC(index); 2396 v = EOREAD4(sc, port); 2397 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2398 v &= ~EHCI_PS_CLEAR; 2399 switch (value) { 2400 case UHF_PORT_ENABLE: 2401 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2402 break; 2403 case UHF_PORT_SUSPEND: 2404 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2405 break; 2406 v &= ~EHCI_PS_SUSP; 2407 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2408 /* see USB2 spec ch. 7.1.7.7 */ 2409 usb_delay_ms(&sc->sc_bus, 20); 2410 EOWRITE4(sc, port, v); 2411 usb_delay_ms(&sc->sc_bus, 2); 2412 #ifdef DEBUG 2413 v = EOREAD4(sc, port); 2414 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2415 printf("ehci: resume failed: %x\n", v); 2416 #endif 2417 break; 2418 case UHF_PORT_POWER: 2419 if (sc->sc_hasppc) 2420 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2421 break; 2422 case UHF_PORT_TEST: 2423 USBHIST_LOG(ehcidebug, "clear port test " 2424 "%d", index, 0, 0, 0); 2425 break; 2426 case UHF_PORT_INDICATOR: 2427 USBHIST_LOG(ehcidebug, "clear port ind " 2428 "%d", index, 0, 0, 0); 2429 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2430 break; 2431 case UHF_C_PORT_CONNECTION: 2432 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2433 break; 2434 case UHF_C_PORT_ENABLE: 2435 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2436 break; 2437 case UHF_C_PORT_SUSPEND: 2438 /* how? */ 2439 break; 2440 case UHF_C_PORT_OVER_CURRENT: 2441 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2442 break; 2443 case UHF_C_PORT_RESET: 2444 sc->sc_isreset[index] = 0; 2445 break; 2446 default: 2447 return -1; 2448 } 2449 #if 0 2450 switch(value) { 2451 case UHF_C_PORT_CONNECTION: 2452 case UHF_C_PORT_ENABLE: 2453 case UHF_C_PORT_SUSPEND: 2454 case UHF_C_PORT_OVER_CURRENT: 2455 case UHF_C_PORT_RESET: 2456 default: 2457 break; 2458 } 2459 #endif 2460 break; 2461 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2462 if (len == 0) 2463 break; 2464 if ((value & 0xff) != 0) { 2465 return -1; 2466 } 2467 totlen = min(buflen, sizeof(hubd)); 2468 memcpy(&hubd, buf, totlen); 2469 hubd.bNbrPorts = sc->sc_noport; 2470 v = EOREAD4(sc, EHCI_HCSPARAMS); 2471 USETW(hubd.wHubCharacteristics, 2472 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2473 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2474 ? UHD_PORT_IND : 0); 2475 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2476 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2477 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2478 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2479 totlen = min(totlen, hubd.bDescLength); 2480 memcpy(buf, &hubd, totlen); 2481 break; 2482 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2483 if (len != 4) { 2484 return -1; 2485 } 2486 memset(buf, 0, len); /* ? XXX */ 2487 totlen = len; 2488 break; 2489 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2490 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2491 if (index < 1 || index > sc->sc_noport) { 2492 return -1; 2493 } 2494 if (len != 4) { 2495 return -1; 2496 } 2497 v = EOREAD4(sc, EHCI_PORTSC(index)); 2498 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2499 2500 i = UPS_HIGH_SPEED; 2501 if (sc->sc_flags & EHCIF_ETTF) { 2502 /* 2503 * If we are doing embedded transaction translation, 2504 * then directly attached LS/FS devices are reset by 2505 * the EHCI controller itself. PSPD is encoded 2506 * the same way as in USBSTATUS. 2507 */ 2508 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2509 } 2510 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2511 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2512 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2513 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2514 if (v & EHCI_PS_PR) i |= UPS_RESET; 2515 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2516 if (sc->sc_vendor_port_status) 2517 i = sc->sc_vendor_port_status(sc, v, i); 2518 USETW(ps.wPortStatus, i); 2519 i = 0; 2520 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2521 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2522 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2523 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2524 USETW(ps.wPortChange, i); 2525 totlen = min(len, sizeof(ps)); 2526 memcpy(buf, &ps, totlen); 2527 break; 2528 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2529 return -1; 2530 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2531 break; 2532 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2533 if (index < 1 || index > sc->sc_noport) { 2534 return -1; 2535 } 2536 port = EHCI_PORTSC(index); 2537 v = EOREAD4(sc, port); 2538 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2539 v &= ~EHCI_PS_CLEAR; 2540 switch(value) { 2541 case UHF_PORT_ENABLE: 2542 EOWRITE4(sc, port, v | EHCI_PS_PE); 2543 break; 2544 case UHF_PORT_SUSPEND: 2545 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2546 break; 2547 case UHF_PORT_RESET: 2548 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2549 if (EHCI_PS_IS_LOWSPEED(v) 2550 && sc->sc_ncomp > 0 2551 && !(sc->sc_flags & EHCIF_ETTF)) { 2552 /* 2553 * Low speed device on non-ETTF controller or 2554 * unaccompanied controller, give up ownership. 2555 */ 2556 ehci_disown(sc, index, 1); 2557 break; 2558 } 2559 /* Start reset sequence. */ 2560 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2561 EOWRITE4(sc, port, v | EHCI_PS_PR); 2562 /* Wait for reset to complete. */ 2563 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2564 if (sc->sc_dying) { 2565 return -1; 2566 } 2567 /* 2568 * An embedded transaction translator will automatically 2569 * terminate the reset sequence so there's no need to 2570 * it. 2571 */ 2572 v = EOREAD4(sc, port); 2573 if (v & EHCI_PS_PR) { 2574 /* Terminate reset sequence. */ 2575 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2576 /* Wait for HC to complete reset. */ 2577 usb_delay_ms(&sc->sc_bus, 2578 EHCI_PORT_RESET_COMPLETE); 2579 if (sc->sc_dying) { 2580 return -1; 2581 } 2582 } 2583 2584 v = EOREAD4(sc, port); 2585 USBHIST_LOG(ehcidebug, 2586 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2587 if (v & EHCI_PS_PR) { 2588 printf("%s: port reset timeout\n", 2589 device_xname(sc->sc_dev)); 2590 return USBD_TIMEOUT; 2591 } 2592 if (!(v & EHCI_PS_PE)) { 2593 /* Not a high speed device, give up ownership.*/ 2594 ehci_disown(sc, index, 0); 2595 break; 2596 } 2597 sc->sc_isreset[index] = 1; 2598 USBHIST_LOG(ehcidebug, 2599 "ehci port %d reset, status = 0x%08x", index, v, 0, 2600 0); 2601 break; 2602 case UHF_PORT_POWER: 2603 USBHIST_LOG(ehcidebug, 2604 "set port power %d (has PPC = %d)", index, 2605 sc->sc_hasppc, 0, 0); 2606 if (sc->sc_hasppc) 2607 EOWRITE4(sc, port, v | EHCI_PS_PP); 2608 break; 2609 case UHF_PORT_TEST: 2610 USBHIST_LOG(ehcidebug, "set port test %d", 2611 index, 0, 0, 0); 2612 break; 2613 case UHF_PORT_INDICATOR: 2614 USBHIST_LOG(ehcidebug, "set port ind %d", 2615 index, 0, 0, 0); 2616 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2617 break; 2618 default: 2619 return -1; 2620 } 2621 break; 2622 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2623 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2624 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2625 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2626 break; 2627 default: 2628 /* default from usbroothub */ 2629 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2630 buflen, 0, 0, 0); 2631 2632 return buflen; 2633 } 2634 2635 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2636 2637 return totlen; 2638 } 2639 2640 Static void 2641 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2642 { 2643 int port; 2644 uint32_t v; 2645 2646 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2647 2648 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2649 #ifdef DIAGNOSTIC 2650 if (sc->sc_npcomp != 0) { 2651 int i = (index-1) / sc->sc_npcomp; 2652 if (i >= sc->sc_ncomp) 2653 printf("%s: strange port\n", 2654 device_xname(sc->sc_dev)); 2655 else 2656 printf("%s: handing over %s speed device on " 2657 "port %d to %s\n", 2658 device_xname(sc->sc_dev), 2659 lowspeed ? "low" : "full", 2660 index, device_xname(sc->sc_comps[i])); 2661 } else { 2662 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2663 } 2664 #endif 2665 port = EHCI_PORTSC(index); 2666 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2667 EOWRITE4(sc, port, v | EHCI_PS_PO); 2668 } 2669 2670 Static usbd_status 2671 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2672 { 2673 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2674 usbd_status err; 2675 2676 /* Insert last in queue. */ 2677 mutex_enter(&sc->sc_lock); 2678 err = usb_insert_transfer(xfer); 2679 mutex_exit(&sc->sc_lock); 2680 if (err) 2681 return err; 2682 2683 /* Pipe isn't running, start first */ 2684 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2685 } 2686 2687 Static usbd_status 2688 ehci_root_intr_start(struct usbd_xfer *xfer) 2689 { 2690 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2691 2692 if (sc->sc_dying) 2693 return USBD_IOERROR; 2694 2695 mutex_enter(&sc->sc_lock); 2696 sc->sc_intrxfer = xfer; 2697 mutex_exit(&sc->sc_lock); 2698 2699 return USBD_IN_PROGRESS; 2700 } 2701 2702 /* Abort a root interrupt request. */ 2703 Static void 2704 ehci_root_intr_abort(struct usbd_xfer *xfer) 2705 { 2706 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2707 2708 KASSERT(mutex_owned(&sc->sc_lock)); 2709 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2710 2711 sc->sc_intrxfer = NULL; 2712 2713 xfer->ux_status = USBD_CANCELLED; 2714 usb_transfer_complete(xfer); 2715 } 2716 2717 /* Close the root pipe. */ 2718 Static void 2719 ehci_root_intr_close(struct usbd_pipe *pipe) 2720 { 2721 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2722 2723 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2724 2725 KASSERT(mutex_owned(&sc->sc_lock)); 2726 2727 sc->sc_intrxfer = NULL; 2728 } 2729 2730 Static void 2731 ehci_root_intr_done(struct usbd_xfer *xfer) 2732 { 2733 xfer->ux_hcpriv = NULL; 2734 } 2735 2736 /************************/ 2737 2738 Static ehci_soft_qh_t * 2739 ehci_alloc_sqh(ehci_softc_t *sc) 2740 { 2741 ehci_soft_qh_t *sqh; 2742 usbd_status err; 2743 int i, offs; 2744 usb_dma_t dma; 2745 2746 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2747 2748 mutex_enter(&sc->sc_lock); 2749 if (sc->sc_freeqhs == NULL) { 2750 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2751 mutex_exit(&sc->sc_lock); 2752 2753 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2754 EHCI_PAGE_SIZE, &dma); 2755 #ifdef EHCI_DEBUG 2756 if (err) 2757 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2758 #endif 2759 if (err) 2760 return NULL; 2761 2762 mutex_enter(&sc->sc_lock); 2763 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2764 offs = i * EHCI_SQH_SIZE; 2765 sqh = KERNADDR(&dma, offs); 2766 sqh->physaddr = DMAADDR(&dma, offs); 2767 sqh->dma = dma; 2768 sqh->offs = offs; 2769 sqh->next = sc->sc_freeqhs; 2770 sc->sc_freeqhs = sqh; 2771 } 2772 } 2773 sqh = sc->sc_freeqhs; 2774 sc->sc_freeqhs = sqh->next; 2775 mutex_exit(&sc->sc_lock); 2776 2777 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2778 sqh->next = NULL; 2779 return sqh; 2780 } 2781 2782 Static void 2783 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2784 { 2785 KASSERT(mutex_owned(&sc->sc_lock)); 2786 2787 sqh->next = sc->sc_freeqhs; 2788 sc->sc_freeqhs = sqh; 2789 } 2790 2791 Static ehci_soft_qtd_t * 2792 ehci_alloc_sqtd(ehci_softc_t *sc) 2793 { 2794 ehci_soft_qtd_t *sqtd = NULL; 2795 usbd_status err; 2796 int i, offs; 2797 usb_dma_t dma; 2798 2799 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2800 2801 mutex_enter(&sc->sc_lock); 2802 if (sc->sc_freeqtds == NULL) { 2803 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2804 mutex_exit(&sc->sc_lock); 2805 2806 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2807 EHCI_PAGE_SIZE, &dma); 2808 #ifdef EHCI_DEBUG 2809 if (err) 2810 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2811 #endif 2812 if (err) 2813 goto done; 2814 2815 mutex_enter(&sc->sc_lock); 2816 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2817 offs = i * EHCI_SQTD_SIZE; 2818 sqtd = KERNADDR(&dma, offs); 2819 sqtd->physaddr = DMAADDR(&dma, offs); 2820 sqtd->dma = dma; 2821 sqtd->offs = offs; 2822 2823 sqtd->nextqtd = sc->sc_freeqtds; 2824 sc->sc_freeqtds = sqtd; 2825 } 2826 } 2827 2828 sqtd = sc->sc_freeqtds; 2829 sc->sc_freeqtds = sqtd->nextqtd; 2830 mutex_exit(&sc->sc_lock); 2831 2832 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2833 sqtd->nextqtd = NULL; 2834 sqtd->xfer = NULL; 2835 2836 done: 2837 return sqtd; 2838 } 2839 2840 Static void 2841 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2842 { 2843 2844 mutex_enter(&sc->sc_lock); 2845 sqtd->nextqtd = sc->sc_freeqtds; 2846 sc->sc_freeqtds = sqtd; 2847 mutex_exit(&sc->sc_lock); 2848 } 2849 2850 Static usbd_status 2851 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2852 int alen, int rd, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2853 { 2854 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2855 ehci_soft_qtd_t *next, *cur; 2856 ehci_physaddr_t nextphys; 2857 uint32_t qtdstatus; 2858 int len, curlen, mps; 2859 int i, tog; 2860 int pages, pageoffs; 2861 size_t curoffs; 2862 vaddr_t va, va_offs; 2863 usb_dma_t *dma = &xfer->ux_dmabuf; 2864 uint16_t flags = xfer->ux_flags; 2865 paddr_t a; 2866 2867 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2868 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2869 2870 ASSERT_SLEEPABLE(); 2871 KASSERT(sp); 2872 KASSERT(alen != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2873 2874 len = alen; 2875 qtdstatus = EHCI_QTD_ACTIVE | 2876 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2877 EHCI_QTD_SET_CERR(3) 2878 ; 2879 2880 size_t nsqtd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 2881 nsqtd += ((len + EHCI_QTD_MAXTRANSFER - 1) / EHCI_QTD_MAXTRANSFER); 2882 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2883 KM_SLEEP); 2884 exfer->ex_nsqtd = nsqtd; 2885 2886 mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2887 cur = ehci_alloc_sqtd(sc); 2888 *sp = cur; 2889 if (cur == NULL) 2890 goto nomem; 2891 2892 curoffs = 0; 2893 for (size_t j = 0;;) { 2894 KASSERT(j < nsqtd); 2895 exfer->ex_sqtds[j++] = cur; 2896 2897 /* The EHCI hardware can handle at most 5 pages. */ 2898 va = (vaddr_t)KERNADDR(dma, curoffs); 2899 va_offs = EHCI_PAGE_OFFSET(va); 2900 if (len - curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2901 /* we can handle it in this QTD */ 2902 curlen = len - curoffs; 2903 } else { 2904 /* must use multiple TDs, fill as much as possible. */ 2905 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2906 2907 /* the length must be a multiple of the max size */ 2908 curlen -= curlen % mps; 2909 USBHIST_LOG(ehcidebug, "multiple QTDs, curlen=%d", 2910 curlen, 0, 0, 0); 2911 KASSERT(curlen != 0); 2912 } 2913 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", len, 2914 curlen, curoffs, 0); 2915 2916 /* 2917 * Allocate another transfer if there's more data left, 2918 * or if force last short transfer flag is set and we're 2919 * allocating a multiple of the max packet size. 2920 */ 2921 2922 if (curoffs + curlen != len || 2923 ((curlen % mps) == 0 && !rd && curlen != 0 && 2924 (flags & USBD_FORCE_SHORT_XFER))) { 2925 next = ehci_alloc_sqtd(sc); 2926 if (next == NULL) 2927 goto nomem; 2928 nextphys = htole32(next->physaddr); 2929 } else { 2930 next = NULL; 2931 nextphys = EHCI_NULL; 2932 } 2933 2934 /* Find number of pages we'll be using, insert dma addresses */ 2935 pages = EHCI_NPAGES(curlen); 2936 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2937 pageoffs = EHCI_PAGE(curoffs); 2938 for (i = 0; i < pages; i++) { 2939 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2940 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2941 /* Cast up to avoid compiler warnings */ 2942 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2943 } 2944 2945 /* First buffer pointer requires a page offset to start at */ 2946 cur->qtd.qtd_buffer[0] |= htole32(va_offs); 2947 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2948 cur->qtd.qtd_status = htole32(qtdstatus); 2949 cur->nextqtd = next; 2950 cur->xfer = xfer; 2951 cur->bufoff = curoffs; 2952 cur->tdlen = curlen; 2953 cur->len = 0; 2954 2955 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2956 curoffs, curoffs + curlen, 0, 0); 2957 2958 /* 2959 * adjust the toggle based on the number of packets in this 2960 * qtd 2961 */ 2962 if (((curlen + mps - 1) / mps) & 1) { 2963 tog ^= 1; 2964 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2965 } 2966 if (next == NULL) 2967 break; 2968 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2969 if (len) 2970 curoffs += curlen; 2971 cur = next; 2972 } 2973 if (ep) 2974 *ep = cur; 2975 2976 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", *sp, cur, 0, 0); 2977 2978 return USBD_NORMAL_COMPLETION; 2979 2980 nomem: 2981 ehci_free_sqtds(sc, exfer); 2982 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2983 return USBD_NOMEM; 2984 } 2985 2986 Static void 2987 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2988 { 2989 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2990 USBHIST_LOG(ehcidebug, "exfer=%p", exfer, 0, 0, 0); 2991 2992 mutex_enter(&sc->sc_lock); 2993 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2994 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2995 2996 if (sqtd == NULL) 2997 break; 2998 2999 sqtd->nextqtd = sc->sc_freeqtds; 3000 sc->sc_freeqtds = sqtd; 3001 } 3002 mutex_exit(&sc->sc_lock); 3003 } 3004 3005 Static void 3006 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3007 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3008 { 3009 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3010 ehci_soft_qtd_t *sqtd, *prev; 3011 int tog = *toggle; 3012 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3013 int len = length; 3014 size_t i; 3015 3016 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3017 USBHIST_LOG(ehcidebug, "xfer=%p len %d isread %d toggle %d", xfer, 3018 len, isread, *toggle); 3019 USBHIST_LOG(ehcidebug, " VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 3020 0, 0, 0); 3021 3022 sqtd = prev = NULL; 3023 for (i = 0; i < exfer->ex_nsqtd; i++, prev = sqtd) { 3024 sqtd = exfer->ex_sqtds[i]; 3025 vaddr_t va = (vaddr_t)KERNADDR(&xfer->ux_dmabuf, sqtd->bufoff); 3026 sqtd->len = sqtd->tdlen; 3027 if (len < sqtd->len) { 3028 sqtd->len = len; 3029 } 3030 3031 USBHIST_LOG(ehcidebug, "sqtd[%d]=%p prev %p len %d", i, sqtd, 3032 prev, sqtd->len); 3033 USBHIST_LOG(ehcidebug, " va %p bufoff %d pa %p", va, sqtd->bufoff, 3034 DMAADDR(&xfer->ux_dmabuf, sqtd->bufoff), 0); 3035 3036 if (prev) { 3037 prev->nextqtd = sqtd; 3038 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3039 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3040 } 3041 usb_syncmem(&sqtd->dma, 3042 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3043 sizeof(sqtd->qtd.qtd_status), 3044 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3045 usb_syncmem(&sqtd->dma, 3046 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3047 sizeof(sqtd->qtd.qtd_buffer[0]), 3048 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3049 3050 sqtd->qtd.qtd_buffer[0] &= ~htole32(EHCI_PAGE_MASK); 3051 sqtd->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3052 /* Reset ... */ 3053 sqtd->qtd.qtd_status &= ~htole32( 3054 EHCI_QTD_STATUS_MASK | 3055 EHCI_QTD_PID_MASK | 3056 EHCI_QTD_CERR_MASK | 3057 EHCI_QTD_C_PAGE_MASK | 3058 EHCI_QTD_BYTES_MASK | 3059 EHCI_QTD_TOGGLE_MASK); 3060 sqtd->qtd.qtd_status |= htole32( 3061 EHCI_QTD_ACTIVE | 3062 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3063 EHCI_QTD_SET_BYTES(sqtd->len) | 3064 EHCI_QTD_SET_CERR(3) | 3065 EHCI_QTD_SET_TOGGLE(tog)); 3066 3067 usb_syncmem(&sqtd->dma, 3068 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3069 sizeof(sqtd->qtd.qtd_status), 3070 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3071 usb_syncmem(&sqtd->dma, 3072 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3073 sizeof(sqtd->qtd.qtd_buffer[0]), 3074 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3075 3076 if (((sqtd->len + mps - 1) / mps) & 1) { 3077 tog ^= 1; 3078 } 3079 3080 len -= sqtd->len; 3081 if (len == 0) 3082 break; 3083 } 3084 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu i %zu", 3085 xfer, length, len, mps, exfer->ex_nsqtd, i); 3086 3087 if (i < exfer->ex_nsqtd) { 3088 /* 3089 * The full allocation chain wasn't used, so we need to 3090 * terminate it. 3091 */ 3092 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3093 } 3094 *lsqtd = sqtd; 3095 *toggle = tog; 3096 } 3097 3098 Static ehci_soft_itd_t * 3099 ehci_alloc_itd(ehci_softc_t *sc) 3100 { 3101 struct ehci_soft_itd *itd, *freeitd; 3102 usbd_status err; 3103 usb_dma_t dma; 3104 3105 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3106 3107 mutex_enter(&sc->sc_lock); 3108 3109 freeitd = LIST_FIRST(&sc->sc_freeitds); 3110 if (freeitd == NULL) { 3111 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3112 mutex_exit(&sc->sc_lock); 3113 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3114 EHCI_PAGE_SIZE, &dma); 3115 3116 if (err) { 3117 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 0); 3118 return NULL; 3119 } 3120 mutex_enter(&sc->sc_lock); 3121 3122 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3123 int offs = i * EHCI_ITD_SIZE; 3124 itd = KERNADDR(&dma, offs); 3125 itd->physaddr = DMAADDR(&dma, offs); 3126 itd->dma = dma; 3127 itd->offs = offs; 3128 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3129 } 3130 freeitd = LIST_FIRST(&sc->sc_freeitds); 3131 } 3132 3133 itd = freeitd; 3134 LIST_REMOVE(itd, free_list); 3135 mutex_exit(&sc->sc_lock); 3136 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3137 3138 itd->frame_list.next = NULL; 3139 itd->frame_list.prev = NULL; 3140 itd->xfer_next = NULL; 3141 itd->slot = 0; 3142 3143 return itd; 3144 } 3145 3146 Static ehci_soft_sitd_t * 3147 ehci_alloc_sitd(ehci_softc_t *sc) 3148 { 3149 struct ehci_soft_sitd *sitd, *freesitd; 3150 usbd_status err; 3151 int i, offs; 3152 usb_dma_t dma; 3153 3154 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3155 3156 mutex_enter(&sc->sc_lock); 3157 freesitd = LIST_FIRST(&sc->sc_freesitds); 3158 if (freesitd == NULL) { 3159 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3160 mutex_exit(&sc->sc_lock); 3161 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3162 EHCI_PAGE_SIZE, &dma); 3163 3164 if (err) { 3165 USBHIST_LOG(ehcidebug, "alloc returned %d", err, 0, 0, 3166 0); 3167 return NULL; 3168 } 3169 3170 mutex_enter(&sc->sc_lock); 3171 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3172 offs = i * EHCI_SITD_SIZE; 3173 sitd = KERNADDR(&dma, offs); 3174 sitd->physaddr = DMAADDR(&dma, offs); 3175 sitd->dma = dma; 3176 sitd->offs = offs; 3177 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3178 } 3179 freesitd = LIST_FIRST(&sc->sc_freesitds); 3180 } 3181 3182 sitd = freesitd; 3183 LIST_REMOVE(sitd, free_list); 3184 mutex_exit(&sc->sc_lock); 3185 3186 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3187 3188 sitd->frame_list.next = NULL; 3189 sitd->frame_list.prev = NULL; 3190 sitd->xfer_next = NULL; 3191 sitd->slot = 0; 3192 3193 return sitd; 3194 } 3195 3196 /****************/ 3197 3198 /* 3199 * Close a reqular pipe. 3200 * Assumes that there are no pending transactions. 3201 */ 3202 Static void 3203 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3204 { 3205 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3206 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3207 ehci_soft_qh_t *sqh = epipe->sqh; 3208 3209 KASSERT(mutex_owned(&sc->sc_lock)); 3210 3211 ehci_rem_qh(sc, sqh, head); 3212 ehci_free_sqh(sc, epipe->sqh); 3213 } 3214 3215 /* 3216 * Abort a device request. 3217 * If this routine is called at splusb() it guarantees that the request 3218 * will be removed from the hardware scheduling and that the callback 3219 * for it will be called with USBD_CANCELLED status. 3220 * It's impossible to guarantee that the requested transfer will not 3221 * have happened since the hardware runs concurrently. 3222 * If the transaction has already happened we rely on the ordinary 3223 * interrupt processing to process it. 3224 * XXX This is most probably wrong. 3225 * XXXMRG this doesn't make sense anymore. 3226 */ 3227 Static void 3228 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3229 { 3230 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3231 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3232 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3233 ehci_soft_qh_t *sqh = epipe->sqh; 3234 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3235 ehci_physaddr_t cur; 3236 uint32_t qhstatus; 3237 int hit; 3238 int wake; 3239 3240 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3241 3242 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3243 3244 KASSERT(mutex_owned(&sc->sc_lock)); 3245 ASSERT_SLEEPABLE(); 3246 3247 if (sc->sc_dying) { 3248 /* If we're dying, just do the software part. */ 3249 xfer->ux_status = status; /* make software ignore it */ 3250 callout_stop(&xfer->ux_callout); 3251 usb_transfer_complete(xfer); 3252 return; 3253 } 3254 3255 /* 3256 * If an abort is already in progress then just wait for it to 3257 * complete and return. 3258 */ 3259 if (xfer->ux_hcflags & UXFER_ABORTING) { 3260 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3261 #ifdef DIAGNOSTIC 3262 if (status == USBD_TIMEOUT) 3263 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3264 #endif 3265 /* Override the status which might be USBD_TIMEOUT. */ 3266 xfer->ux_status = status; 3267 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 0, 0, 0, 3268 0); 3269 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3270 while (xfer->ux_hcflags & UXFER_ABORTING) 3271 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3272 return; 3273 } 3274 xfer->ux_hcflags |= UXFER_ABORTING; 3275 3276 /* 3277 * Step 1: Make interrupt routine and hardware ignore xfer. 3278 */ 3279 xfer->ux_status = status; /* make software ignore it */ 3280 callout_stop(&xfer->ux_callout); 3281 ehci_del_intr_list(sc, exfer); 3282 3283 usb_syncmem(&sqh->dma, 3284 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3285 sizeof(sqh->qh.qh_qtd.qtd_status), 3286 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3287 qhstatus = sqh->qh.qh_qtd.qtd_status; 3288 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3289 usb_syncmem(&sqh->dma, 3290 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3291 sizeof(sqh->qh.qh_qtd.qtd_status), 3292 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3293 3294 if (exfer->ex_type == EX_CTRL) { 3295 fsqtd = exfer->ex_setup; 3296 lsqtd = exfer->ex_status; 3297 } else { 3298 fsqtd = exfer->ex_sqtdstart; 3299 lsqtd = exfer->ex_sqtdend; 3300 } 3301 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3302 usb_syncmem(&sqtd->dma, 3303 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3304 sizeof(sqtd->qtd.qtd_status), 3305 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3306 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3307 usb_syncmem(&sqtd->dma, 3308 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3309 sizeof(sqtd->qtd.qtd_status), 3310 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3311 if (sqtd == lsqtd) 3312 break; 3313 } 3314 3315 /* 3316 * Step 2: Wait until we know hardware has finished any possible 3317 * use of the xfer. Also make sure the soft interrupt routine 3318 * has run. 3319 */ 3320 ehci_sync_hc(sc); 3321 sc->sc_softwake = 1; 3322 usb_schedsoftintr(&sc->sc_bus); 3323 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3324 3325 /* 3326 * Step 3: Remove any vestiges of the xfer from the hardware. 3327 * The complication here is that the hardware may have executed 3328 * beyond the xfer we're trying to abort. So as we're scanning 3329 * the TDs of this xfer we check if the hardware points to 3330 * any of them. 3331 */ 3332 3333 usb_syncmem(&sqh->dma, 3334 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3335 sizeof(sqh->qh.qh_curqtd), 3336 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3337 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3338 hit = 0; 3339 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3340 hit |= cur == sqtd->physaddr; 3341 if (sqtd == lsqtd) 3342 break; 3343 } 3344 sqtd = sqtd->nextqtd; 3345 /* Zap curqtd register if hardware pointed inside the xfer. */ 3346 if (hit && sqtd != NULL) { 3347 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3348 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3349 usb_syncmem(&sqh->dma, 3350 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3351 sizeof(sqh->qh.qh_curqtd), 3352 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3353 sqh->qh.qh_qtd.qtd_status = qhstatus; 3354 usb_syncmem(&sqh->dma, 3355 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3356 sizeof(sqh->qh.qh_qtd.qtd_status), 3357 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3358 } else { 3359 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3360 usb_syncmem(&sqh->dma, 3361 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3362 sizeof(sqh->qh.qh_curqtd), 3363 BUS_DMASYNC_PREREAD); 3364 } 3365 3366 /* 3367 * Step 4: Execute callback. 3368 */ 3369 #ifdef DIAGNOSTIC 3370 exfer->ex_isdone = true; 3371 #endif 3372 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3373 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3374 usb_transfer_complete(xfer); 3375 if (wake) { 3376 cv_broadcast(&xfer->ux_hccv); 3377 } 3378 3379 KASSERT(mutex_owned(&sc->sc_lock)); 3380 } 3381 3382 Static void 3383 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3384 { 3385 ehci_isoc_trans_t trans_status; 3386 struct ehci_xfer *exfer; 3387 ehci_softc_t *sc; 3388 struct ehci_soft_itd *itd; 3389 struct ehci_soft_sitd *sitd; 3390 int i, wake; 3391 3392 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3393 3394 exfer = EHCI_XFER2EXFER(xfer); 3395 sc = EHCI_XFER2SC(xfer); 3396 3397 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3398 3399 KASSERT(mutex_owned(&sc->sc_lock)); 3400 3401 if (sc->sc_dying) { 3402 xfer->ux_status = status; 3403 callout_stop(&xfer->ux_callout); 3404 usb_transfer_complete(xfer); 3405 return; 3406 } 3407 3408 if (xfer->ux_hcflags & UXFER_ABORTING) { 3409 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3410 3411 #ifdef DIAGNOSTIC 3412 if (status == USBD_TIMEOUT) 3413 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3414 #endif 3415 3416 xfer->ux_status = status; 3417 USBHIST_LOG(ehcidebug, 3418 "waiting for abort to finish", 0, 0, 0, 0); 3419 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3420 while (xfer->ux_hcflags & UXFER_ABORTING) 3421 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3422 goto done; 3423 } 3424 xfer->ux_hcflags |= UXFER_ABORTING; 3425 3426 xfer->ux_status = status; 3427 callout_stop(&xfer->ux_callout); 3428 3429 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3430 for (itd = exfer->ex_itdstart; itd != NULL; 3431 itd = itd->xfer_next) { 3432 usb_syncmem(&itd->dma, 3433 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3434 sizeof(itd->itd.itd_ctl), 3435 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3436 3437 for (i = 0; i < 8; i++) { 3438 trans_status = le32toh(itd->itd.itd_ctl[i]); 3439 trans_status &= ~EHCI_ITD_ACTIVE; 3440 itd->itd.itd_ctl[i] = htole32(trans_status); 3441 } 3442 3443 usb_syncmem(&itd->dma, 3444 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3445 sizeof(itd->itd.itd_ctl), 3446 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3447 } 3448 } else { 3449 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3450 sitd = sitd->xfer_next) { 3451 usb_syncmem(&sitd->dma, 3452 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3453 sizeof(sitd->sitd.sitd_buffer), 3454 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3455 3456 trans_status = le32toh(sitd->sitd.sitd_trans); 3457 trans_status &= ~EHCI_SITD_ACTIVE; 3458 sitd->sitd.sitd_trans = htole32(trans_status); 3459 3460 usb_syncmem(&sitd->dma, 3461 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3462 sizeof(sitd->sitd.sitd_buffer), 3463 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3464 } 3465 } 3466 3467 sc->sc_softwake = 1; 3468 usb_schedsoftintr(&sc->sc_bus); 3469 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3470 3471 #ifdef DIAGNOSTIC 3472 exfer->ex_isdone = true; 3473 #endif 3474 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3475 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3476 usb_transfer_complete(xfer); 3477 if (wake) { 3478 cv_broadcast(&xfer->ux_hccv); 3479 } 3480 3481 done: 3482 KASSERT(mutex_owned(&sc->sc_lock)); 3483 return; 3484 } 3485 3486 Static void 3487 ehci_timeout(void *addr) 3488 { 3489 struct usbd_xfer *xfer = addr; 3490 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3491 struct usbd_pipe *pipe = xfer->ux_pipe; 3492 struct usbd_device *dev = pipe->up_dev; 3493 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3494 3495 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3496 3497 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3498 #ifdef EHCI_DEBUG 3499 if (ehcidebug >= 2) 3500 usbd_dump_pipe(pipe); 3501 #endif 3502 3503 if (sc->sc_dying) { 3504 mutex_enter(&sc->sc_lock); 3505 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3506 mutex_exit(&sc->sc_lock); 3507 return; 3508 } 3509 3510 /* Execute the abort in a process context. */ 3511 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3512 USB_TASKQ_MPSAFE); 3513 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3514 } 3515 3516 Static void 3517 ehci_timeout_task(void *addr) 3518 { 3519 struct usbd_xfer *xfer = addr; 3520 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3521 3522 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3523 3524 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3525 3526 mutex_enter(&sc->sc_lock); 3527 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3528 mutex_exit(&sc->sc_lock); 3529 } 3530 3531 /************************/ 3532 3533 Static int 3534 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3535 { 3536 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3537 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3538 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3539 usb_device_request_t *req = &xfer->ux_request; 3540 ehci_soft_qtd_t *setup, *status, *next; 3541 int isread = req->bmRequestType & UT_READ; 3542 int len = xfer->ux_bufsize; 3543 int err; 3544 3545 exfer->ex_type = EX_CTRL; 3546 exfer->ex_status = NULL; 3547 exfer->ex_data = NULL; 3548 exfer->ex_setup = ehci_alloc_sqtd(sc); 3549 if (exfer->ex_setup == NULL) { 3550 err = ENOMEM; 3551 goto bad1; 3552 } 3553 exfer->ex_status = ehci_alloc_sqtd(sc); 3554 if (exfer->ex_status == NULL) { 3555 err = ENOMEM; 3556 goto bad2; 3557 } 3558 setup = exfer->ex_setup; 3559 status = exfer->ex_status; 3560 exfer->ex_nsqtd = 0; 3561 next = status; 3562 /* Set up data transaction */ 3563 if (len != 0) { 3564 ehci_soft_qtd_t *end; 3565 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3566 &exfer->ex_data, &end); 3567 if (err) 3568 goto bad3; 3569 next = exfer->ex_data; 3570 } 3571 3572 /* Clear toggle */ 3573 setup->qtd.qtd_status = htole32( 3574 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3575 EHCI_QTD_SET_TOGGLE(0) | 3576 EHCI_QTD_SET_BYTES(sizeof(*req)) 3577 ); 3578 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3579 setup->qtd.qtd_buffer_hi[0] = 0; 3580 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3581 setup->nextqtd = next; 3582 setup->xfer = xfer; 3583 setup->tdlen = setup->len = sizeof(*req); 3584 3585 status->qtd.qtd_status = htole32( 3586 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3587 EHCI_QTD_SET_TOGGLE(1) | 3588 EHCI_QTD_IOC 3589 ); 3590 status->qtd.qtd_buffer[0] = 0; 3591 status->qtd.qtd_buffer_hi[0] = 0; 3592 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3593 status->nextqtd = NULL; 3594 status->xfer = xfer; 3595 status->tdlen = status->len = 0; 3596 3597 return 0; 3598 bad3: 3599 ehci_free_sqtd(sc, exfer->ex_status); 3600 bad2: 3601 ehci_free_sqtd(sc, exfer->ex_setup); 3602 bad1: 3603 return err; 3604 } 3605 3606 Static void 3607 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3608 { 3609 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3610 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3611 3612 KASSERT(ex->ex_type == EX_CTRL); 3613 3614 ehci_free_sqtd(sc, ex->ex_setup); 3615 ehci_free_sqtd(sc, ex->ex_status); 3616 ehci_free_sqtds(sc, ex); 3617 if (ex->ex_nsqtd) 3618 kmem_free(ex->ex_sqtds, 3619 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3620 } 3621 3622 Static usbd_status 3623 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3624 { 3625 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3626 usbd_status err; 3627 3628 /* Insert last in queue. */ 3629 mutex_enter(&sc->sc_lock); 3630 err = usb_insert_transfer(xfer); 3631 mutex_exit(&sc->sc_lock); 3632 if (err) 3633 return err; 3634 3635 /* Pipe isn't running, start first */ 3636 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3637 } 3638 3639 Static usbd_status 3640 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3641 { 3642 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3643 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3644 usb_device_request_t *req = &xfer->ux_request; 3645 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3646 ehci_soft_qtd_t *setup, *status, *next; 3647 ehci_soft_qh_t *sqh; 3648 3649 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3650 3651 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3652 3653 if (sc->sc_dying) 3654 return USBD_IOERROR; 3655 3656 const int isread = req->bmRequestType & UT_READ; 3657 const int len = UGETW(req->wLength); 3658 3659 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3660 "wValue=0x%04x, wIndex=0x%04x", 3661 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3662 UGETW(req->wIndex)); 3663 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3664 len, epipe->pipe.up_dev->ud_addr, 3665 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3666 3667 sqh = epipe->sqh; 3668 3669 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3670 "address QH %" __PRIuBIT " pipe %d\n", 3671 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3672 epipe->pipe.up_dev->ud_addr); 3673 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3674 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3675 "MPS QH %" __PRIuBIT " pipe %d\n", 3676 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3677 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3678 3679 setup = exfer->ex_setup; 3680 status = exfer->ex_status; 3681 3682 USBHIST_LOG(ehcidebug, "setup %p status %p data %p", 3683 setup, status, exfer->ex_data, 0); 3684 KASSERTMSG(setup != NULL && status != NULL, 3685 "Failed memory allocation, setup %p status %p", 3686 setup, status); 3687 3688 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3689 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3690 3691 /* Clear toggle */ 3692 setup->qtd.qtd_status &= ~htole32( 3693 EHCI_QTD_STATUS_MASK | 3694 EHCI_QTD_BYTES_MASK | 3695 EHCI_QTD_TOGGLE_MASK | 3696 EHCI_QTD_CERR_MASK 3697 ); 3698 setup->qtd.qtd_status |= htole32( 3699 EHCI_QTD_ACTIVE | 3700 EHCI_QTD_SET_CERR(3) | 3701 EHCI_QTD_SET_TOGGLE(0) | 3702 EHCI_QTD_SET_BYTES(sizeof(*req)) 3703 ); 3704 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3705 setup->qtd.qtd_buffer_hi[0] = 0; 3706 3707 next = status; 3708 status->qtd.qtd_status &= ~htole32( 3709 EHCI_QTD_STATUS_MASK | 3710 EHCI_QTD_PID_MASK | 3711 EHCI_QTD_BYTES_MASK | 3712 EHCI_QTD_TOGGLE_MASK | 3713 EHCI_QTD_CERR_MASK 3714 ); 3715 status->qtd.qtd_status |= htole32( 3716 EHCI_QTD_ACTIVE | 3717 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3718 EHCI_QTD_SET_CERR(3) | 3719 EHCI_QTD_SET_TOGGLE(1) | 3720 EHCI_QTD_SET_BYTES(0) | 3721 EHCI_QTD_IOC 3722 ); 3723 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3724 3725 KASSERT(exfer->ex_isdone); 3726 #ifdef DIAGNOSTIC 3727 exfer->ex_isdone = false; 3728 #endif 3729 3730 /* Set up data transaction */ 3731 if (len != 0) { 3732 ehci_soft_qtd_t *end; 3733 3734 /* Start toggle at 1. */ 3735 int toggle = 1; 3736 next = exfer->ex_data; 3737 KASSERTMSG(next != NULL, "Failed memory allocation"); 3738 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3739 end->nextqtd = status; 3740 end->qtd.qtd_next = end->qtd.qtd_altnext = 3741 htole32(status->physaddr); 3742 3743 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3744 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3745 3746 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3747 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3748 } 3749 3750 setup->nextqtd = next; 3751 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3752 3753 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3754 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3755 3756 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3757 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3758 3759 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3760 3761 #ifdef EHCI_DEBUG 3762 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3763 ehci_dump_sqh(sqh); 3764 ehci_dump_sqtds(setup); 3765 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3766 #endif 3767 3768 mutex_enter(&sc->sc_lock); 3769 3770 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3771 ehci_set_qh_qtd(sqh, setup); 3772 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3773 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3774 ehci_timeout, xfer); 3775 } 3776 ehci_add_intr_list(sc, exfer); 3777 xfer->ux_status = USBD_IN_PROGRESS; 3778 mutex_exit(&sc->sc_lock); 3779 3780 #if 0 3781 #ifdef EHCI_DEBUG 3782 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3783 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3784 // delay(10000); 3785 ehci_dump_regs(sc); 3786 ehci_dump_sqh(sc->sc_async_head); 3787 ehci_dump_sqh(sqh); 3788 ehci_dump_sqtds(setup); 3789 #endif 3790 #endif 3791 3792 if (sc->sc_bus.ub_usepolling) 3793 ehci_waitintr(sc, xfer); 3794 3795 return USBD_IN_PROGRESS; 3796 } 3797 3798 Static void 3799 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3800 { 3801 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3802 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3803 usb_device_request_t *req = &xfer->ux_request; 3804 int len = UGETW(req->wLength); 3805 int rd = req->bmRequestType & UT_READ; 3806 3807 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3808 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3809 3810 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3811 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3812 3813 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3814 BUS_DMASYNC_POSTWRITE); 3815 if (len) 3816 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3817 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3818 3819 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3820 } 3821 3822 /* Abort a device control request. */ 3823 Static void 3824 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3825 { 3826 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3827 3828 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3829 ehci_abort_xfer(xfer, USBD_CANCELLED); 3830 } 3831 3832 /* Close a device control pipe. */ 3833 Static void 3834 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3835 { 3836 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3837 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3838 3839 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3840 3841 KASSERT(mutex_owned(&sc->sc_lock)); 3842 3843 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3844 3845 ehci_close_pipe(pipe, sc->sc_async_head); 3846 } 3847 3848 /* 3849 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3850 * qTD status, or miss signalling occasionally under heavy load. If the host 3851 * machine is too fast, we we can miss transaction completion - when we scan 3852 * the active list the transaction still seems to be active. This generally 3853 * exhibits itself as a umass stall that never recovers. 3854 * 3855 * We work around this behaviour by setting up this callback after any softintr 3856 * that completes with transactions still pending, giving us another chance to 3857 * check for completion after the writeback has taken place. 3858 */ 3859 Static void 3860 ehci_intrlist_timeout(void *arg) 3861 { 3862 ehci_softc_t *sc = arg; 3863 3864 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3865 3866 usb_schedsoftintr(&sc->sc_bus); 3867 } 3868 3869 /************************/ 3870 3871 Static int 3872 ehci_device_bulk_init(struct usbd_xfer *xfer) 3873 { 3874 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3875 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3876 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3877 int endpt = ed->bEndpointAddress; 3878 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3879 int len = xfer->ux_bufsize; 3880 int err = 0; 3881 3882 exfer->ex_type = EX_BULK; 3883 exfer->ex_nsqtd = 0; 3884 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3885 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 3886 3887 return err; 3888 } 3889 3890 Static void 3891 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3892 { 3893 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3894 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3895 3896 KASSERT(ex->ex_type == EX_BULK); 3897 3898 ehci_free_sqtds(sc, ex); 3899 if (ex->ex_nsqtd) 3900 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3901 } 3902 3903 Static usbd_status 3904 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3905 { 3906 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3907 usbd_status err; 3908 3909 /* Insert last in queue. */ 3910 mutex_enter(&sc->sc_lock); 3911 err = usb_insert_transfer(xfer); 3912 mutex_exit(&sc->sc_lock); 3913 if (err) 3914 return err; 3915 3916 /* Pipe isn't running, start first */ 3917 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3918 } 3919 3920 Static usbd_status 3921 ehci_device_bulk_start(struct usbd_xfer *xfer) 3922 { 3923 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3924 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3925 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3926 ehci_soft_qh_t *sqh; 3927 ehci_soft_qtd_t *end; 3928 int len, isread, endpt; 3929 3930 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3931 3932 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3933 xfer, xfer->ux_length, xfer->ux_flags, 0); 3934 3935 if (sc->sc_dying) 3936 return USBD_IOERROR; 3937 3938 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3939 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3940 3941 len = xfer->ux_length; 3942 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3943 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3944 sqh = epipe->sqh; 3945 3946 KASSERT(exfer->ex_isdone); 3947 #ifdef DIAGNOSTIC 3948 exfer->ex_isdone = false; 3949 #endif 3950 3951 /* Take lock here to protect nexttoggle */ 3952 mutex_enter(&sc->sc_lock); 3953 3954 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3955 3956 exfer->ex_sqtdend = end; 3957 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3958 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3959 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3960 3961 #ifdef EHCI_DEBUG 3962 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3963 ehci_dump_sqh(sqh); 3964 ehci_dump_sqtds(exfer->ex_sqtdstart); 3965 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3966 #endif 3967 3968 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3969 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3970 3971 /* also does usb_syncmem(sqh) */ 3972 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3973 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3974 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3975 ehci_timeout, xfer); 3976 } 3977 ehci_add_intr_list(sc, exfer); 3978 xfer->ux_status = USBD_IN_PROGRESS; 3979 mutex_exit(&sc->sc_lock); 3980 3981 #if 0 3982 #ifdef EHCI_DEBUG 3983 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3984 // delay(10000); 3985 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3986 ehci_dump_regs(sc); 3987 #if 0 3988 printf("async_head:\n"); 3989 ehci_dump_sqh(sc->sc_async_head); 3990 #endif 3991 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3992 ehci_dump_sqh(sqh); 3993 ehci_dump_sqtds(exfer->ex_sqtdstart); 3994 #endif 3995 #endif 3996 3997 if (sc->sc_bus.ub_usepolling) 3998 ehci_waitintr(sc, xfer); 3999 4000 return USBD_IN_PROGRESS; 4001 } 4002 4003 Static void 4004 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4005 { 4006 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4007 4008 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 4009 ehci_abort_xfer(xfer, USBD_CANCELLED); 4010 } 4011 4012 /* 4013 * Close a device bulk pipe. 4014 */ 4015 Static void 4016 ehci_device_bulk_close(struct usbd_pipe *pipe) 4017 { 4018 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4019 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4020 4021 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4022 4023 KASSERT(mutex_owned(&sc->sc_lock)); 4024 4025 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 4026 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4027 ehci_close_pipe(pipe, sc->sc_async_head); 4028 } 4029 4030 Static void 4031 ehci_device_bulk_done(struct usbd_xfer *xfer) 4032 { 4033 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4034 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4035 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4036 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4037 4038 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4039 4040 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4041 0, 0); 4042 4043 KASSERT(mutex_owned(&sc->sc_lock)); 4044 4045 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4046 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4047 4048 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 4049 } 4050 4051 /************************/ 4052 4053 Static usbd_status 4054 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4055 { 4056 struct ehci_soft_islot *isp; 4057 int islot, lev; 4058 4059 /* Find a poll rate that is large enough. */ 4060 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4061 if (EHCI_ILEV_IVAL(lev) <= ival) 4062 break; 4063 4064 /* Pick an interrupt slot at the right level. */ 4065 /* XXX could do better than picking at random */ 4066 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4067 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4068 4069 sqh->islot = islot; 4070 isp = &sc->sc_islots[islot]; 4071 mutex_enter(&sc->sc_lock); 4072 ehci_add_qh(sc, sqh, isp->sqh); 4073 mutex_exit(&sc->sc_lock); 4074 4075 return USBD_NORMAL_COMPLETION; 4076 } 4077 4078 4079 Static int 4080 ehci_device_intr_init(struct usbd_xfer *xfer) 4081 { 4082 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4083 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4084 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4085 int endpt = ed->bEndpointAddress; 4086 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4087 int len = xfer->ux_bufsize; 4088 int err; 4089 4090 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4091 4092 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4093 xfer->ux_flags, 0); 4094 4095 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4096 KASSERT(len != 0); 4097 4098 exfer->ex_type = EX_INTR; 4099 exfer->ex_nsqtd = 0; 4100 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4101 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 4102 4103 return err; 4104 } 4105 4106 Static void 4107 ehci_device_intr_fini(struct usbd_xfer *xfer) 4108 { 4109 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4110 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4111 4112 KASSERT(ex->ex_type == EX_INTR); 4113 4114 ehci_free_sqtds(sc, ex); 4115 if (ex->ex_nsqtd) 4116 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4117 } 4118 4119 Static usbd_status 4120 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4121 { 4122 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4123 usbd_status err; 4124 4125 /* Insert last in queue. */ 4126 mutex_enter(&sc->sc_lock); 4127 err = usb_insert_transfer(xfer); 4128 mutex_exit(&sc->sc_lock); 4129 if (err) 4130 return err; 4131 4132 /* 4133 * Pipe isn't running (otherwise err would be USBD_INPROG), 4134 * so start it first. 4135 */ 4136 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4137 } 4138 4139 Static usbd_status 4140 ehci_device_intr_start(struct usbd_xfer *xfer) 4141 { 4142 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4143 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4144 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4145 ehci_soft_qtd_t *end; 4146 ehci_soft_qh_t *sqh; 4147 int len, isread, endpt; 4148 4149 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4150 4151 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4152 xfer->ux_flags, 0); 4153 4154 if (sc->sc_dying) 4155 return USBD_IOERROR; 4156 4157 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4158 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4159 4160 len = xfer->ux_length; 4161 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4162 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4163 sqh = epipe->sqh; 4164 4165 KASSERT(exfer->ex_isdone); 4166 #ifdef DIAGNOSTIC 4167 exfer->ex_isdone = false; 4168 #endif 4169 4170 /* Take lock to protect nexttoggle */ 4171 mutex_enter(&sc->sc_lock); 4172 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4173 4174 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4175 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4177 exfer->ex_sqtdend = end; 4178 4179 #ifdef EHCI_DEBUG 4180 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 4181 ehci_dump_sqh(sqh); 4182 ehci_dump_sqtds(exfer->ex_sqtdstart); 4183 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 4184 #endif 4185 4186 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4187 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4188 4189 /* also does usb_syncmem(sqh) */ 4190 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4191 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4192 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4193 ehci_timeout, xfer); 4194 } 4195 ehci_add_intr_list(sc, exfer); 4196 xfer->ux_status = USBD_IN_PROGRESS; 4197 mutex_exit(&sc->sc_lock); 4198 4199 #if 0 4200 #ifdef EHCI_DEBUG 4201 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4202 // delay(10000); 4203 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4204 ehci_dump_regs(sc); 4205 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4206 ehci_dump_sqh(sqh); 4207 ehci_dump_sqtds(exfer->ex_sqtdstart); 4208 #endif 4209 #endif 4210 4211 if (sc->sc_bus.ub_usepolling) 4212 ehci_waitintr(sc, xfer); 4213 4214 return USBD_IN_PROGRESS; 4215 } 4216 4217 Static void 4218 ehci_device_intr_abort(struct usbd_xfer *xfer) 4219 { 4220 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4221 4222 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4223 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4224 4225 /* 4226 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4227 * async doorbell. That's dependent on the async list, wheras 4228 * intr xfers are periodic, should not use this? 4229 */ 4230 ehci_abort_xfer(xfer, USBD_CANCELLED); 4231 } 4232 4233 Static void 4234 ehci_device_intr_close(struct usbd_pipe *pipe) 4235 { 4236 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4237 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4238 struct ehci_soft_islot *isp; 4239 4240 KASSERT(mutex_owned(&sc->sc_lock)); 4241 4242 isp = &sc->sc_islots[epipe->sqh->islot]; 4243 ehci_close_pipe(pipe, isp->sqh); 4244 } 4245 4246 Static void 4247 ehci_device_intr_done(struct usbd_xfer *xfer) 4248 { 4249 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4250 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4251 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4252 ehci_soft_qh_t *sqh; 4253 int len, isread, endpt; 4254 4255 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4256 4257 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4258 0, 0); 4259 4260 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4261 4262 if (xfer->ux_pipe->up_repeat) { 4263 4264 KASSERT(exfer->ex_isdone); 4265 #ifdef DIAGNOSTIC 4266 exfer->ex_isdone = false; 4267 #endif 4268 4269 len = xfer->ux_length; 4270 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4271 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4272 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4273 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4274 sqh = epipe->sqh; 4275 4276 ehci_soft_qtd_t *end; 4277 ehci_reset_sqtd_chain(sc, xfer, len, isread, 4278 &epipe->nexttoggle, &end); 4279 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4280 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4282 4283 exfer->ex_sqtdend = end; 4284 4285 /* also does usb_syncmem(sqh) */ 4286 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4287 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4288 callout_reset(&xfer->ux_callout, 4289 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4290 } 4291 ehci_add_intr_list(sc, exfer); 4292 xfer->ux_status = USBD_IN_PROGRESS; 4293 } else { 4294 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4295 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4296 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4297 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4298 } 4299 } 4300 4301 /************************/ 4302 Static int 4303 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4304 { 4305 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4306 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4307 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4308 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4309 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4310 int i, k, frames; 4311 u_int huba, dir; 4312 int err; 4313 4314 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4315 4316 start = NULL; 4317 sitd = NULL; 4318 4319 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", xfer, xfer->ux_length, 4320 xfer->ux_flags, 0); 4321 4322 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4323 KASSERT(xfer->ux_nframes != 0); 4324 KASSERT(exfer->ex_isdone); 4325 4326 exfer->ex_type = EX_FS_ISOC; 4327 /* 4328 * Step 1: Allocate and initialize sitds. 4329 */ 4330 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4331 if (i > 16 || i == 0) { 4332 /* Spec page 271 says intervals > 16 are invalid */ 4333 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4334 4335 return EINVAL; 4336 } 4337 4338 frames = xfer->ux_nframes; 4339 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4340 sitd = ehci_alloc_sitd(sc); 4341 if (sitd == NULL) { 4342 err = ENOMEM; 4343 goto fail; 4344 } 4345 4346 if (prev) 4347 prev->xfer_next = sitd; 4348 else 4349 start = sitd; 4350 4351 huba = dev->ud_myhsport->up_parent->ud_addr; 4352 4353 #if 0 4354 if (sc->sc_flags & EHCIF_FREESCALE) { 4355 // Set hub address to 0 if embedded TT is used. 4356 if (huba == sc->sc_addr) 4357 huba = 0; 4358 } 4359 #endif 4360 4361 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4362 dir = UE_GET_DIR(k) ? 1 : 0; 4363 sitd->sitd.sitd_endp = 4364 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4365 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4366 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4367 EHCI_SITD_SET_HUBA(huba) | 4368 EHCI_SITD_SET_DIR(dir)); 4369 4370 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4371 } /* End of frame */ 4372 4373 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4374 4375 stop = sitd; 4376 stop->xfer_next = NULL; 4377 exfer->ex_sitdstart = start; 4378 exfer->ex_sitdend = stop; 4379 4380 return 0; 4381 4382 fail: 4383 mutex_enter(&sc->sc_lock); 4384 ehci_soft_sitd_t *next; 4385 for (sitd = start; sitd; sitd = next) { 4386 next = sitd->xfer_next; 4387 ehci_free_sitd_locked(sc, sitd); 4388 } 4389 mutex_exit(&sc->sc_lock); 4390 4391 return err; 4392 } 4393 4394 Static void 4395 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4396 { 4397 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4398 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4399 4400 KASSERT(ex->ex_type == EX_FS_ISOC); 4401 4402 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4403 } 4404 4405 Static usbd_status 4406 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4407 { 4408 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4409 usbd_status err; 4410 4411 mutex_enter(&sc->sc_lock); 4412 err = usb_insert_transfer(xfer); 4413 mutex_exit(&sc->sc_lock); 4414 4415 if (err && err != USBD_IN_PROGRESS) 4416 return err; 4417 4418 return ehci_device_fs_isoc_start(xfer); 4419 } 4420 4421 Static usbd_status 4422 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4423 { 4424 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4425 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4426 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4427 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4428 ehci_soft_sitd_t *sitd; 4429 usb_dma_t *dma_buf; 4430 int i, j, k, frames; 4431 int offs, total_length; 4432 int frindex; 4433 u_int dir; 4434 4435 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4436 4437 sitd = NULL; 4438 total_length = 0; 4439 4440 /* 4441 * To allow continuous transfers, above we start all transfers 4442 * immediately. However, we're still going to get usbd_start_next call 4443 * this when another xfer completes. So, check if this is already 4444 * in progress or not 4445 */ 4446 4447 if (exfer->ex_isrunning) { 4448 return USBD_IN_PROGRESS; 4449 } 4450 4451 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4452 xfer, xfer->ux_length, xfer->ux_flags, 0); 4453 4454 if (sc->sc_dying) 4455 return USBD_IOERROR; 4456 4457 /* 4458 * To avoid complication, don't allow a request right now that'll span 4459 * the entire frame table. To within 4 frames, to allow some leeway 4460 * on either side of where the hc currently is. 4461 */ 4462 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4463 xfer->ux_nframes >= sc->sc_flsize - 4) { 4464 printf("ehci: isoc descriptor requested that spans the entire" 4465 "frametable, too many frames\n"); 4466 return USBD_INVAL; 4467 } 4468 4469 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4470 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4471 KASSERT(exfer->ex_isdone); 4472 #ifdef DIAGNOSTIC 4473 exfer->ex_isdone = false; 4474 #endif 4475 4476 /* 4477 * Step 1: Initialize sitds. 4478 */ 4479 4480 frames = xfer->ux_nframes; 4481 dma_buf = &xfer->ux_dmabuf; 4482 offs = 0; 4483 4484 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4485 i++, sitd = sitd->xfer_next) { 4486 KASSERT(sitd != NULL); 4487 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4488 4489 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4490 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4491 4492 /* Set page0 index and offset - TP and T-offset are set below */ 4493 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4494 4495 total_length += xfer->ux_frlengths[i]; 4496 offs += xfer->ux_frlengths[i]; 4497 4498 sitd->sitd.sitd_buffer[1] = 4499 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4500 4501 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4502 4503 #if 0 4504 if (sc->sc_flags & EHCIF_FREESCALE) { 4505 // Set hub address to 0 if embedded TT is used. 4506 if (huba == sc->sc_addr) 4507 huba = 0; 4508 } 4509 #endif 4510 4511 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4512 dir = UE_GET_DIR(k) ? 1 : 0; 4513 KASSERT(sitd->sitd.sitd_endp == htole32( 4514 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4515 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4516 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4517 EHCI_SITD_SET_HUBA(huba) | 4518 EHCI_SITD_SET_DIR(dir))); 4519 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4520 4521 uint8_t sa = 0; 4522 uint8_t sb = 0; 4523 u_int temp, tlen; 4524 4525 if (dir == 0) { /* OUT */ 4526 temp = 0; 4527 tlen = xfer->ux_frlengths[i]; 4528 if (tlen <= 188) { 4529 temp |= 1; /* T-count = 1, TP = ALL */ 4530 tlen = 1; 4531 } else { 4532 tlen += 187; 4533 tlen /= 188; 4534 temp |= tlen; /* T-count = [1..6] */ 4535 temp |= 8; /* TP = Begin */ 4536 } 4537 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4538 4539 tlen += sa; 4540 4541 if (tlen >= 8) { 4542 sb = 0; 4543 } else { 4544 sb = (1 << tlen); 4545 } 4546 4547 sa = (1 << sa); 4548 sa = (sb - sa) & 0x3F; 4549 sb = 0; 4550 } else { 4551 sb = (-(4 << sa)) & 0xFE; 4552 sa = (1 << sa) & 0x3F; 4553 sa = 0x01; 4554 sb = 0xfc; 4555 } 4556 4557 sitd->sitd.sitd_sched = htole32( 4558 EHCI_SITD_SET_SMASK(sa) | 4559 EHCI_SITD_SET_CMASK(sb) 4560 ); 4561 4562 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4563 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4564 } /* End of frame */ 4565 4566 sitd = exfer->ex_sitdend; 4567 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4568 4569 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4570 sizeof(sitd->sitd.sitd_trans), 4571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4572 4573 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4574 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4575 4576 /* 4577 * Part 2: Transfer descriptors have now been set up, now they must 4578 * be scheduled into the periodic frame list. Erk. Not wanting to 4579 * complicate matters, transfer is denied if the transfer spans 4580 * more than the period frame list. 4581 */ 4582 4583 mutex_enter(&sc->sc_lock); 4584 4585 /* Start inserting frames */ 4586 if (epipe->isoc.cur_xfers > 0) { 4587 frindex = epipe->isoc.next_frame; 4588 } else { 4589 frindex = EOREAD4(sc, EHCI_FRINDEX); 4590 frindex = frindex >> 3; /* Erase microframe index */ 4591 frindex += 2; 4592 } 4593 4594 if (frindex >= sc->sc_flsize) 4595 frindex &= (sc->sc_flsize - 1); 4596 4597 /* Whats the frame interval? */ 4598 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4599 4600 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4601 j++, sitd = sitd->xfer_next) { 4602 KASSERT(sitd); 4603 4604 usb_syncmem(&sc->sc_fldma, 4605 sizeof(ehci_link_t) * frindex, 4606 sizeof(ehci_link_t), 4607 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4608 4609 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4610 if (sitd->sitd.sitd_next == 0) 4611 /* 4612 * FIXME: frindex table gets initialized to NULL 4613 * or EHCI_NULL? 4614 */ 4615 sitd->sitd.sitd_next = EHCI_NULL; 4616 4617 usb_syncmem(&sitd->dma, 4618 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4619 sizeof(ehci_sitd_t), 4620 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4621 4622 sc->sc_flist[frindex] = 4623 htole32(EHCI_LINK_SITD | sitd->physaddr); 4624 4625 usb_syncmem(&sc->sc_fldma, 4626 sizeof(ehci_link_t) * frindex, 4627 sizeof(ehci_link_t), 4628 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4629 4630 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4631 sc->sc_softsitds[frindex] = sitd; 4632 if (sitd->frame_list.next != NULL) 4633 sitd->frame_list.next->frame_list.prev = sitd; 4634 sitd->slot = frindex; 4635 sitd->frame_list.prev = NULL; 4636 4637 frindex += i; 4638 if (frindex >= sc->sc_flsize) 4639 frindex -= sc->sc_flsize; 4640 } 4641 4642 epipe->isoc.cur_xfers++; 4643 epipe->isoc.next_frame = frindex; 4644 4645 exfer->ex_isrunning = true; 4646 4647 ehci_add_intr_list(sc, exfer); 4648 xfer->ux_status = USBD_IN_PROGRESS; 4649 4650 mutex_exit(&sc->sc_lock); 4651 4652 if (sc->sc_bus.ub_usepolling) { 4653 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4654 ehci_waitintr(sc, xfer); 4655 } 4656 4657 return USBD_IN_PROGRESS; 4658 } 4659 4660 Static void 4661 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4662 { 4663 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4664 4665 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4666 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4667 } 4668 4669 Static void 4670 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4671 { 4672 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4673 4674 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4675 } 4676 4677 Static void 4678 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4679 { 4680 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4681 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4682 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4683 4684 KASSERT(mutex_owned(&sc->sc_lock)); 4685 4686 epipe->isoc.cur_xfers--; 4687 if (exfer->ex_isrunning) { 4688 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4689 exfer->ex_isrunning = false; 4690 } 4691 4692 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4693 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4694 } 4695 4696 4697 /************************/ 4698 4699 4700 Static int 4701 ehci_device_isoc_init(struct usbd_xfer *xfer) 4702 { 4703 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4704 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4705 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4706 ehci_soft_itd_t *itd, *prev, *start, *stop; 4707 int i, j, k; 4708 int frames, ufrperframe; 4709 int err; 4710 4711 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4712 4713 start = NULL; 4714 prev = NULL; 4715 itd = NULL; 4716 4717 KASSERT(xfer->ux_nframes != 0); 4718 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4719 KASSERT(exfer->ex_isdone); 4720 4721 exfer->ex_type = EX_ISOC; 4722 4723 /* 4724 * Step 1: Allocate and initialize itds, how many do we need? 4725 * One per transfer if interval >= 8 microframes, less if we use 4726 * multiple microframes per frame. 4727 */ 4728 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4729 if (i > 16 || i == 0) { 4730 /* Spec page 271 says intervals > 16 are invalid */ 4731 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4732 return USBD_INVAL; 4733 } 4734 4735 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4736 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4737 4738 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4739 itd = ehci_alloc_itd(sc); 4740 if (itd == NULL) { 4741 err = ENOMEM; 4742 goto fail; 4743 } 4744 4745 if (prev != NULL) { 4746 /* Maybe not as it's updated by the scheduling? */ 4747 prev->itd.itd_next = 4748 htole32(itd->physaddr | EHCI_LINK_ITD); 4749 4750 prev->xfer_next = itd; 4751 } else { 4752 start = itd; 4753 } 4754 4755 /* 4756 * Other special values 4757 */ 4758 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4759 itd->itd.itd_bufr[0] = htole32( 4760 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4761 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4762 4763 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4764 ? 1 : 0; 4765 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4766 itd->itd.itd_bufr[1] |= htole32( 4767 EHCI_ITD_SET_DIR(k) | 4768 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4769 4770 /* FIXME: handle invalid trans - should be done in openpipe */ 4771 itd->itd.itd_bufr[2] |= 4772 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4773 } /* End of frame */ 4774 4775 stop = itd; 4776 stop->xfer_next = NULL; 4777 4778 exfer->ex_itdstart = start; 4779 exfer->ex_itdend = stop; 4780 4781 return 0; 4782 fail: 4783 mutex_enter(&sc->sc_lock); 4784 ehci_soft_itd_t *next; 4785 for (itd = start; itd; itd = next) { 4786 next = itd->xfer_next; 4787 ehci_free_itd_locked(sc, itd); 4788 } 4789 mutex_exit(&sc->sc_lock); 4790 4791 return err; 4792 4793 } 4794 4795 Static void 4796 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4797 { 4798 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4799 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4800 4801 KASSERT(ex->ex_type == EX_ISOC); 4802 4803 ehci_free_itd_chain(sc, ex->ex_itdstart); 4804 } 4805 4806 Static usbd_status 4807 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4808 { 4809 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4810 usbd_status err; 4811 4812 mutex_enter(&sc->sc_lock); 4813 err = usb_insert_transfer(xfer); 4814 mutex_exit(&sc->sc_lock); 4815 if (err && err != USBD_IN_PROGRESS) 4816 return err; 4817 4818 return ehci_device_isoc_start(xfer); 4819 } 4820 4821 Static usbd_status 4822 ehci_device_isoc_start(struct usbd_xfer *xfer) 4823 { 4824 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4825 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4826 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4827 ehci_soft_itd_t *itd, *prev; 4828 usb_dma_t *dma_buf; 4829 int i, j; 4830 int frames, uframes, ufrperframe; 4831 int trans_count, offs, total_length; 4832 int frindex; 4833 4834 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4835 4836 prev = NULL; 4837 itd = NULL; 4838 trans_count = 0; 4839 total_length = 0; 4840 4841 /* 4842 * To allow continuous transfers, above we start all transfers 4843 * immediately. However, we're still going to get usbd_start_next call 4844 * this when another xfer completes. So, check if this is already 4845 * in progress or not 4846 */ 4847 4848 if (exfer->ex_isrunning) { 4849 return USBD_IN_PROGRESS; 4850 } 4851 4852 USBHIST_LOG(ehcidebug, "xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4853 4854 if (sc->sc_dying) 4855 return USBD_IOERROR; 4856 4857 /* 4858 * To avoid complication, don't allow a request right now that'll span 4859 * the entire frame table. To within 4 frames, to allow some leeway 4860 * on either side of where the hc currently is. 4861 */ 4862 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4863 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4864 USBHIST_LOG(ehcidebug, 4865 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4866 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4867 return USBD_INVAL; 4868 } 4869 4870 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4871 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4872 KASSERT(exfer->ex_isdone); 4873 #ifdef DIAGNOSTIC 4874 exfer->ex_isdone = false; 4875 #endif 4876 4877 /* 4878 * Step 1: Re-Initialize itds 4879 */ 4880 4881 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4882 if (i > 16 || i == 0) { 4883 /* Spec page 271 says intervals > 16 are invalid */ 4884 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4885 return USBD_INVAL; 4886 } 4887 4888 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4889 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4890 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4891 4892 if (frames == 0) { 4893 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4894 return USBD_INVAL; 4895 } 4896 4897 dma_buf = &xfer->ux_dmabuf; 4898 offs = 0; 4899 4900 itd = exfer->ex_itdstart; 4901 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4902 int froffs = offs; 4903 4904 if (prev != NULL) { 4905 prev->itd.itd_next = 4906 htole32(itd->physaddr | EHCI_LINK_ITD); 4907 usb_syncmem(&prev->dma, 4908 prev->offs + offsetof(ehci_itd_t, itd_next), 4909 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4910 prev->xfer_next = itd; 4911 } 4912 4913 /* 4914 * Step 1.5, initialize uframes 4915 */ 4916 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4917 /* Calculate which page in the list this starts in */ 4918 int addr = DMAADDR(dma_buf, froffs); 4919 addr = EHCI_PAGE_OFFSET(addr); 4920 addr += (offs - froffs); 4921 addr = EHCI_PAGE(addr); 4922 addr /= EHCI_PAGE_SIZE; 4923 4924 /* 4925 * This gets the initial offset into the first page, 4926 * looks how far further along the current uframe 4927 * offset is. Works out how many pages that is. 4928 */ 4929 4930 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4931 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4932 EHCI_ITD_SET_PG(addr) | 4933 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4934 4935 total_length += xfer->ux_frlengths[trans_count]; 4936 offs += xfer->ux_frlengths[trans_count]; 4937 trans_count++; 4938 4939 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4940 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4941 break; 4942 } 4943 } 4944 4945 /* 4946 * Step 1.75, set buffer pointers. To simplify matters, all 4947 * pointers are filled out for the next 7 hardware pages in 4948 * the dma block, so no need to worry what pages to cover 4949 * and what to not. 4950 */ 4951 4952 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4953 /* 4954 * Don't try to lookup a page that's past the end 4955 * of buffer 4956 */ 4957 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4958 if (page_offs >= dma_buf->udma_block->size) 4959 break; 4960 4961 uint64_t page = DMAADDR(dma_buf, page_offs); 4962 page = EHCI_PAGE(page); 4963 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4964 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4965 } 4966 /* 4967 * Other special values 4968 */ 4969 4970 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4971 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4972 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4973 4974 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4975 ? 1 : 0; 4976 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4977 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4978 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4979 4980 /* FIXME: handle invalid trans */ 4981 itd->itd.itd_bufr[2] |= 4982 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4983 4984 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4985 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4986 4987 prev = itd; 4988 } /* End of frame */ 4989 4990 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4991 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4992 4993 /* 4994 * Part 2: Transfer descriptors have now been set up, now they must 4995 * be scheduled into the period frame list. Erk. Not wanting to 4996 * complicate matters, transfer is denied if the transfer spans 4997 * more than the period frame list. 4998 */ 4999 5000 mutex_enter(&sc->sc_lock); 5001 5002 /* Start inserting frames */ 5003 if (epipe->isoc.cur_xfers > 0) { 5004 frindex = epipe->isoc.next_frame; 5005 } else { 5006 frindex = EOREAD4(sc, EHCI_FRINDEX); 5007 frindex = frindex >> 3; /* Erase microframe index */ 5008 frindex += 2; 5009 } 5010 5011 if (frindex >= sc->sc_flsize) 5012 frindex &= (sc->sc_flsize - 1); 5013 5014 /* What's the frame interval? */ 5015 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 5016 if (i / USB_UFRAMES_PER_FRAME == 0) 5017 i = 1; 5018 else 5019 i /= USB_UFRAMES_PER_FRAME; 5020 5021 itd = exfer->ex_itdstart; 5022 for (j = 0; j < frames; j++) { 5023 KASSERTMSG(itd != NULL, "frame %d\n", j); 5024 5025 usb_syncmem(&sc->sc_fldma, 5026 sizeof(ehci_link_t) * frindex, 5027 sizeof(ehci_link_t), 5028 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5029 5030 itd->itd.itd_next = sc->sc_flist[frindex]; 5031 if (itd->itd.itd_next == 0) 5032 /* 5033 * FIXME: frindex table gets initialized to NULL 5034 * or EHCI_NULL? 5035 */ 5036 itd->itd.itd_next = EHCI_NULL; 5037 5038 usb_syncmem(&itd->dma, 5039 itd->offs + offsetof(ehci_itd_t, itd_next), 5040 sizeof(itd->itd.itd_next), 5041 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5042 5043 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 5044 5045 usb_syncmem(&sc->sc_fldma, 5046 sizeof(ehci_link_t) * frindex, 5047 sizeof(ehci_link_t), 5048 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5049 5050 itd->frame_list.next = sc->sc_softitds[frindex]; 5051 sc->sc_softitds[frindex] = itd; 5052 if (itd->frame_list.next != NULL) 5053 itd->frame_list.next->frame_list.prev = itd; 5054 itd->slot = frindex; 5055 itd->frame_list.prev = NULL; 5056 5057 frindex += i; 5058 if (frindex >= sc->sc_flsize) 5059 frindex -= sc->sc_flsize; 5060 5061 itd = itd->xfer_next; 5062 } 5063 5064 epipe->isoc.cur_xfers++; 5065 epipe->isoc.next_frame = frindex; 5066 5067 exfer->ex_isrunning = true; 5068 5069 ehci_add_intr_list(sc, exfer); 5070 xfer->ux_status = USBD_IN_PROGRESS; 5071 5072 mutex_exit(&sc->sc_lock); 5073 5074 if (sc->sc_bus.ub_usepolling) { 5075 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 5076 ehci_waitintr(sc, xfer); 5077 } 5078 5079 return USBD_IN_PROGRESS; 5080 } 5081 5082 Static void 5083 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5084 { 5085 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5086 5087 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 5088 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5089 } 5090 5091 Static void 5092 ehci_device_isoc_close(struct usbd_pipe *pipe) 5093 { 5094 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 5095 5096 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 5097 } 5098 5099 Static void 5100 ehci_device_isoc_done(struct usbd_xfer *xfer) 5101 { 5102 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5103 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5104 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5105 5106 KASSERT(mutex_owned(&sc->sc_lock)); 5107 5108 epipe->isoc.cur_xfers--; 5109 if (exfer->ex_isrunning) { 5110 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5111 exfer->ex_isrunning = false; 5112 } 5113 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5114 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5115 } 5116
Indexes created Wed Oct 01 19:09:53 GMT 2025