ehci.c revision 1.234.2.93
1 /* $NetBSD: ehci.c,v 1.234.2.93 2016/03/20 08:06:15 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.93 2016/03/20 08:06:15 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_timeout(void *); 171 Static void ehci_timeout_task(void *); 172 Static void ehci_intrlist_timeout(void *); 173 Static void ehci_doorbell(void *); 174 Static void ehci_pcd(void *); 175 176 Static struct usbd_xfer * 177 ehci_allocx(struct usbd_bus *, unsigned int); 178 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 179 180 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 181 Static int ehci_roothub_ctrl(struct usbd_bus *, 182 usb_device_request_t *, void *, int); 183 184 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 185 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 186 Static void ehci_root_intr_abort(struct usbd_xfer *); 187 Static void ehci_root_intr_close(struct usbd_pipe *); 188 Static void ehci_root_intr_done(struct usbd_xfer *); 189 190 Static int ehci_device_ctrl_init(struct usbd_xfer *); 191 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 193 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 194 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 195 Static void ehci_device_ctrl_close(struct usbd_pipe *); 196 Static void ehci_device_ctrl_done(struct usbd_xfer *); 197 198 Static int ehci_device_bulk_init(struct usbd_xfer *); 199 Static void ehci_device_bulk_fini(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 201 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 202 Static void ehci_device_bulk_abort(struct usbd_xfer *); 203 Static void ehci_device_bulk_close(struct usbd_pipe *); 204 Static void ehci_device_bulk_done(struct usbd_xfer *); 205 206 Static int ehci_device_intr_init(struct usbd_xfer *); 207 Static void ehci_device_intr_fini(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 209 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 210 Static void ehci_device_intr_abort(struct usbd_xfer *); 211 Static void ehci_device_intr_close(struct usbd_pipe *); 212 Static void ehci_device_intr_done(struct usbd_xfer *); 213 214 Static int ehci_device_isoc_init(struct usbd_xfer *); 215 Static void ehci_device_isoc_fini(struct usbd_xfer *); 216 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 217 Static void ehci_device_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_isoc_done(struct usbd_xfer *); 220 221 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 223 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 225 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 226 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 227 228 Static void ehci_device_clear_toggle(struct usbd_pipe *); 229 Static void ehci_noop(struct usbd_pipe *); 230 231 Static void ehci_disown(ehci_softc_t *, int, int); 232 233 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 234 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 235 236 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 237 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 238 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 239 int, int, ehci_soft_qtd_t **, ehci_soft_qtd_t **); 240 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 241 242 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 243 int, int, int *, ehci_soft_qtd_t **); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_softwake_cv, "ehciab"); 416 cv_init(&sc->sc_doorbell, "ehcidi"); 417 418 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 419 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 420 421 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 422 ehci_doorbell, sc); 423 KASSERT(sc->sc_doorbell_si != NULL); 424 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 425 ehci_pcd, sc); 426 KASSERT(sc->sc_pcd_si != NULL); 427 428 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 429 430 vers = EREAD2(sc, EHCI_HCIVERSION); 431 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 432 vers >> 8, vers & 0xff); 433 434 sparams = EREAD4(sc, EHCI_HCSPARAMS); 435 DPRINTF("sparams=%#x", sparams, 0, 0, 0); 436 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 437 ncomp = EHCI_HCS_N_CC(sparams); 438 if (ncomp != sc->sc_ncomp) { 439 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 440 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 441 #if NOHCI == 0 || NUHCI == 0 442 aprint_error("%s: ohci or uhci probably not configured\n", 443 device_xname(sc->sc_dev)); 444 #endif 445 if (ncomp < sc->sc_ncomp) 446 sc->sc_ncomp = ncomp; 447 } 448 if (sc->sc_ncomp > 0) { 449 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 450 aprint_normal("%s: companion controller%s, %d port%s each:", 451 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 452 EHCI_HCS_N_PCC(sparams), 453 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 454 for (i = 0; i < sc->sc_ncomp; i++) 455 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 456 aprint_normal("\n"); 457 } 458 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 459 cparams = EREAD4(sc, EHCI_HCCPARAMS); 460 DPRINTF("cparams=%#x", cparams, 0, 0, 0); 461 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 462 463 if (EHCI_HCC_64BIT(cparams)) { 464 /* MUST clear segment register if 64 bit capable. */ 465 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 466 } 467 468 sc->sc_bus.ub_revision = USBREV_2_0; 469 sc->sc_bus.ub_usedma = true; 470 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 471 472 /* Reset the controller */ 473 DPRINTF("resetting", 0, 0, 0, 0); 474 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 475 usb_delay_ms(&sc->sc_bus, 1); 476 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 477 for (i = 0; i < 100; i++) { 478 usb_delay_ms(&sc->sc_bus, 1); 479 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 480 if (!hcr) 481 break; 482 } 483 if (hcr) { 484 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 485 return EIO; 486 } 487 if (sc->sc_vendor_init) 488 sc->sc_vendor_init(sc); 489 490 /* XXX need proper intr scheduling */ 491 sc->sc_rand = 96; 492 493 /* frame list size at default, read back what we got and use that */ 494 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 495 case 0: sc->sc_flsize = 1024; break; 496 case 1: sc->sc_flsize = 512; break; 497 case 2: sc->sc_flsize = 256; break; 498 case 3: return EIO; 499 } 500 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 501 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 502 if (err) 503 return err; 504 DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); 505 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 506 507 for (i = 0; i < sc->sc_flsize; i++) { 508 sc->sc_flist[i] = EHCI_NULL; 509 } 510 511 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 512 513 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 514 KM_SLEEP); 515 if (sc->sc_softitds == NULL) 516 return ENOMEM; 517 LIST_INIT(&sc->sc_freeitds); 518 LIST_INIT(&sc->sc_freesitds); 519 TAILQ_INIT(&sc->sc_intrhead); 520 521 /* Set up the bus struct. */ 522 sc->sc_bus.ub_methods = &ehci_bus_methods; 523 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 524 525 sc->sc_eintrs = EHCI_NORMAL_INTRS; 526 527 /* 528 * Allocate the interrupt dummy QHs. These are arranged to give poll 529 * intervals that are powers of 2 times 1ms. 530 */ 531 for (i = 0; i < EHCI_INTRQHS; i++) { 532 sqh = ehci_alloc_sqh(sc); 533 if (sqh == NULL) { 534 err = ENOMEM; 535 goto bad1; 536 } 537 sc->sc_islots[i].sqh = sqh; 538 } 539 for (i = 0; i < EHCI_INTRQHS; i++) { 540 sqh = sc->sc_islots[i].sqh; 541 if (i == 0) { 542 /* The last (1ms) QH terminates. */ 543 sqh->qh.qh_link = EHCI_NULL; 544 sqh->next = NULL; 545 } else { 546 /* Otherwise the next QH has half the poll interval */ 547 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 548 sqh->qh.qh_link = htole32(sqh->next->physaddr | 549 EHCI_LINK_QH); 550 } 551 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 552 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 553 sqh->qh.qh_curqtd = EHCI_NULL; 554 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 555 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 556 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 557 sqh->sqtd = NULL; 558 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 559 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 560 } 561 /* Point the frame list at the last level (128ms). */ 562 for (i = 0; i < sc->sc_flsize; i++) { 563 int j; 564 565 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 566 revbits[i & (EHCI_MAX_POLLRATE-1)]; 567 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 568 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 569 i)].sqh->physaddr); 570 } 571 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 572 BUS_DMASYNC_PREWRITE); 573 574 /* Allocate dummy QH that starts the async list. */ 575 sqh = ehci_alloc_sqh(sc); 576 if (sqh == NULL) { 577 err = ENOMEM; 578 goto bad1; 579 } 580 /* Fill the QH */ 581 sqh->qh.qh_endp = 582 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 583 sqh->qh.qh_link = 584 htole32(sqh->physaddr | EHCI_LINK_QH); 585 sqh->qh.qh_curqtd = EHCI_NULL; 586 sqh->next = NULL; 587 /* Fill the overlay qTD */ 588 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 589 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 590 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 591 sqh->sqtd = NULL; 592 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 593 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 594 #ifdef EHCI_DEBUG 595 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 596 ehci_dump_sqh(sqh); 597 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 598 #endif 599 600 /* Point to async list */ 601 sc->sc_async_head = sqh; 602 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 603 604 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 605 606 /* Turn on controller */ 607 EOWRITE4(sc, EHCI_USBCMD, 608 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 609 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 610 EHCI_CMD_ASE | 611 EHCI_CMD_PSE | 612 EHCI_CMD_RS); 613 614 /* Take over port ownership */ 615 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 616 617 for (i = 0; i < 100; i++) { 618 usb_delay_ms(&sc->sc_bus, 1); 619 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 620 if (!hcr) 621 break; 622 } 623 if (hcr) { 624 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 625 return EIO; 626 } 627 628 /* Enable interrupts */ 629 DPRINTF("enabling interupts", 0, 0, 0, 0); 630 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 631 632 return 0; 633 634 #if 0 635 bad2: 636 ehci_free_sqh(sc, sc->sc_async_head); 637 #endif 638 bad1: 639 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 640 return err; 641 } 642 643 int 644 ehci_intr(void *v) 645 { 646 ehci_softc_t *sc = v; 647 int ret = 0; 648 649 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 650 651 if (sc == NULL) 652 return 0; 653 654 mutex_spin_enter(&sc->sc_intr_lock); 655 656 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 657 goto done; 658 659 /* If we get an interrupt while polling, then just ignore it. */ 660 if (sc->sc_bus.ub_usepolling) { 661 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 662 663 if (intrs) 664 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 665 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 666 goto done; 667 } 668 669 ret = ehci_intr1(sc); 670 671 done: 672 mutex_spin_exit(&sc->sc_intr_lock); 673 return ret; 674 } 675 676 Static int 677 ehci_intr1(ehci_softc_t *sc) 678 { 679 uint32_t intrs, eintrs; 680 681 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 682 683 /* In case the interrupt occurs before initialization has completed. */ 684 if (sc == NULL) { 685 #ifdef DIAGNOSTIC 686 printf("ehci_intr1: sc == NULL\n"); 687 #endif 688 return 0; 689 } 690 691 KASSERT(mutex_owned(&sc->sc_intr_lock)); 692 693 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 694 if (!intrs) 695 return 0; 696 697 eintrs = intrs & sc->sc_eintrs; 698 DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, 699 EOREAD4(sc, EHCI_USBSTS), eintrs); 700 if (!eintrs) 701 return 0; 702 703 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 704 if (eintrs & EHCI_STS_IAA) { 705 DPRINTF("door bell", 0, 0, 0, 0); 706 kpreempt_disable(); 707 KASSERT(sc->sc_doorbell_si != NULL); 708 softint_schedule(sc->sc_doorbell_si); 709 kpreempt_enable(); 710 eintrs &= ~EHCI_STS_IAA; 711 } 712 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 713 DPRINTF("INT=%d ERRINT=%d", 714 eintrs & EHCI_STS_INT ? 1 : 0, 715 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 716 usb_schedsoftintr(&sc->sc_bus); 717 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 718 } 719 if (eintrs & EHCI_STS_HSE) { 720 printf("%s: unrecoverable error, controller halted\n", 721 device_xname(sc->sc_dev)); 722 /* XXX what else */ 723 } 724 if (eintrs & EHCI_STS_PCD) { 725 kpreempt_disable(); 726 KASSERT(sc->sc_pcd_si != NULL); 727 softint_schedule(sc->sc_pcd_si); 728 kpreempt_enable(); 729 eintrs &= ~EHCI_STS_PCD; 730 } 731 732 if (eintrs != 0) { 733 /* Block unprocessed interrupts. */ 734 sc->sc_eintrs &= ~eintrs; 735 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 736 printf("%s: blocking intrs 0x%x\n", 737 device_xname(sc->sc_dev), eintrs); 738 } 739 740 return 1; 741 } 742 743 Static void 744 ehci_doorbell(void *addr) 745 { 746 ehci_softc_t *sc = addr; 747 748 mutex_enter(&sc->sc_lock); 749 cv_broadcast(&sc->sc_doorbell); 750 mutex_exit(&sc->sc_lock); 751 } 752 753 Static void 754 ehci_pcd(void *addr) 755 { 756 ehci_softc_t *sc = addr; 757 struct usbd_xfer *xfer; 758 u_char *p; 759 int i, m; 760 761 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 762 763 mutex_enter(&sc->sc_lock); 764 xfer = sc->sc_intrxfer; 765 766 if (xfer == NULL) { 767 /* Just ignore the change. */ 768 goto done; 769 } 770 771 p = xfer->ux_buf; 772 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 773 memset(p, 0, xfer->ux_length); 774 for (i = 1; i <= m; i++) { 775 /* Pick out CHANGE bits from the status reg. */ 776 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 777 p[i/8] |= 1 << (i%8); 778 if (i % 8 == 7) 779 DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); 780 } 781 xfer->ux_actlen = xfer->ux_length; 782 xfer->ux_status = USBD_NORMAL_COMPLETION; 783 784 usb_transfer_complete(xfer); 785 786 done: 787 mutex_exit(&sc->sc_lock); 788 } 789 790 Static void 791 ehci_softintr(void *v) 792 { 793 struct usbd_bus *bus = v; 794 ehci_softc_t *sc = EHCI_BUS2SC(bus); 795 struct ehci_xfer *ex, *nextex; 796 797 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 798 799 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 800 801 ex_completeq_t cq; 802 TAILQ_INIT(&cq); 803 804 /* 805 * The only explanation I can think of for why EHCI is as brain dead 806 * as UHCI interrupt-wise is that Intel was involved in both. 807 * An interrupt just tells us that something is done, we have no 808 * clue what, so we need to scan through all active transfers. :-( 809 */ 810 811 /* 812 * ehci_idone will remove transfer from sc->sc_intrhead if it's 813 * complete and add to our cq list 814 * */ 815 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 816 switch (ex->ex_type) { 817 case EX_CTRL: 818 case EX_BULK: 819 case EX_INTR: 820 ehci_check_qh_intr(sc, ex, &cq); 821 break; 822 case EX_ISOC: 823 ehci_check_itd_intr(sc, ex, &cq); 824 break; 825 case EX_FS_ISOC: 826 ehci_check_sitd_intr(sc, ex, &cq); 827 break; 828 default: 829 KASSERT(false); 830 } 831 832 } 833 834 /* 835 * We abuse ex_next for the interrupt and complete lists and 836 * interrupt transfers will get re-added here so use 837 * the _SAFE version of TAILQ_FOREACH. 838 */ 839 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 840 usb_transfer_complete(&ex->ex_xfer); 841 } 842 843 /* Schedule a callout to catch any dropped transactions. */ 844 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 845 !TAILQ_EMPTY(&sc->sc_intrhead)) 846 callout_reset(&sc->sc_tmo_intrlist, 847 hz, ehci_intrlist_timeout, sc); 848 849 if (sc->sc_softwake) { 850 sc->sc_softwake = 0; 851 cv_broadcast(&sc->sc_softwake_cv); 852 } 853 } 854 855 Static void 856 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 857 { 858 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 859 uint32_t status; 860 861 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 862 863 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 864 865 if (ex->ex_type == EX_CTRL) { 866 fsqtd = ex->ex_setup; 867 lsqtd = ex->ex_status; 868 } else { 869 fsqtd = ex->ex_sqtdstart; 870 lsqtd = ex->ex_sqtdend; 871 } 872 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 873 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 874 875 /* 876 * If the last TD is still active we need to check whether there 877 * is an error somewhere in the middle, or whether there was a 878 * short packet (SPD and not ACTIVE). 879 */ 880 usb_syncmem(&lsqtd->dma, 881 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 882 sizeof(lsqtd->qtd.qtd_status), 883 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 884 status = le32toh(lsqtd->qtd.qtd_status); 885 usb_syncmem(&lsqtd->dma, 886 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 887 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 888 if (status & EHCI_QTD_ACTIVE) { 889 DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); 890 891 /* last qTD has already been checked */ 892 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 893 usb_syncmem(&sqtd->dma, 894 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 895 sizeof(sqtd->qtd.qtd_status), 896 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 897 status = le32toh(sqtd->qtd.qtd_status); 898 usb_syncmem(&sqtd->dma, 899 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 900 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 901 /* If there's an active QTD the xfer isn't done. */ 902 if (status & EHCI_QTD_ACTIVE) 903 break; 904 /* Any kind of error makes the xfer done. */ 905 if (status & EHCI_QTD_HALTED) 906 goto done; 907 /* Handle short packets */ 908 if (EHCI_QTD_GET_BYTES(status) != 0) { 909 /* 910 * If we get here for a control transfer then 911 * we need to let the hardware complete the 912 * status phase. That is, we're not done 913 * quite yet. 914 * 915 * Otherwise, we're done. 916 */ 917 if (ex->ex_type == EX_CTRL) { 918 break; 919 } 920 goto done; 921 } 922 } 923 DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, 924 0, 0); 925 #ifdef EHCI_DEBUG 926 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 927 ehci_dump_sqtds(ex->ex_sqtdstart); 928 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 929 #endif 930 return; 931 } 932 done: 933 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 934 callout_stop(&ex->ex_xfer.ux_callout); 935 ehci_idone(ex, cq); 936 } 937 938 Static void 939 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 940 { 941 ehci_soft_itd_t *itd; 942 int i; 943 944 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 945 946 KASSERT(mutex_owned(&sc->sc_lock)); 947 948 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 949 return; 950 951 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 952 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 953 954 itd = ex->ex_itdend; 955 956 /* 957 * check no active transfers in last itd, meaning we're finished 958 */ 959 960 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 961 sizeof(itd->itd.itd_ctl), 962 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 963 964 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 965 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 966 break; 967 } 968 969 if (i == EHCI_ITD_NUFRAMES) { 970 goto done; /* All 8 descriptors inactive, it's done */ 971 } 972 973 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 974 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 975 976 DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); 977 return; 978 done: 979 DPRINTF("ex %p done", ex, 0, 0, 0); 980 callout_stop(&ex->ex_xfer.ux_callout); 981 ehci_idone(ex, cq); 982 } 983 984 void 985 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 986 { 987 ehci_soft_sitd_t *sitd; 988 989 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 990 991 KASSERT(mutex_owned(&sc->sc_lock)); 992 993 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 994 return; 995 996 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 997 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 998 999 sitd = ex->ex_sitdend; 1000 1001 /* 1002 * check no active transfers in last sitd, meaning we're finished 1003 */ 1004 1005 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1006 sizeof(sitd->sitd.sitd_trans), 1007 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1008 1009 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1010 1011 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1012 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1013 1014 if (active) 1015 return; 1016 1017 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 1018 callout_stop(&(ex->ex_xfer.ux_callout)); 1019 ehci_idone(ex, cq); 1020 } 1021 1022 1023 Static void 1024 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1025 { 1026 struct usbd_xfer *xfer = &ex->ex_xfer; 1027 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1028 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1029 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1030 uint32_t status = 0, nstatus = 0; 1031 int actlen = 0; 1032 1033 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1034 1035 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1036 1037 DPRINTF("ex=%p", ex, 0, 0, 0); 1038 1039 if (xfer->ux_status == USBD_CANCELLED || 1040 xfer->ux_status == USBD_TIMEOUT) { 1041 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1042 return; 1043 } 1044 1045 #ifdef DIAGNOSTIC 1046 #ifdef EHCI_DEBUG 1047 if (ex->ex_isdone) { 1048 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1049 ehci_dump_exfer(ex); 1050 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1051 } 1052 #endif 1053 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1054 ex->ex_type, xfer->ux_status); 1055 ex->ex_isdone = true; 1056 #endif 1057 1058 DPRINTF("xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1059 1060 /* The transfer is done, compute actual length and status. */ 1061 if (ex->ex_type == EX_ISOC) { 1062 /* HS isoc transfer */ 1063 1064 struct ehci_soft_itd *itd; 1065 int i, nframes, len, uframes; 1066 1067 nframes = 0; 1068 1069 #ifdef EHCI_DEBUG 1070 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1071 ehci_dump_itds(ex->ex_itdstart); 1072 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1073 #endif 1074 1075 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1076 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1077 1078 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1079 usb_syncmem(&itd->dma, 1080 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1081 sizeof(itd->itd.itd_ctl), 1082 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1083 1084 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1085 /* 1086 * XXX - driver didn't fill in the frame full 1087 * of uframes. This leads to scheduling 1088 * inefficiencies, but working around 1089 * this doubles complexity of tracking 1090 * an xfer. 1091 */ 1092 if (nframes >= xfer->ux_nframes) 1093 break; 1094 1095 status = le32toh(itd->itd.itd_ctl[i]); 1096 len = EHCI_ITD_GET_LEN(status); 1097 if (EHCI_ITD_GET_STATUS(status) != 0) 1098 len = 0; /*No valid data on error*/ 1099 1100 xfer->ux_frlengths[nframes++] = len; 1101 actlen += len; 1102 } 1103 usb_syncmem(&itd->dma, 1104 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1105 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1106 1107 if (nframes >= xfer->ux_nframes) 1108 break; 1109 } 1110 1111 xfer->ux_actlen = actlen; 1112 xfer->ux_status = USBD_NORMAL_COMPLETION; 1113 goto end; 1114 } else if (ex->ex_type == EX_FS_ISOC) { 1115 /* FS isoc transfer */ 1116 struct ehci_soft_sitd *sitd; 1117 int nframes, len; 1118 1119 nframes = 0; 1120 1121 for (sitd = ex->ex_sitdstart; sitd != NULL; 1122 sitd = sitd->xfer_next) { 1123 usb_syncmem(&sitd->dma, 1124 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1125 sizeof(sitd->sitd.sitd_trans), 1126 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1127 1128 /* 1129 * XXX - driver didn't fill in the frame full 1130 * of uframes. This leads to scheduling 1131 * inefficiencies, but working around 1132 * this doubles complexity of tracking 1133 * an xfer. 1134 */ 1135 if (nframes >= xfer->ux_nframes) 1136 break; 1137 1138 status = le32toh(sitd->sitd.sitd_trans); 1139 usb_syncmem(&sitd->dma, 1140 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1141 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1142 1143 len = EHCI_SITD_GET_LEN(status); 1144 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1145 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1146 /* No valid data on error */ 1147 len = xfer->ux_frlengths[nframes]; 1148 } 1149 1150 /* 1151 * frlengths[i]: # of bytes to send 1152 * len: # of bytes host didn't send 1153 */ 1154 xfer->ux_frlengths[nframes] -= len; 1155 /* frlengths[i]: # of bytes host sent */ 1156 actlen += xfer->ux_frlengths[nframes++]; 1157 1158 if (nframes >= xfer->ux_nframes) 1159 break; 1160 } 1161 1162 xfer->ux_actlen = actlen; 1163 xfer->ux_status = USBD_NORMAL_COMPLETION; 1164 goto end; 1165 } 1166 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1167 ex->ex_type == EX_BULK); 1168 1169 /* Continue processing xfers using queue heads */ 1170 if (ex->ex_type == EX_CTRL) { 1171 fsqtd = ex->ex_setup; 1172 lsqtd = ex->ex_status; 1173 } else { 1174 fsqtd = ex->ex_sqtdstart; 1175 lsqtd = ex->ex_sqtdend; 1176 } 1177 #ifdef EHCI_DEBUG 1178 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1179 ehci_dump_sqtds(fsqtd); 1180 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1181 #endif 1182 1183 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1184 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1185 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1186 nstatus = le32toh(sqtd->qtd.qtd_status); 1187 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1188 BUS_DMASYNC_PREREAD); 1189 if (nstatus & EHCI_QTD_ACTIVE) 1190 break; 1191 1192 status = nstatus; 1193 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1194 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1195 } 1196 1197 /* 1198 * If there are left over TDs we need to update the toggle. 1199 * The default pipe doesn't need it since control transfers 1200 * start the toggle at 0 every time. 1201 * For a short transfer we need to update the toggle for the missing 1202 * packets within the qTD. 1203 */ 1204 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1205 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1206 DPRINTF("toggle update status=0x%08x nstatus=0x%08x", 1207 status, nstatus, 0, 0); 1208 #if 0 1209 ehci_dump_sqh(epipe->sqh); 1210 ehci_dump_sqtds(ex->ex_sqtdstart); 1211 #endif 1212 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1213 } 1214 1215 DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, 1216 status, 0); 1217 xfer->ux_actlen = actlen; 1218 if (status & EHCI_QTD_HALTED) { 1219 #ifdef EHCI_DEBUG 1220 DPRINTF("halted addr=%d endpt=0x%02x", 1221 xfer->ux_pipe->up_dev->ud_addr, 1222 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1223 0, 0); 1224 DPRINTF("cerr=%d pid=%d", 1225 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1226 0, 0); 1227 DPRINTF("active =%d halted=%d buferr=%d babble=%d", 1228 status & EHCI_QTD_ACTIVE ? 1 : 0, 1229 status & EHCI_QTD_HALTED ? 1 : 0, 1230 status & EHCI_QTD_BUFERR ? 1 : 0, 1231 status & EHCI_QTD_BABBLE ? 1 : 0); 1232 1233 DPRINTF("xacterr=%d missed=%d split =%d ping =%d", 1234 status & EHCI_QTD_XACTERR ? 1 : 0, 1235 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1236 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1237 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1238 1239 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1240 ehci_dump_sqh(epipe->sqh); 1241 ehci_dump_sqtds(ex->ex_sqtdstart); 1242 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1243 #endif 1244 /* low&full speed has an extra error flag */ 1245 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1246 EHCI_QH_SPEED_HIGH) 1247 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1248 else 1249 status &= EHCI_QTD_STATERRS; 1250 if (status == 0) /* no other errors means a stall */ { 1251 xfer->ux_status = USBD_STALLED; 1252 } else { 1253 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1254 } 1255 /* XXX need to reset TT on missed microframe */ 1256 if (status & EHCI_QTD_MISSEDMICRO) { 1257 printf("%s: missed microframe, TT reset not " 1258 "implemented, hub might be inoperational\n", 1259 device_xname(sc->sc_dev)); 1260 } 1261 } else { 1262 xfer->ux_status = USBD_NORMAL_COMPLETION; 1263 } 1264 1265 end: 1266 1267 ehci_del_intr_list(sc, ex); 1268 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1269 1270 DPRINTF("ex=%p done", ex, 0, 0, 0); 1271 } 1272 1273 /* 1274 * Wait here until controller claims to have an interrupt. 1275 * Then call ehci_intr and return. Use timeout to avoid waiting 1276 * too long. 1277 */ 1278 Static void 1279 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1280 { 1281 int timo; 1282 uint32_t intrs; 1283 1284 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1285 1286 xfer->ux_status = USBD_IN_PROGRESS; 1287 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1288 usb_delay_ms(&sc->sc_bus, 1); 1289 if (sc->sc_dying) 1290 break; 1291 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1292 sc->sc_eintrs; 1293 DPRINTF("0x%04x", intrs, 0, 0, 0); 1294 #ifdef EHCI_DEBUG 1295 if (ehcidebug >= 15) 1296 ehci_dump_regs(sc); 1297 #endif 1298 if (intrs) { 1299 mutex_spin_enter(&sc->sc_intr_lock); 1300 ehci_intr1(sc); 1301 mutex_spin_exit(&sc->sc_intr_lock); 1302 if (xfer->ux_status != USBD_IN_PROGRESS) 1303 return; 1304 } 1305 } 1306 1307 /* Timeout */ 1308 DPRINTF("timeout", 0, 0, 0, 0); 1309 xfer->ux_status = USBD_TIMEOUT; 1310 mutex_enter(&sc->sc_lock); 1311 usb_transfer_complete(xfer); 1312 mutex_exit(&sc->sc_lock); 1313 } 1314 1315 Static void 1316 ehci_poll(struct usbd_bus *bus) 1317 { 1318 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1319 1320 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1321 1322 #ifdef EHCI_DEBUG 1323 static int last; 1324 int new; 1325 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1326 if (new != last) { 1327 DPRINTF("intrs=0x%04x", new, 0, 0, 0); 1328 last = new; 1329 } 1330 #endif 1331 1332 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1333 mutex_spin_enter(&sc->sc_intr_lock); 1334 ehci_intr1(sc); 1335 mutex_spin_exit(&sc->sc_intr_lock); 1336 } 1337 } 1338 1339 void 1340 ehci_childdet(device_t self, device_t child) 1341 { 1342 struct ehci_softc *sc = device_private(self); 1343 1344 KASSERT(sc->sc_child == child); 1345 sc->sc_child = NULL; 1346 } 1347 1348 int 1349 ehci_detach(struct ehci_softc *sc, int flags) 1350 { 1351 int rv = 0; 1352 1353 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1354 1355 if (sc->sc_child != NULL) 1356 rv = config_detach(sc->sc_child, flags); 1357 1358 if (rv != 0) 1359 return rv; 1360 1361 callout_halt(&sc->sc_tmo_intrlist, NULL); 1362 callout_destroy(&sc->sc_tmo_intrlist); 1363 1364 /* XXX free other data structures XXX */ 1365 if (sc->sc_softitds) 1366 kmem_free(sc->sc_softitds, 1367 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1368 cv_destroy(&sc->sc_doorbell); 1369 cv_destroy(&sc->sc_softwake_cv); 1370 1371 #if 0 1372 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1373 1374 softint_disestablish(sc->sc_doorbell_si); 1375 softint_disestablish(sc->sc_pcd_si); 1376 1377 mutex_destroy(&sc->sc_lock); 1378 mutex_destroy(&sc->sc_intr_lock); 1379 #endif 1380 1381 pool_cache_destroy(sc->sc_xferpool); 1382 1383 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1384 1385 return rv; 1386 } 1387 1388 1389 int 1390 ehci_activate(device_t self, enum devact act) 1391 { 1392 struct ehci_softc *sc = device_private(self); 1393 1394 switch (act) { 1395 case DVACT_DEACTIVATE: 1396 sc->sc_dying = 1; 1397 return 0; 1398 default: 1399 return EOPNOTSUPP; 1400 } 1401 } 1402 1403 /* 1404 * Handle suspend/resume. 1405 * 1406 * We need to switch to polling mode here, because this routine is 1407 * called from an interrupt context. This is all right since we 1408 * are almost suspended anyway. 1409 * 1410 * Note that this power handler isn't to be registered directly; the 1411 * bus glue needs to call out to it. 1412 */ 1413 bool 1414 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1415 { 1416 ehci_softc_t *sc = device_private(dv); 1417 int i; 1418 uint32_t cmd, hcr; 1419 1420 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1421 1422 mutex_spin_enter(&sc->sc_intr_lock); 1423 sc->sc_bus.ub_usepolling++; 1424 mutex_spin_exit(&sc->sc_intr_lock); 1425 1426 for (i = 1; i <= sc->sc_noport; i++) { 1427 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1428 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1429 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1430 } 1431 1432 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1433 1434 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1435 EOWRITE4(sc, EHCI_USBCMD, cmd); 1436 1437 for (i = 0; i < 100; i++) { 1438 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1439 if (hcr == 0) 1440 break; 1441 1442 usb_delay_ms(&sc->sc_bus, 1); 1443 } 1444 if (hcr != 0) 1445 printf("%s: reset timeout\n", device_xname(dv)); 1446 1447 cmd &= ~EHCI_CMD_RS; 1448 EOWRITE4(sc, EHCI_USBCMD, cmd); 1449 1450 for (i = 0; i < 100; i++) { 1451 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1452 if (hcr == EHCI_STS_HCH) 1453 break; 1454 1455 usb_delay_ms(&sc->sc_bus, 1); 1456 } 1457 if (hcr != EHCI_STS_HCH) 1458 printf("%s: config timeout\n", device_xname(dv)); 1459 1460 mutex_spin_enter(&sc->sc_intr_lock); 1461 sc->sc_bus.ub_usepolling--; 1462 mutex_spin_exit(&sc->sc_intr_lock); 1463 1464 return true; 1465 } 1466 1467 bool 1468 ehci_resume(device_t dv, const pmf_qual_t *qual) 1469 { 1470 ehci_softc_t *sc = device_private(dv); 1471 int i; 1472 uint32_t cmd, hcr; 1473 1474 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1475 1476 /* restore things in case the bios sucks */ 1477 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1478 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1479 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1480 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1481 1482 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1483 1484 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1485 1486 hcr = 0; 1487 for (i = 1; i <= sc->sc_noport; i++) { 1488 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1489 if ((cmd & EHCI_PS_PO) == 0 && 1490 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1491 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1492 hcr = 1; 1493 } 1494 } 1495 1496 if (hcr) { 1497 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1498 1499 for (i = 1; i <= sc->sc_noport; i++) { 1500 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1501 if ((cmd & EHCI_PS_PO) == 0 && 1502 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1503 EOWRITE4(sc, EHCI_PORTSC(i), 1504 cmd & ~EHCI_PS_FPR); 1505 } 1506 } 1507 1508 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1509 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1510 1511 for (i = 0; i < 100; i++) { 1512 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1513 if (hcr != EHCI_STS_HCH) 1514 break; 1515 1516 usb_delay_ms(&sc->sc_bus, 1); 1517 } 1518 if (hcr == EHCI_STS_HCH) 1519 printf("%s: config timeout\n", device_xname(dv)); 1520 1521 return true; 1522 } 1523 1524 /* 1525 * Shut down the controller when the system is going down. 1526 */ 1527 bool 1528 ehci_shutdown(device_t self, int flags) 1529 { 1530 ehci_softc_t *sc = device_private(self); 1531 1532 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1533 1534 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1535 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1536 return true; 1537 } 1538 1539 Static struct usbd_xfer * 1540 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1541 { 1542 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1543 struct usbd_xfer *xfer; 1544 1545 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1546 if (xfer != NULL) { 1547 memset(xfer, 0, sizeof(struct ehci_xfer)); 1548 #ifdef DIAGNOSTIC 1549 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1550 ex->ex_isdone = true; 1551 xfer->ux_state = XFER_BUSY; 1552 #endif 1553 } 1554 return xfer; 1555 } 1556 1557 Static void 1558 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1559 { 1560 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1561 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1562 1563 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1564 xfer->ux_state); 1565 KASSERT(ex->ex_isdone); 1566 1567 #ifdef DIAGNOSTIC 1568 xfer->ux_state = XFER_FREE; 1569 #endif 1570 1571 pool_cache_put(sc->sc_xferpool, xfer); 1572 } 1573 1574 Static void 1575 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1576 { 1577 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1578 1579 *lock = &sc->sc_lock; 1580 } 1581 1582 Static void 1583 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1584 { 1585 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1586 1587 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1588 1589 DPRINTF("epipe=%p status=0x%08x", epipe, 1590 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1591 #ifdef EHCI_DEBUG 1592 if (ehcidebug) 1593 usbd_dump_pipe(pipe); 1594 #endif 1595 epipe->nexttoggle = 0; 1596 } 1597 1598 Static void 1599 ehci_noop(struct usbd_pipe *pipe) 1600 { 1601 } 1602 1603 #ifdef EHCI_DEBUG 1604 /* 1605 * Unused function - this is meant to be called from a kernel 1606 * debugger. 1607 */ 1608 void 1609 ehci_dump(void) 1610 { 1611 ehci_softc_t *sc = theehci; 1612 int i; 1613 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1614 EOREAD4(sc, EHCI_USBCMD), 1615 EOREAD4(sc, EHCI_USBSTS), 1616 EOREAD4(sc, EHCI_USBINTR)); 1617 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1618 EOREAD4(sc, EHCI_FRINDEX), 1619 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1620 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1621 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1622 for (i = 1; i <= sc->sc_noport; i++) 1623 printf("port %d status=0x%08x\n", i, 1624 EOREAD4(sc, EHCI_PORTSC(i))); 1625 } 1626 1627 Static void 1628 ehci_dump_regs(ehci_softc_t *sc) 1629 { 1630 int i; 1631 1632 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1633 1634 DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1635 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1636 EOREAD4(sc, EHCI_USBINTR), 0); 1637 DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1638 "async = 0x%08x", 1639 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1640 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1641 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1642 for (i = 1; i <= sc->sc_noport; i += 2) { 1643 if (i == sc->sc_noport) { 1644 DPRINTF("port %d status = 0x%08x", i, 1645 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1646 } else { 1647 DPRINTF( 1648 "port %d status = 0x%08x port %d status = 0x%08x", 1649 i, EOREAD4(sc, EHCI_PORTSC(i)), 1650 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1651 } 1652 } 1653 } 1654 1655 #define ehci_dump_link(link, type) do { \ 1656 DPRINTF(" link 0x%08x (T = %d):", \ 1657 link, \ 1658 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1659 if (type) { \ 1660 DPRINTF( \ 1661 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1662 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1663 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1664 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1665 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1666 } \ 1667 } while(0) 1668 1669 Static void 1670 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1671 { 1672 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1673 int i; 1674 uint32_t stop = 0; 1675 1676 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1677 ehci_dump_sqtd(sqtd); 1678 usb_syncmem(&sqtd->dma, 1679 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1680 sizeof(sqtd->qtd), 1681 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1682 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1683 usb_syncmem(&sqtd->dma, 1684 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1685 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1686 } 1687 if (!stop) 1688 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1689 } 1690 1691 Static void 1692 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1693 { 1694 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1695 1696 usb_syncmem(&sqtd->dma, sqtd->offs, 1697 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1698 1699 DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1700 ehci_dump_qtd(&sqtd->qtd); 1701 1702 usb_syncmem(&sqtd->dma, sqtd->offs, 1703 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1704 } 1705 1706 Static void 1707 ehci_dump_qtd(ehci_qtd_t *qtd) 1708 { 1709 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1710 uint32_t s = le32toh(qtd->qtd_status); 1711 1712 DPRINTFN(10, 1713 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1714 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1715 DPRINTFN(10, 1716 " toggle = %d ioc = %d bytes = %#x " 1717 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1718 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1719 DPRINTFN(10, 1720 " cerr = %d pid = %d stat = %x", 1721 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1722 0); 1723 DPRINTFN(10, 1724 "active =%d halted=%d buferr=%d babble=%d", 1725 s & EHCI_QTD_ACTIVE ? 1 : 0, 1726 s & EHCI_QTD_HALTED ? 1 : 0, 1727 s & EHCI_QTD_BUFERR ? 1 : 0, 1728 s & EHCI_QTD_BABBLE ? 1 : 0); 1729 DPRINTFN(10, 1730 "xacterr=%d missed=%d split =%d ping =%d", 1731 s & EHCI_QTD_XACTERR ? 1 : 0, 1732 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1733 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1734 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1735 DPRINTFN(10, 1736 "buffer[0] = %#x buffer[1] = %#x " 1737 "buffer[2] = %#x buffer[3] = %#x", 1738 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1739 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1740 DPRINTFN(10, 1741 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1742 } 1743 1744 Static void 1745 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1746 { 1747 ehci_qh_t *qh = &sqh->qh; 1748 ehci_link_t link; 1749 uint32_t endp, endphub; 1750 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1751 1752 usb_syncmem(&sqh->dma, sqh->offs, 1753 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1754 1755 DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1756 link = le32toh(qh->qh_link); 1757 ehci_dump_link(link, true); 1758 1759 endp = le32toh(qh->qh_endp); 1760 DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); 1761 DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", 1762 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1763 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1764 DPRINTFN(10, " dtc = %d hrecl = %d", 1765 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1766 DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", 1767 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1768 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1769 1770 endphub = le32toh(qh->qh_endphub); 1771 DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); 1772 DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", 1773 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1774 DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", 1775 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1776 EHCI_QH_GET_MULT(endphub), 0); 1777 1778 link = le32toh(qh->qh_curqtd); 1779 ehci_dump_link(link, false); 1780 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1781 ehci_dump_qtd(&qh->qh_qtd); 1782 1783 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1784 BUS_DMASYNC_PREREAD); 1785 } 1786 1787 Static void 1788 ehci_dump_itds(ehci_soft_itd_t *itd) 1789 { 1790 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1791 int i; 1792 uint32_t stop = 0; 1793 1794 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1795 ehci_dump_itd(itd); 1796 usb_syncmem(&itd->dma, 1797 itd->offs + offsetof(ehci_itd_t, itd_next), 1798 sizeof(itd->itd), 1799 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1800 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1801 usb_syncmem(&itd->dma, 1802 itd->offs + offsetof(ehci_itd_t, itd_next), 1803 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1804 } 1805 if (!stop) 1806 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1807 } 1808 1809 Static void 1810 ehci_dump_itd(struct ehci_soft_itd *itd) 1811 { 1812 ehci_isoc_trans_t t; 1813 ehci_isoc_bufr_ptr_t b, b2, b3; 1814 int i; 1815 1816 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1817 1818 DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); 1819 1820 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1821 t = le32toh(itd->itd.itd_ctl[i]); 1822 DPRINTF("ITDctl %d: stat = %x len = %x", 1823 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1824 DPRINTF(" ioc = %x pg = %x offs = %x", 1825 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1826 EHCI_ITD_GET_OFFS(t), 0); 1827 } 1828 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1829 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1830 DPRINTF(" %x", 1831 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1832 1833 b = le32toh(itd->itd.itd_bufr[0]); 1834 b2 = le32toh(itd->itd.itd_bufr[1]); 1835 b3 = le32toh(itd->itd.itd_bufr[2]); 1836 DPRINTF(" ep = %x daddr = %x dir = %d", 1837 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1838 DPRINTF(" maxpkt = %x multi = %x", 1839 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1840 } 1841 1842 Static void 1843 ehci_dump_sitd(struct ehci_soft_itd *itd) 1844 { 1845 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1846 1847 DPRINTF("SITD %p next = %p prev = %p", 1848 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1849 DPRINTF(" xfernext=%p physaddr=%X slot=%d", 1850 itd->xfer_next, itd->physaddr, itd->slot, 0); 1851 } 1852 1853 Static void 1854 ehci_dump_exfer(struct ehci_xfer *ex) 1855 { 1856 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1857 1858 DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, 1859 ex->ex_isdone, 0); 1860 1861 switch (ex->ex_type) { 1862 case EX_CTRL: 1863 DPRINTF(" setup = %p data = %p status = %p", 1864 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1865 break; 1866 case EX_BULK: 1867 case EX_INTR: 1868 DPRINTF(" qtdstart = %p qtdend = %p", 1869 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1870 break; 1871 case EX_ISOC: 1872 DPRINTF(" itdstart = %p itdend = %p", 1873 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1874 break; 1875 case EX_FS_ISOC: 1876 DPRINTF(" sitdstart = %p sitdend = %p", 1877 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1878 break; 1879 default: 1880 DPRINTF(" unknown type", 0, 0, 0, 0); 1881 } 1882 } 1883 #endif 1884 1885 Static usbd_status 1886 ehci_open(struct usbd_pipe *pipe) 1887 { 1888 struct usbd_device *dev = pipe->up_dev; 1889 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1890 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1891 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1892 uint8_t addr = dev->ud_addr; 1893 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1894 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1895 ehci_soft_qh_t *sqh; 1896 usbd_status err; 1897 int ival, speed, naks; 1898 int hshubaddr, hshubport; 1899 1900 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1901 1902 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1903 ed->bEndpointAddress, rhaddr); 1904 1905 if (dev->ud_myhsport) { 1906 /* 1907 * When directly attached FS/LS device while doing embedded 1908 * transaction translations and we are the hub, set the hub 1909 * address to 0 (us). 1910 */ 1911 if (!(sc->sc_flags & EHCIF_ETTF) 1912 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1913 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1914 } else { 1915 hshubaddr = 0; 1916 } 1917 hshubport = dev->ud_myhsport->up_portno; 1918 } else { 1919 hshubaddr = 0; 1920 hshubport = 0; 1921 } 1922 1923 if (sc->sc_dying) 1924 return USBD_IOERROR; 1925 1926 /* toggle state needed for bulk endpoints */ 1927 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1928 1929 if (addr == rhaddr) { 1930 switch (ed->bEndpointAddress) { 1931 case USB_CONTROL_ENDPOINT: 1932 pipe->up_methods = &roothub_ctrl_methods; 1933 break; 1934 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1935 pipe->up_methods = &ehci_root_intr_methods; 1936 break; 1937 default: 1938 DPRINTF("bad bEndpointAddress 0x%02x", 1939 ed->bEndpointAddress, 0, 0, 0); 1940 return USBD_INVAL; 1941 } 1942 return USBD_NORMAL_COMPLETION; 1943 } 1944 1945 /* XXX All this stuff is only valid for async. */ 1946 switch (dev->ud_speed) { 1947 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1948 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1949 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1950 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1951 } 1952 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1953 DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, 1954 0); 1955 return USBD_INVAL; 1956 } 1957 1958 /* 1959 * For interrupt transfer, nak throttling must be disabled, but for 1960 * the other transfer type, nak throttling should be enabled from the 1961 * viewpoint that avoids the memory thrashing. 1962 */ 1963 naks = (xfertype == UE_INTERRUPT) ? 0 1964 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1965 1966 /* Allocate sqh for everything, save isoc xfers */ 1967 if (xfertype != UE_ISOCHRONOUS) { 1968 sqh = ehci_alloc_sqh(sc); 1969 if (sqh == NULL) 1970 return USBD_NOMEM; 1971 /* qh_link filled when the QH is added */ 1972 sqh->qh.qh_endp = htole32( 1973 EHCI_QH_SET_ADDR(addr) | 1974 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1975 EHCI_QH_SET_EPS(speed) | 1976 EHCI_QH_DTC | 1977 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1978 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1979 EHCI_QH_CTL : 0) | 1980 EHCI_QH_SET_NRL(naks) 1981 ); 1982 sqh->qh.qh_endphub = htole32( 1983 EHCI_QH_SET_MULT(1) | 1984 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1985 ); 1986 if (speed != EHCI_QH_SPEED_HIGH) 1987 sqh->qh.qh_endphub |= htole32( 1988 EHCI_QH_SET_PORT(hshubport) | 1989 EHCI_QH_SET_HUBA(hshubaddr) | 1990 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1991 ); 1992 sqh->qh.qh_curqtd = EHCI_NULL; 1993 /* Fill the overlay qTD */ 1994 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1995 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1996 sqh->qh.qh_qtd.qtd_status = htole32(0); 1997 1998 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1999 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2000 epipe->sqh = sqh; 2001 } else { 2002 sqh = NULL; 2003 } /*xfertype == UE_ISOC*/ 2004 2005 switch (xfertype) { 2006 case UE_CONTROL: 2007 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2008 0, &epipe->ctrl.reqdma); 2009 #ifdef EHCI_DEBUG 2010 if (err) 2011 printf("ehci_open: usb_allocmem()=%d\n", err); 2012 #endif 2013 if (err) 2014 goto bad; 2015 pipe->up_methods = &ehci_device_ctrl_methods; 2016 mutex_enter(&sc->sc_lock); 2017 ehci_add_qh(sc, sqh, sc->sc_async_head); 2018 mutex_exit(&sc->sc_lock); 2019 break; 2020 case UE_BULK: 2021 pipe->up_methods = &ehci_device_bulk_methods; 2022 mutex_enter(&sc->sc_lock); 2023 ehci_add_qh(sc, sqh, sc->sc_async_head); 2024 mutex_exit(&sc->sc_lock); 2025 break; 2026 case UE_INTERRUPT: 2027 pipe->up_methods = &ehci_device_intr_methods; 2028 ival = pipe->up_interval; 2029 if (ival == USBD_DEFAULT_INTERVAL) { 2030 if (speed == EHCI_QH_SPEED_HIGH) { 2031 if (ed->bInterval > 16) { 2032 /* 2033 * illegal with high-speed, but there 2034 * were documentation bugs in the spec, 2035 * so be generous 2036 */ 2037 ival = 256; 2038 } else 2039 ival = (1 << (ed->bInterval - 1)) / 8; 2040 } else 2041 ival = ed->bInterval; 2042 } 2043 err = ehci_device_setintr(sc, sqh, ival); 2044 if (err) 2045 goto bad; 2046 break; 2047 case UE_ISOCHRONOUS: 2048 pipe->up_serialise = false; 2049 if (speed == EHCI_QH_SPEED_HIGH) 2050 pipe->up_methods = &ehci_device_isoc_methods; 2051 else 2052 pipe->up_methods = &ehci_device_fs_isoc_methods; 2053 if (ed->bInterval == 0 || ed->bInterval > 16) { 2054 printf("ehci: opening pipe with invalid bInterval\n"); 2055 err = USBD_INVAL; 2056 goto bad; 2057 } 2058 if (UGETW(ed->wMaxPacketSize) == 0) { 2059 printf("ehci: zero length endpoint open request\n"); 2060 err = USBD_INVAL; 2061 goto bad; 2062 } 2063 epipe->isoc.next_frame = 0; 2064 epipe->isoc.cur_xfers = 0; 2065 break; 2066 default: 2067 DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); 2068 err = USBD_INVAL; 2069 goto bad; 2070 } 2071 return USBD_NORMAL_COMPLETION; 2072 2073 bad: 2074 if (sqh != NULL) { 2075 mutex_enter(&sc->sc_lock); 2076 ehci_free_sqh(sc, sqh); 2077 mutex_exit(&sc->sc_lock); 2078 } 2079 return err; 2080 } 2081 2082 /* 2083 * Add an ED to the schedule. Called with USB lock held. 2084 */ 2085 Static void 2086 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2087 { 2088 2089 KASSERT(mutex_owned(&sc->sc_lock)); 2090 2091 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2092 2093 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2094 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2095 2096 sqh->next = head->next; 2097 sqh->qh.qh_link = head->qh.qh_link; 2098 2099 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2100 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2101 2102 head->next = sqh; 2103 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2104 2105 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2106 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2107 2108 #ifdef EHCI_DEBUG 2109 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2110 ehci_dump_sqh(sqh); 2111 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2112 #endif 2113 } 2114 2115 /* 2116 * Remove an ED from the schedule. Called with USB lock held. 2117 */ 2118 Static void 2119 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2120 { 2121 ehci_soft_qh_t *p; 2122 2123 KASSERT(mutex_owned(&sc->sc_lock)); 2124 2125 /* XXX */ 2126 for (p = head; p != NULL && p->next != sqh; p = p->next) 2127 ; 2128 if (p == NULL) 2129 panic("ehci_rem_qh: ED not found"); 2130 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2131 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2132 p->next = sqh->next; 2133 p->qh.qh_link = sqh->qh.qh_link; 2134 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2135 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2136 2137 ehci_sync_hc(sc); 2138 } 2139 2140 Static void 2141 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2142 { 2143 int i; 2144 uint32_t status; 2145 2146 /* Save toggle bit and ping status. */ 2147 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2148 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2149 status = sqh->qh.qh_qtd.qtd_status & 2150 htole32(EHCI_QTD_TOGGLE_MASK | 2151 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2152 /* Set HALTED to make hw leave it alone. */ 2153 sqh->qh.qh_qtd.qtd_status = 2154 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2155 usb_syncmem(&sqh->dma, 2156 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2157 sizeof(sqh->qh.qh_qtd.qtd_status), 2158 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2159 sqh->qh.qh_curqtd = 0; 2160 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2161 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2162 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2163 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2164 sqh->sqtd = sqtd; 2165 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2166 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2167 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2168 sqh->qh.qh_qtd.qtd_status = status; 2169 usb_syncmem(&sqh->dma, 2170 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2171 sizeof(sqh->qh.qh_qtd.qtd_status), 2172 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2173 } 2174 2175 /* 2176 * Ensure that the HC has released all references to the QH. We do this 2177 * by asking for a Async Advance Doorbell interrupt and then we wait for 2178 * the interrupt. 2179 * To make this easier we first obtain exclusive use of the doorbell. 2180 */ 2181 Static void 2182 ehci_sync_hc(ehci_softc_t *sc) 2183 { 2184 int error __diagused; 2185 2186 KASSERT(mutex_owned(&sc->sc_lock)); 2187 2188 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2189 2190 if (sc->sc_dying) { 2191 DPRINTF("dying", 0, 0, 0, 0); 2192 return; 2193 } 2194 /* ask for doorbell */ 2195 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2196 DPRINTF("cmd = 0x%08x sts = 0x%08x", 2197 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2198 2199 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2200 2201 DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", 2202 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2203 #ifdef DIAGNOSTIC 2204 if (error) 2205 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2206 #endif 2207 } 2208 2209 Static void 2210 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2211 { 2212 2213 KASSERT(mutex_owned(&sc->sc_lock)); 2214 2215 for (; itd != NULL; itd = itd->xfer_next) { 2216 struct ehci_soft_itd *prev = itd->frame_list.prev; 2217 2218 /* Unlink itd from hardware chain, or frame array */ 2219 if (prev == NULL) { /* We're at the table head */ 2220 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2221 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2222 usb_syncmem(&sc->sc_fldma, 2223 sizeof(ehci_link_t) * itd->slot, 2224 sizeof(ehci_link_t), 2225 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2226 2227 if (itd->frame_list.next != NULL) 2228 itd->frame_list.next->frame_list.prev = NULL; 2229 } else { 2230 /* XXX this part is untested... */ 2231 prev->itd.itd_next = itd->itd.itd_next; 2232 usb_syncmem(&itd->dma, 2233 itd->offs + offsetof(ehci_itd_t, itd_next), 2234 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2235 2236 prev->frame_list.next = itd->frame_list.next; 2237 if (itd->frame_list.next != NULL) 2238 itd->frame_list.next->frame_list.prev = prev; 2239 } 2240 } 2241 } 2242 2243 Static void 2244 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2245 { 2246 struct ehci_soft_itd *next; 2247 2248 mutex_enter(&sc->sc_lock); 2249 next = NULL; 2250 for (; itd != NULL; itd = next) { 2251 next = itd->xfer_next; 2252 ehci_free_itd_locked(sc, itd); 2253 } 2254 mutex_exit(&sc->sc_lock); 2255 } 2256 2257 Static void 2258 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2259 { 2260 2261 KASSERT(mutex_owned(&sc->sc_lock)); 2262 2263 for (; sitd != NULL; sitd = sitd->xfer_next) { 2264 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2265 2266 /* Unlink sitd from hardware chain, or frame array */ 2267 if (prev == NULL) { /* We're at the table head */ 2268 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2269 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2270 usb_syncmem(&sc->sc_fldma, 2271 sizeof(ehci_link_t) * sitd->slot, 2272 sizeof(ehci_link_t), 2273 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2274 2275 if (sitd->frame_list.next != NULL) 2276 sitd->frame_list.next->frame_list.prev = NULL; 2277 } else { 2278 /* XXX this part is untested... */ 2279 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2280 usb_syncmem(&sitd->dma, 2281 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2282 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2283 2284 prev->frame_list.next = sitd->frame_list.next; 2285 if (sitd->frame_list.next != NULL) 2286 sitd->frame_list.next->frame_list.prev = prev; 2287 } 2288 } 2289 } 2290 2291 Static void 2292 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2293 { 2294 2295 mutex_enter(&sc->sc_lock); 2296 struct ehci_soft_sitd *next = NULL; 2297 for (; sitd != NULL; sitd = next) { 2298 next = sitd->xfer_next; 2299 ehci_free_sitd_locked(sc, sitd); 2300 } 2301 mutex_exit(&sc->sc_lock); 2302 } 2303 2304 /***********/ 2305 2306 Static int 2307 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2308 void *buf, int buflen) 2309 { 2310 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2311 usb_hub_descriptor_t hubd; 2312 usb_port_status_t ps; 2313 uint16_t len, value, index; 2314 int l, totlen = 0; 2315 int port, i; 2316 uint32_t v; 2317 2318 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2319 2320 if (sc->sc_dying) 2321 return -1; 2322 2323 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, 2324 0, 0); 2325 2326 len = UGETW(req->wLength); 2327 value = UGETW(req->wValue); 2328 index = UGETW(req->wIndex); 2329 2330 #define C(x,y) ((x) | ((y) << 8)) 2331 switch (C(req->bRequest, req->bmRequestType)) { 2332 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2333 if (len == 0) 2334 break; 2335 switch (value) { 2336 case C(0, UDESC_DEVICE): { 2337 usb_device_descriptor_t devd; 2338 totlen = min(buflen, sizeof(devd)); 2339 memcpy(&devd, buf, totlen); 2340 USETW(devd.idVendor, sc->sc_id_vendor); 2341 memcpy(buf, &devd, totlen); 2342 break; 2343 2344 } 2345 #define sd ((usb_string_descriptor_t *)buf) 2346 case C(1, UDESC_STRING): 2347 /* Vendor */ 2348 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2349 break; 2350 case C(2, UDESC_STRING): 2351 /* Product */ 2352 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2353 break; 2354 #undef sd 2355 default: 2356 /* default from usbroothub */ 2357 return buflen; 2358 } 2359 break; 2360 2361 /* Hub requests */ 2362 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2363 break; 2364 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2365 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 2366 value, 0, 0); 2367 if (index < 1 || index > sc->sc_noport) { 2368 return -1; 2369 } 2370 port = EHCI_PORTSC(index); 2371 v = EOREAD4(sc, port); 2372 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2373 v &= ~EHCI_PS_CLEAR; 2374 switch (value) { 2375 case UHF_PORT_ENABLE: 2376 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2377 break; 2378 case UHF_PORT_SUSPEND: 2379 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2380 break; 2381 v &= ~EHCI_PS_SUSP; 2382 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2383 /* see USB2 spec ch. 7.1.7.7 */ 2384 usb_delay_ms(&sc->sc_bus, 20); 2385 EOWRITE4(sc, port, v); 2386 usb_delay_ms(&sc->sc_bus, 2); 2387 #ifdef DEBUG 2388 v = EOREAD4(sc, port); 2389 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2390 printf("ehci: resume failed: %x\n", v); 2391 #endif 2392 break; 2393 case UHF_PORT_POWER: 2394 if (sc->sc_hasppc) 2395 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2396 break; 2397 case UHF_PORT_TEST: 2398 DPRINTF("clear port test %d", index, 0, 0, 0); 2399 break; 2400 case UHF_PORT_INDICATOR: 2401 DPRINTF("clear port ind %d", index, 0, 0, 0); 2402 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2403 break; 2404 case UHF_C_PORT_CONNECTION: 2405 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2406 break; 2407 case UHF_C_PORT_ENABLE: 2408 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2409 break; 2410 case UHF_C_PORT_SUSPEND: 2411 /* how? */ 2412 break; 2413 case UHF_C_PORT_OVER_CURRENT: 2414 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2415 break; 2416 case UHF_C_PORT_RESET: 2417 sc->sc_isreset[index] = 0; 2418 break; 2419 default: 2420 return -1; 2421 } 2422 #if 0 2423 switch(value) { 2424 case UHF_C_PORT_CONNECTION: 2425 case UHF_C_PORT_ENABLE: 2426 case UHF_C_PORT_SUSPEND: 2427 case UHF_C_PORT_OVER_CURRENT: 2428 case UHF_C_PORT_RESET: 2429 default: 2430 break; 2431 } 2432 #endif 2433 break; 2434 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2435 if (len == 0) 2436 break; 2437 if ((value & 0xff) != 0) { 2438 return -1; 2439 } 2440 totlen = min(buflen, sizeof(hubd)); 2441 memcpy(&hubd, buf, totlen); 2442 hubd.bNbrPorts = sc->sc_noport; 2443 v = EOREAD4(sc, EHCI_HCSPARAMS); 2444 USETW(hubd.wHubCharacteristics, 2445 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2446 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2447 ? UHD_PORT_IND : 0); 2448 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2449 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2450 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2451 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2452 totlen = min(totlen, hubd.bDescLength); 2453 memcpy(buf, &hubd, totlen); 2454 break; 2455 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2456 if (len != 4) { 2457 return -1; 2458 } 2459 memset(buf, 0, len); /* ? XXX */ 2460 totlen = len; 2461 break; 2462 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2463 DPRINTF("get port status i=%d", index, 0, 0, 0); 2464 if (index < 1 || index > sc->sc_noport) { 2465 return -1; 2466 } 2467 if (len != 4) { 2468 return -1; 2469 } 2470 v = EOREAD4(sc, EHCI_PORTSC(index)); 2471 DPRINTF("port status=0x%04x", v, 0, 0, 0); 2472 2473 i = UPS_HIGH_SPEED; 2474 if (sc->sc_flags & EHCIF_ETTF) { 2475 /* 2476 * If we are doing embedded transaction translation, 2477 * then directly attached LS/FS devices are reset by 2478 * the EHCI controller itself. PSPD is encoded 2479 * the same way as in USBSTATUS. 2480 */ 2481 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2482 } 2483 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2484 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2485 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2486 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2487 if (v & EHCI_PS_PR) i |= UPS_RESET; 2488 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2489 if (sc->sc_vendor_port_status) 2490 i = sc->sc_vendor_port_status(sc, v, i); 2491 USETW(ps.wPortStatus, i); 2492 i = 0; 2493 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2494 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2495 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2496 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2497 USETW(ps.wPortChange, i); 2498 totlen = min(len, sizeof(ps)); 2499 memcpy(buf, &ps, totlen); 2500 break; 2501 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2502 return -1; 2503 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2504 break; 2505 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2506 if (index < 1 || index > sc->sc_noport) { 2507 return -1; 2508 } 2509 port = EHCI_PORTSC(index); 2510 v = EOREAD4(sc, port); 2511 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2512 v &= ~EHCI_PS_CLEAR; 2513 switch(value) { 2514 case UHF_PORT_ENABLE: 2515 EOWRITE4(sc, port, v | EHCI_PS_PE); 2516 break; 2517 case UHF_PORT_SUSPEND: 2518 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2519 break; 2520 case UHF_PORT_RESET: 2521 DPRINTF("reset port %d", index, 0, 0, 0); 2522 if (EHCI_PS_IS_LOWSPEED(v) 2523 && sc->sc_ncomp > 0 2524 && !(sc->sc_flags & EHCIF_ETTF)) { 2525 /* 2526 * Low speed device on non-ETTF controller or 2527 * unaccompanied controller, give up ownership. 2528 */ 2529 ehci_disown(sc, index, 1); 2530 break; 2531 } 2532 /* Start reset sequence. */ 2533 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2534 EOWRITE4(sc, port, v | EHCI_PS_PR); 2535 /* Wait for reset to complete. */ 2536 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2537 if (sc->sc_dying) { 2538 return -1; 2539 } 2540 /* 2541 * An embedded transaction translator will automatically 2542 * terminate the reset sequence so there's no need to 2543 * it. 2544 */ 2545 v = EOREAD4(sc, port); 2546 if (v & EHCI_PS_PR) { 2547 /* Terminate reset sequence. */ 2548 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2549 /* Wait for HC to complete reset. */ 2550 usb_delay_ms(&sc->sc_bus, 2551 EHCI_PORT_RESET_COMPLETE); 2552 if (sc->sc_dying) { 2553 return -1; 2554 } 2555 } 2556 2557 v = EOREAD4(sc, port); 2558 DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); 2559 if (v & EHCI_PS_PR) { 2560 printf("%s: port reset timeout\n", 2561 device_xname(sc->sc_dev)); 2562 return USBD_TIMEOUT; 2563 } 2564 if (!(v & EHCI_PS_PE)) { 2565 /* Not a high speed device, give up ownership.*/ 2566 ehci_disown(sc, index, 0); 2567 break; 2568 } 2569 sc->sc_isreset[index] = 1; 2570 DPRINTF("ehci port %d reset, status = 0x%08x", index, 2571 v, 0, 0); 2572 break; 2573 case UHF_PORT_POWER: 2574 DPRINTF("set port power %d (has PPC = %d)", index, 2575 sc->sc_hasppc, 0, 0); 2576 if (sc->sc_hasppc) 2577 EOWRITE4(sc, port, v | EHCI_PS_PP); 2578 break; 2579 case UHF_PORT_TEST: 2580 DPRINTF("set port test %d", index, 0, 0, 0); 2581 break; 2582 case UHF_PORT_INDICATOR: 2583 DPRINTF("set port ind %d", index, 0, 0, 0); 2584 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2585 break; 2586 default: 2587 return -1; 2588 } 2589 break; 2590 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2591 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2592 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2593 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2594 break; 2595 default: 2596 /* default from usbroothub */ 2597 DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); 2598 2599 return buflen; 2600 } 2601 2602 DPRINTF("returning %d", totlen, 0, 0, 0); 2603 2604 return totlen; 2605 } 2606 2607 Static void 2608 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2609 { 2610 int port; 2611 uint32_t v; 2612 2613 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2614 2615 DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); 2616 #ifdef DIAGNOSTIC 2617 if (sc->sc_npcomp != 0) { 2618 int i = (index-1) / sc->sc_npcomp; 2619 if (i >= sc->sc_ncomp) 2620 printf("%s: strange port\n", 2621 device_xname(sc->sc_dev)); 2622 else 2623 printf("%s: handing over %s speed device on " 2624 "port %d to %s\n", 2625 device_xname(sc->sc_dev), 2626 lowspeed ? "low" : "full", 2627 index, device_xname(sc->sc_comps[i])); 2628 } else { 2629 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2630 } 2631 #endif 2632 port = EHCI_PORTSC(index); 2633 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2634 EOWRITE4(sc, port, v | EHCI_PS_PO); 2635 } 2636 2637 Static usbd_status 2638 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2639 { 2640 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2641 usbd_status err; 2642 2643 /* Insert last in queue. */ 2644 mutex_enter(&sc->sc_lock); 2645 err = usb_insert_transfer(xfer); 2646 mutex_exit(&sc->sc_lock); 2647 if (err) 2648 return err; 2649 2650 /* Pipe isn't running, start first */ 2651 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2652 } 2653 2654 Static usbd_status 2655 ehci_root_intr_start(struct usbd_xfer *xfer) 2656 { 2657 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2658 2659 if (sc->sc_dying) 2660 return USBD_IOERROR; 2661 2662 mutex_enter(&sc->sc_lock); 2663 sc->sc_intrxfer = xfer; 2664 mutex_exit(&sc->sc_lock); 2665 2666 return USBD_IN_PROGRESS; 2667 } 2668 2669 /* Abort a root interrupt request. */ 2670 Static void 2671 ehci_root_intr_abort(struct usbd_xfer *xfer) 2672 { 2673 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2674 2675 KASSERT(mutex_owned(&sc->sc_lock)); 2676 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2677 2678 sc->sc_intrxfer = NULL; 2679 2680 xfer->ux_status = USBD_CANCELLED; 2681 usb_transfer_complete(xfer); 2682 } 2683 2684 /* Close the root pipe. */ 2685 Static void 2686 ehci_root_intr_close(struct usbd_pipe *pipe) 2687 { 2688 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2689 2690 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2691 2692 KASSERT(mutex_owned(&sc->sc_lock)); 2693 2694 sc->sc_intrxfer = NULL; 2695 } 2696 2697 Static void 2698 ehci_root_intr_done(struct usbd_xfer *xfer) 2699 { 2700 xfer->ux_hcpriv = NULL; 2701 } 2702 2703 /************************/ 2704 2705 Static ehci_soft_qh_t * 2706 ehci_alloc_sqh(ehci_softc_t *sc) 2707 { 2708 ehci_soft_qh_t *sqh; 2709 usbd_status err; 2710 int i, offs; 2711 usb_dma_t dma; 2712 2713 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2714 2715 mutex_enter(&sc->sc_lock); 2716 if (sc->sc_freeqhs == NULL) { 2717 DPRINTF("allocating chunk", 0, 0, 0, 0); 2718 mutex_exit(&sc->sc_lock); 2719 2720 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2721 EHCI_PAGE_SIZE, &dma); 2722 #ifdef EHCI_DEBUG 2723 if (err) 2724 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2725 #endif 2726 if (err) 2727 return NULL; 2728 2729 mutex_enter(&sc->sc_lock); 2730 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2731 offs = i * EHCI_SQH_SIZE; 2732 sqh = KERNADDR(&dma, offs); 2733 sqh->physaddr = DMAADDR(&dma, offs); 2734 sqh->dma = dma; 2735 sqh->offs = offs; 2736 sqh->next = sc->sc_freeqhs; 2737 sc->sc_freeqhs = sqh; 2738 } 2739 } 2740 sqh = sc->sc_freeqhs; 2741 sc->sc_freeqhs = sqh->next; 2742 mutex_exit(&sc->sc_lock); 2743 2744 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2745 sqh->next = NULL; 2746 return sqh; 2747 } 2748 2749 Static void 2750 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2751 { 2752 KASSERT(mutex_owned(&sc->sc_lock)); 2753 2754 sqh->next = sc->sc_freeqhs; 2755 sc->sc_freeqhs = sqh; 2756 } 2757 2758 Static ehci_soft_qtd_t * 2759 ehci_alloc_sqtd(ehci_softc_t *sc) 2760 { 2761 ehci_soft_qtd_t *sqtd = NULL; 2762 usbd_status err; 2763 int i, offs; 2764 usb_dma_t dma; 2765 2766 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2767 2768 mutex_enter(&sc->sc_lock); 2769 if (sc->sc_freeqtds == NULL) { 2770 DPRINTF("allocating chunk", 0, 0, 0, 0); 2771 mutex_exit(&sc->sc_lock); 2772 2773 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2774 EHCI_PAGE_SIZE, &dma); 2775 #ifdef EHCI_DEBUG 2776 if (err) 2777 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2778 #endif 2779 if (err) 2780 goto done; 2781 2782 mutex_enter(&sc->sc_lock); 2783 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2784 offs = i * EHCI_SQTD_SIZE; 2785 sqtd = KERNADDR(&dma, offs); 2786 sqtd->physaddr = DMAADDR(&dma, offs); 2787 sqtd->dma = dma; 2788 sqtd->offs = offs; 2789 2790 sqtd->nextqtd = sc->sc_freeqtds; 2791 sc->sc_freeqtds = sqtd; 2792 } 2793 } 2794 2795 sqtd = sc->sc_freeqtds; 2796 sc->sc_freeqtds = sqtd->nextqtd; 2797 mutex_exit(&sc->sc_lock); 2798 2799 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2800 sqtd->nextqtd = NULL; 2801 sqtd->xfer = NULL; 2802 2803 done: 2804 return sqtd; 2805 } 2806 2807 Static void 2808 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2809 { 2810 2811 mutex_enter(&sc->sc_lock); 2812 sqtd->nextqtd = sc->sc_freeqtds; 2813 sc->sc_freeqtds = sqtd; 2814 mutex_exit(&sc->sc_lock); 2815 } 2816 2817 Static usbd_status 2818 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2819 int alen, int rd, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2820 { 2821 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2822 ehci_soft_qtd_t *next, *cur; 2823 ehci_physaddr_t nextphys; 2824 uint32_t qtdstatus; 2825 int len, curlen, mps; 2826 int i, tog; 2827 int pages, pageoffs; 2828 size_t curoffs; 2829 vaddr_t va, va_offs; 2830 usb_dma_t *dma = &xfer->ux_dmabuf; 2831 uint16_t flags = xfer->ux_flags; 2832 paddr_t a; 2833 2834 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2835 DPRINTF("start len=%d", alen, 0, 0, 0); 2836 2837 ASSERT_SLEEPABLE(); 2838 KASSERT(sp); 2839 KASSERT(alen != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2840 2841 len = alen; 2842 qtdstatus = EHCI_QTD_ACTIVE | 2843 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2844 EHCI_QTD_SET_CERR(3) 2845 ; 2846 2847 size_t nsqtd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 2848 nsqtd += ((len + EHCI_QTD_MAXTRANSFER - 1) / EHCI_QTD_MAXTRANSFER); 2849 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2850 KM_SLEEP); 2851 exfer->ex_nsqtd = nsqtd; 2852 2853 mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2854 cur = ehci_alloc_sqtd(sc); 2855 *sp = cur; 2856 if (cur == NULL) 2857 goto nomem; 2858 2859 curoffs = 0; 2860 for (size_t j = 0;;) { 2861 KASSERT(j < nsqtd); 2862 exfer->ex_sqtds[j++] = cur; 2863 2864 /* The EHCI hardware can handle at most 5 pages. */ 2865 va = (vaddr_t)KERNADDR(dma, curoffs); 2866 va_offs = EHCI_PAGE_OFFSET(va); 2867 if (len - curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2868 /* we can handle it in this QTD */ 2869 curlen = len - curoffs; 2870 } else { 2871 /* must use multiple TDs, fill as much as possible. */ 2872 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2873 2874 /* the length must be a multiple of the max size */ 2875 curlen -= curlen % mps; 2876 DPRINTF("multiple QTDs, curlen=%d", curlen, 0, 0, 0); 2877 KASSERT(curlen != 0); 2878 } 2879 DPRINTF("len=%d curlen=%d curoffs=%zu", len, curlen, curoffs, 2880 0); 2881 2882 /* 2883 * Allocate another transfer if there's more data left, 2884 * or if force last short transfer flag is set and we're 2885 * allocating a multiple of the max packet size. 2886 */ 2887 2888 if (curoffs + curlen != len || 2889 ((curlen % mps) == 0 && !rd && curlen != 0 && 2890 (flags & USBD_FORCE_SHORT_XFER))) { 2891 next = ehci_alloc_sqtd(sc); 2892 if (next == NULL) 2893 goto nomem; 2894 nextphys = htole32(next->physaddr); 2895 } else { 2896 next = NULL; 2897 nextphys = EHCI_NULL; 2898 } 2899 2900 /* Find number of pages we'll be using, insert dma addresses */ 2901 pages = EHCI_NPAGES(curlen); 2902 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2903 pageoffs = EHCI_PAGE(curoffs); 2904 for (i = 0; i < pages; i++) { 2905 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2906 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2907 /* Cast up to avoid compiler warnings */ 2908 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2909 } 2910 2911 /* First buffer pointer requires a page offset to start at */ 2912 cur->qtd.qtd_buffer[0] |= htole32(va_offs); 2913 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2914 cur->qtd.qtd_status = htole32(qtdstatus); 2915 cur->nextqtd = next; 2916 cur->xfer = xfer; 2917 cur->bufoff = curoffs; 2918 cur->tdlen = curlen; 2919 cur->len = 0; 2920 2921 DPRINTF("cbp=0x%08zx end=0x%08zx", curoffs, curoffs + curlen, 2922 0, 0); 2923 2924 /* 2925 * adjust the toggle based on the number of packets in this 2926 * qtd 2927 */ 2928 if (((curlen + mps - 1) / mps) & 1) { 2929 tog ^= 1; 2930 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2931 } 2932 if (next == NULL) 2933 break; 2934 DPRINTF("extend chain", 0, 0, 0, 0); 2935 if (len) 2936 curoffs += curlen; 2937 cur = next; 2938 } 2939 if (ep) 2940 *ep = cur; 2941 2942 DPRINTF("return sqtd=%p sqtdend=%p", *sp, cur, 0, 0); 2943 2944 return USBD_NORMAL_COMPLETION; 2945 2946 nomem: 2947 ehci_free_sqtds(sc, exfer); 2948 DPRINTF("no memory", 0, 0, 0, 0); 2949 return USBD_NOMEM; 2950 } 2951 2952 Static void 2953 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2954 { 2955 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2956 DPRINTF("exfer=%p", exfer, 0, 0, 0); 2957 2958 mutex_enter(&sc->sc_lock); 2959 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2960 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2961 2962 if (sqtd == NULL) 2963 break; 2964 2965 sqtd->nextqtd = sc->sc_freeqtds; 2966 sc->sc_freeqtds = sqtd; 2967 } 2968 mutex_exit(&sc->sc_lock); 2969 } 2970 2971 Static void 2972 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2973 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2974 { 2975 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2976 ehci_soft_qtd_t *sqtd, *prev; 2977 int tog = *toggle; 2978 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2979 int len = length; 2980 size_t i; 2981 2982 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2983 DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, 2984 *toggle); 2985 DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); 2986 2987 sqtd = prev = NULL; 2988 for (i = 0; i < exfer->ex_nsqtd; i++, prev = sqtd) { 2989 sqtd = exfer->ex_sqtds[i]; 2990 vaddr_t va = (vaddr_t)KERNADDR(&xfer->ux_dmabuf, sqtd->bufoff); 2991 sqtd->len = sqtd->tdlen; 2992 if (len < sqtd->len) { 2993 sqtd->len = len; 2994 } 2995 2996 DPRINTF("sqtd[%d]=%p prev %p len %d", i, sqtd, prev, sqtd->len); 2997 DPRINTF(" va %p bufoff %d pa %p", va, sqtd->bufoff, 2998 DMAADDR(&xfer->ux_dmabuf, sqtd->bufoff), 0); 2999 3000 if (prev) { 3001 prev->nextqtd = sqtd; 3002 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3003 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3004 } 3005 usb_syncmem(&sqtd->dma, 3006 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3007 sizeof(sqtd->qtd.qtd_status), 3008 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3009 usb_syncmem(&sqtd->dma, 3010 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3011 sizeof(sqtd->qtd.qtd_buffer[0]), 3012 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3013 3014 sqtd->qtd.qtd_buffer[0] &= ~htole32(EHCI_PAGE_MASK); 3015 sqtd->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3016 /* Reset ... */ 3017 sqtd->qtd.qtd_status &= ~htole32( 3018 EHCI_QTD_STATUS_MASK | 3019 EHCI_QTD_PID_MASK | 3020 EHCI_QTD_CERR_MASK | 3021 EHCI_QTD_C_PAGE_MASK | 3022 EHCI_QTD_BYTES_MASK | 3023 EHCI_QTD_TOGGLE_MASK); 3024 sqtd->qtd.qtd_status |= htole32( 3025 EHCI_QTD_ACTIVE | 3026 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3027 EHCI_QTD_SET_BYTES(sqtd->len) | 3028 EHCI_QTD_SET_CERR(3) | 3029 EHCI_QTD_SET_TOGGLE(tog)); 3030 3031 usb_syncmem(&sqtd->dma, 3032 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3033 sizeof(sqtd->qtd.qtd_status), 3034 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3035 usb_syncmem(&sqtd->dma, 3036 sqtd->offs + offsetof(ehci_qtd_t, qtd_buffer), 3037 sizeof(sqtd->qtd.qtd_buffer[0]), 3038 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3039 3040 if (((sqtd->len + mps - 1) / mps) & 1) { 3041 tog ^= 1; 3042 } 3043 3044 len -= sqtd->len; 3045 if (len == 0) 3046 break; 3047 } 3048 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu i %zu", 3049 xfer, length, len, mps, exfer->ex_nsqtd, i); 3050 3051 if (i < exfer->ex_nsqtd) { 3052 /* 3053 * The full allocation chain wasn't used, so we need to 3054 * terminate it. 3055 */ 3056 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3057 } 3058 *lsqtd = sqtd; 3059 *toggle = tog; 3060 } 3061 3062 Static ehci_soft_itd_t * 3063 ehci_alloc_itd(ehci_softc_t *sc) 3064 { 3065 struct ehci_soft_itd *itd, *freeitd; 3066 usbd_status err; 3067 usb_dma_t dma; 3068 3069 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3070 3071 mutex_enter(&sc->sc_lock); 3072 3073 freeitd = LIST_FIRST(&sc->sc_freeitds); 3074 if (freeitd == NULL) { 3075 DPRINTF("allocating chunk", 0, 0, 0, 0); 3076 mutex_exit(&sc->sc_lock); 3077 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3078 EHCI_PAGE_SIZE, &dma); 3079 3080 if (err) { 3081 DPRINTF("alloc returned %d", err, 0, 0, 0); 3082 return NULL; 3083 } 3084 mutex_enter(&sc->sc_lock); 3085 3086 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3087 int offs = i * EHCI_ITD_SIZE; 3088 itd = KERNADDR(&dma, offs); 3089 itd->physaddr = DMAADDR(&dma, offs); 3090 itd->dma = dma; 3091 itd->offs = offs; 3092 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3093 } 3094 freeitd = LIST_FIRST(&sc->sc_freeitds); 3095 } 3096 3097 itd = freeitd; 3098 LIST_REMOVE(itd, free_list); 3099 mutex_exit(&sc->sc_lock); 3100 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3101 3102 itd->frame_list.next = NULL; 3103 itd->frame_list.prev = NULL; 3104 itd->xfer_next = NULL; 3105 itd->slot = 0; 3106 3107 return itd; 3108 } 3109 3110 Static ehci_soft_sitd_t * 3111 ehci_alloc_sitd(ehci_softc_t *sc) 3112 { 3113 struct ehci_soft_sitd *sitd, *freesitd; 3114 usbd_status err; 3115 int i, offs; 3116 usb_dma_t dma; 3117 3118 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3119 3120 mutex_enter(&sc->sc_lock); 3121 freesitd = LIST_FIRST(&sc->sc_freesitds); 3122 if (freesitd == NULL) { 3123 DPRINTF("allocating chunk", 0, 0, 0, 0); 3124 mutex_exit(&sc->sc_lock); 3125 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3126 EHCI_PAGE_SIZE, &dma); 3127 3128 if (err) { 3129 DPRINTF("alloc returned %d", err, 0, 0, 3130 0); 3131 return NULL; 3132 } 3133 3134 mutex_enter(&sc->sc_lock); 3135 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3136 offs = i * EHCI_SITD_SIZE; 3137 sitd = KERNADDR(&dma, offs); 3138 sitd->physaddr = DMAADDR(&dma, offs); 3139 sitd->dma = dma; 3140 sitd->offs = offs; 3141 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3142 } 3143 freesitd = LIST_FIRST(&sc->sc_freesitds); 3144 } 3145 3146 sitd = freesitd; 3147 LIST_REMOVE(sitd, free_list); 3148 mutex_exit(&sc->sc_lock); 3149 3150 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3151 3152 sitd->frame_list.next = NULL; 3153 sitd->frame_list.prev = NULL; 3154 sitd->xfer_next = NULL; 3155 sitd->slot = 0; 3156 3157 return sitd; 3158 } 3159 3160 /****************/ 3161 3162 /* 3163 * Close a reqular pipe. 3164 * Assumes that there are no pending transactions. 3165 */ 3166 Static void 3167 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3168 { 3169 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3170 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3171 ehci_soft_qh_t *sqh = epipe->sqh; 3172 3173 KASSERT(mutex_owned(&sc->sc_lock)); 3174 3175 ehci_rem_qh(sc, sqh, head); 3176 ehci_free_sqh(sc, epipe->sqh); 3177 } 3178 3179 /* 3180 * Abort a device request. 3181 * If this routine is called at splusb() it guarantees that the request 3182 * will be removed from the hardware scheduling and that the callback 3183 * for it will be called with USBD_CANCELLED status. 3184 * It's impossible to guarantee that the requested transfer will not 3185 * have happened since the hardware runs concurrently. 3186 * If the transaction has already happened we rely on the ordinary 3187 * interrupt processing to process it. 3188 * XXX This is most probably wrong. 3189 * XXXMRG this doesn't make sense anymore. 3190 */ 3191 Static void 3192 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3193 { 3194 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3195 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3196 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3197 ehci_soft_qh_t *sqh = epipe->sqh; 3198 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3199 ehci_physaddr_t cur; 3200 uint32_t qhstatus; 3201 int hit; 3202 int wake; 3203 3204 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3205 3206 DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); 3207 3208 KASSERT(mutex_owned(&sc->sc_lock)); 3209 ASSERT_SLEEPABLE(); 3210 3211 if (sc->sc_dying) { 3212 /* If we're dying, just do the software part. */ 3213 xfer->ux_status = status; /* make software ignore it */ 3214 callout_stop(&xfer->ux_callout); 3215 usb_transfer_complete(xfer); 3216 return; 3217 } 3218 3219 /* 3220 * If an abort is already in progress then just wait for it to 3221 * complete and return. 3222 */ 3223 if (xfer->ux_hcflags & UXFER_ABORTING) { 3224 DPRINTF("already aborting", 0, 0, 0, 0); 3225 #ifdef DIAGNOSTIC 3226 if (status == USBD_TIMEOUT) 3227 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3228 #endif 3229 /* Override the status which might be USBD_TIMEOUT. */ 3230 xfer->ux_status = status; 3231 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3232 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3233 while (xfer->ux_hcflags & UXFER_ABORTING) 3234 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3235 return; 3236 } 3237 xfer->ux_hcflags |= UXFER_ABORTING; 3238 3239 /* 3240 * Step 1: Make interrupt routine and hardware ignore xfer. 3241 */ 3242 xfer->ux_status = status; /* make software ignore it */ 3243 callout_stop(&xfer->ux_callout); 3244 ehci_del_intr_list(sc, exfer); 3245 3246 usb_syncmem(&sqh->dma, 3247 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3248 sizeof(sqh->qh.qh_qtd.qtd_status), 3249 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3250 qhstatus = sqh->qh.qh_qtd.qtd_status; 3251 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3252 usb_syncmem(&sqh->dma, 3253 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3254 sizeof(sqh->qh.qh_qtd.qtd_status), 3255 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3256 3257 if (exfer->ex_type == EX_CTRL) { 3258 fsqtd = exfer->ex_setup; 3259 lsqtd = exfer->ex_status; 3260 } else { 3261 fsqtd = exfer->ex_sqtdstart; 3262 lsqtd = exfer->ex_sqtdend; 3263 } 3264 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3265 usb_syncmem(&sqtd->dma, 3266 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3267 sizeof(sqtd->qtd.qtd_status), 3268 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3269 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3270 usb_syncmem(&sqtd->dma, 3271 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3272 sizeof(sqtd->qtd.qtd_status), 3273 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3274 if (sqtd == lsqtd) 3275 break; 3276 } 3277 3278 /* 3279 * Step 2: Wait until we know hardware has finished any possible 3280 * use of the xfer. Also make sure the soft interrupt routine 3281 * has run. 3282 */ 3283 ehci_sync_hc(sc); 3284 sc->sc_softwake = 1; 3285 usb_schedsoftintr(&sc->sc_bus); 3286 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3287 3288 /* 3289 * Step 3: Remove any vestiges of the xfer from the hardware. 3290 * The complication here is that the hardware may have executed 3291 * beyond the xfer we're trying to abort. So as we're scanning 3292 * the TDs of this xfer we check if the hardware points to 3293 * any of them. 3294 */ 3295 3296 usb_syncmem(&sqh->dma, 3297 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3298 sizeof(sqh->qh.qh_curqtd), 3299 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3300 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3301 hit = 0; 3302 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3303 hit |= cur == sqtd->physaddr; 3304 if (sqtd == lsqtd) 3305 break; 3306 } 3307 sqtd = sqtd->nextqtd; 3308 /* Zap curqtd register if hardware pointed inside the xfer. */ 3309 if (hit && sqtd != NULL) { 3310 DPRINTF("cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3311 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3312 usb_syncmem(&sqh->dma, 3313 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3314 sizeof(sqh->qh.qh_curqtd), 3315 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3316 sqh->qh.qh_qtd.qtd_status = qhstatus; 3317 usb_syncmem(&sqh->dma, 3318 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3319 sizeof(sqh->qh.qh_qtd.qtd_status), 3320 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3321 } else { 3322 DPRINTF("no hit", 0, 0, 0, 0); 3323 usb_syncmem(&sqh->dma, 3324 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3325 sizeof(sqh->qh.qh_curqtd), 3326 BUS_DMASYNC_PREREAD); 3327 } 3328 3329 /* 3330 * Step 4: Execute callback. 3331 */ 3332 #ifdef DIAGNOSTIC 3333 exfer->ex_isdone = true; 3334 #endif 3335 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3336 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3337 usb_transfer_complete(xfer); 3338 if (wake) { 3339 cv_broadcast(&xfer->ux_hccv); 3340 } 3341 3342 KASSERT(mutex_owned(&sc->sc_lock)); 3343 } 3344 3345 Static void 3346 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3347 { 3348 ehci_isoc_trans_t trans_status; 3349 struct ehci_xfer *exfer; 3350 ehci_softc_t *sc; 3351 struct ehci_soft_itd *itd; 3352 struct ehci_soft_sitd *sitd; 3353 int i, wake; 3354 3355 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3356 3357 exfer = EHCI_XFER2EXFER(xfer); 3358 sc = EHCI_XFER2SC(xfer); 3359 3360 DPRINTF("xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3361 3362 KASSERT(mutex_owned(&sc->sc_lock)); 3363 3364 if (sc->sc_dying) { 3365 xfer->ux_status = status; 3366 callout_stop(&xfer->ux_callout); 3367 usb_transfer_complete(xfer); 3368 return; 3369 } 3370 3371 if (xfer->ux_hcflags & UXFER_ABORTING) { 3372 DPRINTF("already aborting", 0, 0, 0, 0); 3373 3374 #ifdef DIAGNOSTIC 3375 if (status == USBD_TIMEOUT) 3376 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3377 #endif 3378 3379 xfer->ux_status = status; 3380 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3381 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3382 while (xfer->ux_hcflags & UXFER_ABORTING) 3383 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3384 goto done; 3385 } 3386 xfer->ux_hcflags |= UXFER_ABORTING; 3387 3388 xfer->ux_status = status; 3389 callout_stop(&xfer->ux_callout); 3390 ehci_del_intr_list(sc, exfer); 3391 3392 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3393 for (itd = exfer->ex_itdstart; itd != NULL; 3394 itd = itd->xfer_next) { 3395 usb_syncmem(&itd->dma, 3396 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3397 sizeof(itd->itd.itd_ctl), 3398 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3399 3400 for (i = 0; i < 8; i++) { 3401 trans_status = le32toh(itd->itd.itd_ctl[i]); 3402 trans_status &= ~EHCI_ITD_ACTIVE; 3403 itd->itd.itd_ctl[i] = htole32(trans_status); 3404 } 3405 3406 usb_syncmem(&itd->dma, 3407 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3408 sizeof(itd->itd.itd_ctl), 3409 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3410 } 3411 } else { 3412 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3413 sitd = sitd->xfer_next) { 3414 usb_syncmem(&sitd->dma, 3415 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3416 sizeof(sitd->sitd.sitd_buffer), 3417 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3418 3419 trans_status = le32toh(sitd->sitd.sitd_trans); 3420 trans_status &= ~EHCI_SITD_ACTIVE; 3421 sitd->sitd.sitd_trans = htole32(trans_status); 3422 3423 usb_syncmem(&sitd->dma, 3424 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3425 sizeof(sitd->sitd.sitd_buffer), 3426 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3427 } 3428 } 3429 3430 sc->sc_softwake = 1; 3431 usb_schedsoftintr(&sc->sc_bus); 3432 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3433 3434 #ifdef DIAGNOSTIC 3435 exfer->ex_isdone = true; 3436 #endif 3437 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3438 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3439 usb_transfer_complete(xfer); 3440 if (wake) { 3441 cv_broadcast(&xfer->ux_hccv); 3442 } 3443 3444 done: 3445 KASSERT(mutex_owned(&sc->sc_lock)); 3446 return; 3447 } 3448 3449 Static void 3450 ehci_timeout(void *addr) 3451 { 3452 struct usbd_xfer *xfer = addr; 3453 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3454 struct usbd_pipe *pipe = xfer->ux_pipe; 3455 struct usbd_device *dev = pipe->up_dev; 3456 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3457 3458 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3459 3460 DPRINTF("exfer %p", exfer, 0, 0, 0); 3461 #ifdef EHCI_DEBUG 3462 if (ehcidebug >= 2) 3463 usbd_dump_pipe(pipe); 3464 #endif 3465 3466 if (sc->sc_dying) { 3467 mutex_enter(&sc->sc_lock); 3468 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3469 mutex_exit(&sc->sc_lock); 3470 return; 3471 } 3472 3473 /* Execute the abort in a process context. */ 3474 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3475 USB_TASKQ_MPSAFE); 3476 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3477 } 3478 3479 Static void 3480 ehci_timeout_task(void *addr) 3481 { 3482 struct usbd_xfer *xfer = addr; 3483 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3484 3485 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3486 3487 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3488 3489 mutex_enter(&sc->sc_lock); 3490 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3491 mutex_exit(&sc->sc_lock); 3492 } 3493 3494 /************************/ 3495 3496 Static int 3497 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3498 { 3499 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3500 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3501 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3502 usb_device_request_t *req = &xfer->ux_request; 3503 ehci_soft_qtd_t *setup, *status, *next; 3504 int isread = req->bmRequestType & UT_READ; 3505 int len = xfer->ux_bufsize; 3506 int err; 3507 3508 exfer->ex_type = EX_CTRL; 3509 exfer->ex_status = NULL; 3510 exfer->ex_data = NULL; 3511 exfer->ex_setup = ehci_alloc_sqtd(sc); 3512 if (exfer->ex_setup == NULL) { 3513 err = ENOMEM; 3514 goto bad1; 3515 } 3516 exfer->ex_status = ehci_alloc_sqtd(sc); 3517 if (exfer->ex_status == NULL) { 3518 err = ENOMEM; 3519 goto bad2; 3520 } 3521 setup = exfer->ex_setup; 3522 status = exfer->ex_status; 3523 exfer->ex_nsqtd = 0; 3524 next = status; 3525 /* Set up data transaction */ 3526 if (len != 0) { 3527 ehci_soft_qtd_t *end; 3528 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3529 &exfer->ex_data, &end); 3530 if (err) 3531 goto bad3; 3532 next = exfer->ex_data; 3533 } 3534 3535 /* Clear toggle */ 3536 setup->qtd.qtd_status = htole32( 3537 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3538 EHCI_QTD_SET_TOGGLE(0) | 3539 EHCI_QTD_SET_BYTES(sizeof(*req)) 3540 ); 3541 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3542 setup->qtd.qtd_buffer_hi[0] = 0; 3543 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3544 setup->nextqtd = next; 3545 setup->xfer = xfer; 3546 setup->tdlen = setup->len = sizeof(*req); 3547 3548 status->qtd.qtd_status = htole32( 3549 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3550 EHCI_QTD_SET_TOGGLE(1) | 3551 EHCI_QTD_IOC 3552 ); 3553 status->qtd.qtd_buffer[0] = 0; 3554 status->qtd.qtd_buffer_hi[0] = 0; 3555 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3556 status->nextqtd = NULL; 3557 status->xfer = xfer; 3558 status->tdlen = status->len = 0; 3559 3560 return 0; 3561 bad3: 3562 ehci_free_sqtd(sc, exfer->ex_status); 3563 bad2: 3564 ehci_free_sqtd(sc, exfer->ex_setup); 3565 bad1: 3566 return err; 3567 } 3568 3569 Static void 3570 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3571 { 3572 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3573 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3574 3575 KASSERT(ex->ex_type == EX_CTRL); 3576 3577 ehci_free_sqtd(sc, ex->ex_setup); 3578 ehci_free_sqtd(sc, ex->ex_status); 3579 ehci_free_sqtds(sc, ex); 3580 if (ex->ex_nsqtd) 3581 kmem_free(ex->ex_sqtds, 3582 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3583 } 3584 3585 Static usbd_status 3586 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3587 { 3588 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3589 usbd_status err; 3590 3591 /* Insert last in queue. */ 3592 mutex_enter(&sc->sc_lock); 3593 err = usb_insert_transfer(xfer); 3594 mutex_exit(&sc->sc_lock); 3595 if (err) 3596 return err; 3597 3598 /* Pipe isn't running, start first */ 3599 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3600 } 3601 3602 Static usbd_status 3603 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3604 { 3605 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3606 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3607 usb_device_request_t *req = &xfer->ux_request; 3608 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3609 ehci_soft_qtd_t *setup, *status, *next; 3610 ehci_soft_qh_t *sqh; 3611 3612 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3613 3614 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3615 3616 if (sc->sc_dying) 3617 return USBD_IOERROR; 3618 3619 const int isread = req->bmRequestType & UT_READ; 3620 const int len = UGETW(req->wLength); 3621 3622 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 3623 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3624 UGETW(req->wIndex)); 3625 DPRINTF("len=%d, addr=%d, endpt=%d", len, epipe->pipe.up_dev->ud_addr, 3626 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3627 3628 sqh = epipe->sqh; 3629 3630 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3631 "address QH %" __PRIuBIT " pipe %d\n", 3632 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3633 epipe->pipe.up_dev->ud_addr); 3634 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3635 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3636 "MPS QH %" __PRIuBIT " pipe %d\n", 3637 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3638 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3639 3640 setup = exfer->ex_setup; 3641 status = exfer->ex_status; 3642 3643 DPRINTF("setup %p status %p data %p", setup, status, exfer->ex_data, 0); 3644 KASSERTMSG(setup != NULL && status != NULL, 3645 "Failed memory allocation, setup %p status %p", 3646 setup, status); 3647 3648 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3649 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3650 3651 /* Clear toggle */ 3652 setup->qtd.qtd_status &= ~htole32( 3653 EHCI_QTD_STATUS_MASK | 3654 EHCI_QTD_BYTES_MASK | 3655 EHCI_QTD_TOGGLE_MASK | 3656 EHCI_QTD_CERR_MASK 3657 ); 3658 setup->qtd.qtd_status |= htole32( 3659 EHCI_QTD_ACTIVE | 3660 EHCI_QTD_SET_CERR(3) | 3661 EHCI_QTD_SET_TOGGLE(0) | 3662 EHCI_QTD_SET_BYTES(sizeof(*req)) 3663 ); 3664 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3665 setup->qtd.qtd_buffer_hi[0] = 0; 3666 3667 next = status; 3668 status->qtd.qtd_status &= ~htole32( 3669 EHCI_QTD_STATUS_MASK | 3670 EHCI_QTD_PID_MASK | 3671 EHCI_QTD_BYTES_MASK | 3672 EHCI_QTD_TOGGLE_MASK | 3673 EHCI_QTD_CERR_MASK 3674 ); 3675 status->qtd.qtd_status |= htole32( 3676 EHCI_QTD_ACTIVE | 3677 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3678 EHCI_QTD_SET_CERR(3) | 3679 EHCI_QTD_SET_TOGGLE(1) | 3680 EHCI_QTD_SET_BYTES(0) | 3681 EHCI_QTD_IOC 3682 ); 3683 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3684 3685 KASSERT(exfer->ex_isdone); 3686 #ifdef DIAGNOSTIC 3687 exfer->ex_isdone = false; 3688 #endif 3689 3690 /* Set up data transaction */ 3691 if (len != 0) { 3692 ehci_soft_qtd_t *end; 3693 3694 /* Start toggle at 1. */ 3695 int toggle = 1; 3696 next = exfer->ex_data; 3697 KASSERTMSG(next != NULL, "Failed memory allocation"); 3698 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3699 end->nextqtd = status; 3700 end->qtd.qtd_next = end->qtd.qtd_altnext = 3701 htole32(status->physaddr); 3702 3703 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3704 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3705 3706 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3707 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3708 } 3709 3710 setup->nextqtd = next; 3711 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3712 3713 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3714 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3715 3716 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3717 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3718 3719 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3720 3721 #ifdef EHCI_DEBUG 3722 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3723 ehci_dump_sqh(sqh); 3724 ehci_dump_sqtds(setup); 3725 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3726 #endif 3727 3728 mutex_enter(&sc->sc_lock); 3729 3730 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3731 ehci_set_qh_qtd(sqh, setup); 3732 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3733 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3734 ehci_timeout, xfer); 3735 } 3736 ehci_add_intr_list(sc, exfer); 3737 xfer->ux_status = USBD_IN_PROGRESS; 3738 mutex_exit(&sc->sc_lock); 3739 3740 #if 0 3741 #ifdef EHCI_DEBUG 3742 DPRINTFN(10, "status=%x, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3743 // delay(10000); 3744 ehci_dump_regs(sc); 3745 ehci_dump_sqh(sc->sc_async_head); 3746 ehci_dump_sqh(sqh); 3747 ehci_dump_sqtds(setup); 3748 #endif 3749 #endif 3750 3751 if (sc->sc_bus.ub_usepolling) 3752 ehci_waitintr(sc, xfer); 3753 3754 return USBD_IN_PROGRESS; 3755 } 3756 3757 Static void 3758 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3759 { 3760 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3761 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3762 usb_device_request_t *req = &xfer->ux_request; 3763 int len = UGETW(req->wLength); 3764 int rd = req->bmRequestType & UT_READ; 3765 3766 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3767 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3768 3769 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3770 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3771 3772 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3773 BUS_DMASYNC_POSTWRITE); 3774 if (len) 3775 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3776 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3777 3778 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3779 } 3780 3781 /* Abort a device control request. */ 3782 Static void 3783 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3784 { 3785 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3786 3787 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3788 ehci_abort_xfer(xfer, USBD_CANCELLED); 3789 } 3790 3791 /* Close a device control pipe. */ 3792 Static void 3793 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3794 { 3795 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3796 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3797 3798 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3799 3800 KASSERT(mutex_owned(&sc->sc_lock)); 3801 3802 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3803 3804 ehci_close_pipe(pipe, sc->sc_async_head); 3805 } 3806 3807 /* 3808 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3809 * qTD status, or miss signalling occasionally under heavy load. If the host 3810 * machine is too fast, we we can miss transaction completion - when we scan 3811 * the active list the transaction still seems to be active. This generally 3812 * exhibits itself as a umass stall that never recovers. 3813 * 3814 * We work around this behaviour by setting up this callback after any softintr 3815 * that completes with transactions still pending, giving us another chance to 3816 * check for completion after the writeback has taken place. 3817 */ 3818 Static void 3819 ehci_intrlist_timeout(void *arg) 3820 { 3821 ehci_softc_t *sc = arg; 3822 3823 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3824 3825 usb_schedsoftintr(&sc->sc_bus); 3826 } 3827 3828 /************************/ 3829 3830 Static int 3831 ehci_device_bulk_init(struct usbd_xfer *xfer) 3832 { 3833 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3834 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3835 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3836 int endpt = ed->bEndpointAddress; 3837 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3838 int len = xfer->ux_bufsize; 3839 int err = 0; 3840 3841 exfer->ex_type = EX_BULK; 3842 exfer->ex_nsqtd = 0; 3843 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3844 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 3845 3846 return err; 3847 } 3848 3849 Static void 3850 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3851 { 3852 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3853 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3854 3855 KASSERT(ex->ex_type == EX_BULK); 3856 3857 ehci_free_sqtds(sc, ex); 3858 if (ex->ex_nsqtd) 3859 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3860 } 3861 3862 Static usbd_status 3863 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3864 { 3865 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3866 usbd_status err; 3867 3868 /* Insert last in queue. */ 3869 mutex_enter(&sc->sc_lock); 3870 err = usb_insert_transfer(xfer); 3871 mutex_exit(&sc->sc_lock); 3872 if (err) 3873 return err; 3874 3875 /* Pipe isn't running, start first */ 3876 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3877 } 3878 3879 Static usbd_status 3880 ehci_device_bulk_start(struct usbd_xfer *xfer) 3881 { 3882 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3883 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3884 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3885 ehci_soft_qh_t *sqh; 3886 ehci_soft_qtd_t *end; 3887 int len, isread, endpt; 3888 3889 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3890 3891 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3892 xfer->ux_flags, 0); 3893 3894 if (sc->sc_dying) 3895 return USBD_IOERROR; 3896 3897 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3898 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3899 3900 len = xfer->ux_length; 3901 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3902 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3903 sqh = epipe->sqh; 3904 3905 KASSERT(exfer->ex_isdone); 3906 #ifdef DIAGNOSTIC 3907 exfer->ex_isdone = false; 3908 #endif 3909 3910 /* Take lock here to protect nexttoggle */ 3911 mutex_enter(&sc->sc_lock); 3912 3913 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3914 3915 exfer->ex_sqtdend = end; 3916 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3917 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3918 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3919 3920 #ifdef EHCI_DEBUG 3921 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3922 ehci_dump_sqh(sqh); 3923 ehci_dump_sqtds(exfer->ex_sqtdstart); 3924 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3925 #endif 3926 3927 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3928 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3929 3930 /* also does usb_syncmem(sqh) */ 3931 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3932 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3933 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3934 ehci_timeout, xfer); 3935 } 3936 ehci_add_intr_list(sc, exfer); 3937 xfer->ux_status = USBD_IN_PROGRESS; 3938 mutex_exit(&sc->sc_lock); 3939 3940 #if 0 3941 #ifdef EHCI_DEBUG 3942 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3943 // delay(10000); 3944 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3945 ehci_dump_regs(sc); 3946 #if 0 3947 printf("async_head:\n"); 3948 ehci_dump_sqh(sc->sc_async_head); 3949 #endif 3950 DPRINTF("sqh:", 0, 0, 0, 0); 3951 ehci_dump_sqh(sqh); 3952 ehci_dump_sqtds(exfer->ex_sqtdstart); 3953 #endif 3954 #endif 3955 3956 if (sc->sc_bus.ub_usepolling) 3957 ehci_waitintr(sc, xfer); 3958 3959 return USBD_IN_PROGRESS; 3960 } 3961 3962 Static void 3963 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3964 { 3965 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3966 3967 DPRINTF("xfer %p", xfer, 0, 0, 0); 3968 ehci_abort_xfer(xfer, USBD_CANCELLED); 3969 } 3970 3971 /* 3972 * Close a device bulk pipe. 3973 */ 3974 Static void 3975 ehci_device_bulk_close(struct usbd_pipe *pipe) 3976 { 3977 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3978 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3979 3980 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3981 3982 KASSERT(mutex_owned(&sc->sc_lock)); 3983 3984 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3985 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3986 ehci_close_pipe(pipe, sc->sc_async_head); 3987 } 3988 3989 Static void 3990 ehci_device_bulk_done(struct usbd_xfer *xfer) 3991 { 3992 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3993 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3994 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3995 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3996 3997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3998 3999 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 4000 4001 KASSERT(mutex_owned(&sc->sc_lock)); 4002 4003 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4004 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4005 4006 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 4007 } 4008 4009 /************************/ 4010 4011 Static usbd_status 4012 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4013 { 4014 struct ehci_soft_islot *isp; 4015 int islot, lev; 4016 4017 /* Find a poll rate that is large enough. */ 4018 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4019 if (EHCI_ILEV_IVAL(lev) <= ival) 4020 break; 4021 4022 /* Pick an interrupt slot at the right level. */ 4023 /* XXX could do better than picking at random */ 4024 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4025 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4026 4027 sqh->islot = islot; 4028 isp = &sc->sc_islots[islot]; 4029 mutex_enter(&sc->sc_lock); 4030 ehci_add_qh(sc, sqh, isp->sqh); 4031 mutex_exit(&sc->sc_lock); 4032 4033 return USBD_NORMAL_COMPLETION; 4034 } 4035 4036 4037 Static int 4038 ehci_device_intr_init(struct usbd_xfer *xfer) 4039 { 4040 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4041 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4042 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4043 int endpt = ed->bEndpointAddress; 4044 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4045 int len = xfer->ux_bufsize; 4046 int err; 4047 4048 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4049 4050 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4051 xfer->ux_flags, 0); 4052 4053 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4054 KASSERT(len != 0); 4055 4056 exfer->ex_type = EX_INTR; 4057 exfer->ex_nsqtd = 0; 4058 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4059 &exfer->ex_sqtdstart, &exfer->ex_sqtdend); 4060 4061 return err; 4062 } 4063 4064 Static void 4065 ehci_device_intr_fini(struct usbd_xfer *xfer) 4066 { 4067 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4068 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4069 4070 KASSERT(ex->ex_type == EX_INTR); 4071 4072 ehci_free_sqtds(sc, ex); 4073 if (ex->ex_nsqtd) 4074 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4075 } 4076 4077 Static usbd_status 4078 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4079 { 4080 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4081 usbd_status err; 4082 4083 /* Insert last in queue. */ 4084 mutex_enter(&sc->sc_lock); 4085 err = usb_insert_transfer(xfer); 4086 mutex_exit(&sc->sc_lock); 4087 if (err) 4088 return err; 4089 4090 /* 4091 * Pipe isn't running (otherwise err would be USBD_INPROG), 4092 * so start it first. 4093 */ 4094 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4095 } 4096 4097 Static usbd_status 4098 ehci_device_intr_start(struct usbd_xfer *xfer) 4099 { 4100 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4101 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4102 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4103 ehci_soft_qtd_t *end; 4104 ehci_soft_qh_t *sqh; 4105 int len, isread, endpt; 4106 4107 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4108 4109 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4110 xfer->ux_flags, 0); 4111 4112 if (sc->sc_dying) 4113 return USBD_IOERROR; 4114 4115 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4116 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4117 4118 len = xfer->ux_length; 4119 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4120 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4121 sqh = epipe->sqh; 4122 4123 KASSERT(exfer->ex_isdone); 4124 #ifdef DIAGNOSTIC 4125 exfer->ex_isdone = false; 4126 #endif 4127 4128 /* Take lock to protect nexttoggle */ 4129 mutex_enter(&sc->sc_lock); 4130 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4131 4132 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4133 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4134 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4135 exfer->ex_sqtdend = end; 4136 4137 #ifdef EHCI_DEBUG 4138 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4139 ehci_dump_sqh(sqh); 4140 ehci_dump_sqtds(exfer->ex_sqtdstart); 4141 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4142 #endif 4143 4144 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4145 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4146 4147 /* also does usb_syncmem(sqh) */ 4148 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4149 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4150 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4151 ehci_timeout, xfer); 4152 } 4153 ehci_add_intr_list(sc, exfer); 4154 xfer->ux_status = USBD_IN_PROGRESS; 4155 mutex_exit(&sc->sc_lock); 4156 4157 #if 0 4158 #ifdef EHCI_DEBUG 4159 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4160 // delay(10000); 4161 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4162 ehci_dump_regs(sc); 4163 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4164 ehci_dump_sqh(sqh); 4165 ehci_dump_sqtds(exfer->ex_sqtdstart); 4166 #endif 4167 #endif 4168 4169 if (sc->sc_bus.ub_usepolling) 4170 ehci_waitintr(sc, xfer); 4171 4172 return USBD_IN_PROGRESS; 4173 } 4174 4175 Static void 4176 ehci_device_intr_abort(struct usbd_xfer *xfer) 4177 { 4178 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4179 4180 DPRINTF("xfer=%p", xfer, 0, 0, 0); 4181 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4182 4183 /* 4184 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4185 * async doorbell. That's dependent on the async list, wheras 4186 * intr xfers are periodic, should not use this? 4187 */ 4188 ehci_abort_xfer(xfer, USBD_CANCELLED); 4189 } 4190 4191 Static void 4192 ehci_device_intr_close(struct usbd_pipe *pipe) 4193 { 4194 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4195 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4196 struct ehci_soft_islot *isp; 4197 4198 KASSERT(mutex_owned(&sc->sc_lock)); 4199 4200 isp = &sc->sc_islots[epipe->sqh->islot]; 4201 ehci_close_pipe(pipe, isp->sqh); 4202 } 4203 4204 Static void 4205 ehci_device_intr_done(struct usbd_xfer *xfer) 4206 { 4207 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4208 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4209 int isread, endpt; 4210 4211 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4212 4213 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4214 0, 0); 4215 4216 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4217 4218 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4219 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4220 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4221 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4222 } 4223 4224 /************************/ 4225 Static int 4226 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4227 { 4228 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4229 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4230 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4231 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4232 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4233 int i, k, frames; 4234 u_int huba, dir; 4235 int err; 4236 4237 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4238 4239 start = NULL; 4240 sitd = NULL; 4241 4242 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4243 xfer->ux_flags, 0); 4244 4245 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4246 KASSERT(xfer->ux_nframes != 0); 4247 KASSERT(exfer->ex_isdone); 4248 4249 exfer->ex_type = EX_FS_ISOC; 4250 /* 4251 * Step 1: Allocate and initialize sitds. 4252 */ 4253 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4254 if (i > 16 || i == 0) { 4255 /* Spec page 271 says intervals > 16 are invalid */ 4256 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4257 4258 return EINVAL; 4259 } 4260 4261 frames = xfer->ux_nframes; 4262 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4263 sitd = ehci_alloc_sitd(sc); 4264 if (sitd == NULL) { 4265 err = ENOMEM; 4266 goto fail; 4267 } 4268 4269 if (prev) 4270 prev->xfer_next = sitd; 4271 else 4272 start = sitd; 4273 4274 huba = dev->ud_myhsport->up_parent->ud_addr; 4275 4276 #if 0 4277 if (sc->sc_flags & EHCIF_FREESCALE) { 4278 // Set hub address to 0 if embedded TT is used. 4279 if (huba == sc->sc_addr) 4280 huba = 0; 4281 } 4282 #endif 4283 4284 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4285 dir = UE_GET_DIR(k) ? 1 : 0; 4286 sitd->sitd.sitd_endp = 4287 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4288 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4289 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4290 EHCI_SITD_SET_HUBA(huba) | 4291 EHCI_SITD_SET_DIR(dir)); 4292 4293 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4294 } /* End of frame */ 4295 4296 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4297 4298 stop = sitd; 4299 stop->xfer_next = NULL; 4300 exfer->ex_sitdstart = start; 4301 exfer->ex_sitdend = stop; 4302 4303 return 0; 4304 4305 fail: 4306 mutex_enter(&sc->sc_lock); 4307 ehci_soft_sitd_t *next; 4308 for (sitd = start; sitd; sitd = next) { 4309 next = sitd->xfer_next; 4310 ehci_free_sitd_locked(sc, sitd); 4311 } 4312 mutex_exit(&sc->sc_lock); 4313 4314 return err; 4315 } 4316 4317 Static void 4318 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4319 { 4320 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4321 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4322 4323 KASSERT(ex->ex_type == EX_FS_ISOC); 4324 4325 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4326 } 4327 4328 Static usbd_status 4329 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4330 { 4331 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4332 usbd_status __diagused err; 4333 4334 mutex_enter(&sc->sc_lock); 4335 err = usb_insert_transfer(xfer); 4336 mutex_exit(&sc->sc_lock); 4337 4338 KASSERT(err == USBD_NORMAL_COMPLETION); 4339 4340 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4341 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4342 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4343 ehci_soft_sitd_t *sitd; 4344 usb_dma_t *dma_buf; 4345 int i, j, k, frames; 4346 int offs, total_length; 4347 int frindex; 4348 u_int dir; 4349 4350 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4351 4352 sitd = NULL; 4353 total_length = 0; 4354 4355 4356 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4357 xfer->ux_flags, 0); 4358 4359 if (sc->sc_dying) 4360 return USBD_IOERROR; 4361 4362 /* 4363 * To avoid complication, don't allow a request right now that'll span 4364 * the entire frame table. To within 4 frames, to allow some leeway 4365 * on either side of where the hc currently is. 4366 */ 4367 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4368 xfer->ux_nframes >= sc->sc_flsize - 4) { 4369 printf("ehci: isoc descriptor requested that spans the entire" 4370 "frametable, too many frames\n"); 4371 return USBD_INVAL; 4372 } 4373 4374 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4375 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4376 KASSERT(exfer->ex_isdone); 4377 #ifdef DIAGNOSTIC 4378 exfer->ex_isdone = false; 4379 #endif 4380 4381 /* 4382 * Step 1: Initialize sitds. 4383 */ 4384 4385 frames = xfer->ux_nframes; 4386 dma_buf = &xfer->ux_dmabuf; 4387 offs = 0; 4388 4389 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4390 i++, sitd = sitd->xfer_next) { 4391 KASSERT(sitd != NULL); 4392 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4393 4394 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4395 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4396 4397 /* Set page0 index and offset - TP and T-offset are set below */ 4398 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4399 4400 total_length += xfer->ux_frlengths[i]; 4401 offs += xfer->ux_frlengths[i]; 4402 4403 sitd->sitd.sitd_buffer[1] = 4404 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4405 4406 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4407 4408 #if 0 4409 if (sc->sc_flags & EHCIF_FREESCALE) { 4410 // Set hub address to 0 if embedded TT is used. 4411 if (huba == sc->sc_addr) 4412 huba = 0; 4413 } 4414 #endif 4415 4416 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4417 dir = UE_GET_DIR(k) ? 1 : 0; 4418 KASSERT(sitd->sitd.sitd_endp == htole32( 4419 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4420 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4421 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4422 EHCI_SITD_SET_HUBA(huba) | 4423 EHCI_SITD_SET_DIR(dir))); 4424 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4425 4426 uint8_t sa = 0; 4427 uint8_t sb = 0; 4428 u_int temp, tlen; 4429 4430 if (dir == 0) { /* OUT */ 4431 temp = 0; 4432 tlen = xfer->ux_frlengths[i]; 4433 if (tlen <= 188) { 4434 temp |= 1; /* T-count = 1, TP = ALL */ 4435 tlen = 1; 4436 } else { 4437 tlen += 187; 4438 tlen /= 188; 4439 temp |= tlen; /* T-count = [1..6] */ 4440 temp |= 8; /* TP = Begin */ 4441 } 4442 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4443 4444 tlen += sa; 4445 4446 if (tlen >= 8) { 4447 sb = 0; 4448 } else { 4449 sb = (1 << tlen); 4450 } 4451 4452 sa = (1 << sa); 4453 sa = (sb - sa) & 0x3F; 4454 sb = 0; 4455 } else { 4456 sb = (-(4 << sa)) & 0xFE; 4457 sa = (1 << sa) & 0x3F; 4458 sa = 0x01; 4459 sb = 0xfc; 4460 } 4461 4462 sitd->sitd.sitd_sched = htole32( 4463 EHCI_SITD_SET_SMASK(sa) | 4464 EHCI_SITD_SET_CMASK(sb) 4465 ); 4466 4467 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4469 } /* End of frame */ 4470 4471 sitd = exfer->ex_sitdend; 4472 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4473 4474 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4475 sizeof(sitd->sitd.sitd_trans), 4476 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4477 4478 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4479 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4480 4481 /* 4482 * Part 2: Transfer descriptors have now been set up, now they must 4483 * be scheduled into the periodic frame list. Erk. Not wanting to 4484 * complicate matters, transfer is denied if the transfer spans 4485 * more than the period frame list. 4486 */ 4487 4488 mutex_enter(&sc->sc_lock); 4489 4490 /* Start inserting frames */ 4491 if (epipe->isoc.cur_xfers > 0) { 4492 frindex = epipe->isoc.next_frame; 4493 } else { 4494 frindex = EOREAD4(sc, EHCI_FRINDEX); 4495 frindex = frindex >> 3; /* Erase microframe index */ 4496 frindex += 2; 4497 } 4498 4499 if (frindex >= sc->sc_flsize) 4500 frindex &= (sc->sc_flsize - 1); 4501 4502 /* Whats the frame interval? */ 4503 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4504 4505 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4506 j++, sitd = sitd->xfer_next) { 4507 KASSERT(sitd); 4508 4509 usb_syncmem(&sc->sc_fldma, 4510 sizeof(ehci_link_t) * frindex, 4511 sizeof(ehci_link_t), 4512 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4513 4514 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4515 if (sitd->sitd.sitd_next == 0) 4516 /* 4517 * FIXME: frindex table gets initialized to NULL 4518 * or EHCI_NULL? 4519 */ 4520 sitd->sitd.sitd_next = EHCI_NULL; 4521 4522 usb_syncmem(&sitd->dma, 4523 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4524 sizeof(ehci_sitd_t), 4525 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4526 4527 sc->sc_flist[frindex] = 4528 htole32(EHCI_LINK_SITD | sitd->physaddr); 4529 4530 usb_syncmem(&sc->sc_fldma, 4531 sizeof(ehci_link_t) * frindex, 4532 sizeof(ehci_link_t), 4533 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4534 4535 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4536 sc->sc_softsitds[frindex] = sitd; 4537 if (sitd->frame_list.next != NULL) 4538 sitd->frame_list.next->frame_list.prev = sitd; 4539 sitd->slot = frindex; 4540 sitd->frame_list.prev = NULL; 4541 4542 frindex += i; 4543 if (frindex >= sc->sc_flsize) 4544 frindex -= sc->sc_flsize; 4545 } 4546 4547 epipe->isoc.cur_xfers++; 4548 epipe->isoc.next_frame = frindex; 4549 4550 ehci_add_intr_list(sc, exfer); 4551 xfer->ux_status = USBD_IN_PROGRESS; 4552 4553 mutex_exit(&sc->sc_lock); 4554 4555 if (sc->sc_bus.ub_usepolling) { 4556 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4557 ehci_waitintr(sc, xfer); 4558 } 4559 4560 return USBD_IN_PROGRESS; 4561 } 4562 4563 Static void 4564 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4565 { 4566 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4567 4568 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4569 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4570 } 4571 4572 Static void 4573 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4574 { 4575 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4576 4577 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4578 } 4579 4580 Static void 4581 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4582 { 4583 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4584 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4585 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4586 4587 KASSERT(mutex_owned(&sc->sc_lock)); 4588 4589 epipe->isoc.cur_xfers--; 4590 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4591 4592 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4593 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4594 } 4595 4596 4597 /************************/ 4598 4599 4600 Static int 4601 ehci_device_isoc_init(struct usbd_xfer *xfer) 4602 { 4603 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4604 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4605 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4606 ehci_soft_itd_t *itd, *prev, *start, *stop; 4607 int i, j, k; 4608 int frames, ufrperframe; 4609 int err; 4610 4611 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4612 4613 start = NULL; 4614 prev = NULL; 4615 itd = NULL; 4616 4617 KASSERT(xfer->ux_nframes != 0); 4618 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4619 KASSERT(exfer->ex_isdone); 4620 4621 exfer->ex_type = EX_ISOC; 4622 4623 /* 4624 * Step 1: Allocate and initialize itds, how many do we need? 4625 * One per transfer if interval >= 8 microframes, less if we use 4626 * multiple microframes per frame. 4627 */ 4628 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4629 if (i > 16 || i == 0) { 4630 /* Spec page 271 says intervals > 16 are invalid */ 4631 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4632 return USBD_INVAL; 4633 } 4634 4635 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4636 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4637 4638 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4639 itd = ehci_alloc_itd(sc); 4640 if (itd == NULL) { 4641 err = ENOMEM; 4642 goto fail; 4643 } 4644 4645 if (prev != NULL) { 4646 /* Maybe not as it's updated by the scheduling? */ 4647 prev->itd.itd_next = 4648 htole32(itd->physaddr | EHCI_LINK_ITD); 4649 4650 prev->xfer_next = itd; 4651 } else { 4652 start = itd; 4653 } 4654 4655 /* 4656 * Other special values 4657 */ 4658 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4659 itd->itd.itd_bufr[0] = htole32( 4660 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4661 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4662 4663 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4664 ? 1 : 0; 4665 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4666 itd->itd.itd_bufr[1] |= htole32( 4667 EHCI_ITD_SET_DIR(k) | 4668 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4669 4670 /* FIXME: handle invalid trans - should be done in openpipe */ 4671 itd->itd.itd_bufr[2] |= 4672 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4673 } /* End of frame */ 4674 4675 stop = itd; 4676 stop->xfer_next = NULL; 4677 4678 exfer->ex_itdstart = start; 4679 exfer->ex_itdend = stop; 4680 4681 return 0; 4682 fail: 4683 mutex_enter(&sc->sc_lock); 4684 ehci_soft_itd_t *next; 4685 for (itd = start; itd; itd = next) { 4686 next = itd->xfer_next; 4687 ehci_free_itd_locked(sc, itd); 4688 } 4689 mutex_exit(&sc->sc_lock); 4690 4691 return err; 4692 4693 } 4694 4695 Static void 4696 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4697 { 4698 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4699 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4700 4701 KASSERT(ex->ex_type == EX_ISOC); 4702 4703 ehci_free_itd_chain(sc, ex->ex_itdstart); 4704 } 4705 4706 Static usbd_status 4707 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4708 { 4709 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4710 usbd_status __diagused err; 4711 4712 mutex_enter(&sc->sc_lock); 4713 err = usb_insert_transfer(xfer); 4714 mutex_exit(&sc->sc_lock); 4715 4716 KASSERT(err == USBD_NORMAL_COMPLETION); 4717 4718 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4719 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4720 ehci_soft_itd_t *itd, *prev; 4721 usb_dma_t *dma_buf; 4722 int i, j; 4723 int frames, uframes, ufrperframe; 4724 int trans_count, offs, total_length; 4725 int frindex; 4726 4727 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4728 4729 prev = NULL; 4730 itd = NULL; 4731 trans_count = 0; 4732 total_length = 0; 4733 4734 DPRINTF("xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4735 4736 if (sc->sc_dying) 4737 return USBD_IOERROR; 4738 4739 /* 4740 * To avoid complication, don't allow a request right now that'll span 4741 * the entire frame table. To within 4 frames, to allow some leeway 4742 * on either side of where the hc currently is. 4743 */ 4744 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4745 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4746 DPRINTF( 4747 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4748 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4749 return USBD_INVAL; 4750 } 4751 4752 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4753 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4754 KASSERT(exfer->ex_isdone); 4755 #ifdef DIAGNOSTIC 4756 exfer->ex_isdone = false; 4757 #endif 4758 4759 /* 4760 * Step 1: Re-Initialize itds 4761 */ 4762 4763 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4764 if (i > 16 || i == 0) { 4765 /* Spec page 271 says intervals > 16 are invalid */ 4766 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4767 return USBD_INVAL; 4768 } 4769 4770 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4771 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4772 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4773 4774 if (frames == 0) { 4775 DPRINTF("frames == 0", 0, 0, 0, 0); 4776 return USBD_INVAL; 4777 } 4778 4779 dma_buf = &xfer->ux_dmabuf; 4780 offs = 0; 4781 4782 itd = exfer->ex_itdstart; 4783 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4784 int froffs = offs; 4785 4786 if (prev != NULL) { 4787 prev->itd.itd_next = 4788 htole32(itd->physaddr | EHCI_LINK_ITD); 4789 usb_syncmem(&prev->dma, 4790 prev->offs + offsetof(ehci_itd_t, itd_next), 4791 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4792 prev->xfer_next = itd; 4793 } 4794 4795 /* 4796 * Step 1.5, initialize uframes 4797 */ 4798 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4799 /* Calculate which page in the list this starts in */ 4800 int addr = DMAADDR(dma_buf, froffs); 4801 addr = EHCI_PAGE_OFFSET(addr); 4802 addr += (offs - froffs); 4803 addr = EHCI_PAGE(addr); 4804 addr /= EHCI_PAGE_SIZE; 4805 4806 /* 4807 * This gets the initial offset into the first page, 4808 * looks how far further along the current uframe 4809 * offset is. Works out how many pages that is. 4810 */ 4811 4812 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4813 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4814 EHCI_ITD_SET_PG(addr) | 4815 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4816 4817 total_length += xfer->ux_frlengths[trans_count]; 4818 offs += xfer->ux_frlengths[trans_count]; 4819 trans_count++; 4820 4821 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4822 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4823 break; 4824 } 4825 } 4826 4827 /* 4828 * Step 1.75, set buffer pointers. To simplify matters, all 4829 * pointers are filled out for the next 7 hardware pages in 4830 * the dma block, so no need to worry what pages to cover 4831 * and what to not. 4832 */ 4833 4834 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4835 /* 4836 * Don't try to lookup a page that's past the end 4837 * of buffer 4838 */ 4839 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4840 if (page_offs >= dma_buf->udma_block->size) 4841 break; 4842 4843 uint64_t page = DMAADDR(dma_buf, page_offs); 4844 page = EHCI_PAGE(page); 4845 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4846 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4847 } 4848 /* 4849 * Other special values 4850 */ 4851 4852 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4853 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4854 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4855 4856 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4857 ? 1 : 0; 4858 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4859 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4860 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4861 4862 /* FIXME: handle invalid trans */ 4863 itd->itd.itd_bufr[2] |= 4864 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4865 4866 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4867 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4868 4869 prev = itd; 4870 } /* End of frame */ 4871 4872 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4873 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4874 4875 /* 4876 * Part 2: Transfer descriptors have now been set up, now they must 4877 * be scheduled into the period frame list. Erk. Not wanting to 4878 * complicate matters, transfer is denied if the transfer spans 4879 * more than the period frame list. 4880 */ 4881 4882 mutex_enter(&sc->sc_lock); 4883 4884 /* Start inserting frames */ 4885 if (epipe->isoc.cur_xfers > 0) { 4886 frindex = epipe->isoc.next_frame; 4887 } else { 4888 frindex = EOREAD4(sc, EHCI_FRINDEX); 4889 frindex = frindex >> 3; /* Erase microframe index */ 4890 frindex += 2; 4891 } 4892 4893 if (frindex >= sc->sc_flsize) 4894 frindex &= (sc->sc_flsize - 1); 4895 4896 /* What's the frame interval? */ 4897 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4898 if (i / USB_UFRAMES_PER_FRAME == 0) 4899 i = 1; 4900 else 4901 i /= USB_UFRAMES_PER_FRAME; 4902 4903 itd = exfer->ex_itdstart; 4904 for (j = 0; j < frames; j++) { 4905 KASSERTMSG(itd != NULL, "frame %d\n", j); 4906 4907 usb_syncmem(&sc->sc_fldma, 4908 sizeof(ehci_link_t) * frindex, 4909 sizeof(ehci_link_t), 4910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4911 4912 itd->itd.itd_next = sc->sc_flist[frindex]; 4913 if (itd->itd.itd_next == 0) 4914 /* 4915 * FIXME: frindex table gets initialized to NULL 4916 * or EHCI_NULL? 4917 */ 4918 itd->itd.itd_next = EHCI_NULL; 4919 4920 usb_syncmem(&itd->dma, 4921 itd->offs + offsetof(ehci_itd_t, itd_next), 4922 sizeof(itd->itd.itd_next), 4923 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4924 4925 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4926 4927 usb_syncmem(&sc->sc_fldma, 4928 sizeof(ehci_link_t) * frindex, 4929 sizeof(ehci_link_t), 4930 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4931 4932 itd->frame_list.next = sc->sc_softitds[frindex]; 4933 sc->sc_softitds[frindex] = itd; 4934 if (itd->frame_list.next != NULL) 4935 itd->frame_list.next->frame_list.prev = itd; 4936 itd->slot = frindex; 4937 itd->frame_list.prev = NULL; 4938 4939 frindex += i; 4940 if (frindex >= sc->sc_flsize) 4941 frindex -= sc->sc_flsize; 4942 4943 itd = itd->xfer_next; 4944 } 4945 4946 epipe->isoc.cur_xfers++; 4947 epipe->isoc.next_frame = frindex; 4948 4949 ehci_add_intr_list(sc, exfer); 4950 xfer->ux_status = USBD_IN_PROGRESS; 4951 4952 mutex_exit(&sc->sc_lock); 4953 4954 if (sc->sc_bus.ub_usepolling) { 4955 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4956 ehci_waitintr(sc, xfer); 4957 } 4958 4959 return USBD_IN_PROGRESS; 4960 } 4961 4962 Static void 4963 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4964 { 4965 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4966 4967 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4968 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4969 } 4970 4971 Static void 4972 ehci_device_isoc_close(struct usbd_pipe *pipe) 4973 { 4974 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4975 4976 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4977 } 4978 4979 Static void 4980 ehci_device_isoc_done(struct usbd_xfer *xfer) 4981 { 4982 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4983 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4984 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4985 4986 KASSERT(mutex_owned(&sc->sc_lock)); 4987 4988 epipe->isoc.cur_xfers--; 4989 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4990 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4991 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4992 } 4993
Indexes created Wed Oct 01 19:09:53 GMT 2025