ehci.c revision 1.234.2.96
1 /* $NetBSD: ehci.c,v 1.234.2.96 2016/04/04 07:43:12 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.96 2016/04/04 07:43:12 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_timeout(void *); 171 Static void ehci_timeout_task(void *); 172 Static void ehci_intrlist_timeout(void *); 173 Static void ehci_doorbell(void *); 174 Static void ehci_pcd(void *); 175 176 Static struct usbd_xfer * 177 ehci_allocx(struct usbd_bus *, unsigned int); 178 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 179 180 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 181 Static int ehci_roothub_ctrl(struct usbd_bus *, 182 usb_device_request_t *, void *, int); 183 184 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 185 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 186 Static void ehci_root_intr_abort(struct usbd_xfer *); 187 Static void ehci_root_intr_close(struct usbd_pipe *); 188 Static void ehci_root_intr_done(struct usbd_xfer *); 189 190 Static int ehci_device_ctrl_init(struct usbd_xfer *); 191 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 193 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 194 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 195 Static void ehci_device_ctrl_close(struct usbd_pipe *); 196 Static void ehci_device_ctrl_done(struct usbd_xfer *); 197 198 Static int ehci_device_bulk_init(struct usbd_xfer *); 199 Static void ehci_device_bulk_fini(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 201 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 202 Static void ehci_device_bulk_abort(struct usbd_xfer *); 203 Static void ehci_device_bulk_close(struct usbd_pipe *); 204 Static void ehci_device_bulk_done(struct usbd_xfer *); 205 206 Static int ehci_device_intr_init(struct usbd_xfer *); 207 Static void ehci_device_intr_fini(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 209 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 210 Static void ehci_device_intr_abort(struct usbd_xfer *); 211 Static void ehci_device_intr_close(struct usbd_pipe *); 212 Static void ehci_device_intr_done(struct usbd_xfer *); 213 214 Static int ehci_device_isoc_init(struct usbd_xfer *); 215 Static void ehci_device_isoc_fini(struct usbd_xfer *); 216 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 217 Static void ehci_device_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_isoc_done(struct usbd_xfer *); 220 221 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 223 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 225 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 226 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 227 228 Static void ehci_device_clear_toggle(struct usbd_pipe *); 229 Static void ehci_noop(struct usbd_pipe *); 230 231 Static void ehci_disown(ehci_softc_t *, int, int); 232 233 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 234 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 235 236 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 237 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 238 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, 239 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 240 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 241 242 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 243 int, int, int *, ehci_soft_qtd_t **); 244 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 245 246 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 247 Static ehci_soft_sitd_t * 248 ehci_alloc_sitd(ehci_softc_t *); 249 250 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 251 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 252 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 253 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 254 255 static inline void 256 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 257 { 258 259 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 260 } 261 262 static inline void 263 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 264 { 265 266 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 267 } 268 269 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 270 271 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 272 int); 273 274 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 275 ehci_soft_qh_t *); 276 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 277 ehci_soft_qh_t *); 278 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 279 Static void ehci_sync_hc(ehci_softc_t *); 280 281 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 282 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 283 284 #ifdef EHCI_DEBUG 285 Static ehci_softc_t *theehci; 286 void ehci_dump(void); 287 #endif 288 289 #ifdef EHCI_DEBUG 290 Static void ehci_dump_regs(ehci_softc_t *); 291 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 292 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 293 Static void ehci_dump_qtd(ehci_qtd_t *); 294 Static void ehci_dump_sqh(ehci_soft_qh_t *); 295 Static void ehci_dump_sitd(struct ehci_soft_itd *); 296 Static void ehci_dump_itds(ehci_soft_itd_t *); 297 Static void ehci_dump_itd(struct ehci_soft_itd *); 298 Static void ehci_dump_exfer(struct ehci_xfer *); 299 #endif 300 301 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 302 303 static inline void 304 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 305 { 306 307 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 308 } 309 310 static inline void 311 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 312 { 313 314 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 315 } 316 317 Static const struct usbd_bus_methods ehci_bus_methods = { 318 .ubm_open = ehci_open, 319 .ubm_softint = ehci_softintr, 320 .ubm_dopoll = ehci_poll, 321 .ubm_allocx = ehci_allocx, 322 .ubm_freex = ehci_freex, 323 .ubm_getlock = ehci_get_lock, 324 .ubm_rhctrl = ehci_roothub_ctrl, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 328 .upm_transfer = ehci_root_intr_transfer, 329 .upm_start = ehci_root_intr_start, 330 .upm_abort = ehci_root_intr_abort, 331 .upm_close = ehci_root_intr_close, 332 .upm_cleartoggle = ehci_noop, 333 .upm_done = ehci_root_intr_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 337 .upm_init = ehci_device_ctrl_init, 338 .upm_fini = ehci_device_ctrl_fini, 339 .upm_transfer = ehci_device_ctrl_transfer, 340 .upm_start = ehci_device_ctrl_start, 341 .upm_abort = ehci_device_ctrl_abort, 342 .upm_close = ehci_device_ctrl_close, 343 .upm_cleartoggle = ehci_noop, 344 .upm_done = ehci_device_ctrl_done, 345 }; 346 347 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 348 .upm_init = ehci_device_intr_init, 349 .upm_fini = ehci_device_intr_fini, 350 .upm_transfer = ehci_device_intr_transfer, 351 .upm_start = ehci_device_intr_start, 352 .upm_abort = ehci_device_intr_abort, 353 .upm_close = ehci_device_intr_close, 354 .upm_cleartoggle = ehci_device_clear_toggle, 355 .upm_done = ehci_device_intr_done, 356 }; 357 358 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 359 .upm_init = ehci_device_bulk_init, 360 .upm_fini = ehci_device_bulk_fini, 361 .upm_transfer = ehci_device_bulk_transfer, 362 .upm_start = ehci_device_bulk_start, 363 .upm_abort = ehci_device_bulk_abort, 364 .upm_close = ehci_device_bulk_close, 365 .upm_cleartoggle = ehci_device_clear_toggle, 366 .upm_done = ehci_device_bulk_done, 367 }; 368 369 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 370 .upm_init = ehci_device_isoc_init, 371 .upm_fini = ehci_device_isoc_fini, 372 .upm_transfer = ehci_device_isoc_transfer, 373 .upm_abort = ehci_device_isoc_abort, 374 .upm_close = ehci_device_isoc_close, 375 .upm_cleartoggle = ehci_noop, 376 .upm_done = ehci_device_isoc_done, 377 }; 378 379 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 380 .upm_init = ehci_device_fs_isoc_init, 381 .upm_fini = ehci_device_fs_isoc_fini, 382 .upm_transfer = ehci_device_fs_isoc_transfer, 383 .upm_abort = ehci_device_fs_isoc_abort, 384 .upm_close = ehci_device_fs_isoc_close, 385 .upm_cleartoggle = ehci_noop, 386 .upm_done = ehci_device_fs_isoc_done, 387 }; 388 389 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 390 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 391 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 392 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 393 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 394 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 395 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 396 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 397 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 398 }; 399 400 int 401 ehci_init(ehci_softc_t *sc) 402 { 403 uint32_t vers, sparams, cparams, hcr; 404 u_int i; 405 usbd_status err; 406 ehci_soft_qh_t *sqh; 407 u_int ncomp; 408 409 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 410 #ifdef EHCI_DEBUG 411 theehci = sc; 412 #endif 413 414 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 415 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 416 cv_init(&sc->sc_softwake_cv, "ehciab"); 417 cv_init(&sc->sc_doorbell, "ehcidi"); 418 419 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 420 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 421 422 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 423 ehci_doorbell, sc); 424 KASSERT(sc->sc_doorbell_si != NULL); 425 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 426 ehci_pcd, sc); 427 KASSERT(sc->sc_pcd_si != NULL); 428 429 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 430 431 vers = EREAD2(sc, EHCI_HCIVERSION); 432 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 433 vers >> 8, vers & 0xff); 434 435 sparams = EREAD4(sc, EHCI_HCSPARAMS); 436 DPRINTF("sparams=%#x", sparams, 0, 0, 0); 437 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 438 ncomp = EHCI_HCS_N_CC(sparams); 439 if (ncomp != sc->sc_ncomp) { 440 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 441 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 442 #if NOHCI == 0 || NUHCI == 0 443 aprint_error("%s: ohci or uhci probably not configured\n", 444 device_xname(sc->sc_dev)); 445 #endif 446 if (ncomp < sc->sc_ncomp) 447 sc->sc_ncomp = ncomp; 448 } 449 if (sc->sc_ncomp > 0) { 450 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 451 aprint_normal("%s: companion controller%s, %d port%s each:", 452 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 453 EHCI_HCS_N_PCC(sparams), 454 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 455 for (i = 0; i < sc->sc_ncomp; i++) 456 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 457 aprint_normal("\n"); 458 } 459 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 460 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 461 462 cparams = EREAD4(sc, EHCI_HCCPARAMS); 463 DPRINTF("cparams=%#x", cparams, 0, 0, 0); 464 465 if (EHCI_HCC_64BIT(cparams)) { 466 /* MUST clear segment register if 64 bit capable. */ 467 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 468 } 469 470 if (cparams & EHCI_HCC_IST_FULLFRAME) { 471 sc->sc_istthreshold = 0; 472 } else { 473 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 474 } 475 476 sc->sc_bus.ub_revision = USBREV_2_0; 477 sc->sc_bus.ub_usedma = true; 478 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 479 480 /* Reset the controller */ 481 DPRINTF("resetting", 0, 0, 0, 0); 482 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 483 usb_delay_ms(&sc->sc_bus, 1); 484 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 485 for (i = 0; i < 100; i++) { 486 usb_delay_ms(&sc->sc_bus, 1); 487 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 488 if (!hcr) 489 break; 490 } 491 if (hcr) { 492 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 493 return EIO; 494 } 495 if (sc->sc_vendor_init) 496 sc->sc_vendor_init(sc); 497 498 /* XXX need proper intr scheduling */ 499 sc->sc_rand = 96; 500 501 /* frame list size at default, read back what we got and use that */ 502 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 503 case 0: sc->sc_flsize = 1024; break; 504 case 1: sc->sc_flsize = 512; break; 505 case 2: sc->sc_flsize = 256; break; 506 case 3: return EIO; 507 } 508 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 509 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 510 if (err) 511 return err; 512 DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); 513 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 514 515 for (i = 0; i < sc->sc_flsize; i++) { 516 sc->sc_flist[i] = EHCI_NULL; 517 } 518 519 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 520 521 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 522 KM_SLEEP); 523 if (sc->sc_softitds == NULL) 524 return ENOMEM; 525 LIST_INIT(&sc->sc_freeitds); 526 LIST_INIT(&sc->sc_freesitds); 527 TAILQ_INIT(&sc->sc_intrhead); 528 529 /* Set up the bus struct. */ 530 sc->sc_bus.ub_methods = &ehci_bus_methods; 531 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 532 533 sc->sc_eintrs = EHCI_NORMAL_INTRS; 534 535 /* 536 * Allocate the interrupt dummy QHs. These are arranged to give poll 537 * intervals that are powers of 2 times 1ms. 538 */ 539 for (i = 0; i < EHCI_INTRQHS; i++) { 540 sqh = ehci_alloc_sqh(sc); 541 if (sqh == NULL) { 542 err = ENOMEM; 543 goto bad1; 544 } 545 sc->sc_islots[i].sqh = sqh; 546 } 547 for (i = 0; i < EHCI_INTRQHS; i++) { 548 sqh = sc->sc_islots[i].sqh; 549 if (i == 0) { 550 /* The last (1ms) QH terminates. */ 551 sqh->qh.qh_link = EHCI_NULL; 552 sqh->next = NULL; 553 } else { 554 /* Otherwise the next QH has half the poll interval */ 555 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 556 sqh->qh.qh_link = htole32(sqh->next->physaddr | 557 EHCI_LINK_QH); 558 } 559 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 560 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 561 sqh->qh.qh_curqtd = EHCI_NULL; 562 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 563 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 564 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 565 sqh->sqtd = NULL; 566 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 567 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 568 } 569 /* Point the frame list at the last level (128ms). */ 570 for (i = 0; i < sc->sc_flsize; i++) { 571 int j; 572 573 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 574 revbits[i & (EHCI_MAX_POLLRATE-1)]; 575 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 576 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 577 i)].sqh->physaddr); 578 } 579 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 580 BUS_DMASYNC_PREWRITE); 581 582 /* Allocate dummy QH that starts the async list. */ 583 sqh = ehci_alloc_sqh(sc); 584 if (sqh == NULL) { 585 err = ENOMEM; 586 goto bad1; 587 } 588 /* Fill the QH */ 589 sqh->qh.qh_endp = 590 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 591 sqh->qh.qh_link = 592 htole32(sqh->physaddr | EHCI_LINK_QH); 593 sqh->qh.qh_curqtd = EHCI_NULL; 594 sqh->next = NULL; 595 /* Fill the overlay qTD */ 596 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 597 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 598 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 599 sqh->sqtd = NULL; 600 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 601 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 602 #ifdef EHCI_DEBUG 603 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 604 ehci_dump_sqh(sqh); 605 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 606 #endif 607 608 /* Point to async list */ 609 sc->sc_async_head = sqh; 610 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 611 612 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 613 614 /* Turn on controller */ 615 EOWRITE4(sc, EHCI_USBCMD, 616 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 617 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 618 EHCI_CMD_ASE | 619 EHCI_CMD_PSE | 620 EHCI_CMD_RS); 621 622 /* Take over port ownership */ 623 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 624 625 for (i = 0; i < 100; i++) { 626 usb_delay_ms(&sc->sc_bus, 1); 627 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 628 if (!hcr) 629 break; 630 } 631 if (hcr) { 632 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 633 return EIO; 634 } 635 636 /* Enable interrupts */ 637 DPRINTF("enabling interupts", 0, 0, 0, 0); 638 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 639 640 return 0; 641 642 #if 0 643 bad2: 644 ehci_free_sqh(sc, sc->sc_async_head); 645 #endif 646 bad1: 647 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 648 return err; 649 } 650 651 int 652 ehci_intr(void *v) 653 { 654 ehci_softc_t *sc = v; 655 int ret = 0; 656 657 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 658 659 if (sc == NULL) 660 return 0; 661 662 mutex_spin_enter(&sc->sc_intr_lock); 663 664 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 665 goto done; 666 667 /* If we get an interrupt while polling, then just ignore it. */ 668 if (sc->sc_bus.ub_usepolling) { 669 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 670 671 if (intrs) 672 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 673 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 674 goto done; 675 } 676 677 ret = ehci_intr1(sc); 678 679 done: 680 mutex_spin_exit(&sc->sc_intr_lock); 681 return ret; 682 } 683 684 Static int 685 ehci_intr1(ehci_softc_t *sc) 686 { 687 uint32_t intrs, eintrs; 688 689 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 690 691 /* In case the interrupt occurs before initialization has completed. */ 692 if (sc == NULL) { 693 #ifdef DIAGNOSTIC 694 printf("ehci_intr1: sc == NULL\n"); 695 #endif 696 return 0; 697 } 698 699 KASSERT(mutex_owned(&sc->sc_intr_lock)); 700 701 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 702 if (!intrs) 703 return 0; 704 705 eintrs = intrs & sc->sc_eintrs; 706 DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, 707 EOREAD4(sc, EHCI_USBSTS), eintrs); 708 if (!eintrs) 709 return 0; 710 711 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 712 if (eintrs & EHCI_STS_IAA) { 713 DPRINTF("door bell", 0, 0, 0, 0); 714 kpreempt_disable(); 715 KASSERT(sc->sc_doorbell_si != NULL); 716 softint_schedule(sc->sc_doorbell_si); 717 kpreempt_enable(); 718 eintrs &= ~EHCI_STS_IAA; 719 } 720 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 721 DPRINTF("INT=%d ERRINT=%d", 722 eintrs & EHCI_STS_INT ? 1 : 0, 723 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 724 usb_schedsoftintr(&sc->sc_bus); 725 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 726 } 727 if (eintrs & EHCI_STS_HSE) { 728 printf("%s: unrecoverable error, controller halted\n", 729 device_xname(sc->sc_dev)); 730 /* XXX what else */ 731 } 732 if (eintrs & EHCI_STS_PCD) { 733 kpreempt_disable(); 734 KASSERT(sc->sc_pcd_si != NULL); 735 softint_schedule(sc->sc_pcd_si); 736 kpreempt_enable(); 737 eintrs &= ~EHCI_STS_PCD; 738 } 739 740 if (eintrs != 0) { 741 /* Block unprocessed interrupts. */ 742 sc->sc_eintrs &= ~eintrs; 743 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 744 printf("%s: blocking intrs 0x%x\n", 745 device_xname(sc->sc_dev), eintrs); 746 } 747 748 return 1; 749 } 750 751 Static void 752 ehci_doorbell(void *addr) 753 { 754 ehci_softc_t *sc = addr; 755 756 mutex_enter(&sc->sc_lock); 757 cv_broadcast(&sc->sc_doorbell); 758 mutex_exit(&sc->sc_lock); 759 } 760 761 Static void 762 ehci_pcd(void *addr) 763 { 764 ehci_softc_t *sc = addr; 765 struct usbd_xfer *xfer; 766 u_char *p; 767 int i, m; 768 769 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 770 771 mutex_enter(&sc->sc_lock); 772 xfer = sc->sc_intrxfer; 773 774 if (xfer == NULL) { 775 /* Just ignore the change. */ 776 goto done; 777 } 778 779 p = xfer->ux_buf; 780 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 781 memset(p, 0, xfer->ux_length); 782 for (i = 1; i <= m; i++) { 783 /* Pick out CHANGE bits from the status reg. */ 784 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 785 p[i/8] |= 1 << (i%8); 786 if (i % 8 == 7) 787 DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); 788 } 789 xfer->ux_actlen = xfer->ux_length; 790 xfer->ux_status = USBD_NORMAL_COMPLETION; 791 792 usb_transfer_complete(xfer); 793 794 done: 795 mutex_exit(&sc->sc_lock); 796 } 797 798 Static void 799 ehci_softintr(void *v) 800 { 801 struct usbd_bus *bus = v; 802 ehci_softc_t *sc = EHCI_BUS2SC(bus); 803 struct ehci_xfer *ex, *nextex; 804 805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 806 807 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 808 809 ex_completeq_t cq; 810 TAILQ_INIT(&cq); 811 812 /* 813 * The only explanation I can think of for why EHCI is as brain dead 814 * as UHCI interrupt-wise is that Intel was involved in both. 815 * An interrupt just tells us that something is done, we have no 816 * clue what, so we need to scan through all active transfers. :-( 817 */ 818 819 /* 820 * ehci_idone will remove transfer from sc->sc_intrhead if it's 821 * complete and add to our cq list 822 * */ 823 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 824 switch (ex->ex_type) { 825 case EX_CTRL: 826 case EX_BULK: 827 case EX_INTR: 828 ehci_check_qh_intr(sc, ex, &cq); 829 break; 830 case EX_ISOC: 831 ehci_check_itd_intr(sc, ex, &cq); 832 break; 833 case EX_FS_ISOC: 834 ehci_check_sitd_intr(sc, ex, &cq); 835 break; 836 default: 837 KASSERT(false); 838 } 839 840 } 841 842 /* 843 * We abuse ex_next for the interrupt and complete lists and 844 * interrupt transfers will get re-added here so use 845 * the _SAFE version of TAILQ_FOREACH. 846 */ 847 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 848 usb_transfer_complete(&ex->ex_xfer); 849 } 850 851 /* Schedule a callout to catch any dropped transactions. */ 852 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 853 !TAILQ_EMPTY(&sc->sc_intrhead)) 854 callout_reset(&sc->sc_tmo_intrlist, 855 hz, ehci_intrlist_timeout, sc); 856 857 if (sc->sc_softwake) { 858 sc->sc_softwake = 0; 859 cv_broadcast(&sc->sc_softwake_cv); 860 } 861 } 862 863 Static void 864 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 865 { 866 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 867 uint32_t status; 868 869 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 870 871 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 872 873 if (ex->ex_type == EX_CTRL) { 874 fsqtd = ex->ex_setup; 875 lsqtd = ex->ex_status; 876 } else { 877 fsqtd = ex->ex_sqtdstart; 878 lsqtd = ex->ex_sqtdend; 879 } 880 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 881 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 882 883 /* 884 * If the last TD is still active we need to check whether there 885 * is an error somewhere in the middle, or whether there was a 886 * short packet (SPD and not ACTIVE). 887 */ 888 usb_syncmem(&lsqtd->dma, 889 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 890 sizeof(lsqtd->qtd.qtd_status), 891 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 892 status = le32toh(lsqtd->qtd.qtd_status); 893 usb_syncmem(&lsqtd->dma, 894 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 895 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 896 if (status & EHCI_QTD_ACTIVE) { 897 DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); 898 899 /* last qTD has already been checked */ 900 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 901 usb_syncmem(&sqtd->dma, 902 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 903 sizeof(sqtd->qtd.qtd_status), 904 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 905 status = le32toh(sqtd->qtd.qtd_status); 906 usb_syncmem(&sqtd->dma, 907 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 908 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 909 /* If there's an active QTD the xfer isn't done. */ 910 if (status & EHCI_QTD_ACTIVE) 911 break; 912 /* Any kind of error makes the xfer done. */ 913 if (status & EHCI_QTD_HALTED) 914 goto done; 915 /* Handle short packets */ 916 if (EHCI_QTD_GET_BYTES(status) != 0) { 917 /* 918 * If we get here for a control transfer then 919 * we need to let the hardware complete the 920 * status phase. That is, we're not done 921 * quite yet. 922 * 923 * Otherwise, we're done. 924 */ 925 if (ex->ex_type == EX_CTRL) { 926 break; 927 } 928 goto done; 929 } 930 } 931 DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, 932 0, 0); 933 #ifdef EHCI_DEBUG 934 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 935 ehci_dump_sqtds(ex->ex_sqtdstart); 936 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 937 #endif 938 return; 939 } 940 done: 941 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 942 callout_stop(&ex->ex_xfer.ux_callout); 943 ehci_idone(ex, cq); 944 } 945 946 Static void 947 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 948 { 949 ehci_soft_itd_t *itd; 950 int i; 951 952 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 953 954 KASSERT(mutex_owned(&sc->sc_lock)); 955 956 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 957 return; 958 959 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 960 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 961 962 itd = ex->ex_itdend; 963 964 /* 965 * check no active transfers in last itd, meaning we're finished 966 */ 967 968 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 969 sizeof(itd->itd.itd_ctl), 970 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 971 972 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 973 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 974 break; 975 } 976 977 if (i == EHCI_ITD_NUFRAMES) { 978 goto done; /* All 8 descriptors inactive, it's done */ 979 } 980 981 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 982 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 983 984 DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); 985 return; 986 done: 987 DPRINTF("ex %p done", ex, 0, 0, 0); 988 callout_stop(&ex->ex_xfer.ux_callout); 989 ehci_idone(ex, cq); 990 } 991 992 void 993 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 994 { 995 ehci_soft_sitd_t *sitd; 996 997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 998 999 KASSERT(mutex_owned(&sc->sc_lock)); 1000 1001 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1002 return; 1003 1004 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1005 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1006 1007 sitd = ex->ex_sitdend; 1008 1009 /* 1010 * check no active transfers in last sitd, meaning we're finished 1011 */ 1012 1013 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1014 sizeof(sitd->sitd.sitd_trans), 1015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1016 1017 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1021 1022 if (active) 1023 return; 1024 1025 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 1026 callout_stop(&(ex->ex_xfer.ux_callout)); 1027 ehci_idone(ex, cq); 1028 } 1029 1030 1031 Static void 1032 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1033 { 1034 struct usbd_xfer *xfer = &ex->ex_xfer; 1035 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1036 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1037 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1038 uint32_t status = 0, nstatus = 0; 1039 int actlen = 0; 1040 1041 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1042 1043 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1044 1045 DPRINTF("ex=%p", ex, 0, 0, 0); 1046 1047 if (xfer->ux_status == USBD_CANCELLED || 1048 xfer->ux_status == USBD_TIMEOUT) { 1049 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1050 return; 1051 } 1052 1053 #ifdef DIAGNOSTIC 1054 #ifdef EHCI_DEBUG 1055 if (ex->ex_isdone) { 1056 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1057 ehci_dump_exfer(ex); 1058 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1059 } 1060 #endif 1061 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1062 ex->ex_type, xfer->ux_status); 1063 ex->ex_isdone = true; 1064 #endif 1065 1066 DPRINTF("xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1067 1068 /* The transfer is done, compute actual length and status. */ 1069 if (ex->ex_type == EX_ISOC) { 1070 /* HS isoc transfer */ 1071 1072 struct ehci_soft_itd *itd; 1073 int i, nframes, len, uframes; 1074 1075 nframes = 0; 1076 1077 #ifdef EHCI_DEBUG 1078 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1079 ehci_dump_itds(ex->ex_itdstart); 1080 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1081 #endif 1082 1083 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1084 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1085 1086 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1087 usb_syncmem(&itd->dma, 1088 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1089 sizeof(itd->itd.itd_ctl), 1090 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1091 1092 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1093 /* 1094 * XXX - driver didn't fill in the frame full 1095 * of uframes. This leads to scheduling 1096 * inefficiencies, but working around 1097 * this doubles complexity of tracking 1098 * an xfer. 1099 */ 1100 if (nframes >= xfer->ux_nframes) 1101 break; 1102 1103 status = le32toh(itd->itd.itd_ctl[i]); 1104 len = EHCI_ITD_GET_LEN(status); 1105 if (EHCI_ITD_GET_STATUS(status) != 0) 1106 len = 0; /*No valid data on error*/ 1107 1108 xfer->ux_frlengths[nframes++] = len; 1109 actlen += len; 1110 } 1111 usb_syncmem(&itd->dma, 1112 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1113 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1114 1115 if (nframes >= xfer->ux_nframes) 1116 break; 1117 } 1118 1119 xfer->ux_actlen = actlen; 1120 xfer->ux_status = USBD_NORMAL_COMPLETION; 1121 goto end; 1122 } else if (ex->ex_type == EX_FS_ISOC) { 1123 /* FS isoc transfer */ 1124 struct ehci_soft_sitd *sitd; 1125 int nframes, len; 1126 1127 nframes = 0; 1128 1129 for (sitd = ex->ex_sitdstart; sitd != NULL; 1130 sitd = sitd->xfer_next) { 1131 usb_syncmem(&sitd->dma, 1132 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1133 sizeof(sitd->sitd.sitd_trans), 1134 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1135 1136 /* 1137 * XXX - driver didn't fill in the frame full 1138 * of uframes. This leads to scheduling 1139 * inefficiencies, but working around 1140 * this doubles complexity of tracking 1141 * an xfer. 1142 */ 1143 if (nframes >= xfer->ux_nframes) 1144 break; 1145 1146 status = le32toh(sitd->sitd.sitd_trans); 1147 usb_syncmem(&sitd->dma, 1148 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1149 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1150 1151 len = EHCI_SITD_GET_LEN(status); 1152 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1153 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1154 /* No valid data on error */ 1155 len = xfer->ux_frlengths[nframes]; 1156 } 1157 1158 /* 1159 * frlengths[i]: # of bytes to send 1160 * len: # of bytes host didn't send 1161 */ 1162 xfer->ux_frlengths[nframes] -= len; 1163 /* frlengths[i]: # of bytes host sent */ 1164 actlen += xfer->ux_frlengths[nframes++]; 1165 1166 if (nframes >= xfer->ux_nframes) 1167 break; 1168 } 1169 1170 xfer->ux_actlen = actlen; 1171 xfer->ux_status = USBD_NORMAL_COMPLETION; 1172 goto end; 1173 } 1174 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1175 ex->ex_type == EX_BULK); 1176 1177 /* Continue processing xfers using queue heads */ 1178 if (ex->ex_type == EX_CTRL) { 1179 fsqtd = ex->ex_setup; 1180 lsqtd = ex->ex_status; 1181 } else { 1182 fsqtd = ex->ex_sqtdstart; 1183 lsqtd = ex->ex_sqtdend; 1184 } 1185 #ifdef EHCI_DEBUG 1186 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1187 ehci_dump_sqtds(fsqtd); 1188 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1189 #endif 1190 1191 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1192 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1193 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1194 nstatus = le32toh(sqtd->qtd.qtd_status); 1195 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1196 BUS_DMASYNC_PREREAD); 1197 if (nstatus & EHCI_QTD_ACTIVE) 1198 break; 1199 1200 status = nstatus; 1201 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1202 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1203 } 1204 1205 /* 1206 * If there are left over TDs we need to update the toggle. 1207 * The default pipe doesn't need it since control transfers 1208 * start the toggle at 0 every time. 1209 * For a short transfer we need to update the toggle for the missing 1210 * packets within the qTD. 1211 */ 1212 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1213 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1214 DPRINTF("toggle update status=0x%08x nstatus=0x%08x", 1215 status, nstatus, 0, 0); 1216 #if 0 1217 ehci_dump_sqh(epipe->sqh); 1218 ehci_dump_sqtds(ex->ex_sqtdstart); 1219 #endif 1220 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1221 } 1222 1223 DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, 1224 status, 0); 1225 xfer->ux_actlen = actlen; 1226 if (status & EHCI_QTD_HALTED) { 1227 #ifdef EHCI_DEBUG 1228 DPRINTF("halted addr=%d endpt=0x%02x", 1229 xfer->ux_pipe->up_dev->ud_addr, 1230 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1231 0, 0); 1232 DPRINTF("cerr=%d pid=%d", 1233 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1234 0, 0); 1235 DPRINTF("active =%d halted=%d buferr=%d babble=%d", 1236 status & EHCI_QTD_ACTIVE ? 1 : 0, 1237 status & EHCI_QTD_HALTED ? 1 : 0, 1238 status & EHCI_QTD_BUFERR ? 1 : 0, 1239 status & EHCI_QTD_BABBLE ? 1 : 0); 1240 1241 DPRINTF("xacterr=%d missed=%d split =%d ping =%d", 1242 status & EHCI_QTD_XACTERR ? 1 : 0, 1243 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1244 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1245 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1246 1247 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1248 ehci_dump_sqh(epipe->sqh); 1249 ehci_dump_sqtds(ex->ex_sqtdstart); 1250 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1251 #endif 1252 /* low&full speed has an extra error flag */ 1253 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1254 EHCI_QH_SPEED_HIGH) 1255 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1256 else 1257 status &= EHCI_QTD_STATERRS; 1258 if (status == 0) /* no other errors means a stall */ { 1259 xfer->ux_status = USBD_STALLED; 1260 } else { 1261 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1262 } 1263 /* XXX need to reset TT on missed microframe */ 1264 if (status & EHCI_QTD_MISSEDMICRO) { 1265 printf("%s: missed microframe, TT reset not " 1266 "implemented, hub might be inoperational\n", 1267 device_xname(sc->sc_dev)); 1268 } 1269 } else { 1270 xfer->ux_status = USBD_NORMAL_COMPLETION; 1271 } 1272 1273 end: 1274 1275 ehci_del_intr_list(sc, ex); 1276 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1277 1278 DPRINTF("ex=%p done", ex, 0, 0, 0); 1279 } 1280 1281 /* 1282 * Wait here until controller claims to have an interrupt. 1283 * Then call ehci_intr and return. Use timeout to avoid waiting 1284 * too long. 1285 */ 1286 Static void 1287 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1288 { 1289 int timo; 1290 uint32_t intrs; 1291 1292 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1293 1294 xfer->ux_status = USBD_IN_PROGRESS; 1295 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1296 usb_delay_ms(&sc->sc_bus, 1); 1297 if (sc->sc_dying) 1298 break; 1299 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1300 sc->sc_eintrs; 1301 DPRINTF("0x%04x", intrs, 0, 0, 0); 1302 #ifdef EHCI_DEBUG 1303 if (ehcidebug >= 15) 1304 ehci_dump_regs(sc); 1305 #endif 1306 if (intrs) { 1307 mutex_spin_enter(&sc->sc_intr_lock); 1308 ehci_intr1(sc); 1309 mutex_spin_exit(&sc->sc_intr_lock); 1310 if (xfer->ux_status != USBD_IN_PROGRESS) 1311 return; 1312 } 1313 } 1314 1315 /* Timeout */ 1316 DPRINTF("timeout", 0, 0, 0, 0); 1317 xfer->ux_status = USBD_TIMEOUT; 1318 mutex_enter(&sc->sc_lock); 1319 usb_transfer_complete(xfer); 1320 mutex_exit(&sc->sc_lock); 1321 } 1322 1323 Static void 1324 ehci_poll(struct usbd_bus *bus) 1325 { 1326 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1327 1328 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1329 1330 #ifdef EHCI_DEBUG 1331 static int last; 1332 int new; 1333 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1334 if (new != last) { 1335 DPRINTF("intrs=0x%04x", new, 0, 0, 0); 1336 last = new; 1337 } 1338 #endif 1339 1340 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1341 mutex_spin_enter(&sc->sc_intr_lock); 1342 ehci_intr1(sc); 1343 mutex_spin_exit(&sc->sc_intr_lock); 1344 } 1345 } 1346 1347 void 1348 ehci_childdet(device_t self, device_t child) 1349 { 1350 struct ehci_softc *sc = device_private(self); 1351 1352 KASSERT(sc->sc_child == child); 1353 sc->sc_child = NULL; 1354 } 1355 1356 int 1357 ehci_detach(struct ehci_softc *sc, int flags) 1358 { 1359 int rv = 0; 1360 1361 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1362 1363 if (sc->sc_child != NULL) 1364 rv = config_detach(sc->sc_child, flags); 1365 1366 if (rv != 0) 1367 return rv; 1368 1369 callout_halt(&sc->sc_tmo_intrlist, NULL); 1370 callout_destroy(&sc->sc_tmo_intrlist); 1371 1372 /* XXX free other data structures XXX */ 1373 if (sc->sc_softitds) 1374 kmem_free(sc->sc_softitds, 1375 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1376 cv_destroy(&sc->sc_doorbell); 1377 cv_destroy(&sc->sc_softwake_cv); 1378 1379 #if 0 1380 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1381 1382 softint_disestablish(sc->sc_doorbell_si); 1383 softint_disestablish(sc->sc_pcd_si); 1384 1385 mutex_destroy(&sc->sc_lock); 1386 mutex_destroy(&sc->sc_intr_lock); 1387 #endif 1388 1389 pool_cache_destroy(sc->sc_xferpool); 1390 1391 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1392 1393 return rv; 1394 } 1395 1396 1397 int 1398 ehci_activate(device_t self, enum devact act) 1399 { 1400 struct ehci_softc *sc = device_private(self); 1401 1402 switch (act) { 1403 case DVACT_DEACTIVATE: 1404 sc->sc_dying = 1; 1405 return 0; 1406 default: 1407 return EOPNOTSUPP; 1408 } 1409 } 1410 1411 /* 1412 * Handle suspend/resume. 1413 * 1414 * We need to switch to polling mode here, because this routine is 1415 * called from an interrupt context. This is all right since we 1416 * are almost suspended anyway. 1417 * 1418 * Note that this power handler isn't to be registered directly; the 1419 * bus glue needs to call out to it. 1420 */ 1421 bool 1422 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1423 { 1424 ehci_softc_t *sc = device_private(dv); 1425 int i; 1426 uint32_t cmd, hcr; 1427 1428 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1429 1430 mutex_spin_enter(&sc->sc_intr_lock); 1431 sc->sc_bus.ub_usepolling++; 1432 mutex_spin_exit(&sc->sc_intr_lock); 1433 1434 for (i = 1; i <= sc->sc_noport; i++) { 1435 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1436 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1437 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1438 } 1439 1440 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1441 1442 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1443 EOWRITE4(sc, EHCI_USBCMD, cmd); 1444 1445 for (i = 0; i < 100; i++) { 1446 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1447 if (hcr == 0) 1448 break; 1449 1450 usb_delay_ms(&sc->sc_bus, 1); 1451 } 1452 if (hcr != 0) 1453 printf("%s: reset timeout\n", device_xname(dv)); 1454 1455 cmd &= ~EHCI_CMD_RS; 1456 EOWRITE4(sc, EHCI_USBCMD, cmd); 1457 1458 for (i = 0; i < 100; i++) { 1459 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1460 if (hcr == EHCI_STS_HCH) 1461 break; 1462 1463 usb_delay_ms(&sc->sc_bus, 1); 1464 } 1465 if (hcr != EHCI_STS_HCH) 1466 printf("%s: config timeout\n", device_xname(dv)); 1467 1468 mutex_spin_enter(&sc->sc_intr_lock); 1469 sc->sc_bus.ub_usepolling--; 1470 mutex_spin_exit(&sc->sc_intr_lock); 1471 1472 return true; 1473 } 1474 1475 bool 1476 ehci_resume(device_t dv, const pmf_qual_t *qual) 1477 { 1478 ehci_softc_t *sc = device_private(dv); 1479 int i; 1480 uint32_t cmd, hcr; 1481 1482 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1483 1484 /* restore things in case the bios sucks */ 1485 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1486 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1487 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1488 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1489 1490 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1491 1492 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1493 1494 hcr = 0; 1495 for (i = 1; i <= sc->sc_noport; i++) { 1496 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1497 if ((cmd & EHCI_PS_PO) == 0 && 1498 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1499 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1500 hcr = 1; 1501 } 1502 } 1503 1504 if (hcr) { 1505 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1506 1507 for (i = 1; i <= sc->sc_noport; i++) { 1508 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1509 if ((cmd & EHCI_PS_PO) == 0 && 1510 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1511 EOWRITE4(sc, EHCI_PORTSC(i), 1512 cmd & ~EHCI_PS_FPR); 1513 } 1514 } 1515 1516 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1517 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1518 1519 for (i = 0; i < 100; i++) { 1520 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1521 if (hcr != EHCI_STS_HCH) 1522 break; 1523 1524 usb_delay_ms(&sc->sc_bus, 1); 1525 } 1526 if (hcr == EHCI_STS_HCH) 1527 printf("%s: config timeout\n", device_xname(dv)); 1528 1529 return true; 1530 } 1531 1532 /* 1533 * Shut down the controller when the system is going down. 1534 */ 1535 bool 1536 ehci_shutdown(device_t self, int flags) 1537 { 1538 ehci_softc_t *sc = device_private(self); 1539 1540 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1541 1542 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1543 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1544 return true; 1545 } 1546 1547 Static struct usbd_xfer * 1548 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1549 { 1550 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1551 struct usbd_xfer *xfer; 1552 1553 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1554 if (xfer != NULL) { 1555 memset(xfer, 0, sizeof(struct ehci_xfer)); 1556 #ifdef DIAGNOSTIC 1557 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1558 ex->ex_isdone = true; 1559 xfer->ux_state = XFER_BUSY; 1560 #endif 1561 } 1562 return xfer; 1563 } 1564 1565 Static void 1566 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1567 { 1568 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1569 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1570 1571 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1572 xfer->ux_state); 1573 KASSERT(ex->ex_isdone); 1574 1575 #ifdef DIAGNOSTIC 1576 xfer->ux_state = XFER_FREE; 1577 #endif 1578 1579 pool_cache_put(sc->sc_xferpool, xfer); 1580 } 1581 1582 Static void 1583 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1584 { 1585 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1586 1587 *lock = &sc->sc_lock; 1588 } 1589 1590 Static void 1591 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1592 { 1593 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1594 1595 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1596 1597 DPRINTF("epipe=%p status=0x%08x", epipe, 1598 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1599 #ifdef EHCI_DEBUG 1600 if (ehcidebug) 1601 usbd_dump_pipe(pipe); 1602 #endif 1603 epipe->nexttoggle = 0; 1604 } 1605 1606 Static void 1607 ehci_noop(struct usbd_pipe *pipe) 1608 { 1609 } 1610 1611 #ifdef EHCI_DEBUG 1612 /* 1613 * Unused function - this is meant to be called from a kernel 1614 * debugger. 1615 */ 1616 void 1617 ehci_dump(void) 1618 { 1619 ehci_softc_t *sc = theehci; 1620 int i; 1621 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1622 EOREAD4(sc, EHCI_USBCMD), 1623 EOREAD4(sc, EHCI_USBSTS), 1624 EOREAD4(sc, EHCI_USBINTR)); 1625 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1626 EOREAD4(sc, EHCI_FRINDEX), 1627 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1628 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1629 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1630 for (i = 1; i <= sc->sc_noport; i++) 1631 printf("port %d status=0x%08x\n", i, 1632 EOREAD4(sc, EHCI_PORTSC(i))); 1633 } 1634 1635 Static void 1636 ehci_dump_regs(ehci_softc_t *sc) 1637 { 1638 int i; 1639 1640 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1641 1642 DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1643 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1644 EOREAD4(sc, EHCI_USBINTR), 0); 1645 DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1646 "async = 0x%08x", 1647 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1648 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1649 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1650 for (i = 1; i <= sc->sc_noport; i += 2) { 1651 if (i == sc->sc_noport) { 1652 DPRINTF("port %d status = 0x%08x", i, 1653 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1654 } else { 1655 DPRINTF( 1656 "port %d status = 0x%08x port %d status = 0x%08x", 1657 i, EOREAD4(sc, EHCI_PORTSC(i)), 1658 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1659 } 1660 } 1661 } 1662 1663 #define ehci_dump_link(link, type) do { \ 1664 DPRINTF(" link 0x%08x (T = %d):", \ 1665 link, \ 1666 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1667 if (type) { \ 1668 DPRINTF( \ 1669 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1670 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1671 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1672 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1673 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1674 } \ 1675 } while(0) 1676 1677 Static void 1678 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1679 { 1680 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1681 int i; 1682 uint32_t stop = 0; 1683 1684 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1685 ehci_dump_sqtd(sqtd); 1686 usb_syncmem(&sqtd->dma, 1687 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1688 sizeof(sqtd->qtd), 1689 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1690 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1691 usb_syncmem(&sqtd->dma, 1692 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1693 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1694 } 1695 if (!stop) 1696 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1697 } 1698 1699 Static void 1700 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1701 { 1702 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1703 1704 usb_syncmem(&sqtd->dma, sqtd->offs, 1705 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1706 1707 DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1708 ehci_dump_qtd(&sqtd->qtd); 1709 1710 usb_syncmem(&sqtd->dma, sqtd->offs, 1711 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1712 } 1713 1714 Static void 1715 ehci_dump_qtd(ehci_qtd_t *qtd) 1716 { 1717 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1718 uint32_t s = le32toh(qtd->qtd_status); 1719 1720 DPRINTFN(10, 1721 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1722 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1723 DPRINTFN(10, 1724 " toggle = %d ioc = %d bytes = %#x " 1725 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1726 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1727 DPRINTFN(10, 1728 " cerr = %d pid = %d stat = %x", 1729 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1730 0); 1731 DPRINTFN(10, 1732 "active =%d halted=%d buferr=%d babble=%d", 1733 s & EHCI_QTD_ACTIVE ? 1 : 0, 1734 s & EHCI_QTD_HALTED ? 1 : 0, 1735 s & EHCI_QTD_BUFERR ? 1 : 0, 1736 s & EHCI_QTD_BABBLE ? 1 : 0); 1737 DPRINTFN(10, 1738 "xacterr=%d missed=%d split =%d ping =%d", 1739 s & EHCI_QTD_XACTERR ? 1 : 0, 1740 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1741 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1742 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1743 DPRINTFN(10, 1744 "buffer[0] = %#x buffer[1] = %#x " 1745 "buffer[2] = %#x buffer[3] = %#x", 1746 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1747 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1748 DPRINTFN(10, 1749 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1750 } 1751 1752 Static void 1753 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1754 { 1755 ehci_qh_t *qh = &sqh->qh; 1756 ehci_link_t link; 1757 uint32_t endp, endphub; 1758 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1759 1760 usb_syncmem(&sqh->dma, sqh->offs, 1761 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1762 1763 DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1764 link = le32toh(qh->qh_link); 1765 ehci_dump_link(link, true); 1766 1767 endp = le32toh(qh->qh_endp); 1768 DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); 1769 DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", 1770 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1771 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1772 DPRINTFN(10, " dtc = %d hrecl = %d", 1773 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1774 DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", 1775 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1776 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1777 1778 endphub = le32toh(qh->qh_endphub); 1779 DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); 1780 DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", 1781 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1782 DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", 1783 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1784 EHCI_QH_GET_MULT(endphub), 0); 1785 1786 link = le32toh(qh->qh_curqtd); 1787 ehci_dump_link(link, false); 1788 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1789 ehci_dump_qtd(&qh->qh_qtd); 1790 1791 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1792 BUS_DMASYNC_PREREAD); 1793 } 1794 1795 Static void 1796 ehci_dump_itds(ehci_soft_itd_t *itd) 1797 { 1798 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1799 int i; 1800 uint32_t stop = 0; 1801 1802 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1803 ehci_dump_itd(itd); 1804 usb_syncmem(&itd->dma, 1805 itd->offs + offsetof(ehci_itd_t, itd_next), 1806 sizeof(itd->itd), 1807 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1808 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1809 usb_syncmem(&itd->dma, 1810 itd->offs + offsetof(ehci_itd_t, itd_next), 1811 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1812 } 1813 if (!stop) 1814 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1815 } 1816 1817 Static void 1818 ehci_dump_itd(struct ehci_soft_itd *itd) 1819 { 1820 ehci_isoc_trans_t t; 1821 ehci_isoc_bufr_ptr_t b, b2, b3; 1822 int i; 1823 1824 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1825 1826 DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); 1827 1828 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1829 t = le32toh(itd->itd.itd_ctl[i]); 1830 DPRINTF("ITDctl %d: stat = %x len = %x", 1831 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1832 DPRINTF(" ioc = %x pg = %x offs = %x", 1833 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1834 EHCI_ITD_GET_OFFS(t), 0); 1835 } 1836 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1837 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1838 DPRINTF(" %x", 1839 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1840 1841 b = le32toh(itd->itd.itd_bufr[0]); 1842 b2 = le32toh(itd->itd.itd_bufr[1]); 1843 b3 = le32toh(itd->itd.itd_bufr[2]); 1844 DPRINTF(" ep = %x daddr = %x dir = %d", 1845 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1846 DPRINTF(" maxpkt = %x multi = %x", 1847 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1848 } 1849 1850 Static void 1851 ehci_dump_sitd(struct ehci_soft_itd *itd) 1852 { 1853 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1854 1855 DPRINTF("SITD %p next = %p prev = %p", 1856 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1857 DPRINTF(" xfernext=%p physaddr=%X slot=%d", 1858 itd->xfer_next, itd->physaddr, itd->slot, 0); 1859 } 1860 1861 Static void 1862 ehci_dump_exfer(struct ehci_xfer *ex) 1863 { 1864 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1865 1866 DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, 1867 ex->ex_isdone, 0); 1868 1869 switch (ex->ex_type) { 1870 case EX_CTRL: 1871 DPRINTF(" setup = %p data = %p status = %p", 1872 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1873 break; 1874 case EX_BULK: 1875 case EX_INTR: 1876 DPRINTF(" qtdstart = %p qtdend = %p", 1877 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1878 break; 1879 case EX_ISOC: 1880 DPRINTF(" itdstart = %p itdend = %p", 1881 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1882 break; 1883 case EX_FS_ISOC: 1884 DPRINTF(" sitdstart = %p sitdend = %p", 1885 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1886 break; 1887 default: 1888 DPRINTF(" unknown type", 0, 0, 0, 0); 1889 } 1890 } 1891 #endif 1892 1893 Static usbd_status 1894 ehci_open(struct usbd_pipe *pipe) 1895 { 1896 struct usbd_device *dev = pipe->up_dev; 1897 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1898 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1899 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1900 uint8_t addr = dev->ud_addr; 1901 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1902 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1903 ehci_soft_qh_t *sqh; 1904 usbd_status err; 1905 int ival, speed, naks; 1906 int hshubaddr, hshubport; 1907 1908 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1909 1910 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1911 ed->bEndpointAddress, rhaddr); 1912 1913 if (dev->ud_myhsport) { 1914 /* 1915 * When directly attached FS/LS device while doing embedded 1916 * transaction translations and we are the hub, set the hub 1917 * address to 0 (us). 1918 */ 1919 if (!(sc->sc_flags & EHCIF_ETTF) 1920 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1921 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1922 } else { 1923 hshubaddr = 0; 1924 } 1925 hshubport = dev->ud_myhsport->up_portno; 1926 } else { 1927 hshubaddr = 0; 1928 hshubport = 0; 1929 } 1930 1931 if (sc->sc_dying) 1932 return USBD_IOERROR; 1933 1934 /* toggle state needed for bulk endpoints */ 1935 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1936 1937 if (addr == rhaddr) { 1938 switch (ed->bEndpointAddress) { 1939 case USB_CONTROL_ENDPOINT: 1940 pipe->up_methods = &roothub_ctrl_methods; 1941 break; 1942 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1943 pipe->up_methods = &ehci_root_intr_methods; 1944 break; 1945 default: 1946 DPRINTF("bad bEndpointAddress 0x%02x", 1947 ed->bEndpointAddress, 0, 0, 0); 1948 return USBD_INVAL; 1949 } 1950 return USBD_NORMAL_COMPLETION; 1951 } 1952 1953 /* XXX All this stuff is only valid for async. */ 1954 switch (dev->ud_speed) { 1955 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1956 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1957 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1958 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1959 } 1960 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1961 DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, 1962 0); 1963 return USBD_INVAL; 1964 } 1965 1966 /* 1967 * For interrupt transfer, nak throttling must be disabled, but for 1968 * the other transfer type, nak throttling should be enabled from the 1969 * viewpoint that avoids the memory thrashing. 1970 */ 1971 naks = (xfertype == UE_INTERRUPT) ? 0 1972 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1973 1974 /* Allocate sqh for everything, save isoc xfers */ 1975 if (xfertype != UE_ISOCHRONOUS) { 1976 sqh = ehci_alloc_sqh(sc); 1977 if (sqh == NULL) 1978 return USBD_NOMEM; 1979 /* qh_link filled when the QH is added */ 1980 sqh->qh.qh_endp = htole32( 1981 EHCI_QH_SET_ADDR(addr) | 1982 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1983 EHCI_QH_SET_EPS(speed) | 1984 EHCI_QH_DTC | 1985 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1986 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1987 EHCI_QH_CTL : 0) | 1988 EHCI_QH_SET_NRL(naks) 1989 ); 1990 sqh->qh.qh_endphub = htole32( 1991 EHCI_QH_SET_MULT(1) | 1992 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1993 ); 1994 if (speed != EHCI_QH_SPEED_HIGH) 1995 sqh->qh.qh_endphub |= htole32( 1996 EHCI_QH_SET_PORT(hshubport) | 1997 EHCI_QH_SET_HUBA(hshubaddr) | 1998 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1999 ); 2000 sqh->qh.qh_curqtd = EHCI_NULL; 2001 /* Fill the overlay qTD */ 2002 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2003 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2004 sqh->qh.qh_qtd.qtd_status = htole32(0); 2005 2006 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2007 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2008 epipe->sqh = sqh; 2009 } else { 2010 sqh = NULL; 2011 } /*xfertype == UE_ISOC*/ 2012 2013 switch (xfertype) { 2014 case UE_CONTROL: 2015 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2016 0, &epipe->ctrl.reqdma); 2017 #ifdef EHCI_DEBUG 2018 if (err) 2019 printf("ehci_open: usb_allocmem()=%d\n", err); 2020 #endif 2021 if (err) 2022 goto bad; 2023 pipe->up_methods = &ehci_device_ctrl_methods; 2024 mutex_enter(&sc->sc_lock); 2025 ehci_add_qh(sc, sqh, sc->sc_async_head); 2026 mutex_exit(&sc->sc_lock); 2027 break; 2028 case UE_BULK: 2029 pipe->up_methods = &ehci_device_bulk_methods; 2030 mutex_enter(&sc->sc_lock); 2031 ehci_add_qh(sc, sqh, sc->sc_async_head); 2032 mutex_exit(&sc->sc_lock); 2033 break; 2034 case UE_INTERRUPT: 2035 pipe->up_methods = &ehci_device_intr_methods; 2036 ival = pipe->up_interval; 2037 if (ival == USBD_DEFAULT_INTERVAL) { 2038 if (speed == EHCI_QH_SPEED_HIGH) { 2039 if (ed->bInterval > 16) { 2040 /* 2041 * illegal with high-speed, but there 2042 * were documentation bugs in the spec, 2043 * so be generous 2044 */ 2045 ival = 256; 2046 } else 2047 ival = (1 << (ed->bInterval - 1)) / 8; 2048 } else 2049 ival = ed->bInterval; 2050 } 2051 err = ehci_device_setintr(sc, sqh, ival); 2052 if (err) 2053 goto bad; 2054 break; 2055 case UE_ISOCHRONOUS: 2056 pipe->up_serialise = false; 2057 if (speed == EHCI_QH_SPEED_HIGH) 2058 pipe->up_methods = &ehci_device_isoc_methods; 2059 else 2060 pipe->up_methods = &ehci_device_fs_isoc_methods; 2061 if (ed->bInterval == 0 || ed->bInterval > 16) { 2062 printf("ehci: opening pipe with invalid bInterval\n"); 2063 err = USBD_INVAL; 2064 goto bad; 2065 } 2066 if (UGETW(ed->wMaxPacketSize) == 0) { 2067 printf("ehci: zero length endpoint open request\n"); 2068 err = USBD_INVAL; 2069 goto bad; 2070 } 2071 epipe->isoc.next_frame = 0; 2072 epipe->isoc.cur_xfers = 0; 2073 break; 2074 default: 2075 DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); 2076 err = USBD_INVAL; 2077 goto bad; 2078 } 2079 return USBD_NORMAL_COMPLETION; 2080 2081 bad: 2082 if (sqh != NULL) { 2083 mutex_enter(&sc->sc_lock); 2084 ehci_free_sqh(sc, sqh); 2085 mutex_exit(&sc->sc_lock); 2086 } 2087 return err; 2088 } 2089 2090 /* 2091 * Add an ED to the schedule. Called with USB lock held. 2092 */ 2093 Static void 2094 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2095 { 2096 2097 KASSERT(mutex_owned(&sc->sc_lock)); 2098 2099 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2100 2101 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2102 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2103 2104 sqh->next = head->next; 2105 sqh->qh.qh_link = head->qh.qh_link; 2106 2107 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2108 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2109 2110 head->next = sqh; 2111 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2112 2113 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2114 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2115 2116 #ifdef EHCI_DEBUG 2117 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2118 ehci_dump_sqh(sqh); 2119 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2120 #endif 2121 } 2122 2123 /* 2124 * Remove an ED from the schedule. Called with USB lock held. 2125 */ 2126 Static void 2127 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2128 { 2129 ehci_soft_qh_t *p; 2130 2131 KASSERT(mutex_owned(&sc->sc_lock)); 2132 2133 /* XXX */ 2134 for (p = head; p != NULL && p->next != sqh; p = p->next) 2135 ; 2136 if (p == NULL) 2137 panic("ehci_rem_qh: ED not found"); 2138 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2139 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2140 p->next = sqh->next; 2141 p->qh.qh_link = sqh->qh.qh_link; 2142 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2143 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2144 2145 ehci_sync_hc(sc); 2146 } 2147 2148 Static void 2149 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2150 { 2151 int i; 2152 uint32_t status; 2153 2154 /* Save toggle bit and ping status. */ 2155 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2156 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2157 status = sqh->qh.qh_qtd.qtd_status & 2158 htole32(EHCI_QTD_TOGGLE_MASK | 2159 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2160 /* Set HALTED to make hw leave it alone. */ 2161 sqh->qh.qh_qtd.qtd_status = 2162 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2163 usb_syncmem(&sqh->dma, 2164 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2165 sizeof(sqh->qh.qh_qtd.qtd_status), 2166 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2167 sqh->qh.qh_curqtd = 0; 2168 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2169 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2170 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2171 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2172 sqh->sqtd = sqtd; 2173 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2175 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2176 sqh->qh.qh_qtd.qtd_status = status; 2177 usb_syncmem(&sqh->dma, 2178 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2179 sizeof(sqh->qh.qh_qtd.qtd_status), 2180 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2181 } 2182 2183 /* 2184 * Ensure that the HC has released all references to the QH. We do this 2185 * by asking for a Async Advance Doorbell interrupt and then we wait for 2186 * the interrupt. 2187 * To make this easier we first obtain exclusive use of the doorbell. 2188 */ 2189 Static void 2190 ehci_sync_hc(ehci_softc_t *sc) 2191 { 2192 int error __diagused; 2193 2194 KASSERT(mutex_owned(&sc->sc_lock)); 2195 2196 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2197 2198 if (sc->sc_dying) { 2199 DPRINTF("dying", 0, 0, 0, 0); 2200 return; 2201 } 2202 /* ask for doorbell */ 2203 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2204 DPRINTF("cmd = 0x%08x sts = 0x%08x", 2205 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2206 2207 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2208 2209 DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", 2210 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2211 #ifdef DIAGNOSTIC 2212 if (error) 2213 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2214 #endif 2215 } 2216 2217 Static void 2218 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2219 { 2220 2221 KASSERT(mutex_owned(&sc->sc_lock)); 2222 2223 for (; itd != NULL; itd = itd->xfer_next) { 2224 struct ehci_soft_itd *prev = itd->frame_list.prev; 2225 2226 /* Unlink itd from hardware chain, or frame array */ 2227 if (prev == NULL) { /* We're at the table head */ 2228 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2229 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2230 usb_syncmem(&sc->sc_fldma, 2231 sizeof(ehci_link_t) * itd->slot, 2232 sizeof(ehci_link_t), 2233 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2234 2235 if (itd->frame_list.next != NULL) 2236 itd->frame_list.next->frame_list.prev = NULL; 2237 } else { 2238 /* XXX this part is untested... */ 2239 prev->itd.itd_next = itd->itd.itd_next; 2240 usb_syncmem(&itd->dma, 2241 itd->offs + offsetof(ehci_itd_t, itd_next), 2242 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2243 2244 prev->frame_list.next = itd->frame_list.next; 2245 if (itd->frame_list.next != NULL) 2246 itd->frame_list.next->frame_list.prev = prev; 2247 } 2248 } 2249 } 2250 2251 Static void 2252 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2253 { 2254 struct ehci_soft_itd *next; 2255 2256 mutex_enter(&sc->sc_lock); 2257 next = NULL; 2258 for (; itd != NULL; itd = next) { 2259 next = itd->xfer_next; 2260 ehci_free_itd_locked(sc, itd); 2261 } 2262 mutex_exit(&sc->sc_lock); 2263 } 2264 2265 Static void 2266 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2267 { 2268 2269 KASSERT(mutex_owned(&sc->sc_lock)); 2270 2271 for (; sitd != NULL; sitd = sitd->xfer_next) { 2272 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2273 2274 /* Unlink sitd from hardware chain, or frame array */ 2275 if (prev == NULL) { /* We're at the table head */ 2276 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2277 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2278 usb_syncmem(&sc->sc_fldma, 2279 sizeof(ehci_link_t) * sitd->slot, 2280 sizeof(ehci_link_t), 2281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2282 2283 if (sitd->frame_list.next != NULL) 2284 sitd->frame_list.next->frame_list.prev = NULL; 2285 } else { 2286 /* XXX this part is untested... */ 2287 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2288 usb_syncmem(&sitd->dma, 2289 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2290 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2291 2292 prev->frame_list.next = sitd->frame_list.next; 2293 if (sitd->frame_list.next != NULL) 2294 sitd->frame_list.next->frame_list.prev = prev; 2295 } 2296 } 2297 } 2298 2299 Static void 2300 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2301 { 2302 2303 mutex_enter(&sc->sc_lock); 2304 struct ehci_soft_sitd *next = NULL; 2305 for (; sitd != NULL; sitd = next) { 2306 next = sitd->xfer_next; 2307 ehci_free_sitd_locked(sc, sitd); 2308 } 2309 mutex_exit(&sc->sc_lock); 2310 } 2311 2312 /***********/ 2313 2314 Static int 2315 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2316 void *buf, int buflen) 2317 { 2318 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2319 usb_hub_descriptor_t hubd; 2320 usb_port_status_t ps; 2321 uint16_t len, value, index; 2322 int l, totlen = 0; 2323 int port, i; 2324 uint32_t v; 2325 2326 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2327 2328 if (sc->sc_dying) 2329 return -1; 2330 2331 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, 2332 0, 0); 2333 2334 len = UGETW(req->wLength); 2335 value = UGETW(req->wValue); 2336 index = UGETW(req->wIndex); 2337 2338 #define C(x,y) ((x) | ((y) << 8)) 2339 switch (C(req->bRequest, req->bmRequestType)) { 2340 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2341 if (len == 0) 2342 break; 2343 switch (value) { 2344 case C(0, UDESC_DEVICE): { 2345 usb_device_descriptor_t devd; 2346 totlen = min(buflen, sizeof(devd)); 2347 memcpy(&devd, buf, totlen); 2348 USETW(devd.idVendor, sc->sc_id_vendor); 2349 memcpy(buf, &devd, totlen); 2350 break; 2351 2352 } 2353 #define sd ((usb_string_descriptor_t *)buf) 2354 case C(1, UDESC_STRING): 2355 /* Vendor */ 2356 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2357 break; 2358 case C(2, UDESC_STRING): 2359 /* Product */ 2360 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2361 break; 2362 #undef sd 2363 default: 2364 /* default from usbroothub */ 2365 return buflen; 2366 } 2367 break; 2368 2369 /* Hub requests */ 2370 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2371 break; 2372 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2373 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 2374 value, 0, 0); 2375 if (index < 1 || index > sc->sc_noport) { 2376 return -1; 2377 } 2378 port = EHCI_PORTSC(index); 2379 v = EOREAD4(sc, port); 2380 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2381 v &= ~EHCI_PS_CLEAR; 2382 switch (value) { 2383 case UHF_PORT_ENABLE: 2384 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2385 break; 2386 case UHF_PORT_SUSPEND: 2387 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2388 break; 2389 v &= ~EHCI_PS_SUSP; 2390 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2391 /* see USB2 spec ch. 7.1.7.7 */ 2392 usb_delay_ms(&sc->sc_bus, 20); 2393 EOWRITE4(sc, port, v); 2394 usb_delay_ms(&sc->sc_bus, 2); 2395 #ifdef DEBUG 2396 v = EOREAD4(sc, port); 2397 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2398 printf("ehci: resume failed: %x\n", v); 2399 #endif 2400 break; 2401 case UHF_PORT_POWER: 2402 if (sc->sc_hasppc) 2403 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2404 break; 2405 case UHF_PORT_TEST: 2406 DPRINTF("clear port test %d", index, 0, 0, 0); 2407 break; 2408 case UHF_PORT_INDICATOR: 2409 DPRINTF("clear port ind %d", index, 0, 0, 0); 2410 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2411 break; 2412 case UHF_C_PORT_CONNECTION: 2413 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2414 break; 2415 case UHF_C_PORT_ENABLE: 2416 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2417 break; 2418 case UHF_C_PORT_SUSPEND: 2419 /* how? */ 2420 break; 2421 case UHF_C_PORT_OVER_CURRENT: 2422 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2423 break; 2424 case UHF_C_PORT_RESET: 2425 sc->sc_isreset[index] = 0; 2426 break; 2427 default: 2428 return -1; 2429 } 2430 #if 0 2431 switch(value) { 2432 case UHF_C_PORT_CONNECTION: 2433 case UHF_C_PORT_ENABLE: 2434 case UHF_C_PORT_SUSPEND: 2435 case UHF_C_PORT_OVER_CURRENT: 2436 case UHF_C_PORT_RESET: 2437 default: 2438 break; 2439 } 2440 #endif 2441 break; 2442 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2443 if (len == 0) 2444 break; 2445 if ((value & 0xff) != 0) { 2446 return -1; 2447 } 2448 totlen = min(buflen, sizeof(hubd)); 2449 memcpy(&hubd, buf, totlen); 2450 hubd.bNbrPorts = sc->sc_noport; 2451 v = EOREAD4(sc, EHCI_HCSPARAMS); 2452 USETW(hubd.wHubCharacteristics, 2453 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2454 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2455 ? UHD_PORT_IND : 0); 2456 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2457 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2458 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2459 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2460 totlen = min(totlen, hubd.bDescLength); 2461 memcpy(buf, &hubd, totlen); 2462 break; 2463 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2464 if (len != 4) { 2465 return -1; 2466 } 2467 memset(buf, 0, len); /* ? XXX */ 2468 totlen = len; 2469 break; 2470 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2471 DPRINTF("get port status i=%d", index, 0, 0, 0); 2472 if (index < 1 || index > sc->sc_noport) { 2473 return -1; 2474 } 2475 if (len != 4) { 2476 return -1; 2477 } 2478 v = EOREAD4(sc, EHCI_PORTSC(index)); 2479 DPRINTF("port status=0x%04x", v, 0, 0, 0); 2480 2481 i = UPS_HIGH_SPEED; 2482 if (sc->sc_flags & EHCIF_ETTF) { 2483 /* 2484 * If we are doing embedded transaction translation, 2485 * then directly attached LS/FS devices are reset by 2486 * the EHCI controller itself. PSPD is encoded 2487 * the same way as in USBSTATUS. 2488 */ 2489 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2490 } 2491 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2492 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2493 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2494 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2495 if (v & EHCI_PS_PR) i |= UPS_RESET; 2496 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2497 if (sc->sc_vendor_port_status) 2498 i = sc->sc_vendor_port_status(sc, v, i); 2499 USETW(ps.wPortStatus, i); 2500 i = 0; 2501 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2502 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2503 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2504 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2505 USETW(ps.wPortChange, i); 2506 totlen = min(len, sizeof(ps)); 2507 memcpy(buf, &ps, totlen); 2508 break; 2509 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2510 return -1; 2511 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2512 break; 2513 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2514 if (index < 1 || index > sc->sc_noport) { 2515 return -1; 2516 } 2517 port = EHCI_PORTSC(index); 2518 v = EOREAD4(sc, port); 2519 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2520 v &= ~EHCI_PS_CLEAR; 2521 switch(value) { 2522 case UHF_PORT_ENABLE: 2523 EOWRITE4(sc, port, v | EHCI_PS_PE); 2524 break; 2525 case UHF_PORT_SUSPEND: 2526 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2527 break; 2528 case UHF_PORT_RESET: 2529 DPRINTF("reset port %d", index, 0, 0, 0); 2530 if (EHCI_PS_IS_LOWSPEED(v) 2531 && sc->sc_ncomp > 0 2532 && !(sc->sc_flags & EHCIF_ETTF)) { 2533 /* 2534 * Low speed device on non-ETTF controller or 2535 * unaccompanied controller, give up ownership. 2536 */ 2537 ehci_disown(sc, index, 1); 2538 break; 2539 } 2540 /* Start reset sequence. */ 2541 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2542 EOWRITE4(sc, port, v | EHCI_PS_PR); 2543 /* Wait for reset to complete. */ 2544 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2545 if (sc->sc_dying) { 2546 return -1; 2547 } 2548 /* 2549 * An embedded transaction translator will automatically 2550 * terminate the reset sequence so there's no need to 2551 * it. 2552 */ 2553 v = EOREAD4(sc, port); 2554 if (v & EHCI_PS_PR) { 2555 /* Terminate reset sequence. */ 2556 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2557 /* Wait for HC to complete reset. */ 2558 usb_delay_ms(&sc->sc_bus, 2559 EHCI_PORT_RESET_COMPLETE); 2560 if (sc->sc_dying) { 2561 return -1; 2562 } 2563 } 2564 2565 v = EOREAD4(sc, port); 2566 DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); 2567 if (v & EHCI_PS_PR) { 2568 printf("%s: port reset timeout\n", 2569 device_xname(sc->sc_dev)); 2570 return USBD_TIMEOUT; 2571 } 2572 if (!(v & EHCI_PS_PE)) { 2573 /* Not a high speed device, give up ownership.*/ 2574 ehci_disown(sc, index, 0); 2575 break; 2576 } 2577 sc->sc_isreset[index] = 1; 2578 DPRINTF("ehci port %d reset, status = 0x%08x", index, 2579 v, 0, 0); 2580 break; 2581 case UHF_PORT_POWER: 2582 DPRINTF("set port power %d (has PPC = %d)", index, 2583 sc->sc_hasppc, 0, 0); 2584 if (sc->sc_hasppc) 2585 EOWRITE4(sc, port, v | EHCI_PS_PP); 2586 break; 2587 case UHF_PORT_TEST: 2588 DPRINTF("set port test %d", index, 0, 0, 0); 2589 break; 2590 case UHF_PORT_INDICATOR: 2591 DPRINTF("set port ind %d", index, 0, 0, 0); 2592 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2593 break; 2594 default: 2595 return -1; 2596 } 2597 break; 2598 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2599 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2600 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2601 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2602 break; 2603 default: 2604 /* default from usbroothub */ 2605 DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); 2606 2607 return buflen; 2608 } 2609 2610 DPRINTF("returning %d", totlen, 0, 0, 0); 2611 2612 return totlen; 2613 } 2614 2615 Static void 2616 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2617 { 2618 int port; 2619 uint32_t v; 2620 2621 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2622 2623 DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); 2624 #ifdef DIAGNOSTIC 2625 if (sc->sc_npcomp != 0) { 2626 int i = (index-1) / sc->sc_npcomp; 2627 if (i >= sc->sc_ncomp) 2628 printf("%s: strange port\n", 2629 device_xname(sc->sc_dev)); 2630 else 2631 printf("%s: handing over %s speed device on " 2632 "port %d to %s\n", 2633 device_xname(sc->sc_dev), 2634 lowspeed ? "low" : "full", 2635 index, device_xname(sc->sc_comps[i])); 2636 } else { 2637 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2638 } 2639 #endif 2640 port = EHCI_PORTSC(index); 2641 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2642 EOWRITE4(sc, port, v | EHCI_PS_PO); 2643 } 2644 2645 Static usbd_status 2646 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2647 { 2648 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2649 usbd_status err; 2650 2651 /* Insert last in queue. */ 2652 mutex_enter(&sc->sc_lock); 2653 err = usb_insert_transfer(xfer); 2654 mutex_exit(&sc->sc_lock); 2655 if (err) 2656 return err; 2657 2658 /* Pipe isn't running, start first */ 2659 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2660 } 2661 2662 Static usbd_status 2663 ehci_root_intr_start(struct usbd_xfer *xfer) 2664 { 2665 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2666 2667 if (sc->sc_dying) 2668 return USBD_IOERROR; 2669 2670 mutex_enter(&sc->sc_lock); 2671 sc->sc_intrxfer = xfer; 2672 mutex_exit(&sc->sc_lock); 2673 2674 return USBD_IN_PROGRESS; 2675 } 2676 2677 /* Abort a root interrupt request. */ 2678 Static void 2679 ehci_root_intr_abort(struct usbd_xfer *xfer) 2680 { 2681 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2682 2683 KASSERT(mutex_owned(&sc->sc_lock)); 2684 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2685 2686 sc->sc_intrxfer = NULL; 2687 2688 xfer->ux_status = USBD_CANCELLED; 2689 usb_transfer_complete(xfer); 2690 } 2691 2692 /* Close the root pipe. */ 2693 Static void 2694 ehci_root_intr_close(struct usbd_pipe *pipe) 2695 { 2696 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2697 2698 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2699 2700 KASSERT(mutex_owned(&sc->sc_lock)); 2701 2702 sc->sc_intrxfer = NULL; 2703 } 2704 2705 Static void 2706 ehci_root_intr_done(struct usbd_xfer *xfer) 2707 { 2708 xfer->ux_hcpriv = NULL; 2709 } 2710 2711 /************************/ 2712 2713 Static ehci_soft_qh_t * 2714 ehci_alloc_sqh(ehci_softc_t *sc) 2715 { 2716 ehci_soft_qh_t *sqh; 2717 usbd_status err; 2718 int i, offs; 2719 usb_dma_t dma; 2720 2721 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2722 2723 mutex_enter(&sc->sc_lock); 2724 if (sc->sc_freeqhs == NULL) { 2725 DPRINTF("allocating chunk", 0, 0, 0, 0); 2726 mutex_exit(&sc->sc_lock); 2727 2728 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2729 EHCI_PAGE_SIZE, &dma); 2730 #ifdef EHCI_DEBUG 2731 if (err) 2732 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2733 #endif 2734 if (err) 2735 return NULL; 2736 2737 mutex_enter(&sc->sc_lock); 2738 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2739 offs = i * EHCI_SQH_SIZE; 2740 sqh = KERNADDR(&dma, offs); 2741 sqh->physaddr = DMAADDR(&dma, offs); 2742 sqh->dma = dma; 2743 sqh->offs = offs; 2744 sqh->next = sc->sc_freeqhs; 2745 sc->sc_freeqhs = sqh; 2746 } 2747 } 2748 sqh = sc->sc_freeqhs; 2749 sc->sc_freeqhs = sqh->next; 2750 mutex_exit(&sc->sc_lock); 2751 2752 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2753 sqh->next = NULL; 2754 return sqh; 2755 } 2756 2757 Static void 2758 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2759 { 2760 KASSERT(mutex_owned(&sc->sc_lock)); 2761 2762 sqh->next = sc->sc_freeqhs; 2763 sc->sc_freeqhs = sqh; 2764 } 2765 2766 Static ehci_soft_qtd_t * 2767 ehci_alloc_sqtd(ehci_softc_t *sc) 2768 { 2769 ehci_soft_qtd_t *sqtd = NULL; 2770 usbd_status err; 2771 int i, offs; 2772 usb_dma_t dma; 2773 2774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2775 2776 mutex_enter(&sc->sc_lock); 2777 if (sc->sc_freeqtds == NULL) { 2778 DPRINTF("allocating chunk", 0, 0, 0, 0); 2779 mutex_exit(&sc->sc_lock); 2780 2781 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2782 EHCI_PAGE_SIZE, &dma); 2783 #ifdef EHCI_DEBUG 2784 if (err) 2785 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2786 #endif 2787 if (err) 2788 goto done; 2789 2790 mutex_enter(&sc->sc_lock); 2791 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2792 offs = i * EHCI_SQTD_SIZE; 2793 sqtd = KERNADDR(&dma, offs); 2794 sqtd->physaddr = DMAADDR(&dma, offs); 2795 sqtd->dma = dma; 2796 sqtd->offs = offs; 2797 2798 sqtd->nextqtd = sc->sc_freeqtds; 2799 sc->sc_freeqtds = sqtd; 2800 } 2801 } 2802 2803 sqtd = sc->sc_freeqtds; 2804 sc->sc_freeqtds = sqtd->nextqtd; 2805 mutex_exit(&sc->sc_lock); 2806 2807 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2808 sqtd->nextqtd = NULL; 2809 sqtd->xfer = NULL; 2810 2811 done: 2812 return sqtd; 2813 } 2814 2815 Static void 2816 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2817 { 2818 2819 mutex_enter(&sc->sc_lock); 2820 sqtd->nextqtd = sc->sc_freeqtds; 2821 sc->sc_freeqtds = sqtd; 2822 mutex_exit(&sc->sc_lock); 2823 } 2824 2825 Static usbd_status 2826 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2827 int alen, int rd, ehci_soft_qtd_t **sp) 2828 { 2829 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2830 uint16_t flags = xfer->ux_flags; 2831 2832 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2833 2834 ASSERT_SLEEPABLE(); 2835 KASSERT(sp); 2836 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2837 2838 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2839 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2840 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2841 KM_SLEEP); 2842 exfer->ex_nsqtd = nsqtd; 2843 2844 DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); 2845 2846 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2847 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2848 if (cur == NULL) 2849 goto nomem; 2850 exfer->ex_sqtds[j++] = cur; 2851 2852 cur->xfer = xfer; 2853 cur->len = 0; 2854 2855 } 2856 2857 *sp = exfer->ex_sqtds[0]; 2858 DPRINTF("return sqtd=%p", *sp, 0, 0, 0); 2859 2860 return USBD_NORMAL_COMPLETION; 2861 2862 nomem: 2863 ehci_free_sqtds(sc, exfer); 2864 DPRINTF("no memory", 0, 0, 0, 0); 2865 return USBD_NOMEM; 2866 } 2867 2868 Static void 2869 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2870 { 2871 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2872 DPRINTF("exfer=%p", exfer, 0, 0, 0); 2873 2874 mutex_enter(&sc->sc_lock); 2875 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2876 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2877 2878 if (sqtd == NULL) 2879 break; 2880 2881 sqtd->nextqtd = sc->sc_freeqtds; 2882 sc->sc_freeqtds = sqtd; 2883 } 2884 mutex_exit(&sc->sc_lock); 2885 } 2886 2887 Static void 2888 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2889 { 2890 if (prev) { 2891 prev->nextqtd = sqtd; 2892 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2893 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2894 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2895 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2896 } 2897 } 2898 2899 Static void 2900 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2901 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2902 { 2903 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2904 usb_dma_t *dma = &xfer->ux_dmabuf; 2905 uint16_t flags = xfer->ux_flags; 2906 ehci_soft_qtd_t *sqtd, *prev; 2907 int tog = *toggle; 2908 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2909 int len = length; 2910 2911 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2912 DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); 2913 DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); 2914 2915 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2916 2917 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2918 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2919 EHCI_QTD_SET_CERR(3) 2920 ; 2921 2922 sqtd = prev = NULL; 2923 size_t curoffs = 0; 2924 size_t j = 0; 2925 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2926 sqtd = exfer->ex_sqtds[j++]; 2927 DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); 2928 2929 /* 2930 * The EHCI hardware can handle at most 5 pages and they do 2931 * not have to be contiguous 2932 */ 2933 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2934 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2935 size_t curlen = len; 2936 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2937 /* must use multiple TDs, fill as much as possible. */ 2938 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2939 2940 /* the length must be a multiple of the max size */ 2941 curlen -= curlen % mps; 2942 } 2943 KASSERT(curlen != 0); 2944 DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, 2945 curoffs, 0); 2946 2947 /* Fill the qTD */ 2948 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2949 sqtd->qtd.qtd_status = htole32( 2950 qtdstatus | 2951 EHCI_QTD_SET_BYTES(curlen) | 2952 EHCI_QTD_SET_TOGGLE(tog)); 2953 2954 /* Find number of pages we'll be using, insert dma addresses */ 2955 size_t pages = EHCI_NPAGES(curlen); 2956 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2957 size_t pageoffs = EHCI_PAGE(curoffs); 2958 for (size_t i = 0; i < pages; i++) { 2959 paddr_t a = DMAADDR(dma, 2960 pageoffs + i * EHCI_PAGE_SIZE); 2961 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2962 /* Cast up to avoid compiler warnings */ 2963 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2964 DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, 2965 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2966 le32toh(sqtd->qtd.qtd_buffer[i])); 2967 } 2968 /* First buffer pointer requires a page offset to start at */ 2969 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2970 2971 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2973 2974 sqtd->len = curlen; 2975 2976 DPRINTF(" va %p pa %p len %d", va, 2977 DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2978 2979 ehci_append_sqtd(sqtd, prev); 2980 2981 if (((curlen + mps - 1) / mps) & 1) { 2982 tog ^= 1; 2983 } 2984 2985 curoffs += curlen; 2986 len -= curlen; 2987 } 2988 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2989 xfer, length, len, mps, exfer->ex_nsqtd, j); 2990 2991 if (!isread && 2992 (flags & USBD_FORCE_SHORT_XFER) && 2993 length % mps == 0) { 2994 /* Force a 0 length transfer at the end. */ 2995 2996 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2997 exfer->ex_nsqtd); 2998 prev = sqtd; 2999 sqtd = exfer->ex_sqtds[j++]; 3000 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3001 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3002 sqtd->qtd.qtd_status = htole32( 3003 qtdstatus | 3004 EHCI_QTD_SET_BYTES(0) | 3005 EHCI_QTD_SET_TOGGLE(tog)); 3006 3007 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3008 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3009 3010 ehci_append_sqtd(sqtd, prev); 3011 tog ^= 1; 3012 } 3013 3014 *lsqtd = sqtd; 3015 *toggle = tog; 3016 } 3017 3018 Static ehci_soft_itd_t * 3019 ehci_alloc_itd(ehci_softc_t *sc) 3020 { 3021 struct ehci_soft_itd *itd, *freeitd; 3022 usbd_status err; 3023 usb_dma_t dma; 3024 3025 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3026 3027 mutex_enter(&sc->sc_lock); 3028 3029 freeitd = LIST_FIRST(&sc->sc_freeitds); 3030 if (freeitd == NULL) { 3031 DPRINTF("allocating chunk", 0, 0, 0, 0); 3032 mutex_exit(&sc->sc_lock); 3033 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3034 EHCI_PAGE_SIZE, &dma); 3035 3036 if (err) { 3037 DPRINTF("alloc returned %d", err, 0, 0, 0); 3038 return NULL; 3039 } 3040 mutex_enter(&sc->sc_lock); 3041 3042 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3043 int offs = i * EHCI_ITD_SIZE; 3044 itd = KERNADDR(&dma, offs); 3045 itd->physaddr = DMAADDR(&dma, offs); 3046 itd->dma = dma; 3047 itd->offs = offs; 3048 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3049 } 3050 freeitd = LIST_FIRST(&sc->sc_freeitds); 3051 } 3052 3053 itd = freeitd; 3054 LIST_REMOVE(itd, free_list); 3055 mutex_exit(&sc->sc_lock); 3056 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3057 3058 itd->frame_list.next = NULL; 3059 itd->frame_list.prev = NULL; 3060 itd->xfer_next = NULL; 3061 itd->slot = 0; 3062 3063 return itd; 3064 } 3065 3066 Static ehci_soft_sitd_t * 3067 ehci_alloc_sitd(ehci_softc_t *sc) 3068 { 3069 struct ehci_soft_sitd *sitd, *freesitd; 3070 usbd_status err; 3071 int i, offs; 3072 usb_dma_t dma; 3073 3074 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3075 3076 mutex_enter(&sc->sc_lock); 3077 freesitd = LIST_FIRST(&sc->sc_freesitds); 3078 if (freesitd == NULL) { 3079 DPRINTF("allocating chunk", 0, 0, 0, 0); 3080 mutex_exit(&sc->sc_lock); 3081 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3082 EHCI_PAGE_SIZE, &dma); 3083 3084 if (err) { 3085 DPRINTF("alloc returned %d", err, 0, 0, 3086 0); 3087 return NULL; 3088 } 3089 3090 mutex_enter(&sc->sc_lock); 3091 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3092 offs = i * EHCI_SITD_SIZE; 3093 sitd = KERNADDR(&dma, offs); 3094 sitd->physaddr = DMAADDR(&dma, offs); 3095 sitd->dma = dma; 3096 sitd->offs = offs; 3097 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3098 } 3099 freesitd = LIST_FIRST(&sc->sc_freesitds); 3100 } 3101 3102 sitd = freesitd; 3103 LIST_REMOVE(sitd, free_list); 3104 mutex_exit(&sc->sc_lock); 3105 3106 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3107 3108 sitd->frame_list.next = NULL; 3109 sitd->frame_list.prev = NULL; 3110 sitd->xfer_next = NULL; 3111 sitd->slot = 0; 3112 3113 return sitd; 3114 } 3115 3116 /****************/ 3117 3118 /* 3119 * Close a reqular pipe. 3120 * Assumes that there are no pending transactions. 3121 */ 3122 Static void 3123 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3124 { 3125 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3126 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3127 ehci_soft_qh_t *sqh = epipe->sqh; 3128 3129 KASSERT(mutex_owned(&sc->sc_lock)); 3130 3131 ehci_rem_qh(sc, sqh, head); 3132 ehci_free_sqh(sc, epipe->sqh); 3133 } 3134 3135 /* 3136 * Abort a device request. 3137 * If this routine is called at splusb() it guarantees that the request 3138 * will be removed from the hardware scheduling and that the callback 3139 * for it will be called with USBD_CANCELLED status. 3140 * It's impossible to guarantee that the requested transfer will not 3141 * have happened since the hardware runs concurrently. 3142 * If the transaction has already happened we rely on the ordinary 3143 * interrupt processing to process it. 3144 * XXX This is most probably wrong. 3145 * XXXMRG this doesn't make sense anymore. 3146 */ 3147 Static void 3148 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3149 { 3150 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3151 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3152 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3153 ehci_soft_qh_t *sqh = epipe->sqh; 3154 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3155 ehci_physaddr_t cur; 3156 uint32_t qhstatus; 3157 int hit; 3158 int wake; 3159 3160 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3161 3162 DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); 3163 3164 KASSERT(mutex_owned(&sc->sc_lock)); 3165 ASSERT_SLEEPABLE(); 3166 3167 if (sc->sc_dying) { 3168 /* If we're dying, just do the software part. */ 3169 xfer->ux_status = status; /* make software ignore it */ 3170 callout_stop(&xfer->ux_callout); 3171 usb_transfer_complete(xfer); 3172 return; 3173 } 3174 3175 /* 3176 * If an abort is already in progress then just wait for it to 3177 * complete and return. 3178 */ 3179 if (xfer->ux_hcflags & UXFER_ABORTING) { 3180 DPRINTF("already aborting", 0, 0, 0, 0); 3181 #ifdef DIAGNOSTIC 3182 if (status == USBD_TIMEOUT) 3183 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3184 #endif 3185 /* Override the status which might be USBD_TIMEOUT. */ 3186 xfer->ux_status = status; 3187 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3188 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3189 while (xfer->ux_hcflags & UXFER_ABORTING) 3190 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3191 return; 3192 } 3193 xfer->ux_hcflags |= UXFER_ABORTING; 3194 3195 /* 3196 * Step 1: Make interrupt routine and hardware ignore xfer. 3197 */ 3198 xfer->ux_status = status; /* make software ignore it */ 3199 callout_stop(&xfer->ux_callout); 3200 ehci_del_intr_list(sc, exfer); 3201 3202 usb_syncmem(&sqh->dma, 3203 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3204 sizeof(sqh->qh.qh_qtd.qtd_status), 3205 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3206 qhstatus = sqh->qh.qh_qtd.qtd_status; 3207 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3208 usb_syncmem(&sqh->dma, 3209 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3210 sizeof(sqh->qh.qh_qtd.qtd_status), 3211 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3212 3213 if (exfer->ex_type == EX_CTRL) { 3214 fsqtd = exfer->ex_setup; 3215 lsqtd = exfer->ex_status; 3216 } else { 3217 fsqtd = exfer->ex_sqtdstart; 3218 lsqtd = exfer->ex_sqtdend; 3219 } 3220 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3221 usb_syncmem(&sqtd->dma, 3222 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3223 sizeof(sqtd->qtd.qtd_status), 3224 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3225 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3226 usb_syncmem(&sqtd->dma, 3227 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3228 sizeof(sqtd->qtd.qtd_status), 3229 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3230 if (sqtd == lsqtd) 3231 break; 3232 } 3233 3234 /* 3235 * Step 2: Wait until we know hardware has finished any possible 3236 * use of the xfer. Also make sure the soft interrupt routine 3237 * has run. 3238 */ 3239 ehci_sync_hc(sc); 3240 sc->sc_softwake = 1; 3241 usb_schedsoftintr(&sc->sc_bus); 3242 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3243 3244 /* 3245 * Step 3: Remove any vestiges of the xfer from the hardware. 3246 * The complication here is that the hardware may have executed 3247 * beyond the xfer we're trying to abort. So as we're scanning 3248 * the TDs of this xfer we check if the hardware points to 3249 * any of them. 3250 */ 3251 3252 usb_syncmem(&sqh->dma, 3253 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3254 sizeof(sqh->qh.qh_curqtd), 3255 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3256 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3257 hit = 0; 3258 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3259 hit |= cur == sqtd->physaddr; 3260 if (sqtd == lsqtd) 3261 break; 3262 } 3263 sqtd = sqtd->nextqtd; 3264 /* Zap curqtd register if hardware pointed inside the xfer. */ 3265 if (hit && sqtd != NULL) { 3266 DPRINTF("cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3267 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3268 usb_syncmem(&sqh->dma, 3269 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3270 sizeof(sqh->qh.qh_curqtd), 3271 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3272 sqh->qh.qh_qtd.qtd_status = qhstatus; 3273 usb_syncmem(&sqh->dma, 3274 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3275 sizeof(sqh->qh.qh_qtd.qtd_status), 3276 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3277 } else { 3278 DPRINTF("no hit", 0, 0, 0, 0); 3279 usb_syncmem(&sqh->dma, 3280 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3281 sizeof(sqh->qh.qh_curqtd), 3282 BUS_DMASYNC_PREREAD); 3283 } 3284 3285 /* 3286 * Step 4: Execute callback. 3287 */ 3288 #ifdef DIAGNOSTIC 3289 exfer->ex_isdone = true; 3290 #endif 3291 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3292 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3293 usb_transfer_complete(xfer); 3294 if (wake) { 3295 cv_broadcast(&xfer->ux_hccv); 3296 } 3297 3298 KASSERT(mutex_owned(&sc->sc_lock)); 3299 } 3300 3301 Static void 3302 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3303 { 3304 ehci_isoc_trans_t trans_status; 3305 struct ehci_xfer *exfer; 3306 ehci_softc_t *sc; 3307 struct ehci_soft_itd *itd; 3308 struct ehci_soft_sitd *sitd; 3309 int i, wake; 3310 3311 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3312 3313 exfer = EHCI_XFER2EXFER(xfer); 3314 sc = EHCI_XFER2SC(xfer); 3315 3316 DPRINTF("xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3317 3318 KASSERT(mutex_owned(&sc->sc_lock)); 3319 3320 if (sc->sc_dying) { 3321 xfer->ux_status = status; 3322 callout_stop(&xfer->ux_callout); 3323 usb_transfer_complete(xfer); 3324 return; 3325 } 3326 3327 if (xfer->ux_hcflags & UXFER_ABORTING) { 3328 DPRINTF("already aborting", 0, 0, 0, 0); 3329 3330 #ifdef DIAGNOSTIC 3331 if (status == USBD_TIMEOUT) 3332 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3333 #endif 3334 3335 xfer->ux_status = status; 3336 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3337 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3338 while (xfer->ux_hcflags & UXFER_ABORTING) 3339 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3340 goto done; 3341 } 3342 xfer->ux_hcflags |= UXFER_ABORTING; 3343 3344 xfer->ux_status = status; 3345 callout_stop(&xfer->ux_callout); 3346 ehci_del_intr_list(sc, exfer); 3347 3348 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3349 for (itd = exfer->ex_itdstart; itd != NULL; 3350 itd = itd->xfer_next) { 3351 usb_syncmem(&itd->dma, 3352 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3353 sizeof(itd->itd.itd_ctl), 3354 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3355 3356 for (i = 0; i < 8; i++) { 3357 trans_status = le32toh(itd->itd.itd_ctl[i]); 3358 trans_status &= ~EHCI_ITD_ACTIVE; 3359 itd->itd.itd_ctl[i] = htole32(trans_status); 3360 } 3361 3362 usb_syncmem(&itd->dma, 3363 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3364 sizeof(itd->itd.itd_ctl), 3365 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3366 } 3367 } else { 3368 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3369 sitd = sitd->xfer_next) { 3370 usb_syncmem(&sitd->dma, 3371 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3372 sizeof(sitd->sitd.sitd_buffer), 3373 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3374 3375 trans_status = le32toh(sitd->sitd.sitd_trans); 3376 trans_status &= ~EHCI_SITD_ACTIVE; 3377 sitd->sitd.sitd_trans = htole32(trans_status); 3378 3379 usb_syncmem(&sitd->dma, 3380 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3381 sizeof(sitd->sitd.sitd_buffer), 3382 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3383 } 3384 } 3385 3386 sc->sc_softwake = 1; 3387 usb_schedsoftintr(&sc->sc_bus); 3388 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3389 3390 #ifdef DIAGNOSTIC 3391 exfer->ex_isdone = true; 3392 #endif 3393 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3394 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3395 usb_transfer_complete(xfer); 3396 if (wake) { 3397 cv_broadcast(&xfer->ux_hccv); 3398 } 3399 3400 done: 3401 KASSERT(mutex_owned(&sc->sc_lock)); 3402 return; 3403 } 3404 3405 Static void 3406 ehci_timeout(void *addr) 3407 { 3408 struct usbd_xfer *xfer = addr; 3409 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3410 struct usbd_pipe *pipe = xfer->ux_pipe; 3411 struct usbd_device *dev = pipe->up_dev; 3412 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3413 3414 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3415 3416 DPRINTF("exfer %p", exfer, 0, 0, 0); 3417 #ifdef EHCI_DEBUG 3418 if (ehcidebug >= 2) 3419 usbd_dump_pipe(pipe); 3420 #endif 3421 3422 if (sc->sc_dying) { 3423 mutex_enter(&sc->sc_lock); 3424 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3425 mutex_exit(&sc->sc_lock); 3426 return; 3427 } 3428 3429 /* Execute the abort in a process context. */ 3430 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3431 USB_TASKQ_MPSAFE); 3432 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3433 } 3434 3435 Static void 3436 ehci_timeout_task(void *addr) 3437 { 3438 struct usbd_xfer *xfer = addr; 3439 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3440 3441 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3442 3443 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3444 3445 mutex_enter(&sc->sc_lock); 3446 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3447 mutex_exit(&sc->sc_lock); 3448 } 3449 3450 /************************/ 3451 3452 Static int 3453 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3454 { 3455 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3456 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3457 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3458 usb_device_request_t *req = &xfer->ux_request; 3459 ehci_soft_qtd_t *setup, *status, *next; 3460 int isread = req->bmRequestType & UT_READ; 3461 int len = xfer->ux_bufsize; 3462 int err; 3463 3464 exfer->ex_type = EX_CTRL; 3465 exfer->ex_status = NULL; 3466 exfer->ex_data = NULL; 3467 exfer->ex_setup = ehci_alloc_sqtd(sc); 3468 if (exfer->ex_setup == NULL) { 3469 err = ENOMEM; 3470 goto bad1; 3471 } 3472 exfer->ex_status = ehci_alloc_sqtd(sc); 3473 if (exfer->ex_status == NULL) { 3474 err = ENOMEM; 3475 goto bad2; 3476 } 3477 setup = exfer->ex_setup; 3478 status = exfer->ex_status; 3479 exfer->ex_nsqtd = 0; 3480 next = status; 3481 /* Set up data transaction */ 3482 if (len != 0) { 3483 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3484 &exfer->ex_data); 3485 if (err) 3486 goto bad3; 3487 next = exfer->ex_data; 3488 } 3489 3490 /* Clear toggle */ 3491 setup->qtd.qtd_status = htole32( 3492 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3493 EHCI_QTD_SET_TOGGLE(0) | 3494 EHCI_QTD_SET_BYTES(sizeof(*req)) 3495 ); 3496 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3497 setup->qtd.qtd_buffer_hi[0] = 0; 3498 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3499 setup->nextqtd = next; 3500 setup->xfer = xfer; 3501 setup->len = sizeof(*req); 3502 3503 status->qtd.qtd_status = htole32( 3504 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3505 EHCI_QTD_SET_TOGGLE(1) | 3506 EHCI_QTD_IOC 3507 ); 3508 status->qtd.qtd_buffer[0] = 0; 3509 status->qtd.qtd_buffer_hi[0] = 0; 3510 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3511 status->nextqtd = NULL; 3512 status->xfer = xfer; 3513 status->len = 0; 3514 3515 return 0; 3516 bad3: 3517 ehci_free_sqtd(sc, exfer->ex_status); 3518 bad2: 3519 ehci_free_sqtd(sc, exfer->ex_setup); 3520 bad1: 3521 return err; 3522 } 3523 3524 Static void 3525 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3526 { 3527 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3528 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3529 3530 KASSERT(ex->ex_type == EX_CTRL); 3531 3532 ehci_free_sqtd(sc, ex->ex_setup); 3533 ehci_free_sqtd(sc, ex->ex_status); 3534 ehci_free_sqtds(sc, ex); 3535 if (ex->ex_nsqtd) 3536 kmem_free(ex->ex_sqtds, 3537 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3538 } 3539 3540 Static usbd_status 3541 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3542 { 3543 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3544 usbd_status err; 3545 3546 /* Insert last in queue. */ 3547 mutex_enter(&sc->sc_lock); 3548 err = usb_insert_transfer(xfer); 3549 mutex_exit(&sc->sc_lock); 3550 if (err) 3551 return err; 3552 3553 /* Pipe isn't running, start first */ 3554 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3555 } 3556 3557 Static usbd_status 3558 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3559 { 3560 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3561 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3562 usb_device_request_t *req = &xfer->ux_request; 3563 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3564 ehci_soft_qtd_t *setup, *status, *next; 3565 ehci_soft_qh_t *sqh; 3566 3567 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3568 3569 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3570 3571 if (sc->sc_dying) 3572 return USBD_IOERROR; 3573 3574 const int isread = req->bmRequestType & UT_READ; 3575 const int len = UGETW(req->wLength); 3576 3577 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 3578 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3579 UGETW(req->wIndex)); 3580 DPRINTF("len=%d, addr=%d, endpt=%d", len, epipe->pipe.up_dev->ud_addr, 3581 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3582 3583 sqh = epipe->sqh; 3584 3585 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3586 "address QH %" __PRIuBIT " pipe %d\n", 3587 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3588 epipe->pipe.up_dev->ud_addr); 3589 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3590 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3591 "MPS QH %" __PRIuBIT " pipe %d\n", 3592 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3593 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3594 3595 setup = exfer->ex_setup; 3596 status = exfer->ex_status; 3597 3598 DPRINTF("setup %p status %p data %p", setup, status, exfer->ex_data, 0); 3599 KASSERTMSG(setup != NULL && status != NULL, 3600 "Failed memory allocation, setup %p status %p", 3601 setup, status); 3602 3603 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3604 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3605 3606 /* Clear toggle */ 3607 setup->qtd.qtd_status &= ~htole32( 3608 EHCI_QTD_STATUS_MASK | 3609 EHCI_QTD_BYTES_MASK | 3610 EHCI_QTD_TOGGLE_MASK | 3611 EHCI_QTD_CERR_MASK 3612 ); 3613 setup->qtd.qtd_status |= htole32( 3614 EHCI_QTD_ACTIVE | 3615 EHCI_QTD_SET_CERR(3) | 3616 EHCI_QTD_SET_TOGGLE(0) | 3617 EHCI_QTD_SET_BYTES(sizeof(*req)) 3618 ); 3619 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3620 setup->qtd.qtd_buffer_hi[0] = 0; 3621 3622 next = status; 3623 status->qtd.qtd_status &= ~htole32( 3624 EHCI_QTD_STATUS_MASK | 3625 EHCI_QTD_PID_MASK | 3626 EHCI_QTD_BYTES_MASK | 3627 EHCI_QTD_TOGGLE_MASK | 3628 EHCI_QTD_CERR_MASK 3629 ); 3630 status->qtd.qtd_status |= htole32( 3631 EHCI_QTD_ACTIVE | 3632 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3633 EHCI_QTD_SET_CERR(3) | 3634 EHCI_QTD_SET_TOGGLE(1) | 3635 EHCI_QTD_SET_BYTES(0) | 3636 EHCI_QTD_IOC 3637 ); 3638 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3639 3640 KASSERT(exfer->ex_isdone); 3641 #ifdef DIAGNOSTIC 3642 exfer->ex_isdone = false; 3643 #endif 3644 3645 /* Set up data transaction */ 3646 if (len != 0) { 3647 ehci_soft_qtd_t *end; 3648 3649 /* Start toggle at 1. */ 3650 int toggle = 1; 3651 next = exfer->ex_data; 3652 KASSERTMSG(next != NULL, "Failed memory allocation"); 3653 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3654 end->nextqtd = status; 3655 end->qtd.qtd_next = end->qtd.qtd_altnext = 3656 htole32(status->physaddr); 3657 3658 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3659 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3660 3661 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3662 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3663 } 3664 3665 setup->nextqtd = next; 3666 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3667 3668 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3669 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3670 3671 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3672 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3673 3674 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3675 3676 #ifdef EHCI_DEBUG 3677 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3678 ehci_dump_sqh(sqh); 3679 ehci_dump_sqtds(setup); 3680 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3681 #endif 3682 3683 mutex_enter(&sc->sc_lock); 3684 3685 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3686 ehci_set_qh_qtd(sqh, setup); 3687 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3688 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3689 ehci_timeout, xfer); 3690 } 3691 ehci_add_intr_list(sc, exfer); 3692 xfer->ux_status = USBD_IN_PROGRESS; 3693 mutex_exit(&sc->sc_lock); 3694 3695 #if 0 3696 #ifdef EHCI_DEBUG 3697 DPRINTFN(10, "status=%x, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3698 // delay(10000); 3699 ehci_dump_regs(sc); 3700 ehci_dump_sqh(sc->sc_async_head); 3701 ehci_dump_sqh(sqh); 3702 ehci_dump_sqtds(setup); 3703 #endif 3704 #endif 3705 3706 if (sc->sc_bus.ub_usepolling) 3707 ehci_waitintr(sc, xfer); 3708 3709 return USBD_IN_PROGRESS; 3710 } 3711 3712 Static void 3713 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3714 { 3715 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3716 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3717 usb_device_request_t *req = &xfer->ux_request; 3718 int len = UGETW(req->wLength); 3719 int rd = req->bmRequestType & UT_READ; 3720 3721 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3722 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3723 3724 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3725 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3726 3727 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3728 BUS_DMASYNC_POSTWRITE); 3729 if (len) 3730 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3731 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3732 3733 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3734 } 3735 3736 /* Abort a device control request. */ 3737 Static void 3738 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3739 { 3740 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3741 3742 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3743 ehci_abort_xfer(xfer, USBD_CANCELLED); 3744 } 3745 3746 /* Close a device control pipe. */ 3747 Static void 3748 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3749 { 3750 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3751 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3752 3753 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3754 3755 KASSERT(mutex_owned(&sc->sc_lock)); 3756 3757 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3758 3759 ehci_close_pipe(pipe, sc->sc_async_head); 3760 } 3761 3762 /* 3763 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3764 * qTD status, or miss signalling occasionally under heavy load. If the host 3765 * machine is too fast, we we can miss transaction completion - when we scan 3766 * the active list the transaction still seems to be active. This generally 3767 * exhibits itself as a umass stall that never recovers. 3768 * 3769 * We work around this behaviour by setting up this callback after any softintr 3770 * that completes with transactions still pending, giving us another chance to 3771 * check for completion after the writeback has taken place. 3772 */ 3773 Static void 3774 ehci_intrlist_timeout(void *arg) 3775 { 3776 ehci_softc_t *sc = arg; 3777 3778 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3779 3780 usb_schedsoftintr(&sc->sc_bus); 3781 } 3782 3783 /************************/ 3784 3785 Static int 3786 ehci_device_bulk_init(struct usbd_xfer *xfer) 3787 { 3788 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3789 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3790 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3791 int endpt = ed->bEndpointAddress; 3792 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3793 int len = xfer->ux_bufsize; 3794 int err = 0; 3795 3796 exfer->ex_type = EX_BULK; 3797 exfer->ex_nsqtd = 0; 3798 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3799 &exfer->ex_sqtdstart); 3800 3801 return err; 3802 } 3803 3804 Static void 3805 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3806 { 3807 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3808 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3809 3810 KASSERT(ex->ex_type == EX_BULK); 3811 3812 ehci_free_sqtds(sc, ex); 3813 if (ex->ex_nsqtd) 3814 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3815 } 3816 3817 Static usbd_status 3818 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3819 { 3820 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3821 usbd_status err; 3822 3823 /* Insert last in queue. */ 3824 mutex_enter(&sc->sc_lock); 3825 err = usb_insert_transfer(xfer); 3826 mutex_exit(&sc->sc_lock); 3827 if (err) 3828 return err; 3829 3830 /* Pipe isn't running, start first */ 3831 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3832 } 3833 3834 Static usbd_status 3835 ehci_device_bulk_start(struct usbd_xfer *xfer) 3836 { 3837 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3838 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3839 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3840 ehci_soft_qh_t *sqh; 3841 ehci_soft_qtd_t *end; 3842 int len, isread, endpt; 3843 3844 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3845 3846 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3847 xfer->ux_flags, 0); 3848 3849 if (sc->sc_dying) 3850 return USBD_IOERROR; 3851 3852 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3853 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3854 3855 len = xfer->ux_length; 3856 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3857 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3858 sqh = epipe->sqh; 3859 3860 KASSERT(exfer->ex_isdone); 3861 #ifdef DIAGNOSTIC 3862 exfer->ex_isdone = false; 3863 #endif 3864 3865 /* Take lock here to protect nexttoggle */ 3866 mutex_enter(&sc->sc_lock); 3867 3868 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3869 3870 exfer->ex_sqtdend = end; 3871 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3872 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3873 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3874 3875 #ifdef EHCI_DEBUG 3876 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3877 ehci_dump_sqh(sqh); 3878 ehci_dump_sqtds(exfer->ex_sqtdstart); 3879 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3880 #endif 3881 3882 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3883 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3884 3885 /* also does usb_syncmem(sqh) */ 3886 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3887 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3888 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3889 ehci_timeout, xfer); 3890 } 3891 ehci_add_intr_list(sc, exfer); 3892 xfer->ux_status = USBD_IN_PROGRESS; 3893 mutex_exit(&sc->sc_lock); 3894 3895 #if 0 3896 #ifdef EHCI_DEBUG 3897 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3898 // delay(10000); 3899 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3900 ehci_dump_regs(sc); 3901 #if 0 3902 printf("async_head:\n"); 3903 ehci_dump_sqh(sc->sc_async_head); 3904 #endif 3905 DPRINTF("sqh:", 0, 0, 0, 0); 3906 ehci_dump_sqh(sqh); 3907 ehci_dump_sqtds(exfer->ex_sqtdstart); 3908 #endif 3909 #endif 3910 3911 if (sc->sc_bus.ub_usepolling) 3912 ehci_waitintr(sc, xfer); 3913 3914 return USBD_IN_PROGRESS; 3915 } 3916 3917 Static void 3918 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3919 { 3920 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3921 3922 DPRINTF("xfer %p", xfer, 0, 0, 0); 3923 ehci_abort_xfer(xfer, USBD_CANCELLED); 3924 } 3925 3926 /* 3927 * Close a device bulk pipe. 3928 */ 3929 Static void 3930 ehci_device_bulk_close(struct usbd_pipe *pipe) 3931 { 3932 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3933 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3934 3935 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3936 3937 KASSERT(mutex_owned(&sc->sc_lock)); 3938 3939 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3940 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3941 ehci_close_pipe(pipe, sc->sc_async_head); 3942 } 3943 3944 Static void 3945 ehci_device_bulk_done(struct usbd_xfer *xfer) 3946 { 3947 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3948 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3949 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3950 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3951 3952 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3953 3954 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 3955 3956 KASSERT(mutex_owned(&sc->sc_lock)); 3957 3958 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3959 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3960 3961 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3962 } 3963 3964 /************************/ 3965 3966 Static usbd_status 3967 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3968 { 3969 struct ehci_soft_islot *isp; 3970 int islot, lev; 3971 3972 /* Find a poll rate that is large enough. */ 3973 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3974 if (EHCI_ILEV_IVAL(lev) <= ival) 3975 break; 3976 3977 /* Pick an interrupt slot at the right level. */ 3978 /* XXX could do better than picking at random */ 3979 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3980 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3981 3982 sqh->islot = islot; 3983 isp = &sc->sc_islots[islot]; 3984 mutex_enter(&sc->sc_lock); 3985 ehci_add_qh(sc, sqh, isp->sqh); 3986 mutex_exit(&sc->sc_lock); 3987 3988 return USBD_NORMAL_COMPLETION; 3989 } 3990 3991 3992 Static int 3993 ehci_device_intr_init(struct usbd_xfer *xfer) 3994 { 3995 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3996 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3997 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3998 int endpt = ed->bEndpointAddress; 3999 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4000 int len = xfer->ux_bufsize; 4001 int err; 4002 4003 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4004 4005 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4006 xfer->ux_flags, 0); 4007 4008 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4009 KASSERT(len != 0); 4010 4011 exfer->ex_type = EX_INTR; 4012 exfer->ex_nsqtd = 0; 4013 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4014 &exfer->ex_sqtdstart); 4015 4016 return err; 4017 } 4018 4019 Static void 4020 ehci_device_intr_fini(struct usbd_xfer *xfer) 4021 { 4022 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4023 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4024 4025 KASSERT(ex->ex_type == EX_INTR); 4026 4027 ehci_free_sqtds(sc, ex); 4028 if (ex->ex_nsqtd) 4029 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4030 } 4031 4032 Static usbd_status 4033 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4034 { 4035 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4036 usbd_status err; 4037 4038 /* Insert last in queue. */ 4039 mutex_enter(&sc->sc_lock); 4040 err = usb_insert_transfer(xfer); 4041 mutex_exit(&sc->sc_lock); 4042 if (err) 4043 return err; 4044 4045 /* 4046 * Pipe isn't running (otherwise err would be USBD_INPROG), 4047 * so start it first. 4048 */ 4049 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4050 } 4051 4052 Static usbd_status 4053 ehci_device_intr_start(struct usbd_xfer *xfer) 4054 { 4055 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4056 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4057 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4058 ehci_soft_qtd_t *end; 4059 ehci_soft_qh_t *sqh; 4060 int len, isread, endpt; 4061 4062 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4063 4064 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4065 xfer->ux_flags, 0); 4066 4067 if (sc->sc_dying) 4068 return USBD_IOERROR; 4069 4070 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4071 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4072 4073 len = xfer->ux_length; 4074 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4075 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4076 sqh = epipe->sqh; 4077 4078 KASSERT(exfer->ex_isdone); 4079 #ifdef DIAGNOSTIC 4080 exfer->ex_isdone = false; 4081 #endif 4082 4083 /* Take lock to protect nexttoggle */ 4084 mutex_enter(&sc->sc_lock); 4085 4086 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4087 4088 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4089 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4090 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4091 exfer->ex_sqtdend = end; 4092 4093 #ifdef EHCI_DEBUG 4094 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4095 ehci_dump_sqh(sqh); 4096 ehci_dump_sqtds(exfer->ex_sqtdstart); 4097 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4098 #endif 4099 4100 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4101 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4102 4103 /* also does usb_syncmem(sqh) */ 4104 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4105 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4106 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4107 ehci_timeout, xfer); 4108 } 4109 ehci_add_intr_list(sc, exfer); 4110 xfer->ux_status = USBD_IN_PROGRESS; 4111 mutex_exit(&sc->sc_lock); 4112 4113 #if 0 4114 #ifdef EHCI_DEBUG 4115 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4116 // delay(10000); 4117 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4118 ehci_dump_regs(sc); 4119 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4120 ehci_dump_sqh(sqh); 4121 ehci_dump_sqtds(exfer->ex_sqtdstart); 4122 #endif 4123 #endif 4124 4125 if (sc->sc_bus.ub_usepolling) 4126 ehci_waitintr(sc, xfer); 4127 4128 return USBD_IN_PROGRESS; 4129 } 4130 4131 Static void 4132 ehci_device_intr_abort(struct usbd_xfer *xfer) 4133 { 4134 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4135 4136 DPRINTF("xfer=%p", xfer, 0, 0, 0); 4137 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4138 4139 /* 4140 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4141 * async doorbell. That's dependent on the async list, wheras 4142 * intr xfers are periodic, should not use this? 4143 */ 4144 ehci_abort_xfer(xfer, USBD_CANCELLED); 4145 } 4146 4147 Static void 4148 ehci_device_intr_close(struct usbd_pipe *pipe) 4149 { 4150 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4151 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4152 struct ehci_soft_islot *isp; 4153 4154 KASSERT(mutex_owned(&sc->sc_lock)); 4155 4156 isp = &sc->sc_islots[epipe->sqh->islot]; 4157 ehci_close_pipe(pipe, isp->sqh); 4158 } 4159 4160 Static void 4161 ehci_device_intr_done(struct usbd_xfer *xfer) 4162 { 4163 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4164 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4165 int isread, endpt; 4166 4167 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4168 4169 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4170 0, 0); 4171 4172 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4173 4174 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4175 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4176 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4177 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4178 } 4179 4180 /************************/ 4181 Static int 4182 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4183 { 4184 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4185 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4186 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4187 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4188 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4189 int i, k, frames; 4190 u_int huba, dir; 4191 int err; 4192 4193 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4194 4195 start = NULL; 4196 sitd = NULL; 4197 4198 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4199 xfer->ux_flags, 0); 4200 4201 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4202 KASSERT(xfer->ux_nframes != 0); 4203 KASSERT(exfer->ex_isdone); 4204 4205 exfer->ex_type = EX_FS_ISOC; 4206 /* 4207 * Step 1: Allocate and initialize sitds. 4208 */ 4209 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4210 if (i > 16 || i == 0) { 4211 /* Spec page 271 says intervals > 16 are invalid */ 4212 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4213 4214 return EINVAL; 4215 } 4216 4217 frames = xfer->ux_nframes; 4218 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4219 sitd = ehci_alloc_sitd(sc); 4220 if (sitd == NULL) { 4221 err = ENOMEM; 4222 goto fail; 4223 } 4224 4225 if (prev) 4226 prev->xfer_next = sitd; 4227 else 4228 start = sitd; 4229 4230 huba = dev->ud_myhsport->up_parent->ud_addr; 4231 4232 #if 0 4233 if (sc->sc_flags & EHCIF_FREESCALE) { 4234 // Set hub address to 0 if embedded TT is used. 4235 if (huba == sc->sc_addr) 4236 huba = 0; 4237 } 4238 #endif 4239 4240 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4241 dir = UE_GET_DIR(k) ? 1 : 0; 4242 sitd->sitd.sitd_endp = 4243 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4244 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4245 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4246 EHCI_SITD_SET_HUBA(huba) | 4247 EHCI_SITD_SET_DIR(dir)); 4248 4249 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4250 } /* End of frame */ 4251 4252 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4253 4254 stop = sitd; 4255 stop->xfer_next = NULL; 4256 exfer->ex_sitdstart = start; 4257 exfer->ex_sitdend = stop; 4258 4259 return 0; 4260 4261 fail: 4262 mutex_enter(&sc->sc_lock); 4263 ehci_soft_sitd_t *next; 4264 for (sitd = start; sitd; sitd = next) { 4265 next = sitd->xfer_next; 4266 ehci_free_sitd_locked(sc, sitd); 4267 } 4268 mutex_exit(&sc->sc_lock); 4269 4270 return err; 4271 } 4272 4273 Static void 4274 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4275 { 4276 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4277 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4278 4279 KASSERT(ex->ex_type == EX_FS_ISOC); 4280 4281 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4282 } 4283 4284 Static usbd_status 4285 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4286 { 4287 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4288 usbd_status __diagused err; 4289 4290 mutex_enter(&sc->sc_lock); 4291 err = usb_insert_transfer(xfer); 4292 mutex_exit(&sc->sc_lock); 4293 4294 KASSERT(err == USBD_NORMAL_COMPLETION); 4295 4296 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4297 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4298 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4299 ehci_soft_sitd_t *sitd; 4300 usb_dma_t *dma_buf; 4301 int i, j, k, frames; 4302 int offs, total_length; 4303 int frindex; 4304 u_int dir; 4305 4306 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4307 4308 sitd = NULL; 4309 total_length = 0; 4310 4311 4312 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4313 xfer->ux_flags, 0); 4314 4315 if (sc->sc_dying) 4316 return USBD_IOERROR; 4317 4318 /* 4319 * To avoid complication, don't allow a request right now that'll span 4320 * the entire frame table. To within 4 frames, to allow some leeway 4321 * on either side of where the hc currently is. 4322 */ 4323 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4324 xfer->ux_nframes >= sc->sc_flsize - 4) { 4325 printf("ehci: isoc descriptor requested that spans the entire" 4326 "frametable, too many frames\n"); 4327 return USBD_INVAL; 4328 } 4329 4330 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4331 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4332 KASSERT(exfer->ex_isdone); 4333 #ifdef DIAGNOSTIC 4334 exfer->ex_isdone = false; 4335 #endif 4336 4337 /* 4338 * Step 1: Initialize sitds. 4339 */ 4340 4341 frames = xfer->ux_nframes; 4342 dma_buf = &xfer->ux_dmabuf; 4343 offs = 0; 4344 4345 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4346 i++, sitd = sitd->xfer_next) { 4347 KASSERT(sitd != NULL); 4348 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4349 4350 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4351 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4352 4353 /* Set page0 index and offset - TP and T-offset are set below */ 4354 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4355 4356 total_length += xfer->ux_frlengths[i]; 4357 offs += xfer->ux_frlengths[i]; 4358 4359 sitd->sitd.sitd_buffer[1] = 4360 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4361 4362 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4363 4364 #if 0 4365 if (sc->sc_flags & EHCIF_FREESCALE) { 4366 // Set hub address to 0 if embedded TT is used. 4367 if (huba == sc->sc_addr) 4368 huba = 0; 4369 } 4370 #endif 4371 4372 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4373 dir = UE_GET_DIR(k) ? 1 : 0; 4374 KASSERT(sitd->sitd.sitd_endp == htole32( 4375 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4376 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4377 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4378 EHCI_SITD_SET_HUBA(huba) | 4379 EHCI_SITD_SET_DIR(dir))); 4380 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4381 4382 uint8_t sa = 0; 4383 uint8_t sb = 0; 4384 u_int temp, tlen; 4385 4386 if (dir == 0) { /* OUT */ 4387 temp = 0; 4388 tlen = xfer->ux_frlengths[i]; 4389 if (tlen <= 188) { 4390 temp |= 1; /* T-count = 1, TP = ALL */ 4391 tlen = 1; 4392 } else { 4393 tlen += 187; 4394 tlen /= 188; 4395 temp |= tlen; /* T-count = [1..6] */ 4396 temp |= 8; /* TP = Begin */ 4397 } 4398 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4399 4400 tlen += sa; 4401 4402 if (tlen >= 8) { 4403 sb = 0; 4404 } else { 4405 sb = (1 << tlen); 4406 } 4407 4408 sa = (1 << sa); 4409 sa = (sb - sa) & 0x3F; 4410 sb = 0; 4411 } else { 4412 sb = (-(4 << sa)) & 0xFE; 4413 sa = (1 << sa) & 0x3F; 4414 sa = 0x01; 4415 sb = 0xfc; 4416 } 4417 4418 sitd->sitd.sitd_sched = htole32( 4419 EHCI_SITD_SET_SMASK(sa) | 4420 EHCI_SITD_SET_CMASK(sb) 4421 ); 4422 4423 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4424 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4425 } /* End of frame */ 4426 4427 sitd = exfer->ex_sitdend; 4428 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4429 4430 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4431 sizeof(sitd->sitd.sitd_trans), 4432 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4433 4434 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4435 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4436 4437 /* 4438 * Part 2: Transfer descriptors have now been set up, now they must 4439 * be scheduled into the periodic frame list. Erk. Not wanting to 4440 * complicate matters, transfer is denied if the transfer spans 4441 * more than the period frame list. 4442 */ 4443 4444 mutex_enter(&sc->sc_lock); 4445 4446 /* Start inserting frames */ 4447 if (epipe->isoc.cur_xfers > 0) { 4448 frindex = epipe->isoc.next_frame; 4449 } else { 4450 frindex = EOREAD4(sc, EHCI_FRINDEX); 4451 frindex = frindex >> 3; /* Erase microframe index */ 4452 frindex += 2; 4453 } 4454 4455 if (frindex >= sc->sc_flsize) 4456 frindex &= (sc->sc_flsize - 1); 4457 4458 /* Whats the frame interval? */ 4459 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4460 4461 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4462 j++, sitd = sitd->xfer_next) { 4463 KASSERT(sitd); 4464 4465 usb_syncmem(&sc->sc_fldma, 4466 sizeof(ehci_link_t) * frindex, 4467 sizeof(ehci_link_t), 4468 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4469 4470 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4471 if (sitd->sitd.sitd_next == 0) 4472 /* 4473 * FIXME: frindex table gets initialized to NULL 4474 * or EHCI_NULL? 4475 */ 4476 sitd->sitd.sitd_next = EHCI_NULL; 4477 4478 usb_syncmem(&sitd->dma, 4479 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4480 sizeof(ehci_sitd_t), 4481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4482 4483 sc->sc_flist[frindex] = 4484 htole32(EHCI_LINK_SITD | sitd->physaddr); 4485 4486 usb_syncmem(&sc->sc_fldma, 4487 sizeof(ehci_link_t) * frindex, 4488 sizeof(ehci_link_t), 4489 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4490 4491 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4492 sc->sc_softsitds[frindex] = sitd; 4493 if (sitd->frame_list.next != NULL) 4494 sitd->frame_list.next->frame_list.prev = sitd; 4495 sitd->slot = frindex; 4496 sitd->frame_list.prev = NULL; 4497 4498 frindex += i; 4499 if (frindex >= sc->sc_flsize) 4500 frindex -= sc->sc_flsize; 4501 } 4502 4503 epipe->isoc.cur_xfers++; 4504 epipe->isoc.next_frame = frindex; 4505 4506 ehci_add_intr_list(sc, exfer); 4507 xfer->ux_status = USBD_IN_PROGRESS; 4508 4509 mutex_exit(&sc->sc_lock); 4510 4511 if (sc->sc_bus.ub_usepolling) { 4512 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4513 ehci_waitintr(sc, xfer); 4514 } 4515 4516 return USBD_IN_PROGRESS; 4517 } 4518 4519 Static void 4520 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4521 { 4522 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4523 4524 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4525 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4526 } 4527 4528 Static void 4529 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4530 { 4531 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4532 4533 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4534 } 4535 4536 Static void 4537 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4538 { 4539 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4540 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4541 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4542 4543 KASSERT(mutex_owned(&sc->sc_lock)); 4544 4545 epipe->isoc.cur_xfers--; 4546 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4547 4548 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4549 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4550 } 4551 4552 4553 /************************/ 4554 4555 4556 Static int 4557 ehci_device_isoc_init(struct usbd_xfer *xfer) 4558 { 4559 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4560 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4561 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4562 ehci_soft_itd_t *itd, *prev, *start, *stop; 4563 int i, j, k; 4564 int frames, ufrperframe; 4565 int err; 4566 4567 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4568 4569 start = NULL; 4570 prev = NULL; 4571 itd = NULL; 4572 4573 KASSERT(xfer->ux_nframes != 0); 4574 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4575 KASSERT(exfer->ex_isdone); 4576 4577 exfer->ex_type = EX_ISOC; 4578 4579 /* 4580 * Step 1: Allocate and initialize itds, how many do we need? 4581 * One per transfer if interval >= 8 microframes, less if we use 4582 * multiple microframes per frame. 4583 */ 4584 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4585 if (i > 16 || i == 0) { 4586 /* Spec page 271 says intervals > 16 are invalid */ 4587 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4588 return USBD_INVAL; 4589 } 4590 4591 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4592 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4593 4594 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4595 itd = ehci_alloc_itd(sc); 4596 if (itd == NULL) { 4597 err = ENOMEM; 4598 goto fail; 4599 } 4600 4601 if (prev != NULL) { 4602 /* Maybe not as it's updated by the scheduling? */ 4603 prev->itd.itd_next = 4604 htole32(itd->physaddr | EHCI_LINK_ITD); 4605 4606 prev->xfer_next = itd; 4607 } else { 4608 start = itd; 4609 } 4610 4611 /* 4612 * Other special values 4613 */ 4614 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4615 itd->itd.itd_bufr[0] = htole32( 4616 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4617 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4618 4619 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4620 ? 1 : 0; 4621 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4622 itd->itd.itd_bufr[1] |= htole32( 4623 EHCI_ITD_SET_DIR(k) | 4624 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4625 4626 /* FIXME: handle invalid trans - should be done in openpipe */ 4627 itd->itd.itd_bufr[2] |= 4628 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4629 } /* End of frame */ 4630 4631 stop = itd; 4632 stop->xfer_next = NULL; 4633 4634 exfer->ex_itdstart = start; 4635 exfer->ex_itdend = stop; 4636 4637 return 0; 4638 fail: 4639 mutex_enter(&sc->sc_lock); 4640 ehci_soft_itd_t *next; 4641 for (itd = start; itd; itd = next) { 4642 next = itd->xfer_next; 4643 ehci_free_itd_locked(sc, itd); 4644 } 4645 mutex_exit(&sc->sc_lock); 4646 4647 return err; 4648 4649 } 4650 4651 Static void 4652 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4653 { 4654 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4655 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4656 4657 KASSERT(ex->ex_type == EX_ISOC); 4658 4659 ehci_free_itd_chain(sc, ex->ex_itdstart); 4660 } 4661 4662 Static usbd_status 4663 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4664 { 4665 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4666 usbd_status __diagused err; 4667 4668 mutex_enter(&sc->sc_lock); 4669 err = usb_insert_transfer(xfer); 4670 mutex_exit(&sc->sc_lock); 4671 4672 KASSERT(err == USBD_NORMAL_COMPLETION); 4673 4674 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4675 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4676 ehci_soft_itd_t *itd, *prev; 4677 usb_dma_t *dma_buf; 4678 int i, j; 4679 int frames, uframes, ufrperframe; 4680 int trans_count, offs, total_length; 4681 int frindex; 4682 4683 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4684 4685 prev = NULL; 4686 itd = NULL; 4687 trans_count = 0; 4688 total_length = 0; 4689 4690 DPRINTF("xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4691 4692 if (sc->sc_dying) 4693 return USBD_IOERROR; 4694 4695 /* 4696 * To avoid complication, don't allow a request right now that'll span 4697 * the entire frame table. To within 4 frames, to allow some leeway 4698 * on either side of where the hc currently is. 4699 */ 4700 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4701 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4702 DPRINTF( 4703 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4704 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4705 return USBD_INVAL; 4706 } 4707 4708 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4709 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4710 KASSERT(exfer->ex_isdone); 4711 #ifdef DIAGNOSTIC 4712 exfer->ex_isdone = false; 4713 #endif 4714 4715 /* 4716 * Step 1: Re-Initialize itds 4717 */ 4718 4719 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4720 if (i > 16 || i == 0) { 4721 /* Spec page 271 says intervals > 16 are invalid */ 4722 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4723 return USBD_INVAL; 4724 } 4725 4726 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4727 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4728 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4729 4730 if (frames == 0) { 4731 DPRINTF("frames == 0", 0, 0, 0, 0); 4732 return USBD_INVAL; 4733 } 4734 4735 dma_buf = &xfer->ux_dmabuf; 4736 offs = 0; 4737 4738 itd = exfer->ex_itdstart; 4739 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4740 int froffs = offs; 4741 4742 if (prev != NULL) { 4743 prev->itd.itd_next = 4744 htole32(itd->physaddr | EHCI_LINK_ITD); 4745 usb_syncmem(&prev->dma, 4746 prev->offs + offsetof(ehci_itd_t, itd_next), 4747 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4748 prev->xfer_next = itd; 4749 } 4750 4751 /* 4752 * Step 1.5, initialize uframes 4753 */ 4754 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4755 /* Calculate which page in the list this starts in */ 4756 int addr = DMAADDR(dma_buf, froffs); 4757 addr = EHCI_PAGE_OFFSET(addr); 4758 addr += (offs - froffs); 4759 addr = EHCI_PAGE(addr); 4760 addr /= EHCI_PAGE_SIZE; 4761 4762 /* 4763 * This gets the initial offset into the first page, 4764 * looks how far further along the current uframe 4765 * offset is. Works out how many pages that is. 4766 */ 4767 4768 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4769 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4770 EHCI_ITD_SET_PG(addr) | 4771 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4772 4773 total_length += xfer->ux_frlengths[trans_count]; 4774 offs += xfer->ux_frlengths[trans_count]; 4775 trans_count++; 4776 4777 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4778 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4779 break; 4780 } 4781 } 4782 4783 /* 4784 * Step 1.75, set buffer pointers. To simplify matters, all 4785 * pointers are filled out for the next 7 hardware pages in 4786 * the dma block, so no need to worry what pages to cover 4787 * and what to not. 4788 */ 4789 4790 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4791 /* 4792 * Don't try to lookup a page that's past the end 4793 * of buffer 4794 */ 4795 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4796 if (page_offs >= dma_buf->udma_block->size) 4797 break; 4798 4799 uint64_t page = DMAADDR(dma_buf, page_offs); 4800 page = EHCI_PAGE(page); 4801 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4802 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4803 } 4804 /* 4805 * Other special values 4806 */ 4807 4808 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4809 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4810 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4811 4812 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4813 ? 1 : 0; 4814 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4815 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4816 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4817 4818 /* FIXME: handle invalid trans */ 4819 itd->itd.itd_bufr[2] |= 4820 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4821 4822 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4823 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4824 4825 prev = itd; 4826 } /* End of frame */ 4827 4828 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4829 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4830 4831 /* 4832 * Part 2: Transfer descriptors have now been set up, now they must 4833 * be scheduled into the period frame list. Erk. Not wanting to 4834 * complicate matters, transfer is denied if the transfer spans 4835 * more than the period frame list. 4836 */ 4837 4838 mutex_enter(&sc->sc_lock); 4839 4840 /* Start inserting frames */ 4841 if (epipe->isoc.cur_xfers > 0) { 4842 frindex = epipe->isoc.next_frame; 4843 } else { 4844 frindex = EOREAD4(sc, EHCI_FRINDEX); 4845 frindex = frindex >> 3; /* Erase microframe index */ 4846 frindex += 2; 4847 } 4848 4849 if (frindex >= sc->sc_flsize) 4850 frindex &= (sc->sc_flsize - 1); 4851 4852 /* What's the frame interval? */ 4853 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4854 if (i / USB_UFRAMES_PER_FRAME == 0) 4855 i = 1; 4856 else 4857 i /= USB_UFRAMES_PER_FRAME; 4858 4859 itd = exfer->ex_itdstart; 4860 for (j = 0; j < frames; j++) { 4861 KASSERTMSG(itd != NULL, "frame %d\n", j); 4862 4863 usb_syncmem(&sc->sc_fldma, 4864 sizeof(ehci_link_t) * frindex, 4865 sizeof(ehci_link_t), 4866 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4867 4868 itd->itd.itd_next = sc->sc_flist[frindex]; 4869 if (itd->itd.itd_next == 0) 4870 /* 4871 * FIXME: frindex table gets initialized to NULL 4872 * or EHCI_NULL? 4873 */ 4874 itd->itd.itd_next = EHCI_NULL; 4875 4876 usb_syncmem(&itd->dma, 4877 itd->offs + offsetof(ehci_itd_t, itd_next), 4878 sizeof(itd->itd.itd_next), 4879 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4880 4881 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4882 4883 usb_syncmem(&sc->sc_fldma, 4884 sizeof(ehci_link_t) * frindex, 4885 sizeof(ehci_link_t), 4886 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4887 4888 itd->frame_list.next = sc->sc_softitds[frindex]; 4889 sc->sc_softitds[frindex] = itd; 4890 if (itd->frame_list.next != NULL) 4891 itd->frame_list.next->frame_list.prev = itd; 4892 itd->slot = frindex; 4893 itd->frame_list.prev = NULL; 4894 4895 frindex += i; 4896 if (frindex >= sc->sc_flsize) 4897 frindex -= sc->sc_flsize; 4898 4899 itd = itd->xfer_next; 4900 } 4901 4902 epipe->isoc.cur_xfers++; 4903 epipe->isoc.next_frame = frindex; 4904 4905 ehci_add_intr_list(sc, exfer); 4906 xfer->ux_status = USBD_IN_PROGRESS; 4907 4908 mutex_exit(&sc->sc_lock); 4909 4910 if (sc->sc_bus.ub_usepolling) { 4911 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4912 ehci_waitintr(sc, xfer); 4913 } 4914 4915 return USBD_IN_PROGRESS; 4916 } 4917 4918 Static void 4919 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4920 { 4921 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4922 4923 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4924 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4925 } 4926 4927 Static void 4928 ehci_device_isoc_close(struct usbd_pipe *pipe) 4929 { 4930 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4931 4932 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4933 } 4934 4935 Static void 4936 ehci_device_isoc_done(struct usbd_xfer *xfer) 4937 { 4938 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4939 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4940 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4941 4942 KASSERT(mutex_owned(&sc->sc_lock)); 4943 4944 epipe->isoc.cur_xfers--; 4945 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4946 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4947 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4948 } 4949
Indexes created Thu Oct 02 01:09:59 GMT 2025