ehci.c revision 1.234.2.97
1 /* $NetBSD: ehci.c,v 1.234.2.97 2016/04/16 14:01:43 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.97 2016/04/16 14:01:43 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_timeout(void *); 171 Static void ehci_timeout_task(void *); 172 Static void ehci_intrlist_timeout(void *); 173 Static void ehci_doorbell(void *); 174 Static void ehci_pcd(void *); 175 176 Static struct usbd_xfer * 177 ehci_allocx(struct usbd_bus *, unsigned int); 178 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 179 180 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 181 Static int ehci_roothub_ctrl(struct usbd_bus *, 182 usb_device_request_t *, void *, int); 183 184 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 185 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 186 Static void ehci_root_intr_abort(struct usbd_xfer *); 187 Static void ehci_root_intr_close(struct usbd_pipe *); 188 Static void ehci_root_intr_done(struct usbd_xfer *); 189 190 Static int ehci_device_ctrl_init(struct usbd_xfer *); 191 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 193 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 194 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 195 Static void ehci_device_ctrl_close(struct usbd_pipe *); 196 Static void ehci_device_ctrl_done(struct usbd_xfer *); 197 198 Static int ehci_device_bulk_init(struct usbd_xfer *); 199 Static void ehci_device_bulk_fini(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 201 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 202 Static void ehci_device_bulk_abort(struct usbd_xfer *); 203 Static void ehci_device_bulk_close(struct usbd_pipe *); 204 Static void ehci_device_bulk_done(struct usbd_xfer *); 205 206 Static int ehci_device_intr_init(struct usbd_xfer *); 207 Static void ehci_device_intr_fini(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 209 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 210 Static void ehci_device_intr_abort(struct usbd_xfer *); 211 Static void ehci_device_intr_close(struct usbd_pipe *); 212 Static void ehci_device_intr_done(struct usbd_xfer *); 213 214 Static int ehci_device_isoc_init(struct usbd_xfer *); 215 Static void ehci_device_isoc_fini(struct usbd_xfer *); 216 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 217 Static void ehci_device_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_isoc_done(struct usbd_xfer *); 220 221 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 223 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 225 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 226 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 227 228 Static void ehci_device_clear_toggle(struct usbd_pipe *); 229 Static void ehci_noop(struct usbd_pipe *); 230 231 Static void ehci_disown(ehci_softc_t *, int, int); 232 233 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 234 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 235 236 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 237 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 238 Static usbd_status ehci_alloc_sqtd_chain(ehci_softc_t *, 239 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 240 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 241 242 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 243 int, int, int *, ehci_soft_qtd_t **); 244 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 245 246 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 247 Static ehci_soft_sitd_t * 248 ehci_alloc_sitd(ehci_softc_t *); 249 250 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 251 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 252 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 253 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 254 255 static inline void 256 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 257 { 258 259 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 260 } 261 262 static inline void 263 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 264 { 265 266 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 267 } 268 269 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 270 271 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 272 int); 273 274 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 275 ehci_soft_qh_t *); 276 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 277 ehci_soft_qh_t *); 278 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 279 Static void ehci_sync_hc(ehci_softc_t *); 280 281 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 282 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 283 284 #ifdef EHCI_DEBUG 285 Static ehci_softc_t *theehci; 286 void ehci_dump(void); 287 #endif 288 289 #ifdef EHCI_DEBUG 290 Static void ehci_dump_regs(ehci_softc_t *); 291 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 292 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 293 Static void ehci_dump_qtd(ehci_qtd_t *); 294 Static void ehci_dump_sqh(ehci_soft_qh_t *); 295 Static void ehci_dump_sitd(struct ehci_soft_itd *); 296 Static void ehci_dump_itds(ehci_soft_itd_t *); 297 Static void ehci_dump_itd(struct ehci_soft_itd *); 298 Static void ehci_dump_exfer(struct ehci_xfer *); 299 #endif 300 301 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 302 303 static inline void 304 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 305 { 306 307 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 308 } 309 310 static inline void 311 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 312 { 313 314 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 315 } 316 317 Static const struct usbd_bus_methods ehci_bus_methods = { 318 .ubm_open = ehci_open, 319 .ubm_softint = ehci_softintr, 320 .ubm_dopoll = ehci_poll, 321 .ubm_allocx = ehci_allocx, 322 .ubm_freex = ehci_freex, 323 .ubm_getlock = ehci_get_lock, 324 .ubm_rhctrl = ehci_roothub_ctrl, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 328 .upm_transfer = ehci_root_intr_transfer, 329 .upm_start = ehci_root_intr_start, 330 .upm_abort = ehci_root_intr_abort, 331 .upm_close = ehci_root_intr_close, 332 .upm_cleartoggle = ehci_noop, 333 .upm_done = ehci_root_intr_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 337 .upm_init = ehci_device_ctrl_init, 338 .upm_fini = ehci_device_ctrl_fini, 339 .upm_transfer = ehci_device_ctrl_transfer, 340 .upm_start = ehci_device_ctrl_start, 341 .upm_abort = ehci_device_ctrl_abort, 342 .upm_close = ehci_device_ctrl_close, 343 .upm_cleartoggle = ehci_noop, 344 .upm_done = ehci_device_ctrl_done, 345 }; 346 347 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 348 .upm_init = ehci_device_intr_init, 349 .upm_fini = ehci_device_intr_fini, 350 .upm_transfer = ehci_device_intr_transfer, 351 .upm_start = ehci_device_intr_start, 352 .upm_abort = ehci_device_intr_abort, 353 .upm_close = ehci_device_intr_close, 354 .upm_cleartoggle = ehci_device_clear_toggle, 355 .upm_done = ehci_device_intr_done, 356 }; 357 358 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 359 .upm_init = ehci_device_bulk_init, 360 .upm_fini = ehci_device_bulk_fini, 361 .upm_transfer = ehci_device_bulk_transfer, 362 .upm_start = ehci_device_bulk_start, 363 .upm_abort = ehci_device_bulk_abort, 364 .upm_close = ehci_device_bulk_close, 365 .upm_cleartoggle = ehci_device_clear_toggle, 366 .upm_done = ehci_device_bulk_done, 367 }; 368 369 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 370 .upm_init = ehci_device_isoc_init, 371 .upm_fini = ehci_device_isoc_fini, 372 .upm_transfer = ehci_device_isoc_transfer, 373 .upm_abort = ehci_device_isoc_abort, 374 .upm_close = ehci_device_isoc_close, 375 .upm_cleartoggle = ehci_noop, 376 .upm_done = ehci_device_isoc_done, 377 }; 378 379 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 380 .upm_init = ehci_device_fs_isoc_init, 381 .upm_fini = ehci_device_fs_isoc_fini, 382 .upm_transfer = ehci_device_fs_isoc_transfer, 383 .upm_abort = ehci_device_fs_isoc_abort, 384 .upm_close = ehci_device_fs_isoc_close, 385 .upm_cleartoggle = ehci_noop, 386 .upm_done = ehci_device_fs_isoc_done, 387 }; 388 389 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 390 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 391 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 392 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 393 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 394 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 395 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 396 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 397 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 398 }; 399 400 int 401 ehci_init(ehci_softc_t *sc) 402 { 403 uint32_t vers, sparams, cparams, hcr; 404 u_int i; 405 usbd_status err; 406 ehci_soft_qh_t *sqh; 407 u_int ncomp; 408 409 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 410 #ifdef EHCI_DEBUG 411 theehci = sc; 412 #endif 413 414 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 415 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 416 cv_init(&sc->sc_softwake_cv, "ehciab"); 417 cv_init(&sc->sc_doorbell, "ehcidi"); 418 419 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 420 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 421 422 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 423 ehci_doorbell, sc); 424 KASSERT(sc->sc_doorbell_si != NULL); 425 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 426 ehci_pcd, sc); 427 KASSERT(sc->sc_pcd_si != NULL); 428 429 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 430 431 vers = EREAD2(sc, EHCI_HCIVERSION); 432 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 433 vers >> 8, vers & 0xff); 434 435 sparams = EREAD4(sc, EHCI_HCSPARAMS); 436 DPRINTF("sparams=%#x", sparams, 0, 0, 0); 437 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 438 ncomp = EHCI_HCS_N_CC(sparams); 439 if (ncomp != sc->sc_ncomp) { 440 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 441 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 442 #if NOHCI == 0 || NUHCI == 0 443 aprint_error("%s: ohci or uhci probably not configured\n", 444 device_xname(sc->sc_dev)); 445 #endif 446 if (ncomp < sc->sc_ncomp) 447 sc->sc_ncomp = ncomp; 448 } 449 if (sc->sc_ncomp > 0) { 450 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 451 aprint_normal("%s: companion controller%s, %d port%s each:", 452 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 453 EHCI_HCS_N_PCC(sparams), 454 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 455 for (i = 0; i < sc->sc_ncomp; i++) 456 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 457 aprint_normal("\n"); 458 } 459 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 460 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 461 462 cparams = EREAD4(sc, EHCI_HCCPARAMS); 463 DPRINTF("cparams=%#x", cparams, 0, 0, 0); 464 465 if (EHCI_HCC_64BIT(cparams)) { 466 /* MUST clear segment register if 64 bit capable. */ 467 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 468 } 469 470 if (cparams & EHCI_HCC_IST_FULLFRAME) { 471 sc->sc_istthreshold = 0; 472 } else { 473 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 474 } 475 476 sc->sc_bus.ub_revision = USBREV_2_0; 477 sc->sc_bus.ub_usedma = true; 478 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 479 480 /* Reset the controller */ 481 DPRINTF("resetting", 0, 0, 0, 0); 482 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 483 usb_delay_ms(&sc->sc_bus, 1); 484 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 485 for (i = 0; i < 100; i++) { 486 usb_delay_ms(&sc->sc_bus, 1); 487 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 488 if (!hcr) 489 break; 490 } 491 if (hcr) { 492 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 493 return EIO; 494 } 495 if (sc->sc_vendor_init) 496 sc->sc_vendor_init(sc); 497 498 /* XXX need proper intr scheduling */ 499 sc->sc_rand = 96; 500 501 /* frame list size at default, read back what we got and use that */ 502 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 503 case 0: sc->sc_flsize = 1024; break; 504 case 1: sc->sc_flsize = 512; break; 505 case 2: sc->sc_flsize = 256; break; 506 case 3: return EIO; 507 } 508 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 509 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 510 if (err) 511 return err; 512 DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); 513 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 514 515 for (i = 0; i < sc->sc_flsize; i++) { 516 sc->sc_flist[i] = EHCI_NULL; 517 } 518 519 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 520 521 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 522 KM_SLEEP); 523 if (sc->sc_softitds == NULL) 524 return ENOMEM; 525 LIST_INIT(&sc->sc_freeitds); 526 LIST_INIT(&sc->sc_freesitds); 527 TAILQ_INIT(&sc->sc_intrhead); 528 529 /* Set up the bus struct. */ 530 sc->sc_bus.ub_methods = &ehci_bus_methods; 531 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 532 533 sc->sc_eintrs = EHCI_NORMAL_INTRS; 534 535 /* 536 * Allocate the interrupt dummy QHs. These are arranged to give poll 537 * intervals that are powers of 2 times 1ms. 538 */ 539 for (i = 0; i < EHCI_INTRQHS; i++) { 540 sqh = ehci_alloc_sqh(sc); 541 if (sqh == NULL) { 542 err = ENOMEM; 543 goto bad1; 544 } 545 sc->sc_islots[i].sqh = sqh; 546 } 547 for (i = 0; i < EHCI_INTRQHS; i++) { 548 sqh = sc->sc_islots[i].sqh; 549 if (i == 0) { 550 /* The last (1ms) QH terminates. */ 551 sqh->qh.qh_link = EHCI_NULL; 552 sqh->next = NULL; 553 } else { 554 /* Otherwise the next QH has half the poll interval */ 555 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 556 sqh->qh.qh_link = htole32(sqh->next->physaddr | 557 EHCI_LINK_QH); 558 } 559 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 560 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 561 sqh->qh.qh_curqtd = EHCI_NULL; 562 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 563 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 564 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 565 sqh->sqtd = NULL; 566 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 567 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 568 } 569 /* Point the frame list at the last level (128ms). */ 570 for (i = 0; i < sc->sc_flsize; i++) { 571 int j; 572 573 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 574 revbits[i & (EHCI_MAX_POLLRATE-1)]; 575 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 576 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 577 i)].sqh->physaddr); 578 } 579 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 580 BUS_DMASYNC_PREWRITE); 581 582 /* Allocate dummy QH that starts the async list. */ 583 sqh = ehci_alloc_sqh(sc); 584 if (sqh == NULL) { 585 err = ENOMEM; 586 goto bad1; 587 } 588 /* Fill the QH */ 589 sqh->qh.qh_endp = 590 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 591 sqh->qh.qh_link = 592 htole32(sqh->physaddr | EHCI_LINK_QH); 593 sqh->qh.qh_curqtd = EHCI_NULL; 594 sqh->next = NULL; 595 /* Fill the overlay qTD */ 596 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 597 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 598 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 599 sqh->sqtd = NULL; 600 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 601 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 602 #ifdef EHCI_DEBUG 603 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 604 ehci_dump_sqh(sqh); 605 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 606 #endif 607 608 /* Point to async list */ 609 sc->sc_async_head = sqh; 610 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 611 612 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 613 614 /* Turn on controller */ 615 EOWRITE4(sc, EHCI_USBCMD, 616 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 617 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 618 EHCI_CMD_ASE | 619 EHCI_CMD_PSE | 620 EHCI_CMD_RS); 621 622 /* Take over port ownership */ 623 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 624 625 for (i = 0; i < 100; i++) { 626 usb_delay_ms(&sc->sc_bus, 1); 627 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 628 if (!hcr) 629 break; 630 } 631 if (hcr) { 632 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 633 return EIO; 634 } 635 636 /* Enable interrupts */ 637 DPRINTF("enabling interupts", 0, 0, 0, 0); 638 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 639 640 return 0; 641 642 #if 0 643 bad2: 644 ehci_free_sqh(sc, sc->sc_async_head); 645 #endif 646 bad1: 647 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 648 return err; 649 } 650 651 int 652 ehci_intr(void *v) 653 { 654 ehci_softc_t *sc = v; 655 int ret = 0; 656 657 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 658 659 if (sc == NULL) 660 return 0; 661 662 mutex_spin_enter(&sc->sc_intr_lock); 663 664 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 665 goto done; 666 667 /* If we get an interrupt while polling, then just ignore it. */ 668 if (sc->sc_bus.ub_usepolling) { 669 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 670 671 if (intrs) 672 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 673 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 674 goto done; 675 } 676 677 ret = ehci_intr1(sc); 678 679 done: 680 mutex_spin_exit(&sc->sc_intr_lock); 681 return ret; 682 } 683 684 Static int 685 ehci_intr1(ehci_softc_t *sc) 686 { 687 uint32_t intrs, eintrs; 688 689 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 690 691 /* In case the interrupt occurs before initialization has completed. */ 692 if (sc == NULL) { 693 #ifdef DIAGNOSTIC 694 printf("ehci_intr1: sc == NULL\n"); 695 #endif 696 return 0; 697 } 698 699 KASSERT(mutex_owned(&sc->sc_intr_lock)); 700 701 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 702 if (!intrs) 703 return 0; 704 705 eintrs = intrs & sc->sc_eintrs; 706 DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, 707 EOREAD4(sc, EHCI_USBSTS), eintrs); 708 if (!eintrs) 709 return 0; 710 711 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 712 if (eintrs & EHCI_STS_IAA) { 713 DPRINTF("door bell", 0, 0, 0, 0); 714 kpreempt_disable(); 715 KASSERT(sc->sc_doorbell_si != NULL); 716 softint_schedule(sc->sc_doorbell_si); 717 kpreempt_enable(); 718 eintrs &= ~EHCI_STS_IAA; 719 } 720 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 721 DPRINTF("INT=%d ERRINT=%d", 722 eintrs & EHCI_STS_INT ? 1 : 0, 723 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 724 usb_schedsoftintr(&sc->sc_bus); 725 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 726 } 727 if (eintrs & EHCI_STS_HSE) { 728 printf("%s: unrecoverable error, controller halted\n", 729 device_xname(sc->sc_dev)); 730 /* XXX what else */ 731 } 732 if (eintrs & EHCI_STS_PCD) { 733 kpreempt_disable(); 734 KASSERT(sc->sc_pcd_si != NULL); 735 softint_schedule(sc->sc_pcd_si); 736 kpreempt_enable(); 737 eintrs &= ~EHCI_STS_PCD; 738 } 739 740 if (eintrs != 0) { 741 /* Block unprocessed interrupts. */ 742 sc->sc_eintrs &= ~eintrs; 743 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 744 printf("%s: blocking intrs 0x%x\n", 745 device_xname(sc->sc_dev), eintrs); 746 } 747 748 return 1; 749 } 750 751 Static void 752 ehci_doorbell(void *addr) 753 { 754 ehci_softc_t *sc = addr; 755 756 mutex_enter(&sc->sc_lock); 757 cv_broadcast(&sc->sc_doorbell); 758 mutex_exit(&sc->sc_lock); 759 } 760 761 Static void 762 ehci_pcd(void *addr) 763 { 764 ehci_softc_t *sc = addr; 765 struct usbd_xfer *xfer; 766 u_char *p; 767 int i, m; 768 769 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 770 771 mutex_enter(&sc->sc_lock); 772 xfer = sc->sc_intrxfer; 773 774 if (xfer == NULL) { 775 /* Just ignore the change. */ 776 goto done; 777 } 778 779 p = xfer->ux_buf; 780 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 781 memset(p, 0, xfer->ux_length); 782 for (i = 1; i <= m; i++) { 783 /* Pick out CHANGE bits from the status reg. */ 784 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 785 p[i/8] |= 1 << (i%8); 786 if (i % 8 == 7) 787 DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); 788 } 789 xfer->ux_actlen = xfer->ux_length; 790 xfer->ux_status = USBD_NORMAL_COMPLETION; 791 792 usb_transfer_complete(xfer); 793 794 done: 795 mutex_exit(&sc->sc_lock); 796 } 797 798 Static void 799 ehci_softintr(void *v) 800 { 801 struct usbd_bus *bus = v; 802 ehci_softc_t *sc = EHCI_BUS2SC(bus); 803 struct ehci_xfer *ex, *nextex; 804 805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 806 807 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 808 809 ex_completeq_t cq; 810 TAILQ_INIT(&cq); 811 812 /* 813 * The only explanation I can think of for why EHCI is as brain dead 814 * as UHCI interrupt-wise is that Intel was involved in both. 815 * An interrupt just tells us that something is done, we have no 816 * clue what, so we need to scan through all active transfers. :-( 817 */ 818 819 /* 820 * ehci_idone will remove transfer from sc->sc_intrhead if it's 821 * complete and add to our cq list 822 * */ 823 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 824 switch (ex->ex_type) { 825 case EX_CTRL: 826 case EX_BULK: 827 case EX_INTR: 828 ehci_check_qh_intr(sc, ex, &cq); 829 break; 830 case EX_ISOC: 831 ehci_check_itd_intr(sc, ex, &cq); 832 break; 833 case EX_FS_ISOC: 834 ehci_check_sitd_intr(sc, ex, &cq); 835 break; 836 default: 837 KASSERT(false); 838 } 839 840 } 841 842 /* 843 * We abuse ex_next for the interrupt and complete lists and 844 * interrupt transfers will get re-added here so use 845 * the _SAFE version of TAILQ_FOREACH. 846 */ 847 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 848 usb_transfer_complete(&ex->ex_xfer); 849 } 850 851 /* Schedule a callout to catch any dropped transactions. */ 852 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 853 !TAILQ_EMPTY(&sc->sc_intrhead)) 854 callout_reset(&sc->sc_tmo_intrlist, 855 hz, ehci_intrlist_timeout, sc); 856 857 if (sc->sc_softwake) { 858 sc->sc_softwake = 0; 859 cv_broadcast(&sc->sc_softwake_cv); 860 } 861 } 862 863 Static void 864 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 865 { 866 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 867 uint32_t status; 868 869 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 870 871 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 872 873 if (ex->ex_type == EX_CTRL) { 874 fsqtd = ex->ex_setup; 875 lsqtd = ex->ex_status; 876 } else { 877 fsqtd = ex->ex_sqtdstart; 878 lsqtd = ex->ex_sqtdend; 879 } 880 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 881 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 882 883 /* 884 * If the last TD is still active we need to check whether there 885 * is an error somewhere in the middle, or whether there was a 886 * short packet (SPD and not ACTIVE). 887 */ 888 usb_syncmem(&lsqtd->dma, 889 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 890 sizeof(lsqtd->qtd.qtd_status), 891 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 892 status = le32toh(lsqtd->qtd.qtd_status); 893 usb_syncmem(&lsqtd->dma, 894 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 895 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 896 if (status & EHCI_QTD_ACTIVE) { 897 DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); 898 899 /* last qTD has already been checked */ 900 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 901 usb_syncmem(&sqtd->dma, 902 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 903 sizeof(sqtd->qtd.qtd_status), 904 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 905 status = le32toh(sqtd->qtd.qtd_status); 906 usb_syncmem(&sqtd->dma, 907 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 908 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 909 /* If there's an active QTD the xfer isn't done. */ 910 if (status & EHCI_QTD_ACTIVE) 911 break; 912 /* Any kind of error makes the xfer done. */ 913 if (status & EHCI_QTD_HALTED) 914 goto done; 915 /* Handle short packets */ 916 if (EHCI_QTD_GET_BYTES(status) != 0) { 917 /* 918 * If we get here for a control transfer then 919 * we need to let the hardware complete the 920 * status phase. That is, we're not done 921 * quite yet. 922 * 923 * Otherwise, we're done. 924 */ 925 if (ex->ex_type == EX_CTRL) { 926 break; 927 } 928 goto done; 929 } 930 } 931 DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, 932 0, 0); 933 #ifdef EHCI_DEBUG 934 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 935 ehci_dump_sqtds(ex->ex_sqtdstart); 936 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 937 #endif 938 return; 939 } 940 done: 941 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 942 callout_stop(&ex->ex_xfer.ux_callout); 943 ehci_idone(ex, cq); 944 } 945 946 Static void 947 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 948 { 949 ehci_soft_itd_t *itd; 950 int i; 951 952 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 953 954 KASSERT(mutex_owned(&sc->sc_lock)); 955 956 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 957 return; 958 959 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 960 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 961 962 itd = ex->ex_itdend; 963 964 /* 965 * check no active transfers in last itd, meaning we're finished 966 */ 967 968 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 969 sizeof(itd->itd.itd_ctl), 970 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 971 972 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 973 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 974 break; 975 } 976 977 if (i == EHCI_ITD_NUFRAMES) { 978 goto done; /* All 8 descriptors inactive, it's done */ 979 } 980 981 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 982 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 983 984 DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); 985 return; 986 done: 987 DPRINTF("ex %p done", ex, 0, 0, 0); 988 callout_stop(&ex->ex_xfer.ux_callout); 989 ehci_idone(ex, cq); 990 } 991 992 void 993 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 994 { 995 ehci_soft_sitd_t *sitd; 996 997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 998 999 KASSERT(mutex_owned(&sc->sc_lock)); 1000 1001 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1002 return; 1003 1004 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1005 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1006 1007 sitd = ex->ex_sitdend; 1008 1009 /* 1010 * check no active transfers in last sitd, meaning we're finished 1011 */ 1012 1013 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1014 sizeof(sitd->sitd.sitd_trans), 1015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1016 1017 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1021 1022 if (active) 1023 return; 1024 1025 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 1026 callout_stop(&(ex->ex_xfer.ux_callout)); 1027 ehci_idone(ex, cq); 1028 } 1029 1030 1031 Static void 1032 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1033 { 1034 struct usbd_xfer *xfer = &ex->ex_xfer; 1035 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1036 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1037 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1038 uint32_t status = 0, nstatus = 0; 1039 int actlen = 0; 1040 1041 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1042 1043 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1044 1045 DPRINTF("ex=%p", ex, 0, 0, 0); 1046 1047 if (xfer->ux_status == USBD_CANCELLED || 1048 xfer->ux_status == USBD_TIMEOUT) { 1049 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1050 return; 1051 } 1052 1053 #ifdef DIAGNOSTIC 1054 #ifdef EHCI_DEBUG 1055 if (ex->ex_isdone) { 1056 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1057 ehci_dump_exfer(ex); 1058 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1059 } 1060 #endif 1061 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1062 ex->ex_type, xfer->ux_status); 1063 ex->ex_isdone = true; 1064 #endif 1065 1066 DPRINTF("xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1067 1068 /* The transfer is done, compute actual length and status. */ 1069 if (ex->ex_type == EX_ISOC) { 1070 /* HS isoc transfer */ 1071 1072 struct ehci_soft_itd *itd; 1073 int i, nframes, len, uframes; 1074 1075 nframes = 0; 1076 1077 #ifdef EHCI_DEBUG 1078 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1079 ehci_dump_itds(ex->ex_itdstart); 1080 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1081 #endif 1082 1083 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1084 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1085 1086 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1087 usb_syncmem(&itd->dma, 1088 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1089 sizeof(itd->itd.itd_ctl), 1090 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1091 1092 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1093 /* 1094 * XXX - driver didn't fill in the frame full 1095 * of uframes. This leads to scheduling 1096 * inefficiencies, but working around 1097 * this doubles complexity of tracking 1098 * an xfer. 1099 */ 1100 if (nframes >= xfer->ux_nframes) 1101 break; 1102 1103 status = le32toh(itd->itd.itd_ctl[i]); 1104 len = EHCI_ITD_GET_LEN(status); 1105 if (EHCI_ITD_GET_STATUS(status) != 0) 1106 len = 0; /*No valid data on error*/ 1107 1108 xfer->ux_frlengths[nframes++] = len; 1109 actlen += len; 1110 } 1111 usb_syncmem(&itd->dma, 1112 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1113 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1114 1115 if (nframes >= xfer->ux_nframes) 1116 break; 1117 } 1118 1119 xfer->ux_actlen = actlen; 1120 xfer->ux_status = USBD_NORMAL_COMPLETION; 1121 goto end; 1122 } else if (ex->ex_type == EX_FS_ISOC) { 1123 /* FS isoc transfer */ 1124 struct ehci_soft_sitd *sitd; 1125 int nframes, len; 1126 1127 nframes = 0; 1128 1129 for (sitd = ex->ex_sitdstart; sitd != NULL; 1130 sitd = sitd->xfer_next) { 1131 usb_syncmem(&sitd->dma, 1132 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1133 sizeof(sitd->sitd.sitd_trans), 1134 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1135 1136 /* 1137 * XXX - driver didn't fill in the frame full 1138 * of uframes. This leads to scheduling 1139 * inefficiencies, but working around 1140 * this doubles complexity of tracking 1141 * an xfer. 1142 */ 1143 if (nframes >= xfer->ux_nframes) 1144 break; 1145 1146 status = le32toh(sitd->sitd.sitd_trans); 1147 usb_syncmem(&sitd->dma, 1148 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1149 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1150 1151 len = EHCI_SITD_GET_LEN(status); 1152 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1153 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1154 /* No valid data on error */ 1155 len = xfer->ux_frlengths[nframes]; 1156 } 1157 1158 /* 1159 * frlengths[i]: # of bytes to send 1160 * len: # of bytes host didn't send 1161 */ 1162 xfer->ux_frlengths[nframes] -= len; 1163 /* frlengths[i]: # of bytes host sent */ 1164 actlen += xfer->ux_frlengths[nframes++]; 1165 1166 if (nframes >= xfer->ux_nframes) 1167 break; 1168 } 1169 1170 xfer->ux_actlen = actlen; 1171 xfer->ux_status = USBD_NORMAL_COMPLETION; 1172 goto end; 1173 } 1174 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1175 ex->ex_type == EX_BULK); 1176 1177 /* Continue processing xfers using queue heads */ 1178 if (ex->ex_type == EX_CTRL) { 1179 fsqtd = ex->ex_setup; 1180 lsqtd = ex->ex_status; 1181 } else { 1182 fsqtd = ex->ex_sqtdstart; 1183 lsqtd = ex->ex_sqtdend; 1184 } 1185 #ifdef EHCI_DEBUG 1186 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1187 ehci_dump_sqtds(fsqtd); 1188 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1189 #endif 1190 1191 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1192 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1193 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1194 nstatus = le32toh(sqtd->qtd.qtd_status); 1195 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1196 BUS_DMASYNC_PREREAD); 1197 if (nstatus & EHCI_QTD_ACTIVE) 1198 break; 1199 1200 status = nstatus; 1201 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1202 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1203 } 1204 1205 /* 1206 * If there are left over TDs we need to update the toggle. 1207 * The default pipe doesn't need it since control transfers 1208 * start the toggle at 0 every time. 1209 * For a short transfer we need to update the toggle for the missing 1210 * packets within the qTD. 1211 */ 1212 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1213 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1214 DPRINTF("toggle update status=0x%08x nstatus=0x%08x", 1215 status, nstatus, 0, 0); 1216 #if 0 1217 ehci_dump_sqh(epipe->sqh); 1218 ehci_dump_sqtds(ex->ex_sqtdstart); 1219 #endif 1220 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1221 } 1222 1223 DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, 1224 status, 0); 1225 xfer->ux_actlen = actlen; 1226 if (status & EHCI_QTD_HALTED) { 1227 #ifdef EHCI_DEBUG 1228 DPRINTF("halted addr=%d endpt=0x%02x", 1229 xfer->ux_pipe->up_dev->ud_addr, 1230 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1231 0, 0); 1232 DPRINTF("cerr=%d pid=%d", 1233 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1234 0, 0); 1235 DPRINTF("active =%d halted=%d buferr=%d babble=%d", 1236 status & EHCI_QTD_ACTIVE ? 1 : 0, 1237 status & EHCI_QTD_HALTED ? 1 : 0, 1238 status & EHCI_QTD_BUFERR ? 1 : 0, 1239 status & EHCI_QTD_BABBLE ? 1 : 0); 1240 1241 DPRINTF("xacterr=%d missed=%d split =%d ping =%d", 1242 status & EHCI_QTD_XACTERR ? 1 : 0, 1243 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1244 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1245 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1246 1247 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1248 ehci_dump_sqh(epipe->sqh); 1249 ehci_dump_sqtds(ex->ex_sqtdstart); 1250 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1251 #endif 1252 /* low&full speed has an extra error flag */ 1253 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1254 EHCI_QH_SPEED_HIGH) 1255 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1256 else 1257 status &= EHCI_QTD_STATERRS; 1258 if (status == 0) /* no other errors means a stall */ { 1259 xfer->ux_status = USBD_STALLED; 1260 } else { 1261 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1262 } 1263 /* XXX need to reset TT on missed microframe */ 1264 if (status & EHCI_QTD_MISSEDMICRO) { 1265 printf("%s: missed microframe, TT reset not " 1266 "implemented, hub might be inoperational\n", 1267 device_xname(sc->sc_dev)); 1268 } 1269 } else { 1270 xfer->ux_status = USBD_NORMAL_COMPLETION; 1271 } 1272 1273 end: 1274 1275 ehci_del_intr_list(sc, ex); 1276 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1277 1278 DPRINTF("ex=%p done", ex, 0, 0, 0); 1279 } 1280 1281 /* 1282 * Wait here until controller claims to have an interrupt. 1283 * Then call ehci_intr and return. Use timeout to avoid waiting 1284 * too long. 1285 */ 1286 Static void 1287 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1288 { 1289 int timo; 1290 uint32_t intrs; 1291 1292 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1293 1294 xfer->ux_status = USBD_IN_PROGRESS; 1295 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1296 usb_delay_ms(&sc->sc_bus, 1); 1297 if (sc->sc_dying) 1298 break; 1299 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1300 sc->sc_eintrs; 1301 DPRINTF("0x%04x", intrs, 0, 0, 0); 1302 #ifdef EHCI_DEBUG 1303 if (ehcidebug >= 15) 1304 ehci_dump_regs(sc); 1305 #endif 1306 if (intrs) { 1307 mutex_spin_enter(&sc->sc_intr_lock); 1308 ehci_intr1(sc); 1309 mutex_spin_exit(&sc->sc_intr_lock); 1310 if (xfer->ux_status != USBD_IN_PROGRESS) 1311 return; 1312 } 1313 } 1314 1315 /* Timeout */ 1316 DPRINTF("timeout", 0, 0, 0, 0); 1317 xfer->ux_status = USBD_TIMEOUT; 1318 mutex_enter(&sc->sc_lock); 1319 usb_transfer_complete(xfer); 1320 mutex_exit(&sc->sc_lock); 1321 } 1322 1323 Static void 1324 ehci_poll(struct usbd_bus *bus) 1325 { 1326 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1327 1328 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1329 1330 #ifdef EHCI_DEBUG 1331 static int last; 1332 int new; 1333 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1334 if (new != last) { 1335 DPRINTF("intrs=0x%04x", new, 0, 0, 0); 1336 last = new; 1337 } 1338 #endif 1339 1340 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1341 mutex_spin_enter(&sc->sc_intr_lock); 1342 ehci_intr1(sc); 1343 mutex_spin_exit(&sc->sc_intr_lock); 1344 } 1345 } 1346 1347 void 1348 ehci_childdet(device_t self, device_t child) 1349 { 1350 struct ehci_softc *sc = device_private(self); 1351 1352 KASSERT(sc->sc_child == child); 1353 sc->sc_child = NULL; 1354 } 1355 1356 int 1357 ehci_detach(struct ehci_softc *sc, int flags) 1358 { 1359 int rv = 0; 1360 1361 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1362 1363 if (sc->sc_child != NULL) 1364 rv = config_detach(sc->sc_child, flags); 1365 1366 if (rv != 0) 1367 return rv; 1368 1369 callout_halt(&sc->sc_tmo_intrlist, NULL); 1370 callout_destroy(&sc->sc_tmo_intrlist); 1371 1372 /* XXX free other data structures XXX */ 1373 if (sc->sc_softitds) 1374 kmem_free(sc->sc_softitds, 1375 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1376 cv_destroy(&sc->sc_doorbell); 1377 cv_destroy(&sc->sc_softwake_cv); 1378 1379 #if 0 1380 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1381 1382 softint_disestablish(sc->sc_doorbell_si); 1383 softint_disestablish(sc->sc_pcd_si); 1384 1385 mutex_destroy(&sc->sc_lock); 1386 mutex_destroy(&sc->sc_intr_lock); 1387 #endif 1388 1389 pool_cache_destroy(sc->sc_xferpool); 1390 1391 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1392 1393 return rv; 1394 } 1395 1396 1397 int 1398 ehci_activate(device_t self, enum devact act) 1399 { 1400 struct ehci_softc *sc = device_private(self); 1401 1402 switch (act) { 1403 case DVACT_DEACTIVATE: 1404 sc->sc_dying = 1; 1405 return 0; 1406 default: 1407 return EOPNOTSUPP; 1408 } 1409 } 1410 1411 /* 1412 * Handle suspend/resume. 1413 * 1414 * We need to switch to polling mode here, because this routine is 1415 * called from an interrupt context. This is all right since we 1416 * are almost suspended anyway. 1417 * 1418 * Note that this power handler isn't to be registered directly; the 1419 * bus glue needs to call out to it. 1420 */ 1421 bool 1422 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1423 { 1424 ehci_softc_t *sc = device_private(dv); 1425 int i; 1426 uint32_t cmd, hcr; 1427 1428 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1429 1430 mutex_spin_enter(&sc->sc_intr_lock); 1431 sc->sc_bus.ub_usepolling++; 1432 mutex_spin_exit(&sc->sc_intr_lock); 1433 1434 for (i = 1; i <= sc->sc_noport; i++) { 1435 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1436 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1437 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1438 } 1439 1440 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1441 1442 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1443 EOWRITE4(sc, EHCI_USBCMD, cmd); 1444 1445 for (i = 0; i < 100; i++) { 1446 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1447 if (hcr == 0) 1448 break; 1449 1450 usb_delay_ms(&sc->sc_bus, 1); 1451 } 1452 if (hcr != 0) 1453 printf("%s: reset timeout\n", device_xname(dv)); 1454 1455 cmd &= ~EHCI_CMD_RS; 1456 EOWRITE4(sc, EHCI_USBCMD, cmd); 1457 1458 for (i = 0; i < 100; i++) { 1459 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1460 if (hcr == EHCI_STS_HCH) 1461 break; 1462 1463 usb_delay_ms(&sc->sc_bus, 1); 1464 } 1465 if (hcr != EHCI_STS_HCH) 1466 printf("%s: config timeout\n", device_xname(dv)); 1467 1468 mutex_spin_enter(&sc->sc_intr_lock); 1469 sc->sc_bus.ub_usepolling--; 1470 mutex_spin_exit(&sc->sc_intr_lock); 1471 1472 return true; 1473 } 1474 1475 bool 1476 ehci_resume(device_t dv, const pmf_qual_t *qual) 1477 { 1478 ehci_softc_t *sc = device_private(dv); 1479 int i; 1480 uint32_t cmd, hcr; 1481 1482 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1483 1484 /* restore things in case the bios sucks */ 1485 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1486 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1487 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1488 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1489 1490 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1491 1492 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1493 1494 hcr = 0; 1495 for (i = 1; i <= sc->sc_noport; i++) { 1496 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1497 if ((cmd & EHCI_PS_PO) == 0 && 1498 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1499 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1500 hcr = 1; 1501 } 1502 } 1503 1504 if (hcr) { 1505 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1506 1507 for (i = 1; i <= sc->sc_noport; i++) { 1508 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1509 if ((cmd & EHCI_PS_PO) == 0 && 1510 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1511 EOWRITE4(sc, EHCI_PORTSC(i), 1512 cmd & ~EHCI_PS_FPR); 1513 } 1514 } 1515 1516 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1517 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1518 1519 for (i = 0; i < 100; i++) { 1520 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1521 if (hcr != EHCI_STS_HCH) 1522 break; 1523 1524 usb_delay_ms(&sc->sc_bus, 1); 1525 } 1526 if (hcr == EHCI_STS_HCH) 1527 printf("%s: config timeout\n", device_xname(dv)); 1528 1529 return true; 1530 } 1531 1532 /* 1533 * Shut down the controller when the system is going down. 1534 */ 1535 bool 1536 ehci_shutdown(device_t self, int flags) 1537 { 1538 ehci_softc_t *sc = device_private(self); 1539 1540 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1541 1542 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1543 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1544 return true; 1545 } 1546 1547 Static struct usbd_xfer * 1548 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1549 { 1550 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1551 struct usbd_xfer *xfer; 1552 1553 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1554 if (xfer != NULL) { 1555 memset(xfer, 0, sizeof(struct ehci_xfer)); 1556 #ifdef DIAGNOSTIC 1557 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1558 ex->ex_isdone = true; 1559 xfer->ux_state = XFER_BUSY; 1560 #endif 1561 } 1562 return xfer; 1563 } 1564 1565 Static void 1566 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1567 { 1568 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1569 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1570 1571 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1572 xfer->ux_state); 1573 KASSERT(ex->ex_isdone); 1574 1575 #ifdef DIAGNOSTIC 1576 xfer->ux_state = XFER_FREE; 1577 #endif 1578 1579 pool_cache_put(sc->sc_xferpool, xfer); 1580 } 1581 1582 Static void 1583 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1584 { 1585 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1586 1587 *lock = &sc->sc_lock; 1588 } 1589 1590 Static void 1591 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1592 { 1593 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1594 1595 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1596 1597 DPRINTF("epipe=%p status=0x%08x", epipe, 1598 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1599 #ifdef EHCI_DEBUG 1600 if (ehcidebug) 1601 usbd_dump_pipe(pipe); 1602 #endif 1603 epipe->nexttoggle = 0; 1604 } 1605 1606 Static void 1607 ehci_noop(struct usbd_pipe *pipe) 1608 { 1609 } 1610 1611 #ifdef EHCI_DEBUG 1612 /* 1613 * Unused function - this is meant to be called from a kernel 1614 * debugger. 1615 */ 1616 void 1617 ehci_dump(void) 1618 { 1619 ehci_softc_t *sc = theehci; 1620 int i; 1621 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1622 EOREAD4(sc, EHCI_USBCMD), 1623 EOREAD4(sc, EHCI_USBSTS), 1624 EOREAD4(sc, EHCI_USBINTR)); 1625 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1626 EOREAD4(sc, EHCI_FRINDEX), 1627 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1628 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1629 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1630 for (i = 1; i <= sc->sc_noport; i++) 1631 printf("port %d status=0x%08x\n", i, 1632 EOREAD4(sc, EHCI_PORTSC(i))); 1633 } 1634 1635 Static void 1636 ehci_dump_regs(ehci_softc_t *sc) 1637 { 1638 int i; 1639 1640 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1641 1642 DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1643 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1644 EOREAD4(sc, EHCI_USBINTR), 0); 1645 DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1646 "async = 0x%08x", 1647 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1648 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1649 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1650 for (i = 1; i <= sc->sc_noport; i += 2) { 1651 if (i == sc->sc_noport) { 1652 DPRINTF("port %d status = 0x%08x", i, 1653 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1654 } else { 1655 DPRINTF( 1656 "port %d status = 0x%08x port %d status = 0x%08x", 1657 i, EOREAD4(sc, EHCI_PORTSC(i)), 1658 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1659 } 1660 } 1661 } 1662 1663 #define ehci_dump_link(link, type) do { \ 1664 DPRINTF(" link 0x%08x (T = %d):", \ 1665 link, \ 1666 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1667 if (type) { \ 1668 DPRINTF( \ 1669 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1670 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1671 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1672 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1673 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1674 } \ 1675 } while(0) 1676 1677 Static void 1678 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1679 { 1680 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1681 int i; 1682 uint32_t stop = 0; 1683 1684 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1685 ehci_dump_sqtd(sqtd); 1686 usb_syncmem(&sqtd->dma, 1687 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1688 sizeof(sqtd->qtd), 1689 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1690 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1691 usb_syncmem(&sqtd->dma, 1692 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1693 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1694 } 1695 if (!stop) 1696 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1697 } 1698 1699 Static void 1700 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1701 { 1702 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1703 1704 usb_syncmem(&sqtd->dma, sqtd->offs, 1705 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1706 1707 DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1708 ehci_dump_qtd(&sqtd->qtd); 1709 1710 usb_syncmem(&sqtd->dma, sqtd->offs, 1711 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1712 } 1713 1714 Static void 1715 ehci_dump_qtd(ehci_qtd_t *qtd) 1716 { 1717 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1718 uint32_t s = le32toh(qtd->qtd_status); 1719 1720 DPRINTFN(10, 1721 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1722 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1723 DPRINTFN(10, 1724 " toggle = %d ioc = %d bytes = %#x " 1725 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1726 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1727 DPRINTFN(10, 1728 " cerr = %d pid = %d stat = %x", 1729 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1730 0); 1731 DPRINTFN(10, 1732 "active =%d halted=%d buferr=%d babble=%d", 1733 s & EHCI_QTD_ACTIVE ? 1 : 0, 1734 s & EHCI_QTD_HALTED ? 1 : 0, 1735 s & EHCI_QTD_BUFERR ? 1 : 0, 1736 s & EHCI_QTD_BABBLE ? 1 : 0); 1737 DPRINTFN(10, 1738 "xacterr=%d missed=%d split =%d ping =%d", 1739 s & EHCI_QTD_XACTERR ? 1 : 0, 1740 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1741 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1742 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1743 DPRINTFN(10, 1744 "buffer[0] = %#x buffer[1] = %#x " 1745 "buffer[2] = %#x buffer[3] = %#x", 1746 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1747 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1748 DPRINTFN(10, 1749 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1750 } 1751 1752 Static void 1753 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1754 { 1755 ehci_qh_t *qh = &sqh->qh; 1756 ehci_link_t link; 1757 uint32_t endp, endphub; 1758 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1759 1760 usb_syncmem(&sqh->dma, sqh->offs, 1761 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1762 1763 DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1764 link = le32toh(qh->qh_link); 1765 ehci_dump_link(link, true); 1766 1767 endp = le32toh(qh->qh_endp); 1768 DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); 1769 DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", 1770 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1771 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1772 DPRINTFN(10, " dtc = %d hrecl = %d", 1773 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1774 DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", 1775 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1776 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1777 1778 endphub = le32toh(qh->qh_endphub); 1779 DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); 1780 DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", 1781 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1782 DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", 1783 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1784 EHCI_QH_GET_MULT(endphub), 0); 1785 1786 link = le32toh(qh->qh_curqtd); 1787 ehci_dump_link(link, false); 1788 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1789 ehci_dump_qtd(&qh->qh_qtd); 1790 1791 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1792 BUS_DMASYNC_PREREAD); 1793 } 1794 1795 Static void 1796 ehci_dump_itds(ehci_soft_itd_t *itd) 1797 { 1798 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1799 int i; 1800 uint32_t stop = 0; 1801 1802 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1803 ehci_dump_itd(itd); 1804 usb_syncmem(&itd->dma, 1805 itd->offs + offsetof(ehci_itd_t, itd_next), 1806 sizeof(itd->itd), 1807 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1808 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1809 usb_syncmem(&itd->dma, 1810 itd->offs + offsetof(ehci_itd_t, itd_next), 1811 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1812 } 1813 if (!stop) 1814 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1815 } 1816 1817 Static void 1818 ehci_dump_itd(struct ehci_soft_itd *itd) 1819 { 1820 ehci_isoc_trans_t t; 1821 ehci_isoc_bufr_ptr_t b, b2, b3; 1822 int i; 1823 1824 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1825 1826 DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); 1827 1828 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1829 t = le32toh(itd->itd.itd_ctl[i]); 1830 DPRINTF("ITDctl %d: stat = %x len = %x", 1831 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1832 DPRINTF(" ioc = %x pg = %x offs = %x", 1833 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1834 EHCI_ITD_GET_OFFS(t), 0); 1835 } 1836 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1837 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1838 DPRINTF(" %x", 1839 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1840 1841 b = le32toh(itd->itd.itd_bufr[0]); 1842 b2 = le32toh(itd->itd.itd_bufr[1]); 1843 b3 = le32toh(itd->itd.itd_bufr[2]); 1844 DPRINTF(" ep = %x daddr = %x dir = %d", 1845 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1846 DPRINTF(" maxpkt = %x multi = %x", 1847 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1848 } 1849 1850 Static void 1851 ehci_dump_sitd(struct ehci_soft_itd *itd) 1852 { 1853 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1854 1855 DPRINTF("SITD %p next = %p prev = %p", 1856 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1857 DPRINTF(" xfernext=%p physaddr=%X slot=%d", 1858 itd->xfer_next, itd->physaddr, itd->slot, 0); 1859 } 1860 1861 Static void 1862 ehci_dump_exfer(struct ehci_xfer *ex) 1863 { 1864 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1865 1866 DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, 1867 ex->ex_isdone, 0); 1868 1869 switch (ex->ex_type) { 1870 case EX_CTRL: 1871 DPRINTF(" setup = %p data = %p status = %p", 1872 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1873 break; 1874 case EX_BULK: 1875 case EX_INTR: 1876 DPRINTF(" qtdstart = %p qtdend = %p", 1877 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1878 break; 1879 case EX_ISOC: 1880 DPRINTF(" itdstart = %p itdend = %p", 1881 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1882 break; 1883 case EX_FS_ISOC: 1884 DPRINTF(" sitdstart = %p sitdend = %p", 1885 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1886 break; 1887 default: 1888 DPRINTF(" unknown type", 0, 0, 0, 0); 1889 } 1890 } 1891 #endif 1892 1893 Static usbd_status 1894 ehci_open(struct usbd_pipe *pipe) 1895 { 1896 struct usbd_device *dev = pipe->up_dev; 1897 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1898 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1899 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1900 uint8_t addr = dev->ud_addr; 1901 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1902 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1903 ehci_soft_qh_t *sqh; 1904 usbd_status err; 1905 int ival, speed, naks; 1906 int hshubaddr, hshubport; 1907 1908 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1909 1910 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1911 ed->bEndpointAddress, rhaddr); 1912 1913 if (dev->ud_myhsport) { 1914 /* 1915 * When directly attached FS/LS device while doing embedded 1916 * transaction translations and we are the hub, set the hub 1917 * address to 0 (us). 1918 */ 1919 if (!(sc->sc_flags & EHCIF_ETTF) 1920 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1921 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1922 } else { 1923 hshubaddr = 0; 1924 } 1925 hshubport = dev->ud_myhsport->up_portno; 1926 } else { 1927 hshubaddr = 0; 1928 hshubport = 0; 1929 } 1930 1931 if (sc->sc_dying) 1932 return USBD_IOERROR; 1933 1934 /* toggle state needed for bulk endpoints */ 1935 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1936 1937 if (addr == rhaddr) { 1938 switch (ed->bEndpointAddress) { 1939 case USB_CONTROL_ENDPOINT: 1940 pipe->up_methods = &roothub_ctrl_methods; 1941 break; 1942 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1943 pipe->up_methods = &ehci_root_intr_methods; 1944 break; 1945 default: 1946 DPRINTF("bad bEndpointAddress 0x%02x", 1947 ed->bEndpointAddress, 0, 0, 0); 1948 return USBD_INVAL; 1949 } 1950 return USBD_NORMAL_COMPLETION; 1951 } 1952 1953 /* XXX All this stuff is only valid for async. */ 1954 switch (dev->ud_speed) { 1955 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1956 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1957 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1958 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1959 } 1960 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1961 DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, 1962 0); 1963 return USBD_INVAL; 1964 } 1965 1966 /* 1967 * For interrupt transfer, nak throttling must be disabled, but for 1968 * the other transfer type, nak throttling should be enabled from the 1969 * viewpoint that avoids the memory thrashing. 1970 */ 1971 naks = (xfertype == UE_INTERRUPT) ? 0 1972 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1973 1974 /* Allocate sqh for everything, save isoc xfers */ 1975 if (xfertype != UE_ISOCHRONOUS) { 1976 sqh = ehci_alloc_sqh(sc); 1977 if (sqh == NULL) 1978 return USBD_NOMEM; 1979 /* qh_link filled when the QH is added */ 1980 sqh->qh.qh_endp = htole32( 1981 EHCI_QH_SET_ADDR(addr) | 1982 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1983 EHCI_QH_SET_EPS(speed) | 1984 EHCI_QH_DTC | 1985 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1986 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1987 EHCI_QH_CTL : 0) | 1988 EHCI_QH_SET_NRL(naks) 1989 ); 1990 sqh->qh.qh_endphub = htole32( 1991 EHCI_QH_SET_MULT(1) | 1992 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1993 ); 1994 if (speed != EHCI_QH_SPEED_HIGH) 1995 sqh->qh.qh_endphub |= htole32( 1996 EHCI_QH_SET_PORT(hshubport) | 1997 EHCI_QH_SET_HUBA(hshubaddr) | 1998 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1999 ); 2000 sqh->qh.qh_curqtd = EHCI_NULL; 2001 /* Fill the overlay qTD */ 2002 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2003 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2004 sqh->qh.qh_qtd.qtd_status = htole32(0); 2005 2006 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2007 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2008 epipe->sqh = sqh; 2009 } else { 2010 sqh = NULL; 2011 } /*xfertype == UE_ISOC*/ 2012 2013 switch (xfertype) { 2014 case UE_CONTROL: 2015 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2016 0, &epipe->ctrl.reqdma); 2017 #ifdef EHCI_DEBUG 2018 if (err) 2019 printf("ehci_open: usb_allocmem()=%d\n", err); 2020 #endif 2021 if (err) 2022 goto bad; 2023 pipe->up_methods = &ehci_device_ctrl_methods; 2024 mutex_enter(&sc->sc_lock); 2025 ehci_add_qh(sc, sqh, sc->sc_async_head); 2026 mutex_exit(&sc->sc_lock); 2027 break; 2028 case UE_BULK: 2029 pipe->up_methods = &ehci_device_bulk_methods; 2030 mutex_enter(&sc->sc_lock); 2031 ehci_add_qh(sc, sqh, sc->sc_async_head); 2032 mutex_exit(&sc->sc_lock); 2033 break; 2034 case UE_INTERRUPT: 2035 pipe->up_methods = &ehci_device_intr_methods; 2036 ival = pipe->up_interval; 2037 if (ival == USBD_DEFAULT_INTERVAL) { 2038 if (speed == EHCI_QH_SPEED_HIGH) { 2039 if (ed->bInterval > 16) { 2040 /* 2041 * illegal with high-speed, but there 2042 * were documentation bugs in the spec, 2043 * so be generous 2044 */ 2045 ival = 256; 2046 } else 2047 ival = (1 << (ed->bInterval - 1)) / 8; 2048 } else 2049 ival = ed->bInterval; 2050 } 2051 err = ehci_device_setintr(sc, sqh, ival); 2052 if (err) 2053 goto bad; 2054 break; 2055 case UE_ISOCHRONOUS: 2056 pipe->up_serialise = false; 2057 if (speed == EHCI_QH_SPEED_HIGH) 2058 pipe->up_methods = &ehci_device_isoc_methods; 2059 else 2060 pipe->up_methods = &ehci_device_fs_isoc_methods; 2061 if (ed->bInterval == 0 || ed->bInterval > 16) { 2062 printf("ehci: opening pipe with invalid bInterval\n"); 2063 err = USBD_INVAL; 2064 goto bad; 2065 } 2066 if (UGETW(ed->wMaxPacketSize) == 0) { 2067 printf("ehci: zero length endpoint open request\n"); 2068 err = USBD_INVAL; 2069 goto bad; 2070 } 2071 epipe->isoc.next_frame = 0; 2072 epipe->isoc.cur_xfers = 0; 2073 break; 2074 default: 2075 DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); 2076 err = USBD_INVAL; 2077 goto bad; 2078 } 2079 return USBD_NORMAL_COMPLETION; 2080 2081 bad: 2082 if (sqh != NULL) { 2083 mutex_enter(&sc->sc_lock); 2084 ehci_free_sqh(sc, sqh); 2085 mutex_exit(&sc->sc_lock); 2086 } 2087 return err; 2088 } 2089 2090 /* 2091 * Add an ED to the schedule. Called with USB lock held. 2092 */ 2093 Static void 2094 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2095 { 2096 2097 KASSERT(mutex_owned(&sc->sc_lock)); 2098 2099 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2100 2101 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2102 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2103 2104 sqh->next = head->next; 2105 sqh->qh.qh_link = head->qh.qh_link; 2106 2107 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2108 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2109 2110 head->next = sqh; 2111 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2112 2113 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2114 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2115 2116 #ifdef EHCI_DEBUG 2117 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2118 ehci_dump_sqh(sqh); 2119 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2120 #endif 2121 } 2122 2123 /* 2124 * Remove an ED from the schedule. Called with USB lock held. 2125 */ 2126 Static void 2127 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2128 { 2129 ehci_soft_qh_t *p; 2130 2131 KASSERT(mutex_owned(&sc->sc_lock)); 2132 2133 /* XXX */ 2134 for (p = head; p != NULL && p->next != sqh; p = p->next) 2135 ; 2136 if (p == NULL) 2137 panic("ehci_rem_qh: ED not found"); 2138 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2139 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2140 p->next = sqh->next; 2141 p->qh.qh_link = sqh->qh.qh_link; 2142 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2143 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2144 2145 ehci_sync_hc(sc); 2146 } 2147 2148 Static void 2149 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2150 { 2151 int i; 2152 uint32_t status; 2153 2154 /* Save toggle bit and ping status. */ 2155 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2156 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2157 status = sqh->qh.qh_qtd.qtd_status & 2158 htole32(EHCI_QTD_TOGGLE_MASK | 2159 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2160 /* Set HALTED to make hw leave it alone. */ 2161 sqh->qh.qh_qtd.qtd_status = 2162 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2163 usb_syncmem(&sqh->dma, 2164 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2165 sizeof(sqh->qh.qh_qtd.qtd_status), 2166 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2167 sqh->qh.qh_curqtd = 0; 2168 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2169 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2170 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2171 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2172 sqh->sqtd = sqtd; 2173 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2175 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2176 sqh->qh.qh_qtd.qtd_status = status; 2177 usb_syncmem(&sqh->dma, 2178 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2179 sizeof(sqh->qh.qh_qtd.qtd_status), 2180 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2181 } 2182 2183 /* 2184 * Ensure that the HC has released all references to the QH. We do this 2185 * by asking for a Async Advance Doorbell interrupt and then we wait for 2186 * the interrupt. 2187 * To make this easier we first obtain exclusive use of the doorbell. 2188 */ 2189 Static void 2190 ehci_sync_hc(ehci_softc_t *sc) 2191 { 2192 int error __diagused; 2193 2194 KASSERT(mutex_owned(&sc->sc_lock)); 2195 2196 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2197 2198 if (sc->sc_dying) { 2199 DPRINTF("dying", 0, 0, 0, 0); 2200 return; 2201 } 2202 /* ask for doorbell */ 2203 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2204 DPRINTF("cmd = 0x%08x sts = 0x%08x", 2205 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2206 2207 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2208 2209 DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", 2210 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2211 #ifdef DIAGNOSTIC 2212 if (error) 2213 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2214 #endif 2215 } 2216 2217 Static void 2218 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2219 { 2220 2221 KASSERT(mutex_owned(&sc->sc_lock)); 2222 2223 for (; itd != NULL; itd = itd->xfer_next) { 2224 struct ehci_soft_itd *prev = itd->frame_list.prev; 2225 2226 /* Unlink itd from hardware chain, or frame array */ 2227 if (prev == NULL) { /* We're at the table head */ 2228 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2229 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2230 usb_syncmem(&sc->sc_fldma, 2231 sizeof(ehci_link_t) * itd->slot, 2232 sizeof(ehci_link_t), 2233 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2234 2235 if (itd->frame_list.next != NULL) 2236 itd->frame_list.next->frame_list.prev = NULL; 2237 } else { 2238 /* XXX this part is untested... */ 2239 prev->itd.itd_next = itd->itd.itd_next; 2240 usb_syncmem(&itd->dma, 2241 itd->offs + offsetof(ehci_itd_t, itd_next), 2242 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2243 2244 prev->frame_list.next = itd->frame_list.next; 2245 if (itd->frame_list.next != NULL) 2246 itd->frame_list.next->frame_list.prev = prev; 2247 } 2248 } 2249 } 2250 2251 Static void 2252 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2253 { 2254 struct ehci_soft_itd *next; 2255 2256 mutex_enter(&sc->sc_lock); 2257 next = NULL; 2258 for (; itd != NULL; itd = next) { 2259 next = itd->xfer_next; 2260 ehci_free_itd_locked(sc, itd); 2261 } 2262 mutex_exit(&sc->sc_lock); 2263 } 2264 2265 Static void 2266 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2267 { 2268 2269 KASSERT(mutex_owned(&sc->sc_lock)); 2270 2271 for (; sitd != NULL; sitd = sitd->xfer_next) { 2272 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2273 2274 /* Unlink sitd from hardware chain, or frame array */ 2275 if (prev == NULL) { /* We're at the table head */ 2276 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2277 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2278 usb_syncmem(&sc->sc_fldma, 2279 sizeof(ehci_link_t) * sitd->slot, 2280 sizeof(ehci_link_t), 2281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2282 2283 if (sitd->frame_list.next != NULL) 2284 sitd->frame_list.next->frame_list.prev = NULL; 2285 } else { 2286 /* XXX this part is untested... */ 2287 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2288 usb_syncmem(&sitd->dma, 2289 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2290 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2291 2292 prev->frame_list.next = sitd->frame_list.next; 2293 if (sitd->frame_list.next != NULL) 2294 sitd->frame_list.next->frame_list.prev = prev; 2295 } 2296 } 2297 } 2298 2299 Static void 2300 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2301 { 2302 2303 mutex_enter(&sc->sc_lock); 2304 struct ehci_soft_sitd *next = NULL; 2305 for (; sitd != NULL; sitd = next) { 2306 next = sitd->xfer_next; 2307 ehci_free_sitd_locked(sc, sitd); 2308 } 2309 mutex_exit(&sc->sc_lock); 2310 } 2311 2312 /***********/ 2313 2314 Static int 2315 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2316 void *buf, int buflen) 2317 { 2318 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2319 usb_hub_descriptor_t hubd; 2320 usb_port_status_t ps; 2321 uint16_t len, value, index; 2322 int l, totlen = 0; 2323 int port, i; 2324 uint32_t v; 2325 2326 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2327 2328 if (sc->sc_dying) 2329 return -1; 2330 2331 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, 2332 0, 0); 2333 2334 len = UGETW(req->wLength); 2335 value = UGETW(req->wValue); 2336 index = UGETW(req->wIndex); 2337 2338 #define C(x,y) ((x) | ((y) << 8)) 2339 switch (C(req->bRequest, req->bmRequestType)) { 2340 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2341 if (len == 0) 2342 break; 2343 switch (value) { 2344 case C(0, UDESC_DEVICE): { 2345 usb_device_descriptor_t devd; 2346 totlen = min(buflen, sizeof(devd)); 2347 memcpy(&devd, buf, totlen); 2348 USETW(devd.idVendor, sc->sc_id_vendor); 2349 memcpy(buf, &devd, totlen); 2350 break; 2351 2352 } 2353 #define sd ((usb_string_descriptor_t *)buf) 2354 case C(1, UDESC_STRING): 2355 /* Vendor */ 2356 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2357 break; 2358 case C(2, UDESC_STRING): 2359 /* Product */ 2360 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2361 break; 2362 #undef sd 2363 default: 2364 /* default from usbroothub */ 2365 return buflen; 2366 } 2367 break; 2368 2369 /* Hub requests */ 2370 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2371 break; 2372 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2373 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 2374 value, 0, 0); 2375 if (index < 1 || index > sc->sc_noport) { 2376 return -1; 2377 } 2378 port = EHCI_PORTSC(index); 2379 v = EOREAD4(sc, port); 2380 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2381 v &= ~EHCI_PS_CLEAR; 2382 switch (value) { 2383 case UHF_PORT_ENABLE: 2384 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2385 break; 2386 case UHF_PORT_SUSPEND: 2387 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2388 break; 2389 v &= ~EHCI_PS_SUSP; 2390 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2391 /* see USB2 spec ch. 7.1.7.7 */ 2392 usb_delay_ms(&sc->sc_bus, 20); 2393 EOWRITE4(sc, port, v); 2394 usb_delay_ms(&sc->sc_bus, 2); 2395 #ifdef DEBUG 2396 v = EOREAD4(sc, port); 2397 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2398 printf("ehci: resume failed: %x\n", v); 2399 #endif 2400 break; 2401 case UHF_PORT_POWER: 2402 if (sc->sc_hasppc) 2403 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2404 break; 2405 case UHF_PORT_TEST: 2406 DPRINTF("clear port test %d", index, 0, 0, 0); 2407 break; 2408 case UHF_PORT_INDICATOR: 2409 DPRINTF("clear port ind %d", index, 0, 0, 0); 2410 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2411 break; 2412 case UHF_C_PORT_CONNECTION: 2413 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2414 break; 2415 case UHF_C_PORT_ENABLE: 2416 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2417 break; 2418 case UHF_C_PORT_SUSPEND: 2419 /* how? */ 2420 break; 2421 case UHF_C_PORT_OVER_CURRENT: 2422 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2423 break; 2424 case UHF_C_PORT_RESET: 2425 sc->sc_isreset[index] = 0; 2426 break; 2427 default: 2428 return -1; 2429 } 2430 #if 0 2431 switch(value) { 2432 case UHF_C_PORT_CONNECTION: 2433 case UHF_C_PORT_ENABLE: 2434 case UHF_C_PORT_SUSPEND: 2435 case UHF_C_PORT_OVER_CURRENT: 2436 case UHF_C_PORT_RESET: 2437 default: 2438 break; 2439 } 2440 #endif 2441 break; 2442 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2443 if (len == 0) 2444 break; 2445 if ((value & 0xff) != 0) { 2446 return -1; 2447 } 2448 totlen = min(buflen, sizeof(hubd)); 2449 memcpy(&hubd, buf, totlen); 2450 hubd.bNbrPorts = sc->sc_noport; 2451 v = EOREAD4(sc, EHCI_HCSPARAMS); 2452 USETW(hubd.wHubCharacteristics, 2453 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2454 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2455 ? UHD_PORT_IND : 0); 2456 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2457 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2458 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2459 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2460 totlen = min(totlen, hubd.bDescLength); 2461 memcpy(buf, &hubd, totlen); 2462 break; 2463 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2464 if (len != 4) { 2465 return -1; 2466 } 2467 memset(buf, 0, len); /* ? XXX */ 2468 totlen = len; 2469 break; 2470 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2471 DPRINTF("get port status i=%d", index, 0, 0, 0); 2472 if (index < 1 || index > sc->sc_noport) { 2473 return -1; 2474 } 2475 if (len != 4) { 2476 return -1; 2477 } 2478 v = EOREAD4(sc, EHCI_PORTSC(index)); 2479 DPRINTF("port status=0x%04x", v, 0, 0, 0); 2480 2481 i = UPS_HIGH_SPEED; 2482 if (sc->sc_flags & EHCIF_ETTF) { 2483 /* 2484 * If we are doing embedded transaction translation, 2485 * then directly attached LS/FS devices are reset by 2486 * the EHCI controller itself. PSPD is encoded 2487 * the same way as in USBSTATUS. 2488 */ 2489 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2490 } 2491 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2492 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2493 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2494 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2495 if (v & EHCI_PS_PR) i |= UPS_RESET; 2496 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2497 if (sc->sc_vendor_port_status) 2498 i = sc->sc_vendor_port_status(sc, v, i); 2499 USETW(ps.wPortStatus, i); 2500 i = 0; 2501 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2502 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2503 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2504 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2505 USETW(ps.wPortChange, i); 2506 totlen = min(len, sizeof(ps)); 2507 memcpy(buf, &ps, totlen); 2508 break; 2509 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2510 return -1; 2511 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2512 break; 2513 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2514 if (index < 1 || index > sc->sc_noport) { 2515 return -1; 2516 } 2517 port = EHCI_PORTSC(index); 2518 v = EOREAD4(sc, port); 2519 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2520 v &= ~EHCI_PS_CLEAR; 2521 switch(value) { 2522 case UHF_PORT_ENABLE: 2523 EOWRITE4(sc, port, v | EHCI_PS_PE); 2524 break; 2525 case UHF_PORT_SUSPEND: 2526 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2527 break; 2528 case UHF_PORT_RESET: 2529 DPRINTF("reset port %d", index, 0, 0, 0); 2530 if (EHCI_PS_IS_LOWSPEED(v) 2531 && sc->sc_ncomp > 0 2532 && !(sc->sc_flags & EHCIF_ETTF)) { 2533 /* 2534 * Low speed device on non-ETTF controller or 2535 * unaccompanied controller, give up ownership. 2536 */ 2537 ehci_disown(sc, index, 1); 2538 break; 2539 } 2540 /* Start reset sequence. */ 2541 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2542 EOWRITE4(sc, port, v | EHCI_PS_PR); 2543 /* Wait for reset to complete. */ 2544 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2545 if (sc->sc_dying) { 2546 return -1; 2547 } 2548 /* 2549 * An embedded transaction translator will automatically 2550 * terminate the reset sequence so there's no need to 2551 * it. 2552 */ 2553 v = EOREAD4(sc, port); 2554 if (v & EHCI_PS_PR) { 2555 /* Terminate reset sequence. */ 2556 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2557 /* Wait for HC to complete reset. */ 2558 usb_delay_ms(&sc->sc_bus, 2559 EHCI_PORT_RESET_COMPLETE); 2560 if (sc->sc_dying) { 2561 return -1; 2562 } 2563 } 2564 2565 v = EOREAD4(sc, port); 2566 DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); 2567 if (v & EHCI_PS_PR) { 2568 printf("%s: port reset timeout\n", 2569 device_xname(sc->sc_dev)); 2570 return USBD_TIMEOUT; 2571 } 2572 if (!(v & EHCI_PS_PE)) { 2573 /* Not a high speed device, give up ownership.*/ 2574 ehci_disown(sc, index, 0); 2575 break; 2576 } 2577 sc->sc_isreset[index] = 1; 2578 DPRINTF("ehci port %d reset, status = 0x%08x", index, 2579 v, 0, 0); 2580 break; 2581 case UHF_PORT_POWER: 2582 DPRINTF("set port power %d (has PPC = %d)", index, 2583 sc->sc_hasppc, 0, 0); 2584 if (sc->sc_hasppc) 2585 EOWRITE4(sc, port, v | EHCI_PS_PP); 2586 break; 2587 case UHF_PORT_TEST: 2588 DPRINTF("set port test %d", index, 0, 0, 0); 2589 break; 2590 case UHF_PORT_INDICATOR: 2591 DPRINTF("set port ind %d", index, 0, 0, 0); 2592 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2593 break; 2594 default: 2595 return -1; 2596 } 2597 break; 2598 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2599 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2600 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2601 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2602 break; 2603 default: 2604 /* default from usbroothub */ 2605 DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); 2606 2607 return buflen; 2608 } 2609 2610 DPRINTF("returning %d", totlen, 0, 0, 0); 2611 2612 return totlen; 2613 } 2614 2615 Static void 2616 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2617 { 2618 int port; 2619 uint32_t v; 2620 2621 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2622 2623 DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); 2624 #ifdef DIAGNOSTIC 2625 if (sc->sc_npcomp != 0) { 2626 int i = (index-1) / sc->sc_npcomp; 2627 if (i >= sc->sc_ncomp) 2628 printf("%s: strange port\n", 2629 device_xname(sc->sc_dev)); 2630 else 2631 printf("%s: handing over %s speed device on " 2632 "port %d to %s\n", 2633 device_xname(sc->sc_dev), 2634 lowspeed ? "low" : "full", 2635 index, device_xname(sc->sc_comps[i])); 2636 } else { 2637 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2638 } 2639 #endif 2640 port = EHCI_PORTSC(index); 2641 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2642 EOWRITE4(sc, port, v | EHCI_PS_PO); 2643 } 2644 2645 Static usbd_status 2646 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2647 { 2648 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2649 usbd_status err; 2650 2651 /* Insert last in queue. */ 2652 mutex_enter(&sc->sc_lock); 2653 err = usb_insert_transfer(xfer); 2654 mutex_exit(&sc->sc_lock); 2655 if (err) 2656 return err; 2657 2658 /* Pipe isn't running, start first */ 2659 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2660 } 2661 2662 Static usbd_status 2663 ehci_root_intr_start(struct usbd_xfer *xfer) 2664 { 2665 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2666 2667 if (sc->sc_dying) 2668 return USBD_IOERROR; 2669 2670 mutex_enter(&sc->sc_lock); 2671 sc->sc_intrxfer = xfer; 2672 mutex_exit(&sc->sc_lock); 2673 2674 return USBD_IN_PROGRESS; 2675 } 2676 2677 /* Abort a root interrupt request. */ 2678 Static void 2679 ehci_root_intr_abort(struct usbd_xfer *xfer) 2680 { 2681 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2682 2683 KASSERT(mutex_owned(&sc->sc_lock)); 2684 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2685 2686 sc->sc_intrxfer = NULL; 2687 2688 xfer->ux_status = USBD_CANCELLED; 2689 usb_transfer_complete(xfer); 2690 } 2691 2692 /* Close the root pipe. */ 2693 Static void 2694 ehci_root_intr_close(struct usbd_pipe *pipe) 2695 { 2696 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2697 2698 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2699 2700 KASSERT(mutex_owned(&sc->sc_lock)); 2701 2702 sc->sc_intrxfer = NULL; 2703 } 2704 2705 Static void 2706 ehci_root_intr_done(struct usbd_xfer *xfer) 2707 { 2708 } 2709 2710 /************************/ 2711 2712 Static ehci_soft_qh_t * 2713 ehci_alloc_sqh(ehci_softc_t *sc) 2714 { 2715 ehci_soft_qh_t *sqh; 2716 usbd_status err; 2717 int i, offs; 2718 usb_dma_t dma; 2719 2720 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2721 2722 mutex_enter(&sc->sc_lock); 2723 if (sc->sc_freeqhs == NULL) { 2724 DPRINTF("allocating chunk", 0, 0, 0, 0); 2725 mutex_exit(&sc->sc_lock); 2726 2727 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2728 EHCI_PAGE_SIZE, &dma); 2729 #ifdef EHCI_DEBUG 2730 if (err) 2731 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2732 #endif 2733 if (err) 2734 return NULL; 2735 2736 mutex_enter(&sc->sc_lock); 2737 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2738 offs = i * EHCI_SQH_SIZE; 2739 sqh = KERNADDR(&dma, offs); 2740 sqh->physaddr = DMAADDR(&dma, offs); 2741 sqh->dma = dma; 2742 sqh->offs = offs; 2743 sqh->next = sc->sc_freeqhs; 2744 sc->sc_freeqhs = sqh; 2745 } 2746 } 2747 sqh = sc->sc_freeqhs; 2748 sc->sc_freeqhs = sqh->next; 2749 mutex_exit(&sc->sc_lock); 2750 2751 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2752 sqh->next = NULL; 2753 return sqh; 2754 } 2755 2756 Static void 2757 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2758 { 2759 KASSERT(mutex_owned(&sc->sc_lock)); 2760 2761 sqh->next = sc->sc_freeqhs; 2762 sc->sc_freeqhs = sqh; 2763 } 2764 2765 Static ehci_soft_qtd_t * 2766 ehci_alloc_sqtd(ehci_softc_t *sc) 2767 { 2768 ehci_soft_qtd_t *sqtd = NULL; 2769 usbd_status err; 2770 int i, offs; 2771 usb_dma_t dma; 2772 2773 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2774 2775 mutex_enter(&sc->sc_lock); 2776 if (sc->sc_freeqtds == NULL) { 2777 DPRINTF("allocating chunk", 0, 0, 0, 0); 2778 mutex_exit(&sc->sc_lock); 2779 2780 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2781 EHCI_PAGE_SIZE, &dma); 2782 #ifdef EHCI_DEBUG 2783 if (err) 2784 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2785 #endif 2786 if (err) 2787 goto done; 2788 2789 mutex_enter(&sc->sc_lock); 2790 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2791 offs = i * EHCI_SQTD_SIZE; 2792 sqtd = KERNADDR(&dma, offs); 2793 sqtd->physaddr = DMAADDR(&dma, offs); 2794 sqtd->dma = dma; 2795 sqtd->offs = offs; 2796 2797 sqtd->nextqtd = sc->sc_freeqtds; 2798 sc->sc_freeqtds = sqtd; 2799 } 2800 } 2801 2802 sqtd = sc->sc_freeqtds; 2803 sc->sc_freeqtds = sqtd->nextqtd; 2804 mutex_exit(&sc->sc_lock); 2805 2806 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2807 sqtd->nextqtd = NULL; 2808 sqtd->xfer = NULL; 2809 2810 done: 2811 return sqtd; 2812 } 2813 2814 Static void 2815 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2816 { 2817 2818 mutex_enter(&sc->sc_lock); 2819 sqtd->nextqtd = sc->sc_freeqtds; 2820 sc->sc_freeqtds = sqtd; 2821 mutex_exit(&sc->sc_lock); 2822 } 2823 2824 Static usbd_status 2825 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2826 int alen, int rd, ehci_soft_qtd_t **sp) 2827 { 2828 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2829 uint16_t flags = xfer->ux_flags; 2830 2831 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2832 2833 ASSERT_SLEEPABLE(); 2834 KASSERT(sp); 2835 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2836 2837 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2838 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2839 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2840 KM_SLEEP); 2841 exfer->ex_nsqtd = nsqtd; 2842 2843 DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); 2844 2845 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2846 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2847 if (cur == NULL) 2848 goto nomem; 2849 exfer->ex_sqtds[j++] = cur; 2850 2851 cur->xfer = xfer; 2852 cur->len = 0; 2853 2854 } 2855 2856 *sp = exfer->ex_sqtds[0]; 2857 DPRINTF("return sqtd=%p", *sp, 0, 0, 0); 2858 2859 return USBD_NORMAL_COMPLETION; 2860 2861 nomem: 2862 ehci_free_sqtds(sc, exfer); 2863 DPRINTF("no memory", 0, 0, 0, 0); 2864 return USBD_NOMEM; 2865 } 2866 2867 Static void 2868 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2869 { 2870 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2871 DPRINTF("exfer=%p", exfer, 0, 0, 0); 2872 2873 mutex_enter(&sc->sc_lock); 2874 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2875 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2876 2877 if (sqtd == NULL) 2878 break; 2879 2880 sqtd->nextqtd = sc->sc_freeqtds; 2881 sc->sc_freeqtds = sqtd; 2882 } 2883 mutex_exit(&sc->sc_lock); 2884 } 2885 2886 Static void 2887 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2888 { 2889 if (prev) { 2890 prev->nextqtd = sqtd; 2891 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2892 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2893 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2894 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2895 } 2896 } 2897 2898 Static void 2899 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2900 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2901 { 2902 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2903 usb_dma_t *dma = &xfer->ux_dmabuf; 2904 uint16_t flags = xfer->ux_flags; 2905 ehci_soft_qtd_t *sqtd, *prev; 2906 int tog = *toggle; 2907 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2908 int len = length; 2909 2910 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2911 DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); 2912 DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); 2913 2914 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2915 2916 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2917 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2918 EHCI_QTD_SET_CERR(3) 2919 ; 2920 2921 sqtd = prev = NULL; 2922 size_t curoffs = 0; 2923 size_t j = 0; 2924 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2925 sqtd = exfer->ex_sqtds[j++]; 2926 DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); 2927 2928 /* 2929 * The EHCI hardware can handle at most 5 pages and they do 2930 * not have to be contiguous 2931 */ 2932 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2933 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2934 size_t curlen = len; 2935 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2936 /* must use multiple TDs, fill as much as possible. */ 2937 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2938 2939 /* the length must be a multiple of the max size */ 2940 curlen -= curlen % mps; 2941 } 2942 KASSERT(curlen != 0); 2943 DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, 2944 curoffs, 0); 2945 2946 /* Fill the qTD */ 2947 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2948 sqtd->qtd.qtd_status = htole32( 2949 qtdstatus | 2950 EHCI_QTD_SET_BYTES(curlen) | 2951 EHCI_QTD_SET_TOGGLE(tog)); 2952 2953 /* Find number of pages we'll be using, insert dma addresses */ 2954 size_t pages = EHCI_NPAGES(curlen); 2955 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2956 size_t pageoffs = EHCI_PAGE(curoffs); 2957 for (size_t i = 0; i < pages; i++) { 2958 paddr_t a = DMAADDR(dma, 2959 pageoffs + i * EHCI_PAGE_SIZE); 2960 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2961 /* Cast up to avoid compiler warnings */ 2962 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2963 DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, 2964 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2965 le32toh(sqtd->qtd.qtd_buffer[i])); 2966 } 2967 /* First buffer pointer requires a page offset to start at */ 2968 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2969 2970 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2971 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2972 2973 sqtd->len = curlen; 2974 2975 DPRINTF(" va %p pa %p len %d", va, 2976 DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2977 2978 ehci_append_sqtd(sqtd, prev); 2979 2980 if (((curlen + mps - 1) / mps) & 1) { 2981 tog ^= 1; 2982 } 2983 2984 curoffs += curlen; 2985 len -= curlen; 2986 } 2987 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2988 xfer, length, len, mps, exfer->ex_nsqtd, j); 2989 2990 if (!isread && 2991 (flags & USBD_FORCE_SHORT_XFER) && 2992 length % mps == 0) { 2993 /* Force a 0 length transfer at the end. */ 2994 2995 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2996 exfer->ex_nsqtd); 2997 prev = sqtd; 2998 sqtd = exfer->ex_sqtds[j++]; 2999 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3000 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3001 sqtd->qtd.qtd_status = htole32( 3002 qtdstatus | 3003 EHCI_QTD_SET_BYTES(0) | 3004 EHCI_QTD_SET_TOGGLE(tog)); 3005 3006 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3007 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3008 3009 ehci_append_sqtd(sqtd, prev); 3010 tog ^= 1; 3011 } 3012 3013 *lsqtd = sqtd; 3014 *toggle = tog; 3015 } 3016 3017 Static ehci_soft_itd_t * 3018 ehci_alloc_itd(ehci_softc_t *sc) 3019 { 3020 struct ehci_soft_itd *itd, *freeitd; 3021 usbd_status err; 3022 usb_dma_t dma; 3023 3024 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3025 3026 mutex_enter(&sc->sc_lock); 3027 3028 freeitd = LIST_FIRST(&sc->sc_freeitds); 3029 if (freeitd == NULL) { 3030 DPRINTF("allocating chunk", 0, 0, 0, 0); 3031 mutex_exit(&sc->sc_lock); 3032 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3033 EHCI_PAGE_SIZE, &dma); 3034 3035 if (err) { 3036 DPRINTF("alloc returned %d", err, 0, 0, 0); 3037 return NULL; 3038 } 3039 mutex_enter(&sc->sc_lock); 3040 3041 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3042 int offs = i * EHCI_ITD_SIZE; 3043 itd = KERNADDR(&dma, offs); 3044 itd->physaddr = DMAADDR(&dma, offs); 3045 itd->dma = dma; 3046 itd->offs = offs; 3047 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3048 } 3049 freeitd = LIST_FIRST(&sc->sc_freeitds); 3050 } 3051 3052 itd = freeitd; 3053 LIST_REMOVE(itd, free_list); 3054 mutex_exit(&sc->sc_lock); 3055 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3056 3057 itd->frame_list.next = NULL; 3058 itd->frame_list.prev = NULL; 3059 itd->xfer_next = NULL; 3060 itd->slot = 0; 3061 3062 return itd; 3063 } 3064 3065 Static ehci_soft_sitd_t * 3066 ehci_alloc_sitd(ehci_softc_t *sc) 3067 { 3068 struct ehci_soft_sitd *sitd, *freesitd; 3069 usbd_status err; 3070 int i, offs; 3071 usb_dma_t dma; 3072 3073 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3074 3075 mutex_enter(&sc->sc_lock); 3076 freesitd = LIST_FIRST(&sc->sc_freesitds); 3077 if (freesitd == NULL) { 3078 DPRINTF("allocating chunk", 0, 0, 0, 0); 3079 mutex_exit(&sc->sc_lock); 3080 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3081 EHCI_PAGE_SIZE, &dma); 3082 3083 if (err) { 3084 DPRINTF("alloc returned %d", err, 0, 0, 3085 0); 3086 return NULL; 3087 } 3088 3089 mutex_enter(&sc->sc_lock); 3090 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3091 offs = i * EHCI_SITD_SIZE; 3092 sitd = KERNADDR(&dma, offs); 3093 sitd->physaddr = DMAADDR(&dma, offs); 3094 sitd->dma = dma; 3095 sitd->offs = offs; 3096 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3097 } 3098 freesitd = LIST_FIRST(&sc->sc_freesitds); 3099 } 3100 3101 sitd = freesitd; 3102 LIST_REMOVE(sitd, free_list); 3103 mutex_exit(&sc->sc_lock); 3104 3105 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3106 3107 sitd->frame_list.next = NULL; 3108 sitd->frame_list.prev = NULL; 3109 sitd->xfer_next = NULL; 3110 sitd->slot = 0; 3111 3112 return sitd; 3113 } 3114 3115 /****************/ 3116 3117 /* 3118 * Close a reqular pipe. 3119 * Assumes that there are no pending transactions. 3120 */ 3121 Static void 3122 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3123 { 3124 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3125 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3126 ehci_soft_qh_t *sqh = epipe->sqh; 3127 3128 KASSERT(mutex_owned(&sc->sc_lock)); 3129 3130 ehci_rem_qh(sc, sqh, head); 3131 ehci_free_sqh(sc, epipe->sqh); 3132 } 3133 3134 /* 3135 * Abort a device request. 3136 * If this routine is called at splusb() it guarantees that the request 3137 * will be removed from the hardware scheduling and that the callback 3138 * for it will be called with USBD_CANCELLED status. 3139 * It's impossible to guarantee that the requested transfer will not 3140 * have happened since the hardware runs concurrently. 3141 * If the transaction has already happened we rely on the ordinary 3142 * interrupt processing to process it. 3143 * XXX This is most probably wrong. 3144 * XXXMRG this doesn't make sense anymore. 3145 */ 3146 Static void 3147 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3148 { 3149 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3150 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3151 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3152 ehci_soft_qh_t *sqh = epipe->sqh; 3153 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3154 ehci_physaddr_t cur; 3155 uint32_t qhstatus; 3156 int hit; 3157 int wake; 3158 3159 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3160 3161 DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); 3162 3163 KASSERT(mutex_owned(&sc->sc_lock)); 3164 ASSERT_SLEEPABLE(); 3165 3166 if (sc->sc_dying) { 3167 /* If we're dying, just do the software part. */ 3168 xfer->ux_status = status; /* make software ignore it */ 3169 callout_stop(&xfer->ux_callout); 3170 usb_transfer_complete(xfer); 3171 return; 3172 } 3173 3174 /* 3175 * If an abort is already in progress then just wait for it to 3176 * complete and return. 3177 */ 3178 if (xfer->ux_hcflags & UXFER_ABORTING) { 3179 DPRINTF("already aborting", 0, 0, 0, 0); 3180 #ifdef DIAGNOSTIC 3181 if (status == USBD_TIMEOUT) 3182 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3183 #endif 3184 /* Override the status which might be USBD_TIMEOUT. */ 3185 xfer->ux_status = status; 3186 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3187 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3188 while (xfer->ux_hcflags & UXFER_ABORTING) 3189 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3190 return; 3191 } 3192 xfer->ux_hcflags |= UXFER_ABORTING; 3193 3194 /* 3195 * Step 1: Make interrupt routine and hardware ignore xfer. 3196 */ 3197 xfer->ux_status = status; /* make software ignore it */ 3198 callout_stop(&xfer->ux_callout); 3199 ehci_del_intr_list(sc, exfer); 3200 3201 usb_syncmem(&sqh->dma, 3202 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3203 sizeof(sqh->qh.qh_qtd.qtd_status), 3204 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3205 qhstatus = sqh->qh.qh_qtd.qtd_status; 3206 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3207 usb_syncmem(&sqh->dma, 3208 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3209 sizeof(sqh->qh.qh_qtd.qtd_status), 3210 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3211 3212 if (exfer->ex_type == EX_CTRL) { 3213 fsqtd = exfer->ex_setup; 3214 lsqtd = exfer->ex_status; 3215 } else { 3216 fsqtd = exfer->ex_sqtdstart; 3217 lsqtd = exfer->ex_sqtdend; 3218 } 3219 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3220 usb_syncmem(&sqtd->dma, 3221 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3222 sizeof(sqtd->qtd.qtd_status), 3223 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3224 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3225 usb_syncmem(&sqtd->dma, 3226 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3227 sizeof(sqtd->qtd.qtd_status), 3228 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3229 if (sqtd == lsqtd) 3230 break; 3231 } 3232 3233 /* 3234 * Step 2: Wait until we know hardware has finished any possible 3235 * use of the xfer. Also make sure the soft interrupt routine 3236 * has run. 3237 */ 3238 ehci_sync_hc(sc); 3239 sc->sc_softwake = 1; 3240 usb_schedsoftintr(&sc->sc_bus); 3241 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3242 3243 /* 3244 * Step 3: Remove any vestiges of the xfer from the hardware. 3245 * The complication here is that the hardware may have executed 3246 * beyond the xfer we're trying to abort. So as we're scanning 3247 * the TDs of this xfer we check if the hardware points to 3248 * any of them. 3249 */ 3250 3251 usb_syncmem(&sqh->dma, 3252 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3253 sizeof(sqh->qh.qh_curqtd), 3254 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3255 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3256 hit = 0; 3257 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3258 hit |= cur == sqtd->physaddr; 3259 if (sqtd == lsqtd) 3260 break; 3261 } 3262 sqtd = sqtd->nextqtd; 3263 /* Zap curqtd register if hardware pointed inside the xfer. */ 3264 if (hit && sqtd != NULL) { 3265 DPRINTF("cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3266 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3267 usb_syncmem(&sqh->dma, 3268 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3269 sizeof(sqh->qh.qh_curqtd), 3270 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3271 sqh->qh.qh_qtd.qtd_status = qhstatus; 3272 usb_syncmem(&sqh->dma, 3273 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3274 sizeof(sqh->qh.qh_qtd.qtd_status), 3275 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3276 } else { 3277 DPRINTF("no hit", 0, 0, 0, 0); 3278 usb_syncmem(&sqh->dma, 3279 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3280 sizeof(sqh->qh.qh_curqtd), 3281 BUS_DMASYNC_PREREAD); 3282 } 3283 3284 /* 3285 * Step 4: Execute callback. 3286 */ 3287 #ifdef DIAGNOSTIC 3288 exfer->ex_isdone = true; 3289 #endif 3290 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3291 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3292 usb_transfer_complete(xfer); 3293 if (wake) { 3294 cv_broadcast(&xfer->ux_hccv); 3295 } 3296 3297 KASSERT(mutex_owned(&sc->sc_lock)); 3298 } 3299 3300 Static void 3301 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3302 { 3303 ehci_isoc_trans_t trans_status; 3304 struct ehci_xfer *exfer; 3305 ehci_softc_t *sc; 3306 struct ehci_soft_itd *itd; 3307 struct ehci_soft_sitd *sitd; 3308 int i, wake; 3309 3310 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3311 3312 exfer = EHCI_XFER2EXFER(xfer); 3313 sc = EHCI_XFER2SC(xfer); 3314 3315 DPRINTF("xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3316 3317 KASSERT(mutex_owned(&sc->sc_lock)); 3318 3319 if (sc->sc_dying) { 3320 xfer->ux_status = status; 3321 callout_stop(&xfer->ux_callout); 3322 usb_transfer_complete(xfer); 3323 return; 3324 } 3325 3326 if (xfer->ux_hcflags & UXFER_ABORTING) { 3327 DPRINTF("already aborting", 0, 0, 0, 0); 3328 3329 #ifdef DIAGNOSTIC 3330 if (status == USBD_TIMEOUT) 3331 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3332 #endif 3333 3334 xfer->ux_status = status; 3335 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3336 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3337 while (xfer->ux_hcflags & UXFER_ABORTING) 3338 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3339 goto done; 3340 } 3341 xfer->ux_hcflags |= UXFER_ABORTING; 3342 3343 xfer->ux_status = status; 3344 callout_stop(&xfer->ux_callout); 3345 ehci_del_intr_list(sc, exfer); 3346 3347 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3348 for (itd = exfer->ex_itdstart; itd != NULL; 3349 itd = itd->xfer_next) { 3350 usb_syncmem(&itd->dma, 3351 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3352 sizeof(itd->itd.itd_ctl), 3353 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3354 3355 for (i = 0; i < 8; i++) { 3356 trans_status = le32toh(itd->itd.itd_ctl[i]); 3357 trans_status &= ~EHCI_ITD_ACTIVE; 3358 itd->itd.itd_ctl[i] = htole32(trans_status); 3359 } 3360 3361 usb_syncmem(&itd->dma, 3362 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3363 sizeof(itd->itd.itd_ctl), 3364 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3365 } 3366 } else { 3367 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3368 sitd = sitd->xfer_next) { 3369 usb_syncmem(&sitd->dma, 3370 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3371 sizeof(sitd->sitd.sitd_buffer), 3372 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3373 3374 trans_status = le32toh(sitd->sitd.sitd_trans); 3375 trans_status &= ~EHCI_SITD_ACTIVE; 3376 sitd->sitd.sitd_trans = htole32(trans_status); 3377 3378 usb_syncmem(&sitd->dma, 3379 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3380 sizeof(sitd->sitd.sitd_buffer), 3381 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3382 } 3383 } 3384 3385 sc->sc_softwake = 1; 3386 usb_schedsoftintr(&sc->sc_bus); 3387 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3388 3389 #ifdef DIAGNOSTIC 3390 exfer->ex_isdone = true; 3391 #endif 3392 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3393 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3394 usb_transfer_complete(xfer); 3395 if (wake) { 3396 cv_broadcast(&xfer->ux_hccv); 3397 } 3398 3399 done: 3400 KASSERT(mutex_owned(&sc->sc_lock)); 3401 return; 3402 } 3403 3404 Static void 3405 ehci_timeout(void *addr) 3406 { 3407 struct usbd_xfer *xfer = addr; 3408 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3409 struct usbd_pipe *pipe = xfer->ux_pipe; 3410 struct usbd_device *dev = pipe->up_dev; 3411 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3412 3413 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3414 3415 DPRINTF("exfer %p", exfer, 0, 0, 0); 3416 #ifdef EHCI_DEBUG 3417 if (ehcidebug >= 2) 3418 usbd_dump_pipe(pipe); 3419 #endif 3420 3421 if (sc->sc_dying) { 3422 mutex_enter(&sc->sc_lock); 3423 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3424 mutex_exit(&sc->sc_lock); 3425 return; 3426 } 3427 3428 /* Execute the abort in a process context. */ 3429 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3430 USB_TASKQ_MPSAFE); 3431 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3432 } 3433 3434 Static void 3435 ehci_timeout_task(void *addr) 3436 { 3437 struct usbd_xfer *xfer = addr; 3438 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3439 3440 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3441 3442 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3443 3444 mutex_enter(&sc->sc_lock); 3445 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3446 mutex_exit(&sc->sc_lock); 3447 } 3448 3449 /************************/ 3450 3451 Static int 3452 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3453 { 3454 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3455 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3456 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3457 usb_device_request_t *req = &xfer->ux_request; 3458 ehci_soft_qtd_t *setup, *status, *next; 3459 int isread = req->bmRequestType & UT_READ; 3460 int len = xfer->ux_bufsize; 3461 int err; 3462 3463 exfer->ex_type = EX_CTRL; 3464 exfer->ex_status = NULL; 3465 exfer->ex_data = NULL; 3466 exfer->ex_setup = ehci_alloc_sqtd(sc); 3467 if (exfer->ex_setup == NULL) { 3468 err = ENOMEM; 3469 goto bad1; 3470 } 3471 exfer->ex_status = ehci_alloc_sqtd(sc); 3472 if (exfer->ex_status == NULL) { 3473 err = ENOMEM; 3474 goto bad2; 3475 } 3476 setup = exfer->ex_setup; 3477 status = exfer->ex_status; 3478 exfer->ex_nsqtd = 0; 3479 next = status; 3480 /* Set up data transaction */ 3481 if (len != 0) { 3482 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3483 &exfer->ex_data); 3484 if (err) 3485 goto bad3; 3486 next = exfer->ex_data; 3487 } 3488 3489 /* Clear toggle */ 3490 setup->qtd.qtd_status = htole32( 3491 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3492 EHCI_QTD_SET_TOGGLE(0) | 3493 EHCI_QTD_SET_BYTES(sizeof(*req)) 3494 ); 3495 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3496 setup->qtd.qtd_buffer_hi[0] = 0; 3497 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3498 setup->nextqtd = next; 3499 setup->xfer = xfer; 3500 setup->len = sizeof(*req); 3501 3502 status->qtd.qtd_status = htole32( 3503 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3504 EHCI_QTD_SET_TOGGLE(1) | 3505 EHCI_QTD_IOC 3506 ); 3507 status->qtd.qtd_buffer[0] = 0; 3508 status->qtd.qtd_buffer_hi[0] = 0; 3509 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3510 status->nextqtd = NULL; 3511 status->xfer = xfer; 3512 status->len = 0; 3513 3514 return 0; 3515 bad3: 3516 ehci_free_sqtd(sc, exfer->ex_status); 3517 bad2: 3518 ehci_free_sqtd(sc, exfer->ex_setup); 3519 bad1: 3520 return err; 3521 } 3522 3523 Static void 3524 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3525 { 3526 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3527 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3528 3529 KASSERT(ex->ex_type == EX_CTRL); 3530 3531 ehci_free_sqtd(sc, ex->ex_setup); 3532 ehci_free_sqtd(sc, ex->ex_status); 3533 ehci_free_sqtds(sc, ex); 3534 if (ex->ex_nsqtd) 3535 kmem_free(ex->ex_sqtds, 3536 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3537 } 3538 3539 Static usbd_status 3540 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3541 { 3542 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3543 usbd_status err; 3544 3545 /* Insert last in queue. */ 3546 mutex_enter(&sc->sc_lock); 3547 err = usb_insert_transfer(xfer); 3548 mutex_exit(&sc->sc_lock); 3549 if (err) 3550 return err; 3551 3552 /* Pipe isn't running, start first */ 3553 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3554 } 3555 3556 Static usbd_status 3557 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3558 { 3559 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3560 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3561 usb_device_request_t *req = &xfer->ux_request; 3562 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3563 ehci_soft_qtd_t *setup, *status, *next; 3564 ehci_soft_qh_t *sqh; 3565 3566 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3567 3568 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3569 3570 if (sc->sc_dying) 3571 return USBD_IOERROR; 3572 3573 const int isread = req->bmRequestType & UT_READ; 3574 const int len = UGETW(req->wLength); 3575 3576 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 3577 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3578 UGETW(req->wIndex)); 3579 DPRINTF("len=%d, addr=%d, endpt=%d", len, epipe->pipe.up_dev->ud_addr, 3580 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3581 3582 sqh = epipe->sqh; 3583 3584 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3585 "address QH %" __PRIuBIT " pipe %d\n", 3586 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3587 epipe->pipe.up_dev->ud_addr); 3588 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3589 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3590 "MPS QH %" __PRIuBIT " pipe %d\n", 3591 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3592 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3593 3594 setup = exfer->ex_setup; 3595 status = exfer->ex_status; 3596 3597 DPRINTF("setup %p status %p data %p", setup, status, exfer->ex_data, 0); 3598 KASSERTMSG(setup != NULL && status != NULL, 3599 "Failed memory allocation, setup %p status %p", 3600 setup, status); 3601 3602 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3603 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3604 3605 /* Clear toggle */ 3606 setup->qtd.qtd_status &= ~htole32( 3607 EHCI_QTD_STATUS_MASK | 3608 EHCI_QTD_BYTES_MASK | 3609 EHCI_QTD_TOGGLE_MASK | 3610 EHCI_QTD_CERR_MASK 3611 ); 3612 setup->qtd.qtd_status |= htole32( 3613 EHCI_QTD_ACTIVE | 3614 EHCI_QTD_SET_CERR(3) | 3615 EHCI_QTD_SET_TOGGLE(0) | 3616 EHCI_QTD_SET_BYTES(sizeof(*req)) 3617 ); 3618 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3619 setup->qtd.qtd_buffer_hi[0] = 0; 3620 3621 next = status; 3622 status->qtd.qtd_status &= ~htole32( 3623 EHCI_QTD_STATUS_MASK | 3624 EHCI_QTD_PID_MASK | 3625 EHCI_QTD_BYTES_MASK | 3626 EHCI_QTD_TOGGLE_MASK | 3627 EHCI_QTD_CERR_MASK 3628 ); 3629 status->qtd.qtd_status |= htole32( 3630 EHCI_QTD_ACTIVE | 3631 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3632 EHCI_QTD_SET_CERR(3) | 3633 EHCI_QTD_SET_TOGGLE(1) | 3634 EHCI_QTD_SET_BYTES(0) | 3635 EHCI_QTD_IOC 3636 ); 3637 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3638 3639 KASSERT(exfer->ex_isdone); 3640 #ifdef DIAGNOSTIC 3641 exfer->ex_isdone = false; 3642 #endif 3643 3644 /* Set up data transaction */ 3645 if (len != 0) { 3646 ehci_soft_qtd_t *end; 3647 3648 /* Start toggle at 1. */ 3649 int toggle = 1; 3650 next = exfer->ex_data; 3651 KASSERTMSG(next != NULL, "Failed memory allocation"); 3652 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3653 end->nextqtd = status; 3654 end->qtd.qtd_next = end->qtd.qtd_altnext = 3655 htole32(status->physaddr); 3656 3657 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3658 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3659 3660 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3661 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3662 } 3663 3664 setup->nextqtd = next; 3665 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3666 3667 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3668 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3669 3670 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3671 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3672 3673 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3674 3675 #ifdef EHCI_DEBUG 3676 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3677 ehci_dump_sqh(sqh); 3678 ehci_dump_sqtds(setup); 3679 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3680 #endif 3681 3682 mutex_enter(&sc->sc_lock); 3683 3684 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3685 ehci_set_qh_qtd(sqh, setup); 3686 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3687 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3688 ehci_timeout, xfer); 3689 } 3690 ehci_add_intr_list(sc, exfer); 3691 xfer->ux_status = USBD_IN_PROGRESS; 3692 mutex_exit(&sc->sc_lock); 3693 3694 #if 0 3695 #ifdef EHCI_DEBUG 3696 DPRINTFN(10, "status=%x, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3697 // delay(10000); 3698 ehci_dump_regs(sc); 3699 ehci_dump_sqh(sc->sc_async_head); 3700 ehci_dump_sqh(sqh); 3701 ehci_dump_sqtds(setup); 3702 #endif 3703 #endif 3704 3705 if (sc->sc_bus.ub_usepolling) 3706 ehci_waitintr(sc, xfer); 3707 3708 return USBD_IN_PROGRESS; 3709 } 3710 3711 Static void 3712 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3713 { 3714 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3715 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3716 usb_device_request_t *req = &xfer->ux_request; 3717 int len = UGETW(req->wLength); 3718 int rd = req->bmRequestType & UT_READ; 3719 3720 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3721 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3722 3723 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3724 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3725 3726 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3727 BUS_DMASYNC_POSTWRITE); 3728 if (len) 3729 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3730 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3731 3732 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3733 } 3734 3735 /* Abort a device control request. */ 3736 Static void 3737 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3738 { 3739 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3740 3741 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3742 ehci_abort_xfer(xfer, USBD_CANCELLED); 3743 } 3744 3745 /* Close a device control pipe. */ 3746 Static void 3747 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3748 { 3749 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3750 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3751 3752 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3753 3754 KASSERT(mutex_owned(&sc->sc_lock)); 3755 3756 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3757 3758 ehci_close_pipe(pipe, sc->sc_async_head); 3759 } 3760 3761 /* 3762 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3763 * qTD status, or miss signalling occasionally under heavy load. If the host 3764 * machine is too fast, we we can miss transaction completion - when we scan 3765 * the active list the transaction still seems to be active. This generally 3766 * exhibits itself as a umass stall that never recovers. 3767 * 3768 * We work around this behaviour by setting up this callback after any softintr 3769 * that completes with transactions still pending, giving us another chance to 3770 * check for completion after the writeback has taken place. 3771 */ 3772 Static void 3773 ehci_intrlist_timeout(void *arg) 3774 { 3775 ehci_softc_t *sc = arg; 3776 3777 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3778 3779 usb_schedsoftintr(&sc->sc_bus); 3780 } 3781 3782 /************************/ 3783 3784 Static int 3785 ehci_device_bulk_init(struct usbd_xfer *xfer) 3786 { 3787 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3788 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3789 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3790 int endpt = ed->bEndpointAddress; 3791 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3792 int len = xfer->ux_bufsize; 3793 int err = 0; 3794 3795 exfer->ex_type = EX_BULK; 3796 exfer->ex_nsqtd = 0; 3797 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3798 &exfer->ex_sqtdstart); 3799 3800 return err; 3801 } 3802 3803 Static void 3804 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3805 { 3806 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3807 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3808 3809 KASSERT(ex->ex_type == EX_BULK); 3810 3811 ehci_free_sqtds(sc, ex); 3812 if (ex->ex_nsqtd) 3813 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3814 } 3815 3816 Static usbd_status 3817 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3818 { 3819 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3820 usbd_status err; 3821 3822 /* Insert last in queue. */ 3823 mutex_enter(&sc->sc_lock); 3824 err = usb_insert_transfer(xfer); 3825 mutex_exit(&sc->sc_lock); 3826 if (err) 3827 return err; 3828 3829 /* Pipe isn't running, start first */ 3830 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3831 } 3832 3833 Static usbd_status 3834 ehci_device_bulk_start(struct usbd_xfer *xfer) 3835 { 3836 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3837 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3838 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3839 ehci_soft_qh_t *sqh; 3840 ehci_soft_qtd_t *end; 3841 int len, isread, endpt; 3842 3843 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3844 3845 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3846 xfer->ux_flags, 0); 3847 3848 if (sc->sc_dying) 3849 return USBD_IOERROR; 3850 3851 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3852 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3853 3854 len = xfer->ux_length; 3855 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3856 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3857 sqh = epipe->sqh; 3858 3859 KASSERT(exfer->ex_isdone); 3860 #ifdef DIAGNOSTIC 3861 exfer->ex_isdone = false; 3862 #endif 3863 3864 /* Take lock here to protect nexttoggle */ 3865 mutex_enter(&sc->sc_lock); 3866 3867 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3868 3869 exfer->ex_sqtdend = end; 3870 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3871 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3872 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3873 3874 #ifdef EHCI_DEBUG 3875 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3876 ehci_dump_sqh(sqh); 3877 ehci_dump_sqtds(exfer->ex_sqtdstart); 3878 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3879 #endif 3880 3881 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3882 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3883 3884 /* also does usb_syncmem(sqh) */ 3885 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3886 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3887 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3888 ehci_timeout, xfer); 3889 } 3890 ehci_add_intr_list(sc, exfer); 3891 xfer->ux_status = USBD_IN_PROGRESS; 3892 mutex_exit(&sc->sc_lock); 3893 3894 #if 0 3895 #ifdef EHCI_DEBUG 3896 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3897 // delay(10000); 3898 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3899 ehci_dump_regs(sc); 3900 #if 0 3901 printf("async_head:\n"); 3902 ehci_dump_sqh(sc->sc_async_head); 3903 #endif 3904 DPRINTF("sqh:", 0, 0, 0, 0); 3905 ehci_dump_sqh(sqh); 3906 ehci_dump_sqtds(exfer->ex_sqtdstart); 3907 #endif 3908 #endif 3909 3910 if (sc->sc_bus.ub_usepolling) 3911 ehci_waitintr(sc, xfer); 3912 3913 return USBD_IN_PROGRESS; 3914 } 3915 3916 Static void 3917 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3918 { 3919 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3920 3921 DPRINTF("xfer %p", xfer, 0, 0, 0); 3922 ehci_abort_xfer(xfer, USBD_CANCELLED); 3923 } 3924 3925 /* 3926 * Close a device bulk pipe. 3927 */ 3928 Static void 3929 ehci_device_bulk_close(struct usbd_pipe *pipe) 3930 { 3931 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3932 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3933 3934 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3935 3936 KASSERT(mutex_owned(&sc->sc_lock)); 3937 3938 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3939 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3940 ehci_close_pipe(pipe, sc->sc_async_head); 3941 } 3942 3943 Static void 3944 ehci_device_bulk_done(struct usbd_xfer *xfer) 3945 { 3946 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3947 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3948 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3949 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3950 3951 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3952 3953 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 3954 3955 KASSERT(mutex_owned(&sc->sc_lock)); 3956 3957 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3958 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3959 3960 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3961 } 3962 3963 /************************/ 3964 3965 Static usbd_status 3966 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3967 { 3968 struct ehci_soft_islot *isp; 3969 int islot, lev; 3970 3971 /* Find a poll rate that is large enough. */ 3972 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3973 if (EHCI_ILEV_IVAL(lev) <= ival) 3974 break; 3975 3976 /* Pick an interrupt slot at the right level. */ 3977 /* XXX could do better than picking at random */ 3978 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3979 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3980 3981 sqh->islot = islot; 3982 isp = &sc->sc_islots[islot]; 3983 mutex_enter(&sc->sc_lock); 3984 ehci_add_qh(sc, sqh, isp->sqh); 3985 mutex_exit(&sc->sc_lock); 3986 3987 return USBD_NORMAL_COMPLETION; 3988 } 3989 3990 3991 Static int 3992 ehci_device_intr_init(struct usbd_xfer *xfer) 3993 { 3994 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3995 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3996 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3997 int endpt = ed->bEndpointAddress; 3998 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3999 int len = xfer->ux_bufsize; 4000 int err; 4001 4002 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4003 4004 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4005 xfer->ux_flags, 0); 4006 4007 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4008 KASSERT(len != 0); 4009 4010 exfer->ex_type = EX_INTR; 4011 exfer->ex_nsqtd = 0; 4012 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4013 &exfer->ex_sqtdstart); 4014 4015 return err; 4016 } 4017 4018 Static void 4019 ehci_device_intr_fini(struct usbd_xfer *xfer) 4020 { 4021 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4022 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4023 4024 KASSERT(ex->ex_type == EX_INTR); 4025 4026 ehci_free_sqtds(sc, ex); 4027 if (ex->ex_nsqtd) 4028 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4029 } 4030 4031 Static usbd_status 4032 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4033 { 4034 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4035 usbd_status err; 4036 4037 /* Insert last in queue. */ 4038 mutex_enter(&sc->sc_lock); 4039 err = usb_insert_transfer(xfer); 4040 mutex_exit(&sc->sc_lock); 4041 if (err) 4042 return err; 4043 4044 /* 4045 * Pipe isn't running (otherwise err would be USBD_INPROG), 4046 * so start it first. 4047 */ 4048 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4049 } 4050 4051 Static usbd_status 4052 ehci_device_intr_start(struct usbd_xfer *xfer) 4053 { 4054 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4055 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4056 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4057 ehci_soft_qtd_t *end; 4058 ehci_soft_qh_t *sqh; 4059 int len, isread, endpt; 4060 4061 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4062 4063 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4064 xfer->ux_flags, 0); 4065 4066 if (sc->sc_dying) 4067 return USBD_IOERROR; 4068 4069 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4070 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4071 4072 len = xfer->ux_length; 4073 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4074 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4075 sqh = epipe->sqh; 4076 4077 KASSERT(exfer->ex_isdone); 4078 #ifdef DIAGNOSTIC 4079 exfer->ex_isdone = false; 4080 #endif 4081 4082 /* Take lock to protect nexttoggle */ 4083 mutex_enter(&sc->sc_lock); 4084 4085 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4086 4087 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4088 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4089 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4090 exfer->ex_sqtdend = end; 4091 4092 #ifdef EHCI_DEBUG 4093 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4094 ehci_dump_sqh(sqh); 4095 ehci_dump_sqtds(exfer->ex_sqtdstart); 4096 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4097 #endif 4098 4099 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4100 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4101 4102 /* also does usb_syncmem(sqh) */ 4103 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4104 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4105 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4106 ehci_timeout, xfer); 4107 } 4108 ehci_add_intr_list(sc, exfer); 4109 xfer->ux_status = USBD_IN_PROGRESS; 4110 mutex_exit(&sc->sc_lock); 4111 4112 #if 0 4113 #ifdef EHCI_DEBUG 4114 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4115 // delay(10000); 4116 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4117 ehci_dump_regs(sc); 4118 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4119 ehci_dump_sqh(sqh); 4120 ehci_dump_sqtds(exfer->ex_sqtdstart); 4121 #endif 4122 #endif 4123 4124 if (sc->sc_bus.ub_usepolling) 4125 ehci_waitintr(sc, xfer); 4126 4127 return USBD_IN_PROGRESS; 4128 } 4129 4130 Static void 4131 ehci_device_intr_abort(struct usbd_xfer *xfer) 4132 { 4133 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4134 4135 DPRINTF("xfer=%p", xfer, 0, 0, 0); 4136 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4137 4138 /* 4139 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4140 * async doorbell. That's dependent on the async list, wheras 4141 * intr xfers are periodic, should not use this? 4142 */ 4143 ehci_abort_xfer(xfer, USBD_CANCELLED); 4144 } 4145 4146 Static void 4147 ehci_device_intr_close(struct usbd_pipe *pipe) 4148 { 4149 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4150 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4151 struct ehci_soft_islot *isp; 4152 4153 KASSERT(mutex_owned(&sc->sc_lock)); 4154 4155 isp = &sc->sc_islots[epipe->sqh->islot]; 4156 ehci_close_pipe(pipe, isp->sqh); 4157 } 4158 4159 Static void 4160 ehci_device_intr_done(struct usbd_xfer *xfer) 4161 { 4162 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4163 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4164 int isread, endpt; 4165 4166 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4167 4168 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4169 0, 0); 4170 4171 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4172 4173 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4174 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4175 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4176 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4177 } 4178 4179 /************************/ 4180 Static int 4181 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4182 { 4183 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4184 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4185 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4186 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4187 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4188 int i, k, frames; 4189 u_int huba, dir; 4190 int err; 4191 4192 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4193 4194 start = NULL; 4195 sitd = NULL; 4196 4197 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4198 xfer->ux_flags, 0); 4199 4200 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4201 KASSERT(xfer->ux_nframes != 0); 4202 KASSERT(exfer->ex_isdone); 4203 4204 exfer->ex_type = EX_FS_ISOC; 4205 /* 4206 * Step 1: Allocate and initialize sitds. 4207 */ 4208 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4209 if (i > 16 || i == 0) { 4210 /* Spec page 271 says intervals > 16 are invalid */ 4211 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4212 4213 return EINVAL; 4214 } 4215 4216 frames = xfer->ux_nframes; 4217 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4218 sitd = ehci_alloc_sitd(sc); 4219 if (sitd == NULL) { 4220 err = ENOMEM; 4221 goto fail; 4222 } 4223 4224 if (prev) 4225 prev->xfer_next = sitd; 4226 else 4227 start = sitd; 4228 4229 huba = dev->ud_myhsport->up_parent->ud_addr; 4230 4231 #if 0 4232 if (sc->sc_flags & EHCIF_FREESCALE) { 4233 // Set hub address to 0 if embedded TT is used. 4234 if (huba == sc->sc_addr) 4235 huba = 0; 4236 } 4237 #endif 4238 4239 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4240 dir = UE_GET_DIR(k) ? 1 : 0; 4241 sitd->sitd.sitd_endp = 4242 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4243 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4244 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4245 EHCI_SITD_SET_HUBA(huba) | 4246 EHCI_SITD_SET_DIR(dir)); 4247 4248 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4249 } /* End of frame */ 4250 4251 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4252 4253 stop = sitd; 4254 stop->xfer_next = NULL; 4255 exfer->ex_sitdstart = start; 4256 exfer->ex_sitdend = stop; 4257 4258 return 0; 4259 4260 fail: 4261 mutex_enter(&sc->sc_lock); 4262 ehci_soft_sitd_t *next; 4263 for (sitd = start; sitd; sitd = next) { 4264 next = sitd->xfer_next; 4265 ehci_free_sitd_locked(sc, sitd); 4266 } 4267 mutex_exit(&sc->sc_lock); 4268 4269 return err; 4270 } 4271 4272 Static void 4273 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4274 { 4275 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4276 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4277 4278 KASSERT(ex->ex_type == EX_FS_ISOC); 4279 4280 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4281 } 4282 4283 Static usbd_status 4284 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4285 { 4286 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4287 usbd_status __diagused err; 4288 4289 mutex_enter(&sc->sc_lock); 4290 err = usb_insert_transfer(xfer); 4291 mutex_exit(&sc->sc_lock); 4292 4293 KASSERT(err == USBD_NORMAL_COMPLETION); 4294 4295 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4296 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4297 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4298 ehci_soft_sitd_t *sitd; 4299 usb_dma_t *dma_buf; 4300 int i, j, k, frames; 4301 int offs, total_length; 4302 int frindex; 4303 u_int dir; 4304 4305 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4306 4307 sitd = NULL; 4308 total_length = 0; 4309 4310 4311 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4312 xfer->ux_flags, 0); 4313 4314 if (sc->sc_dying) 4315 return USBD_IOERROR; 4316 4317 /* 4318 * To avoid complication, don't allow a request right now that'll span 4319 * the entire frame table. To within 4 frames, to allow some leeway 4320 * on either side of where the hc currently is. 4321 */ 4322 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4323 xfer->ux_nframes >= sc->sc_flsize - 4) { 4324 printf("ehci: isoc descriptor requested that spans the entire" 4325 "frametable, too many frames\n"); 4326 return USBD_INVAL; 4327 } 4328 4329 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4330 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4331 KASSERT(exfer->ex_isdone); 4332 #ifdef DIAGNOSTIC 4333 exfer->ex_isdone = false; 4334 #endif 4335 4336 /* 4337 * Step 1: Initialize sitds. 4338 */ 4339 4340 frames = xfer->ux_nframes; 4341 dma_buf = &xfer->ux_dmabuf; 4342 offs = 0; 4343 4344 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4345 i++, sitd = sitd->xfer_next) { 4346 KASSERT(sitd != NULL); 4347 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4348 4349 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4350 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4351 4352 /* Set page0 index and offset - TP and T-offset are set below */ 4353 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4354 4355 total_length += xfer->ux_frlengths[i]; 4356 offs += xfer->ux_frlengths[i]; 4357 4358 sitd->sitd.sitd_buffer[1] = 4359 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4360 4361 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4362 4363 #if 0 4364 if (sc->sc_flags & EHCIF_FREESCALE) { 4365 // Set hub address to 0 if embedded TT is used. 4366 if (huba == sc->sc_addr) 4367 huba = 0; 4368 } 4369 #endif 4370 4371 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4372 dir = UE_GET_DIR(k) ? 1 : 0; 4373 KASSERT(sitd->sitd.sitd_endp == htole32( 4374 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4375 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4376 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4377 EHCI_SITD_SET_HUBA(huba) | 4378 EHCI_SITD_SET_DIR(dir))); 4379 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4380 4381 uint8_t sa = 0; 4382 uint8_t sb = 0; 4383 u_int temp, tlen; 4384 4385 if (dir == 0) { /* OUT */ 4386 temp = 0; 4387 tlen = xfer->ux_frlengths[i]; 4388 if (tlen <= 188) { 4389 temp |= 1; /* T-count = 1, TP = ALL */ 4390 tlen = 1; 4391 } else { 4392 tlen += 187; 4393 tlen /= 188; 4394 temp |= tlen; /* T-count = [1..6] */ 4395 temp |= 8; /* TP = Begin */ 4396 } 4397 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4398 4399 tlen += sa; 4400 4401 if (tlen >= 8) { 4402 sb = 0; 4403 } else { 4404 sb = (1 << tlen); 4405 } 4406 4407 sa = (1 << sa); 4408 sa = (sb - sa) & 0x3F; 4409 sb = 0; 4410 } else { 4411 sb = (-(4 << sa)) & 0xFE; 4412 sa = (1 << sa) & 0x3F; 4413 sa = 0x01; 4414 sb = 0xfc; 4415 } 4416 4417 sitd->sitd.sitd_sched = htole32( 4418 EHCI_SITD_SET_SMASK(sa) | 4419 EHCI_SITD_SET_CMASK(sb) 4420 ); 4421 4422 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4423 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4424 } /* End of frame */ 4425 4426 sitd = exfer->ex_sitdend; 4427 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4428 4429 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4430 sizeof(sitd->sitd.sitd_trans), 4431 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4432 4433 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4434 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4435 4436 /* 4437 * Part 2: Transfer descriptors have now been set up, now they must 4438 * be scheduled into the periodic frame list. Erk. Not wanting to 4439 * complicate matters, transfer is denied if the transfer spans 4440 * more than the period frame list. 4441 */ 4442 4443 mutex_enter(&sc->sc_lock); 4444 4445 /* Start inserting frames */ 4446 if (epipe->isoc.cur_xfers > 0) { 4447 frindex = epipe->isoc.next_frame; 4448 } else { 4449 frindex = EOREAD4(sc, EHCI_FRINDEX); 4450 frindex = frindex >> 3; /* Erase microframe index */ 4451 frindex += 2; 4452 } 4453 4454 if (frindex >= sc->sc_flsize) 4455 frindex &= (sc->sc_flsize - 1); 4456 4457 /* Whats the frame interval? */ 4458 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4459 4460 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4461 j++, sitd = sitd->xfer_next) { 4462 KASSERT(sitd); 4463 4464 usb_syncmem(&sc->sc_fldma, 4465 sizeof(ehci_link_t) * frindex, 4466 sizeof(ehci_link_t), 4467 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4468 4469 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4470 if (sitd->sitd.sitd_next == 0) 4471 /* 4472 * FIXME: frindex table gets initialized to NULL 4473 * or EHCI_NULL? 4474 */ 4475 sitd->sitd.sitd_next = EHCI_NULL; 4476 4477 usb_syncmem(&sitd->dma, 4478 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4479 sizeof(ehci_sitd_t), 4480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4481 4482 sc->sc_flist[frindex] = 4483 htole32(EHCI_LINK_SITD | sitd->physaddr); 4484 4485 usb_syncmem(&sc->sc_fldma, 4486 sizeof(ehci_link_t) * frindex, 4487 sizeof(ehci_link_t), 4488 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4489 4490 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4491 sc->sc_softsitds[frindex] = sitd; 4492 if (sitd->frame_list.next != NULL) 4493 sitd->frame_list.next->frame_list.prev = sitd; 4494 sitd->slot = frindex; 4495 sitd->frame_list.prev = NULL; 4496 4497 frindex += i; 4498 if (frindex >= sc->sc_flsize) 4499 frindex -= sc->sc_flsize; 4500 } 4501 4502 epipe->isoc.cur_xfers++; 4503 epipe->isoc.next_frame = frindex; 4504 4505 ehci_add_intr_list(sc, exfer); 4506 xfer->ux_status = USBD_IN_PROGRESS; 4507 4508 mutex_exit(&sc->sc_lock); 4509 4510 if (sc->sc_bus.ub_usepolling) { 4511 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4512 ehci_waitintr(sc, xfer); 4513 } 4514 4515 return USBD_IN_PROGRESS; 4516 } 4517 4518 Static void 4519 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4520 { 4521 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4522 4523 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4524 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4525 } 4526 4527 Static void 4528 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4529 { 4530 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4531 4532 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4533 } 4534 4535 Static void 4536 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4537 { 4538 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4539 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4540 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4541 4542 KASSERT(mutex_owned(&sc->sc_lock)); 4543 4544 epipe->isoc.cur_xfers--; 4545 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4546 4547 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4548 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4549 } 4550 4551 4552 /************************/ 4553 4554 4555 Static int 4556 ehci_device_isoc_init(struct usbd_xfer *xfer) 4557 { 4558 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4559 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4560 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4561 ehci_soft_itd_t *itd, *prev, *start, *stop; 4562 int i, j, k; 4563 int frames, ufrperframe; 4564 int err; 4565 4566 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4567 4568 start = NULL; 4569 prev = NULL; 4570 itd = NULL; 4571 4572 KASSERT(xfer->ux_nframes != 0); 4573 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4574 KASSERT(exfer->ex_isdone); 4575 4576 exfer->ex_type = EX_ISOC; 4577 4578 /* 4579 * Step 1: Allocate and initialize itds, how many do we need? 4580 * One per transfer if interval >= 8 microframes, less if we use 4581 * multiple microframes per frame. 4582 */ 4583 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4584 if (i > 16 || i == 0) { 4585 /* Spec page 271 says intervals > 16 are invalid */ 4586 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4587 return USBD_INVAL; 4588 } 4589 4590 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4591 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4592 4593 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4594 itd = ehci_alloc_itd(sc); 4595 if (itd == NULL) { 4596 err = ENOMEM; 4597 goto fail; 4598 } 4599 4600 if (prev != NULL) { 4601 /* Maybe not as it's updated by the scheduling? */ 4602 prev->itd.itd_next = 4603 htole32(itd->physaddr | EHCI_LINK_ITD); 4604 4605 prev->xfer_next = itd; 4606 } else { 4607 start = itd; 4608 } 4609 4610 /* 4611 * Other special values 4612 */ 4613 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4614 itd->itd.itd_bufr[0] = htole32( 4615 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4616 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4617 4618 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4619 ? 1 : 0; 4620 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4621 itd->itd.itd_bufr[1] |= htole32( 4622 EHCI_ITD_SET_DIR(k) | 4623 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4624 4625 /* FIXME: handle invalid trans - should be done in openpipe */ 4626 itd->itd.itd_bufr[2] |= 4627 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4628 } /* End of frame */ 4629 4630 stop = itd; 4631 stop->xfer_next = NULL; 4632 4633 exfer->ex_itdstart = start; 4634 exfer->ex_itdend = stop; 4635 4636 return 0; 4637 fail: 4638 mutex_enter(&sc->sc_lock); 4639 ehci_soft_itd_t *next; 4640 for (itd = start; itd; itd = next) { 4641 next = itd->xfer_next; 4642 ehci_free_itd_locked(sc, itd); 4643 } 4644 mutex_exit(&sc->sc_lock); 4645 4646 return err; 4647 4648 } 4649 4650 Static void 4651 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4652 { 4653 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4654 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4655 4656 KASSERT(ex->ex_type == EX_ISOC); 4657 4658 ehci_free_itd_chain(sc, ex->ex_itdstart); 4659 } 4660 4661 Static usbd_status 4662 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4663 { 4664 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4665 usbd_status __diagused err; 4666 4667 mutex_enter(&sc->sc_lock); 4668 err = usb_insert_transfer(xfer); 4669 mutex_exit(&sc->sc_lock); 4670 4671 KASSERT(err == USBD_NORMAL_COMPLETION); 4672 4673 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4674 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4675 ehci_soft_itd_t *itd, *prev; 4676 usb_dma_t *dma_buf; 4677 int i, j; 4678 int frames, uframes, ufrperframe; 4679 int trans_count, offs, total_length; 4680 int frindex; 4681 4682 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4683 4684 prev = NULL; 4685 itd = NULL; 4686 trans_count = 0; 4687 total_length = 0; 4688 4689 DPRINTF("xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4690 4691 if (sc->sc_dying) 4692 return USBD_IOERROR; 4693 4694 /* 4695 * To avoid complication, don't allow a request right now that'll span 4696 * the entire frame table. To within 4 frames, to allow some leeway 4697 * on either side of where the hc currently is. 4698 */ 4699 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4700 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4701 DPRINTF( 4702 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4703 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4704 return USBD_INVAL; 4705 } 4706 4707 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4708 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4709 KASSERT(exfer->ex_isdone); 4710 #ifdef DIAGNOSTIC 4711 exfer->ex_isdone = false; 4712 #endif 4713 4714 /* 4715 * Step 1: Re-Initialize itds 4716 */ 4717 4718 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4719 if (i > 16 || i == 0) { 4720 /* Spec page 271 says intervals > 16 are invalid */ 4721 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4722 return USBD_INVAL; 4723 } 4724 4725 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4726 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4727 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4728 4729 if (frames == 0) { 4730 DPRINTF("frames == 0", 0, 0, 0, 0); 4731 return USBD_INVAL; 4732 } 4733 4734 dma_buf = &xfer->ux_dmabuf; 4735 offs = 0; 4736 4737 itd = exfer->ex_itdstart; 4738 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4739 int froffs = offs; 4740 4741 if (prev != NULL) { 4742 prev->itd.itd_next = 4743 htole32(itd->physaddr | EHCI_LINK_ITD); 4744 usb_syncmem(&prev->dma, 4745 prev->offs + offsetof(ehci_itd_t, itd_next), 4746 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4747 prev->xfer_next = itd; 4748 } 4749 4750 /* 4751 * Step 1.5, initialize uframes 4752 */ 4753 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4754 /* Calculate which page in the list this starts in */ 4755 int addr = DMAADDR(dma_buf, froffs); 4756 addr = EHCI_PAGE_OFFSET(addr); 4757 addr += (offs - froffs); 4758 addr = EHCI_PAGE(addr); 4759 addr /= EHCI_PAGE_SIZE; 4760 4761 /* 4762 * This gets the initial offset into the first page, 4763 * looks how far further along the current uframe 4764 * offset is. Works out how many pages that is. 4765 */ 4766 4767 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4768 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4769 EHCI_ITD_SET_PG(addr) | 4770 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4771 4772 total_length += xfer->ux_frlengths[trans_count]; 4773 offs += xfer->ux_frlengths[trans_count]; 4774 trans_count++; 4775 4776 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4777 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4778 break; 4779 } 4780 } 4781 4782 /* 4783 * Step 1.75, set buffer pointers. To simplify matters, all 4784 * pointers are filled out for the next 7 hardware pages in 4785 * the dma block, so no need to worry what pages to cover 4786 * and what to not. 4787 */ 4788 4789 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4790 /* 4791 * Don't try to lookup a page that's past the end 4792 * of buffer 4793 */ 4794 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4795 if (page_offs >= dma_buf->udma_block->size) 4796 break; 4797 4798 uint64_t page = DMAADDR(dma_buf, page_offs); 4799 page = EHCI_PAGE(page); 4800 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4801 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4802 } 4803 /* 4804 * Other special values 4805 */ 4806 4807 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4808 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4809 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4810 4811 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4812 ? 1 : 0; 4813 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4814 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4815 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4816 4817 /* FIXME: handle invalid trans */ 4818 itd->itd.itd_bufr[2] |= 4819 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4820 4821 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4822 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4823 4824 prev = itd; 4825 } /* End of frame */ 4826 4827 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4828 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4829 4830 /* 4831 * Part 2: Transfer descriptors have now been set up, now they must 4832 * be scheduled into the period frame list. Erk. Not wanting to 4833 * complicate matters, transfer is denied if the transfer spans 4834 * more than the period frame list. 4835 */ 4836 4837 mutex_enter(&sc->sc_lock); 4838 4839 /* Start inserting frames */ 4840 if (epipe->isoc.cur_xfers > 0) { 4841 frindex = epipe->isoc.next_frame; 4842 } else { 4843 frindex = EOREAD4(sc, EHCI_FRINDEX); 4844 frindex = frindex >> 3; /* Erase microframe index */ 4845 frindex += 2; 4846 } 4847 4848 if (frindex >= sc->sc_flsize) 4849 frindex &= (sc->sc_flsize - 1); 4850 4851 /* What's the frame interval? */ 4852 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4853 if (i / USB_UFRAMES_PER_FRAME == 0) 4854 i = 1; 4855 else 4856 i /= USB_UFRAMES_PER_FRAME; 4857 4858 itd = exfer->ex_itdstart; 4859 for (j = 0; j < frames; j++) { 4860 KASSERTMSG(itd != NULL, "frame %d\n", j); 4861 4862 usb_syncmem(&sc->sc_fldma, 4863 sizeof(ehci_link_t) * frindex, 4864 sizeof(ehci_link_t), 4865 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4866 4867 itd->itd.itd_next = sc->sc_flist[frindex]; 4868 if (itd->itd.itd_next == 0) 4869 /* 4870 * FIXME: frindex table gets initialized to NULL 4871 * or EHCI_NULL? 4872 */ 4873 itd->itd.itd_next = EHCI_NULL; 4874 4875 usb_syncmem(&itd->dma, 4876 itd->offs + offsetof(ehci_itd_t, itd_next), 4877 sizeof(itd->itd.itd_next), 4878 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4879 4880 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4881 4882 usb_syncmem(&sc->sc_fldma, 4883 sizeof(ehci_link_t) * frindex, 4884 sizeof(ehci_link_t), 4885 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4886 4887 itd->frame_list.next = sc->sc_softitds[frindex]; 4888 sc->sc_softitds[frindex] = itd; 4889 if (itd->frame_list.next != NULL) 4890 itd->frame_list.next->frame_list.prev = itd; 4891 itd->slot = frindex; 4892 itd->frame_list.prev = NULL; 4893 4894 frindex += i; 4895 if (frindex >= sc->sc_flsize) 4896 frindex -= sc->sc_flsize; 4897 4898 itd = itd->xfer_next; 4899 } 4900 4901 epipe->isoc.cur_xfers++; 4902 epipe->isoc.next_frame = frindex; 4903 4904 ehci_add_intr_list(sc, exfer); 4905 xfer->ux_status = USBD_IN_PROGRESS; 4906 4907 mutex_exit(&sc->sc_lock); 4908 4909 if (sc->sc_bus.ub_usepolling) { 4910 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4911 ehci_waitintr(sc, xfer); 4912 } 4913 4914 return USBD_IN_PROGRESS; 4915 } 4916 4917 Static void 4918 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4919 { 4920 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4921 4922 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4923 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4924 } 4925 4926 Static void 4927 ehci_device_isoc_close(struct usbd_pipe *pipe) 4928 { 4929 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4930 4931 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4932 } 4933 4934 Static void 4935 ehci_device_isoc_done(struct usbd_xfer *xfer) 4936 { 4937 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4938 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4939 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4940 4941 KASSERT(mutex_owned(&sc->sc_lock)); 4942 4943 epipe->isoc.cur_xfers--; 4944 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4945 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4946 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4947 } 4948
Indexes created Thu Oct 02 01:09:59 GMT 2025