ehci.c revision 1.248
1 /* $NetBSD: ehci.c,v 1.248 2016/03/13 07:01:43 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.248 2016/03/13 07:01:43 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 #include <dev/usb/usbroothub_subr.h> 88 89 #include <dev/usb/ehcireg.h> 90 #include <dev/usb/ehcivar.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 struct ehci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 ehci_soft_qh_t *sqh; 134 union { 135 ehci_soft_qtd_t *qtd; 136 /* ehci_soft_itd_t *itd; */ 137 } tail; 138 union { 139 /* Control pipe */ 140 struct { 141 usb_dma_t reqdma; 142 } ctl; 143 /* Interrupt pipe */ 144 struct { 145 u_int length; 146 } intr; 147 /* Bulk pipe */ 148 struct { 149 u_int length; 150 } bulk; 151 /* Iso pipe */ 152 struct { 153 u_int next_frame; 154 u_int cur_xfers; 155 } isoc; 156 } u; 157 }; 158 159 Static usbd_status ehci_open(usbd_pipe_handle); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 164 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 167 Static void ehci_idone(struct ehci_xfer *); 168 Static void ehci_timeout(void *); 169 Static void ehci_timeout_task(void *); 170 Static void ehci_intrlist_timeout(void *); 171 Static void ehci_doorbell(void *); 172 Static void ehci_pcd(void *); 173 174 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 175 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 176 177 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 178 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 181 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 182 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 183 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 184 Static void ehci_root_ctrl_close(usbd_pipe_handle); 185 Static void ehci_root_ctrl_done(usbd_xfer_handle); 186 187 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 188 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 189 Static void ehci_root_intr_abort(usbd_xfer_handle); 190 Static void ehci_root_intr_close(usbd_pipe_handle); 191 Static void ehci_root_intr_done(usbd_xfer_handle); 192 193 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 194 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 195 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 196 Static void ehci_device_ctrl_close(usbd_pipe_handle); 197 Static void ehci_device_ctrl_done(usbd_xfer_handle); 198 199 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 200 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 201 Static void ehci_device_bulk_abort(usbd_xfer_handle); 202 Static void ehci_device_bulk_close(usbd_pipe_handle); 203 Static void ehci_device_bulk_done(usbd_xfer_handle); 204 205 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 206 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 207 Static void ehci_device_intr_abort(usbd_xfer_handle); 208 Static void ehci_device_intr_close(usbd_pipe_handle); 209 Static void ehci_device_intr_done(usbd_xfer_handle); 210 211 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 212 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 213 Static void ehci_device_isoc_abort(usbd_xfer_handle); 214 Static void ehci_device_isoc_close(usbd_pipe_handle); 215 Static void ehci_device_isoc_done(usbd_xfer_handle); 216 217 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 218 Static void ehci_noop(usbd_pipe_handle pipe); 219 220 Static void ehci_disown(ehci_softc_t *, int, int); 221 222 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 223 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 224 225 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 226 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 227 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 228 ehci_softc_t *, int, int, usbd_xfer_handle, 229 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 230 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 231 ehci_soft_qtd_t *); 232 233 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 234 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 236 struct ehci_xfer *exfer); 237 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 238 usbd_status status); 239 240 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 241 242 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 243 int ival); 244 245 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 246 ehci_soft_qh_t *); 247 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 250 Static void ehci_sync_hc(ehci_softc_t *); 251 252 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 253 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 254 255 #ifdef EHCI_DEBUG 256 Static ehci_softc_t *theehci; 257 void ehci_dump(void); 258 #endif 259 260 #ifdef EHCI_DEBUG 261 Static void ehci_dump_regs(ehci_softc_t *); 262 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 263 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 264 Static void ehci_dump_qtd(ehci_qtd_t *); 265 Static void ehci_dump_sqh(ehci_soft_qh_t *); 266 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 267 Static void ehci_dump_itd(struct ehci_soft_itd *); 268 Static void ehci_dump_exfer(struct ehci_xfer *); 269 #endif 270 271 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 272 273 #define EHCI_INTR_ENDPT 1 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 280 (ex)->inext.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .open_pipe = ehci_open, 286 .soft_intr = ehci_softintr, 287 .do_poll = ehci_poll, 288 .allocm = ehci_allocm, 289 .freem = ehci_freem, 290 .allocx = ehci_allocx, 291 .freex = ehci_freex, 292 .get_lock = ehci_get_lock, 293 .new_device = NULL, 294 }; 295 296 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 297 .transfer = ehci_root_ctrl_transfer, 298 .start = ehci_root_ctrl_start, 299 .abort = ehci_root_ctrl_abort, 300 .close = ehci_root_ctrl_close, 301 .cleartoggle = ehci_noop, 302 .done = ehci_root_ctrl_done, 303 }; 304 305 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 306 .transfer = ehci_root_intr_transfer, 307 .start = ehci_root_intr_start, 308 .abort = ehci_root_intr_abort, 309 .close = ehci_root_intr_close, 310 .cleartoggle = ehci_noop, 311 .done = ehci_root_intr_done, 312 }; 313 314 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 315 .transfer = ehci_device_ctrl_transfer, 316 .start = ehci_device_ctrl_start, 317 .abort = ehci_device_ctrl_abort, 318 .close = ehci_device_ctrl_close, 319 .cleartoggle = ehci_noop, 320 .done = ehci_device_ctrl_done, 321 }; 322 323 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 324 .transfer = ehci_device_intr_transfer, 325 .start = ehci_device_intr_start, 326 .abort = ehci_device_intr_abort, 327 .close = ehci_device_intr_close, 328 .cleartoggle = ehci_device_clear_toggle, 329 .done = ehci_device_intr_done, 330 }; 331 332 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 333 .transfer = ehci_device_bulk_transfer, 334 .start = ehci_device_bulk_start, 335 .abort = ehci_device_bulk_abort, 336 .close = ehci_device_bulk_close, 337 .cleartoggle = ehci_device_clear_toggle, 338 .done = ehci_device_bulk_done, 339 }; 340 341 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 342 .transfer = ehci_device_isoc_transfer, 343 .start = ehci_device_isoc_start, 344 .abort = ehci_device_isoc_abort, 345 .close = ehci_device_isoc_close, 346 .cleartoggle = ehci_noop, 347 .done = ehci_device_isoc_done, 348 }; 349 350 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 351 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 352 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 353 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 354 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 355 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 356 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 357 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 358 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 359 }; 360 361 usbd_status 362 ehci_init(ehci_softc_t *sc) 363 { 364 u_int32_t vers, sparams, cparams, hcr; 365 u_int i; 366 usbd_status err; 367 ehci_soft_qh_t *sqh; 368 u_int ncomp; 369 370 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 371 #ifdef EHCI_DEBUG 372 theehci = sc; 373 #endif 374 375 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 376 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 377 cv_init(&sc->sc_softwake_cv, "ehciab"); 378 cv_init(&sc->sc_doorbell, "ehcidi"); 379 380 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 381 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 382 383 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 384 ehci_doorbell, sc); 385 KASSERT(sc->sc_doorbell_si != NULL); 386 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 387 ehci_pcd, sc); 388 KASSERT(sc->sc_pcd_si != NULL); 389 390 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 391 392 vers = EREAD2(sc, EHCI_HCIVERSION); 393 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 394 vers >> 8, vers & 0xff); 395 396 sparams = EREAD4(sc, EHCI_HCSPARAMS); 397 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 398 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 399 ncomp = EHCI_HCS_N_CC(sparams); 400 if (ncomp != sc->sc_ncomp) { 401 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 402 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 403 #if NOHCI == 0 || NUHCI == 0 404 aprint_error("%s: ohci or uhci probably not configured\n", 405 device_xname(sc->sc_dev)); 406 #endif 407 if (ncomp < sc->sc_ncomp) 408 sc->sc_ncomp = ncomp; 409 } 410 if (sc->sc_ncomp > 0) { 411 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 412 aprint_normal("%s: companion controller%s, %d port%s each:", 413 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 414 EHCI_HCS_N_PCC(sparams), 415 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 416 for (i = 0; i < sc->sc_ncomp; i++) 417 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 418 aprint_normal("\n"); 419 } 420 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 421 cparams = EREAD4(sc, EHCI_HCCPARAMS); 422 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 423 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 424 425 if (EHCI_HCC_64BIT(cparams)) { 426 /* MUST clear segment register if 64 bit capable. */ 427 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 428 } 429 430 sc->sc_bus.usbrev = USBREV_2_0; 431 432 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 433 USB_MEM_RESERVE); 434 435 /* Reset the controller */ 436 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 437 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 438 usb_delay_ms(&sc->sc_bus, 1); 439 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 440 for (i = 0; i < 100; i++) { 441 usb_delay_ms(&sc->sc_bus, 1); 442 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 443 if (!hcr) 444 break; 445 } 446 if (hcr) { 447 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 448 return (USBD_IOERROR); 449 } 450 if (sc->sc_vendor_init) 451 sc->sc_vendor_init(sc); 452 453 /* XXX need proper intr scheduling */ 454 sc->sc_rand = 96; 455 456 /* frame list size at default, read back what we got and use that */ 457 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 458 case 0: sc->sc_flsize = 1024; break; 459 case 1: sc->sc_flsize = 512; break; 460 case 2: sc->sc_flsize = 256; break; 461 case 3: return (USBD_IOERROR); 462 } 463 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 464 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 465 if (err) 466 return (err); 467 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 468 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 469 470 for (i = 0; i < sc->sc_flsize; i++) { 471 sc->sc_flist[i] = EHCI_NULL; 472 } 473 474 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 475 476 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 477 KM_SLEEP); 478 if (sc->sc_softitds == NULL) 479 return ENOMEM; 480 LIST_INIT(&sc->sc_freeitds); 481 TAILQ_INIT(&sc->sc_intrhead); 482 483 /* Set up the bus struct. */ 484 sc->sc_bus.methods = &ehci_bus_methods; 485 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 486 487 sc->sc_eintrs = EHCI_NORMAL_INTRS; 488 489 /* 490 * Allocate the interrupt dummy QHs. These are arranged to give poll 491 * intervals that are powers of 2 times 1ms. 492 */ 493 for (i = 0; i < EHCI_INTRQHS; i++) { 494 sqh = ehci_alloc_sqh(sc); 495 if (sqh == NULL) { 496 err = USBD_NOMEM; 497 goto bad1; 498 } 499 sc->sc_islots[i].sqh = sqh; 500 } 501 for (i = 0; i < EHCI_INTRQHS; i++) { 502 sqh = sc->sc_islots[i].sqh; 503 if (i == 0) { 504 /* The last (1ms) QH terminates. */ 505 sqh->qh.qh_link = EHCI_NULL; 506 sqh->next = NULL; 507 } else { 508 /* Otherwise the next QH has half the poll interval */ 509 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 510 sqh->qh.qh_link = htole32(sqh->next->physaddr | 511 EHCI_LINK_QH); 512 } 513 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 514 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 515 sqh->qh.qh_curqtd = EHCI_NULL; 516 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 517 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 518 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 519 sqh->sqtd = NULL; 520 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 521 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 522 } 523 /* Point the frame list at the last level (128ms). */ 524 for (i = 0; i < sc->sc_flsize; i++) { 525 int j; 526 527 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 528 revbits[i & (EHCI_MAX_POLLRATE-1)]; 529 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 530 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 531 i)].sqh->physaddr); 532 } 533 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 534 BUS_DMASYNC_PREWRITE); 535 536 /* Allocate dummy QH that starts the async list. */ 537 sqh = ehci_alloc_sqh(sc); 538 if (sqh == NULL) { 539 err = USBD_NOMEM; 540 goto bad1; 541 } 542 /* Fill the QH */ 543 sqh->qh.qh_endp = 544 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 545 sqh->qh.qh_link = 546 htole32(sqh->physaddr | EHCI_LINK_QH); 547 sqh->qh.qh_curqtd = EHCI_NULL; 548 sqh->next = NULL; 549 /* Fill the overlay qTD */ 550 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 551 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 552 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 553 sqh->sqtd = NULL; 554 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 555 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 556 #ifdef EHCI_DEBUG 557 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 558 ehci_dump_sqh(sqh); 559 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 560 #endif 561 562 /* Point to async list */ 563 sc->sc_async_head = sqh; 564 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 565 566 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 567 568 /* Turn on controller */ 569 EOWRITE4(sc, EHCI_USBCMD, 570 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 571 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 572 EHCI_CMD_ASE | 573 EHCI_CMD_PSE | 574 EHCI_CMD_RS); 575 576 /* Take over port ownership */ 577 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 578 579 for (i = 0; i < 100; i++) { 580 usb_delay_ms(&sc->sc_bus, 1); 581 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 582 if (!hcr) 583 break; 584 } 585 if (hcr) { 586 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 587 return (USBD_IOERROR); 588 } 589 590 /* Enable interrupts */ 591 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 592 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 593 594 return (USBD_NORMAL_COMPLETION); 595 596 #if 0 597 bad2: 598 ehci_free_sqh(sc, sc->sc_async_head); 599 #endif 600 bad1: 601 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 602 return (err); 603 } 604 605 int 606 ehci_intr(void *v) 607 { 608 ehci_softc_t *sc = v; 609 int ret = 0; 610 611 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 612 613 if (sc == NULL) 614 return 0; 615 616 mutex_spin_enter(&sc->sc_intr_lock); 617 618 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 619 goto done; 620 621 /* If we get an interrupt while polling, then just ignore it. */ 622 if (sc->sc_bus.use_polling) { 623 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 624 625 if (intrs) 626 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 627 #ifdef DIAGNOSTIC 628 USBHIST_LOGN(ehcidebug, 16, 629 "ignored interrupt while polling", 0, 0, 0, 0); 630 #endif 631 goto done; 632 } 633 634 ret = ehci_intr1(sc); 635 636 done: 637 mutex_spin_exit(&sc->sc_intr_lock); 638 return ret; 639 } 640 641 Static int 642 ehci_intr1(ehci_softc_t *sc) 643 { 644 u_int32_t intrs, eintrs; 645 646 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 647 648 /* In case the interrupt occurs before initialization has completed. */ 649 if (sc == NULL) { 650 #ifdef DIAGNOSTIC 651 printf("ehci_intr1: sc == NULL\n"); 652 #endif 653 return (0); 654 } 655 656 KASSERT(mutex_owned(&sc->sc_intr_lock)); 657 658 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 659 if (!intrs) 660 return (0); 661 662 eintrs = intrs & sc->sc_eintrs; 663 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 664 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 665 if (!eintrs) 666 return (0); 667 668 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 669 sc->sc_bus.no_intrs++; 670 if (eintrs & EHCI_STS_IAA) { 671 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 672 kpreempt_disable(); 673 KASSERT(sc->sc_doorbell_si != NULL); 674 softint_schedule(sc->sc_doorbell_si); 675 kpreempt_enable(); 676 eintrs &= ~EHCI_STS_IAA; 677 } 678 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 679 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 680 eintrs & EHCI_STS_INT ? 1 : 0, 681 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 682 usb_schedsoftintr(&sc->sc_bus); 683 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 684 } 685 if (eintrs & EHCI_STS_HSE) { 686 printf("%s: unrecoverable error, controller halted\n", 687 device_xname(sc->sc_dev)); 688 /* XXX what else */ 689 } 690 if (eintrs & EHCI_STS_PCD) { 691 kpreempt_disable(); 692 KASSERT(sc->sc_pcd_si != NULL); 693 softint_schedule(sc->sc_pcd_si); 694 kpreempt_enable(); 695 eintrs &= ~EHCI_STS_PCD; 696 } 697 698 if (eintrs != 0) { 699 /* Block unprocessed interrupts. */ 700 sc->sc_eintrs &= ~eintrs; 701 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 702 printf("%s: blocking intrs 0x%x\n", 703 device_xname(sc->sc_dev), eintrs); 704 } 705 706 return (1); 707 } 708 709 Static void 710 ehci_doorbell(void *addr) 711 { 712 ehci_softc_t *sc = addr; 713 714 mutex_enter(&sc->sc_lock); 715 cv_broadcast(&sc->sc_doorbell); 716 mutex_exit(&sc->sc_lock); 717 } 718 719 Static void 720 ehci_pcd(void *addr) 721 { 722 ehci_softc_t *sc = addr; 723 usbd_xfer_handle xfer; 724 u_char *p; 725 int i, m; 726 727 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 728 729 mutex_enter(&sc->sc_lock); 730 xfer = sc->sc_intrxfer; 731 732 if (xfer == NULL) { 733 /* Just ignore the change. */ 734 goto done; 735 } 736 737 p = KERNADDR(&xfer->dmabuf, 0); 738 m = min(sc->sc_noport, xfer->length * 8 - 1); 739 memset(p, 0, xfer->length); 740 for (i = 1; i <= m; i++) { 741 /* Pick out CHANGE bits from the status reg. */ 742 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 743 p[i/8] |= 1 << (i%8); 744 if (i % 8 == 7) 745 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 746 p[i/8], 0, 0); 747 } 748 xfer->actlen = xfer->length; 749 xfer->status = USBD_NORMAL_COMPLETION; 750 751 usb_transfer_complete(xfer); 752 753 done: 754 mutex_exit(&sc->sc_lock); 755 } 756 757 Static void 758 ehci_softintr(void *v) 759 { 760 struct usbd_bus *bus = v; 761 ehci_softc_t *sc = bus->hci_private; 762 struct ehci_xfer *ex, *nextex; 763 764 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 765 766 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 767 768 /* 769 * The only explanation I can think of for why EHCI is as brain dead 770 * as UHCI interrupt-wise is that Intel was involved in both. 771 * An interrupt just tells us that something is done, we have no 772 * clue what, so we need to scan through all active transfers. :-( 773 */ 774 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 775 nextex = TAILQ_NEXT(ex, inext); 776 ehci_check_intr(sc, ex); 777 } 778 779 /* Schedule a callout to catch any dropped transactions. */ 780 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 781 !TAILQ_EMPTY(&sc->sc_intrhead)) 782 callout_reset(&sc->sc_tmo_intrlist, 783 hz, ehci_intrlist_timeout, sc); 784 785 if (sc->sc_softwake) { 786 sc->sc_softwake = 0; 787 cv_broadcast(&sc->sc_softwake_cv); 788 } 789 } 790 791 /* Check for an interrupt. */ 792 Static void 793 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 794 { 795 int attr; 796 797 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 798 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 799 800 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 801 802 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 803 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 804 ehci_check_itd_intr(sc, ex); 805 else 806 ehci_check_qh_intr(sc, ex); 807 808 return; 809 } 810 811 Static void 812 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 813 { 814 ehci_soft_qtd_t *sqtd, *lsqtd; 815 __uint32_t status; 816 817 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 818 819 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 820 821 if (ex->sqtdstart == NULL) { 822 printf("ehci_check_qh_intr: not valid sqtd\n"); 823 return; 824 } 825 826 lsqtd = ex->sqtdend; 827 #ifdef DIAGNOSTIC 828 if (lsqtd == NULL) { 829 printf("ehci_check_qh_intr: lsqtd==0\n"); 830 return; 831 } 832 #endif 833 /* 834 * If the last TD is still active we need to check whether there 835 * is an error somewhere in the middle, or whether there was a 836 * short packet (SPD and not ACTIVE). 837 */ 838 usb_syncmem(&lsqtd->dma, 839 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 840 sizeof(lsqtd->qtd.qtd_status), 841 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 842 status = le32toh(lsqtd->qtd.qtd_status); 843 usb_syncmem(&lsqtd->dma, 844 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 845 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 846 if (status & EHCI_QTD_ACTIVE) { 847 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 848 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 849 usb_syncmem(&sqtd->dma, 850 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 851 sizeof(sqtd->qtd.qtd_status), 852 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 853 status = le32toh(sqtd->qtd.qtd_status); 854 usb_syncmem(&sqtd->dma, 855 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 856 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 857 /* If there's an active QTD the xfer isn't done. */ 858 if (status & EHCI_QTD_ACTIVE) 859 break; 860 /* Any kind of error makes the xfer done. */ 861 if (status & EHCI_QTD_HALTED) 862 goto done; 863 /* Handle short packets */ 864 if (EHCI_QTD_GET_BYTES(status) != 0) { 865 usbd_pipe_handle pipe = ex->xfer.pipe; 866 usb_endpoint_descriptor_t *ed = 867 pipe->endpoint->edesc; 868 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 869 870 /* 871 * If we get here for a control transfer then 872 * we need to let the hardware complete the 873 * status phase. That is, we're not done 874 * quite yet. 875 * 876 * Otherwise, we're done. 877 */ 878 if (xt == UE_CONTROL) { 879 break; 880 } 881 goto done; 882 } 883 } 884 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 885 ex, ex->sqtdstart, 0, 0); 886 #ifdef EHCI_DEBUG 887 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 0, 0); 888 ehci_dump_sqtds(ex->sqtdstart); 889 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 0); 890 #endif 891 892 return; 893 } 894 done: 895 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 896 callout_stop(&ex->xfer.timeout_handle); 897 ehci_idone(ex); 898 } 899 900 Static void 901 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 902 { 903 ehci_soft_itd_t *itd; 904 int i; 905 906 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 907 908 KASSERT(mutex_owned(&sc->sc_lock)); 909 910 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 911 return; 912 913 if (ex->itdstart == NULL) { 914 printf("ehci_check_itd_intr: not valid itd\n"); 915 return; 916 } 917 918 itd = ex->itdend; 919 #ifdef DIAGNOSTIC 920 if (itd == NULL) { 921 printf("ehci_check_itd_intr: itdend == 0\n"); 922 return; 923 } 924 #endif 925 926 /* 927 * check no active transfers in last itd, meaning we're finished 928 */ 929 930 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 931 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 932 BUS_DMASYNC_POSTREAD); 933 934 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 935 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 936 break; 937 } 938 939 if (i == EHCI_ITD_NUFRAMES) { 940 goto done; /* All 8 descriptors inactive, it's done */ 941 } 942 943 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 944 ex->itdstart, 0, 0); 945 return; 946 done: 947 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 948 callout_stop(&ex->xfer.timeout_handle); 949 ehci_idone(ex); 950 } 951 952 Static void 953 ehci_idone(struct ehci_xfer *ex) 954 { 955 usbd_xfer_handle xfer = &ex->xfer; 956 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 957 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 958 ehci_soft_qtd_t *sqtd, *lsqtd; 959 u_int32_t status = 0, nstatus = 0; 960 int actlen; 961 962 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 963 964 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 965 966 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 967 968 #ifdef DIAGNOSTIC 969 if (ex->isdone) { 970 printf("ehci_idone: ex=%p is done!\n", ex); 971 #ifdef EHCI_DEBUG 972 ehci_dump_exfer(ex); 973 #endif 974 return; 975 } 976 ex->isdone = 1; 977 #endif 978 979 if (xfer->status == USBD_CANCELLED || 980 xfer->status == USBD_TIMEOUT) { 981 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 982 return; 983 } 984 985 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 986 #ifdef EHCI_DEBUG 987 ehci_dump_sqtds(ex->sqtdstart); 988 #endif 989 990 /* The transfer is done, compute actual length and status. */ 991 992 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 993 == UE_ISOCHRONOUS) { 994 /* Isoc transfer */ 995 struct ehci_soft_itd *itd; 996 int i, nframes, len, uframes; 997 998 nframes = 0; 999 actlen = 0; 1000 1001 i = xfer->pipe->endpoint->edesc->bInterval; 1002 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1003 1004 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1005 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1006 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1007 BUS_DMASYNC_POSTREAD); 1008 1009 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1010 /* XXX - driver didn't fill in the frame full 1011 * of uframes. This leads to scheduling 1012 * inefficiencies, but working around 1013 * this doubles complexity of tracking 1014 * an xfer. 1015 */ 1016 if (nframes >= xfer->nframes) 1017 break; 1018 1019 status = le32toh(itd->itd.itd_ctl[i]); 1020 len = EHCI_ITD_GET_LEN(status); 1021 if (EHCI_ITD_GET_STATUS(status) != 0) 1022 len = 0; /*No valid data on error*/ 1023 1024 xfer->frlengths[nframes++] = len; 1025 actlen += len; 1026 } 1027 1028 if (nframes >= xfer->nframes) 1029 break; 1030 } 1031 1032 xfer->actlen = actlen; 1033 xfer->status = USBD_NORMAL_COMPLETION; 1034 goto end; 1035 } 1036 1037 /* Continue processing xfers using queue heads */ 1038 1039 lsqtd = ex->sqtdend; 1040 actlen = 0; 1041 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 1042 sqtd = sqtd->nextqtd) { 1043 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1044 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1045 nstatus = le32toh(sqtd->qtd.qtd_status); 1046 if (nstatus & EHCI_QTD_ACTIVE) 1047 break; 1048 1049 status = nstatus; 1050 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1051 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1052 } 1053 1054 1055 /* 1056 * If there are left over TDs we need to update the toggle. 1057 * The default pipe doesn't need it since control transfers 1058 * start the toggle at 0 every time. 1059 * For a short transfer we need to update the toggle for the missing 1060 * packets within the qTD. 1061 */ 1062 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1063 xfer->pipe->device->default_pipe != xfer->pipe) { 1064 USBHIST_LOG(ehcidebug, 1065 "toggle update status=0x%08x nstatus=0x%08x", 1066 status, nstatus, 0, 0); 1067 #if 0 1068 ehci_dump_sqh(epipe->sqh); 1069 ehci_dump_sqtds(ex->sqtdstart); 1070 #endif 1071 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1072 } 1073 1074 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->length, 1075 actlen, status, 0); 1076 xfer->actlen = actlen; 1077 if (status & EHCI_QTD_HALTED) { 1078 #ifdef EHCI_DEBUG 1079 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1080 xfer->pipe->device->address, 1081 xfer->pipe->endpoint->edesc->bEndpointAddress, 0, 0); 1082 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1083 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1084 status, 0); 1085 USBHIST_LOG(ehcidebug, 1086 "active =%d halted=%d buferr=%d babble=%d", 1087 status & EHCI_QTD_ACTIVE ? 1 : 0, 1088 status & EHCI_QTD_HALTED ? 1 : 0, 1089 status & EHCI_QTD_BUFERR ? 1 : 0, 1090 status & EHCI_QTD_BABBLE ? 1 : 0); 1091 1092 USBHIST_LOG(ehcidebug, 1093 "xacterr=%d missed=%d split =%d ping =%d", 1094 status & EHCI_QTD_XACTERR ? 1 : 0, 1095 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1096 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1097 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1098 1099 ehci_dump_sqh(epipe->sqh); 1100 ehci_dump_sqtds(ex->sqtdstart); 1101 #endif 1102 /* low&full speed has an extra error flag */ 1103 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1104 EHCI_QH_SPEED_HIGH) 1105 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1106 else 1107 status &= EHCI_QTD_STATERRS; 1108 if (status == 0) /* no other errors means a stall */ { 1109 xfer->status = USBD_STALLED; 1110 } else { 1111 xfer->status = USBD_IOERROR; /* more info XXX */ 1112 } 1113 /* XXX need to reset TT on missed microframe */ 1114 if (status & EHCI_QTD_MISSEDMICRO) { 1115 printf("%s: missed microframe, TT reset not " 1116 "implemented, hub might be inoperational\n", 1117 device_xname(sc->sc_dev)); 1118 } 1119 } else { 1120 xfer->status = USBD_NORMAL_COMPLETION; 1121 } 1122 1123 end: 1124 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1125 * during this call, before methods->done is called: dma sync required 1126 * beforehand? */ 1127 usb_transfer_complete(xfer); 1128 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1129 } 1130 1131 /* 1132 * Wait here until controller claims to have an interrupt. 1133 * Then call ehci_intr and return. Use timeout to avoid waiting 1134 * too long. 1135 */ 1136 Static void 1137 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1138 { 1139 int timo; 1140 u_int32_t intrs; 1141 1142 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1143 1144 xfer->status = USBD_IN_PROGRESS; 1145 for (timo = xfer->timeout; timo >= 0; timo--) { 1146 usb_delay_ms(&sc->sc_bus, 1); 1147 if (sc->sc_dying) 1148 break; 1149 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1150 sc->sc_eintrs; 1151 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1152 #ifdef EHCI_DEBUG 1153 if (ehcidebug > 15) 1154 ehci_dump_regs(sc); 1155 #endif 1156 if (intrs) { 1157 mutex_spin_enter(&sc->sc_intr_lock); 1158 ehci_intr1(sc); 1159 mutex_spin_exit(&sc->sc_intr_lock); 1160 if (xfer->status != USBD_IN_PROGRESS) 1161 return; 1162 } 1163 } 1164 1165 /* Timeout */ 1166 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1167 xfer->status = USBD_TIMEOUT; 1168 mutex_enter(&sc->sc_lock); 1169 usb_transfer_complete(xfer); 1170 mutex_exit(&sc->sc_lock); 1171 /* XXX should free TD */ 1172 } 1173 1174 Static void 1175 ehci_poll(struct usbd_bus *bus) 1176 { 1177 ehci_softc_t *sc = bus->hci_private; 1178 1179 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1180 1181 #ifdef EHCI_DEBUG 1182 static int last; 1183 int new; 1184 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1185 if (new != last) { 1186 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1187 last = new; 1188 } 1189 #endif 1190 1191 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1192 mutex_spin_enter(&sc->sc_intr_lock); 1193 ehci_intr1(sc); 1194 mutex_spin_exit(&sc->sc_intr_lock); 1195 } 1196 } 1197 1198 void 1199 ehci_childdet(device_t self, device_t child) 1200 { 1201 struct ehci_softc *sc = device_private(self); 1202 1203 KASSERT(sc->sc_child == child); 1204 sc->sc_child = NULL; 1205 } 1206 1207 int 1208 ehci_detach(struct ehci_softc *sc, int flags) 1209 { 1210 int rv = 0; 1211 1212 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1213 1214 if (sc->sc_child != NULL) 1215 rv = config_detach(sc->sc_child, flags); 1216 1217 if (rv != 0) 1218 return (rv); 1219 1220 callout_halt(&sc->sc_tmo_intrlist, NULL); 1221 callout_destroy(&sc->sc_tmo_intrlist); 1222 1223 /* XXX free other data structures XXX */ 1224 if (sc->sc_softitds) 1225 kmem_free(sc->sc_softitds, 1226 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1227 cv_destroy(&sc->sc_doorbell); 1228 cv_destroy(&sc->sc_softwake_cv); 1229 1230 #if 0 1231 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1232 1233 softint_disestablish(sc->sc_doorbell_si); 1234 softint_disestablish(sc->sc_pcd_si); 1235 1236 mutex_destroy(&sc->sc_lock); 1237 mutex_destroy(&sc->sc_intr_lock); 1238 #endif 1239 1240 pool_cache_destroy(sc->sc_xferpool); 1241 1242 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1243 1244 return (rv); 1245 } 1246 1247 1248 int 1249 ehci_activate(device_t self, enum devact act) 1250 { 1251 struct ehci_softc *sc = device_private(self); 1252 1253 switch (act) { 1254 case DVACT_DEACTIVATE: 1255 sc->sc_dying = 1; 1256 return 0; 1257 default: 1258 return EOPNOTSUPP; 1259 } 1260 } 1261 1262 /* 1263 * Handle suspend/resume. 1264 * 1265 * We need to switch to polling mode here, because this routine is 1266 * called from an interrupt context. This is all right since we 1267 * are almost suspended anyway. 1268 * 1269 * Note that this power handler isn't to be registered directly; the 1270 * bus glue needs to call out to it. 1271 */ 1272 bool 1273 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1274 { 1275 ehci_softc_t *sc = device_private(dv); 1276 int i; 1277 uint32_t cmd, hcr; 1278 1279 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1280 1281 mutex_spin_enter(&sc->sc_intr_lock); 1282 sc->sc_bus.use_polling++; 1283 mutex_spin_exit(&sc->sc_intr_lock); 1284 1285 for (i = 1; i <= sc->sc_noport; i++) { 1286 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1287 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1288 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1289 } 1290 1291 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1292 1293 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1294 EOWRITE4(sc, EHCI_USBCMD, cmd); 1295 1296 for (i = 0; i < 100; i++) { 1297 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1298 if (hcr == 0) 1299 break; 1300 1301 usb_delay_ms(&sc->sc_bus, 1); 1302 } 1303 if (hcr != 0) 1304 printf("%s: reset timeout\n", device_xname(dv)); 1305 1306 cmd &= ~EHCI_CMD_RS; 1307 EOWRITE4(sc, EHCI_USBCMD, cmd); 1308 1309 for (i = 0; i < 100; i++) { 1310 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1311 if (hcr == EHCI_STS_HCH) 1312 break; 1313 1314 usb_delay_ms(&sc->sc_bus, 1); 1315 } 1316 if (hcr != EHCI_STS_HCH) 1317 printf("%s: config timeout\n", device_xname(dv)); 1318 1319 mutex_spin_enter(&sc->sc_intr_lock); 1320 sc->sc_bus.use_polling--; 1321 mutex_spin_exit(&sc->sc_intr_lock); 1322 1323 return true; 1324 } 1325 1326 bool 1327 ehci_resume(device_t dv, const pmf_qual_t *qual) 1328 { 1329 ehci_softc_t *sc = device_private(dv); 1330 int i; 1331 uint32_t cmd, hcr; 1332 1333 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1334 1335 /* restore things in case the bios sucks */ 1336 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1337 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1338 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1339 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1340 1341 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1342 1343 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1344 1345 hcr = 0; 1346 for (i = 1; i <= sc->sc_noport; i++) { 1347 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1348 if ((cmd & EHCI_PS_PO) == 0 && 1349 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1350 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1351 hcr = 1; 1352 } 1353 } 1354 1355 if (hcr) { 1356 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1357 1358 for (i = 1; i <= sc->sc_noport; i++) { 1359 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1360 if ((cmd & EHCI_PS_PO) == 0 && 1361 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1362 EOWRITE4(sc, EHCI_PORTSC(i), 1363 cmd & ~EHCI_PS_FPR); 1364 } 1365 } 1366 1367 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1368 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1369 1370 for (i = 0; i < 100; i++) { 1371 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1372 if (hcr != EHCI_STS_HCH) 1373 break; 1374 1375 usb_delay_ms(&sc->sc_bus, 1); 1376 } 1377 if (hcr == EHCI_STS_HCH) 1378 printf("%s: config timeout\n", device_xname(dv)); 1379 1380 return true; 1381 } 1382 1383 /* 1384 * Shut down the controller when the system is going down. 1385 */ 1386 bool 1387 ehci_shutdown(device_t self, int flags) 1388 { 1389 ehci_softc_t *sc = device_private(self); 1390 1391 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1392 1393 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1394 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1395 return true; 1396 } 1397 1398 Static usbd_status 1399 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1400 { 1401 struct ehci_softc *sc = bus->hci_private; 1402 usbd_status err; 1403 1404 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1405 #ifdef EHCI_DEBUG 1406 if (err) 1407 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1408 usbd_errstr(err), err); 1409 #endif 1410 if (err == USBD_NOMEM) 1411 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1412 #ifdef EHCI_DEBUG 1413 if (err) 1414 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1415 usbd_errstr(err), err); 1416 #endif 1417 return (err); 1418 } 1419 1420 Static void 1421 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1422 { 1423 struct ehci_softc *sc = bus->hci_private; 1424 1425 if (dma->block->flags & USB_DMA_RESERVE) { 1426 usb_reserve_freem(&sc->sc_dma_reserve, 1427 dma); 1428 return; 1429 } 1430 usb_freemem(&sc->sc_bus, dma); 1431 } 1432 1433 Static usbd_xfer_handle 1434 ehci_allocx(struct usbd_bus *bus) 1435 { 1436 struct ehci_softc *sc = bus->hci_private; 1437 usbd_xfer_handle xfer; 1438 1439 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1440 if (xfer != NULL) { 1441 memset(xfer, 0, sizeof(struct ehci_xfer)); 1442 #ifdef DIAGNOSTIC 1443 EXFER(xfer)->isdone = 1; 1444 xfer->busy_free = XFER_BUSY; 1445 #endif 1446 } 1447 return (xfer); 1448 } 1449 1450 Static void 1451 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1452 { 1453 struct ehci_softc *sc = bus->hci_private; 1454 1455 #ifdef DIAGNOSTIC 1456 if (xfer->busy_free != XFER_BUSY) { 1457 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1458 xfer->busy_free); 1459 } 1460 xfer->busy_free = XFER_FREE; 1461 if (!EXFER(xfer)->isdone) { 1462 printf("ehci_freex: !isdone\n"); 1463 } 1464 #endif 1465 pool_cache_put(sc->sc_xferpool, xfer); 1466 } 1467 1468 Static void 1469 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1470 { 1471 struct ehci_softc *sc = bus->hci_private; 1472 1473 *lock = &sc->sc_lock; 1474 } 1475 1476 Static void 1477 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1478 { 1479 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1480 1481 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1482 1483 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1484 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1485 #ifdef EHCI_DEBUG 1486 if (ehcidebug) 1487 usbd_dump_pipe(pipe); 1488 #endif 1489 epipe->nexttoggle = 0; 1490 } 1491 1492 Static void 1493 ehci_noop(usbd_pipe_handle pipe) 1494 { 1495 } 1496 1497 #ifdef EHCI_DEBUG 1498 /* 1499 * Unused function - this is meant to be called from a kernel 1500 * debugger. 1501 */ 1502 void 1503 ehci_dump(void) 1504 { 1505 ehci_softc_t *sc = theehci; 1506 int i; 1507 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1508 EOREAD4(sc, EHCI_USBCMD), 1509 EOREAD4(sc, EHCI_USBSTS), 1510 EOREAD4(sc, EHCI_USBINTR)); 1511 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1512 EOREAD4(sc, EHCI_FRINDEX), 1513 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1514 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1515 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1516 for (i = 1; i <= sc->sc_noport; i++) 1517 printf("port %d status=0x%08x\n", i, 1518 EOREAD4(sc, EHCI_PORTSC(i))); 1519 } 1520 1521 Static void 1522 ehci_dump_regs(ehci_softc_t *sc) 1523 { 1524 int i; 1525 1526 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1527 1528 USBHIST_LOG(ehcidebug, 1529 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1530 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1531 EOREAD4(sc, EHCI_USBINTR), 0); 1532 USBHIST_LOG(ehcidebug, 1533 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1534 "async = 0x%08x", 1535 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1536 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1537 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1538 for (i = 1; i <= sc->sc_noport; i += 2) { 1539 if (i == sc->sc_noport) { 1540 USBHIST_LOG(ehcidebug, 1541 "port %d status = 0x%08x", i, 1542 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1543 } else { 1544 USBHIST_LOG(ehcidebug, 1545 "port %d status = 0x%08x port %d status = 0x%08x", 1546 i, EOREAD4(sc, EHCI_PORTSC(i)), 1547 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1548 } 1549 } 1550 } 1551 1552 #define ehci_dump_link(link, type) do { \ 1553 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1554 link, \ 1555 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1556 if (type) { \ 1557 USBHIST_LOG(ehcidebug, \ 1558 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1559 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1560 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1561 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1562 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1563 } \ 1564 } while(0) 1565 1566 Static void 1567 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1568 { 1569 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1570 int i; 1571 uint32_t stop = 0; 1572 1573 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1574 ehci_dump_sqtd(sqtd); 1575 usb_syncmem(&sqtd->dma, 1576 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1577 sizeof(sqtd->qtd), 1578 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1579 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1580 usb_syncmem(&sqtd->dma, 1581 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1582 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1583 } 1584 if (!stop) 1585 USBHIST_LOG(ehcidebug, 1586 "dump aborted, too many TDs", 0, 0, 0, 0); 1587 } 1588 1589 Static void 1590 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1591 { 1592 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1593 1594 usb_syncmem(&sqtd->dma, sqtd->offs, 1595 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1596 1597 USBHIST_LOGN(ehcidebug, 10, 1598 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1599 ehci_dump_qtd(&sqtd->qtd); 1600 1601 usb_syncmem(&sqtd->dma, sqtd->offs, 1602 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1603 } 1604 1605 Static void 1606 ehci_dump_qtd(ehci_qtd_t *qtd) 1607 { 1608 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1609 uint32_t s = le32toh(qtd->qtd_status); 1610 1611 USBHIST_LOGN(ehcidebug, 10, 1612 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1613 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1614 USBHIST_LOGN(ehcidebug, 10, 1615 " toggle = %d ioc = %d bytes = %#x " 1616 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1617 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1618 USBHIST_LOGN(ehcidebug, 10, 1619 " cerr = %d pid = %d stat = %x", 1620 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1621 0); 1622 USBHIST_LOGN(ehcidebug, 10, 1623 "active =%d halted=%d buferr=%d babble=%d", 1624 s & EHCI_QTD_ACTIVE ? 1 : 0, 1625 s & EHCI_QTD_HALTED ? 1 : 0, 1626 s & EHCI_QTD_BUFERR ? 1 : 0, 1627 s & EHCI_QTD_BABBLE ? 1 : 0); 1628 USBHIST_LOGN(ehcidebug, 10, 1629 "xacterr=%d missed=%d split =%d ping =%d", 1630 s & EHCI_QTD_XACTERR ? 1 : 0, 1631 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1632 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1633 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1634 USBHIST_LOGN(ehcidebug, 10, 1635 "buffer[0] = %#x buffer[1] = %#x " 1636 "buffer[2] = %#x buffer[3] = %#x", 1637 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1638 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1639 USBHIST_LOGN(ehcidebug, 10, 1640 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1641 } 1642 1643 Static void 1644 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1645 { 1646 ehci_qh_t *qh = &sqh->qh; 1647 ehci_link_t link; 1648 u_int32_t endp, endphub; 1649 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1650 1651 usb_syncmem(&sqh->dma, sqh->offs, 1652 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1653 1654 USBHIST_LOGN(ehcidebug, 10, 1655 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1656 link = le32toh(qh->qh_link); 1657 ehci_dump_link(link, true); 1658 1659 endp = le32toh(qh->qh_endp); 1660 USBHIST_LOGN(ehcidebug, 10, 1661 " endp = %#x", endp, 0, 0, 0); 1662 USBHIST_LOGN(ehcidebug, 10, 1663 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1664 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1665 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1666 USBHIST_LOGN(ehcidebug, 10, 1667 " dtc = %d hrecl = %d", 1668 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1669 USBHIST_LOGN(ehcidebug, 10, 1670 " ctl = %d nrl = %d mpl = %#x(%d)", 1671 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1672 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1673 1674 endphub = le32toh(qh->qh_endphub); 1675 USBHIST_LOGN(ehcidebug, 10, 1676 " endphub = %#x", endphub, 0, 0, 0); 1677 USBHIST_LOGN(ehcidebug, 10, 1678 " smask = 0x%02x cmask = 0x%02x", 1679 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1680 USBHIST_LOGN(ehcidebug, 10, 1681 " huba = 0x%02x port = %d mult = %d", 1682 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1683 EHCI_QH_GET_MULT(endphub), 0); 1684 1685 link = le32toh(qh->qh_curqtd); 1686 ehci_dump_link(link, false); 1687 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1688 ehci_dump_qtd(&qh->qh_qtd); 1689 1690 usb_syncmem(&sqh->dma, sqh->offs, 1691 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1692 } 1693 1694 Static void 1695 ehci_dump_itd(struct ehci_soft_itd *itd) 1696 { 1697 ehci_isoc_trans_t t; 1698 ehci_isoc_bufr_ptr_t b, b2, b3; 1699 int i; 1700 1701 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1702 1703 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1704 0, 0); 1705 1706 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1707 t = le32toh(itd->itd.itd_ctl[i]); 1708 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1709 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1710 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1711 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1712 EHCI_ITD_GET_OFFS(t), 0); 1713 } 1714 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1715 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1716 USBHIST_LOG(ehcidebug, " %x", 1717 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1718 1719 b = le32toh(itd->itd.itd_bufr[0]); 1720 b2 = le32toh(itd->itd.itd_bufr[1]); 1721 b3 = le32toh(itd->itd.itd_bufr[2]); 1722 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1723 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1724 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1725 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1726 } 1727 1728 Static void 1729 ehci_dump_sitd(struct ehci_soft_itd *itd) 1730 { 1731 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1732 1733 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1734 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1735 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1736 itd->xfer_next, itd->physaddr, itd->slot, 0); 1737 } 1738 1739 Static void 1740 ehci_dump_exfer(struct ehci_xfer *ex) 1741 { 1742 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1743 1744 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1745 ex, ex->sqtdstart, ex->sqtdend, 0); 1746 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1747 ex->itdstart, ex->itdend, ex->isdone, 0); 1748 } 1749 #endif 1750 1751 Static usbd_status 1752 ehci_open(usbd_pipe_handle pipe) 1753 { 1754 usbd_device_handle dev = pipe->device; 1755 ehci_softc_t *sc = dev->bus->hci_private; 1756 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1757 u_int8_t addr = dev->address; 1758 u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1759 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1760 ehci_soft_qh_t *sqh; 1761 usbd_status err; 1762 int ival, speed, naks; 1763 int hshubaddr, hshubport; 1764 1765 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1766 1767 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1768 pipe, addr, ed->bEndpointAddress, sc->sc_addr); 1769 1770 if (dev->myhsport) { 1771 /* 1772 * When directly attached FS/LS device while doing embedded 1773 * transaction translations and we are the hub, set the hub 1774 * address to 0 (us). 1775 */ 1776 if (!(sc->sc_flags & EHCIF_ETTF) 1777 || (dev->myhsport->parent->address != sc->sc_addr)) { 1778 hshubaddr = dev->myhsport->parent->address; 1779 } else { 1780 hshubaddr = 0; 1781 } 1782 hshubport = dev->myhsport->portno; 1783 } else { 1784 hshubaddr = 0; 1785 hshubport = 0; 1786 } 1787 1788 if (sc->sc_dying) 1789 return (USBD_IOERROR); 1790 1791 /* toggle state needed for bulk endpoints */ 1792 epipe->nexttoggle = pipe->endpoint->datatoggle; 1793 1794 if (addr == sc->sc_addr) { 1795 switch (ed->bEndpointAddress) { 1796 case USB_CONTROL_ENDPOINT: 1797 pipe->methods = &ehci_root_ctrl_methods; 1798 break; 1799 case UE_DIR_IN | EHCI_INTR_ENDPT: 1800 pipe->methods = &ehci_root_intr_methods; 1801 break; 1802 default: 1803 USBHIST_LOG(ehcidebug, 1804 "bad bEndpointAddress 0x%02x", 1805 ed->bEndpointAddress, 0, 0, 0); 1806 return (USBD_INVAL); 1807 } 1808 return (USBD_NORMAL_COMPLETION); 1809 } 1810 1811 /* XXX All this stuff is only valid for async. */ 1812 switch (dev->speed) { 1813 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1814 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1815 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1816 default: panic("ehci_open: bad device speed %d", dev->speed); 1817 } 1818 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1819 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1820 "isoc endpoint.\n"); 1821 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1822 "attached to a USB2 hub, and transaction translations are " 1823 "not yet supported.\n"); 1824 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1825 "root hub instead.\n"); 1826 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1827 hshubaddr, hshubport, 0, 0); 1828 return USBD_INVAL; 1829 } 1830 1831 /* 1832 * For interrupt transfer, nak throttling must be disabled, but for 1833 * the other transfer type, nak throttling should be enabled from the 1834 * viewpoint that avoids the memory thrashing. 1835 */ 1836 naks = (xfertype == UE_INTERRUPT) ? 0 1837 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1838 1839 /* Allocate sqh for everything, save isoc xfers */ 1840 if (xfertype != UE_ISOCHRONOUS) { 1841 sqh = ehci_alloc_sqh(sc); 1842 if (sqh == NULL) 1843 return (USBD_NOMEM); 1844 /* qh_link filled when the QH is added */ 1845 sqh->qh.qh_endp = htole32( 1846 EHCI_QH_SET_ADDR(addr) | 1847 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1848 EHCI_QH_SET_EPS(speed) | 1849 EHCI_QH_DTC | 1850 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1851 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1852 EHCI_QH_CTL : 0) | 1853 EHCI_QH_SET_NRL(naks) 1854 ); 1855 sqh->qh.qh_endphub = htole32( 1856 EHCI_QH_SET_MULT(1) | 1857 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1858 ); 1859 if (speed != EHCI_QH_SPEED_HIGH) 1860 sqh->qh.qh_endphub |= htole32( 1861 EHCI_QH_SET_PORT(hshubport) | 1862 EHCI_QH_SET_HUBA(hshubaddr) | 1863 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1864 ); 1865 sqh->qh.qh_curqtd = EHCI_NULL; 1866 /* Fill the overlay qTD */ 1867 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1868 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1869 sqh->qh.qh_qtd.qtd_status = htole32(0); 1870 1871 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1872 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1873 epipe->sqh = sqh; 1874 } else { 1875 sqh = NULL; 1876 } /*xfertype == UE_ISOC*/ 1877 1878 switch (xfertype) { 1879 case UE_CONTROL: 1880 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1881 0, &epipe->u.ctl.reqdma); 1882 #ifdef EHCI_DEBUG 1883 if (err) 1884 printf("ehci_open: usb_allocmem()=%d\n", err); 1885 #endif 1886 if (err) 1887 goto bad; 1888 pipe->methods = &ehci_device_ctrl_methods; 1889 mutex_enter(&sc->sc_lock); 1890 ehci_add_qh(sc, sqh, sc->sc_async_head); 1891 mutex_exit(&sc->sc_lock); 1892 break; 1893 case UE_BULK: 1894 pipe->methods = &ehci_device_bulk_methods; 1895 mutex_enter(&sc->sc_lock); 1896 ehci_add_qh(sc, sqh, sc->sc_async_head); 1897 mutex_exit(&sc->sc_lock); 1898 break; 1899 case UE_INTERRUPT: 1900 pipe->methods = &ehci_device_intr_methods; 1901 ival = pipe->interval; 1902 if (ival == USBD_DEFAULT_INTERVAL) { 1903 if (speed == EHCI_QH_SPEED_HIGH) { 1904 if (ed->bInterval > 16) { 1905 /* 1906 * illegal with high-speed, but there 1907 * were documentation bugs in the spec, 1908 * so be generous 1909 */ 1910 ival = 256; 1911 } else 1912 ival = (1 << (ed->bInterval - 1)) / 8; 1913 } else 1914 ival = ed->bInterval; 1915 } 1916 err = ehci_device_setintr(sc, sqh, ival); 1917 if (err) 1918 goto bad; 1919 break; 1920 case UE_ISOCHRONOUS: 1921 pipe->methods = &ehci_device_isoc_methods; 1922 if (ed->bInterval == 0 || ed->bInterval > 16) { 1923 printf("ehci: opening pipe with invalid bInterval\n"); 1924 err = USBD_INVAL; 1925 goto bad; 1926 } 1927 if (UGETW(ed->wMaxPacketSize) == 0) { 1928 printf("ehci: zero length endpoint open request\n"); 1929 err = USBD_INVAL; 1930 goto bad; 1931 } 1932 epipe->u.isoc.next_frame = 0; 1933 epipe->u.isoc.cur_xfers = 0; 1934 break; 1935 default: 1936 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 1937 err = USBD_INVAL; 1938 goto bad; 1939 } 1940 return (USBD_NORMAL_COMPLETION); 1941 1942 bad: 1943 if (sqh != NULL) 1944 ehci_free_sqh(sc, sqh); 1945 return (err); 1946 } 1947 1948 /* 1949 * Add an ED to the schedule. Called with USB lock held. 1950 */ 1951 Static void 1952 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1953 { 1954 1955 KASSERT(mutex_owned(&sc->sc_lock)); 1956 1957 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1958 1959 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1960 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1961 1962 sqh->next = head->next; 1963 sqh->qh.qh_link = head->qh.qh_link; 1964 1965 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1966 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1967 1968 head->next = sqh; 1969 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1970 1971 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1972 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1973 1974 #ifdef EHCI_DEBUG 1975 ehci_dump_sqh(sqh); 1976 #endif 1977 } 1978 1979 /* 1980 * Remove an ED from the schedule. Called with USB lock held. 1981 */ 1982 Static void 1983 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1984 { 1985 ehci_soft_qh_t *p; 1986 1987 KASSERT(mutex_owned(&sc->sc_lock)); 1988 1989 /* XXX */ 1990 for (p = head; p != NULL && p->next != sqh; p = p->next) 1991 ; 1992 if (p == NULL) 1993 panic("ehci_rem_qh: ED not found"); 1994 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1995 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1996 p->next = sqh->next; 1997 p->qh.qh_link = sqh->qh.qh_link; 1998 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1999 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2000 2001 ehci_sync_hc(sc); 2002 } 2003 2004 Static void 2005 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2006 { 2007 int i; 2008 u_int32_t status; 2009 2010 /* Save toggle bit and ping status. */ 2011 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2012 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2013 status = sqh->qh.qh_qtd.qtd_status & 2014 htole32(EHCI_QTD_TOGGLE_MASK | 2015 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2016 /* Set HALTED to make hw leave it alone. */ 2017 sqh->qh.qh_qtd.qtd_status = 2018 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2019 usb_syncmem(&sqh->dma, 2020 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2021 sizeof(sqh->qh.qh_qtd.qtd_status), 2022 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2023 sqh->qh.qh_curqtd = 0; 2024 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2025 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2026 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2027 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2028 sqh->sqtd = sqtd; 2029 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2030 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2031 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2032 sqh->qh.qh_qtd.qtd_status = status; 2033 usb_syncmem(&sqh->dma, 2034 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2035 sizeof(sqh->qh.qh_qtd.qtd_status), 2036 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2037 } 2038 2039 /* 2040 * Ensure that the HC has released all references to the QH. We do this 2041 * by asking for a Async Advance Doorbell interrupt and then we wait for 2042 * the interrupt. 2043 * To make this easier we first obtain exclusive use of the doorbell. 2044 */ 2045 Static void 2046 ehci_sync_hc(ehci_softc_t *sc) 2047 { 2048 int error __diagused; 2049 2050 KASSERT(mutex_owned(&sc->sc_lock)); 2051 2052 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2053 2054 if (sc->sc_dying) { 2055 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2056 return; 2057 } 2058 /* ask for doorbell */ 2059 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2060 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2061 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2062 2063 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2064 2065 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2066 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2067 #ifdef DIAGNOSTIC 2068 if (error) 2069 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2070 #endif 2071 } 2072 2073 Static void 2074 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2075 { 2076 struct ehci_soft_itd *itd, *prev; 2077 2078 prev = NULL; 2079 2080 if (exfer->itdstart == NULL || exfer->itdend == NULL) 2081 panic("ehci isoc xfer being freed, but with no itd chain"); 2082 2083 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2084 prev = itd->u.frame_list.prev; 2085 /* Unlink itd from hardware chain, or frame array */ 2086 if (prev == NULL) { /* We're at the table head */ 2087 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2088 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2089 usb_syncmem(&sc->sc_fldma, 2090 sizeof(ehci_link_t) * itd->slot, 2091 sizeof(ehci_link_t), 2092 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2093 2094 if (itd->u.frame_list.next != NULL) 2095 itd->u.frame_list.next->u.frame_list.prev = NULL; 2096 } else { 2097 /* XXX this part is untested... */ 2098 prev->itd.itd_next = itd->itd.itd_next; 2099 usb_syncmem(&itd->dma, 2100 itd->offs + offsetof(ehci_itd_t, itd_next), 2101 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2102 2103 prev->u.frame_list.next = itd->u.frame_list.next; 2104 if (itd->u.frame_list.next != NULL) 2105 itd->u.frame_list.next->u.frame_list.prev = prev; 2106 } 2107 } 2108 2109 prev = NULL; 2110 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2111 if (prev != NULL) 2112 ehci_free_itd(sc, prev); 2113 prev = itd; 2114 } 2115 if (prev) 2116 ehci_free_itd(sc, prev); 2117 exfer->itdstart = NULL; 2118 exfer->itdend = NULL; 2119 } 2120 2121 /***********/ 2122 2123 /* 2124 * Data structures and routines to emulate the root hub. 2125 */ 2126 Static usb_device_descriptor_t ehci_devd = { 2127 USB_DEVICE_DESCRIPTOR_SIZE, 2128 UDESC_DEVICE, /* type */ 2129 {0x00, 0x02}, /* USB version */ 2130 UDCLASS_HUB, /* class */ 2131 UDSUBCLASS_HUB, /* subclass */ 2132 UDPROTO_HSHUBSTT, /* protocol */ 2133 64, /* max packet */ 2134 {0},{0},{0x00,0x01}, /* device id */ 2135 1,2,0, /* string indicies */ 2136 1 /* # of configurations */ 2137 }; 2138 2139 Static const usb_device_qualifier_t ehci_odevd = { 2140 USB_DEVICE_DESCRIPTOR_SIZE, 2141 UDESC_DEVICE_QUALIFIER, /* type */ 2142 {0x00, 0x02}, /* USB version */ 2143 UDCLASS_HUB, /* class */ 2144 UDSUBCLASS_HUB, /* subclass */ 2145 UDPROTO_FSHUB, /* protocol */ 2146 64, /* max packet */ 2147 1, /* # of configurations */ 2148 0 2149 }; 2150 2151 Static const usb_config_descriptor_t ehci_confd = { 2152 USB_CONFIG_DESCRIPTOR_SIZE, 2153 UDESC_CONFIG, 2154 {USB_CONFIG_DESCRIPTOR_SIZE + 2155 USB_INTERFACE_DESCRIPTOR_SIZE + 2156 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2157 1, 2158 1, 2159 0, 2160 UC_ATTR_MBO | UC_SELF_POWERED, 2161 0 /* max power */ 2162 }; 2163 2164 Static const usb_interface_descriptor_t ehci_ifcd = { 2165 USB_INTERFACE_DESCRIPTOR_SIZE, 2166 UDESC_INTERFACE, 2167 0, 2168 0, 2169 1, 2170 UICLASS_HUB, 2171 UISUBCLASS_HUB, 2172 UIPROTO_HSHUBSTT, 2173 0 2174 }; 2175 2176 Static const usb_endpoint_descriptor_t ehci_endpd = { 2177 USB_ENDPOINT_DESCRIPTOR_SIZE, 2178 UDESC_ENDPOINT, 2179 UE_DIR_IN | EHCI_INTR_ENDPT, 2180 UE_INTERRUPT, 2181 {8, 0}, /* max packet */ 2182 12 2183 }; 2184 2185 Static const usb_hub_descriptor_t ehci_hubd = { 2186 USB_HUB_DESCRIPTOR_SIZE, 2187 UDESC_HUB, 2188 0, 2189 {0,0}, 2190 0, 2191 0, 2192 {""}, 2193 {""}, 2194 }; 2195 2196 /* 2197 * Simulate a hardware hub by handling all the necessary requests. 2198 */ 2199 Static usbd_status 2200 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2201 { 2202 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2203 usbd_status err; 2204 2205 /* Insert last in queue. */ 2206 mutex_enter(&sc->sc_lock); 2207 err = usb_insert_transfer(xfer); 2208 mutex_exit(&sc->sc_lock); 2209 if (err) 2210 return (err); 2211 2212 /* Pipe isn't running, start first */ 2213 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2214 } 2215 2216 Static usbd_status 2217 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2218 { 2219 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2220 usb_device_request_t *req; 2221 void *buf = NULL; 2222 int port, i; 2223 int len, value, index, l, totlen = 0; 2224 usb_port_status_t ps; 2225 usb_hub_descriptor_t hubd; 2226 usbd_status err; 2227 u_int32_t v; 2228 2229 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2230 2231 if (sc->sc_dying) 2232 return (USBD_IOERROR); 2233 2234 #ifdef DIAGNOSTIC 2235 if (!(xfer->rqflags & URQ_REQUEST)) 2236 /* XXX panic */ 2237 return (USBD_INVAL); 2238 #endif 2239 req = &xfer->request; 2240 2241 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2242 req->bmRequestType, req->bRequest, 0, 0); 2243 2244 len = UGETW(req->wLength); 2245 value = UGETW(req->wValue); 2246 index = UGETW(req->wIndex); 2247 2248 if (len != 0) 2249 buf = KERNADDR(&xfer->dmabuf, 0); 2250 2251 #define C(x,y) ((x) | ((y) << 8)) 2252 switch(C(req->bRequest, req->bmRequestType)) { 2253 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2254 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2255 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2256 /* 2257 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2258 * for the integrated root hub. 2259 */ 2260 break; 2261 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2262 if (len > 0) { 2263 *(u_int8_t *)buf = sc->sc_conf; 2264 totlen = 1; 2265 } 2266 break; 2267 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2268 USBHIST_LOG(ehcidebug, "wValue=0x%04x", value, 0, 0, 0); 2269 if (len == 0) 2270 break; 2271 switch(value >> 8) { 2272 case UDESC_DEVICE: 2273 if ((value & 0xff) != 0) { 2274 err = USBD_IOERROR; 2275 goto ret; 2276 } 2277 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2278 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2279 memcpy(buf, &ehci_devd, l); 2280 break; 2281 /* 2282 * We can't really operate at another speed, but the spec says 2283 * we need this descriptor. 2284 */ 2285 case UDESC_DEVICE_QUALIFIER: 2286 if ((value & 0xff) != 0) { 2287 err = USBD_IOERROR; 2288 goto ret; 2289 } 2290 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2291 memcpy(buf, &ehci_odevd, l); 2292 break; 2293 /* 2294 * We can't really operate at another speed, but the spec says 2295 * we need this descriptor. 2296 */ 2297 case UDESC_OTHER_SPEED_CONFIGURATION: 2298 case UDESC_CONFIG: 2299 if ((value & 0xff) != 0) { 2300 err = USBD_IOERROR; 2301 goto ret; 2302 } 2303 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2304 memcpy(buf, &ehci_confd, l); 2305 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2306 value >> 8; 2307 buf = (char *)buf + l; 2308 len -= l; 2309 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2310 totlen += l; 2311 memcpy(buf, &ehci_ifcd, l); 2312 buf = (char *)buf + l; 2313 len -= l; 2314 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2315 totlen += l; 2316 memcpy(buf, &ehci_endpd, l); 2317 break; 2318 case UDESC_STRING: 2319 #define sd ((usb_string_descriptor_t *)buf) 2320 switch (value & 0xff) { 2321 case 0: /* Language table */ 2322 totlen = usb_makelangtbl(sd, len); 2323 break; 2324 case 1: /* Vendor */ 2325 totlen = usb_makestrdesc(sd, len, 2326 sc->sc_vendor); 2327 break; 2328 case 2: /* Product */ 2329 totlen = usb_makestrdesc(sd, len, 2330 "EHCI root hub"); 2331 break; 2332 } 2333 #undef sd 2334 break; 2335 default: 2336 err = USBD_IOERROR; 2337 goto ret; 2338 } 2339 break; 2340 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2341 if (len > 0) { 2342 *(u_int8_t *)buf = 0; 2343 totlen = 1; 2344 } 2345 break; 2346 case C(UR_GET_STATUS, UT_READ_DEVICE): 2347 if (len > 1) { 2348 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2349 totlen = 2; 2350 } 2351 break; 2352 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2353 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2354 if (len > 1) { 2355 USETW(((usb_status_t *)buf)->wStatus, 0); 2356 totlen = 2; 2357 } 2358 break; 2359 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2360 if (value >= USB_MAX_DEVICES) { 2361 err = USBD_IOERROR; 2362 goto ret; 2363 } 2364 sc->sc_addr = value; 2365 break; 2366 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2367 if (value != 0 && value != 1) { 2368 err = USBD_IOERROR; 2369 goto ret; 2370 } 2371 sc->sc_conf = value; 2372 break; 2373 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2374 break; 2375 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2376 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2377 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2378 err = USBD_IOERROR; 2379 goto ret; 2380 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2381 break; 2382 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2383 break; 2384 /* Hub requests */ 2385 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2386 break; 2387 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2388 USBHIST_LOG(ehcidebug, 2389 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2390 0, 0); 2391 if (index < 1 || index > sc->sc_noport) { 2392 err = USBD_IOERROR; 2393 goto ret; 2394 } 2395 port = EHCI_PORTSC(index); 2396 v = EOREAD4(sc, port); 2397 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2398 v &= ~EHCI_PS_CLEAR; 2399 switch(value) { 2400 case UHF_PORT_ENABLE: 2401 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2402 break; 2403 case UHF_PORT_SUSPEND: 2404 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2405 break; 2406 v &= ~EHCI_PS_SUSP; 2407 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2408 /* see USB2 spec ch. 7.1.7.7 */ 2409 usb_delay_ms(&sc->sc_bus, 20); 2410 EOWRITE4(sc, port, v); 2411 usb_delay_ms(&sc->sc_bus, 2); 2412 #ifdef DEBUG 2413 v = EOREAD4(sc, port); 2414 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2415 printf("ehci: resume failed: %x\n", v); 2416 #endif 2417 break; 2418 case UHF_PORT_POWER: 2419 if (sc->sc_hasppc) 2420 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2421 break; 2422 case UHF_PORT_TEST: 2423 USBHIST_LOG(ehcidebug, "clear port test " 2424 "%d", index, 0, 0, 0); 2425 break; 2426 case UHF_PORT_INDICATOR: 2427 USBHIST_LOG(ehcidebug, "clear port ind " 2428 "%d", index, 0, 0, 0); 2429 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2430 break; 2431 case UHF_C_PORT_CONNECTION: 2432 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2433 break; 2434 case UHF_C_PORT_ENABLE: 2435 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2436 break; 2437 case UHF_C_PORT_SUSPEND: 2438 /* how? */ 2439 break; 2440 case UHF_C_PORT_OVER_CURRENT: 2441 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2442 break; 2443 case UHF_C_PORT_RESET: 2444 sc->sc_isreset[index] = 0; 2445 break; 2446 default: 2447 err = USBD_IOERROR; 2448 goto ret; 2449 } 2450 #if 0 2451 switch(value) { 2452 case UHF_C_PORT_CONNECTION: 2453 case UHF_C_PORT_ENABLE: 2454 case UHF_C_PORT_SUSPEND: 2455 case UHF_C_PORT_OVER_CURRENT: 2456 case UHF_C_PORT_RESET: 2457 default: 2458 break; 2459 } 2460 #endif 2461 break; 2462 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2463 if (len == 0) 2464 break; 2465 if ((value & 0xff) != 0) { 2466 err = USBD_IOERROR; 2467 goto ret; 2468 } 2469 hubd = ehci_hubd; 2470 hubd.bNbrPorts = sc->sc_noport; 2471 v = EOREAD4(sc, EHCI_HCSPARAMS); 2472 USETW(hubd.wHubCharacteristics, 2473 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2474 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2475 ? UHD_PORT_IND : 0); 2476 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2477 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2478 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2479 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2480 l = min(len, hubd.bDescLength); 2481 totlen = l; 2482 memcpy(buf, &hubd, l); 2483 break; 2484 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2485 if (len != 4) { 2486 err = USBD_IOERROR; 2487 goto ret; 2488 } 2489 memset(buf, 0, len); /* ? XXX */ 2490 totlen = len; 2491 break; 2492 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2493 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2494 if (index < 1 || index > sc->sc_noport) { 2495 err = USBD_IOERROR; 2496 goto ret; 2497 } 2498 if (len != 4) { 2499 err = USBD_IOERROR; 2500 goto ret; 2501 } 2502 v = EOREAD4(sc, EHCI_PORTSC(index)); 2503 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2504 2505 i = UPS_HIGH_SPEED; 2506 if (sc->sc_flags & EHCIF_ETTF) { 2507 /* 2508 * If we are doing embedded transaction translation, 2509 * then directly attached LS/FS devices are reset by 2510 * the EHCI controller itself. PSPD is encoded 2511 * the same way as in USBSTATUS. 2512 */ 2513 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2514 } 2515 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2516 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2517 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2518 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2519 if (v & EHCI_PS_PR) i |= UPS_RESET; 2520 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2521 if (sc->sc_vendor_port_status) 2522 i = sc->sc_vendor_port_status(sc, v, i); 2523 USETW(ps.wPortStatus, i); 2524 i = 0; 2525 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2526 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2527 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2528 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2529 USETW(ps.wPortChange, i); 2530 l = min(len, sizeof ps); 2531 memcpy(buf, &ps, l); 2532 totlen = l; 2533 break; 2534 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2535 err = USBD_IOERROR; 2536 goto ret; 2537 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2538 break; 2539 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2540 if (index < 1 || index > sc->sc_noport) { 2541 err = USBD_IOERROR; 2542 goto ret; 2543 } 2544 port = EHCI_PORTSC(index); 2545 v = EOREAD4(sc, port); 2546 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2547 v &= ~EHCI_PS_CLEAR; 2548 switch(value) { 2549 case UHF_PORT_ENABLE: 2550 EOWRITE4(sc, port, v | EHCI_PS_PE); 2551 break; 2552 case UHF_PORT_SUSPEND: 2553 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2554 break; 2555 case UHF_PORT_RESET: 2556 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2557 if (EHCI_PS_IS_LOWSPEED(v) 2558 && sc->sc_ncomp > 0 2559 && !(sc->sc_flags & EHCIF_ETTF)) { 2560 /* 2561 * Low speed device on non-ETTF controller or 2562 * unaccompanied controller, give up ownership. 2563 */ 2564 ehci_disown(sc, index, 1); 2565 break; 2566 } 2567 /* Start reset sequence. */ 2568 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2569 EOWRITE4(sc, port, v | EHCI_PS_PR); 2570 /* Wait for reset to complete. */ 2571 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2572 if (sc->sc_dying) { 2573 err = USBD_IOERROR; 2574 goto ret; 2575 } 2576 /* 2577 * An embedded transaction translator will automatically 2578 * terminate the reset sequence so there's no need to 2579 * it. 2580 */ 2581 v = EOREAD4(sc, port); 2582 if (v & EHCI_PS_PR) { 2583 /* Terminate reset sequence. */ 2584 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2585 /* Wait for HC to complete reset. */ 2586 usb_delay_ms(&sc->sc_bus, 2587 EHCI_PORT_RESET_COMPLETE); 2588 if (sc->sc_dying) { 2589 err = USBD_IOERROR; 2590 goto ret; 2591 } 2592 } 2593 2594 v = EOREAD4(sc, port); 2595 USBHIST_LOG(ehcidebug, 2596 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2597 if (v & EHCI_PS_PR) { 2598 printf("%s: port reset timeout\n", 2599 device_xname(sc->sc_dev)); 2600 return (USBD_TIMEOUT); 2601 } 2602 if (!(v & EHCI_PS_PE)) { 2603 /* Not a high speed device, give up ownership.*/ 2604 ehci_disown(sc, index, 0); 2605 break; 2606 } 2607 sc->sc_isreset[index] = 1; 2608 USBHIST_LOG(ehcidebug, 2609 "ehci port %d reset, status = 0x%08x", index, v, 0, 2610 0); 2611 break; 2612 case UHF_PORT_POWER: 2613 USBHIST_LOG(ehcidebug, 2614 "set port power %d (has PPC = %d)", index, 2615 sc->sc_hasppc, 0, 0); 2616 if (sc->sc_hasppc) 2617 EOWRITE4(sc, port, v | EHCI_PS_PP); 2618 break; 2619 case UHF_PORT_TEST: 2620 USBHIST_LOG(ehcidebug, "set port test %d", 2621 index, 0, 0, 0); 2622 break; 2623 case UHF_PORT_INDICATOR: 2624 USBHIST_LOG(ehcidebug, "set port ind %d", 2625 index, 0, 0, 0); 2626 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2627 break; 2628 default: 2629 err = USBD_IOERROR; 2630 goto ret; 2631 } 2632 break; 2633 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2634 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2635 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2636 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2637 break; 2638 default: 2639 err = USBD_IOERROR; 2640 goto ret; 2641 } 2642 xfer->actlen = totlen; 2643 err = USBD_NORMAL_COMPLETION; 2644 ret: 2645 mutex_enter(&sc->sc_lock); 2646 xfer->status = err; 2647 usb_transfer_complete(xfer); 2648 mutex_exit(&sc->sc_lock); 2649 return (USBD_IN_PROGRESS); 2650 } 2651 2652 Static void 2653 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2654 { 2655 int port; 2656 u_int32_t v; 2657 2658 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2659 2660 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2661 #ifdef DIAGNOSTIC 2662 if (sc->sc_npcomp != 0) { 2663 int i = (index-1) / sc->sc_npcomp; 2664 if (i >= sc->sc_ncomp) 2665 printf("%s: strange port\n", 2666 device_xname(sc->sc_dev)); 2667 else 2668 printf("%s: handing over %s speed device on " 2669 "port %d to %s\n", 2670 device_xname(sc->sc_dev), 2671 lowspeed ? "low" : "full", 2672 index, device_xname(sc->sc_comps[i])); 2673 } else { 2674 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2675 } 2676 #endif 2677 port = EHCI_PORTSC(index); 2678 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2679 EOWRITE4(sc, port, v | EHCI_PS_PO); 2680 } 2681 2682 /* Abort a root control request. */ 2683 Static void 2684 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2685 { 2686 /* Nothing to do, all transfers are synchronous. */ 2687 } 2688 2689 /* Close the root pipe. */ 2690 Static void 2691 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2692 { 2693 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2694 /* Nothing to do. */ 2695 } 2696 2697 Static void 2698 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2699 { 2700 xfer->hcpriv = NULL; 2701 } 2702 2703 Static usbd_status 2704 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2705 { 2706 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2707 usbd_status err; 2708 2709 /* Insert last in queue. */ 2710 mutex_enter(&sc->sc_lock); 2711 err = usb_insert_transfer(xfer); 2712 mutex_exit(&sc->sc_lock); 2713 if (err) 2714 return (err); 2715 2716 /* Pipe isn't running, start first */ 2717 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2718 } 2719 2720 Static usbd_status 2721 ehci_root_intr_start(usbd_xfer_handle xfer) 2722 { 2723 usbd_pipe_handle pipe = xfer->pipe; 2724 ehci_softc_t *sc = pipe->device->bus->hci_private; 2725 2726 if (sc->sc_dying) 2727 return (USBD_IOERROR); 2728 2729 mutex_enter(&sc->sc_lock); 2730 sc->sc_intrxfer = xfer; 2731 mutex_exit(&sc->sc_lock); 2732 2733 return (USBD_IN_PROGRESS); 2734 } 2735 2736 /* Abort a root interrupt request. */ 2737 Static void 2738 ehci_root_intr_abort(usbd_xfer_handle xfer) 2739 { 2740 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2741 2742 KASSERT(mutex_owned(&sc->sc_lock)); 2743 KASSERT(xfer->pipe->intrxfer == xfer); 2744 2745 sc->sc_intrxfer = NULL; 2746 2747 xfer->status = USBD_CANCELLED; 2748 usb_transfer_complete(xfer); 2749 } 2750 2751 /* Close the root pipe. */ 2752 Static void 2753 ehci_root_intr_close(usbd_pipe_handle pipe) 2754 { 2755 ehci_softc_t *sc = pipe->device->bus->hci_private; 2756 2757 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2758 2759 KASSERT(mutex_owned(&sc->sc_lock)); 2760 2761 sc->sc_intrxfer = NULL; 2762 } 2763 2764 Static void 2765 ehci_root_intr_done(usbd_xfer_handle xfer) 2766 { 2767 xfer->hcpriv = NULL; 2768 } 2769 2770 /************************/ 2771 2772 Static ehci_soft_qh_t * 2773 ehci_alloc_sqh(ehci_softc_t *sc) 2774 { 2775 ehci_soft_qh_t *sqh; 2776 usbd_status err; 2777 int i, offs; 2778 usb_dma_t dma; 2779 2780 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2781 2782 if (sc->sc_freeqhs == NULL) { 2783 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2784 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2785 EHCI_PAGE_SIZE, &dma); 2786 #ifdef EHCI_DEBUG 2787 if (err) 2788 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2789 #endif 2790 if (err) 2791 return (NULL); 2792 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2793 offs = i * EHCI_SQH_SIZE; 2794 sqh = KERNADDR(&dma, offs); 2795 sqh->physaddr = DMAADDR(&dma, offs); 2796 sqh->dma = dma; 2797 sqh->offs = offs; 2798 sqh->next = sc->sc_freeqhs; 2799 sc->sc_freeqhs = sqh; 2800 } 2801 } 2802 sqh = sc->sc_freeqhs; 2803 sc->sc_freeqhs = sqh->next; 2804 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2805 sqh->next = NULL; 2806 return (sqh); 2807 } 2808 2809 Static void 2810 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2811 { 2812 sqh->next = sc->sc_freeqhs; 2813 sc->sc_freeqhs = sqh; 2814 } 2815 2816 Static ehci_soft_qtd_t * 2817 ehci_alloc_sqtd(ehci_softc_t *sc) 2818 { 2819 ehci_soft_qtd_t *sqtd = NULL; 2820 usbd_status err; 2821 int i, offs; 2822 usb_dma_t dma; 2823 2824 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2825 2826 if (sc->sc_freeqtds == NULL) { 2827 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2828 2829 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2830 EHCI_PAGE_SIZE, &dma); 2831 #ifdef EHCI_DEBUG 2832 if (err) 2833 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2834 #endif 2835 if (err) 2836 goto done; 2837 2838 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2839 offs = i * EHCI_SQTD_SIZE; 2840 sqtd = KERNADDR(&dma, offs); 2841 sqtd->physaddr = DMAADDR(&dma, offs); 2842 sqtd->dma = dma; 2843 sqtd->offs = offs; 2844 2845 sqtd->nextqtd = sc->sc_freeqtds; 2846 sc->sc_freeqtds = sqtd; 2847 } 2848 } 2849 2850 sqtd = sc->sc_freeqtds; 2851 sc->sc_freeqtds = sqtd->nextqtd; 2852 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2853 sqtd->nextqtd = NULL; 2854 sqtd->xfer = NULL; 2855 2856 done: 2857 return (sqtd); 2858 } 2859 2860 Static void 2861 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2862 { 2863 2864 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2865 2866 sqtd->nextqtd = sc->sc_freeqtds; 2867 sc->sc_freeqtds = sqtd; 2868 } 2869 2870 Static usbd_status 2871 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2872 int alen, int rd, usbd_xfer_handle xfer, 2873 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2874 { 2875 ehci_soft_qtd_t *next, *cur; 2876 ehci_physaddr_t nextphys; 2877 u_int32_t qtdstatus; 2878 int len, curlen, mps; 2879 int i, tog; 2880 int pages, pageoffs; 2881 bus_size_t curoffs; 2882 vaddr_t va, va_offs; 2883 usb_dma_t *dma = &xfer->dmabuf; 2884 u_int16_t flags = xfer->flags; 2885 paddr_t a; 2886 2887 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2888 2889 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2890 2891 len = alen; 2892 qtdstatus = EHCI_QTD_ACTIVE | 2893 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2894 EHCI_QTD_SET_CERR(3) 2895 /* IOC set below */ 2896 /* BYTES set below */ 2897 ; 2898 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2899 tog = epipe->nexttoggle; 2900 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2901 2902 cur = ehci_alloc_sqtd(sc); 2903 *sp = cur; 2904 if (cur == NULL) 2905 goto nomem; 2906 2907 usb_syncmem(dma, 0, alen, 2908 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2909 curoffs = 0; 2910 for (;;) { 2911 /* The EHCI hardware can handle at most 5 pages. */ 2912 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2913 va_offs = EHCI_PAGE_OFFSET(va_offs); 2914 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2915 /* we can handle it in this QTD */ 2916 curlen = len - curoffs; 2917 } else { 2918 /* must use multiple TDs, fill as much as possible. */ 2919 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2920 2921 /* the length must be a multiple of the max size */ 2922 curlen -= curlen % mps; 2923 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2924 "curlen=%d", curlen, 0, 0, 0); 2925 #ifdef DIAGNOSTIC 2926 if (curlen == 0) 2927 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2928 #endif 2929 } 2930 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2931 len, curlen, (size_t)curoffs, 0); 2932 2933 /* 2934 * Allocate another transfer if there's more data left, 2935 * or if force last short transfer flag is set and we're 2936 * allocating a multiple of the max packet size. 2937 */ 2938 2939 if (curoffs + curlen != len || 2940 ((curlen % mps) == 0 && !rd && curlen != 0 && 2941 (flags & USBD_FORCE_SHORT_XFER))) { 2942 next = ehci_alloc_sqtd(sc); 2943 if (next == NULL) 2944 goto nomem; 2945 nextphys = htole32(next->physaddr); 2946 } else { 2947 next = NULL; 2948 nextphys = EHCI_NULL; 2949 } 2950 2951 /* Find number of pages we'll be using, insert dma addresses */ 2952 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2953 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2954 pageoffs = EHCI_PAGE(curoffs); 2955 for (i = 0; i < pages; i++) { 2956 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2957 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2958 /* Cast up to avoid compiler warnings */ 2959 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2960 } 2961 2962 /* First buffer pointer requires a page offset to start at */ 2963 va = (vaddr_t)KERNADDR(dma, curoffs); 2964 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2965 2966 cur->nextqtd = next; 2967 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2968 cur->qtd.qtd_status = 2969 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2970 cur->xfer = xfer; 2971 cur->len = curlen; 2972 2973 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2974 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 2975 2976 /* adjust the toggle based on the number of packets in this 2977 qtd */ 2978 if (((curlen + mps - 1) / mps) & 1) { 2979 tog ^= 1; 2980 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2981 } 2982 if (next == NULL) 2983 break; 2984 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2985 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2986 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2987 if (len) 2988 curoffs += curlen; 2989 cur = next; 2990 } 2991 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2992 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2993 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2994 *ep = cur; 2995 epipe->nexttoggle = tog; 2996 2997 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2998 *sp, *ep, 0, 0); 2999 3000 return (USBD_NORMAL_COMPLETION); 3001 3002 nomem: 3003 /* XXX free chain */ 3004 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3005 return (USBD_NOMEM); 3006 } 3007 3008 Static void 3009 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 3010 ehci_soft_qtd_t *sqtdend) 3011 { 3012 ehci_soft_qtd_t *p; 3013 int i; 3014 3015 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3016 3017 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 3018 sqtd, sqtdend, 0, 0); 3019 3020 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 3021 p = sqtd->nextqtd; 3022 ehci_free_sqtd(sc, sqtd); 3023 } 3024 } 3025 3026 Static ehci_soft_itd_t * 3027 ehci_alloc_itd(ehci_softc_t *sc) 3028 { 3029 struct ehci_soft_itd *itd, *freeitd; 3030 usbd_status err; 3031 int i, offs, frindex, previndex; 3032 usb_dma_t dma; 3033 3034 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3035 3036 mutex_enter(&sc->sc_lock); 3037 3038 /* Find an itd that wasn't freed this frame or last frame. This can 3039 * discard itds that were freed before frindex wrapped around 3040 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3041 * interrupt and fiddling with list when that happens */ 3042 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3043 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3044 3045 freeitd = NULL; 3046 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 3047 if (itd == NULL) 3048 break; 3049 if (itd->slot != frindex && itd->slot != previndex) { 3050 freeitd = itd; 3051 break; 3052 } 3053 } 3054 3055 if (freeitd == NULL) { 3056 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3057 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3058 EHCI_PAGE_SIZE, &dma); 3059 3060 if (err) { 3061 USBHIST_LOG(ehcidebug, 3062 "alloc returned %d", err, 0, 0, 0); 3063 mutex_exit(&sc->sc_lock); 3064 return NULL; 3065 } 3066 3067 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 3068 offs = i * EHCI_ITD_SIZE; 3069 itd = KERNADDR(&dma, offs); 3070 itd->physaddr = DMAADDR(&dma, offs); 3071 itd->dma = dma; 3072 itd->offs = offs; 3073 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3074 } 3075 freeitd = LIST_FIRST(&sc->sc_freeitds); 3076 } 3077 3078 itd = freeitd; 3079 LIST_REMOVE(itd, u.free_list); 3080 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3081 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 3082 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 3083 BUS_DMASYNC_PREREAD); 3084 3085 itd->u.frame_list.next = NULL; 3086 itd->u.frame_list.prev = NULL; 3087 itd->xfer_next = NULL; 3088 itd->slot = 0; 3089 3090 mutex_exit(&sc->sc_lock); 3091 3092 return itd; 3093 } 3094 3095 Static void 3096 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3097 { 3098 3099 KASSERT(mutex_owned(&sc->sc_lock)); 3100 3101 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3102 } 3103 3104 /****************/ 3105 3106 /* 3107 * Close a reqular pipe. 3108 * Assumes that there are no pending transactions. 3109 */ 3110 Static void 3111 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3112 { 3113 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3114 ehci_softc_t *sc = pipe->device->bus->hci_private; 3115 ehci_soft_qh_t *sqh = epipe->sqh; 3116 3117 KASSERT(mutex_owned(&sc->sc_lock)); 3118 3119 ehci_rem_qh(sc, sqh, head); 3120 ehci_free_sqh(sc, epipe->sqh); 3121 } 3122 3123 /* 3124 * Abort a device request. 3125 * If this routine is called at splusb() it guarantees that the request 3126 * will be removed from the hardware scheduling and that the callback 3127 * for it will be called with USBD_CANCELLED status. 3128 * It's impossible to guarantee that the requested transfer will not 3129 * have happened since the hardware runs concurrently. 3130 * If the transaction has already happened we rely on the ordinary 3131 * interrupt processing to process it. 3132 * XXX This is most probably wrong. 3133 * XXXMRG this doesn't make sense anymore. 3134 */ 3135 Static void 3136 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3137 { 3138 #define exfer EXFER(xfer) 3139 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3140 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3141 ehci_soft_qh_t *sqh = epipe->sqh; 3142 ehci_soft_qtd_t *sqtd; 3143 ehci_physaddr_t cur; 3144 u_int32_t qhstatus; 3145 int hit; 3146 int wake; 3147 3148 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3149 3150 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3151 3152 KASSERT(mutex_owned(&sc->sc_lock)); 3153 3154 if (sc->sc_dying) { 3155 /* If we're dying, just do the software part. */ 3156 xfer->status = status; /* make software ignore it */ 3157 callout_stop(&xfer->timeout_handle); 3158 usb_transfer_complete(xfer); 3159 return; 3160 } 3161 3162 if (cpu_intr_p() || cpu_softintr_p()) 3163 panic("ehci_abort_xfer: not in process context"); 3164 3165 /* 3166 * If an abort is already in progress then just wait for it to 3167 * complete and return. 3168 */ 3169 if (xfer->hcflags & UXFER_ABORTING) { 3170 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3171 #ifdef DIAGNOSTIC 3172 if (status == USBD_TIMEOUT) 3173 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3174 #endif 3175 /* Override the status which might be USBD_TIMEOUT. */ 3176 xfer->status = status; 3177 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3178 0, 0, 0, 0); 3179 xfer->hcflags |= UXFER_ABORTWAIT; 3180 while (xfer->hcflags & UXFER_ABORTING) 3181 cv_wait(&xfer->hccv, &sc->sc_lock); 3182 return; 3183 } 3184 xfer->hcflags |= UXFER_ABORTING; 3185 3186 /* 3187 * Step 1: Make interrupt routine and hardware ignore xfer. 3188 */ 3189 xfer->status = status; /* make software ignore it */ 3190 callout_stop(&xfer->timeout_handle); 3191 3192 usb_syncmem(&sqh->dma, 3193 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3194 sizeof(sqh->qh.qh_qtd.qtd_status), 3195 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3196 qhstatus = sqh->qh.qh_qtd.qtd_status; 3197 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3198 usb_syncmem(&sqh->dma, 3199 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3200 sizeof(sqh->qh.qh_qtd.qtd_status), 3201 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3202 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3203 usb_syncmem(&sqtd->dma, 3204 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3205 sizeof(sqtd->qtd.qtd_status), 3206 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3207 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3208 usb_syncmem(&sqtd->dma, 3209 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3210 sizeof(sqtd->qtd.qtd_status), 3211 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3212 if (sqtd == exfer->sqtdend) 3213 break; 3214 } 3215 3216 /* 3217 * Step 2: Wait until we know hardware has finished any possible 3218 * use of the xfer. Also make sure the soft interrupt routine 3219 * has run. 3220 */ 3221 ehci_sync_hc(sc); 3222 sc->sc_softwake = 1; 3223 usb_schedsoftintr(&sc->sc_bus); 3224 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3225 3226 /* 3227 * Step 3: Remove any vestiges of the xfer from the hardware. 3228 * The complication here is that the hardware may have executed 3229 * beyond the xfer we're trying to abort. So as we're scanning 3230 * the TDs of this xfer we check if the hardware points to 3231 * any of them. 3232 */ 3233 3234 usb_syncmem(&sqh->dma, 3235 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3236 sizeof(sqh->qh.qh_curqtd), 3237 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3238 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3239 hit = 0; 3240 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3241 hit |= cur == sqtd->physaddr; 3242 if (sqtd == exfer->sqtdend) 3243 break; 3244 } 3245 sqtd = sqtd->nextqtd; 3246 /* Zap curqtd register if hardware pointed inside the xfer. */ 3247 if (hit && sqtd != NULL) { 3248 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3249 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3250 usb_syncmem(&sqh->dma, 3251 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3252 sizeof(sqh->qh.qh_curqtd), 3253 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3254 sqh->qh.qh_qtd.qtd_status = qhstatus; 3255 usb_syncmem(&sqh->dma, 3256 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3257 sizeof(sqh->qh.qh_qtd.qtd_status), 3258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3259 } else { 3260 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3261 } 3262 3263 /* 3264 * Step 4: Execute callback. 3265 */ 3266 #ifdef DIAGNOSTIC 3267 exfer->isdone = 1; 3268 #endif 3269 wake = xfer->hcflags & UXFER_ABORTWAIT; 3270 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3271 usb_transfer_complete(xfer); 3272 if (wake) { 3273 cv_broadcast(&xfer->hccv); 3274 } 3275 3276 KASSERT(mutex_owned(&sc->sc_lock)); 3277 #undef exfer 3278 } 3279 3280 Static void 3281 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3282 { 3283 ehci_isoc_trans_t trans_status; 3284 struct ehci_pipe *epipe; 3285 struct ehci_xfer *exfer; 3286 ehci_softc_t *sc; 3287 struct ehci_soft_itd *itd; 3288 int i, wake; 3289 3290 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3291 3292 epipe = (struct ehci_pipe *) xfer->pipe; 3293 exfer = EXFER(xfer); 3294 sc = epipe->pipe.device->bus->hci_private; 3295 3296 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3297 3298 KASSERT(mutex_owned(&sc->sc_lock)); 3299 3300 if (sc->sc_dying) { 3301 xfer->status = status; 3302 callout_stop(&xfer->timeout_handle); 3303 usb_transfer_complete(xfer); 3304 return; 3305 } 3306 3307 if (xfer->hcflags & UXFER_ABORTING) { 3308 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3309 3310 #ifdef DIAGNOSTIC 3311 if (status == USBD_TIMEOUT) 3312 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3313 #endif 3314 3315 xfer->status = status; 3316 USBHIST_LOG(ehcidebug, 3317 "waiting for abort to finish", 0, 0, 0, 0); 3318 xfer->hcflags |= UXFER_ABORTWAIT; 3319 while (xfer->hcflags & UXFER_ABORTING) 3320 cv_wait(&xfer->hccv, &sc->sc_lock); 3321 goto done; 3322 } 3323 xfer->hcflags |= UXFER_ABORTING; 3324 3325 xfer->status = status; 3326 callout_stop(&xfer->timeout_handle); 3327 3328 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3329 usb_syncmem(&itd->dma, 3330 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3331 sizeof(itd->itd.itd_ctl), 3332 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3333 3334 for (i = 0; i < 8; i++) { 3335 trans_status = le32toh(itd->itd.itd_ctl[i]); 3336 trans_status &= ~EHCI_ITD_ACTIVE; 3337 itd->itd.itd_ctl[i] = htole32(trans_status); 3338 } 3339 3340 usb_syncmem(&itd->dma, 3341 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3342 sizeof(itd->itd.itd_ctl), 3343 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3344 } 3345 3346 sc->sc_softwake = 1; 3347 usb_schedsoftintr(&sc->sc_bus); 3348 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3349 3350 #ifdef DIAGNOSTIC 3351 exfer->isdone = 1; 3352 #endif 3353 wake = xfer->hcflags & UXFER_ABORTWAIT; 3354 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3355 usb_transfer_complete(xfer); 3356 if (wake) { 3357 cv_broadcast(&xfer->hccv); 3358 } 3359 3360 done: 3361 KASSERT(mutex_owned(&sc->sc_lock)); 3362 return; 3363 } 3364 3365 Static void 3366 ehci_timeout(void *addr) 3367 { 3368 struct ehci_xfer *exfer = addr; 3369 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3370 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3371 3372 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3373 3374 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3375 #ifdef EHCI_DEBUG 3376 if (ehcidebug > 1) 3377 usbd_dump_pipe(exfer->xfer.pipe); 3378 #endif 3379 3380 if (sc->sc_dying) { 3381 mutex_enter(&sc->sc_lock); 3382 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3383 mutex_exit(&sc->sc_lock); 3384 return; 3385 } 3386 3387 /* Execute the abort in a process context. */ 3388 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3389 USB_TASKQ_MPSAFE); 3390 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3391 USB_TASKQ_HC); 3392 } 3393 3394 Static void 3395 ehci_timeout_task(void *addr) 3396 { 3397 usbd_xfer_handle xfer = addr; 3398 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3399 3400 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3401 3402 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3403 3404 mutex_enter(&sc->sc_lock); 3405 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3406 mutex_exit(&sc->sc_lock); 3407 } 3408 3409 /************************/ 3410 3411 Static usbd_status 3412 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3413 { 3414 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3415 usbd_status err; 3416 3417 /* Insert last in queue. */ 3418 mutex_enter(&sc->sc_lock); 3419 err = usb_insert_transfer(xfer); 3420 mutex_exit(&sc->sc_lock); 3421 if (err) 3422 return (err); 3423 3424 /* Pipe isn't running, start first */ 3425 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3426 } 3427 3428 Static usbd_status 3429 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3430 { 3431 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3432 usbd_status err; 3433 3434 if (sc->sc_dying) 3435 return (USBD_IOERROR); 3436 3437 #ifdef DIAGNOSTIC 3438 if (!(xfer->rqflags & URQ_REQUEST)) { 3439 /* XXX panic */ 3440 printf("ehci_device_ctrl_transfer: not a request\n"); 3441 return (USBD_INVAL); 3442 } 3443 #endif 3444 3445 err = ehci_device_request(xfer); 3446 if (err) { 3447 return (err); 3448 } 3449 3450 if (sc->sc_bus.use_polling) 3451 ehci_waitintr(sc, xfer); 3452 3453 return (USBD_IN_PROGRESS); 3454 } 3455 3456 Static void 3457 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3458 { 3459 struct ehci_xfer *ex = EXFER(xfer); 3460 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3461 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3462 usb_device_request_t *req = &xfer->request; 3463 int len = UGETW(req->wLength); 3464 int rd = req->bmRequestType & UT_READ; 3465 3466 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3467 3468 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3469 3470 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3471 3472 #ifdef DIAGNOSTIC 3473 if (!(xfer->rqflags & URQ_REQUEST)) { 3474 panic("ehci_ctrl_done: not a request"); 3475 } 3476 #endif 3477 3478 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3479 ehci_del_intr_list(sc, ex); /* remove from active list */ 3480 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3481 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3482 BUS_DMASYNC_POSTWRITE); 3483 if (len) 3484 usb_syncmem(&xfer->dmabuf, 0, len, 3485 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3486 } 3487 3488 USBHIST_LOG(ehcidebug, "length=%d", xfer->actlen, 0, 0, 0); 3489 } 3490 3491 /* Abort a device control request. */ 3492 Static void 3493 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3494 { 3495 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3496 3497 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3498 ehci_abort_xfer(xfer, USBD_CANCELLED); 3499 } 3500 3501 /* Close a device control pipe. */ 3502 Static void 3503 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3504 { 3505 ehci_softc_t *sc = pipe->device->bus->hci_private; 3506 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3507 3508 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3509 3510 KASSERT(mutex_owned(&sc->sc_lock)); 3511 3512 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3513 3514 ehci_close_pipe(pipe, sc->sc_async_head); 3515 } 3516 3517 Static usbd_status 3518 ehci_device_request(usbd_xfer_handle xfer) 3519 { 3520 #define exfer EXFER(xfer) 3521 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3522 usb_device_request_t *req = &xfer->request; 3523 usbd_device_handle dev = epipe->pipe.device; 3524 ehci_softc_t *sc = dev->bus->hci_private; 3525 ehci_soft_qtd_t *setup, *stat, *next; 3526 ehci_soft_qh_t *sqh; 3527 int isread; 3528 int len; 3529 usbd_status err; 3530 3531 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3532 3533 isread = req->bmRequestType & UT_READ; 3534 len = UGETW(req->wLength); 3535 3536 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3537 "wValue=0x%04x, wIndex=0x%04x", 3538 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3539 UGETW(req->wIndex)); 3540 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3541 len, dev->address, 3542 epipe->pipe.endpoint->edesc->bEndpointAddress, 0); 3543 3544 setup = ehci_alloc_sqtd(sc); 3545 if (setup == NULL) { 3546 err = USBD_NOMEM; 3547 goto bad1; 3548 } 3549 stat = ehci_alloc_sqtd(sc); 3550 if (stat == NULL) { 3551 err = USBD_NOMEM; 3552 goto bad2; 3553 } 3554 3555 mutex_enter(&sc->sc_lock); 3556 3557 sqh = epipe->sqh; 3558 3559 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->address, 3560 "address QH %d pipe %d\n", 3561 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->address); 3562 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3563 UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize), 3564 "MPS QH %d pipe %d\n", 3565 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3566 UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)); 3567 3568 /* Set up data transaction */ 3569 if (len != 0) { 3570 ehci_soft_qtd_t *end; 3571 3572 /* Start toggle at 1. */ 3573 epipe->nexttoggle = 1; 3574 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3575 &next, &end); 3576 if (err) 3577 goto bad3; 3578 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3579 end->nextqtd = stat; 3580 end->qtd.qtd_next = end->qtd.qtd_altnext = 3581 htole32(stat->physaddr); 3582 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3584 } else { 3585 next = stat; 3586 } 3587 3588 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3589 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3590 3591 /* Clear toggle */ 3592 setup->qtd.qtd_status = htole32( 3593 EHCI_QTD_ACTIVE | 3594 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3595 EHCI_QTD_SET_CERR(3) | 3596 EHCI_QTD_SET_TOGGLE(0) | 3597 EHCI_QTD_SET_BYTES(sizeof *req) 3598 ); 3599 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3600 setup->qtd.qtd_buffer_hi[0] = 0; 3601 setup->nextqtd = next; 3602 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3603 setup->xfer = xfer; 3604 setup->len = sizeof *req; 3605 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3607 3608 stat->qtd.qtd_status = htole32( 3609 EHCI_QTD_ACTIVE | 3610 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3611 EHCI_QTD_SET_CERR(3) | 3612 EHCI_QTD_SET_TOGGLE(1) | 3613 EHCI_QTD_IOC 3614 ); 3615 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3616 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3617 stat->nextqtd = NULL; 3618 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3619 stat->xfer = xfer; 3620 stat->len = 0; 3621 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3622 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3623 3624 #ifdef EHCI_DEBUG 3625 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3626 ehci_dump_sqh(sqh); 3627 ehci_dump_sqtds(setup); 3628 #endif 3629 3630 exfer->sqtdstart = setup; 3631 exfer->sqtdend = stat; 3632 #ifdef DIAGNOSTIC 3633 if (!exfer->isdone) { 3634 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3635 } 3636 exfer->isdone = 0; 3637 #endif 3638 3639 /* Insert qTD in QH list. */ 3640 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3641 if (xfer->timeout && !sc->sc_bus.use_polling) { 3642 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3643 ehci_timeout, xfer); 3644 } 3645 ehci_add_intr_list(sc, exfer); 3646 xfer->status = USBD_IN_PROGRESS; 3647 mutex_exit(&sc->sc_lock); 3648 3649 #ifdef EHCI_DEBUG 3650 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3651 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3652 // delay(10000); 3653 ehci_dump_regs(sc); 3654 ehci_dump_sqh(sc->sc_async_head); 3655 ehci_dump_sqh(sqh); 3656 ehci_dump_sqtds(setup); 3657 #endif 3658 3659 return (USBD_NORMAL_COMPLETION); 3660 3661 bad3: 3662 mutex_exit(&sc->sc_lock); 3663 ehci_free_sqtd(sc, stat); 3664 bad2: 3665 ehci_free_sqtd(sc, setup); 3666 bad1: 3667 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3668 mutex_enter(&sc->sc_lock); 3669 xfer->status = err; 3670 usb_transfer_complete(xfer); 3671 mutex_exit(&sc->sc_lock); 3672 return (err); 3673 #undef exfer 3674 } 3675 3676 /* 3677 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3678 * qTD status, or miss signalling occasionally under heavy load. If the host 3679 * machine is too fast, we we can miss transaction completion - when we scan 3680 * the active list the transaction still seems to be active. This generally 3681 * exhibits itself as a umass stall that never recovers. 3682 * 3683 * We work around this behaviour by setting up this callback after any softintr 3684 * that completes with transactions still pending, giving us another chance to 3685 * check for completion after the writeback has taken place. 3686 */ 3687 Static void 3688 ehci_intrlist_timeout(void *arg) 3689 { 3690 ehci_softc_t *sc = arg; 3691 3692 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3693 3694 usb_schedsoftintr(&sc->sc_bus); 3695 } 3696 3697 /************************/ 3698 3699 Static usbd_status 3700 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3701 { 3702 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3703 usbd_status err; 3704 3705 /* Insert last in queue. */ 3706 mutex_enter(&sc->sc_lock); 3707 err = usb_insert_transfer(xfer); 3708 mutex_exit(&sc->sc_lock); 3709 if (err) 3710 return (err); 3711 3712 /* Pipe isn't running, start first */ 3713 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3714 } 3715 3716 Static usbd_status 3717 ehci_device_bulk_start(usbd_xfer_handle xfer) 3718 { 3719 #define exfer EXFER(xfer) 3720 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3721 usbd_device_handle dev = epipe->pipe.device; 3722 ehci_softc_t *sc = dev->bus->hci_private; 3723 ehci_soft_qtd_t *data, *dataend; 3724 ehci_soft_qh_t *sqh; 3725 usbd_status err; 3726 int len, isread, endpt; 3727 3728 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3729 3730 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3731 xfer, xfer->length, xfer->flags, 0); 3732 3733 if (sc->sc_dying) 3734 return (USBD_IOERROR); 3735 3736 #ifdef DIAGNOSTIC 3737 if (xfer->rqflags & URQ_REQUEST) 3738 panic("ehci_device_bulk_start: a request"); 3739 #endif 3740 3741 mutex_enter(&sc->sc_lock); 3742 3743 len = xfer->length; 3744 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3745 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3746 sqh = epipe->sqh; 3747 3748 epipe->u.bulk.length = len; 3749 3750 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3751 &dataend); 3752 if (err) { 3753 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3754 xfer->status = err; 3755 usb_transfer_complete(xfer); 3756 mutex_exit(&sc->sc_lock); 3757 return (err); 3758 } 3759 3760 #ifdef EHCI_DEBUG 3761 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 3762 ehci_dump_sqh(sqh); 3763 ehci_dump_sqtds(data); 3764 #endif 3765 3766 /* Set up interrupt info. */ 3767 exfer->sqtdstart = data; 3768 exfer->sqtdend = dataend; 3769 #ifdef DIAGNOSTIC 3770 if (!exfer->isdone) { 3771 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3772 } 3773 exfer->isdone = 0; 3774 #endif 3775 3776 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3777 if (xfer->timeout && !sc->sc_bus.use_polling) { 3778 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3779 ehci_timeout, xfer); 3780 } 3781 ehci_add_intr_list(sc, exfer); 3782 xfer->status = USBD_IN_PROGRESS; 3783 mutex_exit(&sc->sc_lock); 3784 3785 #ifdef EHCI_DEBUG 3786 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3787 // delay(10000); 3788 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3789 ehci_dump_regs(sc); 3790 #if 0 3791 printf("async_head:\n"); 3792 ehci_dump_sqh(sc->sc_async_head); 3793 #endif 3794 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3795 ehci_dump_sqh(sqh); 3796 ehci_dump_sqtds(data); 3797 #endif 3798 3799 if (sc->sc_bus.use_polling) 3800 ehci_waitintr(sc, xfer); 3801 3802 return (USBD_IN_PROGRESS); 3803 #undef exfer 3804 } 3805 3806 Static void 3807 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3808 { 3809 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3810 3811 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3812 ehci_abort_xfer(xfer, USBD_CANCELLED); 3813 } 3814 3815 /* 3816 * Close a device bulk pipe. 3817 */ 3818 Static void 3819 ehci_device_bulk_close(usbd_pipe_handle pipe) 3820 { 3821 ehci_softc_t *sc = pipe->device->bus->hci_private; 3822 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3823 3824 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3825 3826 KASSERT(mutex_owned(&sc->sc_lock)); 3827 3828 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3829 pipe->endpoint->datatoggle = epipe->nexttoggle; 3830 ehci_close_pipe(pipe, sc->sc_async_head); 3831 } 3832 3833 Static void 3834 ehci_device_bulk_done(usbd_xfer_handle xfer) 3835 { 3836 struct ehci_xfer *ex = EXFER(xfer); 3837 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3838 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3839 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3840 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3841 3842 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3843 3844 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3845 xfer, xfer->actlen, 0, 0); 3846 3847 KASSERT(mutex_owned(&sc->sc_lock)); 3848 3849 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3850 ehci_del_intr_list(sc, ex); /* remove from active list */ 3851 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3852 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3853 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3854 } 3855 3856 USBHIST_LOG(ehcidebug, "length=%d", xfer->actlen, 0, 0, 0); 3857 } 3858 3859 /************************/ 3860 3861 Static usbd_status 3862 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3863 { 3864 struct ehci_soft_islot *isp; 3865 int islot, lev; 3866 3867 /* Find a poll rate that is large enough. */ 3868 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3869 if (EHCI_ILEV_IVAL(lev) <= ival) 3870 break; 3871 3872 /* Pick an interrupt slot at the right level. */ 3873 /* XXX could do better than picking at random */ 3874 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3875 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3876 3877 sqh->islot = islot; 3878 isp = &sc->sc_islots[islot]; 3879 mutex_enter(&sc->sc_lock); 3880 ehci_add_qh(sc, sqh, isp->sqh); 3881 mutex_exit(&sc->sc_lock); 3882 3883 return (USBD_NORMAL_COMPLETION); 3884 } 3885 3886 Static usbd_status 3887 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3888 { 3889 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3890 usbd_status err; 3891 3892 /* Insert last in queue. */ 3893 mutex_enter(&sc->sc_lock); 3894 err = usb_insert_transfer(xfer); 3895 mutex_exit(&sc->sc_lock); 3896 if (err) 3897 return (err); 3898 3899 /* 3900 * Pipe isn't running (otherwise err would be USBD_INPROG), 3901 * so start it first. 3902 */ 3903 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3904 } 3905 3906 Static usbd_status 3907 ehci_device_intr_start(usbd_xfer_handle xfer) 3908 { 3909 #define exfer EXFER(xfer) 3910 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3911 usbd_device_handle dev = xfer->pipe->device; 3912 ehci_softc_t *sc = dev->bus->hci_private; 3913 ehci_soft_qtd_t *data, *dataend; 3914 ehci_soft_qh_t *sqh; 3915 usbd_status err; 3916 int len, isread, endpt; 3917 3918 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3919 3920 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3921 xfer, xfer->length, xfer->flags, 0); 3922 3923 if (sc->sc_dying) 3924 return (USBD_IOERROR); 3925 3926 #ifdef DIAGNOSTIC 3927 if (xfer->rqflags & URQ_REQUEST) 3928 panic("ehci_device_intr_start: a request"); 3929 #endif 3930 3931 mutex_enter(&sc->sc_lock); 3932 3933 len = xfer->length; 3934 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3935 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3936 sqh = epipe->sqh; 3937 3938 epipe->u.intr.length = len; 3939 3940 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3941 &dataend); 3942 if (err) { 3943 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3944 xfer->status = err; 3945 usb_transfer_complete(xfer); 3946 mutex_exit(&sc->sc_lock); 3947 return (err); 3948 } 3949 3950 #ifdef EHCI_DEBUG 3951 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 3952 ehci_dump_sqh(sqh); 3953 ehci_dump_sqtds(data); 3954 #endif 3955 3956 /* Set up interrupt info. */ 3957 exfer->sqtdstart = data; 3958 exfer->sqtdend = dataend; 3959 #ifdef DIAGNOSTIC 3960 if (!exfer->isdone) { 3961 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3962 } 3963 exfer->isdone = 0; 3964 #endif 3965 3966 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3967 if (xfer->timeout && !sc->sc_bus.use_polling) { 3968 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3969 ehci_timeout, xfer); 3970 } 3971 ehci_add_intr_list(sc, exfer); 3972 xfer->status = USBD_IN_PROGRESS; 3973 mutex_exit(&sc->sc_lock); 3974 3975 #ifdef EHCI_DEBUG 3976 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3977 // delay(10000); 3978 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3979 ehci_dump_regs(sc); 3980 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3981 ehci_dump_sqh(sqh); 3982 ehci_dump_sqtds(data); 3983 #endif 3984 3985 if (sc->sc_bus.use_polling) 3986 ehci_waitintr(sc, xfer); 3987 3988 return (USBD_IN_PROGRESS); 3989 #undef exfer 3990 } 3991 3992 Static void 3993 ehci_device_intr_abort(usbd_xfer_handle xfer) 3994 { 3995 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3996 3997 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3998 KASSERT(xfer->pipe->intrxfer == xfer); 3999 4000 /* 4001 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4002 * async doorbell. That's dependent on the async list, wheras 4003 * intr xfers are periodic, should not use this? 4004 */ 4005 ehci_abort_xfer(xfer, USBD_CANCELLED); 4006 } 4007 4008 Static void 4009 ehci_device_intr_close(usbd_pipe_handle pipe) 4010 { 4011 ehci_softc_t *sc = pipe->device->bus->hci_private; 4012 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 4013 struct ehci_soft_islot *isp; 4014 4015 KASSERT(mutex_owned(&sc->sc_lock)); 4016 4017 isp = &sc->sc_islots[epipe->sqh->islot]; 4018 ehci_close_pipe(pipe, isp->sqh); 4019 } 4020 4021 Static void 4022 ehci_device_intr_done(usbd_xfer_handle xfer) 4023 { 4024 #define exfer EXFER(xfer) 4025 struct ehci_xfer *ex = EXFER(xfer); 4026 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 4027 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 4028 ehci_soft_qtd_t *data, *dataend; 4029 ehci_soft_qh_t *sqh; 4030 usbd_status err; 4031 int len, isread, endpt; 4032 4033 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4034 4035 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4036 xfer, xfer->actlen, 0, 0); 4037 4038 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 4039 4040 if (xfer->pipe->repeat) { 4041 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4042 4043 len = epipe->u.intr.length; 4044 xfer->length = len; 4045 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 4046 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4047 usb_syncmem(&xfer->dmabuf, 0, len, 4048 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4049 sqh = epipe->sqh; 4050 4051 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4052 &data, &dataend); 4053 if (err) { 4054 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4055 xfer->status = err; 4056 return; 4057 } 4058 4059 /* Set up interrupt info. */ 4060 exfer->sqtdstart = data; 4061 exfer->sqtdend = dataend; 4062 #ifdef DIAGNOSTIC 4063 if (!exfer->isdone) { 4064 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4065 exfer, 0, 0, 0); 4066 printf("ehci_device_intr_done: not done, ex=%p\n", 4067 exfer); 4068 } 4069 exfer->isdone = 0; 4070 #endif 4071 4072 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4073 if (xfer->timeout && !sc->sc_bus.use_polling) { 4074 callout_reset(&xfer->timeout_handle, 4075 mstohz(xfer->timeout), ehci_timeout, xfer); 4076 } 4077 4078 xfer->status = USBD_IN_PROGRESS; 4079 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4080 ehci_del_intr_list(sc, ex); /* remove from active list */ 4081 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4082 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 4083 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4084 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 4085 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4086 } 4087 #undef exfer 4088 } 4089 4090 /************************/ 4091 4092 Static usbd_status 4093 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4094 { 4095 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 4096 usbd_status err; 4097 4098 mutex_enter(&sc->sc_lock); 4099 err = usb_insert_transfer(xfer); 4100 mutex_exit(&sc->sc_lock); 4101 if (err && err != USBD_IN_PROGRESS) 4102 return err; 4103 4104 return ehci_device_isoc_start(xfer); 4105 } 4106 4107 Static usbd_status 4108 ehci_device_isoc_start(usbd_xfer_handle xfer) 4109 { 4110 struct ehci_pipe *epipe; 4111 ehci_softc_t *sc; 4112 struct ehci_xfer *exfer; 4113 ehci_soft_itd_t *itd, *prev, *start, *stop; 4114 usb_dma_t *dma_buf; 4115 int i, j, k, frames, uframes, ufrperframe; 4116 int trans_count, offs, total_length; 4117 int frindex; 4118 4119 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4120 4121 start = NULL; 4122 prev = NULL; 4123 itd = NULL; 4124 trans_count = 0; 4125 total_length = 0; 4126 exfer = (struct ehci_xfer *) xfer; 4127 sc = xfer->pipe->device->bus->hci_private; 4128 epipe = (struct ehci_pipe *)xfer->pipe; 4129 4130 /* 4131 * To allow continuous transfers, above we start all transfers 4132 * immediately. However, we're still going to get usbd_start_next call 4133 * this when another xfer completes. So, check if this is already 4134 * in progress or not 4135 */ 4136 4137 if (exfer->itdstart != NULL) 4138 return USBD_IN_PROGRESS; 4139 4140 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4141 xfer, xfer->length, xfer->flags, 0); 4142 4143 if (sc->sc_dying) 4144 return USBD_IOERROR; 4145 4146 /* 4147 * To avoid complication, don't allow a request right now that'll span 4148 * the entire frame table. To within 4 frames, to allow some leeway 4149 * on either side of where the hc currently is. 4150 */ 4151 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 4152 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 4153 USBHIST_LOG(ehcidebug, 4154 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4155 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4156 return USBD_INVAL; 4157 } 4158 4159 #ifdef DIAGNOSTIC 4160 if (xfer->rqflags & URQ_REQUEST) 4161 panic("ehci_device_isoc_start: request"); 4162 4163 if (!exfer->isdone) { 4164 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4165 0, 0, 0); 4166 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4167 } 4168 exfer->isdone = 0; 4169 #endif 4170 4171 /* 4172 * Step 1: Allocate and initialize itds, how many do we need? 4173 * One per transfer if interval >= 8 microframes, fewer if we use 4174 * multiple microframes per frame. 4175 */ 4176 4177 i = epipe->pipe.endpoint->edesc->bInterval; 4178 if (i > 16 || i == 0) { 4179 /* Spec page 271 says intervals > 16 are invalid */ 4180 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4181 return USBD_INVAL; 4182 } 4183 4184 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4185 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4186 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4187 4188 if (frames == 0) { 4189 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4190 return USBD_INVAL; 4191 } 4192 4193 dma_buf = &xfer->dmabuf; 4194 offs = 0; 4195 4196 for (i = 0; i < frames; i++) { 4197 int froffs = offs; 4198 itd = ehci_alloc_itd(sc); 4199 4200 if (prev != NULL) { 4201 prev->itd.itd_next = 4202 htole32(itd->physaddr | EHCI_LINK_ITD); 4203 usb_syncmem(&itd->dma, 4204 itd->offs + offsetof(ehci_itd_t, itd_next), 4205 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4206 4207 prev->xfer_next = itd; 4208 } else { 4209 start = itd; 4210 } 4211 4212 /* 4213 * Step 1.5, initialize uframes 4214 */ 4215 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4216 /* Calculate which page in the list this starts in */ 4217 int addr = DMAADDR(dma_buf, froffs); 4218 addr = EHCI_PAGE_OFFSET(addr); 4219 addr += (offs - froffs); 4220 addr = EHCI_PAGE(addr); 4221 addr /= EHCI_PAGE_SIZE; 4222 4223 /* This gets the initial offset into the first page, 4224 * looks how far further along the current uframe 4225 * offset is. Works out how many pages that is. 4226 */ 4227 4228 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4229 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4230 EHCI_ITD_SET_PG(addr) | 4231 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4232 4233 total_length += xfer->frlengths[trans_count]; 4234 offs += xfer->frlengths[trans_count]; 4235 trans_count++; 4236 4237 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4238 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4239 break; 4240 } 4241 } 4242 4243 /* Step 1.75, set buffer pointers. To simplify matters, all 4244 * pointers are filled out for the next 7 hardware pages in 4245 * the dma block, so no need to worry what pages to cover 4246 * and what to not. 4247 */ 4248 4249 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4250 /* 4251 * Don't try to lookup a page that's past the end 4252 * of buffer 4253 */ 4254 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4255 if (page_offs >= dma_buf->block->size) 4256 break; 4257 4258 unsigned long long page = DMAADDR(dma_buf, page_offs); 4259 page = EHCI_PAGE(page); 4260 itd->itd.itd_bufr[j] = 4261 htole32(EHCI_ITD_SET_BPTR(page)); 4262 itd->itd.itd_bufr_hi[j] = 4263 htole32(page >> 32); 4264 } 4265 4266 /* 4267 * Other special values 4268 */ 4269 4270 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4271 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4272 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4273 4274 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4275 ? 1 : 0; 4276 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4277 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4278 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4279 4280 /* FIXME: handle invalid trans */ 4281 itd->itd.itd_bufr[2] |= 4282 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4283 4284 usb_syncmem(&itd->dma, 4285 itd->offs + offsetof(ehci_itd_t, itd_next), 4286 sizeof(ehci_itd_t), 4287 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4288 4289 prev = itd; 4290 } /* End of frame */ 4291 4292 stop = itd; 4293 stop->xfer_next = NULL; 4294 exfer->isoc_len = total_length; 4295 4296 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4297 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4298 4299 /* 4300 * Part 2: Transfer descriptors have now been set up, now they must 4301 * be scheduled into the period frame list. Erk. Not wanting to 4302 * complicate matters, transfer is denied if the transfer spans 4303 * more than the period frame list. 4304 */ 4305 4306 mutex_enter(&sc->sc_lock); 4307 4308 /* Start inserting frames */ 4309 if (epipe->u.isoc.cur_xfers > 0) { 4310 frindex = epipe->u.isoc.next_frame; 4311 } else { 4312 frindex = EOREAD4(sc, EHCI_FRINDEX); 4313 frindex = frindex >> 3; /* Erase microframe index */ 4314 frindex += 2; 4315 } 4316 4317 if (frindex >= sc->sc_flsize) 4318 frindex &= (sc->sc_flsize - 1); 4319 4320 /* What's the frame interval? */ 4321 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4322 if (i / USB_UFRAMES_PER_FRAME == 0) 4323 i = 1; 4324 else 4325 i /= USB_UFRAMES_PER_FRAME; 4326 4327 itd = start; 4328 for (j = 0; j < frames; j++) { 4329 if (itd == NULL) 4330 panic("ehci: unexpectedly ran out of isoc itds, isoc_start"); 4331 4332 itd->itd.itd_next = sc->sc_flist[frindex]; 4333 if (itd->itd.itd_next == 0) 4334 /* FIXME: frindex table gets initialized to NULL 4335 * or EHCI_NULL? */ 4336 itd->itd.itd_next = EHCI_NULL; 4337 4338 usb_syncmem(&itd->dma, 4339 itd->offs + offsetof(ehci_itd_t, itd_next), 4340 sizeof(itd->itd.itd_next), 4341 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4342 4343 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4344 4345 usb_syncmem(&sc->sc_fldma, 4346 sizeof(ehci_link_t) * frindex, 4347 sizeof(ehci_link_t), 4348 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4349 4350 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4351 sc->sc_softitds[frindex] = itd; 4352 if (itd->u.frame_list.next != NULL) 4353 itd->u.frame_list.next->u.frame_list.prev = itd; 4354 itd->slot = frindex; 4355 itd->u.frame_list.prev = NULL; 4356 4357 frindex += i; 4358 if (frindex >= sc->sc_flsize) 4359 frindex -= sc->sc_flsize; 4360 4361 itd = itd->xfer_next; 4362 } 4363 4364 epipe->u.isoc.cur_xfers++; 4365 epipe->u.isoc.next_frame = frindex; 4366 4367 exfer->itdstart = start; 4368 exfer->itdend = stop; 4369 exfer->sqtdstart = NULL; 4370 exfer->sqtdend = NULL; 4371 4372 ehci_add_intr_list(sc, exfer); 4373 xfer->status = USBD_IN_PROGRESS; 4374 xfer->done = 0; 4375 mutex_exit(&sc->sc_lock); 4376 4377 if (sc->sc_bus.use_polling) { 4378 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4379 ehci_waitintr(sc, xfer); 4380 } 4381 4382 return USBD_IN_PROGRESS; 4383 } 4384 4385 Static void 4386 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4387 { 4388 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4389 4390 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4391 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4392 } 4393 4394 Static void 4395 ehci_device_isoc_close(usbd_pipe_handle pipe) 4396 { 4397 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4398 4399 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4400 } 4401 4402 Static void 4403 ehci_device_isoc_done(usbd_xfer_handle xfer) 4404 { 4405 struct ehci_xfer *exfer; 4406 ehci_softc_t *sc; 4407 struct ehci_pipe *epipe; 4408 4409 exfer = EXFER(xfer); 4410 sc = xfer->pipe->device->bus->hci_private; 4411 epipe = (struct ehci_pipe *) xfer->pipe; 4412 4413 KASSERT(mutex_owned(&sc->sc_lock)); 4414 4415 epipe->u.isoc.cur_xfers--; 4416 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4417 ehci_del_intr_list(sc, exfer); 4418 ehci_rem_free_itd_chain(sc, exfer); 4419 } 4420 4421 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4422 BUS_DMASYNC_POSTREAD); 4423 4424 } 4425
Indexes created Mon Sep 22 21:09:42 GMT 2025