ehci.c revision 1.249
1 /* $NetBSD: ehci.c,v 1.249 2016/04/23 10:15:31 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.249 2016/04/23 10:15:31 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_timeout(void *); 171 Static void ehci_timeout_task(void *); 172 Static void ehci_intrlist_timeout(void *); 173 Static void ehci_doorbell(void *); 174 Static void ehci_pcd(void *); 175 176 Static struct usbd_xfer * 177 ehci_allocx(struct usbd_bus *, unsigned int); 178 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 179 180 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 181 Static int ehci_roothub_ctrl(struct usbd_bus *, 182 usb_device_request_t *, void *, int); 183 184 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 185 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 186 Static void ehci_root_intr_abort(struct usbd_xfer *); 187 Static void ehci_root_intr_close(struct usbd_pipe *); 188 Static void ehci_root_intr_done(struct usbd_xfer *); 189 190 Static int ehci_device_ctrl_init(struct usbd_xfer *); 191 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 193 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 194 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 195 Static void ehci_device_ctrl_close(struct usbd_pipe *); 196 Static void ehci_device_ctrl_done(struct usbd_xfer *); 197 198 Static int ehci_device_bulk_init(struct usbd_xfer *); 199 Static void ehci_device_bulk_fini(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 201 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 202 Static void ehci_device_bulk_abort(struct usbd_xfer *); 203 Static void ehci_device_bulk_close(struct usbd_pipe *); 204 Static void ehci_device_bulk_done(struct usbd_xfer *); 205 206 Static int ehci_device_intr_init(struct usbd_xfer *); 207 Static void ehci_device_intr_fini(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 209 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 210 Static void ehci_device_intr_abort(struct usbd_xfer *); 211 Static void ehci_device_intr_close(struct usbd_pipe *); 212 Static void ehci_device_intr_done(struct usbd_xfer *); 213 214 Static int ehci_device_isoc_init(struct usbd_xfer *); 215 Static void ehci_device_isoc_fini(struct usbd_xfer *); 216 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 217 Static void ehci_device_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_isoc_done(struct usbd_xfer *); 220 221 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 223 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 225 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 226 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 227 228 Static void ehci_device_clear_toggle(struct usbd_pipe *); 229 Static void ehci_noop(struct usbd_pipe *); 230 231 Static void ehci_disown(ehci_softc_t *, int, int); 232 233 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 234 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 235 236 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 237 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 238 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 239 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 240 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 241 242 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 243 int, int, int *, ehci_soft_qtd_t **); 244 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 245 246 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 247 Static ehci_soft_sitd_t * 248 ehci_alloc_sitd(ehci_softc_t *); 249 250 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 251 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 252 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 253 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 254 255 static inline void 256 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 257 { 258 259 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 260 } 261 262 static inline void 263 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 264 { 265 266 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 267 } 268 269 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 270 271 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 272 int); 273 274 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 275 ehci_soft_qh_t *); 276 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 277 ehci_soft_qh_t *); 278 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 279 Static void ehci_sync_hc(ehci_softc_t *); 280 281 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 282 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 283 284 #ifdef EHCI_DEBUG 285 Static ehci_softc_t *theehci; 286 void ehci_dump(void); 287 #endif 288 289 #ifdef EHCI_DEBUG 290 Static void ehci_dump_regs(ehci_softc_t *); 291 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 292 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 293 Static void ehci_dump_qtd(ehci_qtd_t *); 294 Static void ehci_dump_sqh(ehci_soft_qh_t *); 295 Static void ehci_dump_sitd(struct ehci_soft_itd *); 296 Static void ehci_dump_itds(ehci_soft_itd_t *); 297 Static void ehci_dump_itd(struct ehci_soft_itd *); 298 Static void ehci_dump_exfer(struct ehci_xfer *); 299 #endif 300 301 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 302 303 static inline void 304 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 305 { 306 307 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 308 } 309 310 static inline void 311 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 312 { 313 314 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 315 } 316 317 Static const struct usbd_bus_methods ehci_bus_methods = { 318 .ubm_open = ehci_open, 319 .ubm_softint = ehci_softintr, 320 .ubm_dopoll = ehci_poll, 321 .ubm_allocx = ehci_allocx, 322 .ubm_freex = ehci_freex, 323 .ubm_getlock = ehci_get_lock, 324 .ubm_rhctrl = ehci_roothub_ctrl, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 328 .upm_transfer = ehci_root_intr_transfer, 329 .upm_start = ehci_root_intr_start, 330 .upm_abort = ehci_root_intr_abort, 331 .upm_close = ehci_root_intr_close, 332 .upm_cleartoggle = ehci_noop, 333 .upm_done = ehci_root_intr_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 337 .upm_init = ehci_device_ctrl_init, 338 .upm_fini = ehci_device_ctrl_fini, 339 .upm_transfer = ehci_device_ctrl_transfer, 340 .upm_start = ehci_device_ctrl_start, 341 .upm_abort = ehci_device_ctrl_abort, 342 .upm_close = ehci_device_ctrl_close, 343 .upm_cleartoggle = ehci_noop, 344 .upm_done = ehci_device_ctrl_done, 345 }; 346 347 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 348 .upm_init = ehci_device_intr_init, 349 .upm_fini = ehci_device_intr_fini, 350 .upm_transfer = ehci_device_intr_transfer, 351 .upm_start = ehci_device_intr_start, 352 .upm_abort = ehci_device_intr_abort, 353 .upm_close = ehci_device_intr_close, 354 .upm_cleartoggle = ehci_device_clear_toggle, 355 .upm_done = ehci_device_intr_done, 356 }; 357 358 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 359 .upm_init = ehci_device_bulk_init, 360 .upm_fini = ehci_device_bulk_fini, 361 .upm_transfer = ehci_device_bulk_transfer, 362 .upm_start = ehci_device_bulk_start, 363 .upm_abort = ehci_device_bulk_abort, 364 .upm_close = ehci_device_bulk_close, 365 .upm_cleartoggle = ehci_device_clear_toggle, 366 .upm_done = ehci_device_bulk_done, 367 }; 368 369 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 370 .upm_init = ehci_device_isoc_init, 371 .upm_fini = ehci_device_isoc_fini, 372 .upm_transfer = ehci_device_isoc_transfer, 373 .upm_abort = ehci_device_isoc_abort, 374 .upm_close = ehci_device_isoc_close, 375 .upm_cleartoggle = ehci_noop, 376 .upm_done = ehci_device_isoc_done, 377 }; 378 379 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 380 .upm_init = ehci_device_fs_isoc_init, 381 .upm_fini = ehci_device_fs_isoc_fini, 382 .upm_transfer = ehci_device_fs_isoc_transfer, 383 .upm_abort = ehci_device_fs_isoc_abort, 384 .upm_close = ehci_device_fs_isoc_close, 385 .upm_cleartoggle = ehci_noop, 386 .upm_done = ehci_device_fs_isoc_done, 387 }; 388 389 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 390 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 391 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 392 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 393 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 394 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 395 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 396 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 397 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 398 }; 399 400 int 401 ehci_init(ehci_softc_t *sc) 402 { 403 uint32_t vers, sparams, cparams, hcr; 404 u_int i; 405 usbd_status err; 406 ehci_soft_qh_t *sqh; 407 u_int ncomp; 408 409 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 410 #ifdef EHCI_DEBUG 411 theehci = sc; 412 #endif 413 414 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 415 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 416 cv_init(&sc->sc_softwake_cv, "ehciab"); 417 cv_init(&sc->sc_doorbell, "ehcidi"); 418 419 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 420 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 421 422 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 423 ehci_doorbell, sc); 424 KASSERT(sc->sc_doorbell_si != NULL); 425 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 426 ehci_pcd, sc); 427 KASSERT(sc->sc_pcd_si != NULL); 428 429 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 430 431 vers = EREAD2(sc, EHCI_HCIVERSION); 432 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 433 vers >> 8, vers & 0xff); 434 435 sparams = EREAD4(sc, EHCI_HCSPARAMS); 436 DPRINTF("sparams=%#x", sparams, 0, 0, 0); 437 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 438 ncomp = EHCI_HCS_N_CC(sparams); 439 if (ncomp != sc->sc_ncomp) { 440 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 441 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 442 #if NOHCI == 0 || NUHCI == 0 443 aprint_error("%s: ohci or uhci probably not configured\n", 444 device_xname(sc->sc_dev)); 445 #endif 446 if (ncomp < sc->sc_ncomp) 447 sc->sc_ncomp = ncomp; 448 } 449 if (sc->sc_ncomp > 0) { 450 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 451 aprint_normal("%s: companion controller%s, %d port%s each:", 452 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 453 EHCI_HCS_N_PCC(sparams), 454 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 455 for (i = 0; i < sc->sc_ncomp; i++) 456 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 457 aprint_normal("\n"); 458 } 459 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 460 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 461 462 cparams = EREAD4(sc, EHCI_HCCPARAMS); 463 DPRINTF("cparams=%#x", cparams, 0, 0, 0); 464 465 if (EHCI_HCC_64BIT(cparams)) { 466 /* MUST clear segment register if 64 bit capable. */ 467 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 468 } 469 470 if (cparams & EHCI_HCC_IST_FULLFRAME) { 471 sc->sc_istthreshold = 0; 472 } else { 473 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 474 } 475 476 sc->sc_bus.ub_revision = USBREV_2_0; 477 sc->sc_bus.ub_usedma = true; 478 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 479 480 /* Reset the controller */ 481 DPRINTF("resetting", 0, 0, 0, 0); 482 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 483 usb_delay_ms(&sc->sc_bus, 1); 484 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 485 for (i = 0; i < 100; i++) { 486 usb_delay_ms(&sc->sc_bus, 1); 487 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 488 if (!hcr) 489 break; 490 } 491 if (hcr) { 492 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 493 return EIO; 494 } 495 if (sc->sc_vendor_init) 496 sc->sc_vendor_init(sc); 497 498 /* XXX need proper intr scheduling */ 499 sc->sc_rand = 96; 500 501 /* frame list size at default, read back what we got and use that */ 502 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 503 case 0: sc->sc_flsize = 1024; break; 504 case 1: sc->sc_flsize = 512; break; 505 case 2: sc->sc_flsize = 256; break; 506 case 3: return EIO; 507 } 508 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 509 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 510 if (err) 511 return err; 512 DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); 513 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 514 515 for (i = 0; i < sc->sc_flsize; i++) { 516 sc->sc_flist[i] = EHCI_NULL; 517 } 518 519 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 520 521 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 522 KM_SLEEP); 523 if (sc->sc_softitds == NULL) 524 return ENOMEM; 525 LIST_INIT(&sc->sc_freeitds); 526 LIST_INIT(&sc->sc_freesitds); 527 TAILQ_INIT(&sc->sc_intrhead); 528 529 /* Set up the bus struct. */ 530 sc->sc_bus.ub_methods = &ehci_bus_methods; 531 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 532 533 sc->sc_eintrs = EHCI_NORMAL_INTRS; 534 535 /* 536 * Allocate the interrupt dummy QHs. These are arranged to give poll 537 * intervals that are powers of 2 times 1ms. 538 */ 539 for (i = 0; i < EHCI_INTRQHS; i++) { 540 sqh = ehci_alloc_sqh(sc); 541 if (sqh == NULL) { 542 err = ENOMEM; 543 goto bad1; 544 } 545 sc->sc_islots[i].sqh = sqh; 546 } 547 for (i = 0; i < EHCI_INTRQHS; i++) { 548 sqh = sc->sc_islots[i].sqh; 549 if (i == 0) { 550 /* The last (1ms) QH terminates. */ 551 sqh->qh.qh_link = EHCI_NULL; 552 sqh->next = NULL; 553 } else { 554 /* Otherwise the next QH has half the poll interval */ 555 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 556 sqh->qh.qh_link = htole32(sqh->next->physaddr | 557 EHCI_LINK_QH); 558 } 559 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 560 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 561 sqh->qh.qh_curqtd = EHCI_NULL; 562 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 563 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 564 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 565 sqh->sqtd = NULL; 566 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 567 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 568 } 569 /* Point the frame list at the last level (128ms). */ 570 for (i = 0; i < sc->sc_flsize; i++) { 571 int j; 572 573 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 574 revbits[i & (EHCI_MAX_POLLRATE-1)]; 575 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 576 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 577 i)].sqh->physaddr); 578 } 579 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 580 BUS_DMASYNC_PREWRITE); 581 582 /* Allocate dummy QH that starts the async list. */ 583 sqh = ehci_alloc_sqh(sc); 584 if (sqh == NULL) { 585 err = ENOMEM; 586 goto bad1; 587 } 588 /* Fill the QH */ 589 sqh->qh.qh_endp = 590 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 591 sqh->qh.qh_link = 592 htole32(sqh->physaddr | EHCI_LINK_QH); 593 sqh->qh.qh_curqtd = EHCI_NULL; 594 sqh->next = NULL; 595 /* Fill the overlay qTD */ 596 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 597 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 598 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 599 sqh->sqtd = NULL; 600 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 601 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 602 #ifdef EHCI_DEBUG 603 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 604 ehci_dump_sqh(sqh); 605 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 606 #endif 607 608 /* Point to async list */ 609 sc->sc_async_head = sqh; 610 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 611 612 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 613 614 /* Turn on controller */ 615 EOWRITE4(sc, EHCI_USBCMD, 616 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 617 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 618 EHCI_CMD_ASE | 619 EHCI_CMD_PSE | 620 EHCI_CMD_RS); 621 622 /* Take over port ownership */ 623 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 624 625 for (i = 0; i < 100; i++) { 626 usb_delay_ms(&sc->sc_bus, 1); 627 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 628 if (!hcr) 629 break; 630 } 631 if (hcr) { 632 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 633 return EIO; 634 } 635 636 /* Enable interrupts */ 637 DPRINTF("enabling interupts", 0, 0, 0, 0); 638 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 639 640 return 0; 641 642 #if 0 643 bad2: 644 ehci_free_sqh(sc, sc->sc_async_head); 645 #endif 646 bad1: 647 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 648 return err; 649 } 650 651 int 652 ehci_intr(void *v) 653 { 654 ehci_softc_t *sc = v; 655 int ret = 0; 656 657 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 658 659 if (sc == NULL) 660 return 0; 661 662 mutex_spin_enter(&sc->sc_intr_lock); 663 664 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 665 goto done; 666 667 /* If we get an interrupt while polling, then just ignore it. */ 668 if (sc->sc_bus.ub_usepolling) { 669 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 670 671 if (intrs) 672 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 673 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 674 goto done; 675 } 676 677 ret = ehci_intr1(sc); 678 679 done: 680 mutex_spin_exit(&sc->sc_intr_lock); 681 return ret; 682 } 683 684 Static int 685 ehci_intr1(ehci_softc_t *sc) 686 { 687 uint32_t intrs, eintrs; 688 689 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 690 691 /* In case the interrupt occurs before initialization has completed. */ 692 if (sc == NULL) { 693 #ifdef DIAGNOSTIC 694 printf("ehci_intr1: sc == NULL\n"); 695 #endif 696 return 0; 697 } 698 699 KASSERT(mutex_owned(&sc->sc_intr_lock)); 700 701 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 702 if (!intrs) 703 return 0; 704 705 eintrs = intrs & sc->sc_eintrs; 706 DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, 707 EOREAD4(sc, EHCI_USBSTS), eintrs); 708 if (!eintrs) 709 return 0; 710 711 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 712 if (eintrs & EHCI_STS_IAA) { 713 DPRINTF("door bell", 0, 0, 0, 0); 714 kpreempt_disable(); 715 KASSERT(sc->sc_doorbell_si != NULL); 716 softint_schedule(sc->sc_doorbell_si); 717 kpreempt_enable(); 718 eintrs &= ~EHCI_STS_IAA; 719 } 720 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 721 DPRINTF("INT=%d ERRINT=%d", 722 eintrs & EHCI_STS_INT ? 1 : 0, 723 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 724 usb_schedsoftintr(&sc->sc_bus); 725 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 726 } 727 if (eintrs & EHCI_STS_HSE) { 728 printf("%s: unrecoverable error, controller halted\n", 729 device_xname(sc->sc_dev)); 730 /* XXX what else */ 731 } 732 if (eintrs & EHCI_STS_PCD) { 733 kpreempt_disable(); 734 KASSERT(sc->sc_pcd_si != NULL); 735 softint_schedule(sc->sc_pcd_si); 736 kpreempt_enable(); 737 eintrs &= ~EHCI_STS_PCD; 738 } 739 740 if (eintrs != 0) { 741 /* Block unprocessed interrupts. */ 742 sc->sc_eintrs &= ~eintrs; 743 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 744 printf("%s: blocking intrs 0x%x\n", 745 device_xname(sc->sc_dev), eintrs); 746 } 747 748 return 1; 749 } 750 751 Static void 752 ehci_doorbell(void *addr) 753 { 754 ehci_softc_t *sc = addr; 755 756 mutex_enter(&sc->sc_lock); 757 cv_broadcast(&sc->sc_doorbell); 758 mutex_exit(&sc->sc_lock); 759 } 760 761 Static void 762 ehci_pcd(void *addr) 763 { 764 ehci_softc_t *sc = addr; 765 struct usbd_xfer *xfer; 766 u_char *p; 767 int i, m; 768 769 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 770 771 mutex_enter(&sc->sc_lock); 772 xfer = sc->sc_intrxfer; 773 774 if (xfer == NULL) { 775 /* Just ignore the change. */ 776 goto done; 777 } 778 779 p = xfer->ux_buf; 780 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 781 memset(p, 0, xfer->ux_length); 782 for (i = 1; i <= m; i++) { 783 /* Pick out CHANGE bits from the status reg. */ 784 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 785 p[i/8] |= 1 << (i%8); 786 if (i % 8 == 7) 787 DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); 788 } 789 xfer->ux_actlen = xfer->ux_length; 790 xfer->ux_status = USBD_NORMAL_COMPLETION; 791 792 usb_transfer_complete(xfer); 793 794 done: 795 mutex_exit(&sc->sc_lock); 796 } 797 798 Static void 799 ehci_softintr(void *v) 800 { 801 struct usbd_bus *bus = v; 802 ehci_softc_t *sc = EHCI_BUS2SC(bus); 803 struct ehci_xfer *ex, *nextex; 804 805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 806 807 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 808 809 ex_completeq_t cq; 810 TAILQ_INIT(&cq); 811 812 /* 813 * The only explanation I can think of for why EHCI is as brain dead 814 * as UHCI interrupt-wise is that Intel was involved in both. 815 * An interrupt just tells us that something is done, we have no 816 * clue what, so we need to scan through all active transfers. :-( 817 */ 818 819 /* 820 * ehci_idone will remove transfer from sc->sc_intrhead if it's 821 * complete and add to our cq list 822 * 823 */ 824 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 825 switch (ex->ex_type) { 826 case EX_CTRL: 827 case EX_BULK: 828 case EX_INTR: 829 ehci_check_qh_intr(sc, ex, &cq); 830 break; 831 case EX_ISOC: 832 ehci_check_itd_intr(sc, ex, &cq); 833 break; 834 case EX_FS_ISOC: 835 ehci_check_sitd_intr(sc, ex, &cq); 836 break; 837 default: 838 KASSERT(false); 839 } 840 841 } 842 843 /* 844 * We abuse ex_next for the interrupt and complete lists and 845 * interrupt transfers will get re-added here so use 846 * the _SAFE version of TAILQ_FOREACH. 847 */ 848 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 849 usb_transfer_complete(&ex->ex_xfer); 850 } 851 852 /* Schedule a callout to catch any dropped transactions. */ 853 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 854 !TAILQ_EMPTY(&sc->sc_intrhead)) 855 callout_reset(&sc->sc_tmo_intrlist, 856 hz, ehci_intrlist_timeout, sc); 857 858 if (sc->sc_softwake) { 859 sc->sc_softwake = 0; 860 cv_broadcast(&sc->sc_softwake_cv); 861 } 862 } 863 864 Static void 865 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 866 { 867 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 868 uint32_t status; 869 870 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 871 872 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 873 874 if (ex->ex_type == EX_CTRL) { 875 fsqtd = ex->ex_setup; 876 lsqtd = ex->ex_status; 877 } else { 878 fsqtd = ex->ex_sqtdstart; 879 lsqtd = ex->ex_sqtdend; 880 } 881 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 882 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 883 884 /* 885 * If the last TD is still active we need to check whether there 886 * is an error somewhere in the middle, or whether there was a 887 * short packet (SPD and not ACTIVE). 888 */ 889 usb_syncmem(&lsqtd->dma, 890 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 891 sizeof(lsqtd->qtd.qtd_status), 892 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 893 status = le32toh(lsqtd->qtd.qtd_status); 894 usb_syncmem(&lsqtd->dma, 895 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 896 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 897 if (status & EHCI_QTD_ACTIVE) { 898 DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); 899 900 /* last qTD has already been checked */ 901 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 902 usb_syncmem(&sqtd->dma, 903 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 904 sizeof(sqtd->qtd.qtd_status), 905 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 906 status = le32toh(sqtd->qtd.qtd_status); 907 usb_syncmem(&sqtd->dma, 908 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 909 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 910 /* If there's an active QTD the xfer isn't done. */ 911 if (status & EHCI_QTD_ACTIVE) 912 break; 913 /* Any kind of error makes the xfer done. */ 914 if (status & EHCI_QTD_HALTED) 915 goto done; 916 /* Handle short packets */ 917 if (EHCI_QTD_GET_BYTES(status) != 0) { 918 /* 919 * If we get here for a control transfer then 920 * we need to let the hardware complete the 921 * status phase. That is, we're not done 922 * quite yet. 923 * 924 * Otherwise, we're done. 925 */ 926 if (ex->ex_type == EX_CTRL) { 927 break; 928 } 929 goto done; 930 } 931 } 932 DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, 933 0, 0); 934 #ifdef EHCI_DEBUG 935 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 936 ehci_dump_sqtds(ex->ex_sqtdstart); 937 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 938 #endif 939 return; 940 } 941 done: 942 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 943 callout_stop(&ex->ex_xfer.ux_callout); 944 ehci_idone(ex, cq); 945 } 946 947 Static void 948 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 949 { 950 ehci_soft_itd_t *itd; 951 int i; 952 953 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 954 955 KASSERT(mutex_owned(&sc->sc_lock)); 956 957 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 958 return; 959 960 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 961 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 962 963 itd = ex->ex_itdend; 964 965 /* 966 * check no active transfers in last itd, meaning we're finished 967 */ 968 969 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 970 sizeof(itd->itd.itd_ctl), 971 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 972 973 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 974 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 975 break; 976 } 977 978 if (i == EHCI_ITD_NUFRAMES) { 979 goto done; /* All 8 descriptors inactive, it's done */ 980 } 981 982 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 983 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 984 985 DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); 986 return; 987 done: 988 DPRINTF("ex %p done", ex, 0, 0, 0); 989 callout_stop(&ex->ex_xfer.ux_callout); 990 ehci_idone(ex, cq); 991 } 992 993 void 994 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 995 { 996 ehci_soft_sitd_t *sitd; 997 998 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 999 1000 KASSERT(mutex_owned(&sc->sc_lock)); 1001 1002 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1003 return; 1004 1005 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1006 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1007 1008 sitd = ex->ex_sitdend; 1009 1010 /* 1011 * check no active transfers in last sitd, meaning we're finished 1012 */ 1013 1014 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1015 sizeof(sitd->sitd.sitd_trans), 1016 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1017 1018 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1019 1020 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1021 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1022 1023 if (active) 1024 return; 1025 1026 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 1027 callout_stop(&(ex->ex_xfer.ux_callout)); 1028 ehci_idone(ex, cq); 1029 } 1030 1031 1032 Static void 1033 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1034 { 1035 struct usbd_xfer *xfer = &ex->ex_xfer; 1036 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1037 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1038 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1039 uint32_t status = 0, nstatus = 0; 1040 int actlen = 0; 1041 1042 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1043 1044 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1045 1046 DPRINTF("ex=%p", ex, 0, 0, 0); 1047 1048 if (xfer->ux_status == USBD_CANCELLED || 1049 xfer->ux_status == USBD_TIMEOUT) { 1050 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1051 return; 1052 } 1053 1054 #ifdef DIAGNOSTIC 1055 #ifdef EHCI_DEBUG 1056 if (ex->ex_isdone) { 1057 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1058 ehci_dump_exfer(ex); 1059 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1060 } 1061 #endif 1062 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1063 ex->ex_type, xfer->ux_status); 1064 ex->ex_isdone = true; 1065 #endif 1066 1067 DPRINTF("xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1068 1069 /* The transfer is done, compute actual length and status. */ 1070 if (ex->ex_type == EX_ISOC) { 1071 /* HS isoc transfer */ 1072 1073 struct ehci_soft_itd *itd; 1074 int i, nframes, len, uframes; 1075 1076 nframes = 0; 1077 1078 #ifdef EHCI_DEBUG 1079 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1080 ehci_dump_itds(ex->ex_itdstart); 1081 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1082 #endif 1083 1084 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1085 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1086 1087 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1088 usb_syncmem(&itd->dma, 1089 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1090 sizeof(itd->itd.itd_ctl), 1091 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1092 1093 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1094 /* 1095 * XXX - driver didn't fill in the frame full 1096 * of uframes. This leads to scheduling 1097 * inefficiencies, but working around 1098 * this doubles complexity of tracking 1099 * an xfer. 1100 */ 1101 if (nframes >= xfer->ux_nframes) 1102 break; 1103 1104 status = le32toh(itd->itd.itd_ctl[i]); 1105 len = EHCI_ITD_GET_LEN(status); 1106 if (EHCI_ITD_GET_STATUS(status) != 0) 1107 len = 0; /*No valid data on error*/ 1108 1109 xfer->ux_frlengths[nframes++] = len; 1110 actlen += len; 1111 } 1112 usb_syncmem(&itd->dma, 1113 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1114 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1115 1116 if (nframes >= xfer->ux_nframes) 1117 break; 1118 } 1119 1120 xfer->ux_actlen = actlen; 1121 xfer->ux_status = USBD_NORMAL_COMPLETION; 1122 goto end; 1123 } else if (ex->ex_type == EX_FS_ISOC) { 1124 /* FS isoc transfer */ 1125 struct ehci_soft_sitd *sitd; 1126 int nframes, len; 1127 1128 nframes = 0; 1129 1130 for (sitd = ex->ex_sitdstart; sitd != NULL; 1131 sitd = sitd->xfer_next) { 1132 usb_syncmem(&sitd->dma, 1133 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1134 sizeof(sitd->sitd.sitd_trans), 1135 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1136 1137 /* 1138 * XXX - driver didn't fill in the frame full 1139 * of uframes. This leads to scheduling 1140 * inefficiencies, but working around 1141 * this doubles complexity of tracking 1142 * an xfer. 1143 */ 1144 if (nframes >= xfer->ux_nframes) 1145 break; 1146 1147 status = le32toh(sitd->sitd.sitd_trans); 1148 usb_syncmem(&sitd->dma, 1149 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1150 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1151 1152 len = EHCI_SITD_GET_LEN(status); 1153 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1154 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1155 /* No valid data on error */ 1156 len = xfer->ux_frlengths[nframes]; 1157 } 1158 1159 /* 1160 * frlengths[i]: # of bytes to send 1161 * len: # of bytes host didn't send 1162 */ 1163 xfer->ux_frlengths[nframes] -= len; 1164 /* frlengths[i]: # of bytes host sent */ 1165 actlen += xfer->ux_frlengths[nframes++]; 1166 1167 if (nframes >= xfer->ux_nframes) 1168 break; 1169 } 1170 1171 xfer->ux_actlen = actlen; 1172 xfer->ux_status = USBD_NORMAL_COMPLETION; 1173 goto end; 1174 } 1175 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1176 ex->ex_type == EX_BULK); 1177 1178 /* Continue processing xfers using queue heads */ 1179 if (ex->ex_type == EX_CTRL) { 1180 fsqtd = ex->ex_setup; 1181 lsqtd = ex->ex_status; 1182 } else { 1183 fsqtd = ex->ex_sqtdstart; 1184 lsqtd = ex->ex_sqtdend; 1185 } 1186 #ifdef EHCI_DEBUG 1187 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1188 ehci_dump_sqtds(fsqtd); 1189 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1190 #endif 1191 1192 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1193 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1194 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1195 nstatus = le32toh(sqtd->qtd.qtd_status); 1196 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1197 BUS_DMASYNC_PREREAD); 1198 if (nstatus & EHCI_QTD_ACTIVE) 1199 break; 1200 1201 status = nstatus; 1202 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1203 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1204 } 1205 1206 /* 1207 * If there are left over TDs we need to update the toggle. 1208 * The default pipe doesn't need it since control transfers 1209 * start the toggle at 0 every time. 1210 * For a short transfer we need to update the toggle for the missing 1211 * packets within the qTD. 1212 */ 1213 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1214 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1215 DPRINTF("toggle update status=0x%08x nstatus=0x%08x", 1216 status, nstatus, 0, 0); 1217 #if 0 1218 ehci_dump_sqh(epipe->sqh); 1219 ehci_dump_sqtds(ex->ex_sqtdstart); 1220 #endif 1221 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1222 } 1223 1224 DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, 1225 status, 0); 1226 xfer->ux_actlen = actlen; 1227 if (status & EHCI_QTD_HALTED) { 1228 #ifdef EHCI_DEBUG 1229 DPRINTF("halted addr=%d endpt=0x%02x", 1230 xfer->ux_pipe->up_dev->ud_addr, 1231 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1232 0, 0); 1233 DPRINTF("cerr=%d pid=%d", 1234 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1235 0, 0); 1236 DPRINTF("active =%d halted=%d buferr=%d babble=%d", 1237 status & EHCI_QTD_ACTIVE ? 1 : 0, 1238 status & EHCI_QTD_HALTED ? 1 : 0, 1239 status & EHCI_QTD_BUFERR ? 1 : 0, 1240 status & EHCI_QTD_BABBLE ? 1 : 0); 1241 1242 DPRINTF("xacterr=%d missed=%d split =%d ping =%d", 1243 status & EHCI_QTD_XACTERR ? 1 : 0, 1244 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1245 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1246 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1247 1248 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1249 ehci_dump_sqh(epipe->sqh); 1250 ehci_dump_sqtds(ex->ex_sqtdstart); 1251 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1252 #endif 1253 /* low&full speed has an extra error flag */ 1254 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1255 EHCI_QH_SPEED_HIGH) 1256 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1257 else 1258 status &= EHCI_QTD_STATERRS; 1259 if (status == 0) /* no other errors means a stall */ { 1260 xfer->ux_status = USBD_STALLED; 1261 } else { 1262 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1263 } 1264 /* XXX need to reset TT on missed microframe */ 1265 if (status & EHCI_QTD_MISSEDMICRO) { 1266 printf("%s: missed microframe, TT reset not " 1267 "implemented, hub might be inoperational\n", 1268 device_xname(sc->sc_dev)); 1269 } 1270 } else { 1271 xfer->ux_status = USBD_NORMAL_COMPLETION; 1272 } 1273 1274 end: 1275 1276 ehci_del_intr_list(sc, ex); 1277 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1278 1279 DPRINTF("ex=%p done", ex, 0, 0, 0); 1280 } 1281 1282 /* 1283 * Wait here until controller claims to have an interrupt. 1284 * Then call ehci_intr and return. Use timeout to avoid waiting 1285 * too long. 1286 */ 1287 Static void 1288 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1289 { 1290 int timo; 1291 uint32_t intrs; 1292 1293 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1294 1295 xfer->ux_status = USBD_IN_PROGRESS; 1296 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1297 usb_delay_ms(&sc->sc_bus, 1); 1298 if (sc->sc_dying) 1299 break; 1300 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1301 sc->sc_eintrs; 1302 DPRINTF("0x%04x", intrs, 0, 0, 0); 1303 #ifdef EHCI_DEBUG 1304 if (ehcidebug >= 15) 1305 ehci_dump_regs(sc); 1306 #endif 1307 if (intrs) { 1308 mutex_spin_enter(&sc->sc_intr_lock); 1309 ehci_intr1(sc); 1310 mutex_spin_exit(&sc->sc_intr_lock); 1311 if (xfer->ux_status != USBD_IN_PROGRESS) 1312 return; 1313 } 1314 } 1315 1316 /* Timeout */ 1317 DPRINTF("timeout", 0, 0, 0, 0); 1318 xfer->ux_status = USBD_TIMEOUT; 1319 mutex_enter(&sc->sc_lock); 1320 usb_transfer_complete(xfer); 1321 mutex_exit(&sc->sc_lock); 1322 } 1323 1324 Static void 1325 ehci_poll(struct usbd_bus *bus) 1326 { 1327 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1328 1329 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1330 1331 #ifdef EHCI_DEBUG 1332 static int last; 1333 int new; 1334 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1335 if (new != last) { 1336 DPRINTF("intrs=0x%04x", new, 0, 0, 0); 1337 last = new; 1338 } 1339 #endif 1340 1341 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1342 mutex_spin_enter(&sc->sc_intr_lock); 1343 ehci_intr1(sc); 1344 mutex_spin_exit(&sc->sc_intr_lock); 1345 } 1346 } 1347 1348 void 1349 ehci_childdet(device_t self, device_t child) 1350 { 1351 struct ehci_softc *sc = device_private(self); 1352 1353 KASSERT(sc->sc_child == child); 1354 sc->sc_child = NULL; 1355 } 1356 1357 int 1358 ehci_detach(struct ehci_softc *sc, int flags) 1359 { 1360 int rv = 0; 1361 1362 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1363 1364 if (sc->sc_child != NULL) 1365 rv = config_detach(sc->sc_child, flags); 1366 1367 if (rv != 0) 1368 return rv; 1369 1370 callout_halt(&sc->sc_tmo_intrlist, NULL); 1371 callout_destroy(&sc->sc_tmo_intrlist); 1372 1373 /* XXX free other data structures XXX */ 1374 if (sc->sc_softitds) 1375 kmem_free(sc->sc_softitds, 1376 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1377 cv_destroy(&sc->sc_doorbell); 1378 cv_destroy(&sc->sc_softwake_cv); 1379 1380 #if 0 1381 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1382 1383 softint_disestablish(sc->sc_doorbell_si); 1384 softint_disestablish(sc->sc_pcd_si); 1385 1386 mutex_destroy(&sc->sc_lock); 1387 mutex_destroy(&sc->sc_intr_lock); 1388 #endif 1389 1390 pool_cache_destroy(sc->sc_xferpool); 1391 1392 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1393 1394 return rv; 1395 } 1396 1397 1398 int 1399 ehci_activate(device_t self, enum devact act) 1400 { 1401 struct ehci_softc *sc = device_private(self); 1402 1403 switch (act) { 1404 case DVACT_DEACTIVATE: 1405 sc->sc_dying = 1; 1406 return 0; 1407 default: 1408 return EOPNOTSUPP; 1409 } 1410 } 1411 1412 /* 1413 * Handle suspend/resume. 1414 * 1415 * We need to switch to polling mode here, because this routine is 1416 * called from an interrupt context. This is all right since we 1417 * are almost suspended anyway. 1418 * 1419 * Note that this power handler isn't to be registered directly; the 1420 * bus glue needs to call out to it. 1421 */ 1422 bool 1423 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1424 { 1425 ehci_softc_t *sc = device_private(dv); 1426 int i; 1427 uint32_t cmd, hcr; 1428 1429 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1430 1431 mutex_spin_enter(&sc->sc_intr_lock); 1432 sc->sc_bus.ub_usepolling++; 1433 mutex_spin_exit(&sc->sc_intr_lock); 1434 1435 for (i = 1; i <= sc->sc_noport; i++) { 1436 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1437 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1438 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1439 } 1440 1441 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1442 1443 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1444 EOWRITE4(sc, EHCI_USBCMD, cmd); 1445 1446 for (i = 0; i < 100; i++) { 1447 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1448 if (hcr == 0) 1449 break; 1450 1451 usb_delay_ms(&sc->sc_bus, 1); 1452 } 1453 if (hcr != 0) 1454 printf("%s: reset timeout\n", device_xname(dv)); 1455 1456 cmd &= ~EHCI_CMD_RS; 1457 EOWRITE4(sc, EHCI_USBCMD, cmd); 1458 1459 for (i = 0; i < 100; i++) { 1460 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1461 if (hcr == EHCI_STS_HCH) 1462 break; 1463 1464 usb_delay_ms(&sc->sc_bus, 1); 1465 } 1466 if (hcr != EHCI_STS_HCH) 1467 printf("%s: config timeout\n", device_xname(dv)); 1468 1469 mutex_spin_enter(&sc->sc_intr_lock); 1470 sc->sc_bus.ub_usepolling--; 1471 mutex_spin_exit(&sc->sc_intr_lock); 1472 1473 return true; 1474 } 1475 1476 bool 1477 ehci_resume(device_t dv, const pmf_qual_t *qual) 1478 { 1479 ehci_softc_t *sc = device_private(dv); 1480 int i; 1481 uint32_t cmd, hcr; 1482 1483 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1484 1485 /* restore things in case the bios sucks */ 1486 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1487 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1488 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1489 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1490 1491 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1492 1493 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1494 1495 hcr = 0; 1496 for (i = 1; i <= sc->sc_noport; i++) { 1497 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1498 if ((cmd & EHCI_PS_PO) == 0 && 1499 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1500 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1501 hcr = 1; 1502 } 1503 } 1504 1505 if (hcr) { 1506 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1507 1508 for (i = 1; i <= sc->sc_noport; i++) { 1509 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1510 if ((cmd & EHCI_PS_PO) == 0 && 1511 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1512 EOWRITE4(sc, EHCI_PORTSC(i), 1513 cmd & ~EHCI_PS_FPR); 1514 } 1515 } 1516 1517 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1518 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1519 1520 for (i = 0; i < 100; i++) { 1521 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1522 if (hcr != EHCI_STS_HCH) 1523 break; 1524 1525 usb_delay_ms(&sc->sc_bus, 1); 1526 } 1527 if (hcr == EHCI_STS_HCH) 1528 printf("%s: config timeout\n", device_xname(dv)); 1529 1530 return true; 1531 } 1532 1533 /* 1534 * Shut down the controller when the system is going down. 1535 */ 1536 bool 1537 ehci_shutdown(device_t self, int flags) 1538 { 1539 ehci_softc_t *sc = device_private(self); 1540 1541 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1542 1543 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1544 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1545 return true; 1546 } 1547 1548 Static struct usbd_xfer * 1549 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1550 { 1551 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1552 struct usbd_xfer *xfer; 1553 1554 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1555 if (xfer != NULL) { 1556 memset(xfer, 0, sizeof(struct ehci_xfer)); 1557 #ifdef DIAGNOSTIC 1558 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1559 ex->ex_isdone = true; 1560 xfer->ux_state = XFER_BUSY; 1561 #endif 1562 } 1563 return xfer; 1564 } 1565 1566 Static void 1567 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1568 { 1569 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1570 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1571 1572 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1573 xfer->ux_state); 1574 KASSERT(ex->ex_isdone); 1575 1576 #ifdef DIAGNOSTIC 1577 xfer->ux_state = XFER_FREE; 1578 #endif 1579 1580 pool_cache_put(sc->sc_xferpool, xfer); 1581 } 1582 1583 Static void 1584 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1585 { 1586 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1587 1588 *lock = &sc->sc_lock; 1589 } 1590 1591 Static void 1592 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1593 { 1594 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1595 1596 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1597 1598 DPRINTF("epipe=%p status=0x%08x", epipe, 1599 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1600 #ifdef EHCI_DEBUG 1601 if (ehcidebug) 1602 usbd_dump_pipe(pipe); 1603 #endif 1604 epipe->nexttoggle = 0; 1605 } 1606 1607 Static void 1608 ehci_noop(struct usbd_pipe *pipe) 1609 { 1610 } 1611 1612 #ifdef EHCI_DEBUG 1613 /* 1614 * Unused function - this is meant to be called from a kernel 1615 * debugger. 1616 */ 1617 void 1618 ehci_dump(void) 1619 { 1620 ehci_softc_t *sc = theehci; 1621 int i; 1622 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1623 EOREAD4(sc, EHCI_USBCMD), 1624 EOREAD4(sc, EHCI_USBSTS), 1625 EOREAD4(sc, EHCI_USBINTR)); 1626 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1627 EOREAD4(sc, EHCI_FRINDEX), 1628 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1629 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1630 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1631 for (i = 1; i <= sc->sc_noport; i++) 1632 printf("port %d status=0x%08x\n", i, 1633 EOREAD4(sc, EHCI_PORTSC(i))); 1634 } 1635 1636 Static void 1637 ehci_dump_regs(ehci_softc_t *sc) 1638 { 1639 int i; 1640 1641 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1642 1643 DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1644 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1645 EOREAD4(sc, EHCI_USBINTR), 0); 1646 DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1647 "async = 0x%08x", 1648 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1649 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1650 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1651 for (i = 1; i <= sc->sc_noport; i += 2) { 1652 if (i == sc->sc_noport) { 1653 DPRINTF("port %d status = 0x%08x", i, 1654 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1655 } else { 1656 DPRINTF( 1657 "port %d status = 0x%08x port %d status = 0x%08x", 1658 i, EOREAD4(sc, EHCI_PORTSC(i)), 1659 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1660 } 1661 } 1662 } 1663 1664 #define ehci_dump_link(link, type) do { \ 1665 DPRINTF(" link 0x%08x (T = %d):", \ 1666 link, \ 1667 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1668 if (type) { \ 1669 DPRINTF( \ 1670 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1671 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1672 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1673 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1674 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1675 } \ 1676 } while(0) 1677 1678 Static void 1679 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1680 { 1681 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1682 int i; 1683 uint32_t stop = 0; 1684 1685 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1686 ehci_dump_sqtd(sqtd); 1687 usb_syncmem(&sqtd->dma, 1688 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1689 sizeof(sqtd->qtd), 1690 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1691 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1692 usb_syncmem(&sqtd->dma, 1693 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1694 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1695 } 1696 if (!stop) 1697 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1698 } 1699 1700 Static void 1701 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1702 { 1703 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1704 1705 usb_syncmem(&sqtd->dma, sqtd->offs, 1706 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1707 1708 DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1709 ehci_dump_qtd(&sqtd->qtd); 1710 1711 usb_syncmem(&sqtd->dma, sqtd->offs, 1712 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1713 } 1714 1715 Static void 1716 ehci_dump_qtd(ehci_qtd_t *qtd) 1717 { 1718 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1719 uint32_t s = le32toh(qtd->qtd_status); 1720 1721 DPRINTFN(10, 1722 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1723 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1724 DPRINTFN(10, 1725 " toggle = %d ioc = %d bytes = %#x " 1726 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1727 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1728 DPRINTFN(10, 1729 " cerr = %d pid = %d stat = %x", 1730 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1731 0); 1732 DPRINTFN(10, 1733 "active =%d halted=%d buferr=%d babble=%d", 1734 s & EHCI_QTD_ACTIVE ? 1 : 0, 1735 s & EHCI_QTD_HALTED ? 1 : 0, 1736 s & EHCI_QTD_BUFERR ? 1 : 0, 1737 s & EHCI_QTD_BABBLE ? 1 : 0); 1738 DPRINTFN(10, 1739 "xacterr=%d missed=%d split =%d ping =%d", 1740 s & EHCI_QTD_XACTERR ? 1 : 0, 1741 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1742 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1743 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1744 DPRINTFN(10, 1745 "buffer[0] = %#x buffer[1] = %#x " 1746 "buffer[2] = %#x buffer[3] = %#x", 1747 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1748 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1749 DPRINTFN(10, 1750 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1751 } 1752 1753 Static void 1754 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1755 { 1756 ehci_qh_t *qh = &sqh->qh; 1757 ehci_link_t link; 1758 uint32_t endp, endphub; 1759 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1760 1761 usb_syncmem(&sqh->dma, sqh->offs, 1762 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1763 1764 DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1765 link = le32toh(qh->qh_link); 1766 ehci_dump_link(link, true); 1767 1768 endp = le32toh(qh->qh_endp); 1769 DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); 1770 DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", 1771 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1772 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1773 DPRINTFN(10, " dtc = %d hrecl = %d", 1774 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1775 DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", 1776 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1777 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1778 1779 endphub = le32toh(qh->qh_endphub); 1780 DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); 1781 DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", 1782 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1783 DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", 1784 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1785 EHCI_QH_GET_MULT(endphub), 0); 1786 1787 link = le32toh(qh->qh_curqtd); 1788 ehci_dump_link(link, false); 1789 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1790 ehci_dump_qtd(&qh->qh_qtd); 1791 1792 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1793 BUS_DMASYNC_PREREAD); 1794 } 1795 1796 Static void 1797 ehci_dump_itds(ehci_soft_itd_t *itd) 1798 { 1799 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1800 int i; 1801 uint32_t stop = 0; 1802 1803 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1804 ehci_dump_itd(itd); 1805 usb_syncmem(&itd->dma, 1806 itd->offs + offsetof(ehci_itd_t, itd_next), 1807 sizeof(itd->itd), 1808 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1809 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1810 usb_syncmem(&itd->dma, 1811 itd->offs + offsetof(ehci_itd_t, itd_next), 1812 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1813 } 1814 if (!stop) 1815 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1816 } 1817 1818 Static void 1819 ehci_dump_itd(struct ehci_soft_itd *itd) 1820 { 1821 ehci_isoc_trans_t t; 1822 ehci_isoc_bufr_ptr_t b, b2, b3; 1823 int i; 1824 1825 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1826 1827 DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); 1828 1829 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1830 t = le32toh(itd->itd.itd_ctl[i]); 1831 DPRINTF("ITDctl %d: stat = %x len = %x", 1832 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1833 DPRINTF(" ioc = %x pg = %x offs = %x", 1834 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1835 EHCI_ITD_GET_OFFS(t), 0); 1836 } 1837 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1838 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1839 DPRINTF(" %x", 1840 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1841 1842 b = le32toh(itd->itd.itd_bufr[0]); 1843 b2 = le32toh(itd->itd.itd_bufr[1]); 1844 b3 = le32toh(itd->itd.itd_bufr[2]); 1845 DPRINTF(" ep = %x daddr = %x dir = %d", 1846 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1847 DPRINTF(" maxpkt = %x multi = %x", 1848 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1849 } 1850 1851 Static void 1852 ehci_dump_sitd(struct ehci_soft_itd *itd) 1853 { 1854 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1855 1856 DPRINTF("SITD %p next = %p prev = %p", 1857 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1858 DPRINTF(" xfernext=%p physaddr=%X slot=%d", 1859 itd->xfer_next, itd->physaddr, itd->slot, 0); 1860 } 1861 1862 Static void 1863 ehci_dump_exfer(struct ehci_xfer *ex) 1864 { 1865 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1866 1867 DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, 1868 ex->ex_isdone, 0); 1869 1870 switch (ex->ex_type) { 1871 case EX_CTRL: 1872 DPRINTF(" setup = %p data = %p status = %p", 1873 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1874 break; 1875 case EX_BULK: 1876 case EX_INTR: 1877 DPRINTF(" qtdstart = %p qtdend = %p", 1878 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1879 break; 1880 case EX_ISOC: 1881 DPRINTF(" itdstart = %p itdend = %p", 1882 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1883 break; 1884 case EX_FS_ISOC: 1885 DPRINTF(" sitdstart = %p sitdend = %p", 1886 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1887 break; 1888 default: 1889 DPRINTF(" unknown type", 0, 0, 0, 0); 1890 } 1891 } 1892 #endif 1893 1894 Static usbd_status 1895 ehci_open(struct usbd_pipe *pipe) 1896 { 1897 struct usbd_device *dev = pipe->up_dev; 1898 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1899 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1900 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1901 uint8_t addr = dev->ud_addr; 1902 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1903 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1904 ehci_soft_qh_t *sqh; 1905 usbd_status err; 1906 int ival, speed, naks; 1907 int hshubaddr, hshubport; 1908 1909 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1910 1911 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1912 ed->bEndpointAddress, rhaddr); 1913 1914 if (dev->ud_myhsport) { 1915 /* 1916 * When directly attached FS/LS device while doing embedded 1917 * transaction translations and we are the hub, set the hub 1918 * address to 0 (us). 1919 */ 1920 if (!(sc->sc_flags & EHCIF_ETTF) 1921 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1922 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1923 } else { 1924 hshubaddr = 0; 1925 } 1926 hshubport = dev->ud_myhsport->up_portno; 1927 } else { 1928 hshubaddr = 0; 1929 hshubport = 0; 1930 } 1931 1932 if (sc->sc_dying) 1933 return USBD_IOERROR; 1934 1935 /* toggle state needed for bulk endpoints */ 1936 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1937 1938 if (addr == rhaddr) { 1939 switch (ed->bEndpointAddress) { 1940 case USB_CONTROL_ENDPOINT: 1941 pipe->up_methods = &roothub_ctrl_methods; 1942 break; 1943 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1944 pipe->up_methods = &ehci_root_intr_methods; 1945 break; 1946 default: 1947 DPRINTF("bad bEndpointAddress 0x%02x", 1948 ed->bEndpointAddress, 0, 0, 0); 1949 return USBD_INVAL; 1950 } 1951 return USBD_NORMAL_COMPLETION; 1952 } 1953 1954 /* XXX All this stuff is only valid for async. */ 1955 switch (dev->ud_speed) { 1956 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1957 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1958 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1959 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1960 } 1961 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1962 DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, 1963 0); 1964 return USBD_INVAL; 1965 } 1966 1967 /* 1968 * For interrupt transfer, nak throttling must be disabled, but for 1969 * the other transfer type, nak throttling should be enabled from the 1970 * viewpoint that avoids the memory thrashing. 1971 */ 1972 naks = (xfertype == UE_INTERRUPT) ? 0 1973 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1974 1975 /* Allocate sqh for everything, save isoc xfers */ 1976 if (xfertype != UE_ISOCHRONOUS) { 1977 sqh = ehci_alloc_sqh(sc); 1978 if (sqh == NULL) 1979 return USBD_NOMEM; 1980 /* qh_link filled when the QH is added */ 1981 sqh->qh.qh_endp = htole32( 1982 EHCI_QH_SET_ADDR(addr) | 1983 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1984 EHCI_QH_SET_EPS(speed) | 1985 EHCI_QH_DTC | 1986 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1987 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1988 EHCI_QH_CTL : 0) | 1989 EHCI_QH_SET_NRL(naks) 1990 ); 1991 sqh->qh.qh_endphub = htole32( 1992 EHCI_QH_SET_MULT(1) | 1993 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1994 ); 1995 if (speed != EHCI_QH_SPEED_HIGH) 1996 sqh->qh.qh_endphub |= htole32( 1997 EHCI_QH_SET_PORT(hshubport) | 1998 EHCI_QH_SET_HUBA(hshubaddr) | 1999 EHCI_QH_SET_CMASK(0x08) /* XXX */ 2000 ); 2001 sqh->qh.qh_curqtd = EHCI_NULL; 2002 /* Fill the overlay qTD */ 2003 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2004 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2005 sqh->qh.qh_qtd.qtd_status = htole32(0); 2006 2007 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2008 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2009 epipe->sqh = sqh; 2010 } else { 2011 sqh = NULL; 2012 } /*xfertype == UE_ISOC*/ 2013 2014 switch (xfertype) { 2015 case UE_CONTROL: 2016 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2017 0, &epipe->ctrl.reqdma); 2018 #ifdef EHCI_DEBUG 2019 if (err) 2020 printf("ehci_open: usb_allocmem()=%d\n", err); 2021 #endif 2022 if (err) 2023 goto bad; 2024 pipe->up_methods = &ehci_device_ctrl_methods; 2025 mutex_enter(&sc->sc_lock); 2026 ehci_add_qh(sc, sqh, sc->sc_async_head); 2027 mutex_exit(&sc->sc_lock); 2028 break; 2029 case UE_BULK: 2030 pipe->up_methods = &ehci_device_bulk_methods; 2031 mutex_enter(&sc->sc_lock); 2032 ehci_add_qh(sc, sqh, sc->sc_async_head); 2033 mutex_exit(&sc->sc_lock); 2034 break; 2035 case UE_INTERRUPT: 2036 pipe->up_methods = &ehci_device_intr_methods; 2037 ival = pipe->up_interval; 2038 if (ival == USBD_DEFAULT_INTERVAL) { 2039 if (speed == EHCI_QH_SPEED_HIGH) { 2040 if (ed->bInterval > 16) { 2041 /* 2042 * illegal with high-speed, but there 2043 * were documentation bugs in the spec, 2044 * so be generous 2045 */ 2046 ival = 256; 2047 } else 2048 ival = (1 << (ed->bInterval - 1)) / 8; 2049 } else 2050 ival = ed->bInterval; 2051 } 2052 err = ehci_device_setintr(sc, sqh, ival); 2053 if (err) 2054 goto bad; 2055 break; 2056 case UE_ISOCHRONOUS: 2057 pipe->up_serialise = false; 2058 if (speed == EHCI_QH_SPEED_HIGH) 2059 pipe->up_methods = &ehci_device_isoc_methods; 2060 else 2061 pipe->up_methods = &ehci_device_fs_isoc_methods; 2062 if (ed->bInterval == 0 || ed->bInterval > 16) { 2063 printf("ehci: opening pipe with invalid bInterval\n"); 2064 err = USBD_INVAL; 2065 goto bad; 2066 } 2067 if (UGETW(ed->wMaxPacketSize) == 0) { 2068 printf("ehci: zero length endpoint open request\n"); 2069 err = USBD_INVAL; 2070 goto bad; 2071 } 2072 epipe->isoc.next_frame = 0; 2073 epipe->isoc.cur_xfers = 0; 2074 break; 2075 default: 2076 DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); 2077 err = USBD_INVAL; 2078 goto bad; 2079 } 2080 return USBD_NORMAL_COMPLETION; 2081 2082 bad: 2083 if (sqh != NULL) { 2084 mutex_enter(&sc->sc_lock); 2085 ehci_free_sqh(sc, sqh); 2086 mutex_exit(&sc->sc_lock); 2087 } 2088 return err; 2089 } 2090 2091 /* 2092 * Add an ED to the schedule. Called with USB lock held. 2093 */ 2094 Static void 2095 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2096 { 2097 2098 KASSERT(mutex_owned(&sc->sc_lock)); 2099 2100 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2101 2102 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2103 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2104 2105 sqh->next = head->next; 2106 sqh->qh.qh_link = head->qh.qh_link; 2107 2108 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2109 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2110 2111 head->next = sqh; 2112 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2113 2114 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2115 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2116 2117 #ifdef EHCI_DEBUG 2118 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2119 ehci_dump_sqh(sqh); 2120 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2121 #endif 2122 } 2123 2124 /* 2125 * Remove an ED from the schedule. Called with USB lock held. 2126 */ 2127 Static void 2128 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2129 { 2130 ehci_soft_qh_t *p; 2131 2132 KASSERT(mutex_owned(&sc->sc_lock)); 2133 2134 /* XXX */ 2135 for (p = head; p != NULL && p->next != sqh; p = p->next) 2136 ; 2137 if (p == NULL) 2138 panic("ehci_rem_qh: ED not found"); 2139 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2140 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2141 p->next = sqh->next; 2142 p->qh.qh_link = sqh->qh.qh_link; 2143 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2144 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2145 2146 ehci_sync_hc(sc); 2147 } 2148 2149 Static void 2150 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2151 { 2152 int i; 2153 uint32_t status; 2154 2155 /* Save toggle bit and ping status. */ 2156 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2157 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2158 status = sqh->qh.qh_qtd.qtd_status & 2159 htole32(EHCI_QTD_TOGGLE_MASK | 2160 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2161 /* Set HALTED to make hw leave it alone. */ 2162 sqh->qh.qh_qtd.qtd_status = 2163 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2164 usb_syncmem(&sqh->dma, 2165 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2166 sizeof(sqh->qh.qh_qtd.qtd_status), 2167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2168 sqh->qh.qh_curqtd = 0; 2169 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2170 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2171 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2172 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2173 sqh->sqtd = sqtd; 2174 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2175 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2176 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2177 sqh->qh.qh_qtd.qtd_status = status; 2178 usb_syncmem(&sqh->dma, 2179 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2180 sizeof(sqh->qh.qh_qtd.qtd_status), 2181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2182 } 2183 2184 /* 2185 * Ensure that the HC has released all references to the QH. We do this 2186 * by asking for a Async Advance Doorbell interrupt and then we wait for 2187 * the interrupt. 2188 * To make this easier we first obtain exclusive use of the doorbell. 2189 */ 2190 Static void 2191 ehci_sync_hc(ehci_softc_t *sc) 2192 { 2193 int error __diagused; 2194 2195 KASSERT(mutex_owned(&sc->sc_lock)); 2196 2197 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2198 2199 if (sc->sc_dying) { 2200 DPRINTF("dying", 0, 0, 0, 0); 2201 return; 2202 } 2203 /* ask for doorbell */ 2204 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2205 DPRINTF("cmd = 0x%08x sts = 0x%08x", 2206 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2207 2208 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2209 2210 DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", 2211 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2212 #ifdef DIAGNOSTIC 2213 if (error) 2214 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2215 #endif 2216 } 2217 2218 Static void 2219 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2220 { 2221 2222 KASSERT(mutex_owned(&sc->sc_lock)); 2223 2224 for (; itd != NULL; itd = itd->xfer_next) { 2225 struct ehci_soft_itd *prev = itd->frame_list.prev; 2226 2227 /* Unlink itd from hardware chain, or frame array */ 2228 if (prev == NULL) { /* We're at the table head */ 2229 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2230 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2231 usb_syncmem(&sc->sc_fldma, 2232 sizeof(ehci_link_t) * itd->slot, 2233 sizeof(ehci_link_t), 2234 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2235 2236 if (itd->frame_list.next != NULL) 2237 itd->frame_list.next->frame_list.prev = NULL; 2238 } else { 2239 /* XXX this part is untested... */ 2240 prev->itd.itd_next = itd->itd.itd_next; 2241 usb_syncmem(&itd->dma, 2242 itd->offs + offsetof(ehci_itd_t, itd_next), 2243 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2244 2245 prev->frame_list.next = itd->frame_list.next; 2246 if (itd->frame_list.next != NULL) 2247 itd->frame_list.next->frame_list.prev = prev; 2248 } 2249 } 2250 } 2251 2252 Static void 2253 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2254 { 2255 struct ehci_soft_itd *next; 2256 2257 mutex_enter(&sc->sc_lock); 2258 next = NULL; 2259 for (; itd != NULL; itd = next) { 2260 next = itd->xfer_next; 2261 ehci_free_itd_locked(sc, itd); 2262 } 2263 mutex_exit(&sc->sc_lock); 2264 } 2265 2266 Static void 2267 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2268 { 2269 2270 KASSERT(mutex_owned(&sc->sc_lock)); 2271 2272 for (; sitd != NULL; sitd = sitd->xfer_next) { 2273 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2274 2275 /* Unlink sitd from hardware chain, or frame array */ 2276 if (prev == NULL) { /* We're at the table head */ 2277 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2278 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2279 usb_syncmem(&sc->sc_fldma, 2280 sizeof(ehci_link_t) * sitd->slot, 2281 sizeof(ehci_link_t), 2282 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2283 2284 if (sitd->frame_list.next != NULL) 2285 sitd->frame_list.next->frame_list.prev = NULL; 2286 } else { 2287 /* XXX this part is untested... */ 2288 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2289 usb_syncmem(&sitd->dma, 2290 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2291 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2292 2293 prev->frame_list.next = sitd->frame_list.next; 2294 if (sitd->frame_list.next != NULL) 2295 sitd->frame_list.next->frame_list.prev = prev; 2296 } 2297 } 2298 } 2299 2300 Static void 2301 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2302 { 2303 2304 mutex_enter(&sc->sc_lock); 2305 struct ehci_soft_sitd *next = NULL; 2306 for (; sitd != NULL; sitd = next) { 2307 next = sitd->xfer_next; 2308 ehci_free_sitd_locked(sc, sitd); 2309 } 2310 mutex_exit(&sc->sc_lock); 2311 } 2312 2313 /***********/ 2314 2315 Static int 2316 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2317 void *buf, int buflen) 2318 { 2319 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2320 usb_hub_descriptor_t hubd; 2321 usb_port_status_t ps; 2322 uint16_t len, value, index; 2323 int l, totlen = 0; 2324 int port, i; 2325 uint32_t v; 2326 2327 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2328 2329 if (sc->sc_dying) 2330 return -1; 2331 2332 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, 2333 0, 0); 2334 2335 len = UGETW(req->wLength); 2336 value = UGETW(req->wValue); 2337 index = UGETW(req->wIndex); 2338 2339 #define C(x,y) ((x) | ((y) << 8)) 2340 switch (C(req->bRequest, req->bmRequestType)) { 2341 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2342 if (len == 0) 2343 break; 2344 switch (value) { 2345 case C(0, UDESC_DEVICE): { 2346 usb_device_descriptor_t devd; 2347 totlen = min(buflen, sizeof(devd)); 2348 memcpy(&devd, buf, totlen); 2349 USETW(devd.idVendor, sc->sc_id_vendor); 2350 memcpy(buf, &devd, totlen); 2351 break; 2352 2353 } 2354 #define sd ((usb_string_descriptor_t *)buf) 2355 case C(1, UDESC_STRING): 2356 /* Vendor */ 2357 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2358 break; 2359 case C(2, UDESC_STRING): 2360 /* Product */ 2361 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2362 break; 2363 #undef sd 2364 default: 2365 /* default from usbroothub */ 2366 return buflen; 2367 } 2368 break; 2369 2370 /* Hub requests */ 2371 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2372 break; 2373 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2374 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 2375 value, 0, 0); 2376 if (index < 1 || index > sc->sc_noport) { 2377 return -1; 2378 } 2379 port = EHCI_PORTSC(index); 2380 v = EOREAD4(sc, port); 2381 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2382 v &= ~EHCI_PS_CLEAR; 2383 switch (value) { 2384 case UHF_PORT_ENABLE: 2385 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2386 break; 2387 case UHF_PORT_SUSPEND: 2388 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2389 break; 2390 v &= ~EHCI_PS_SUSP; 2391 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2392 /* see USB2 spec ch. 7.1.7.7 */ 2393 usb_delay_ms(&sc->sc_bus, 20); 2394 EOWRITE4(sc, port, v); 2395 usb_delay_ms(&sc->sc_bus, 2); 2396 #ifdef DEBUG 2397 v = EOREAD4(sc, port); 2398 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2399 printf("ehci: resume failed: %x\n", v); 2400 #endif 2401 break; 2402 case UHF_PORT_POWER: 2403 if (sc->sc_hasppc) 2404 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2405 break; 2406 case UHF_PORT_TEST: 2407 DPRINTF("clear port test %d", index, 0, 0, 0); 2408 break; 2409 case UHF_PORT_INDICATOR: 2410 DPRINTF("clear port ind %d", index, 0, 0, 0); 2411 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2412 break; 2413 case UHF_C_PORT_CONNECTION: 2414 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2415 break; 2416 case UHF_C_PORT_ENABLE: 2417 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2418 break; 2419 case UHF_C_PORT_SUSPEND: 2420 /* how? */ 2421 break; 2422 case UHF_C_PORT_OVER_CURRENT: 2423 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2424 break; 2425 case UHF_C_PORT_RESET: 2426 sc->sc_isreset[index] = 0; 2427 break; 2428 default: 2429 return -1; 2430 } 2431 #if 0 2432 switch(value) { 2433 case UHF_C_PORT_CONNECTION: 2434 case UHF_C_PORT_ENABLE: 2435 case UHF_C_PORT_SUSPEND: 2436 case UHF_C_PORT_OVER_CURRENT: 2437 case UHF_C_PORT_RESET: 2438 default: 2439 break; 2440 } 2441 #endif 2442 break; 2443 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2444 if (len == 0) 2445 break; 2446 if ((value & 0xff) != 0) { 2447 return -1; 2448 } 2449 totlen = min(buflen, sizeof(hubd)); 2450 memcpy(&hubd, buf, totlen); 2451 hubd.bNbrPorts = sc->sc_noport; 2452 v = EOREAD4(sc, EHCI_HCSPARAMS); 2453 USETW(hubd.wHubCharacteristics, 2454 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2455 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2456 ? UHD_PORT_IND : 0); 2457 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2458 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2459 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2460 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2461 totlen = min(totlen, hubd.bDescLength); 2462 memcpy(buf, &hubd, totlen); 2463 break; 2464 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2465 if (len != 4) { 2466 return -1; 2467 } 2468 memset(buf, 0, len); /* ? XXX */ 2469 totlen = len; 2470 break; 2471 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2472 DPRINTF("get port status i=%d", index, 0, 0, 0); 2473 if (index < 1 || index > sc->sc_noport) { 2474 return -1; 2475 } 2476 if (len != 4) { 2477 return -1; 2478 } 2479 v = EOREAD4(sc, EHCI_PORTSC(index)); 2480 DPRINTF("port status=0x%04x", v, 0, 0, 0); 2481 2482 i = UPS_HIGH_SPEED; 2483 if (sc->sc_flags & EHCIF_ETTF) { 2484 /* 2485 * If we are doing embedded transaction translation, 2486 * then directly attached LS/FS devices are reset by 2487 * the EHCI controller itself. PSPD is encoded 2488 * the same way as in USBSTATUS. 2489 */ 2490 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2491 } 2492 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2493 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2494 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2495 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2496 if (v & EHCI_PS_PR) i |= UPS_RESET; 2497 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2498 if (sc->sc_vendor_port_status) 2499 i = sc->sc_vendor_port_status(sc, v, i); 2500 USETW(ps.wPortStatus, i); 2501 i = 0; 2502 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2503 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2504 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2505 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2506 USETW(ps.wPortChange, i); 2507 totlen = min(len, sizeof(ps)); 2508 memcpy(buf, &ps, totlen); 2509 break; 2510 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2511 return -1; 2512 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2513 break; 2514 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2515 if (index < 1 || index > sc->sc_noport) { 2516 return -1; 2517 } 2518 port = EHCI_PORTSC(index); 2519 v = EOREAD4(sc, port); 2520 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2521 v &= ~EHCI_PS_CLEAR; 2522 switch(value) { 2523 case UHF_PORT_ENABLE: 2524 EOWRITE4(sc, port, v | EHCI_PS_PE); 2525 break; 2526 case UHF_PORT_SUSPEND: 2527 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2528 break; 2529 case UHF_PORT_RESET: 2530 DPRINTF("reset port %d", index, 0, 0, 0); 2531 if (EHCI_PS_IS_LOWSPEED(v) 2532 && sc->sc_ncomp > 0 2533 && !(sc->sc_flags & EHCIF_ETTF)) { 2534 /* 2535 * Low speed device on non-ETTF controller or 2536 * unaccompanied controller, give up ownership. 2537 */ 2538 ehci_disown(sc, index, 1); 2539 break; 2540 } 2541 /* Start reset sequence. */ 2542 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2543 EOWRITE4(sc, port, v | EHCI_PS_PR); 2544 /* Wait for reset to complete. */ 2545 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2546 if (sc->sc_dying) { 2547 return -1; 2548 } 2549 /* 2550 * An embedded transaction translator will automatically 2551 * terminate the reset sequence so there's no need to 2552 * it. 2553 */ 2554 v = EOREAD4(sc, port); 2555 if (v & EHCI_PS_PR) { 2556 /* Terminate reset sequence. */ 2557 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2558 /* Wait for HC to complete reset. */ 2559 usb_delay_ms(&sc->sc_bus, 2560 EHCI_PORT_RESET_COMPLETE); 2561 if (sc->sc_dying) { 2562 return -1; 2563 } 2564 } 2565 2566 v = EOREAD4(sc, port); 2567 DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); 2568 if (v & EHCI_PS_PR) { 2569 printf("%s: port reset timeout\n", 2570 device_xname(sc->sc_dev)); 2571 return USBD_TIMEOUT; 2572 } 2573 if (!(v & EHCI_PS_PE)) { 2574 /* Not a high speed device, give up ownership.*/ 2575 ehci_disown(sc, index, 0); 2576 break; 2577 } 2578 sc->sc_isreset[index] = 1; 2579 DPRINTF("ehci port %d reset, status = 0x%08x", index, 2580 v, 0, 0); 2581 break; 2582 case UHF_PORT_POWER: 2583 DPRINTF("set port power %d (has PPC = %d)", index, 2584 sc->sc_hasppc, 0, 0); 2585 if (sc->sc_hasppc) 2586 EOWRITE4(sc, port, v | EHCI_PS_PP); 2587 break; 2588 case UHF_PORT_TEST: 2589 DPRINTF("set port test %d", index, 0, 0, 0); 2590 break; 2591 case UHF_PORT_INDICATOR: 2592 DPRINTF("set port ind %d", index, 0, 0, 0); 2593 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2594 break; 2595 default: 2596 return -1; 2597 } 2598 break; 2599 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2600 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2601 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2602 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2603 break; 2604 default: 2605 /* default from usbroothub */ 2606 DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); 2607 2608 return buflen; 2609 } 2610 2611 DPRINTF("returning %d", totlen, 0, 0, 0); 2612 2613 return totlen; 2614 } 2615 2616 Static void 2617 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2618 { 2619 int port; 2620 uint32_t v; 2621 2622 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2623 2624 DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); 2625 #ifdef DIAGNOSTIC 2626 if (sc->sc_npcomp != 0) { 2627 int i = (index-1) / sc->sc_npcomp; 2628 if (i >= sc->sc_ncomp) 2629 printf("%s: strange port\n", 2630 device_xname(sc->sc_dev)); 2631 else 2632 printf("%s: handing over %s speed device on " 2633 "port %d to %s\n", 2634 device_xname(sc->sc_dev), 2635 lowspeed ? "low" : "full", 2636 index, device_xname(sc->sc_comps[i])); 2637 } else { 2638 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2639 } 2640 #endif 2641 port = EHCI_PORTSC(index); 2642 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2643 EOWRITE4(sc, port, v | EHCI_PS_PO); 2644 } 2645 2646 Static usbd_status 2647 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2648 { 2649 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2650 usbd_status err; 2651 2652 /* Insert last in queue. */ 2653 mutex_enter(&sc->sc_lock); 2654 err = usb_insert_transfer(xfer); 2655 mutex_exit(&sc->sc_lock); 2656 if (err) 2657 return err; 2658 2659 /* Pipe isn't running, start first */ 2660 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2661 } 2662 2663 Static usbd_status 2664 ehci_root_intr_start(struct usbd_xfer *xfer) 2665 { 2666 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2667 2668 if (sc->sc_dying) 2669 return USBD_IOERROR; 2670 2671 mutex_enter(&sc->sc_lock); 2672 sc->sc_intrxfer = xfer; 2673 mutex_exit(&sc->sc_lock); 2674 2675 return USBD_IN_PROGRESS; 2676 } 2677 2678 /* Abort a root interrupt request. */ 2679 Static void 2680 ehci_root_intr_abort(struct usbd_xfer *xfer) 2681 { 2682 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2683 2684 KASSERT(mutex_owned(&sc->sc_lock)); 2685 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2686 2687 sc->sc_intrxfer = NULL; 2688 2689 xfer->ux_status = USBD_CANCELLED; 2690 usb_transfer_complete(xfer); 2691 } 2692 2693 /* Close the root pipe. */ 2694 Static void 2695 ehci_root_intr_close(struct usbd_pipe *pipe) 2696 { 2697 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2698 2699 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2700 2701 KASSERT(mutex_owned(&sc->sc_lock)); 2702 2703 sc->sc_intrxfer = NULL; 2704 } 2705 2706 Static void 2707 ehci_root_intr_done(struct usbd_xfer *xfer) 2708 { 2709 } 2710 2711 /************************/ 2712 2713 Static ehci_soft_qh_t * 2714 ehci_alloc_sqh(ehci_softc_t *sc) 2715 { 2716 ehci_soft_qh_t *sqh; 2717 usbd_status err; 2718 int i, offs; 2719 usb_dma_t dma; 2720 2721 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2722 2723 mutex_enter(&sc->sc_lock); 2724 if (sc->sc_freeqhs == NULL) { 2725 DPRINTF("allocating chunk", 0, 0, 0, 0); 2726 mutex_exit(&sc->sc_lock); 2727 2728 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2729 EHCI_PAGE_SIZE, &dma); 2730 #ifdef EHCI_DEBUG 2731 if (err) 2732 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2733 #endif 2734 if (err) 2735 return NULL; 2736 2737 mutex_enter(&sc->sc_lock); 2738 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2739 offs = i * EHCI_SQH_SIZE; 2740 sqh = KERNADDR(&dma, offs); 2741 sqh->physaddr = DMAADDR(&dma, offs); 2742 sqh->dma = dma; 2743 sqh->offs = offs; 2744 sqh->next = sc->sc_freeqhs; 2745 sc->sc_freeqhs = sqh; 2746 } 2747 } 2748 sqh = sc->sc_freeqhs; 2749 sc->sc_freeqhs = sqh->next; 2750 mutex_exit(&sc->sc_lock); 2751 2752 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2753 sqh->next = NULL; 2754 return sqh; 2755 } 2756 2757 Static void 2758 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2759 { 2760 KASSERT(mutex_owned(&sc->sc_lock)); 2761 2762 sqh->next = sc->sc_freeqhs; 2763 sc->sc_freeqhs = sqh; 2764 } 2765 2766 Static ehci_soft_qtd_t * 2767 ehci_alloc_sqtd(ehci_softc_t *sc) 2768 { 2769 ehci_soft_qtd_t *sqtd = NULL; 2770 usbd_status err; 2771 int i, offs; 2772 usb_dma_t dma; 2773 2774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2775 2776 mutex_enter(&sc->sc_lock); 2777 if (sc->sc_freeqtds == NULL) { 2778 DPRINTF("allocating chunk", 0, 0, 0, 0); 2779 mutex_exit(&sc->sc_lock); 2780 2781 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2782 EHCI_PAGE_SIZE, &dma); 2783 #ifdef EHCI_DEBUG 2784 if (err) 2785 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2786 #endif 2787 if (err) 2788 goto done; 2789 2790 mutex_enter(&sc->sc_lock); 2791 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2792 offs = i * EHCI_SQTD_SIZE; 2793 sqtd = KERNADDR(&dma, offs); 2794 sqtd->physaddr = DMAADDR(&dma, offs); 2795 sqtd->dma = dma; 2796 sqtd->offs = offs; 2797 2798 sqtd->nextqtd = sc->sc_freeqtds; 2799 sc->sc_freeqtds = sqtd; 2800 } 2801 } 2802 2803 sqtd = sc->sc_freeqtds; 2804 sc->sc_freeqtds = sqtd->nextqtd; 2805 mutex_exit(&sc->sc_lock); 2806 2807 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2808 sqtd->nextqtd = NULL; 2809 sqtd->xfer = NULL; 2810 2811 done: 2812 return sqtd; 2813 } 2814 2815 Static void 2816 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2817 { 2818 2819 mutex_enter(&sc->sc_lock); 2820 sqtd->nextqtd = sc->sc_freeqtds; 2821 sc->sc_freeqtds = sqtd; 2822 mutex_exit(&sc->sc_lock); 2823 } 2824 2825 Static int 2826 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2827 int alen, int rd, ehci_soft_qtd_t **sp) 2828 { 2829 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2830 uint16_t flags = xfer->ux_flags; 2831 2832 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2833 2834 ASSERT_SLEEPABLE(); 2835 KASSERT(sp); 2836 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2837 2838 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2839 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2840 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2841 KM_SLEEP); 2842 exfer->ex_nsqtd = nsqtd; 2843 2844 DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); 2845 2846 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2847 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2848 if (cur == NULL) 2849 goto nomem; 2850 exfer->ex_sqtds[j++] = cur; 2851 2852 cur->xfer = xfer; 2853 cur->len = 0; 2854 2855 } 2856 2857 *sp = exfer->ex_sqtds[0]; 2858 DPRINTF("return sqtd=%p", *sp, 0, 0, 0); 2859 2860 return 0; 2861 2862 nomem: 2863 ehci_free_sqtds(sc, exfer); 2864 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2865 DPRINTF("no memory", 0, 0, 0, 0); 2866 return ENOMEM; 2867 } 2868 2869 Static void 2870 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2871 { 2872 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2873 DPRINTF("exfer=%p", exfer, 0, 0, 0); 2874 2875 mutex_enter(&sc->sc_lock); 2876 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2877 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2878 2879 if (sqtd == NULL) 2880 break; 2881 2882 sqtd->nextqtd = sc->sc_freeqtds; 2883 sc->sc_freeqtds = sqtd; 2884 } 2885 mutex_exit(&sc->sc_lock); 2886 } 2887 2888 Static void 2889 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2890 { 2891 if (prev) { 2892 prev->nextqtd = sqtd; 2893 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2894 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2895 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2896 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2897 } 2898 } 2899 2900 Static void 2901 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2902 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2903 { 2904 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2905 usb_dma_t *dma = &xfer->ux_dmabuf; 2906 uint16_t flags = xfer->ux_flags; 2907 ehci_soft_qtd_t *sqtd, *prev; 2908 int tog = *toggle; 2909 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2910 int len = length; 2911 2912 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2913 DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); 2914 DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); 2915 2916 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2917 2918 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2919 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2920 EHCI_QTD_SET_CERR(3) 2921 ; 2922 2923 sqtd = prev = NULL; 2924 size_t curoffs = 0; 2925 size_t j = 0; 2926 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2927 sqtd = exfer->ex_sqtds[j++]; 2928 DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); 2929 2930 /* 2931 * The EHCI hardware can handle at most 5 pages and they do 2932 * not have to be contiguous 2933 */ 2934 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2935 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2936 size_t curlen = len; 2937 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2938 /* must use multiple TDs, fill as much as possible. */ 2939 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2940 2941 /* the length must be a multiple of the max size */ 2942 curlen -= curlen % mps; 2943 } 2944 KASSERT(curlen != 0); 2945 DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, 2946 curoffs, 0); 2947 2948 /* Fill the qTD */ 2949 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2950 sqtd->qtd.qtd_status = htole32( 2951 qtdstatus | 2952 EHCI_QTD_SET_BYTES(curlen) | 2953 EHCI_QTD_SET_TOGGLE(tog)); 2954 2955 /* Find number of pages we'll be using, insert dma addresses */ 2956 size_t pages = EHCI_NPAGES(curlen); 2957 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2958 size_t pageoffs = EHCI_PAGE(curoffs); 2959 for (size_t i = 0; i < pages; i++) { 2960 paddr_t a = DMAADDR(dma, 2961 pageoffs + i * EHCI_PAGE_SIZE); 2962 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2963 /* Cast up to avoid compiler warnings */ 2964 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2965 DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, 2966 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2967 le32toh(sqtd->qtd.qtd_buffer[i])); 2968 } 2969 /* First buffer pointer requires a page offset to start at */ 2970 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2971 2972 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2973 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2974 2975 sqtd->len = curlen; 2976 2977 DPRINTF(" va %p pa %p len %d", va, 2978 DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2979 2980 ehci_append_sqtd(sqtd, prev); 2981 2982 if (((curlen + mps - 1) / mps) & 1) { 2983 tog ^= 1; 2984 } 2985 2986 curoffs += curlen; 2987 len -= curlen; 2988 } 2989 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2990 xfer, length, len, mps, exfer->ex_nsqtd, j); 2991 2992 if (!isread && 2993 (flags & USBD_FORCE_SHORT_XFER) && 2994 length % mps == 0) { 2995 /* Force a 0 length transfer at the end. */ 2996 2997 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2998 exfer->ex_nsqtd); 2999 prev = sqtd; 3000 sqtd = exfer->ex_sqtds[j++]; 3001 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3002 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3003 sqtd->qtd.qtd_status = htole32( 3004 qtdstatus | 3005 EHCI_QTD_SET_BYTES(0) | 3006 EHCI_QTD_SET_TOGGLE(tog)); 3007 3008 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3009 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3010 3011 ehci_append_sqtd(sqtd, prev); 3012 tog ^= 1; 3013 } 3014 3015 *lsqtd = sqtd; 3016 *toggle = tog; 3017 } 3018 3019 Static ehci_soft_itd_t * 3020 ehci_alloc_itd(ehci_softc_t *sc) 3021 { 3022 struct ehci_soft_itd *itd, *freeitd; 3023 usbd_status err; 3024 usb_dma_t dma; 3025 3026 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3027 3028 mutex_enter(&sc->sc_lock); 3029 3030 freeitd = LIST_FIRST(&sc->sc_freeitds); 3031 if (freeitd == NULL) { 3032 DPRINTF("allocating chunk", 0, 0, 0, 0); 3033 mutex_exit(&sc->sc_lock); 3034 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3035 EHCI_PAGE_SIZE, &dma); 3036 3037 if (err) { 3038 DPRINTF("alloc returned %d", err, 0, 0, 0); 3039 return NULL; 3040 } 3041 mutex_enter(&sc->sc_lock); 3042 3043 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3044 int offs = i * EHCI_ITD_SIZE; 3045 itd = KERNADDR(&dma, offs); 3046 itd->physaddr = DMAADDR(&dma, offs); 3047 itd->dma = dma; 3048 itd->offs = offs; 3049 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3050 } 3051 freeitd = LIST_FIRST(&sc->sc_freeitds); 3052 } 3053 3054 itd = freeitd; 3055 LIST_REMOVE(itd, free_list); 3056 mutex_exit(&sc->sc_lock); 3057 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3058 3059 itd->frame_list.next = NULL; 3060 itd->frame_list.prev = NULL; 3061 itd->xfer_next = NULL; 3062 itd->slot = 0; 3063 3064 return itd; 3065 } 3066 3067 Static ehci_soft_sitd_t * 3068 ehci_alloc_sitd(ehci_softc_t *sc) 3069 { 3070 struct ehci_soft_sitd *sitd, *freesitd; 3071 usbd_status err; 3072 int i, offs; 3073 usb_dma_t dma; 3074 3075 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3076 3077 mutex_enter(&sc->sc_lock); 3078 freesitd = LIST_FIRST(&sc->sc_freesitds); 3079 if (freesitd == NULL) { 3080 DPRINTF("allocating chunk", 0, 0, 0, 0); 3081 mutex_exit(&sc->sc_lock); 3082 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3083 EHCI_PAGE_SIZE, &dma); 3084 3085 if (err) { 3086 DPRINTF("alloc returned %d", err, 0, 0, 3087 0); 3088 return NULL; 3089 } 3090 3091 mutex_enter(&sc->sc_lock); 3092 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3093 offs = i * EHCI_SITD_SIZE; 3094 sitd = KERNADDR(&dma, offs); 3095 sitd->physaddr = DMAADDR(&dma, offs); 3096 sitd->dma = dma; 3097 sitd->offs = offs; 3098 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3099 } 3100 freesitd = LIST_FIRST(&sc->sc_freesitds); 3101 } 3102 3103 sitd = freesitd; 3104 LIST_REMOVE(sitd, free_list); 3105 mutex_exit(&sc->sc_lock); 3106 3107 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3108 3109 sitd->frame_list.next = NULL; 3110 sitd->frame_list.prev = NULL; 3111 sitd->xfer_next = NULL; 3112 sitd->slot = 0; 3113 3114 return sitd; 3115 } 3116 3117 /****************/ 3118 3119 /* 3120 * Close a reqular pipe. 3121 * Assumes that there are no pending transactions. 3122 */ 3123 Static void 3124 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3125 { 3126 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3127 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3128 ehci_soft_qh_t *sqh = epipe->sqh; 3129 3130 KASSERT(mutex_owned(&sc->sc_lock)); 3131 3132 ehci_rem_qh(sc, sqh, head); 3133 ehci_free_sqh(sc, epipe->sqh); 3134 } 3135 3136 /* 3137 * Abort a device request. 3138 * If this routine is called at splusb() it guarantees that the request 3139 * will be removed from the hardware scheduling and that the callback 3140 * for it will be called with USBD_CANCELLED status. 3141 * It's impossible to guarantee that the requested transfer will not 3142 * have happened since the hardware runs concurrently. 3143 * If the transaction has already happened we rely on the ordinary 3144 * interrupt processing to process it. 3145 * XXX This is most probably wrong. 3146 * XXXMRG this doesn't make sense anymore. 3147 */ 3148 Static void 3149 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3150 { 3151 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3152 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3153 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3154 ehci_soft_qh_t *sqh = epipe->sqh; 3155 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3156 ehci_physaddr_t cur; 3157 uint32_t qhstatus; 3158 int hit; 3159 int wake; 3160 3161 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3162 3163 DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); 3164 3165 KASSERT(mutex_owned(&sc->sc_lock)); 3166 ASSERT_SLEEPABLE(); 3167 3168 if (sc->sc_dying) { 3169 /* If we're dying, just do the software part. */ 3170 xfer->ux_status = status; /* make software ignore it */ 3171 callout_stop(&xfer->ux_callout); 3172 usb_transfer_complete(xfer); 3173 return; 3174 } 3175 3176 /* 3177 * If an abort is already in progress then just wait for it to 3178 * complete and return. 3179 */ 3180 if (xfer->ux_hcflags & UXFER_ABORTING) { 3181 DPRINTF("already aborting", 0, 0, 0, 0); 3182 #ifdef DIAGNOSTIC 3183 if (status == USBD_TIMEOUT) 3184 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3185 #endif 3186 /* Override the status which might be USBD_TIMEOUT. */ 3187 xfer->ux_status = status; 3188 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3189 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3190 while (xfer->ux_hcflags & UXFER_ABORTING) 3191 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3192 return; 3193 } 3194 xfer->ux_hcflags |= UXFER_ABORTING; 3195 3196 /* 3197 * Step 1: Make interrupt routine and hardware ignore xfer. 3198 */ 3199 xfer->ux_status = status; /* make software ignore it */ 3200 callout_stop(&xfer->ux_callout); 3201 ehci_del_intr_list(sc, exfer); 3202 3203 usb_syncmem(&sqh->dma, 3204 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3205 sizeof(sqh->qh.qh_qtd.qtd_status), 3206 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3207 qhstatus = sqh->qh.qh_qtd.qtd_status; 3208 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3209 usb_syncmem(&sqh->dma, 3210 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3211 sizeof(sqh->qh.qh_qtd.qtd_status), 3212 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3213 3214 if (exfer->ex_type == EX_CTRL) { 3215 fsqtd = exfer->ex_setup; 3216 lsqtd = exfer->ex_status; 3217 } else { 3218 fsqtd = exfer->ex_sqtdstart; 3219 lsqtd = exfer->ex_sqtdend; 3220 } 3221 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3222 usb_syncmem(&sqtd->dma, 3223 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3224 sizeof(sqtd->qtd.qtd_status), 3225 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3226 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3227 usb_syncmem(&sqtd->dma, 3228 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3229 sizeof(sqtd->qtd.qtd_status), 3230 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3231 if (sqtd == lsqtd) 3232 break; 3233 } 3234 3235 /* 3236 * Step 2: Wait until we know hardware has finished any possible 3237 * use of the xfer. Also make sure the soft interrupt routine 3238 * has run. 3239 */ 3240 ehci_sync_hc(sc); 3241 sc->sc_softwake = 1; 3242 usb_schedsoftintr(&sc->sc_bus); 3243 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3244 3245 /* 3246 * Step 3: Remove any vestiges of the xfer from the hardware. 3247 * The complication here is that the hardware may have executed 3248 * beyond the xfer we're trying to abort. So as we're scanning 3249 * the TDs of this xfer we check if the hardware points to 3250 * any of them. 3251 */ 3252 3253 usb_syncmem(&sqh->dma, 3254 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3255 sizeof(sqh->qh.qh_curqtd), 3256 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3257 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3258 hit = 0; 3259 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3260 hit |= cur == sqtd->physaddr; 3261 if (sqtd == lsqtd) 3262 break; 3263 } 3264 sqtd = sqtd->nextqtd; 3265 /* Zap curqtd register if hardware pointed inside the xfer. */ 3266 if (hit && sqtd != NULL) { 3267 DPRINTF("cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3268 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3269 usb_syncmem(&sqh->dma, 3270 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3271 sizeof(sqh->qh.qh_curqtd), 3272 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3273 sqh->qh.qh_qtd.qtd_status = qhstatus; 3274 usb_syncmem(&sqh->dma, 3275 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3276 sizeof(sqh->qh.qh_qtd.qtd_status), 3277 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3278 } else { 3279 DPRINTF("no hit", 0, 0, 0, 0); 3280 usb_syncmem(&sqh->dma, 3281 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3282 sizeof(sqh->qh.qh_curqtd), 3283 BUS_DMASYNC_PREREAD); 3284 } 3285 3286 /* 3287 * Step 4: Execute callback. 3288 */ 3289 #ifdef DIAGNOSTIC 3290 exfer->ex_isdone = true; 3291 #endif 3292 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3293 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3294 usb_transfer_complete(xfer); 3295 if (wake) { 3296 cv_broadcast(&xfer->ux_hccv); 3297 } 3298 3299 KASSERT(mutex_owned(&sc->sc_lock)); 3300 } 3301 3302 Static void 3303 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3304 { 3305 ehci_isoc_trans_t trans_status; 3306 struct ehci_xfer *exfer; 3307 ehci_softc_t *sc; 3308 struct ehci_soft_itd *itd; 3309 struct ehci_soft_sitd *sitd; 3310 int i, wake; 3311 3312 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3313 3314 exfer = EHCI_XFER2EXFER(xfer); 3315 sc = EHCI_XFER2SC(xfer); 3316 3317 DPRINTF("xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3318 3319 KASSERT(mutex_owned(&sc->sc_lock)); 3320 3321 if (sc->sc_dying) { 3322 xfer->ux_status = status; 3323 callout_stop(&xfer->ux_callout); 3324 usb_transfer_complete(xfer); 3325 return; 3326 } 3327 3328 if (xfer->ux_hcflags & UXFER_ABORTING) { 3329 DPRINTF("already aborting", 0, 0, 0, 0); 3330 3331 #ifdef DIAGNOSTIC 3332 if (status == USBD_TIMEOUT) 3333 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3334 #endif 3335 3336 xfer->ux_status = status; 3337 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3338 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3339 while (xfer->ux_hcflags & UXFER_ABORTING) 3340 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3341 goto done; 3342 } 3343 xfer->ux_hcflags |= UXFER_ABORTING; 3344 3345 xfer->ux_status = status; 3346 callout_stop(&xfer->ux_callout); 3347 ehci_del_intr_list(sc, exfer); 3348 3349 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3350 for (itd = exfer->ex_itdstart; itd != NULL; 3351 itd = itd->xfer_next) { 3352 usb_syncmem(&itd->dma, 3353 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3354 sizeof(itd->itd.itd_ctl), 3355 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3356 3357 for (i = 0; i < 8; i++) { 3358 trans_status = le32toh(itd->itd.itd_ctl[i]); 3359 trans_status &= ~EHCI_ITD_ACTIVE; 3360 itd->itd.itd_ctl[i] = htole32(trans_status); 3361 } 3362 3363 usb_syncmem(&itd->dma, 3364 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3365 sizeof(itd->itd.itd_ctl), 3366 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3367 } 3368 } else { 3369 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3370 sitd = sitd->xfer_next) { 3371 usb_syncmem(&sitd->dma, 3372 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3373 sizeof(sitd->sitd.sitd_buffer), 3374 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3375 3376 trans_status = le32toh(sitd->sitd.sitd_trans); 3377 trans_status &= ~EHCI_SITD_ACTIVE; 3378 sitd->sitd.sitd_trans = htole32(trans_status); 3379 3380 usb_syncmem(&sitd->dma, 3381 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3382 sizeof(sitd->sitd.sitd_buffer), 3383 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3384 } 3385 } 3386 3387 sc->sc_softwake = 1; 3388 usb_schedsoftintr(&sc->sc_bus); 3389 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3390 3391 #ifdef DIAGNOSTIC 3392 exfer->ex_isdone = true; 3393 #endif 3394 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3395 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3396 usb_transfer_complete(xfer); 3397 if (wake) { 3398 cv_broadcast(&xfer->ux_hccv); 3399 } 3400 3401 done: 3402 KASSERT(mutex_owned(&sc->sc_lock)); 3403 return; 3404 } 3405 3406 Static void 3407 ehci_timeout(void *addr) 3408 { 3409 struct usbd_xfer *xfer = addr; 3410 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3411 struct usbd_pipe *pipe = xfer->ux_pipe; 3412 struct usbd_device *dev = pipe->up_dev; 3413 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3414 3415 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3416 3417 DPRINTF("exfer %p", exfer, 0, 0, 0); 3418 #ifdef EHCI_DEBUG 3419 if (ehcidebug >= 2) 3420 usbd_dump_pipe(pipe); 3421 #endif 3422 3423 if (sc->sc_dying) { 3424 mutex_enter(&sc->sc_lock); 3425 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3426 mutex_exit(&sc->sc_lock); 3427 return; 3428 } 3429 3430 /* Execute the abort in a process context. */ 3431 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3432 USB_TASKQ_MPSAFE); 3433 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3434 } 3435 3436 Static void 3437 ehci_timeout_task(void *addr) 3438 { 3439 struct usbd_xfer *xfer = addr; 3440 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3441 3442 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3443 3444 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3445 3446 mutex_enter(&sc->sc_lock); 3447 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3448 mutex_exit(&sc->sc_lock); 3449 } 3450 3451 /************************/ 3452 3453 Static int 3454 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3455 { 3456 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3457 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3458 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3459 usb_device_request_t *req = &xfer->ux_request; 3460 ehci_soft_qtd_t *setup, *status, *next; 3461 int isread = req->bmRequestType & UT_READ; 3462 int len = xfer->ux_bufsize; 3463 int err; 3464 3465 exfer->ex_type = EX_CTRL; 3466 exfer->ex_status = NULL; 3467 exfer->ex_data = NULL; 3468 exfer->ex_setup = ehci_alloc_sqtd(sc); 3469 if (exfer->ex_setup == NULL) { 3470 err = ENOMEM; 3471 goto bad1; 3472 } 3473 exfer->ex_status = ehci_alloc_sqtd(sc); 3474 if (exfer->ex_status == NULL) { 3475 err = ENOMEM; 3476 goto bad2; 3477 } 3478 setup = exfer->ex_setup; 3479 status = exfer->ex_status; 3480 exfer->ex_nsqtd = 0; 3481 next = status; 3482 /* Set up data transaction */ 3483 if (len != 0) { 3484 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3485 &exfer->ex_data); 3486 if (err) 3487 goto bad3; 3488 next = exfer->ex_data; 3489 } 3490 3491 /* Clear toggle */ 3492 setup->qtd.qtd_status = htole32( 3493 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3494 EHCI_QTD_SET_TOGGLE(0) | 3495 EHCI_QTD_SET_BYTES(sizeof(*req)) 3496 ); 3497 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3498 setup->qtd.qtd_buffer_hi[0] = 0; 3499 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3500 setup->nextqtd = next; 3501 setup->xfer = xfer; 3502 setup->len = sizeof(*req); 3503 3504 status->qtd.qtd_status = htole32( 3505 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3506 EHCI_QTD_SET_TOGGLE(1) | 3507 EHCI_QTD_IOC 3508 ); 3509 status->qtd.qtd_buffer[0] = 0; 3510 status->qtd.qtd_buffer_hi[0] = 0; 3511 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3512 status->nextqtd = NULL; 3513 status->xfer = xfer; 3514 status->len = 0; 3515 3516 return 0; 3517 bad3: 3518 ehci_free_sqtd(sc, exfer->ex_status); 3519 bad2: 3520 ehci_free_sqtd(sc, exfer->ex_setup); 3521 bad1: 3522 return err; 3523 } 3524 3525 Static void 3526 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3527 { 3528 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3529 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3530 3531 KASSERT(ex->ex_type == EX_CTRL); 3532 3533 ehci_free_sqtd(sc, ex->ex_setup); 3534 ehci_free_sqtd(sc, ex->ex_status); 3535 ehci_free_sqtds(sc, ex); 3536 if (ex->ex_nsqtd) 3537 kmem_free(ex->ex_sqtds, 3538 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3539 } 3540 3541 Static usbd_status 3542 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3543 { 3544 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3545 usbd_status err; 3546 3547 /* Insert last in queue. */ 3548 mutex_enter(&sc->sc_lock); 3549 err = usb_insert_transfer(xfer); 3550 mutex_exit(&sc->sc_lock); 3551 if (err) 3552 return err; 3553 3554 /* Pipe isn't running, start first */ 3555 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3556 } 3557 3558 Static usbd_status 3559 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3560 { 3561 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3562 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3563 usb_device_request_t *req = &xfer->ux_request; 3564 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3565 ehci_soft_qtd_t *setup, *status, *next; 3566 ehci_soft_qh_t *sqh; 3567 3568 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3569 3570 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3571 3572 if (sc->sc_dying) 3573 return USBD_IOERROR; 3574 3575 const int isread = req->bmRequestType & UT_READ; 3576 const int len = UGETW(req->wLength); 3577 3578 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 3579 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3580 UGETW(req->wIndex)); 3581 DPRINTF("len=%d, addr=%d, endpt=%d", len, epipe->pipe.up_dev->ud_addr, 3582 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3583 3584 sqh = epipe->sqh; 3585 3586 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3587 "address QH %" __PRIuBIT " pipe %d\n", 3588 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3589 epipe->pipe.up_dev->ud_addr); 3590 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3591 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3592 "MPS QH %" __PRIuBIT " pipe %d\n", 3593 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3594 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3595 3596 setup = exfer->ex_setup; 3597 status = exfer->ex_status; 3598 3599 DPRINTF("setup %p status %p data %p", setup, status, exfer->ex_data, 0); 3600 KASSERTMSG(setup != NULL && status != NULL, 3601 "Failed memory allocation, setup %p status %p", 3602 setup, status); 3603 3604 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3605 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3606 3607 /* Clear toggle */ 3608 setup->qtd.qtd_status &= ~htole32( 3609 EHCI_QTD_STATUS_MASK | 3610 EHCI_QTD_BYTES_MASK | 3611 EHCI_QTD_TOGGLE_MASK | 3612 EHCI_QTD_CERR_MASK 3613 ); 3614 setup->qtd.qtd_status |= htole32( 3615 EHCI_QTD_ACTIVE | 3616 EHCI_QTD_SET_CERR(3) | 3617 EHCI_QTD_SET_TOGGLE(0) | 3618 EHCI_QTD_SET_BYTES(sizeof(*req)) 3619 ); 3620 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3621 setup->qtd.qtd_buffer_hi[0] = 0; 3622 3623 next = status; 3624 status->qtd.qtd_status &= ~htole32( 3625 EHCI_QTD_STATUS_MASK | 3626 EHCI_QTD_PID_MASK | 3627 EHCI_QTD_BYTES_MASK | 3628 EHCI_QTD_TOGGLE_MASK | 3629 EHCI_QTD_CERR_MASK 3630 ); 3631 status->qtd.qtd_status |= htole32( 3632 EHCI_QTD_ACTIVE | 3633 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3634 EHCI_QTD_SET_CERR(3) | 3635 EHCI_QTD_SET_TOGGLE(1) | 3636 EHCI_QTD_SET_BYTES(0) | 3637 EHCI_QTD_IOC 3638 ); 3639 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3640 3641 KASSERT(exfer->ex_isdone); 3642 #ifdef DIAGNOSTIC 3643 exfer->ex_isdone = false; 3644 #endif 3645 3646 /* Set up data transaction */ 3647 if (len != 0) { 3648 ehci_soft_qtd_t *end; 3649 3650 /* Start toggle at 1. */ 3651 int toggle = 1; 3652 next = exfer->ex_data; 3653 KASSERTMSG(next != NULL, "Failed memory allocation"); 3654 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3655 end->nextqtd = status; 3656 end->qtd.qtd_next = end->qtd.qtd_altnext = 3657 htole32(status->physaddr); 3658 3659 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3660 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3661 3662 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3663 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3664 } 3665 3666 setup->nextqtd = next; 3667 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3668 3669 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3670 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3671 3672 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3673 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3674 3675 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3676 3677 #ifdef EHCI_DEBUG 3678 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3679 ehci_dump_sqh(sqh); 3680 ehci_dump_sqtds(setup); 3681 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3682 #endif 3683 3684 mutex_enter(&sc->sc_lock); 3685 3686 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3687 ehci_set_qh_qtd(sqh, setup); 3688 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3689 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3690 ehci_timeout, xfer); 3691 } 3692 ehci_add_intr_list(sc, exfer); 3693 xfer->ux_status = USBD_IN_PROGRESS; 3694 mutex_exit(&sc->sc_lock); 3695 3696 #if 0 3697 #ifdef EHCI_DEBUG 3698 DPRINTFN(10, "status=%x, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3699 // delay(10000); 3700 ehci_dump_regs(sc); 3701 ehci_dump_sqh(sc->sc_async_head); 3702 ehci_dump_sqh(sqh); 3703 ehci_dump_sqtds(setup); 3704 #endif 3705 #endif 3706 3707 if (sc->sc_bus.ub_usepolling) 3708 ehci_waitintr(sc, xfer); 3709 3710 return USBD_IN_PROGRESS; 3711 } 3712 3713 Static void 3714 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3715 { 3716 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3717 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3718 usb_device_request_t *req = &xfer->ux_request; 3719 int len = UGETW(req->wLength); 3720 int rd = req->bmRequestType & UT_READ; 3721 3722 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3723 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3724 3725 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3726 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3727 3728 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3729 BUS_DMASYNC_POSTWRITE); 3730 if (len) 3731 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3732 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3733 3734 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3735 } 3736 3737 /* Abort a device control request. */ 3738 Static void 3739 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3740 { 3741 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3742 3743 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3744 ehci_abort_xfer(xfer, USBD_CANCELLED); 3745 } 3746 3747 /* Close a device control pipe. */ 3748 Static void 3749 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3750 { 3751 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3752 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3753 3754 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3755 3756 KASSERT(mutex_owned(&sc->sc_lock)); 3757 3758 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3759 3760 ehci_close_pipe(pipe, sc->sc_async_head); 3761 } 3762 3763 /* 3764 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3765 * qTD status, or miss signalling occasionally under heavy load. If the host 3766 * machine is too fast, we we can miss transaction completion - when we scan 3767 * the active list the transaction still seems to be active. This generally 3768 * exhibits itself as a umass stall that never recovers. 3769 * 3770 * We work around this behaviour by setting up this callback after any softintr 3771 * that completes with transactions still pending, giving us another chance to 3772 * check for completion after the writeback has taken place. 3773 */ 3774 Static void 3775 ehci_intrlist_timeout(void *arg) 3776 { 3777 ehci_softc_t *sc = arg; 3778 3779 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3780 3781 usb_schedsoftintr(&sc->sc_bus); 3782 } 3783 3784 /************************/ 3785 3786 Static int 3787 ehci_device_bulk_init(struct usbd_xfer *xfer) 3788 { 3789 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3790 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3791 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3792 int endpt = ed->bEndpointAddress; 3793 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3794 int len = xfer->ux_bufsize; 3795 int err = 0; 3796 3797 exfer->ex_type = EX_BULK; 3798 exfer->ex_nsqtd = 0; 3799 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3800 &exfer->ex_sqtdstart); 3801 3802 return err; 3803 } 3804 3805 Static void 3806 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3807 { 3808 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3809 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3810 3811 KASSERT(ex->ex_type == EX_BULK); 3812 3813 ehci_free_sqtds(sc, ex); 3814 if (ex->ex_nsqtd) 3815 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3816 } 3817 3818 Static usbd_status 3819 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3820 { 3821 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3822 usbd_status err; 3823 3824 /* Insert last in queue. */ 3825 mutex_enter(&sc->sc_lock); 3826 err = usb_insert_transfer(xfer); 3827 mutex_exit(&sc->sc_lock); 3828 if (err) 3829 return err; 3830 3831 /* Pipe isn't running, start first */ 3832 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3833 } 3834 3835 Static usbd_status 3836 ehci_device_bulk_start(struct usbd_xfer *xfer) 3837 { 3838 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3839 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3840 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3841 ehci_soft_qh_t *sqh; 3842 ehci_soft_qtd_t *end; 3843 int len, isread, endpt; 3844 3845 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3846 3847 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3848 xfer->ux_flags, 0); 3849 3850 if (sc->sc_dying) 3851 return USBD_IOERROR; 3852 3853 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3854 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3855 3856 len = xfer->ux_length; 3857 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3858 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3859 sqh = epipe->sqh; 3860 3861 KASSERT(exfer->ex_isdone); 3862 #ifdef DIAGNOSTIC 3863 exfer->ex_isdone = false; 3864 #endif 3865 3866 /* Take lock here to protect nexttoggle */ 3867 mutex_enter(&sc->sc_lock); 3868 3869 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3870 3871 exfer->ex_sqtdend = end; 3872 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3873 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3874 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3875 3876 #ifdef EHCI_DEBUG 3877 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3878 ehci_dump_sqh(sqh); 3879 ehci_dump_sqtds(exfer->ex_sqtdstart); 3880 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3881 #endif 3882 3883 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3884 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3885 3886 /* also does usb_syncmem(sqh) */ 3887 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3888 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3889 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3890 ehci_timeout, xfer); 3891 } 3892 ehci_add_intr_list(sc, exfer); 3893 xfer->ux_status = USBD_IN_PROGRESS; 3894 mutex_exit(&sc->sc_lock); 3895 3896 #if 0 3897 #ifdef EHCI_DEBUG 3898 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3899 // delay(10000); 3900 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3901 ehci_dump_regs(sc); 3902 #if 0 3903 printf("async_head:\n"); 3904 ehci_dump_sqh(sc->sc_async_head); 3905 #endif 3906 DPRINTF("sqh:", 0, 0, 0, 0); 3907 ehci_dump_sqh(sqh); 3908 ehci_dump_sqtds(exfer->ex_sqtdstart); 3909 #endif 3910 #endif 3911 3912 if (sc->sc_bus.ub_usepolling) 3913 ehci_waitintr(sc, xfer); 3914 3915 return USBD_IN_PROGRESS; 3916 } 3917 3918 Static void 3919 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3920 { 3921 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3922 3923 DPRINTF("xfer %p", xfer, 0, 0, 0); 3924 ehci_abort_xfer(xfer, USBD_CANCELLED); 3925 } 3926 3927 /* 3928 * Close a device bulk pipe. 3929 */ 3930 Static void 3931 ehci_device_bulk_close(struct usbd_pipe *pipe) 3932 { 3933 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3934 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3935 3936 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3937 3938 KASSERT(mutex_owned(&sc->sc_lock)); 3939 3940 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3941 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3942 ehci_close_pipe(pipe, sc->sc_async_head); 3943 } 3944 3945 Static void 3946 ehci_device_bulk_done(struct usbd_xfer *xfer) 3947 { 3948 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3949 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3950 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3951 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3952 3953 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3954 3955 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 3956 3957 KASSERT(mutex_owned(&sc->sc_lock)); 3958 3959 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3960 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3961 3962 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3963 } 3964 3965 /************************/ 3966 3967 Static usbd_status 3968 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3969 { 3970 struct ehci_soft_islot *isp; 3971 int islot, lev; 3972 3973 /* Find a poll rate that is large enough. */ 3974 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3975 if (EHCI_ILEV_IVAL(lev) <= ival) 3976 break; 3977 3978 /* Pick an interrupt slot at the right level. */ 3979 /* XXX could do better than picking at random */ 3980 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3981 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3982 3983 sqh->islot = islot; 3984 isp = &sc->sc_islots[islot]; 3985 mutex_enter(&sc->sc_lock); 3986 ehci_add_qh(sc, sqh, isp->sqh); 3987 mutex_exit(&sc->sc_lock); 3988 3989 return USBD_NORMAL_COMPLETION; 3990 } 3991 3992 3993 Static int 3994 ehci_device_intr_init(struct usbd_xfer *xfer) 3995 { 3996 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3997 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3998 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3999 int endpt = ed->bEndpointAddress; 4000 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4001 int len = xfer->ux_bufsize; 4002 int err; 4003 4004 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4005 4006 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4007 xfer->ux_flags, 0); 4008 4009 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4010 KASSERT(len != 0); 4011 4012 exfer->ex_type = EX_INTR; 4013 exfer->ex_nsqtd = 0; 4014 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4015 &exfer->ex_sqtdstart); 4016 4017 return err; 4018 } 4019 4020 Static void 4021 ehci_device_intr_fini(struct usbd_xfer *xfer) 4022 { 4023 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4024 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4025 4026 KASSERT(ex->ex_type == EX_INTR); 4027 4028 ehci_free_sqtds(sc, ex); 4029 if (ex->ex_nsqtd) 4030 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4031 } 4032 4033 Static usbd_status 4034 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4035 { 4036 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4037 usbd_status err; 4038 4039 /* Insert last in queue. */ 4040 mutex_enter(&sc->sc_lock); 4041 err = usb_insert_transfer(xfer); 4042 mutex_exit(&sc->sc_lock); 4043 if (err) 4044 return err; 4045 4046 /* 4047 * Pipe isn't running (otherwise err would be USBD_INPROG), 4048 * so start it first. 4049 */ 4050 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4051 } 4052 4053 Static usbd_status 4054 ehci_device_intr_start(struct usbd_xfer *xfer) 4055 { 4056 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4057 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4058 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4059 ehci_soft_qtd_t *end; 4060 ehci_soft_qh_t *sqh; 4061 int len, isread, endpt; 4062 4063 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4064 4065 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4066 xfer->ux_flags, 0); 4067 4068 if (sc->sc_dying) 4069 return USBD_IOERROR; 4070 4071 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4072 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4073 4074 len = xfer->ux_length; 4075 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4076 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4077 sqh = epipe->sqh; 4078 4079 KASSERT(exfer->ex_isdone); 4080 #ifdef DIAGNOSTIC 4081 exfer->ex_isdone = false; 4082 #endif 4083 4084 /* Take lock to protect nexttoggle */ 4085 mutex_enter(&sc->sc_lock); 4086 4087 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4088 4089 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4090 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4091 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4092 exfer->ex_sqtdend = end; 4093 4094 #ifdef EHCI_DEBUG 4095 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4096 ehci_dump_sqh(sqh); 4097 ehci_dump_sqtds(exfer->ex_sqtdstart); 4098 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4099 #endif 4100 4101 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4102 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4103 4104 /* also does usb_syncmem(sqh) */ 4105 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4106 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4107 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4108 ehci_timeout, xfer); 4109 } 4110 ehci_add_intr_list(sc, exfer); 4111 xfer->ux_status = USBD_IN_PROGRESS; 4112 mutex_exit(&sc->sc_lock); 4113 4114 #if 0 4115 #ifdef EHCI_DEBUG 4116 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4117 // delay(10000); 4118 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4119 ehci_dump_regs(sc); 4120 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4121 ehci_dump_sqh(sqh); 4122 ehci_dump_sqtds(exfer->ex_sqtdstart); 4123 #endif 4124 #endif 4125 4126 if (sc->sc_bus.ub_usepolling) 4127 ehci_waitintr(sc, xfer); 4128 4129 return USBD_IN_PROGRESS; 4130 } 4131 4132 Static void 4133 ehci_device_intr_abort(struct usbd_xfer *xfer) 4134 { 4135 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4136 4137 DPRINTF("xfer=%p", xfer, 0, 0, 0); 4138 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4139 4140 /* 4141 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4142 * async doorbell. That's dependent on the async list, wheras 4143 * intr xfers are periodic, should not use this? 4144 */ 4145 ehci_abort_xfer(xfer, USBD_CANCELLED); 4146 } 4147 4148 Static void 4149 ehci_device_intr_close(struct usbd_pipe *pipe) 4150 { 4151 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4152 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4153 struct ehci_soft_islot *isp; 4154 4155 KASSERT(mutex_owned(&sc->sc_lock)); 4156 4157 isp = &sc->sc_islots[epipe->sqh->islot]; 4158 ehci_close_pipe(pipe, isp->sqh); 4159 } 4160 4161 Static void 4162 ehci_device_intr_done(struct usbd_xfer *xfer) 4163 { 4164 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4165 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4166 int isread, endpt; 4167 4168 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4169 4170 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4171 0, 0); 4172 4173 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4174 4175 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4176 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4177 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4178 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4179 } 4180 4181 /************************/ 4182 Static int 4183 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4184 { 4185 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4186 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4187 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4188 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4189 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4190 int i, k, frames; 4191 u_int huba, dir; 4192 int err; 4193 4194 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4195 4196 start = NULL; 4197 sitd = NULL; 4198 4199 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4200 xfer->ux_flags, 0); 4201 4202 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4203 KASSERT(xfer->ux_nframes != 0); 4204 KASSERT(exfer->ex_isdone); 4205 4206 exfer->ex_type = EX_FS_ISOC; 4207 /* 4208 * Step 1: Allocate and initialize sitds. 4209 */ 4210 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4211 if (i > 16 || i == 0) { 4212 /* Spec page 271 says intervals > 16 are invalid */ 4213 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4214 4215 return EINVAL; 4216 } 4217 4218 frames = xfer->ux_nframes; 4219 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4220 sitd = ehci_alloc_sitd(sc); 4221 if (sitd == NULL) { 4222 err = ENOMEM; 4223 goto fail; 4224 } 4225 4226 if (prev) 4227 prev->xfer_next = sitd; 4228 else 4229 start = sitd; 4230 4231 huba = dev->ud_myhsport->up_parent->ud_addr; 4232 4233 #if 0 4234 if (sc->sc_flags & EHCIF_FREESCALE) { 4235 // Set hub address to 0 if embedded TT is used. 4236 if (huba == sc->sc_addr) 4237 huba = 0; 4238 } 4239 #endif 4240 4241 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4242 dir = UE_GET_DIR(k) ? 1 : 0; 4243 sitd->sitd.sitd_endp = 4244 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4245 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4246 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4247 EHCI_SITD_SET_HUBA(huba) | 4248 EHCI_SITD_SET_DIR(dir)); 4249 4250 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4251 } /* End of frame */ 4252 4253 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4254 4255 stop = sitd; 4256 stop->xfer_next = NULL; 4257 exfer->ex_sitdstart = start; 4258 exfer->ex_sitdend = stop; 4259 4260 return 0; 4261 4262 fail: 4263 mutex_enter(&sc->sc_lock); 4264 ehci_soft_sitd_t *next; 4265 for (sitd = start; sitd; sitd = next) { 4266 next = sitd->xfer_next; 4267 ehci_free_sitd_locked(sc, sitd); 4268 } 4269 mutex_exit(&sc->sc_lock); 4270 4271 return err; 4272 } 4273 4274 Static void 4275 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4276 { 4277 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4278 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4279 4280 KASSERT(ex->ex_type == EX_FS_ISOC); 4281 4282 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4283 } 4284 4285 Static usbd_status 4286 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4287 { 4288 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4289 usbd_status __diagused err; 4290 4291 mutex_enter(&sc->sc_lock); 4292 err = usb_insert_transfer(xfer); 4293 mutex_exit(&sc->sc_lock); 4294 4295 KASSERT(err == USBD_NORMAL_COMPLETION); 4296 4297 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4298 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4299 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4300 ehci_soft_sitd_t *sitd; 4301 usb_dma_t *dma_buf; 4302 int i, j, k, frames; 4303 int offs, total_length; 4304 int frindex; 4305 u_int dir; 4306 4307 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4308 4309 sitd = NULL; 4310 total_length = 0; 4311 4312 4313 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4314 xfer->ux_flags, 0); 4315 4316 if (sc->sc_dying) 4317 return USBD_IOERROR; 4318 4319 /* 4320 * To avoid complication, don't allow a request right now that'll span 4321 * the entire frame table. To within 4 frames, to allow some leeway 4322 * on either side of where the hc currently is. 4323 */ 4324 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4325 xfer->ux_nframes >= sc->sc_flsize - 4) { 4326 printf("ehci: isoc descriptor requested that spans the entire" 4327 "frametable, too many frames\n"); 4328 return USBD_INVAL; 4329 } 4330 4331 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4332 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4333 KASSERT(exfer->ex_isdone); 4334 #ifdef DIAGNOSTIC 4335 exfer->ex_isdone = false; 4336 #endif 4337 4338 /* 4339 * Step 1: Initialize sitds. 4340 */ 4341 4342 frames = xfer->ux_nframes; 4343 dma_buf = &xfer->ux_dmabuf; 4344 offs = 0; 4345 4346 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4347 i++, sitd = sitd->xfer_next) { 4348 KASSERT(sitd != NULL); 4349 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4350 4351 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4352 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4353 4354 /* Set page0 index and offset - TP and T-offset are set below */ 4355 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4356 4357 total_length += xfer->ux_frlengths[i]; 4358 offs += xfer->ux_frlengths[i]; 4359 4360 sitd->sitd.sitd_buffer[1] = 4361 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4362 4363 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4364 4365 #if 0 4366 if (sc->sc_flags & EHCIF_FREESCALE) { 4367 // Set hub address to 0 if embedded TT is used. 4368 if (huba == sc->sc_addr) 4369 huba = 0; 4370 } 4371 #endif 4372 4373 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4374 dir = UE_GET_DIR(k) ? 1 : 0; 4375 KASSERT(sitd->sitd.sitd_endp == htole32( 4376 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4377 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4378 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4379 EHCI_SITD_SET_HUBA(huba) | 4380 EHCI_SITD_SET_DIR(dir))); 4381 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4382 4383 uint8_t sa = 0; 4384 uint8_t sb = 0; 4385 u_int temp, tlen; 4386 4387 if (dir == 0) { /* OUT */ 4388 temp = 0; 4389 tlen = xfer->ux_frlengths[i]; 4390 if (tlen <= 188) { 4391 temp |= 1; /* T-count = 1, TP = ALL */ 4392 tlen = 1; 4393 } else { 4394 tlen += 187; 4395 tlen /= 188; 4396 temp |= tlen; /* T-count = [1..6] */ 4397 temp |= 8; /* TP = Begin */ 4398 } 4399 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4400 4401 tlen += sa; 4402 4403 if (tlen >= 8) { 4404 sb = 0; 4405 } else { 4406 sb = (1 << tlen); 4407 } 4408 4409 sa = (1 << sa); 4410 sa = (sb - sa) & 0x3F; 4411 sb = 0; 4412 } else { 4413 sb = (-(4 << sa)) & 0xFE; 4414 sa = (1 << sa) & 0x3F; 4415 sa = 0x01; 4416 sb = 0xfc; 4417 } 4418 4419 sitd->sitd.sitd_sched = htole32( 4420 EHCI_SITD_SET_SMASK(sa) | 4421 EHCI_SITD_SET_CMASK(sb) 4422 ); 4423 4424 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4425 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4426 } /* End of frame */ 4427 4428 sitd = exfer->ex_sitdend; 4429 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4430 4431 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4432 sizeof(sitd->sitd.sitd_trans), 4433 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4434 4435 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4436 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4437 4438 /* 4439 * Part 2: Transfer descriptors have now been set up, now they must 4440 * be scheduled into the periodic frame list. Erk. Not wanting to 4441 * complicate matters, transfer is denied if the transfer spans 4442 * more than the period frame list. 4443 */ 4444 4445 mutex_enter(&sc->sc_lock); 4446 4447 /* Start inserting frames */ 4448 if (epipe->isoc.cur_xfers > 0) { 4449 frindex = epipe->isoc.next_frame; 4450 } else { 4451 frindex = EOREAD4(sc, EHCI_FRINDEX); 4452 frindex = frindex >> 3; /* Erase microframe index */ 4453 frindex += 2; 4454 } 4455 4456 if (frindex >= sc->sc_flsize) 4457 frindex &= (sc->sc_flsize - 1); 4458 4459 /* Whats the frame interval? */ 4460 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4461 4462 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4463 j++, sitd = sitd->xfer_next) { 4464 KASSERT(sitd); 4465 4466 usb_syncmem(&sc->sc_fldma, 4467 sizeof(ehci_link_t) * frindex, 4468 sizeof(ehci_link_t), 4469 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4470 4471 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4472 if (sitd->sitd.sitd_next == 0) 4473 /* 4474 * FIXME: frindex table gets initialized to NULL 4475 * or EHCI_NULL? 4476 */ 4477 sitd->sitd.sitd_next = EHCI_NULL; 4478 4479 usb_syncmem(&sitd->dma, 4480 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4481 sizeof(ehci_sitd_t), 4482 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4483 4484 sc->sc_flist[frindex] = 4485 htole32(EHCI_LINK_SITD | sitd->physaddr); 4486 4487 usb_syncmem(&sc->sc_fldma, 4488 sizeof(ehci_link_t) * frindex, 4489 sizeof(ehci_link_t), 4490 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4491 4492 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4493 sc->sc_softsitds[frindex] = sitd; 4494 if (sitd->frame_list.next != NULL) 4495 sitd->frame_list.next->frame_list.prev = sitd; 4496 sitd->slot = frindex; 4497 sitd->frame_list.prev = NULL; 4498 4499 frindex += i; 4500 if (frindex >= sc->sc_flsize) 4501 frindex -= sc->sc_flsize; 4502 } 4503 4504 epipe->isoc.cur_xfers++; 4505 epipe->isoc.next_frame = frindex; 4506 4507 ehci_add_intr_list(sc, exfer); 4508 xfer->ux_status = USBD_IN_PROGRESS; 4509 4510 mutex_exit(&sc->sc_lock); 4511 4512 if (sc->sc_bus.ub_usepolling) { 4513 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4514 ehci_waitintr(sc, xfer); 4515 } 4516 4517 return USBD_IN_PROGRESS; 4518 } 4519 4520 Static void 4521 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4522 { 4523 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4524 4525 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4526 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4527 } 4528 4529 Static void 4530 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4531 { 4532 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4533 4534 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4535 } 4536 4537 Static void 4538 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4539 { 4540 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4541 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4542 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4543 4544 KASSERT(mutex_owned(&sc->sc_lock)); 4545 4546 epipe->isoc.cur_xfers--; 4547 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4548 4549 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4550 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4551 } 4552 4553 4554 /************************/ 4555 4556 4557 Static int 4558 ehci_device_isoc_init(struct usbd_xfer *xfer) 4559 { 4560 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4561 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4562 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4563 ehci_soft_itd_t *itd, *prev, *start, *stop; 4564 int i, j, k; 4565 int frames, ufrperframe; 4566 int err; 4567 4568 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4569 4570 start = NULL; 4571 prev = NULL; 4572 itd = NULL; 4573 4574 KASSERT(xfer->ux_nframes != 0); 4575 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4576 KASSERT(exfer->ex_isdone); 4577 4578 exfer->ex_type = EX_ISOC; 4579 4580 /* 4581 * Step 1: Allocate and initialize itds, how many do we need? 4582 * One per transfer if interval >= 8 microframes, less if we use 4583 * multiple microframes per frame. 4584 */ 4585 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4586 if (i > 16 || i == 0) { 4587 /* Spec page 271 says intervals > 16 are invalid */ 4588 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4589 return USBD_INVAL; 4590 } 4591 4592 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4593 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4594 4595 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4596 itd = ehci_alloc_itd(sc); 4597 if (itd == NULL) { 4598 err = ENOMEM; 4599 goto fail; 4600 } 4601 4602 if (prev != NULL) { 4603 /* Maybe not as it's updated by the scheduling? */ 4604 prev->itd.itd_next = 4605 htole32(itd->physaddr | EHCI_LINK_ITD); 4606 4607 prev->xfer_next = itd; 4608 } else { 4609 start = itd; 4610 } 4611 4612 /* 4613 * Other special values 4614 */ 4615 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4616 itd->itd.itd_bufr[0] = htole32( 4617 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4618 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4619 4620 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4621 ? 1 : 0; 4622 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4623 itd->itd.itd_bufr[1] |= htole32( 4624 EHCI_ITD_SET_DIR(k) | 4625 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4626 4627 /* FIXME: handle invalid trans - should be done in openpipe */ 4628 itd->itd.itd_bufr[2] |= 4629 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4630 } /* End of frame */ 4631 4632 stop = itd; 4633 stop->xfer_next = NULL; 4634 4635 exfer->ex_itdstart = start; 4636 exfer->ex_itdend = stop; 4637 4638 return 0; 4639 fail: 4640 mutex_enter(&sc->sc_lock); 4641 ehci_soft_itd_t *next; 4642 for (itd = start; itd; itd = next) { 4643 next = itd->xfer_next; 4644 ehci_free_itd_locked(sc, itd); 4645 } 4646 mutex_exit(&sc->sc_lock); 4647 4648 return err; 4649 4650 } 4651 4652 Static void 4653 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4654 { 4655 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4656 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4657 4658 KASSERT(ex->ex_type == EX_ISOC); 4659 4660 ehci_free_itd_chain(sc, ex->ex_itdstart); 4661 } 4662 4663 Static usbd_status 4664 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4665 { 4666 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4667 usbd_status __diagused err; 4668 4669 mutex_enter(&sc->sc_lock); 4670 err = usb_insert_transfer(xfer); 4671 mutex_exit(&sc->sc_lock); 4672 4673 KASSERT(err == USBD_NORMAL_COMPLETION); 4674 4675 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4676 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4677 ehci_soft_itd_t *itd, *prev; 4678 usb_dma_t *dma_buf; 4679 int i, j; 4680 int frames, uframes, ufrperframe; 4681 int trans_count, offs, total_length; 4682 int frindex; 4683 4684 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4685 4686 prev = NULL; 4687 itd = NULL; 4688 trans_count = 0; 4689 total_length = 0; 4690 4691 DPRINTF("xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4692 4693 if (sc->sc_dying) 4694 return USBD_IOERROR; 4695 4696 /* 4697 * To avoid complication, don't allow a request right now that'll span 4698 * the entire frame table. To within 4 frames, to allow some leeway 4699 * on either side of where the hc currently is. 4700 */ 4701 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4702 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4703 DPRINTF( 4704 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4705 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4706 return USBD_INVAL; 4707 } 4708 4709 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4710 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4711 KASSERT(exfer->ex_isdone); 4712 #ifdef DIAGNOSTIC 4713 exfer->ex_isdone = false; 4714 #endif 4715 4716 /* 4717 * Step 1: Re-Initialize itds 4718 */ 4719 4720 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4721 if (i > 16 || i == 0) { 4722 /* Spec page 271 says intervals > 16 are invalid */ 4723 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4724 return USBD_INVAL; 4725 } 4726 4727 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4728 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4729 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4730 4731 if (frames == 0) { 4732 DPRINTF("frames == 0", 0, 0, 0, 0); 4733 return USBD_INVAL; 4734 } 4735 4736 dma_buf = &xfer->ux_dmabuf; 4737 offs = 0; 4738 4739 itd = exfer->ex_itdstart; 4740 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4741 int froffs = offs; 4742 4743 if (prev != NULL) { 4744 prev->itd.itd_next = 4745 htole32(itd->physaddr | EHCI_LINK_ITD); 4746 usb_syncmem(&prev->dma, 4747 prev->offs + offsetof(ehci_itd_t, itd_next), 4748 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4749 prev->xfer_next = itd; 4750 } 4751 4752 /* 4753 * Step 1.5, initialize uframes 4754 */ 4755 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4756 /* Calculate which page in the list this starts in */ 4757 int addr = DMAADDR(dma_buf, froffs); 4758 addr = EHCI_PAGE_OFFSET(addr); 4759 addr += (offs - froffs); 4760 addr = EHCI_PAGE(addr); 4761 addr /= EHCI_PAGE_SIZE; 4762 4763 /* 4764 * This gets the initial offset into the first page, 4765 * looks how far further along the current uframe 4766 * offset is. Works out how many pages that is. 4767 */ 4768 4769 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4770 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4771 EHCI_ITD_SET_PG(addr) | 4772 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4773 4774 total_length += xfer->ux_frlengths[trans_count]; 4775 offs += xfer->ux_frlengths[trans_count]; 4776 trans_count++; 4777 4778 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4779 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4780 break; 4781 } 4782 } 4783 4784 /* 4785 * Step 1.75, set buffer pointers. To simplify matters, all 4786 * pointers are filled out for the next 7 hardware pages in 4787 * the dma block, so no need to worry what pages to cover 4788 * and what to not. 4789 */ 4790 4791 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4792 /* 4793 * Don't try to lookup a page that's past the end 4794 * of buffer 4795 */ 4796 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4797 if (page_offs >= dma_buf->udma_block->size) 4798 break; 4799 4800 uint64_t page = DMAADDR(dma_buf, page_offs); 4801 page = EHCI_PAGE(page); 4802 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4803 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4804 } 4805 /* 4806 * Other special values 4807 */ 4808 4809 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4810 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4811 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4812 4813 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4814 ? 1 : 0; 4815 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4816 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4817 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4818 4819 /* FIXME: handle invalid trans */ 4820 itd->itd.itd_bufr[2] |= 4821 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4822 4823 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4824 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4825 4826 prev = itd; 4827 } /* End of frame */ 4828 4829 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4830 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4831 4832 /* 4833 * Part 2: Transfer descriptors have now been set up, now they must 4834 * be scheduled into the period frame list. Erk. Not wanting to 4835 * complicate matters, transfer is denied if the transfer spans 4836 * more than the period frame list. 4837 */ 4838 4839 mutex_enter(&sc->sc_lock); 4840 4841 /* Start inserting frames */ 4842 if (epipe->isoc.cur_xfers > 0) { 4843 frindex = epipe->isoc.next_frame; 4844 } else { 4845 frindex = EOREAD4(sc, EHCI_FRINDEX); 4846 frindex = frindex >> 3; /* Erase microframe index */ 4847 frindex += 2; 4848 } 4849 4850 if (frindex >= sc->sc_flsize) 4851 frindex &= (sc->sc_flsize - 1); 4852 4853 /* What's the frame interval? */ 4854 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4855 if (i / USB_UFRAMES_PER_FRAME == 0) 4856 i = 1; 4857 else 4858 i /= USB_UFRAMES_PER_FRAME; 4859 4860 itd = exfer->ex_itdstart; 4861 for (j = 0; j < frames; j++) { 4862 KASSERTMSG(itd != NULL, "frame %d\n", j); 4863 4864 usb_syncmem(&sc->sc_fldma, 4865 sizeof(ehci_link_t) * frindex, 4866 sizeof(ehci_link_t), 4867 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4868 4869 itd->itd.itd_next = sc->sc_flist[frindex]; 4870 if (itd->itd.itd_next == 0) 4871 /* 4872 * FIXME: frindex table gets initialized to NULL 4873 * or EHCI_NULL? 4874 */ 4875 itd->itd.itd_next = EHCI_NULL; 4876 4877 usb_syncmem(&itd->dma, 4878 itd->offs + offsetof(ehci_itd_t, itd_next), 4879 sizeof(itd->itd.itd_next), 4880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4881 4882 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4883 4884 usb_syncmem(&sc->sc_fldma, 4885 sizeof(ehci_link_t) * frindex, 4886 sizeof(ehci_link_t), 4887 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4888 4889 itd->frame_list.next = sc->sc_softitds[frindex]; 4890 sc->sc_softitds[frindex] = itd; 4891 if (itd->frame_list.next != NULL) 4892 itd->frame_list.next->frame_list.prev = itd; 4893 itd->slot = frindex; 4894 itd->frame_list.prev = NULL; 4895 4896 frindex += i; 4897 if (frindex >= sc->sc_flsize) 4898 frindex -= sc->sc_flsize; 4899 4900 itd = itd->xfer_next; 4901 } 4902 4903 epipe->isoc.cur_xfers++; 4904 epipe->isoc.next_frame = frindex; 4905 4906 ehci_add_intr_list(sc, exfer); 4907 xfer->ux_status = USBD_IN_PROGRESS; 4908 4909 mutex_exit(&sc->sc_lock); 4910 4911 if (sc->sc_bus.ub_usepolling) { 4912 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4913 ehci_waitintr(sc, xfer); 4914 } 4915 4916 return USBD_IN_PROGRESS; 4917 } 4918 4919 Static void 4920 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4921 { 4922 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4923 4924 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4925 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4926 } 4927 4928 Static void 4929 ehci_device_isoc_close(struct usbd_pipe *pipe) 4930 { 4931 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4932 4933 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4934 } 4935 4936 Static void 4937 ehci_device_isoc_done(struct usbd_xfer *xfer) 4938 { 4939 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4940 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4941 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4942 4943 KASSERT(mutex_owned(&sc->sc_lock)); 4944 4945 epipe->isoc.cur_xfers--; 4946 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4947 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4948 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4949 } 4950
Indexes created Mon Sep 22 21:09:42 GMT 2025