ehci.c revision 1.251
1 /* $NetBSD: ehci.c,v 1.251 2016/05/06 16:30:01 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.251 2016/05/06 16:30:01 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static void ehci_intrlist_timeout(void *); 172 Static void ehci_doorbell(void *); 173 Static void ehci_pcd(void *); 174 175 Static struct usbd_xfer * 176 ehci_allocx(struct usbd_bus *, unsigned int); 177 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 178 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_softwake_cv, "ehciab"); 416 cv_init(&sc->sc_doorbell, "ehcidi"); 417 418 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 419 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 420 421 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 422 ehci_doorbell, sc); 423 KASSERT(sc->sc_doorbell_si != NULL); 424 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 425 ehci_pcd, sc); 426 KASSERT(sc->sc_pcd_si != NULL); 427 428 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 429 430 vers = EREAD2(sc, EHCI_HCIVERSION); 431 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 432 vers >> 8, vers & 0xff); 433 434 sparams = EREAD4(sc, EHCI_HCSPARAMS); 435 DPRINTF("sparams=%#x", sparams, 0, 0, 0); 436 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 437 ncomp = EHCI_HCS_N_CC(sparams); 438 if (ncomp != sc->sc_ncomp) { 439 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 440 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 441 #if NOHCI == 0 || NUHCI == 0 442 aprint_error("%s: ohci or uhci probably not configured\n", 443 device_xname(sc->sc_dev)); 444 #endif 445 if (ncomp < sc->sc_ncomp) 446 sc->sc_ncomp = ncomp; 447 } 448 if (sc->sc_ncomp > 0) { 449 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 450 aprint_normal("%s: companion controller%s, %d port%s each:", 451 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 452 EHCI_HCS_N_PCC(sparams), 453 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 454 for (i = 0; i < sc->sc_ncomp; i++) 455 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 456 aprint_normal("\n"); 457 } 458 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 459 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 460 461 cparams = EREAD4(sc, EHCI_HCCPARAMS); 462 DPRINTF("cparams=%#x", cparams, 0, 0, 0); 463 464 if (EHCI_HCC_64BIT(cparams)) { 465 /* MUST clear segment register if 64 bit capable. */ 466 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 467 } 468 469 if (cparams & EHCI_HCC_IST_FULLFRAME) { 470 sc->sc_istthreshold = 0; 471 } else { 472 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 473 } 474 475 sc->sc_bus.ub_revision = USBREV_2_0; 476 sc->sc_bus.ub_usedma = true; 477 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 478 479 /* Reset the controller */ 480 DPRINTF("resetting", 0, 0, 0, 0); 481 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 482 usb_delay_ms(&sc->sc_bus, 1); 483 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 484 for (i = 0; i < 100; i++) { 485 usb_delay_ms(&sc->sc_bus, 1); 486 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 487 if (!hcr) 488 break; 489 } 490 if (hcr) { 491 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 492 return EIO; 493 } 494 if (sc->sc_vendor_init) 495 sc->sc_vendor_init(sc); 496 497 /* XXX need proper intr scheduling */ 498 sc->sc_rand = 96; 499 500 /* frame list size at default, read back what we got and use that */ 501 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 502 case 0: sc->sc_flsize = 1024; break; 503 case 1: sc->sc_flsize = 512; break; 504 case 2: sc->sc_flsize = 256; break; 505 case 3: return EIO; 506 } 507 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 508 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 509 if (err) 510 return err; 511 DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); 512 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 513 514 for (i = 0; i < sc->sc_flsize; i++) { 515 sc->sc_flist[i] = EHCI_NULL; 516 } 517 518 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 519 520 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 521 KM_SLEEP); 522 if (sc->sc_softitds == NULL) 523 return ENOMEM; 524 LIST_INIT(&sc->sc_freeitds); 525 LIST_INIT(&sc->sc_freesitds); 526 TAILQ_INIT(&sc->sc_intrhead); 527 528 /* Set up the bus struct. */ 529 sc->sc_bus.ub_methods = &ehci_bus_methods; 530 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 531 532 sc->sc_eintrs = EHCI_NORMAL_INTRS; 533 534 /* 535 * Allocate the interrupt dummy QHs. These are arranged to give poll 536 * intervals that are powers of 2 times 1ms. 537 */ 538 for (i = 0; i < EHCI_INTRQHS; i++) { 539 sqh = ehci_alloc_sqh(sc); 540 if (sqh == NULL) { 541 err = ENOMEM; 542 goto bad1; 543 } 544 sc->sc_islots[i].sqh = sqh; 545 } 546 for (i = 0; i < EHCI_INTRQHS; i++) { 547 sqh = sc->sc_islots[i].sqh; 548 if (i == 0) { 549 /* The last (1ms) QH terminates. */ 550 sqh->qh.qh_link = EHCI_NULL; 551 sqh->next = NULL; 552 } else { 553 /* Otherwise the next QH has half the poll interval */ 554 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 555 sqh->qh.qh_link = htole32(sqh->next->physaddr | 556 EHCI_LINK_QH); 557 } 558 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 559 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 560 sqh->qh.qh_curqtd = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 562 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 563 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 564 sqh->sqtd = NULL; 565 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 566 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 567 } 568 /* Point the frame list at the last level (128ms). */ 569 for (i = 0; i < sc->sc_flsize; i++) { 570 int j; 571 572 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 573 revbits[i & (EHCI_MAX_POLLRATE-1)]; 574 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 575 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 576 i)].sqh->physaddr); 577 } 578 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 579 BUS_DMASYNC_PREWRITE); 580 581 /* Allocate dummy QH that starts the async list. */ 582 sqh = ehci_alloc_sqh(sc); 583 if (sqh == NULL) { 584 err = ENOMEM; 585 goto bad1; 586 } 587 /* Fill the QH */ 588 sqh->qh.qh_endp = 589 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 590 sqh->qh.qh_link = 591 htole32(sqh->physaddr | EHCI_LINK_QH); 592 sqh->qh.qh_curqtd = EHCI_NULL; 593 sqh->next = NULL; 594 /* Fill the overlay qTD */ 595 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 596 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 597 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 598 sqh->sqtd = NULL; 599 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 600 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 601 #ifdef EHCI_DEBUG 602 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 603 ehci_dump_sqh(sqh); 604 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 605 #endif 606 607 /* Point to async list */ 608 sc->sc_async_head = sqh; 609 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 610 611 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 612 613 /* Turn on controller */ 614 EOWRITE4(sc, EHCI_USBCMD, 615 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 616 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 617 EHCI_CMD_ASE | 618 EHCI_CMD_PSE | 619 EHCI_CMD_RS); 620 621 /* Take over port ownership */ 622 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 623 624 for (i = 0; i < 100; i++) { 625 usb_delay_ms(&sc->sc_bus, 1); 626 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 627 if (!hcr) 628 break; 629 } 630 if (hcr) { 631 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 632 return EIO; 633 } 634 635 /* Enable interrupts */ 636 DPRINTF("enabling interupts", 0, 0, 0, 0); 637 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 638 639 return 0; 640 641 #if 0 642 bad2: 643 ehci_free_sqh(sc, sc->sc_async_head); 644 #endif 645 bad1: 646 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 647 return err; 648 } 649 650 int 651 ehci_intr(void *v) 652 { 653 ehci_softc_t *sc = v; 654 int ret = 0; 655 656 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 657 658 if (sc == NULL) 659 return 0; 660 661 mutex_spin_enter(&sc->sc_intr_lock); 662 663 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 664 goto done; 665 666 /* If we get an interrupt while polling, then just ignore it. */ 667 if (sc->sc_bus.ub_usepolling) { 668 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 669 670 if (intrs) 671 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 672 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 673 goto done; 674 } 675 676 ret = ehci_intr1(sc); 677 678 done: 679 mutex_spin_exit(&sc->sc_intr_lock); 680 return ret; 681 } 682 683 Static int 684 ehci_intr1(ehci_softc_t *sc) 685 { 686 uint32_t intrs, eintrs; 687 688 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 689 690 /* In case the interrupt occurs before initialization has completed. */ 691 if (sc == NULL) { 692 #ifdef DIAGNOSTIC 693 printf("ehci_intr1: sc == NULL\n"); 694 #endif 695 return 0; 696 } 697 698 KASSERT(mutex_owned(&sc->sc_intr_lock)); 699 700 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 701 if (!intrs) 702 return 0; 703 704 eintrs = intrs & sc->sc_eintrs; 705 DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, 706 EOREAD4(sc, EHCI_USBSTS), eintrs); 707 if (!eintrs) 708 return 0; 709 710 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 711 if (eintrs & EHCI_STS_IAA) { 712 DPRINTF("door bell", 0, 0, 0, 0); 713 kpreempt_disable(); 714 KASSERT(sc->sc_doorbell_si != NULL); 715 softint_schedule(sc->sc_doorbell_si); 716 kpreempt_enable(); 717 eintrs &= ~EHCI_STS_IAA; 718 } 719 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 720 DPRINTF("INT=%d ERRINT=%d", 721 eintrs & EHCI_STS_INT ? 1 : 0, 722 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 723 usb_schedsoftintr(&sc->sc_bus); 724 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 725 } 726 if (eintrs & EHCI_STS_HSE) { 727 printf("%s: unrecoverable error, controller halted\n", 728 device_xname(sc->sc_dev)); 729 /* XXX what else */ 730 } 731 if (eintrs & EHCI_STS_PCD) { 732 kpreempt_disable(); 733 KASSERT(sc->sc_pcd_si != NULL); 734 softint_schedule(sc->sc_pcd_si); 735 kpreempt_enable(); 736 eintrs &= ~EHCI_STS_PCD; 737 } 738 739 if (eintrs != 0) { 740 /* Block unprocessed interrupts. */ 741 sc->sc_eintrs &= ~eintrs; 742 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 743 printf("%s: blocking intrs 0x%x\n", 744 device_xname(sc->sc_dev), eintrs); 745 } 746 747 return 1; 748 } 749 750 Static void 751 ehci_doorbell(void *addr) 752 { 753 ehci_softc_t *sc = addr; 754 755 mutex_enter(&sc->sc_lock); 756 cv_broadcast(&sc->sc_doorbell); 757 mutex_exit(&sc->sc_lock); 758 } 759 760 Static void 761 ehci_pcd(void *addr) 762 { 763 ehci_softc_t *sc = addr; 764 struct usbd_xfer *xfer; 765 u_char *p; 766 int i, m; 767 768 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 769 770 mutex_enter(&sc->sc_lock); 771 xfer = sc->sc_intrxfer; 772 773 if (xfer == NULL) { 774 /* Just ignore the change. */ 775 goto done; 776 } 777 778 p = xfer->ux_buf; 779 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 780 memset(p, 0, xfer->ux_length); 781 for (i = 1; i <= m; i++) { 782 /* Pick out CHANGE bits from the status reg. */ 783 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 784 p[i/8] |= 1 << (i%8); 785 if (i % 8 == 7) 786 DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); 787 } 788 xfer->ux_actlen = xfer->ux_length; 789 xfer->ux_status = USBD_NORMAL_COMPLETION; 790 791 usb_transfer_complete(xfer); 792 793 done: 794 mutex_exit(&sc->sc_lock); 795 } 796 797 Static void 798 ehci_softintr(void *v) 799 { 800 struct usbd_bus *bus = v; 801 ehci_softc_t *sc = EHCI_BUS2SC(bus); 802 struct ehci_xfer *ex, *nextex; 803 804 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 805 806 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 807 808 ex_completeq_t cq; 809 TAILQ_INIT(&cq); 810 811 /* 812 * The only explanation I can think of for why EHCI is as brain dead 813 * as UHCI interrupt-wise is that Intel was involved in both. 814 * An interrupt just tells us that something is done, we have no 815 * clue what, so we need to scan through all active transfers. :-( 816 */ 817 818 /* 819 * ehci_idone will remove transfer from sc->sc_intrhead if it's 820 * complete and add to our cq list 821 * 822 */ 823 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 824 switch (ex->ex_type) { 825 case EX_CTRL: 826 case EX_BULK: 827 case EX_INTR: 828 ehci_check_qh_intr(sc, ex, &cq); 829 break; 830 case EX_ISOC: 831 ehci_check_itd_intr(sc, ex, &cq); 832 break; 833 case EX_FS_ISOC: 834 ehci_check_sitd_intr(sc, ex, &cq); 835 break; 836 default: 837 KASSERT(false); 838 } 839 840 } 841 842 /* 843 * We abuse ex_next for the interrupt and complete lists and 844 * interrupt transfers will get re-added here so use 845 * the _SAFE version of TAILQ_FOREACH. 846 */ 847 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 848 usb_transfer_complete(&ex->ex_xfer); 849 } 850 851 /* Schedule a callout to catch any dropped transactions. */ 852 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 853 !TAILQ_EMPTY(&sc->sc_intrhead)) 854 callout_reset(&sc->sc_tmo_intrlist, 855 hz, ehci_intrlist_timeout, sc); 856 857 if (sc->sc_softwake) { 858 sc->sc_softwake = 0; 859 cv_broadcast(&sc->sc_softwake_cv); 860 } 861 } 862 863 Static void 864 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 865 { 866 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 867 uint32_t status; 868 869 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 870 871 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 872 873 if (ex->ex_type == EX_CTRL) { 874 fsqtd = ex->ex_setup; 875 lsqtd = ex->ex_status; 876 } else { 877 fsqtd = ex->ex_sqtdstart; 878 lsqtd = ex->ex_sqtdend; 879 } 880 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 881 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 882 883 /* 884 * If the last TD is still active we need to check whether there 885 * is an error somewhere in the middle, or whether there was a 886 * short packet (SPD and not ACTIVE). 887 */ 888 usb_syncmem(&lsqtd->dma, 889 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 890 sizeof(lsqtd->qtd.qtd_status), 891 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 892 status = le32toh(lsqtd->qtd.qtd_status); 893 usb_syncmem(&lsqtd->dma, 894 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 895 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 896 if (status & EHCI_QTD_ACTIVE) { 897 DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); 898 899 /* last qTD has already been checked */ 900 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 901 usb_syncmem(&sqtd->dma, 902 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 903 sizeof(sqtd->qtd.qtd_status), 904 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 905 status = le32toh(sqtd->qtd.qtd_status); 906 usb_syncmem(&sqtd->dma, 907 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 908 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 909 /* If there's an active QTD the xfer isn't done. */ 910 if (status & EHCI_QTD_ACTIVE) 911 break; 912 /* Any kind of error makes the xfer done. */ 913 if (status & EHCI_QTD_HALTED) 914 goto done; 915 /* Handle short packets */ 916 if (EHCI_QTD_GET_BYTES(status) != 0) { 917 /* 918 * If we get here for a control transfer then 919 * we need to let the hardware complete the 920 * status phase. That is, we're not done 921 * quite yet. 922 * 923 * Otherwise, we're done. 924 */ 925 if (ex->ex_type == EX_CTRL) { 926 break; 927 } 928 goto done; 929 } 930 } 931 DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, 932 0, 0); 933 #ifdef EHCI_DEBUG 934 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 935 ehci_dump_sqtds(ex->ex_sqtdstart); 936 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 937 #endif 938 return; 939 } 940 done: 941 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 942 callout_stop(&ex->ex_xfer.ux_callout); 943 ehci_idone(ex, cq); 944 } 945 946 Static void 947 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 948 { 949 ehci_soft_itd_t *itd; 950 int i; 951 952 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 953 954 KASSERT(mutex_owned(&sc->sc_lock)); 955 956 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 957 return; 958 959 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 960 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 961 962 itd = ex->ex_itdend; 963 964 /* 965 * check no active transfers in last itd, meaning we're finished 966 */ 967 968 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 969 sizeof(itd->itd.itd_ctl), 970 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 971 972 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 973 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 974 break; 975 } 976 977 if (i == EHCI_ITD_NUFRAMES) { 978 goto done; /* All 8 descriptors inactive, it's done */ 979 } 980 981 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 982 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 983 984 DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); 985 return; 986 done: 987 DPRINTF("ex %p done", ex, 0, 0, 0); 988 callout_stop(&ex->ex_xfer.ux_callout); 989 ehci_idone(ex, cq); 990 } 991 992 void 993 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 994 { 995 ehci_soft_sitd_t *sitd; 996 997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 998 999 KASSERT(mutex_owned(&sc->sc_lock)); 1000 1001 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1002 return; 1003 1004 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1005 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1006 1007 sitd = ex->ex_sitdend; 1008 1009 /* 1010 * check no active transfers in last sitd, meaning we're finished 1011 */ 1012 1013 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1014 sizeof(sitd->sitd.sitd_trans), 1015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1016 1017 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1021 1022 if (active) 1023 return; 1024 1025 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 1026 callout_stop(&(ex->ex_xfer.ux_callout)); 1027 ehci_idone(ex, cq); 1028 } 1029 1030 1031 Static void 1032 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1033 { 1034 struct usbd_xfer *xfer = &ex->ex_xfer; 1035 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1036 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1037 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1038 uint32_t status = 0, nstatus = 0; 1039 int actlen = 0; 1040 1041 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1042 1043 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1044 1045 DPRINTF("ex=%p", ex, 0, 0, 0); 1046 1047 if (xfer->ux_status == USBD_CANCELLED || 1048 xfer->ux_status == USBD_TIMEOUT) { 1049 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1050 return; 1051 } 1052 1053 #ifdef DIAGNOSTIC 1054 #ifdef EHCI_DEBUG 1055 if (ex->ex_isdone) { 1056 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1057 ehci_dump_exfer(ex); 1058 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1059 } 1060 #endif 1061 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1062 ex->ex_type, xfer->ux_status); 1063 ex->ex_isdone = true; 1064 #endif 1065 1066 DPRINTF("xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1067 1068 /* The transfer is done, compute actual length and status. */ 1069 if (ex->ex_type == EX_ISOC) { 1070 /* HS isoc transfer */ 1071 1072 struct ehci_soft_itd *itd; 1073 int i, nframes, len, uframes; 1074 1075 nframes = 0; 1076 1077 #ifdef EHCI_DEBUG 1078 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1079 ehci_dump_itds(ex->ex_itdstart); 1080 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1081 #endif 1082 1083 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1084 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1085 1086 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1087 usb_syncmem(&itd->dma, 1088 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1089 sizeof(itd->itd.itd_ctl), 1090 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1091 1092 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1093 /* 1094 * XXX - driver didn't fill in the frame full 1095 * of uframes. This leads to scheduling 1096 * inefficiencies, but working around 1097 * this doubles complexity of tracking 1098 * an xfer. 1099 */ 1100 if (nframes >= xfer->ux_nframes) 1101 break; 1102 1103 status = le32toh(itd->itd.itd_ctl[i]); 1104 len = EHCI_ITD_GET_LEN(status); 1105 if (EHCI_ITD_GET_STATUS(status) != 0) 1106 len = 0; /*No valid data on error*/ 1107 1108 xfer->ux_frlengths[nframes++] = len; 1109 actlen += len; 1110 } 1111 usb_syncmem(&itd->dma, 1112 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1113 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1114 1115 if (nframes >= xfer->ux_nframes) 1116 break; 1117 } 1118 1119 xfer->ux_actlen = actlen; 1120 xfer->ux_status = USBD_NORMAL_COMPLETION; 1121 goto end; 1122 } else if (ex->ex_type == EX_FS_ISOC) { 1123 /* FS isoc transfer */ 1124 struct ehci_soft_sitd *sitd; 1125 int nframes, len; 1126 1127 nframes = 0; 1128 1129 for (sitd = ex->ex_sitdstart; sitd != NULL; 1130 sitd = sitd->xfer_next) { 1131 usb_syncmem(&sitd->dma, 1132 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1133 sizeof(sitd->sitd.sitd_trans), 1134 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1135 1136 /* 1137 * XXX - driver didn't fill in the frame full 1138 * of uframes. This leads to scheduling 1139 * inefficiencies, but working around 1140 * this doubles complexity of tracking 1141 * an xfer. 1142 */ 1143 if (nframes >= xfer->ux_nframes) 1144 break; 1145 1146 status = le32toh(sitd->sitd.sitd_trans); 1147 usb_syncmem(&sitd->dma, 1148 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1149 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1150 1151 len = EHCI_SITD_GET_LEN(status); 1152 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1153 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1154 /* No valid data on error */ 1155 len = xfer->ux_frlengths[nframes]; 1156 } 1157 1158 /* 1159 * frlengths[i]: # of bytes to send 1160 * len: # of bytes host didn't send 1161 */ 1162 xfer->ux_frlengths[nframes] -= len; 1163 /* frlengths[i]: # of bytes host sent */ 1164 actlen += xfer->ux_frlengths[nframes++]; 1165 1166 if (nframes >= xfer->ux_nframes) 1167 break; 1168 } 1169 1170 xfer->ux_actlen = actlen; 1171 xfer->ux_status = USBD_NORMAL_COMPLETION; 1172 goto end; 1173 } 1174 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1175 ex->ex_type == EX_BULK); 1176 1177 /* Continue processing xfers using queue heads */ 1178 if (ex->ex_type == EX_CTRL) { 1179 fsqtd = ex->ex_setup; 1180 lsqtd = ex->ex_status; 1181 } else { 1182 fsqtd = ex->ex_sqtdstart; 1183 lsqtd = ex->ex_sqtdend; 1184 } 1185 #ifdef EHCI_DEBUG 1186 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1187 ehci_dump_sqtds(fsqtd); 1188 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1189 #endif 1190 1191 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1192 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1193 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1194 nstatus = le32toh(sqtd->qtd.qtd_status); 1195 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1196 BUS_DMASYNC_PREREAD); 1197 if (nstatus & EHCI_QTD_ACTIVE) 1198 break; 1199 1200 status = nstatus; 1201 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1202 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1203 } 1204 1205 /* 1206 * If there are left over TDs we need to update the toggle. 1207 * The default pipe doesn't need it since control transfers 1208 * start the toggle at 0 every time. 1209 * For a short transfer we need to update the toggle for the missing 1210 * packets within the qTD. 1211 */ 1212 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1213 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1214 DPRINTF("toggle update status=0x%08x nstatus=0x%08x", 1215 status, nstatus, 0, 0); 1216 #if 0 1217 ehci_dump_sqh(epipe->sqh); 1218 ehci_dump_sqtds(ex->ex_sqtdstart); 1219 #endif 1220 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1221 } 1222 1223 DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, 1224 status, 0); 1225 xfer->ux_actlen = actlen; 1226 if (status & EHCI_QTD_HALTED) { 1227 #ifdef EHCI_DEBUG 1228 DPRINTF("halted addr=%d endpt=0x%02x", 1229 xfer->ux_pipe->up_dev->ud_addr, 1230 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1231 0, 0); 1232 DPRINTF("cerr=%d pid=%d", 1233 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1234 0, 0); 1235 DPRINTF("active =%d halted=%d buferr=%d babble=%d", 1236 status & EHCI_QTD_ACTIVE ? 1 : 0, 1237 status & EHCI_QTD_HALTED ? 1 : 0, 1238 status & EHCI_QTD_BUFERR ? 1 : 0, 1239 status & EHCI_QTD_BABBLE ? 1 : 0); 1240 1241 DPRINTF("xacterr=%d missed=%d split =%d ping =%d", 1242 status & EHCI_QTD_XACTERR ? 1 : 0, 1243 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1244 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1245 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1246 1247 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1248 ehci_dump_sqh(epipe->sqh); 1249 ehci_dump_sqtds(ex->ex_sqtdstart); 1250 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1251 #endif 1252 /* low&full speed has an extra error flag */ 1253 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1254 EHCI_QH_SPEED_HIGH) 1255 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1256 else 1257 status &= EHCI_QTD_STATERRS; 1258 if (status == 0) /* no other errors means a stall */ { 1259 xfer->ux_status = USBD_STALLED; 1260 } else { 1261 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1262 } 1263 /* XXX need to reset TT on missed microframe */ 1264 if (status & EHCI_QTD_MISSEDMICRO) { 1265 printf("%s: missed microframe, TT reset not " 1266 "implemented, hub might be inoperational\n", 1267 device_xname(sc->sc_dev)); 1268 } 1269 } else { 1270 xfer->ux_status = USBD_NORMAL_COMPLETION; 1271 } 1272 1273 end: 1274 1275 ehci_del_intr_list(sc, ex); 1276 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1277 1278 DPRINTF("ex=%p done", ex, 0, 0, 0); 1279 } 1280 1281 Static void 1282 ehci_poll(struct usbd_bus *bus) 1283 { 1284 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1285 1286 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1287 1288 #ifdef EHCI_DEBUG 1289 static int last; 1290 int new; 1291 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1292 if (new != last) { 1293 DPRINTF("intrs=0x%04x", new, 0, 0, 0); 1294 last = new; 1295 } 1296 #endif 1297 1298 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1299 mutex_spin_enter(&sc->sc_intr_lock); 1300 ehci_intr1(sc); 1301 mutex_spin_exit(&sc->sc_intr_lock); 1302 } 1303 } 1304 1305 void 1306 ehci_childdet(device_t self, device_t child) 1307 { 1308 struct ehci_softc *sc = device_private(self); 1309 1310 KASSERT(sc->sc_child == child); 1311 sc->sc_child = NULL; 1312 } 1313 1314 int 1315 ehci_detach(struct ehci_softc *sc, int flags) 1316 { 1317 int rv = 0; 1318 1319 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1320 1321 if (sc->sc_child != NULL) 1322 rv = config_detach(sc->sc_child, flags); 1323 1324 if (rv != 0) 1325 return rv; 1326 1327 callout_halt(&sc->sc_tmo_intrlist, NULL); 1328 callout_destroy(&sc->sc_tmo_intrlist); 1329 1330 /* XXX free other data structures XXX */ 1331 if (sc->sc_softitds) 1332 kmem_free(sc->sc_softitds, 1333 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1334 cv_destroy(&sc->sc_doorbell); 1335 cv_destroy(&sc->sc_softwake_cv); 1336 1337 #if 0 1338 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1339 1340 softint_disestablish(sc->sc_doorbell_si); 1341 softint_disestablish(sc->sc_pcd_si); 1342 1343 mutex_destroy(&sc->sc_lock); 1344 mutex_destroy(&sc->sc_intr_lock); 1345 #endif 1346 1347 pool_cache_destroy(sc->sc_xferpool); 1348 1349 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1350 1351 return rv; 1352 } 1353 1354 1355 int 1356 ehci_activate(device_t self, enum devact act) 1357 { 1358 struct ehci_softc *sc = device_private(self); 1359 1360 switch (act) { 1361 case DVACT_DEACTIVATE: 1362 sc->sc_dying = 1; 1363 return 0; 1364 default: 1365 return EOPNOTSUPP; 1366 } 1367 } 1368 1369 /* 1370 * Handle suspend/resume. 1371 * 1372 * We need to switch to polling mode here, because this routine is 1373 * called from an interrupt context. This is all right since we 1374 * are almost suspended anyway. 1375 * 1376 * Note that this power handler isn't to be registered directly; the 1377 * bus glue needs to call out to it. 1378 */ 1379 bool 1380 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1381 { 1382 ehci_softc_t *sc = device_private(dv); 1383 int i; 1384 uint32_t cmd, hcr; 1385 1386 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1387 1388 mutex_spin_enter(&sc->sc_intr_lock); 1389 sc->sc_bus.ub_usepolling++; 1390 mutex_spin_exit(&sc->sc_intr_lock); 1391 1392 for (i = 1; i <= sc->sc_noport; i++) { 1393 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1394 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1395 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1396 } 1397 1398 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1399 1400 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1401 EOWRITE4(sc, EHCI_USBCMD, cmd); 1402 1403 for (i = 0; i < 100; i++) { 1404 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1405 if (hcr == 0) 1406 break; 1407 1408 usb_delay_ms(&sc->sc_bus, 1); 1409 } 1410 if (hcr != 0) 1411 printf("%s: reset timeout\n", device_xname(dv)); 1412 1413 cmd &= ~EHCI_CMD_RS; 1414 EOWRITE4(sc, EHCI_USBCMD, cmd); 1415 1416 for (i = 0; i < 100; i++) { 1417 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1418 if (hcr == EHCI_STS_HCH) 1419 break; 1420 1421 usb_delay_ms(&sc->sc_bus, 1); 1422 } 1423 if (hcr != EHCI_STS_HCH) 1424 printf("%s: config timeout\n", device_xname(dv)); 1425 1426 mutex_spin_enter(&sc->sc_intr_lock); 1427 sc->sc_bus.ub_usepolling--; 1428 mutex_spin_exit(&sc->sc_intr_lock); 1429 1430 return true; 1431 } 1432 1433 bool 1434 ehci_resume(device_t dv, const pmf_qual_t *qual) 1435 { 1436 ehci_softc_t *sc = device_private(dv); 1437 int i; 1438 uint32_t cmd, hcr; 1439 1440 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1441 1442 /* restore things in case the bios sucks */ 1443 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1444 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1445 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1446 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1447 1448 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1449 1450 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1451 1452 hcr = 0; 1453 for (i = 1; i <= sc->sc_noport; i++) { 1454 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1455 if ((cmd & EHCI_PS_PO) == 0 && 1456 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1457 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1458 hcr = 1; 1459 } 1460 } 1461 1462 if (hcr) { 1463 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1464 1465 for (i = 1; i <= sc->sc_noport; i++) { 1466 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1467 if ((cmd & EHCI_PS_PO) == 0 && 1468 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1469 EOWRITE4(sc, EHCI_PORTSC(i), 1470 cmd & ~EHCI_PS_FPR); 1471 } 1472 } 1473 1474 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1475 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1476 1477 for (i = 0; i < 100; i++) { 1478 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1479 if (hcr != EHCI_STS_HCH) 1480 break; 1481 1482 usb_delay_ms(&sc->sc_bus, 1); 1483 } 1484 if (hcr == EHCI_STS_HCH) 1485 printf("%s: config timeout\n", device_xname(dv)); 1486 1487 return true; 1488 } 1489 1490 /* 1491 * Shut down the controller when the system is going down. 1492 */ 1493 bool 1494 ehci_shutdown(device_t self, int flags) 1495 { 1496 ehci_softc_t *sc = device_private(self); 1497 1498 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1499 1500 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1501 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1502 return true; 1503 } 1504 1505 Static struct usbd_xfer * 1506 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1507 { 1508 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1509 struct usbd_xfer *xfer; 1510 1511 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1512 if (xfer != NULL) { 1513 memset(xfer, 0, sizeof(struct ehci_xfer)); 1514 #ifdef DIAGNOSTIC 1515 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1516 ex->ex_isdone = true; 1517 xfer->ux_state = XFER_BUSY; 1518 #endif 1519 } 1520 return xfer; 1521 } 1522 1523 Static void 1524 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1525 { 1526 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1527 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1528 1529 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1530 xfer->ux_state); 1531 KASSERT(ex->ex_isdone); 1532 1533 #ifdef DIAGNOSTIC 1534 xfer->ux_state = XFER_FREE; 1535 #endif 1536 1537 pool_cache_put(sc->sc_xferpool, xfer); 1538 } 1539 1540 Static void 1541 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1542 { 1543 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1544 1545 *lock = &sc->sc_lock; 1546 } 1547 1548 Static void 1549 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1550 { 1551 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1552 1553 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1554 1555 DPRINTF("epipe=%p status=0x%08x", epipe, 1556 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1557 #ifdef EHCI_DEBUG 1558 if (ehcidebug) 1559 usbd_dump_pipe(pipe); 1560 #endif 1561 epipe->nexttoggle = 0; 1562 } 1563 1564 Static void 1565 ehci_noop(struct usbd_pipe *pipe) 1566 { 1567 } 1568 1569 #ifdef EHCI_DEBUG 1570 /* 1571 * Unused function - this is meant to be called from a kernel 1572 * debugger. 1573 */ 1574 void 1575 ehci_dump(void) 1576 { 1577 ehci_softc_t *sc = theehci; 1578 int i; 1579 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1580 EOREAD4(sc, EHCI_USBCMD), 1581 EOREAD4(sc, EHCI_USBSTS), 1582 EOREAD4(sc, EHCI_USBINTR)); 1583 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1584 EOREAD4(sc, EHCI_FRINDEX), 1585 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1586 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1587 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1588 for (i = 1; i <= sc->sc_noport; i++) 1589 printf("port %d status=0x%08x\n", i, 1590 EOREAD4(sc, EHCI_PORTSC(i))); 1591 } 1592 1593 Static void 1594 ehci_dump_regs(ehci_softc_t *sc) 1595 { 1596 int i; 1597 1598 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1599 1600 DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1601 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1602 EOREAD4(sc, EHCI_USBINTR), 0); 1603 DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1604 "async = 0x%08x", 1605 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1606 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1607 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1608 for (i = 1; i <= sc->sc_noport; i += 2) { 1609 if (i == sc->sc_noport) { 1610 DPRINTF("port %d status = 0x%08x", i, 1611 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1612 } else { 1613 DPRINTF( 1614 "port %d status = 0x%08x port %d status = 0x%08x", 1615 i, EOREAD4(sc, EHCI_PORTSC(i)), 1616 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1617 } 1618 } 1619 } 1620 1621 #define ehci_dump_link(link, type) do { \ 1622 DPRINTF(" link 0x%08x (T = %d):", \ 1623 link, \ 1624 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1625 if (type) { \ 1626 DPRINTF( \ 1627 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1628 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1629 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1630 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1631 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1632 } \ 1633 } while(0) 1634 1635 Static void 1636 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1637 { 1638 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1639 int i; 1640 uint32_t stop = 0; 1641 1642 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1643 ehci_dump_sqtd(sqtd); 1644 usb_syncmem(&sqtd->dma, 1645 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1646 sizeof(sqtd->qtd), 1647 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1648 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1649 usb_syncmem(&sqtd->dma, 1650 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1651 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1652 } 1653 if (!stop) 1654 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1655 } 1656 1657 Static void 1658 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1659 { 1660 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1661 1662 usb_syncmem(&sqtd->dma, sqtd->offs, 1663 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1664 1665 DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1666 ehci_dump_qtd(&sqtd->qtd); 1667 1668 usb_syncmem(&sqtd->dma, sqtd->offs, 1669 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1670 } 1671 1672 Static void 1673 ehci_dump_qtd(ehci_qtd_t *qtd) 1674 { 1675 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1676 uint32_t s = le32toh(qtd->qtd_status); 1677 1678 DPRINTFN(10, 1679 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1680 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1681 DPRINTFN(10, 1682 " toggle = %d ioc = %d bytes = %#x " 1683 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1684 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1685 DPRINTFN(10, 1686 " cerr = %d pid = %d stat = %x", 1687 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1688 0); 1689 DPRINTFN(10, 1690 "active =%d halted=%d buferr=%d babble=%d", 1691 s & EHCI_QTD_ACTIVE ? 1 : 0, 1692 s & EHCI_QTD_HALTED ? 1 : 0, 1693 s & EHCI_QTD_BUFERR ? 1 : 0, 1694 s & EHCI_QTD_BABBLE ? 1 : 0); 1695 DPRINTFN(10, 1696 "xacterr=%d missed=%d split =%d ping =%d", 1697 s & EHCI_QTD_XACTERR ? 1 : 0, 1698 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1699 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1700 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1701 DPRINTFN(10, 1702 "buffer[0] = %#x buffer[1] = %#x " 1703 "buffer[2] = %#x buffer[3] = %#x", 1704 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1705 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1706 DPRINTFN(10, 1707 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1708 } 1709 1710 Static void 1711 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1712 { 1713 ehci_qh_t *qh = &sqh->qh; 1714 ehci_link_t link; 1715 uint32_t endp, endphub; 1716 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1717 1718 usb_syncmem(&sqh->dma, sqh->offs, 1719 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1720 1721 DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1722 link = le32toh(qh->qh_link); 1723 ehci_dump_link(link, true); 1724 1725 endp = le32toh(qh->qh_endp); 1726 DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); 1727 DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", 1728 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1729 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1730 DPRINTFN(10, " dtc = %d hrecl = %d", 1731 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1732 DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", 1733 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1734 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1735 1736 endphub = le32toh(qh->qh_endphub); 1737 DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); 1738 DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", 1739 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1740 DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", 1741 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1742 EHCI_QH_GET_MULT(endphub), 0); 1743 1744 link = le32toh(qh->qh_curqtd); 1745 ehci_dump_link(link, false); 1746 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1747 ehci_dump_qtd(&qh->qh_qtd); 1748 1749 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1750 BUS_DMASYNC_PREREAD); 1751 } 1752 1753 Static void 1754 ehci_dump_itds(ehci_soft_itd_t *itd) 1755 { 1756 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1757 int i; 1758 uint32_t stop = 0; 1759 1760 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1761 ehci_dump_itd(itd); 1762 usb_syncmem(&itd->dma, 1763 itd->offs + offsetof(ehci_itd_t, itd_next), 1764 sizeof(itd->itd), 1765 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1766 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1767 usb_syncmem(&itd->dma, 1768 itd->offs + offsetof(ehci_itd_t, itd_next), 1769 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1770 } 1771 if (!stop) 1772 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1773 } 1774 1775 Static void 1776 ehci_dump_itd(struct ehci_soft_itd *itd) 1777 { 1778 ehci_isoc_trans_t t; 1779 ehci_isoc_bufr_ptr_t b, b2, b3; 1780 int i; 1781 1782 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1783 1784 DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); 1785 1786 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1787 t = le32toh(itd->itd.itd_ctl[i]); 1788 DPRINTF("ITDctl %d: stat = %x len = %x", 1789 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1790 DPRINTF(" ioc = %x pg = %x offs = %x", 1791 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1792 EHCI_ITD_GET_OFFS(t), 0); 1793 } 1794 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1795 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1796 DPRINTF(" %x", 1797 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1798 1799 b = le32toh(itd->itd.itd_bufr[0]); 1800 b2 = le32toh(itd->itd.itd_bufr[1]); 1801 b3 = le32toh(itd->itd.itd_bufr[2]); 1802 DPRINTF(" ep = %x daddr = %x dir = %d", 1803 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1804 DPRINTF(" maxpkt = %x multi = %x", 1805 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1806 } 1807 1808 Static void 1809 ehci_dump_sitd(struct ehci_soft_itd *itd) 1810 { 1811 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1812 1813 DPRINTF("SITD %p next = %p prev = %p", 1814 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1815 DPRINTF(" xfernext=%p physaddr=%X slot=%d", 1816 itd->xfer_next, itd->physaddr, itd->slot, 0); 1817 } 1818 1819 Static void 1820 ehci_dump_exfer(struct ehci_xfer *ex) 1821 { 1822 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1823 1824 DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, 1825 ex->ex_isdone, 0); 1826 1827 switch (ex->ex_type) { 1828 case EX_CTRL: 1829 DPRINTF(" setup = %p data = %p status = %p", 1830 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1831 break; 1832 case EX_BULK: 1833 case EX_INTR: 1834 DPRINTF(" qtdstart = %p qtdend = %p", 1835 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1836 break; 1837 case EX_ISOC: 1838 DPRINTF(" itdstart = %p itdend = %p", 1839 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1840 break; 1841 case EX_FS_ISOC: 1842 DPRINTF(" sitdstart = %p sitdend = %p", 1843 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1844 break; 1845 default: 1846 DPRINTF(" unknown type", 0, 0, 0, 0); 1847 } 1848 } 1849 #endif 1850 1851 Static usbd_status 1852 ehci_open(struct usbd_pipe *pipe) 1853 { 1854 struct usbd_device *dev = pipe->up_dev; 1855 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1856 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1857 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1858 uint8_t addr = dev->ud_addr; 1859 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1860 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1861 ehci_soft_qh_t *sqh; 1862 usbd_status err; 1863 int ival, speed, naks; 1864 int hshubaddr, hshubport; 1865 1866 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1867 1868 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1869 ed->bEndpointAddress, rhaddr); 1870 1871 if (dev->ud_myhsport) { 1872 /* 1873 * When directly attached FS/LS device while doing embedded 1874 * transaction translations and we are the hub, set the hub 1875 * address to 0 (us). 1876 */ 1877 if (!(sc->sc_flags & EHCIF_ETTF) 1878 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1879 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1880 } else { 1881 hshubaddr = 0; 1882 } 1883 hshubport = dev->ud_myhsport->up_portno; 1884 } else { 1885 hshubaddr = 0; 1886 hshubport = 0; 1887 } 1888 1889 if (sc->sc_dying) 1890 return USBD_IOERROR; 1891 1892 /* toggle state needed for bulk endpoints */ 1893 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1894 1895 if (addr == rhaddr) { 1896 switch (ed->bEndpointAddress) { 1897 case USB_CONTROL_ENDPOINT: 1898 pipe->up_methods = &roothub_ctrl_methods; 1899 break; 1900 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1901 pipe->up_methods = &ehci_root_intr_methods; 1902 break; 1903 default: 1904 DPRINTF("bad bEndpointAddress 0x%02x", 1905 ed->bEndpointAddress, 0, 0, 0); 1906 return USBD_INVAL; 1907 } 1908 return USBD_NORMAL_COMPLETION; 1909 } 1910 1911 /* XXX All this stuff is only valid for async. */ 1912 switch (dev->ud_speed) { 1913 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1914 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1915 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1916 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1917 } 1918 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1919 DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, 1920 0); 1921 return USBD_INVAL; 1922 } 1923 1924 /* 1925 * For interrupt transfer, nak throttling must be disabled, but for 1926 * the other transfer type, nak throttling should be enabled from the 1927 * viewpoint that avoids the memory thrashing. 1928 */ 1929 naks = (xfertype == UE_INTERRUPT) ? 0 1930 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1931 1932 /* Allocate sqh for everything, save isoc xfers */ 1933 if (xfertype != UE_ISOCHRONOUS) { 1934 sqh = ehci_alloc_sqh(sc); 1935 if (sqh == NULL) 1936 return USBD_NOMEM; 1937 /* qh_link filled when the QH is added */ 1938 sqh->qh.qh_endp = htole32( 1939 EHCI_QH_SET_ADDR(addr) | 1940 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1941 EHCI_QH_SET_EPS(speed) | 1942 EHCI_QH_DTC | 1943 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1944 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1945 EHCI_QH_CTL : 0) | 1946 EHCI_QH_SET_NRL(naks) 1947 ); 1948 sqh->qh.qh_endphub = htole32( 1949 EHCI_QH_SET_MULT(1) | 1950 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1951 ); 1952 if (speed != EHCI_QH_SPEED_HIGH) 1953 sqh->qh.qh_endphub |= htole32( 1954 EHCI_QH_SET_PORT(hshubport) | 1955 EHCI_QH_SET_HUBA(hshubaddr) | 1956 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1957 ); 1958 sqh->qh.qh_curqtd = EHCI_NULL; 1959 /* Fill the overlay qTD */ 1960 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1961 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1962 sqh->qh.qh_qtd.qtd_status = htole32(0); 1963 1964 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1965 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1966 epipe->sqh = sqh; 1967 } else { 1968 sqh = NULL; 1969 } /*xfertype == UE_ISOC*/ 1970 1971 switch (xfertype) { 1972 case UE_CONTROL: 1973 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1974 0, &epipe->ctrl.reqdma); 1975 #ifdef EHCI_DEBUG 1976 if (err) 1977 printf("ehci_open: usb_allocmem()=%d\n", err); 1978 #endif 1979 if (err) 1980 goto bad; 1981 pipe->up_methods = &ehci_device_ctrl_methods; 1982 mutex_enter(&sc->sc_lock); 1983 ehci_add_qh(sc, sqh, sc->sc_async_head); 1984 mutex_exit(&sc->sc_lock); 1985 break; 1986 case UE_BULK: 1987 pipe->up_methods = &ehci_device_bulk_methods; 1988 mutex_enter(&sc->sc_lock); 1989 ehci_add_qh(sc, sqh, sc->sc_async_head); 1990 mutex_exit(&sc->sc_lock); 1991 break; 1992 case UE_INTERRUPT: 1993 pipe->up_methods = &ehci_device_intr_methods; 1994 ival = pipe->up_interval; 1995 if (ival == USBD_DEFAULT_INTERVAL) { 1996 if (speed == EHCI_QH_SPEED_HIGH) { 1997 if (ed->bInterval > 16) { 1998 /* 1999 * illegal with high-speed, but there 2000 * were documentation bugs in the spec, 2001 * so be generous 2002 */ 2003 ival = 256; 2004 } else 2005 ival = (1 << (ed->bInterval - 1)) / 8; 2006 } else 2007 ival = ed->bInterval; 2008 } 2009 err = ehci_device_setintr(sc, sqh, ival); 2010 if (err) 2011 goto bad; 2012 break; 2013 case UE_ISOCHRONOUS: 2014 pipe->up_serialise = false; 2015 if (speed == EHCI_QH_SPEED_HIGH) 2016 pipe->up_methods = &ehci_device_isoc_methods; 2017 else 2018 pipe->up_methods = &ehci_device_fs_isoc_methods; 2019 if (ed->bInterval == 0 || ed->bInterval > 16) { 2020 printf("ehci: opening pipe with invalid bInterval\n"); 2021 err = USBD_INVAL; 2022 goto bad; 2023 } 2024 if (UGETW(ed->wMaxPacketSize) == 0) { 2025 printf("ehci: zero length endpoint open request\n"); 2026 err = USBD_INVAL; 2027 goto bad; 2028 } 2029 epipe->isoc.next_frame = 0; 2030 epipe->isoc.cur_xfers = 0; 2031 break; 2032 default: 2033 DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); 2034 err = USBD_INVAL; 2035 goto bad; 2036 } 2037 return USBD_NORMAL_COMPLETION; 2038 2039 bad: 2040 if (sqh != NULL) { 2041 mutex_enter(&sc->sc_lock); 2042 ehci_free_sqh(sc, sqh); 2043 mutex_exit(&sc->sc_lock); 2044 } 2045 return err; 2046 } 2047 2048 /* 2049 * Add an ED to the schedule. Called with USB lock held. 2050 */ 2051 Static void 2052 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2053 { 2054 2055 KASSERT(mutex_owned(&sc->sc_lock)); 2056 2057 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2058 2059 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2060 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2061 2062 sqh->next = head->next; 2063 sqh->qh.qh_link = head->qh.qh_link; 2064 2065 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2066 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2067 2068 head->next = sqh; 2069 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2070 2071 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2072 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2073 2074 #ifdef EHCI_DEBUG 2075 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2076 ehci_dump_sqh(sqh); 2077 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2078 #endif 2079 } 2080 2081 /* 2082 * Remove an ED from the schedule. Called with USB lock held. 2083 */ 2084 Static void 2085 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2086 { 2087 ehci_soft_qh_t *p; 2088 2089 KASSERT(mutex_owned(&sc->sc_lock)); 2090 2091 /* XXX */ 2092 for (p = head; p != NULL && p->next != sqh; p = p->next) 2093 ; 2094 if (p == NULL) 2095 panic("ehci_rem_qh: ED not found"); 2096 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2097 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2098 p->next = sqh->next; 2099 p->qh.qh_link = sqh->qh.qh_link; 2100 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2101 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2102 2103 ehci_sync_hc(sc); 2104 } 2105 2106 Static void 2107 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2108 { 2109 int i; 2110 uint32_t status; 2111 2112 /* Save toggle bit and ping status. */ 2113 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2114 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2115 status = sqh->qh.qh_qtd.qtd_status & 2116 htole32(EHCI_QTD_TOGGLE_MASK | 2117 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2118 /* Set HALTED to make hw leave it alone. */ 2119 sqh->qh.qh_qtd.qtd_status = 2120 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2121 usb_syncmem(&sqh->dma, 2122 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2123 sizeof(sqh->qh.qh_qtd.qtd_status), 2124 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2125 sqh->qh.qh_curqtd = 0; 2126 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2127 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2128 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2129 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2130 sqh->sqtd = sqtd; 2131 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2132 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2133 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2134 sqh->qh.qh_qtd.qtd_status = status; 2135 usb_syncmem(&sqh->dma, 2136 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2137 sizeof(sqh->qh.qh_qtd.qtd_status), 2138 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2139 } 2140 2141 /* 2142 * Ensure that the HC has released all references to the QH. We do this 2143 * by asking for a Async Advance Doorbell interrupt and then we wait for 2144 * the interrupt. 2145 * To make this easier we first obtain exclusive use of the doorbell. 2146 */ 2147 Static void 2148 ehci_sync_hc(ehci_softc_t *sc) 2149 { 2150 int error __diagused; 2151 2152 KASSERT(mutex_owned(&sc->sc_lock)); 2153 2154 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2155 2156 if (sc->sc_dying) { 2157 DPRINTF("dying", 0, 0, 0, 0); 2158 return; 2159 } 2160 /* ask for doorbell */ 2161 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2162 DPRINTF("cmd = 0x%08x sts = 0x%08x", 2163 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2164 2165 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2166 2167 DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", 2168 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2169 #ifdef DIAGNOSTIC 2170 if (error) 2171 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2172 #endif 2173 } 2174 2175 Static void 2176 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2177 { 2178 2179 KASSERT(mutex_owned(&sc->sc_lock)); 2180 2181 for (; itd != NULL; itd = itd->xfer_next) { 2182 struct ehci_soft_itd *prev = itd->frame_list.prev; 2183 2184 /* Unlink itd from hardware chain, or frame array */ 2185 if (prev == NULL) { /* We're at the table head */ 2186 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2187 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2188 usb_syncmem(&sc->sc_fldma, 2189 sizeof(ehci_link_t) * itd->slot, 2190 sizeof(ehci_link_t), 2191 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2192 2193 if (itd->frame_list.next != NULL) 2194 itd->frame_list.next->frame_list.prev = NULL; 2195 } else { 2196 /* XXX this part is untested... */ 2197 prev->itd.itd_next = itd->itd.itd_next; 2198 usb_syncmem(&itd->dma, 2199 itd->offs + offsetof(ehci_itd_t, itd_next), 2200 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2201 2202 prev->frame_list.next = itd->frame_list.next; 2203 if (itd->frame_list.next != NULL) 2204 itd->frame_list.next->frame_list.prev = prev; 2205 } 2206 } 2207 } 2208 2209 Static void 2210 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2211 { 2212 struct ehci_soft_itd *next; 2213 2214 mutex_enter(&sc->sc_lock); 2215 next = NULL; 2216 for (; itd != NULL; itd = next) { 2217 next = itd->xfer_next; 2218 ehci_free_itd_locked(sc, itd); 2219 } 2220 mutex_exit(&sc->sc_lock); 2221 } 2222 2223 Static void 2224 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2225 { 2226 2227 KASSERT(mutex_owned(&sc->sc_lock)); 2228 2229 for (; sitd != NULL; sitd = sitd->xfer_next) { 2230 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2231 2232 /* Unlink sitd from hardware chain, or frame array */ 2233 if (prev == NULL) { /* We're at the table head */ 2234 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2235 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2236 usb_syncmem(&sc->sc_fldma, 2237 sizeof(ehci_link_t) * sitd->slot, 2238 sizeof(ehci_link_t), 2239 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2240 2241 if (sitd->frame_list.next != NULL) 2242 sitd->frame_list.next->frame_list.prev = NULL; 2243 } else { 2244 /* XXX this part is untested... */ 2245 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2246 usb_syncmem(&sitd->dma, 2247 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2248 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2249 2250 prev->frame_list.next = sitd->frame_list.next; 2251 if (sitd->frame_list.next != NULL) 2252 sitd->frame_list.next->frame_list.prev = prev; 2253 } 2254 } 2255 } 2256 2257 Static void 2258 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2259 { 2260 2261 mutex_enter(&sc->sc_lock); 2262 struct ehci_soft_sitd *next = NULL; 2263 for (; sitd != NULL; sitd = next) { 2264 next = sitd->xfer_next; 2265 ehci_free_sitd_locked(sc, sitd); 2266 } 2267 mutex_exit(&sc->sc_lock); 2268 } 2269 2270 /***********/ 2271 2272 Static int 2273 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2274 void *buf, int buflen) 2275 { 2276 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2277 usb_hub_descriptor_t hubd; 2278 usb_port_status_t ps; 2279 uint16_t len, value, index; 2280 int l, totlen = 0; 2281 int port, i; 2282 uint32_t v; 2283 2284 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2285 2286 if (sc->sc_dying) 2287 return -1; 2288 2289 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, 2290 0, 0); 2291 2292 len = UGETW(req->wLength); 2293 value = UGETW(req->wValue); 2294 index = UGETW(req->wIndex); 2295 2296 #define C(x,y) ((x) | ((y) << 8)) 2297 switch (C(req->bRequest, req->bmRequestType)) { 2298 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2299 if (len == 0) 2300 break; 2301 switch (value) { 2302 case C(0, UDESC_DEVICE): { 2303 usb_device_descriptor_t devd; 2304 totlen = min(buflen, sizeof(devd)); 2305 memcpy(&devd, buf, totlen); 2306 USETW(devd.idVendor, sc->sc_id_vendor); 2307 memcpy(buf, &devd, totlen); 2308 break; 2309 2310 } 2311 #define sd ((usb_string_descriptor_t *)buf) 2312 case C(1, UDESC_STRING): 2313 /* Vendor */ 2314 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2315 break; 2316 case C(2, UDESC_STRING): 2317 /* Product */ 2318 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2319 break; 2320 #undef sd 2321 default: 2322 /* default from usbroothub */ 2323 return buflen; 2324 } 2325 break; 2326 2327 /* Hub requests */ 2328 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2329 break; 2330 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2331 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 2332 value, 0, 0); 2333 if (index < 1 || index > sc->sc_noport) { 2334 return -1; 2335 } 2336 port = EHCI_PORTSC(index); 2337 v = EOREAD4(sc, port); 2338 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2339 v &= ~EHCI_PS_CLEAR; 2340 switch (value) { 2341 case UHF_PORT_ENABLE: 2342 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2343 break; 2344 case UHF_PORT_SUSPEND: 2345 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2346 break; 2347 v &= ~EHCI_PS_SUSP; 2348 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2349 /* see USB2 spec ch. 7.1.7.7 */ 2350 usb_delay_ms(&sc->sc_bus, 20); 2351 EOWRITE4(sc, port, v); 2352 usb_delay_ms(&sc->sc_bus, 2); 2353 #ifdef DEBUG 2354 v = EOREAD4(sc, port); 2355 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2356 printf("ehci: resume failed: %x\n", v); 2357 #endif 2358 break; 2359 case UHF_PORT_POWER: 2360 if (sc->sc_hasppc) 2361 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2362 break; 2363 case UHF_PORT_TEST: 2364 DPRINTF("clear port test %d", index, 0, 0, 0); 2365 break; 2366 case UHF_PORT_INDICATOR: 2367 DPRINTF("clear port ind %d", index, 0, 0, 0); 2368 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2369 break; 2370 case UHF_C_PORT_CONNECTION: 2371 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2372 break; 2373 case UHF_C_PORT_ENABLE: 2374 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2375 break; 2376 case UHF_C_PORT_SUSPEND: 2377 /* how? */ 2378 break; 2379 case UHF_C_PORT_OVER_CURRENT: 2380 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2381 break; 2382 case UHF_C_PORT_RESET: 2383 sc->sc_isreset[index] = 0; 2384 break; 2385 default: 2386 return -1; 2387 } 2388 #if 0 2389 switch(value) { 2390 case UHF_C_PORT_CONNECTION: 2391 case UHF_C_PORT_ENABLE: 2392 case UHF_C_PORT_SUSPEND: 2393 case UHF_C_PORT_OVER_CURRENT: 2394 case UHF_C_PORT_RESET: 2395 default: 2396 break; 2397 } 2398 #endif 2399 break; 2400 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2401 if (len == 0) 2402 break; 2403 if ((value & 0xff) != 0) { 2404 return -1; 2405 } 2406 totlen = min(buflen, sizeof(hubd)); 2407 memcpy(&hubd, buf, totlen); 2408 hubd.bNbrPorts = sc->sc_noport; 2409 v = EOREAD4(sc, EHCI_HCSPARAMS); 2410 USETW(hubd.wHubCharacteristics, 2411 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2412 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2413 ? UHD_PORT_IND : 0); 2414 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2415 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2416 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2417 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2418 totlen = min(totlen, hubd.bDescLength); 2419 memcpy(buf, &hubd, totlen); 2420 break; 2421 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2422 if (len != 4) { 2423 return -1; 2424 } 2425 memset(buf, 0, len); /* ? XXX */ 2426 totlen = len; 2427 break; 2428 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2429 DPRINTF("get port status i=%d", index, 0, 0, 0); 2430 if (index < 1 || index > sc->sc_noport) { 2431 return -1; 2432 } 2433 if (len != 4) { 2434 return -1; 2435 } 2436 v = EOREAD4(sc, EHCI_PORTSC(index)); 2437 DPRINTF("port status=0x%04x", v, 0, 0, 0); 2438 2439 i = UPS_HIGH_SPEED; 2440 if (sc->sc_flags & EHCIF_ETTF) { 2441 /* 2442 * If we are doing embedded transaction translation, 2443 * then directly attached LS/FS devices are reset by 2444 * the EHCI controller itself. PSPD is encoded 2445 * the same way as in USBSTATUS. 2446 */ 2447 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2448 } 2449 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2450 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2451 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2452 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2453 if (v & EHCI_PS_PR) i |= UPS_RESET; 2454 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2455 if (sc->sc_vendor_port_status) 2456 i = sc->sc_vendor_port_status(sc, v, i); 2457 USETW(ps.wPortStatus, i); 2458 i = 0; 2459 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2460 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2461 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2462 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2463 USETW(ps.wPortChange, i); 2464 totlen = min(len, sizeof(ps)); 2465 memcpy(buf, &ps, totlen); 2466 break; 2467 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2468 return -1; 2469 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2470 break; 2471 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2472 if (index < 1 || index > sc->sc_noport) { 2473 return -1; 2474 } 2475 port = EHCI_PORTSC(index); 2476 v = EOREAD4(sc, port); 2477 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2478 v &= ~EHCI_PS_CLEAR; 2479 switch(value) { 2480 case UHF_PORT_ENABLE: 2481 EOWRITE4(sc, port, v | EHCI_PS_PE); 2482 break; 2483 case UHF_PORT_SUSPEND: 2484 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2485 break; 2486 case UHF_PORT_RESET: 2487 DPRINTF("reset port %d", index, 0, 0, 0); 2488 if (EHCI_PS_IS_LOWSPEED(v) 2489 && sc->sc_ncomp > 0 2490 && !(sc->sc_flags & EHCIF_ETTF)) { 2491 /* 2492 * Low speed device on non-ETTF controller or 2493 * unaccompanied controller, give up ownership. 2494 */ 2495 ehci_disown(sc, index, 1); 2496 break; 2497 } 2498 /* Start reset sequence. */ 2499 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2500 EOWRITE4(sc, port, v | EHCI_PS_PR); 2501 /* Wait for reset to complete. */ 2502 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2503 if (sc->sc_dying) { 2504 return -1; 2505 } 2506 /* 2507 * An embedded transaction translator will automatically 2508 * terminate the reset sequence so there's no need to 2509 * it. 2510 */ 2511 v = EOREAD4(sc, port); 2512 if (v & EHCI_PS_PR) { 2513 /* Terminate reset sequence. */ 2514 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2515 /* Wait for HC to complete reset. */ 2516 usb_delay_ms(&sc->sc_bus, 2517 EHCI_PORT_RESET_COMPLETE); 2518 if (sc->sc_dying) { 2519 return -1; 2520 } 2521 } 2522 2523 v = EOREAD4(sc, port); 2524 DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); 2525 if (v & EHCI_PS_PR) { 2526 printf("%s: port reset timeout\n", 2527 device_xname(sc->sc_dev)); 2528 return USBD_TIMEOUT; 2529 } 2530 if (!(v & EHCI_PS_PE)) { 2531 /* Not a high speed device, give up ownership.*/ 2532 ehci_disown(sc, index, 0); 2533 break; 2534 } 2535 sc->sc_isreset[index] = 1; 2536 DPRINTF("ehci port %d reset, status = 0x%08x", index, 2537 v, 0, 0); 2538 break; 2539 case UHF_PORT_POWER: 2540 DPRINTF("set port power %d (has PPC = %d)", index, 2541 sc->sc_hasppc, 0, 0); 2542 if (sc->sc_hasppc) 2543 EOWRITE4(sc, port, v | EHCI_PS_PP); 2544 break; 2545 case UHF_PORT_TEST: 2546 DPRINTF("set port test %d", index, 0, 0, 0); 2547 break; 2548 case UHF_PORT_INDICATOR: 2549 DPRINTF("set port ind %d", index, 0, 0, 0); 2550 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2551 break; 2552 default: 2553 return -1; 2554 } 2555 break; 2556 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2557 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2558 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2559 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2560 break; 2561 default: 2562 /* default from usbroothub */ 2563 DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); 2564 2565 return buflen; 2566 } 2567 2568 DPRINTF("returning %d", totlen, 0, 0, 0); 2569 2570 return totlen; 2571 } 2572 2573 Static void 2574 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2575 { 2576 int port; 2577 uint32_t v; 2578 2579 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2580 2581 DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); 2582 #ifdef DIAGNOSTIC 2583 if (sc->sc_npcomp != 0) { 2584 int i = (index-1) / sc->sc_npcomp; 2585 if (i >= sc->sc_ncomp) 2586 printf("%s: strange port\n", 2587 device_xname(sc->sc_dev)); 2588 else 2589 printf("%s: handing over %s speed device on " 2590 "port %d to %s\n", 2591 device_xname(sc->sc_dev), 2592 lowspeed ? "low" : "full", 2593 index, device_xname(sc->sc_comps[i])); 2594 } else { 2595 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2596 } 2597 #endif 2598 port = EHCI_PORTSC(index); 2599 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2600 EOWRITE4(sc, port, v | EHCI_PS_PO); 2601 } 2602 2603 Static usbd_status 2604 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2605 { 2606 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2607 usbd_status err; 2608 2609 /* Insert last in queue. */ 2610 mutex_enter(&sc->sc_lock); 2611 err = usb_insert_transfer(xfer); 2612 mutex_exit(&sc->sc_lock); 2613 if (err) 2614 return err; 2615 2616 /* Pipe isn't running, start first */ 2617 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2618 } 2619 2620 Static usbd_status 2621 ehci_root_intr_start(struct usbd_xfer *xfer) 2622 { 2623 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2624 2625 if (sc->sc_dying) 2626 return USBD_IOERROR; 2627 2628 mutex_enter(&sc->sc_lock); 2629 sc->sc_intrxfer = xfer; 2630 mutex_exit(&sc->sc_lock); 2631 2632 return USBD_IN_PROGRESS; 2633 } 2634 2635 /* Abort a root interrupt request. */ 2636 Static void 2637 ehci_root_intr_abort(struct usbd_xfer *xfer) 2638 { 2639 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2640 2641 KASSERT(mutex_owned(&sc->sc_lock)); 2642 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2643 2644 sc->sc_intrxfer = NULL; 2645 2646 xfer->ux_status = USBD_CANCELLED; 2647 usb_transfer_complete(xfer); 2648 } 2649 2650 /* Close the root pipe. */ 2651 Static void 2652 ehci_root_intr_close(struct usbd_pipe *pipe) 2653 { 2654 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2655 2656 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2657 2658 KASSERT(mutex_owned(&sc->sc_lock)); 2659 2660 sc->sc_intrxfer = NULL; 2661 } 2662 2663 Static void 2664 ehci_root_intr_done(struct usbd_xfer *xfer) 2665 { 2666 } 2667 2668 /************************/ 2669 2670 Static ehci_soft_qh_t * 2671 ehci_alloc_sqh(ehci_softc_t *sc) 2672 { 2673 ehci_soft_qh_t *sqh; 2674 usbd_status err; 2675 int i, offs; 2676 usb_dma_t dma; 2677 2678 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2679 2680 mutex_enter(&sc->sc_lock); 2681 if (sc->sc_freeqhs == NULL) { 2682 DPRINTF("allocating chunk", 0, 0, 0, 0); 2683 mutex_exit(&sc->sc_lock); 2684 2685 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2686 EHCI_PAGE_SIZE, &dma); 2687 #ifdef EHCI_DEBUG 2688 if (err) 2689 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2690 #endif 2691 if (err) 2692 return NULL; 2693 2694 mutex_enter(&sc->sc_lock); 2695 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2696 offs = i * EHCI_SQH_SIZE; 2697 sqh = KERNADDR(&dma, offs); 2698 sqh->physaddr = DMAADDR(&dma, offs); 2699 sqh->dma = dma; 2700 sqh->offs = offs; 2701 sqh->next = sc->sc_freeqhs; 2702 sc->sc_freeqhs = sqh; 2703 } 2704 } 2705 sqh = sc->sc_freeqhs; 2706 sc->sc_freeqhs = sqh->next; 2707 mutex_exit(&sc->sc_lock); 2708 2709 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2710 sqh->next = NULL; 2711 return sqh; 2712 } 2713 2714 Static void 2715 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2716 { 2717 KASSERT(mutex_owned(&sc->sc_lock)); 2718 2719 sqh->next = sc->sc_freeqhs; 2720 sc->sc_freeqhs = sqh; 2721 } 2722 2723 Static ehci_soft_qtd_t * 2724 ehci_alloc_sqtd(ehci_softc_t *sc) 2725 { 2726 ehci_soft_qtd_t *sqtd = NULL; 2727 usbd_status err; 2728 int i, offs; 2729 usb_dma_t dma; 2730 2731 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2732 2733 mutex_enter(&sc->sc_lock); 2734 if (sc->sc_freeqtds == NULL) { 2735 DPRINTF("allocating chunk", 0, 0, 0, 0); 2736 mutex_exit(&sc->sc_lock); 2737 2738 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2739 EHCI_PAGE_SIZE, &dma); 2740 #ifdef EHCI_DEBUG 2741 if (err) 2742 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2743 #endif 2744 if (err) 2745 goto done; 2746 2747 mutex_enter(&sc->sc_lock); 2748 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2749 offs = i * EHCI_SQTD_SIZE; 2750 sqtd = KERNADDR(&dma, offs); 2751 sqtd->physaddr = DMAADDR(&dma, offs); 2752 sqtd->dma = dma; 2753 sqtd->offs = offs; 2754 2755 sqtd->nextqtd = sc->sc_freeqtds; 2756 sc->sc_freeqtds = sqtd; 2757 } 2758 } 2759 2760 sqtd = sc->sc_freeqtds; 2761 sc->sc_freeqtds = sqtd->nextqtd; 2762 mutex_exit(&sc->sc_lock); 2763 2764 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2765 sqtd->nextqtd = NULL; 2766 sqtd->xfer = NULL; 2767 2768 done: 2769 return sqtd; 2770 } 2771 2772 Static void 2773 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2774 { 2775 2776 mutex_enter(&sc->sc_lock); 2777 sqtd->nextqtd = sc->sc_freeqtds; 2778 sc->sc_freeqtds = sqtd; 2779 mutex_exit(&sc->sc_lock); 2780 } 2781 2782 Static int 2783 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2784 int alen, int rd, ehci_soft_qtd_t **sp) 2785 { 2786 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2787 uint16_t flags = xfer->ux_flags; 2788 2789 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2790 2791 ASSERT_SLEEPABLE(); 2792 KASSERT(sp); 2793 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2794 2795 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2796 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2797 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2798 KM_SLEEP); 2799 exfer->ex_nsqtd = nsqtd; 2800 2801 DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); 2802 2803 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2804 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2805 if (cur == NULL) 2806 goto nomem; 2807 exfer->ex_sqtds[j++] = cur; 2808 2809 cur->xfer = xfer; 2810 cur->len = 0; 2811 2812 } 2813 2814 *sp = exfer->ex_sqtds[0]; 2815 DPRINTF("return sqtd=%p", *sp, 0, 0, 0); 2816 2817 return 0; 2818 2819 nomem: 2820 ehci_free_sqtds(sc, exfer); 2821 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2822 DPRINTF("no memory", 0, 0, 0, 0); 2823 return ENOMEM; 2824 } 2825 2826 Static void 2827 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2828 { 2829 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2830 DPRINTF("exfer=%p", exfer, 0, 0, 0); 2831 2832 mutex_enter(&sc->sc_lock); 2833 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2834 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2835 2836 if (sqtd == NULL) 2837 break; 2838 2839 sqtd->nextqtd = sc->sc_freeqtds; 2840 sc->sc_freeqtds = sqtd; 2841 } 2842 mutex_exit(&sc->sc_lock); 2843 } 2844 2845 Static void 2846 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2847 { 2848 if (prev) { 2849 prev->nextqtd = sqtd; 2850 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2851 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2852 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2853 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2854 } 2855 } 2856 2857 Static void 2858 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2859 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2860 { 2861 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2862 usb_dma_t *dma = &xfer->ux_dmabuf; 2863 uint16_t flags = xfer->ux_flags; 2864 ehci_soft_qtd_t *sqtd, *prev; 2865 int tog = *toggle; 2866 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2867 int len = length; 2868 2869 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2870 DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); 2871 DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); 2872 2873 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2874 2875 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2876 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2877 EHCI_QTD_SET_CERR(3) 2878 ; 2879 2880 sqtd = prev = NULL; 2881 size_t curoffs = 0; 2882 size_t j = 0; 2883 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2884 sqtd = exfer->ex_sqtds[j++]; 2885 DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); 2886 2887 /* 2888 * The EHCI hardware can handle at most 5 pages and they do 2889 * not have to be contiguous 2890 */ 2891 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2892 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2893 size_t curlen = len; 2894 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2895 /* must use multiple TDs, fill as much as possible. */ 2896 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2897 2898 /* the length must be a multiple of the max size */ 2899 curlen -= curlen % mps; 2900 } 2901 KASSERT(curlen != 0); 2902 DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, 2903 curoffs, 0); 2904 2905 /* Fill the qTD */ 2906 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2907 sqtd->qtd.qtd_status = htole32( 2908 qtdstatus | 2909 EHCI_QTD_SET_BYTES(curlen) | 2910 EHCI_QTD_SET_TOGGLE(tog)); 2911 2912 /* Find number of pages we'll be using, insert dma addresses */ 2913 size_t pages = EHCI_NPAGES(curlen); 2914 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2915 size_t pageoffs = EHCI_PAGE(curoffs); 2916 for (size_t i = 0; i < pages; i++) { 2917 paddr_t a = DMAADDR(dma, 2918 pageoffs + i * EHCI_PAGE_SIZE); 2919 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2920 /* Cast up to avoid compiler warnings */ 2921 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2922 DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, 2923 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2924 le32toh(sqtd->qtd.qtd_buffer[i])); 2925 } 2926 /* First buffer pointer requires a page offset to start at */ 2927 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2928 2929 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2930 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2931 2932 sqtd->len = curlen; 2933 2934 DPRINTF(" va %p pa %p len %d", va, 2935 DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2936 2937 ehci_append_sqtd(sqtd, prev); 2938 2939 if (((curlen + mps - 1) / mps) & 1) { 2940 tog ^= 1; 2941 } 2942 2943 curoffs += curlen; 2944 len -= curlen; 2945 } 2946 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2947 xfer, length, len, mps, exfer->ex_nsqtd, j); 2948 2949 if (!isread && 2950 (flags & USBD_FORCE_SHORT_XFER) && 2951 length % mps == 0) { 2952 /* Force a 0 length transfer at the end. */ 2953 2954 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2955 exfer->ex_nsqtd); 2956 prev = sqtd; 2957 sqtd = exfer->ex_sqtds[j++]; 2958 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 2959 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2960 sqtd->qtd.qtd_status = htole32( 2961 qtdstatus | 2962 EHCI_QTD_SET_BYTES(0) | 2963 EHCI_QTD_SET_TOGGLE(tog)); 2964 2965 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2966 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2967 2968 ehci_append_sqtd(sqtd, prev); 2969 tog ^= 1; 2970 } 2971 2972 *lsqtd = sqtd; 2973 *toggle = tog; 2974 } 2975 2976 Static ehci_soft_itd_t * 2977 ehci_alloc_itd(ehci_softc_t *sc) 2978 { 2979 struct ehci_soft_itd *itd, *freeitd; 2980 usbd_status err; 2981 usb_dma_t dma; 2982 2983 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2984 2985 mutex_enter(&sc->sc_lock); 2986 2987 freeitd = LIST_FIRST(&sc->sc_freeitds); 2988 if (freeitd == NULL) { 2989 DPRINTF("allocating chunk", 0, 0, 0, 0); 2990 mutex_exit(&sc->sc_lock); 2991 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2992 EHCI_PAGE_SIZE, &dma); 2993 2994 if (err) { 2995 DPRINTF("alloc returned %d", err, 0, 0, 0); 2996 return NULL; 2997 } 2998 mutex_enter(&sc->sc_lock); 2999 3000 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3001 int offs = i * EHCI_ITD_SIZE; 3002 itd = KERNADDR(&dma, offs); 3003 itd->physaddr = DMAADDR(&dma, offs); 3004 itd->dma = dma; 3005 itd->offs = offs; 3006 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3007 } 3008 freeitd = LIST_FIRST(&sc->sc_freeitds); 3009 } 3010 3011 itd = freeitd; 3012 LIST_REMOVE(itd, free_list); 3013 mutex_exit(&sc->sc_lock); 3014 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3015 3016 itd->frame_list.next = NULL; 3017 itd->frame_list.prev = NULL; 3018 itd->xfer_next = NULL; 3019 itd->slot = 0; 3020 3021 return itd; 3022 } 3023 3024 Static ehci_soft_sitd_t * 3025 ehci_alloc_sitd(ehci_softc_t *sc) 3026 { 3027 struct ehci_soft_sitd *sitd, *freesitd; 3028 usbd_status err; 3029 int i, offs; 3030 usb_dma_t dma; 3031 3032 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3033 3034 mutex_enter(&sc->sc_lock); 3035 freesitd = LIST_FIRST(&sc->sc_freesitds); 3036 if (freesitd == NULL) { 3037 DPRINTF("allocating chunk", 0, 0, 0, 0); 3038 mutex_exit(&sc->sc_lock); 3039 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3040 EHCI_PAGE_SIZE, &dma); 3041 3042 if (err) { 3043 DPRINTF("alloc returned %d", err, 0, 0, 3044 0); 3045 return NULL; 3046 } 3047 3048 mutex_enter(&sc->sc_lock); 3049 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3050 offs = i * EHCI_SITD_SIZE; 3051 sitd = KERNADDR(&dma, offs); 3052 sitd->physaddr = DMAADDR(&dma, offs); 3053 sitd->dma = dma; 3054 sitd->offs = offs; 3055 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3056 } 3057 freesitd = LIST_FIRST(&sc->sc_freesitds); 3058 } 3059 3060 sitd = freesitd; 3061 LIST_REMOVE(sitd, free_list); 3062 mutex_exit(&sc->sc_lock); 3063 3064 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3065 3066 sitd->frame_list.next = NULL; 3067 sitd->frame_list.prev = NULL; 3068 sitd->xfer_next = NULL; 3069 sitd->slot = 0; 3070 3071 return sitd; 3072 } 3073 3074 /****************/ 3075 3076 /* 3077 * Close a reqular pipe. 3078 * Assumes that there are no pending transactions. 3079 */ 3080 Static void 3081 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3082 { 3083 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3084 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3085 ehci_soft_qh_t *sqh = epipe->sqh; 3086 3087 KASSERT(mutex_owned(&sc->sc_lock)); 3088 3089 ehci_rem_qh(sc, sqh, head); 3090 ehci_free_sqh(sc, epipe->sqh); 3091 } 3092 3093 /* 3094 * Abort a device request. 3095 * If this routine is called at splusb() it guarantees that the request 3096 * will be removed from the hardware scheduling and that the callback 3097 * for it will be called with USBD_CANCELLED status. 3098 * It's impossible to guarantee that the requested transfer will not 3099 * have happened since the hardware runs concurrently. 3100 * If the transaction has already happened we rely on the ordinary 3101 * interrupt processing to process it. 3102 * XXX This is most probably wrong. 3103 * XXXMRG this doesn't make sense anymore. 3104 */ 3105 Static void 3106 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3107 { 3108 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3109 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3110 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3111 ehci_soft_qh_t *sqh = epipe->sqh; 3112 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3113 ehci_physaddr_t cur; 3114 uint32_t qhstatus; 3115 int hit; 3116 int wake; 3117 3118 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3119 3120 DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); 3121 3122 KASSERT(mutex_owned(&sc->sc_lock)); 3123 ASSERT_SLEEPABLE(); 3124 3125 if (sc->sc_dying) { 3126 /* If we're dying, just do the software part. */ 3127 xfer->ux_status = status; /* make software ignore it */ 3128 callout_stop(&xfer->ux_callout); 3129 usb_transfer_complete(xfer); 3130 return; 3131 } 3132 3133 /* 3134 * If an abort is already in progress then just wait for it to 3135 * complete and return. 3136 */ 3137 if (xfer->ux_hcflags & UXFER_ABORTING) { 3138 DPRINTF("already aborting", 0, 0, 0, 0); 3139 #ifdef DIAGNOSTIC 3140 if (status == USBD_TIMEOUT) 3141 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3142 #endif 3143 /* Override the status which might be USBD_TIMEOUT. */ 3144 xfer->ux_status = status; 3145 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3146 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3147 while (xfer->ux_hcflags & UXFER_ABORTING) 3148 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3149 return; 3150 } 3151 xfer->ux_hcflags |= UXFER_ABORTING; 3152 3153 /* 3154 * Step 1: Make interrupt routine and hardware ignore xfer. 3155 */ 3156 xfer->ux_status = status; /* make software ignore it */ 3157 callout_stop(&xfer->ux_callout); 3158 ehci_del_intr_list(sc, exfer); 3159 3160 usb_syncmem(&sqh->dma, 3161 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3162 sizeof(sqh->qh.qh_qtd.qtd_status), 3163 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3164 qhstatus = sqh->qh.qh_qtd.qtd_status; 3165 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3166 usb_syncmem(&sqh->dma, 3167 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3168 sizeof(sqh->qh.qh_qtd.qtd_status), 3169 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3170 3171 if (exfer->ex_type == EX_CTRL) { 3172 fsqtd = exfer->ex_setup; 3173 lsqtd = exfer->ex_status; 3174 } else { 3175 fsqtd = exfer->ex_sqtdstart; 3176 lsqtd = exfer->ex_sqtdend; 3177 } 3178 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3179 usb_syncmem(&sqtd->dma, 3180 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3181 sizeof(sqtd->qtd.qtd_status), 3182 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3183 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3184 usb_syncmem(&sqtd->dma, 3185 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3186 sizeof(sqtd->qtd.qtd_status), 3187 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3188 if (sqtd == lsqtd) 3189 break; 3190 } 3191 3192 /* 3193 * Step 2: Wait until we know hardware has finished any possible 3194 * use of the xfer. Also make sure the soft interrupt routine 3195 * has run. 3196 */ 3197 ehci_sync_hc(sc); 3198 sc->sc_softwake = 1; 3199 usb_schedsoftintr(&sc->sc_bus); 3200 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3201 3202 /* 3203 * Step 3: Remove any vestiges of the xfer from the hardware. 3204 * The complication here is that the hardware may have executed 3205 * beyond the xfer we're trying to abort. So as we're scanning 3206 * the TDs of this xfer we check if the hardware points to 3207 * any of them. 3208 */ 3209 3210 usb_syncmem(&sqh->dma, 3211 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3212 sizeof(sqh->qh.qh_curqtd), 3213 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3214 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3215 hit = 0; 3216 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3217 hit |= cur == sqtd->physaddr; 3218 if (sqtd == lsqtd) 3219 break; 3220 } 3221 sqtd = sqtd->nextqtd; 3222 /* Zap curqtd register if hardware pointed inside the xfer. */ 3223 if (hit && sqtd != NULL) { 3224 DPRINTF("cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3225 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3226 usb_syncmem(&sqh->dma, 3227 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3228 sizeof(sqh->qh.qh_curqtd), 3229 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3230 sqh->qh.qh_qtd.qtd_status = qhstatus; 3231 usb_syncmem(&sqh->dma, 3232 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3233 sizeof(sqh->qh.qh_qtd.qtd_status), 3234 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3235 } else { 3236 DPRINTF("no hit", 0, 0, 0, 0); 3237 usb_syncmem(&sqh->dma, 3238 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3239 sizeof(sqh->qh.qh_curqtd), 3240 BUS_DMASYNC_PREREAD); 3241 } 3242 3243 /* 3244 * Step 4: Execute callback. 3245 */ 3246 #ifdef DIAGNOSTIC 3247 exfer->ex_isdone = true; 3248 #endif 3249 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3250 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3251 usb_transfer_complete(xfer); 3252 if (wake) { 3253 cv_broadcast(&xfer->ux_hccv); 3254 } 3255 3256 KASSERT(mutex_owned(&sc->sc_lock)); 3257 } 3258 3259 Static void 3260 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3261 { 3262 ehci_isoc_trans_t trans_status; 3263 struct ehci_xfer *exfer; 3264 ehci_softc_t *sc; 3265 struct ehci_soft_itd *itd; 3266 struct ehci_soft_sitd *sitd; 3267 int i, wake; 3268 3269 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3270 3271 exfer = EHCI_XFER2EXFER(xfer); 3272 sc = EHCI_XFER2SC(xfer); 3273 3274 DPRINTF("xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3275 3276 KASSERT(mutex_owned(&sc->sc_lock)); 3277 3278 if (sc->sc_dying) { 3279 xfer->ux_status = status; 3280 callout_stop(&xfer->ux_callout); 3281 usb_transfer_complete(xfer); 3282 return; 3283 } 3284 3285 if (xfer->ux_hcflags & UXFER_ABORTING) { 3286 DPRINTF("already aborting", 0, 0, 0, 0); 3287 3288 #ifdef DIAGNOSTIC 3289 if (status == USBD_TIMEOUT) 3290 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3291 #endif 3292 3293 xfer->ux_status = status; 3294 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3295 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3296 while (xfer->ux_hcflags & UXFER_ABORTING) 3297 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3298 goto done; 3299 } 3300 xfer->ux_hcflags |= UXFER_ABORTING; 3301 3302 xfer->ux_status = status; 3303 callout_stop(&xfer->ux_callout); 3304 ehci_del_intr_list(sc, exfer); 3305 3306 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3307 for (itd = exfer->ex_itdstart; itd != NULL; 3308 itd = itd->xfer_next) { 3309 usb_syncmem(&itd->dma, 3310 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3311 sizeof(itd->itd.itd_ctl), 3312 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3313 3314 for (i = 0; i < 8; i++) { 3315 trans_status = le32toh(itd->itd.itd_ctl[i]); 3316 trans_status &= ~EHCI_ITD_ACTIVE; 3317 itd->itd.itd_ctl[i] = htole32(trans_status); 3318 } 3319 3320 usb_syncmem(&itd->dma, 3321 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3322 sizeof(itd->itd.itd_ctl), 3323 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3324 } 3325 } else { 3326 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3327 sitd = sitd->xfer_next) { 3328 usb_syncmem(&sitd->dma, 3329 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3330 sizeof(sitd->sitd.sitd_buffer), 3331 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3332 3333 trans_status = le32toh(sitd->sitd.sitd_trans); 3334 trans_status &= ~EHCI_SITD_ACTIVE; 3335 sitd->sitd.sitd_trans = htole32(trans_status); 3336 3337 usb_syncmem(&sitd->dma, 3338 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3339 sizeof(sitd->sitd.sitd_buffer), 3340 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3341 } 3342 } 3343 3344 sc->sc_softwake = 1; 3345 usb_schedsoftintr(&sc->sc_bus); 3346 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3347 3348 #ifdef DIAGNOSTIC 3349 exfer->ex_isdone = true; 3350 #endif 3351 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3352 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3353 usb_transfer_complete(xfer); 3354 if (wake) { 3355 cv_broadcast(&xfer->ux_hccv); 3356 } 3357 3358 done: 3359 KASSERT(mutex_owned(&sc->sc_lock)); 3360 return; 3361 } 3362 3363 Static void 3364 ehci_timeout(void *addr) 3365 { 3366 struct usbd_xfer *xfer = addr; 3367 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3368 struct usbd_pipe *pipe = xfer->ux_pipe; 3369 struct usbd_device *dev = pipe->up_dev; 3370 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3371 3372 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3373 3374 DPRINTF("exfer %p", exfer, 0, 0, 0); 3375 #ifdef EHCI_DEBUG 3376 if (ehcidebug >= 2) 3377 usbd_dump_pipe(pipe); 3378 #endif 3379 3380 if (sc->sc_dying) { 3381 mutex_enter(&sc->sc_lock); 3382 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3383 mutex_exit(&sc->sc_lock); 3384 return; 3385 } 3386 3387 /* Execute the abort in a process context. */ 3388 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3389 USB_TASKQ_MPSAFE); 3390 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3391 } 3392 3393 Static void 3394 ehci_timeout_task(void *addr) 3395 { 3396 struct usbd_xfer *xfer = addr; 3397 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3398 3399 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3400 3401 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3402 3403 mutex_enter(&sc->sc_lock); 3404 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3405 mutex_exit(&sc->sc_lock); 3406 } 3407 3408 /************************/ 3409 3410 Static int 3411 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3412 { 3413 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3414 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3415 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3416 usb_device_request_t *req = &xfer->ux_request; 3417 ehci_soft_qtd_t *setup, *status, *next; 3418 int isread = req->bmRequestType & UT_READ; 3419 int len = xfer->ux_bufsize; 3420 int err; 3421 3422 exfer->ex_type = EX_CTRL; 3423 exfer->ex_status = NULL; 3424 exfer->ex_data = NULL; 3425 exfer->ex_setup = ehci_alloc_sqtd(sc); 3426 if (exfer->ex_setup == NULL) { 3427 err = ENOMEM; 3428 goto bad1; 3429 } 3430 exfer->ex_status = ehci_alloc_sqtd(sc); 3431 if (exfer->ex_status == NULL) { 3432 err = ENOMEM; 3433 goto bad2; 3434 } 3435 setup = exfer->ex_setup; 3436 status = exfer->ex_status; 3437 exfer->ex_nsqtd = 0; 3438 next = status; 3439 /* Set up data transaction */ 3440 if (len != 0) { 3441 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3442 &exfer->ex_data); 3443 if (err) 3444 goto bad3; 3445 next = exfer->ex_data; 3446 } 3447 3448 /* Clear toggle */ 3449 setup->qtd.qtd_status = htole32( 3450 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3451 EHCI_QTD_SET_TOGGLE(0) | 3452 EHCI_QTD_SET_BYTES(sizeof(*req)) 3453 ); 3454 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3455 setup->qtd.qtd_buffer_hi[0] = 0; 3456 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3457 setup->nextqtd = next; 3458 setup->xfer = xfer; 3459 setup->len = sizeof(*req); 3460 3461 status->qtd.qtd_status = htole32( 3462 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3463 EHCI_QTD_SET_TOGGLE(1) | 3464 EHCI_QTD_IOC 3465 ); 3466 status->qtd.qtd_buffer[0] = 0; 3467 status->qtd.qtd_buffer_hi[0] = 0; 3468 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3469 status->nextqtd = NULL; 3470 status->xfer = xfer; 3471 status->len = 0; 3472 3473 return 0; 3474 bad3: 3475 ehci_free_sqtd(sc, exfer->ex_status); 3476 bad2: 3477 ehci_free_sqtd(sc, exfer->ex_setup); 3478 bad1: 3479 return err; 3480 } 3481 3482 Static void 3483 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3484 { 3485 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3486 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3487 3488 KASSERT(ex->ex_type == EX_CTRL); 3489 3490 ehci_free_sqtd(sc, ex->ex_setup); 3491 ehci_free_sqtd(sc, ex->ex_status); 3492 ehci_free_sqtds(sc, ex); 3493 if (ex->ex_nsqtd) 3494 kmem_free(ex->ex_sqtds, 3495 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3496 } 3497 3498 Static usbd_status 3499 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3500 { 3501 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3502 usbd_status err; 3503 3504 /* Insert last in queue. */ 3505 mutex_enter(&sc->sc_lock); 3506 err = usb_insert_transfer(xfer); 3507 mutex_exit(&sc->sc_lock); 3508 if (err) 3509 return err; 3510 3511 /* Pipe isn't running, start first */ 3512 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3513 } 3514 3515 Static usbd_status 3516 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3517 { 3518 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3519 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3520 usb_device_request_t *req = &xfer->ux_request; 3521 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3522 ehci_soft_qtd_t *setup, *status, *next; 3523 ehci_soft_qh_t *sqh; 3524 3525 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3526 3527 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3528 3529 if (sc->sc_dying) 3530 return USBD_IOERROR; 3531 3532 const int isread = req->bmRequestType & UT_READ; 3533 const int len = UGETW(req->wLength); 3534 3535 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 3536 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3537 UGETW(req->wIndex)); 3538 DPRINTF("len=%d, addr=%d, endpt=%d", len, epipe->pipe.up_dev->ud_addr, 3539 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3540 3541 sqh = epipe->sqh; 3542 3543 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3544 "address QH %" __PRIuBIT " pipe %d\n", 3545 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3546 epipe->pipe.up_dev->ud_addr); 3547 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3548 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3549 "MPS QH %" __PRIuBIT " pipe %d\n", 3550 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3551 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3552 3553 setup = exfer->ex_setup; 3554 status = exfer->ex_status; 3555 3556 DPRINTF("setup %p status %p data %p", setup, status, exfer->ex_data, 0); 3557 KASSERTMSG(setup != NULL && status != NULL, 3558 "Failed memory allocation, setup %p status %p", 3559 setup, status); 3560 3561 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3562 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3563 3564 /* Clear toggle */ 3565 setup->qtd.qtd_status &= ~htole32( 3566 EHCI_QTD_STATUS_MASK | 3567 EHCI_QTD_BYTES_MASK | 3568 EHCI_QTD_TOGGLE_MASK | 3569 EHCI_QTD_CERR_MASK 3570 ); 3571 setup->qtd.qtd_status |= htole32( 3572 EHCI_QTD_ACTIVE | 3573 EHCI_QTD_SET_CERR(3) | 3574 EHCI_QTD_SET_TOGGLE(0) | 3575 EHCI_QTD_SET_BYTES(sizeof(*req)) 3576 ); 3577 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3578 setup->qtd.qtd_buffer_hi[0] = 0; 3579 3580 next = status; 3581 status->qtd.qtd_status &= ~htole32( 3582 EHCI_QTD_STATUS_MASK | 3583 EHCI_QTD_PID_MASK | 3584 EHCI_QTD_BYTES_MASK | 3585 EHCI_QTD_TOGGLE_MASK | 3586 EHCI_QTD_CERR_MASK 3587 ); 3588 status->qtd.qtd_status |= htole32( 3589 EHCI_QTD_ACTIVE | 3590 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3591 EHCI_QTD_SET_CERR(3) | 3592 EHCI_QTD_SET_TOGGLE(1) | 3593 EHCI_QTD_SET_BYTES(0) | 3594 EHCI_QTD_IOC 3595 ); 3596 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3597 3598 KASSERT(exfer->ex_isdone); 3599 #ifdef DIAGNOSTIC 3600 exfer->ex_isdone = false; 3601 #endif 3602 3603 /* Set up data transaction */ 3604 if (len != 0) { 3605 ehci_soft_qtd_t *end; 3606 3607 /* Start toggle at 1. */ 3608 int toggle = 1; 3609 next = exfer->ex_data; 3610 KASSERTMSG(next != NULL, "Failed memory allocation"); 3611 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3612 end->nextqtd = status; 3613 end->qtd.qtd_next = end->qtd.qtd_altnext = 3614 htole32(status->physaddr); 3615 3616 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3617 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3618 3619 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3620 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3621 } 3622 3623 setup->nextqtd = next; 3624 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3625 3626 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3627 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3628 3629 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3630 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3631 3632 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3633 3634 #ifdef EHCI_DEBUG 3635 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3636 ehci_dump_sqh(sqh); 3637 ehci_dump_sqtds(setup); 3638 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3639 #endif 3640 3641 mutex_enter(&sc->sc_lock); 3642 3643 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3644 ehci_set_qh_qtd(sqh, setup); 3645 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3646 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3647 ehci_timeout, xfer); 3648 } 3649 ehci_add_intr_list(sc, exfer); 3650 xfer->ux_status = USBD_IN_PROGRESS; 3651 mutex_exit(&sc->sc_lock); 3652 3653 #if 0 3654 #ifdef EHCI_DEBUG 3655 DPRINTFN(10, "status=%x, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3656 // delay(10000); 3657 ehci_dump_regs(sc); 3658 ehci_dump_sqh(sc->sc_async_head); 3659 ehci_dump_sqh(sqh); 3660 ehci_dump_sqtds(setup); 3661 #endif 3662 #endif 3663 3664 return USBD_IN_PROGRESS; 3665 } 3666 3667 Static void 3668 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3669 { 3670 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3671 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3672 usb_device_request_t *req = &xfer->ux_request; 3673 int len = UGETW(req->wLength); 3674 int rd = req->bmRequestType & UT_READ; 3675 3676 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3677 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3678 3679 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3680 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3681 3682 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3683 BUS_DMASYNC_POSTWRITE); 3684 if (len) 3685 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3686 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3687 3688 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3689 } 3690 3691 /* Abort a device control request. */ 3692 Static void 3693 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3694 { 3695 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3696 3697 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3698 ehci_abort_xfer(xfer, USBD_CANCELLED); 3699 } 3700 3701 /* Close a device control pipe. */ 3702 Static void 3703 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3704 { 3705 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3706 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3707 3708 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3709 3710 KASSERT(mutex_owned(&sc->sc_lock)); 3711 3712 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3713 3714 ehci_close_pipe(pipe, sc->sc_async_head); 3715 } 3716 3717 /* 3718 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3719 * qTD status, or miss signalling occasionally under heavy load. If the host 3720 * machine is too fast, we we can miss transaction completion - when we scan 3721 * the active list the transaction still seems to be active. This generally 3722 * exhibits itself as a umass stall that never recovers. 3723 * 3724 * We work around this behaviour by setting up this callback after any softintr 3725 * that completes with transactions still pending, giving us another chance to 3726 * check for completion after the writeback has taken place. 3727 */ 3728 Static void 3729 ehci_intrlist_timeout(void *arg) 3730 { 3731 ehci_softc_t *sc = arg; 3732 3733 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3734 3735 usb_schedsoftintr(&sc->sc_bus); 3736 } 3737 3738 /************************/ 3739 3740 Static int 3741 ehci_device_bulk_init(struct usbd_xfer *xfer) 3742 { 3743 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3744 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3745 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3746 int endpt = ed->bEndpointAddress; 3747 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3748 int len = xfer->ux_bufsize; 3749 int err = 0; 3750 3751 exfer->ex_type = EX_BULK; 3752 exfer->ex_nsqtd = 0; 3753 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3754 &exfer->ex_sqtdstart); 3755 3756 return err; 3757 } 3758 3759 Static void 3760 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3761 { 3762 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3763 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3764 3765 KASSERT(ex->ex_type == EX_BULK); 3766 3767 ehci_free_sqtds(sc, ex); 3768 if (ex->ex_nsqtd) 3769 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3770 } 3771 3772 Static usbd_status 3773 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3774 { 3775 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3776 usbd_status err; 3777 3778 /* Insert last in queue. */ 3779 mutex_enter(&sc->sc_lock); 3780 err = usb_insert_transfer(xfer); 3781 mutex_exit(&sc->sc_lock); 3782 if (err) 3783 return err; 3784 3785 /* Pipe isn't running, start first */ 3786 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3787 } 3788 3789 Static usbd_status 3790 ehci_device_bulk_start(struct usbd_xfer *xfer) 3791 { 3792 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3793 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3794 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3795 ehci_soft_qh_t *sqh; 3796 ehci_soft_qtd_t *end; 3797 int len, isread, endpt; 3798 3799 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3800 3801 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3802 xfer->ux_flags, 0); 3803 3804 if (sc->sc_dying) 3805 return USBD_IOERROR; 3806 3807 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3808 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3809 3810 len = xfer->ux_length; 3811 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3812 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3813 sqh = epipe->sqh; 3814 3815 KASSERT(exfer->ex_isdone); 3816 #ifdef DIAGNOSTIC 3817 exfer->ex_isdone = false; 3818 #endif 3819 3820 /* Take lock here to protect nexttoggle */ 3821 mutex_enter(&sc->sc_lock); 3822 3823 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3824 3825 exfer->ex_sqtdend = end; 3826 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3827 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3828 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3829 3830 #ifdef EHCI_DEBUG 3831 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3832 ehci_dump_sqh(sqh); 3833 ehci_dump_sqtds(exfer->ex_sqtdstart); 3834 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3835 #endif 3836 3837 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3838 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3839 3840 /* also does usb_syncmem(sqh) */ 3841 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3842 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3843 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3844 ehci_timeout, xfer); 3845 } 3846 ehci_add_intr_list(sc, exfer); 3847 xfer->ux_status = USBD_IN_PROGRESS; 3848 mutex_exit(&sc->sc_lock); 3849 3850 #if 0 3851 #ifdef EHCI_DEBUG 3852 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3853 // delay(10000); 3854 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3855 ehci_dump_regs(sc); 3856 #if 0 3857 printf("async_head:\n"); 3858 ehci_dump_sqh(sc->sc_async_head); 3859 #endif 3860 DPRINTF("sqh:", 0, 0, 0, 0); 3861 ehci_dump_sqh(sqh); 3862 ehci_dump_sqtds(exfer->ex_sqtdstart); 3863 #endif 3864 #endif 3865 3866 return USBD_IN_PROGRESS; 3867 } 3868 3869 Static void 3870 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3871 { 3872 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3873 3874 DPRINTF("xfer %p", xfer, 0, 0, 0); 3875 ehci_abort_xfer(xfer, USBD_CANCELLED); 3876 } 3877 3878 /* 3879 * Close a device bulk pipe. 3880 */ 3881 Static void 3882 ehci_device_bulk_close(struct usbd_pipe *pipe) 3883 { 3884 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3885 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3886 3887 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3888 3889 KASSERT(mutex_owned(&sc->sc_lock)); 3890 3891 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3892 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3893 ehci_close_pipe(pipe, sc->sc_async_head); 3894 } 3895 3896 Static void 3897 ehci_device_bulk_done(struct usbd_xfer *xfer) 3898 { 3899 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3900 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3901 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3902 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3903 3904 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3905 3906 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 3907 3908 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3909 3910 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3911 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3912 3913 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3914 } 3915 3916 /************************/ 3917 3918 Static usbd_status 3919 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3920 { 3921 struct ehci_soft_islot *isp; 3922 int islot, lev; 3923 3924 /* Find a poll rate that is large enough. */ 3925 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3926 if (EHCI_ILEV_IVAL(lev) <= ival) 3927 break; 3928 3929 /* Pick an interrupt slot at the right level. */ 3930 /* XXX could do better than picking at random */ 3931 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3932 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3933 3934 sqh->islot = islot; 3935 isp = &sc->sc_islots[islot]; 3936 mutex_enter(&sc->sc_lock); 3937 ehci_add_qh(sc, sqh, isp->sqh); 3938 mutex_exit(&sc->sc_lock); 3939 3940 return USBD_NORMAL_COMPLETION; 3941 } 3942 3943 3944 Static int 3945 ehci_device_intr_init(struct usbd_xfer *xfer) 3946 { 3947 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3948 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3949 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3950 int endpt = ed->bEndpointAddress; 3951 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3952 int len = xfer->ux_bufsize; 3953 int err; 3954 3955 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3956 3957 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3958 xfer->ux_flags, 0); 3959 3960 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3961 KASSERT(len != 0); 3962 3963 exfer->ex_type = EX_INTR; 3964 exfer->ex_nsqtd = 0; 3965 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3966 &exfer->ex_sqtdstart); 3967 3968 return err; 3969 } 3970 3971 Static void 3972 ehci_device_intr_fini(struct usbd_xfer *xfer) 3973 { 3974 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3975 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3976 3977 KASSERT(ex->ex_type == EX_INTR); 3978 3979 ehci_free_sqtds(sc, ex); 3980 if (ex->ex_nsqtd) 3981 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3982 } 3983 3984 Static usbd_status 3985 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3986 { 3987 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3988 usbd_status err; 3989 3990 /* Insert last in queue. */ 3991 mutex_enter(&sc->sc_lock); 3992 err = usb_insert_transfer(xfer); 3993 mutex_exit(&sc->sc_lock); 3994 if (err) 3995 return err; 3996 3997 /* 3998 * Pipe isn't running (otherwise err would be USBD_INPROG), 3999 * so start it first. 4000 */ 4001 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4002 } 4003 4004 Static usbd_status 4005 ehci_device_intr_start(struct usbd_xfer *xfer) 4006 { 4007 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4008 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4009 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4010 ehci_soft_qtd_t *end; 4011 ehci_soft_qh_t *sqh; 4012 int len, isread, endpt; 4013 4014 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4015 4016 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4017 xfer->ux_flags, 0); 4018 4019 if (sc->sc_dying) 4020 return USBD_IOERROR; 4021 4022 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4023 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4024 4025 len = xfer->ux_length; 4026 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4027 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4028 sqh = epipe->sqh; 4029 4030 KASSERT(exfer->ex_isdone); 4031 #ifdef DIAGNOSTIC 4032 exfer->ex_isdone = false; 4033 #endif 4034 4035 /* Take lock to protect nexttoggle */ 4036 mutex_enter(&sc->sc_lock); 4037 4038 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4039 4040 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4041 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4042 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4043 exfer->ex_sqtdend = end; 4044 4045 #ifdef EHCI_DEBUG 4046 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4047 ehci_dump_sqh(sqh); 4048 ehci_dump_sqtds(exfer->ex_sqtdstart); 4049 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4050 #endif 4051 4052 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4053 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4054 4055 /* also does usb_syncmem(sqh) */ 4056 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4057 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4058 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4059 ehci_timeout, xfer); 4060 } 4061 ehci_add_intr_list(sc, exfer); 4062 xfer->ux_status = USBD_IN_PROGRESS; 4063 mutex_exit(&sc->sc_lock); 4064 4065 #if 0 4066 #ifdef EHCI_DEBUG 4067 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4068 // delay(10000); 4069 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4070 ehci_dump_regs(sc); 4071 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4072 ehci_dump_sqh(sqh); 4073 ehci_dump_sqtds(exfer->ex_sqtdstart); 4074 #endif 4075 #endif 4076 4077 return USBD_IN_PROGRESS; 4078 } 4079 4080 Static void 4081 ehci_device_intr_abort(struct usbd_xfer *xfer) 4082 { 4083 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4084 4085 DPRINTF("xfer=%p", xfer, 0, 0, 0); 4086 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4087 4088 /* 4089 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4090 * async doorbell. That's dependent on the async list, wheras 4091 * intr xfers are periodic, should not use this? 4092 */ 4093 ehci_abort_xfer(xfer, USBD_CANCELLED); 4094 } 4095 4096 Static void 4097 ehci_device_intr_close(struct usbd_pipe *pipe) 4098 { 4099 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4100 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4101 struct ehci_soft_islot *isp; 4102 4103 KASSERT(mutex_owned(&sc->sc_lock)); 4104 4105 isp = &sc->sc_islots[epipe->sqh->islot]; 4106 ehci_close_pipe(pipe, isp->sqh); 4107 } 4108 4109 Static void 4110 ehci_device_intr_done(struct usbd_xfer *xfer) 4111 { 4112 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4113 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4114 int isread, endpt; 4115 4116 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4117 4118 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4119 0, 0); 4120 4121 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4122 4123 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4124 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4125 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4126 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4127 } 4128 4129 /************************/ 4130 Static int 4131 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4132 { 4133 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4134 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4135 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4136 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4137 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4138 int i, k, frames; 4139 u_int huba, dir; 4140 int err; 4141 4142 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4143 4144 start = NULL; 4145 sitd = NULL; 4146 4147 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4148 xfer->ux_flags, 0); 4149 4150 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4151 KASSERT(xfer->ux_nframes != 0); 4152 KASSERT(exfer->ex_isdone); 4153 4154 exfer->ex_type = EX_FS_ISOC; 4155 /* 4156 * Step 1: Allocate and initialize sitds. 4157 */ 4158 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4159 if (i > 16 || i == 0) { 4160 /* Spec page 271 says intervals > 16 are invalid */ 4161 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4162 4163 return EINVAL; 4164 } 4165 4166 frames = xfer->ux_nframes; 4167 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4168 sitd = ehci_alloc_sitd(sc); 4169 if (sitd == NULL) { 4170 err = ENOMEM; 4171 goto fail; 4172 } 4173 4174 if (prev) 4175 prev->xfer_next = sitd; 4176 else 4177 start = sitd; 4178 4179 huba = dev->ud_myhsport->up_parent->ud_addr; 4180 4181 #if 0 4182 if (sc->sc_flags & EHCIF_FREESCALE) { 4183 // Set hub address to 0 if embedded TT is used. 4184 if (huba == sc->sc_addr) 4185 huba = 0; 4186 } 4187 #endif 4188 4189 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4190 dir = UE_GET_DIR(k) ? 1 : 0; 4191 sitd->sitd.sitd_endp = 4192 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4193 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4194 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4195 EHCI_SITD_SET_HUBA(huba) | 4196 EHCI_SITD_SET_DIR(dir)); 4197 4198 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4199 } /* End of frame */ 4200 4201 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4202 4203 stop = sitd; 4204 stop->xfer_next = NULL; 4205 exfer->ex_sitdstart = start; 4206 exfer->ex_sitdend = stop; 4207 4208 return 0; 4209 4210 fail: 4211 mutex_enter(&sc->sc_lock); 4212 ehci_soft_sitd_t *next; 4213 for (sitd = start; sitd; sitd = next) { 4214 next = sitd->xfer_next; 4215 ehci_free_sitd_locked(sc, sitd); 4216 } 4217 mutex_exit(&sc->sc_lock); 4218 4219 return err; 4220 } 4221 4222 Static void 4223 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4224 { 4225 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4226 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4227 4228 KASSERT(ex->ex_type == EX_FS_ISOC); 4229 4230 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4231 } 4232 4233 Static usbd_status 4234 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4235 { 4236 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4237 usbd_status __diagused err; 4238 4239 mutex_enter(&sc->sc_lock); 4240 err = usb_insert_transfer(xfer); 4241 mutex_exit(&sc->sc_lock); 4242 4243 KASSERT(err == USBD_NORMAL_COMPLETION); 4244 4245 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4246 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4247 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4248 ehci_soft_sitd_t *sitd; 4249 usb_dma_t *dma_buf; 4250 int i, j, k, frames; 4251 int offs, total_length; 4252 int frindex; 4253 u_int dir; 4254 4255 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4256 4257 sitd = NULL; 4258 total_length = 0; 4259 4260 4261 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4262 xfer->ux_flags, 0); 4263 4264 if (sc->sc_dying) 4265 return USBD_IOERROR; 4266 4267 /* 4268 * To avoid complication, don't allow a request right now that'll span 4269 * the entire frame table. To within 4 frames, to allow some leeway 4270 * on either side of where the hc currently is. 4271 */ 4272 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4273 xfer->ux_nframes >= sc->sc_flsize - 4) { 4274 printf("ehci: isoc descriptor requested that spans the entire" 4275 "frametable, too many frames\n"); 4276 return USBD_INVAL; 4277 } 4278 4279 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4280 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4281 KASSERT(exfer->ex_isdone); 4282 #ifdef DIAGNOSTIC 4283 exfer->ex_isdone = false; 4284 #endif 4285 4286 /* 4287 * Step 1: Initialize sitds. 4288 */ 4289 4290 frames = xfer->ux_nframes; 4291 dma_buf = &xfer->ux_dmabuf; 4292 offs = 0; 4293 4294 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4295 i++, sitd = sitd->xfer_next) { 4296 KASSERT(sitd != NULL); 4297 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4298 4299 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4300 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4301 4302 /* Set page0 index and offset - TP and T-offset are set below */ 4303 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4304 4305 total_length += xfer->ux_frlengths[i]; 4306 offs += xfer->ux_frlengths[i]; 4307 4308 sitd->sitd.sitd_buffer[1] = 4309 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4310 4311 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4312 4313 #if 0 4314 if (sc->sc_flags & EHCIF_FREESCALE) { 4315 // Set hub address to 0 if embedded TT is used. 4316 if (huba == sc->sc_addr) 4317 huba = 0; 4318 } 4319 #endif 4320 4321 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4322 dir = UE_GET_DIR(k) ? 1 : 0; 4323 KASSERT(sitd->sitd.sitd_endp == htole32( 4324 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4325 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4326 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4327 EHCI_SITD_SET_HUBA(huba) | 4328 EHCI_SITD_SET_DIR(dir))); 4329 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4330 4331 uint8_t sa = 0; 4332 uint8_t sb = 0; 4333 u_int temp, tlen; 4334 4335 if (dir == 0) { /* OUT */ 4336 temp = 0; 4337 tlen = xfer->ux_frlengths[i]; 4338 if (tlen <= 188) { 4339 temp |= 1; /* T-count = 1, TP = ALL */ 4340 tlen = 1; 4341 } else { 4342 tlen += 187; 4343 tlen /= 188; 4344 temp |= tlen; /* T-count = [1..6] */ 4345 temp |= 8; /* TP = Begin */ 4346 } 4347 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4348 4349 tlen += sa; 4350 4351 if (tlen >= 8) { 4352 sb = 0; 4353 } else { 4354 sb = (1 << tlen); 4355 } 4356 4357 sa = (1 << sa); 4358 sa = (sb - sa) & 0x3F; 4359 sb = 0; 4360 } else { 4361 sb = (-(4 << sa)) & 0xFE; 4362 sa = (1 << sa) & 0x3F; 4363 sa = 0x01; 4364 sb = 0xfc; 4365 } 4366 4367 sitd->sitd.sitd_sched = htole32( 4368 EHCI_SITD_SET_SMASK(sa) | 4369 EHCI_SITD_SET_CMASK(sb) 4370 ); 4371 4372 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4373 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4374 } /* End of frame */ 4375 4376 sitd = exfer->ex_sitdend; 4377 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4378 4379 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4380 sizeof(sitd->sitd.sitd_trans), 4381 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4382 4383 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4385 4386 /* 4387 * Part 2: Transfer descriptors have now been set up, now they must 4388 * be scheduled into the periodic frame list. Erk. Not wanting to 4389 * complicate matters, transfer is denied if the transfer spans 4390 * more than the period frame list. 4391 */ 4392 4393 mutex_enter(&sc->sc_lock); 4394 4395 /* Start inserting frames */ 4396 if (epipe->isoc.cur_xfers > 0) { 4397 frindex = epipe->isoc.next_frame; 4398 } else { 4399 frindex = EOREAD4(sc, EHCI_FRINDEX); 4400 frindex = frindex >> 3; /* Erase microframe index */ 4401 frindex += 2; 4402 } 4403 4404 if (frindex >= sc->sc_flsize) 4405 frindex &= (sc->sc_flsize - 1); 4406 4407 /* Whats the frame interval? */ 4408 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4409 4410 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4411 j++, sitd = sitd->xfer_next) { 4412 KASSERT(sitd); 4413 4414 usb_syncmem(&sc->sc_fldma, 4415 sizeof(ehci_link_t) * frindex, 4416 sizeof(ehci_link_t), 4417 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4418 4419 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4420 if (sitd->sitd.sitd_next == 0) 4421 /* 4422 * FIXME: frindex table gets initialized to NULL 4423 * or EHCI_NULL? 4424 */ 4425 sitd->sitd.sitd_next = EHCI_NULL; 4426 4427 usb_syncmem(&sitd->dma, 4428 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4429 sizeof(ehci_sitd_t), 4430 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4431 4432 sc->sc_flist[frindex] = 4433 htole32(EHCI_LINK_SITD | sitd->physaddr); 4434 4435 usb_syncmem(&sc->sc_fldma, 4436 sizeof(ehci_link_t) * frindex, 4437 sizeof(ehci_link_t), 4438 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4439 4440 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4441 sc->sc_softsitds[frindex] = sitd; 4442 if (sitd->frame_list.next != NULL) 4443 sitd->frame_list.next->frame_list.prev = sitd; 4444 sitd->slot = frindex; 4445 sitd->frame_list.prev = NULL; 4446 4447 frindex += i; 4448 if (frindex >= sc->sc_flsize) 4449 frindex -= sc->sc_flsize; 4450 } 4451 4452 epipe->isoc.cur_xfers++; 4453 epipe->isoc.next_frame = frindex; 4454 4455 ehci_add_intr_list(sc, exfer); 4456 xfer->ux_status = USBD_IN_PROGRESS; 4457 4458 mutex_exit(&sc->sc_lock); 4459 4460 return USBD_IN_PROGRESS; 4461 } 4462 4463 Static void 4464 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4465 { 4466 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4467 4468 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4469 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4470 } 4471 4472 Static void 4473 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4474 { 4475 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4476 4477 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4478 } 4479 4480 Static void 4481 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4482 { 4483 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4484 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4485 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4486 4487 KASSERT(mutex_owned(&sc->sc_lock)); 4488 4489 epipe->isoc.cur_xfers--; 4490 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4491 4492 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4493 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4494 } 4495 4496 4497 /************************/ 4498 4499 4500 Static int 4501 ehci_device_isoc_init(struct usbd_xfer *xfer) 4502 { 4503 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4504 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4505 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4506 ehci_soft_itd_t *itd, *prev, *start, *stop; 4507 int i, j, k; 4508 int frames, ufrperframe; 4509 int err; 4510 4511 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4512 4513 start = NULL; 4514 prev = NULL; 4515 itd = NULL; 4516 4517 KASSERT(xfer->ux_nframes != 0); 4518 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4519 KASSERT(exfer->ex_isdone); 4520 4521 exfer->ex_type = EX_ISOC; 4522 4523 /* 4524 * Step 1: Allocate and initialize itds, how many do we need? 4525 * One per transfer if interval >= 8 microframes, less if we use 4526 * multiple microframes per frame. 4527 */ 4528 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4529 if (i > 16 || i == 0) { 4530 /* Spec page 271 says intervals > 16 are invalid */ 4531 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4532 return USBD_INVAL; 4533 } 4534 4535 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4536 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4537 4538 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4539 itd = ehci_alloc_itd(sc); 4540 if (itd == NULL) { 4541 err = ENOMEM; 4542 goto fail; 4543 } 4544 4545 if (prev != NULL) { 4546 /* Maybe not as it's updated by the scheduling? */ 4547 prev->itd.itd_next = 4548 htole32(itd->physaddr | EHCI_LINK_ITD); 4549 4550 prev->xfer_next = itd; 4551 } else { 4552 start = itd; 4553 } 4554 4555 /* 4556 * Other special values 4557 */ 4558 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4559 itd->itd.itd_bufr[0] = htole32( 4560 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4561 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4562 4563 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4564 ? 1 : 0; 4565 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4566 itd->itd.itd_bufr[1] |= htole32( 4567 EHCI_ITD_SET_DIR(k) | 4568 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4569 4570 /* FIXME: handle invalid trans - should be done in openpipe */ 4571 itd->itd.itd_bufr[2] |= 4572 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4573 } /* End of frame */ 4574 4575 stop = itd; 4576 stop->xfer_next = NULL; 4577 4578 exfer->ex_itdstart = start; 4579 exfer->ex_itdend = stop; 4580 4581 return 0; 4582 fail: 4583 mutex_enter(&sc->sc_lock); 4584 ehci_soft_itd_t *next; 4585 for (itd = start; itd; itd = next) { 4586 next = itd->xfer_next; 4587 ehci_free_itd_locked(sc, itd); 4588 } 4589 mutex_exit(&sc->sc_lock); 4590 4591 return err; 4592 4593 } 4594 4595 Static void 4596 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4597 { 4598 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4599 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4600 4601 KASSERT(ex->ex_type == EX_ISOC); 4602 4603 ehci_free_itd_chain(sc, ex->ex_itdstart); 4604 } 4605 4606 Static usbd_status 4607 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4608 { 4609 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4610 usbd_status __diagused err; 4611 4612 mutex_enter(&sc->sc_lock); 4613 err = usb_insert_transfer(xfer); 4614 mutex_exit(&sc->sc_lock); 4615 4616 KASSERT(err == USBD_NORMAL_COMPLETION); 4617 4618 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4619 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4620 ehci_soft_itd_t *itd, *prev; 4621 usb_dma_t *dma_buf; 4622 int i, j; 4623 int frames, uframes, ufrperframe; 4624 int trans_count, offs, total_length; 4625 int frindex; 4626 4627 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4628 4629 prev = NULL; 4630 itd = NULL; 4631 trans_count = 0; 4632 total_length = 0; 4633 4634 DPRINTF("xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4635 4636 if (sc->sc_dying) 4637 return USBD_IOERROR; 4638 4639 /* 4640 * To avoid complication, don't allow a request right now that'll span 4641 * the entire frame table. To within 4 frames, to allow some leeway 4642 * on either side of where the hc currently is. 4643 */ 4644 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4645 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4646 DPRINTF( 4647 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4648 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4649 return USBD_INVAL; 4650 } 4651 4652 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4653 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4654 KASSERT(exfer->ex_isdone); 4655 #ifdef DIAGNOSTIC 4656 exfer->ex_isdone = false; 4657 #endif 4658 4659 /* 4660 * Step 1: Re-Initialize itds 4661 */ 4662 4663 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4664 if (i > 16 || i == 0) { 4665 /* Spec page 271 says intervals > 16 are invalid */ 4666 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4667 return USBD_INVAL; 4668 } 4669 4670 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4671 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4672 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4673 4674 if (frames == 0) { 4675 DPRINTF("frames == 0", 0, 0, 0, 0); 4676 return USBD_INVAL; 4677 } 4678 4679 dma_buf = &xfer->ux_dmabuf; 4680 offs = 0; 4681 4682 itd = exfer->ex_itdstart; 4683 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4684 int froffs = offs; 4685 4686 if (prev != NULL) { 4687 prev->itd.itd_next = 4688 htole32(itd->physaddr | EHCI_LINK_ITD); 4689 usb_syncmem(&prev->dma, 4690 prev->offs + offsetof(ehci_itd_t, itd_next), 4691 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4692 prev->xfer_next = itd; 4693 } 4694 4695 /* 4696 * Step 1.5, initialize uframes 4697 */ 4698 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4699 /* Calculate which page in the list this starts in */ 4700 int addr = DMAADDR(dma_buf, froffs); 4701 addr = EHCI_PAGE_OFFSET(addr); 4702 addr += (offs - froffs); 4703 addr = EHCI_PAGE(addr); 4704 addr /= EHCI_PAGE_SIZE; 4705 4706 /* 4707 * This gets the initial offset into the first page, 4708 * looks how far further along the current uframe 4709 * offset is. Works out how many pages that is. 4710 */ 4711 4712 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4713 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4714 EHCI_ITD_SET_PG(addr) | 4715 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4716 4717 total_length += xfer->ux_frlengths[trans_count]; 4718 offs += xfer->ux_frlengths[trans_count]; 4719 trans_count++; 4720 4721 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4722 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4723 break; 4724 } 4725 } 4726 4727 /* 4728 * Step 1.75, set buffer pointers. To simplify matters, all 4729 * pointers are filled out for the next 7 hardware pages in 4730 * the dma block, so no need to worry what pages to cover 4731 * and what to not. 4732 */ 4733 4734 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4735 /* 4736 * Don't try to lookup a page that's past the end 4737 * of buffer 4738 */ 4739 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4740 if (page_offs >= dma_buf->udma_block->size) 4741 break; 4742 4743 uint64_t page = DMAADDR(dma_buf, page_offs); 4744 page = EHCI_PAGE(page); 4745 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4746 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4747 } 4748 /* 4749 * Other special values 4750 */ 4751 4752 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4753 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4754 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4755 4756 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4757 ? 1 : 0; 4758 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4759 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4760 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4761 4762 /* FIXME: handle invalid trans */ 4763 itd->itd.itd_bufr[2] |= 4764 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4765 4766 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4767 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4768 4769 prev = itd; 4770 } /* End of frame */ 4771 4772 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4773 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4774 4775 /* 4776 * Part 2: Transfer descriptors have now been set up, now they must 4777 * be scheduled into the period frame list. Erk. Not wanting to 4778 * complicate matters, transfer is denied if the transfer spans 4779 * more than the period frame list. 4780 */ 4781 4782 mutex_enter(&sc->sc_lock); 4783 4784 /* Start inserting frames */ 4785 if (epipe->isoc.cur_xfers > 0) { 4786 frindex = epipe->isoc.next_frame; 4787 } else { 4788 frindex = EOREAD4(sc, EHCI_FRINDEX); 4789 frindex = frindex >> 3; /* Erase microframe index */ 4790 frindex += 2; 4791 } 4792 4793 if (frindex >= sc->sc_flsize) 4794 frindex &= (sc->sc_flsize - 1); 4795 4796 /* What's the frame interval? */ 4797 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4798 if (i / USB_UFRAMES_PER_FRAME == 0) 4799 i = 1; 4800 else 4801 i /= USB_UFRAMES_PER_FRAME; 4802 4803 itd = exfer->ex_itdstart; 4804 for (j = 0; j < frames; j++) { 4805 KASSERTMSG(itd != NULL, "frame %d\n", j); 4806 4807 usb_syncmem(&sc->sc_fldma, 4808 sizeof(ehci_link_t) * frindex, 4809 sizeof(ehci_link_t), 4810 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4811 4812 itd->itd.itd_next = sc->sc_flist[frindex]; 4813 if (itd->itd.itd_next == 0) 4814 /* 4815 * FIXME: frindex table gets initialized to NULL 4816 * or EHCI_NULL? 4817 */ 4818 itd->itd.itd_next = EHCI_NULL; 4819 4820 usb_syncmem(&itd->dma, 4821 itd->offs + offsetof(ehci_itd_t, itd_next), 4822 sizeof(itd->itd.itd_next), 4823 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4824 4825 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4826 4827 usb_syncmem(&sc->sc_fldma, 4828 sizeof(ehci_link_t) * frindex, 4829 sizeof(ehci_link_t), 4830 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4831 4832 itd->frame_list.next = sc->sc_softitds[frindex]; 4833 sc->sc_softitds[frindex] = itd; 4834 if (itd->frame_list.next != NULL) 4835 itd->frame_list.next->frame_list.prev = itd; 4836 itd->slot = frindex; 4837 itd->frame_list.prev = NULL; 4838 4839 frindex += i; 4840 if (frindex >= sc->sc_flsize) 4841 frindex -= sc->sc_flsize; 4842 4843 itd = itd->xfer_next; 4844 } 4845 4846 epipe->isoc.cur_xfers++; 4847 epipe->isoc.next_frame = frindex; 4848 4849 ehci_add_intr_list(sc, exfer); 4850 xfer->ux_status = USBD_IN_PROGRESS; 4851 4852 mutex_exit(&sc->sc_lock); 4853 4854 return USBD_IN_PROGRESS; 4855 } 4856 4857 Static void 4858 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4859 { 4860 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4861 4862 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4863 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4864 } 4865 4866 Static void 4867 ehci_device_isoc_close(struct usbd_pipe *pipe) 4868 { 4869 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4870 4871 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4872 } 4873 4874 Static void 4875 ehci_device_isoc_done(struct usbd_xfer *xfer) 4876 { 4877 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4878 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4879 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4880 4881 KASSERT(mutex_owned(&sc->sc_lock)); 4882 4883 epipe->isoc.cur_xfers--; 4884 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4885 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4886 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4887 } 4888
Indexes created Mon Sep 22 21:09:42 GMT 2025