ehci.c revision 1.252
1 /* $NetBSD: ehci.c,v 1.252 2016/05/14 07:14:31 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.252 2016/05/14 07:14:31 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static void ehci_intrlist_timeout(void *); 172 Static void ehci_doorbell(void *); 173 Static void ehci_pcd(void *); 174 175 Static struct usbd_xfer * 176 ehci_allocx(struct usbd_bus *, unsigned int); 177 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 178 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_softwake_cv, "ehciab"); 416 cv_init(&sc->sc_doorbell, "ehcidi"); 417 418 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 419 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 420 421 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 422 ehci_doorbell, sc); 423 KASSERT(sc->sc_doorbell_si != NULL); 424 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 425 ehci_pcd, sc); 426 KASSERT(sc->sc_pcd_si != NULL); 427 428 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 429 430 vers = EREAD2(sc, EHCI_HCIVERSION); 431 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 432 vers >> 8, vers & 0xff); 433 434 sparams = EREAD4(sc, EHCI_HCSPARAMS); 435 DPRINTF("sparams=%#x", sparams, 0, 0, 0); 436 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 437 ncomp = EHCI_HCS_N_CC(sparams); 438 if (ncomp != sc->sc_ncomp) { 439 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 440 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 441 #if NOHCI == 0 || NUHCI == 0 442 aprint_error("%s: ohci or uhci probably not configured\n", 443 device_xname(sc->sc_dev)); 444 #endif 445 if (ncomp < sc->sc_ncomp) 446 sc->sc_ncomp = ncomp; 447 } 448 if (sc->sc_ncomp > 0) { 449 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 450 aprint_normal("%s: companion controller%s, %d port%s each:", 451 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 452 EHCI_HCS_N_PCC(sparams), 453 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 454 for (i = 0; i < sc->sc_ncomp; i++) 455 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 456 aprint_normal("\n"); 457 } 458 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 459 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 460 461 cparams = EREAD4(sc, EHCI_HCCPARAMS); 462 DPRINTF("cparams=%#x", cparams, 0, 0, 0); 463 464 if (EHCI_HCC_64BIT(cparams)) { 465 /* MUST clear segment register if 64 bit capable. */ 466 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 467 } 468 469 if (cparams & EHCI_HCC_IST_FULLFRAME) { 470 sc->sc_istthreshold = 0; 471 } else { 472 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 473 } 474 475 sc->sc_bus.ub_revision = USBREV_2_0; 476 sc->sc_bus.ub_usedma = true; 477 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 478 479 /* Reset the controller */ 480 DPRINTF("resetting", 0, 0, 0, 0); 481 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 482 usb_delay_ms(&sc->sc_bus, 1); 483 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 484 for (i = 0; i < 100; i++) { 485 usb_delay_ms(&sc->sc_bus, 1); 486 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 487 if (!hcr) 488 break; 489 } 490 if (hcr) { 491 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 492 return EIO; 493 } 494 if (sc->sc_vendor_init) 495 sc->sc_vendor_init(sc); 496 497 /* XXX need proper intr scheduling */ 498 sc->sc_rand = 96; 499 500 /* frame list size at default, read back what we got and use that */ 501 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 502 case 0: sc->sc_flsize = 1024; break; 503 case 1: sc->sc_flsize = 512; break; 504 case 2: sc->sc_flsize = 256; break; 505 case 3: return EIO; 506 } 507 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 508 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 509 if (err) 510 return err; 511 DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); 512 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 513 514 for (i = 0; i < sc->sc_flsize; i++) { 515 sc->sc_flist[i] = EHCI_NULL; 516 } 517 518 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 519 520 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 521 KM_SLEEP); 522 if (sc->sc_softitds == NULL) 523 return ENOMEM; 524 LIST_INIT(&sc->sc_freeitds); 525 LIST_INIT(&sc->sc_freesitds); 526 TAILQ_INIT(&sc->sc_intrhead); 527 528 /* Set up the bus struct. */ 529 sc->sc_bus.ub_methods = &ehci_bus_methods; 530 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 531 532 sc->sc_eintrs = EHCI_NORMAL_INTRS; 533 534 /* 535 * Allocate the interrupt dummy QHs. These are arranged to give poll 536 * intervals that are powers of 2 times 1ms. 537 */ 538 for (i = 0; i < EHCI_INTRQHS; i++) { 539 sqh = ehci_alloc_sqh(sc); 540 if (sqh == NULL) { 541 err = ENOMEM; 542 goto bad1; 543 } 544 sc->sc_islots[i].sqh = sqh; 545 } 546 for (i = 0; i < EHCI_INTRQHS; i++) { 547 sqh = sc->sc_islots[i].sqh; 548 if (i == 0) { 549 /* The last (1ms) QH terminates. */ 550 sqh->qh.qh_link = EHCI_NULL; 551 sqh->next = NULL; 552 } else { 553 /* Otherwise the next QH has half the poll interval */ 554 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 555 sqh->qh.qh_link = htole32(sqh->next->physaddr | 556 EHCI_LINK_QH); 557 } 558 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 559 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 560 sqh->qh.qh_curqtd = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 562 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 563 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 564 sqh->sqtd = NULL; 565 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 566 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 567 } 568 /* Point the frame list at the last level (128ms). */ 569 for (i = 0; i < sc->sc_flsize; i++) { 570 int j; 571 572 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 573 revbits[i & (EHCI_MAX_POLLRATE-1)]; 574 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 575 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 576 i)].sqh->physaddr); 577 } 578 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 579 BUS_DMASYNC_PREWRITE); 580 581 /* Allocate dummy QH that starts the async list. */ 582 sqh = ehci_alloc_sqh(sc); 583 if (sqh == NULL) { 584 err = ENOMEM; 585 goto bad1; 586 } 587 /* Fill the QH */ 588 sqh->qh.qh_endp = 589 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 590 sqh->qh.qh_link = 591 htole32(sqh->physaddr | EHCI_LINK_QH); 592 sqh->qh.qh_curqtd = EHCI_NULL; 593 sqh->next = NULL; 594 /* Fill the overlay qTD */ 595 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 596 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 597 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 598 sqh->sqtd = NULL; 599 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 600 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 601 #ifdef EHCI_DEBUG 602 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 603 ehci_dump_sqh(sqh); 604 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 605 #endif 606 607 /* Point to async list */ 608 sc->sc_async_head = sqh; 609 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 610 611 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 612 613 /* Turn on controller */ 614 EOWRITE4(sc, EHCI_USBCMD, 615 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 616 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 617 EHCI_CMD_ASE | 618 EHCI_CMD_PSE | 619 EHCI_CMD_RS); 620 621 /* Take over port ownership */ 622 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 623 624 for (i = 0; i < 100; i++) { 625 usb_delay_ms(&sc->sc_bus, 1); 626 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 627 if (!hcr) 628 break; 629 } 630 if (hcr) { 631 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 632 return EIO; 633 } 634 635 /* Enable interrupts */ 636 DPRINTF("enabling interupts", 0, 0, 0, 0); 637 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 638 639 return 0; 640 641 #if 0 642 bad2: 643 ehci_free_sqh(sc, sc->sc_async_head); 644 #endif 645 bad1: 646 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 647 return err; 648 } 649 650 int 651 ehci_intr(void *v) 652 { 653 ehci_softc_t *sc = v; 654 int ret = 0; 655 656 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 657 658 if (sc == NULL) 659 return 0; 660 661 mutex_spin_enter(&sc->sc_intr_lock); 662 663 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 664 goto done; 665 666 /* If we get an interrupt while polling, then just ignore it. */ 667 if (sc->sc_bus.ub_usepolling) { 668 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 669 670 if (intrs) 671 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 672 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 673 goto done; 674 } 675 676 ret = ehci_intr1(sc); 677 678 done: 679 mutex_spin_exit(&sc->sc_intr_lock); 680 return ret; 681 } 682 683 Static int 684 ehci_intr1(ehci_softc_t *sc) 685 { 686 uint32_t intrs, eintrs; 687 688 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 689 690 /* In case the interrupt occurs before initialization has completed. */ 691 if (sc == NULL) { 692 #ifdef DIAGNOSTIC 693 printf("ehci_intr1: sc == NULL\n"); 694 #endif 695 return 0; 696 } 697 698 KASSERT(mutex_owned(&sc->sc_intr_lock)); 699 700 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 701 if (!intrs) 702 return 0; 703 704 eintrs = intrs & sc->sc_eintrs; 705 DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, 706 EOREAD4(sc, EHCI_USBSTS), eintrs); 707 if (!eintrs) 708 return 0; 709 710 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 711 if (eintrs & EHCI_STS_IAA) { 712 DPRINTF("door bell", 0, 0, 0, 0); 713 kpreempt_disable(); 714 KASSERT(sc->sc_doorbell_si != NULL); 715 softint_schedule(sc->sc_doorbell_si); 716 kpreempt_enable(); 717 eintrs &= ~EHCI_STS_IAA; 718 } 719 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 720 DPRINTF("INT=%d ERRINT=%d", 721 eintrs & EHCI_STS_INT ? 1 : 0, 722 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 723 usb_schedsoftintr(&sc->sc_bus); 724 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 725 } 726 if (eintrs & EHCI_STS_HSE) { 727 printf("%s: unrecoverable error, controller halted\n", 728 device_xname(sc->sc_dev)); 729 /* XXX what else */ 730 } 731 if (eintrs & EHCI_STS_PCD) { 732 kpreempt_disable(); 733 KASSERT(sc->sc_pcd_si != NULL); 734 softint_schedule(sc->sc_pcd_si); 735 kpreempt_enable(); 736 eintrs &= ~EHCI_STS_PCD; 737 } 738 739 if (eintrs != 0) { 740 /* Block unprocessed interrupts. */ 741 sc->sc_eintrs &= ~eintrs; 742 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 743 printf("%s: blocking intrs 0x%x\n", 744 device_xname(sc->sc_dev), eintrs); 745 } 746 747 return 1; 748 } 749 750 Static void 751 ehci_doorbell(void *addr) 752 { 753 ehci_softc_t *sc = addr; 754 755 mutex_enter(&sc->sc_lock); 756 cv_broadcast(&sc->sc_doorbell); 757 mutex_exit(&sc->sc_lock); 758 } 759 760 Static void 761 ehci_pcd(void *addr) 762 { 763 ehci_softc_t *sc = addr; 764 struct usbd_xfer *xfer; 765 u_char *p; 766 int i, m; 767 768 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 769 770 mutex_enter(&sc->sc_lock); 771 xfer = sc->sc_intrxfer; 772 773 if (xfer == NULL) { 774 /* Just ignore the change. */ 775 goto done; 776 } 777 778 p = xfer->ux_buf; 779 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 780 memset(p, 0, xfer->ux_length); 781 for (i = 1; i <= m; i++) { 782 /* Pick out CHANGE bits from the status reg. */ 783 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 784 p[i/8] |= 1 << (i%8); 785 if (i % 8 == 7) 786 DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); 787 } 788 xfer->ux_actlen = xfer->ux_length; 789 xfer->ux_status = USBD_NORMAL_COMPLETION; 790 791 usb_transfer_complete(xfer); 792 793 done: 794 mutex_exit(&sc->sc_lock); 795 } 796 797 Static void 798 ehci_softintr(void *v) 799 { 800 struct usbd_bus *bus = v; 801 ehci_softc_t *sc = EHCI_BUS2SC(bus); 802 struct ehci_xfer *ex, *nextex; 803 804 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 805 806 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 807 808 ex_completeq_t cq; 809 TAILQ_INIT(&cq); 810 811 /* 812 * The only explanation I can think of for why EHCI is as brain dead 813 * as UHCI interrupt-wise is that Intel was involved in both. 814 * An interrupt just tells us that something is done, we have no 815 * clue what, so we need to scan through all active transfers. :-( 816 */ 817 818 /* 819 * ehci_idone will remove transfer from sc->sc_intrhead if it's 820 * complete and add to our cq list 821 * 822 */ 823 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 824 switch (ex->ex_type) { 825 case EX_CTRL: 826 case EX_BULK: 827 case EX_INTR: 828 ehci_check_qh_intr(sc, ex, &cq); 829 break; 830 case EX_ISOC: 831 ehci_check_itd_intr(sc, ex, &cq); 832 break; 833 case EX_FS_ISOC: 834 ehci_check_sitd_intr(sc, ex, &cq); 835 break; 836 default: 837 KASSERT(false); 838 } 839 840 } 841 842 /* 843 * We abuse ex_next for the interrupt and complete lists and 844 * interrupt transfers will get re-added here so use 845 * the _SAFE version of TAILQ_FOREACH. 846 */ 847 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 848 usb_transfer_complete(&ex->ex_xfer); 849 } 850 851 /* Schedule a callout to catch any dropped transactions. */ 852 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 853 !TAILQ_EMPTY(&sc->sc_intrhead)) 854 callout_reset(&sc->sc_tmo_intrlist, 855 hz, ehci_intrlist_timeout, sc); 856 857 if (sc->sc_softwake) { 858 sc->sc_softwake = 0; 859 cv_broadcast(&sc->sc_softwake_cv); 860 } 861 } 862 863 Static void 864 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 865 { 866 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 867 uint32_t status; 868 869 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 870 871 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 872 873 if (ex->ex_type == EX_CTRL) { 874 fsqtd = ex->ex_setup; 875 lsqtd = ex->ex_status; 876 } else { 877 fsqtd = ex->ex_sqtdstart; 878 lsqtd = ex->ex_sqtdend; 879 } 880 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 881 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 882 883 /* 884 * If the last TD is still active we need to check whether there 885 * is an error somewhere in the middle, or whether there was a 886 * short packet (SPD and not ACTIVE). 887 */ 888 usb_syncmem(&lsqtd->dma, 889 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 890 sizeof(lsqtd->qtd.qtd_status), 891 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 892 status = le32toh(lsqtd->qtd.qtd_status); 893 usb_syncmem(&lsqtd->dma, 894 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 895 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 896 if (status & EHCI_QTD_ACTIVE) { 897 DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); 898 899 /* last qTD has already been checked */ 900 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 901 usb_syncmem(&sqtd->dma, 902 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 903 sizeof(sqtd->qtd.qtd_status), 904 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 905 status = le32toh(sqtd->qtd.qtd_status); 906 usb_syncmem(&sqtd->dma, 907 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 908 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 909 /* If there's an active QTD the xfer isn't done. */ 910 if (status & EHCI_QTD_ACTIVE) 911 break; 912 /* Any kind of error makes the xfer done. */ 913 if (status & EHCI_QTD_HALTED) 914 goto done; 915 /* Handle short packets */ 916 if (EHCI_QTD_GET_BYTES(status) != 0) { 917 /* 918 * If we get here for a control transfer then 919 * we need to let the hardware complete the 920 * status phase. That is, we're not done 921 * quite yet. 922 * 923 * Otherwise, we're done. 924 */ 925 if (ex->ex_type == EX_CTRL) { 926 break; 927 } 928 goto done; 929 } 930 } 931 DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, 932 0, 0); 933 #ifdef EHCI_DEBUG 934 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 935 ehci_dump_sqtds(ex->ex_sqtdstart); 936 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 937 #endif 938 return; 939 } 940 done: 941 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 942 callout_stop(&ex->ex_xfer.ux_callout); 943 ehci_idone(ex, cq); 944 } 945 946 Static void 947 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 948 { 949 ehci_soft_itd_t *itd; 950 int i; 951 952 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 953 954 KASSERT(mutex_owned(&sc->sc_lock)); 955 956 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 957 return; 958 959 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 960 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 961 962 itd = ex->ex_itdend; 963 964 /* 965 * check no active transfers in last itd, meaning we're finished 966 */ 967 968 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 969 sizeof(itd->itd.itd_ctl), 970 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 971 972 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 973 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 974 break; 975 } 976 977 if (i == EHCI_ITD_NUFRAMES) { 978 goto done; /* All 8 descriptors inactive, it's done */ 979 } 980 981 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 982 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 983 984 DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); 985 return; 986 done: 987 DPRINTF("ex %p done", ex, 0, 0, 0); 988 callout_stop(&ex->ex_xfer.ux_callout); 989 ehci_idone(ex, cq); 990 } 991 992 void 993 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 994 { 995 ehci_soft_sitd_t *sitd; 996 997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 998 999 KASSERT(mutex_owned(&sc->sc_lock)); 1000 1001 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1002 return; 1003 1004 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1005 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1006 1007 sitd = ex->ex_sitdend; 1008 1009 /* 1010 * check no active transfers in last sitd, meaning we're finished 1011 */ 1012 1013 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1014 sizeof(sitd->sitd.sitd_trans), 1015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1016 1017 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1021 1022 if (active) 1023 return; 1024 1025 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 1026 callout_stop(&(ex->ex_xfer.ux_callout)); 1027 ehci_idone(ex, cq); 1028 } 1029 1030 1031 Static void 1032 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1033 { 1034 struct usbd_xfer *xfer = &ex->ex_xfer; 1035 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1036 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1037 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1038 uint32_t status = 0, nstatus = 0; 1039 int actlen = 0; 1040 1041 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1042 1043 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1044 1045 DPRINTF("ex=%p", ex, 0, 0, 0); 1046 1047 if (xfer->ux_status == USBD_CANCELLED || 1048 xfer->ux_status == USBD_TIMEOUT) { 1049 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1050 return; 1051 } 1052 1053 #ifdef DIAGNOSTIC 1054 #ifdef EHCI_DEBUG 1055 if (ex->ex_isdone) { 1056 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1057 ehci_dump_exfer(ex); 1058 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1059 } 1060 #endif 1061 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1062 ex->ex_type, xfer->ux_status); 1063 ex->ex_isdone = true; 1064 #endif 1065 1066 DPRINTF("xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1067 1068 /* The transfer is done, compute actual length and status. */ 1069 if (ex->ex_type == EX_ISOC) { 1070 /* HS isoc transfer */ 1071 1072 struct ehci_soft_itd *itd; 1073 int i, nframes, len, uframes; 1074 1075 nframes = 0; 1076 1077 #ifdef EHCI_DEBUG 1078 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1079 ehci_dump_itds(ex->ex_itdstart); 1080 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1081 #endif 1082 1083 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1084 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1085 1086 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1087 usb_syncmem(&itd->dma, 1088 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1089 sizeof(itd->itd.itd_ctl), 1090 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1091 1092 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1093 /* 1094 * XXX - driver didn't fill in the frame full 1095 * of uframes. This leads to scheduling 1096 * inefficiencies, but working around 1097 * this doubles complexity of tracking 1098 * an xfer. 1099 */ 1100 if (nframes >= xfer->ux_nframes) 1101 break; 1102 1103 status = le32toh(itd->itd.itd_ctl[i]); 1104 len = EHCI_ITD_GET_LEN(status); 1105 if (EHCI_ITD_GET_STATUS(status) != 0) 1106 len = 0; /*No valid data on error*/ 1107 1108 xfer->ux_frlengths[nframes++] = len; 1109 actlen += len; 1110 } 1111 usb_syncmem(&itd->dma, 1112 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1113 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1114 1115 if (nframes >= xfer->ux_nframes) 1116 break; 1117 } 1118 1119 xfer->ux_actlen = actlen; 1120 xfer->ux_status = USBD_NORMAL_COMPLETION; 1121 goto end; 1122 } else if (ex->ex_type == EX_FS_ISOC) { 1123 /* FS isoc transfer */ 1124 struct ehci_soft_sitd *sitd; 1125 int nframes, len; 1126 1127 nframes = 0; 1128 1129 for (sitd = ex->ex_sitdstart; sitd != NULL; 1130 sitd = sitd->xfer_next) { 1131 usb_syncmem(&sitd->dma, 1132 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1133 sizeof(sitd->sitd.sitd_trans), 1134 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1135 1136 /* 1137 * XXX - driver didn't fill in the frame full 1138 * of uframes. This leads to scheduling 1139 * inefficiencies, but working around 1140 * this doubles complexity of tracking 1141 * an xfer. 1142 */ 1143 if (nframes >= xfer->ux_nframes) 1144 break; 1145 1146 status = le32toh(sitd->sitd.sitd_trans); 1147 usb_syncmem(&sitd->dma, 1148 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1149 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1150 1151 len = EHCI_SITD_GET_LEN(status); 1152 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1153 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1154 /* No valid data on error */ 1155 len = xfer->ux_frlengths[nframes]; 1156 } 1157 1158 /* 1159 * frlengths[i]: # of bytes to send 1160 * len: # of bytes host didn't send 1161 */ 1162 xfer->ux_frlengths[nframes] -= len; 1163 /* frlengths[i]: # of bytes host sent */ 1164 actlen += xfer->ux_frlengths[nframes++]; 1165 1166 if (nframes >= xfer->ux_nframes) 1167 break; 1168 } 1169 1170 xfer->ux_actlen = actlen; 1171 xfer->ux_status = USBD_NORMAL_COMPLETION; 1172 goto end; 1173 } 1174 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1175 ex->ex_type == EX_BULK); 1176 1177 /* Continue processing xfers using queue heads */ 1178 if (ex->ex_type == EX_CTRL) { 1179 fsqtd = ex->ex_setup; 1180 lsqtd = ex->ex_status; 1181 } else { 1182 fsqtd = ex->ex_sqtdstart; 1183 lsqtd = ex->ex_sqtdend; 1184 } 1185 #ifdef EHCI_DEBUG 1186 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1187 ehci_dump_sqtds(fsqtd); 1188 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1189 #endif 1190 1191 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1192 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1193 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1194 nstatus = le32toh(sqtd->qtd.qtd_status); 1195 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1196 BUS_DMASYNC_PREREAD); 1197 if (nstatus & EHCI_QTD_ACTIVE) 1198 break; 1199 1200 status = nstatus; 1201 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1202 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1203 } 1204 1205 /* 1206 * If there are left over TDs we need to update the toggle. 1207 * The default pipe doesn't need it since control transfers 1208 * start the toggle at 0 every time. 1209 * For a short transfer we need to update the toggle for the missing 1210 * packets within the qTD. 1211 */ 1212 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1213 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1214 DPRINTF("toggle update status=0x%08x nstatus=0x%08x", 1215 status, nstatus, 0, 0); 1216 #if 0 1217 ehci_dump_sqh(epipe->sqh); 1218 ehci_dump_sqtds(ex->ex_sqtdstart); 1219 #endif 1220 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1221 } 1222 1223 DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, 1224 status, 0); 1225 xfer->ux_actlen = actlen; 1226 if (status & EHCI_QTD_HALTED) { 1227 #ifdef EHCI_DEBUG 1228 DPRINTF("halted addr=%d endpt=0x%02x", 1229 xfer->ux_pipe->up_dev->ud_addr, 1230 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1231 0, 0); 1232 DPRINTF("cerr=%d pid=%d", 1233 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1234 0, 0); 1235 DPRINTF("active =%d halted=%d buferr=%d babble=%d", 1236 status & EHCI_QTD_ACTIVE ? 1 : 0, 1237 status & EHCI_QTD_HALTED ? 1 : 0, 1238 status & EHCI_QTD_BUFERR ? 1 : 0, 1239 status & EHCI_QTD_BABBLE ? 1 : 0); 1240 1241 DPRINTF("xacterr=%d missed=%d split =%d ping =%d", 1242 status & EHCI_QTD_XACTERR ? 1 : 0, 1243 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1244 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1245 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1246 1247 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1248 ehci_dump_sqh(epipe->sqh); 1249 ehci_dump_sqtds(ex->ex_sqtdstart); 1250 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1251 #endif 1252 /* low&full speed has an extra error flag */ 1253 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1254 EHCI_QH_SPEED_HIGH) 1255 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1256 else 1257 status &= EHCI_QTD_STATERRS; 1258 if (status == 0) /* no other errors means a stall */ { 1259 xfer->ux_status = USBD_STALLED; 1260 } else { 1261 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1262 } 1263 /* XXX need to reset TT on missed microframe */ 1264 if (status & EHCI_QTD_MISSEDMICRO) { 1265 printf("%s: missed microframe, TT reset not " 1266 "implemented, hub might be inoperational\n", 1267 device_xname(sc->sc_dev)); 1268 } 1269 } else { 1270 xfer->ux_status = USBD_NORMAL_COMPLETION; 1271 } 1272 1273 end: 1274 1275 ehci_del_intr_list(sc, ex); 1276 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1277 1278 DPRINTF("ex=%p done", ex, 0, 0, 0); 1279 } 1280 1281 Static void 1282 ehci_poll(struct usbd_bus *bus) 1283 { 1284 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1285 1286 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1287 1288 #ifdef EHCI_DEBUG 1289 static int last; 1290 int new; 1291 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1292 if (new != last) { 1293 DPRINTF("intrs=0x%04x", new, 0, 0, 0); 1294 last = new; 1295 } 1296 #endif 1297 1298 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1299 mutex_spin_enter(&sc->sc_intr_lock); 1300 ehci_intr1(sc); 1301 mutex_spin_exit(&sc->sc_intr_lock); 1302 } 1303 } 1304 1305 void 1306 ehci_childdet(device_t self, device_t child) 1307 { 1308 struct ehci_softc *sc = device_private(self); 1309 1310 KASSERT(sc->sc_child == child); 1311 sc->sc_child = NULL; 1312 } 1313 1314 int 1315 ehci_detach(struct ehci_softc *sc, int flags) 1316 { 1317 int rv = 0; 1318 1319 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1320 1321 if (sc->sc_child != NULL) 1322 rv = config_detach(sc->sc_child, flags); 1323 1324 if (rv != 0) 1325 return rv; 1326 1327 callout_halt(&sc->sc_tmo_intrlist, NULL); 1328 callout_destroy(&sc->sc_tmo_intrlist); 1329 1330 /* XXX free other data structures XXX */ 1331 if (sc->sc_softitds) 1332 kmem_free(sc->sc_softitds, 1333 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1334 cv_destroy(&sc->sc_doorbell); 1335 cv_destroy(&sc->sc_softwake_cv); 1336 1337 #if 0 1338 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1339 1340 softint_disestablish(sc->sc_doorbell_si); 1341 softint_disestablish(sc->sc_pcd_si); 1342 1343 mutex_destroy(&sc->sc_lock); 1344 mutex_destroy(&sc->sc_intr_lock); 1345 #endif 1346 1347 pool_cache_destroy(sc->sc_xferpool); 1348 1349 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1350 1351 return rv; 1352 } 1353 1354 1355 int 1356 ehci_activate(device_t self, enum devact act) 1357 { 1358 struct ehci_softc *sc = device_private(self); 1359 1360 switch (act) { 1361 case DVACT_DEACTIVATE: 1362 sc->sc_dying = 1; 1363 return 0; 1364 default: 1365 return EOPNOTSUPP; 1366 } 1367 } 1368 1369 /* 1370 * Handle suspend/resume. 1371 * 1372 * We need to switch to polling mode here, because this routine is 1373 * called from an interrupt context. This is all right since we 1374 * are almost suspended anyway. 1375 * 1376 * Note that this power handler isn't to be registered directly; the 1377 * bus glue needs to call out to it. 1378 */ 1379 bool 1380 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1381 { 1382 ehci_softc_t *sc = device_private(dv); 1383 int i; 1384 uint32_t cmd, hcr; 1385 1386 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1387 1388 mutex_spin_enter(&sc->sc_intr_lock); 1389 sc->sc_bus.ub_usepolling++; 1390 mutex_spin_exit(&sc->sc_intr_lock); 1391 1392 for (i = 1; i <= sc->sc_noport; i++) { 1393 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1394 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1395 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1396 } 1397 1398 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1399 1400 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1401 EOWRITE4(sc, EHCI_USBCMD, cmd); 1402 1403 for (i = 0; i < 100; i++) { 1404 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1405 if (hcr == 0) 1406 break; 1407 1408 usb_delay_ms(&sc->sc_bus, 1); 1409 } 1410 if (hcr != 0) 1411 printf("%s: reset timeout\n", device_xname(dv)); 1412 1413 cmd &= ~EHCI_CMD_RS; 1414 EOWRITE4(sc, EHCI_USBCMD, cmd); 1415 1416 for (i = 0; i < 100; i++) { 1417 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1418 if (hcr == EHCI_STS_HCH) 1419 break; 1420 1421 usb_delay_ms(&sc->sc_bus, 1); 1422 } 1423 if (hcr != EHCI_STS_HCH) 1424 printf("%s: config timeout\n", device_xname(dv)); 1425 1426 mutex_spin_enter(&sc->sc_intr_lock); 1427 sc->sc_bus.ub_usepolling--; 1428 mutex_spin_exit(&sc->sc_intr_lock); 1429 1430 return true; 1431 } 1432 1433 bool 1434 ehci_resume(device_t dv, const pmf_qual_t *qual) 1435 { 1436 ehci_softc_t *sc = device_private(dv); 1437 int i; 1438 uint32_t cmd, hcr; 1439 1440 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1441 1442 /* restore things in case the bios sucks */ 1443 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1444 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1445 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1446 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1447 1448 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1449 1450 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1451 1452 hcr = 0; 1453 for (i = 1; i <= sc->sc_noport; i++) { 1454 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1455 if ((cmd & EHCI_PS_PO) == 0 && 1456 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1457 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1458 hcr = 1; 1459 } 1460 } 1461 1462 if (hcr) { 1463 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1464 1465 for (i = 1; i <= sc->sc_noport; i++) { 1466 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1467 if ((cmd & EHCI_PS_PO) == 0 && 1468 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1469 EOWRITE4(sc, EHCI_PORTSC(i), 1470 cmd & ~EHCI_PS_FPR); 1471 } 1472 } 1473 1474 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1475 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1476 1477 for (i = 0; i < 100; i++) { 1478 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1479 if (hcr != EHCI_STS_HCH) 1480 break; 1481 1482 usb_delay_ms(&sc->sc_bus, 1); 1483 } 1484 if (hcr == EHCI_STS_HCH) 1485 printf("%s: config timeout\n", device_xname(dv)); 1486 1487 return true; 1488 } 1489 1490 /* 1491 * Shut down the controller when the system is going down. 1492 */ 1493 bool 1494 ehci_shutdown(device_t self, int flags) 1495 { 1496 ehci_softc_t *sc = device_private(self); 1497 1498 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1499 1500 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1501 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1502 return true; 1503 } 1504 1505 Static struct usbd_xfer * 1506 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1507 { 1508 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1509 struct usbd_xfer *xfer; 1510 1511 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1512 if (xfer != NULL) { 1513 memset(xfer, 0, sizeof(struct ehci_xfer)); 1514 #ifdef DIAGNOSTIC 1515 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1516 ex->ex_isdone = true; 1517 xfer->ux_state = XFER_BUSY; 1518 #endif 1519 } 1520 return xfer; 1521 } 1522 1523 Static void 1524 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1525 { 1526 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1527 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1528 1529 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1530 xfer->ux_state); 1531 KASSERT(ex->ex_isdone); 1532 1533 #ifdef DIAGNOSTIC 1534 xfer->ux_state = XFER_FREE; 1535 #endif 1536 1537 pool_cache_put(sc->sc_xferpool, xfer); 1538 } 1539 1540 Static void 1541 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1542 { 1543 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1544 1545 *lock = &sc->sc_lock; 1546 } 1547 1548 Static void 1549 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1550 { 1551 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1552 1553 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1554 1555 DPRINTF("epipe=%p status=0x%08x", epipe, 1556 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1557 #ifdef EHCI_DEBUG 1558 if (ehcidebug) 1559 usbd_dump_pipe(pipe); 1560 #endif 1561 epipe->nexttoggle = 0; 1562 } 1563 1564 Static void 1565 ehci_noop(struct usbd_pipe *pipe) 1566 { 1567 } 1568 1569 #ifdef EHCI_DEBUG 1570 /* 1571 * Unused function - this is meant to be called from a kernel 1572 * debugger. 1573 */ 1574 void 1575 ehci_dump(void) 1576 { 1577 ehci_softc_t *sc = theehci; 1578 int i; 1579 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1580 EOREAD4(sc, EHCI_USBCMD), 1581 EOREAD4(sc, EHCI_USBSTS), 1582 EOREAD4(sc, EHCI_USBINTR)); 1583 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1584 EOREAD4(sc, EHCI_FRINDEX), 1585 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1586 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1587 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1588 for (i = 1; i <= sc->sc_noport; i++) 1589 printf("port %d status=0x%08x\n", i, 1590 EOREAD4(sc, EHCI_PORTSC(i))); 1591 } 1592 1593 Static void 1594 ehci_dump_regs(ehci_softc_t *sc) 1595 { 1596 int i; 1597 1598 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1599 1600 DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1601 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1602 EOREAD4(sc, EHCI_USBINTR), 0); 1603 DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1604 "async = 0x%08x", 1605 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1606 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1607 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1608 for (i = 1; i <= sc->sc_noport; i += 2) { 1609 if (i == sc->sc_noport) { 1610 DPRINTF("port %d status = 0x%08x", i, 1611 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1612 } else { 1613 DPRINTF( 1614 "port %d status = 0x%08x port %d status = 0x%08x", 1615 i, EOREAD4(sc, EHCI_PORTSC(i)), 1616 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1617 } 1618 } 1619 } 1620 1621 #define ehci_dump_link(link, type) do { \ 1622 DPRINTF(" link 0x%08x (T = %d):", \ 1623 link, \ 1624 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1625 if (type) { \ 1626 DPRINTF( \ 1627 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1628 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1629 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1630 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1631 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1632 } \ 1633 } while(0) 1634 1635 Static void 1636 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1637 { 1638 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1639 int i; 1640 uint32_t stop = 0; 1641 1642 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1643 ehci_dump_sqtd(sqtd); 1644 usb_syncmem(&sqtd->dma, 1645 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1646 sizeof(sqtd->qtd), 1647 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1648 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1649 usb_syncmem(&sqtd->dma, 1650 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1651 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1652 } 1653 if (!stop) 1654 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1655 } 1656 1657 Static void 1658 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1659 { 1660 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1661 1662 usb_syncmem(&sqtd->dma, sqtd->offs, 1663 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1664 1665 DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1666 ehci_dump_qtd(&sqtd->qtd); 1667 1668 usb_syncmem(&sqtd->dma, sqtd->offs, 1669 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1670 } 1671 1672 Static void 1673 ehci_dump_qtd(ehci_qtd_t *qtd) 1674 { 1675 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1676 uint32_t s = le32toh(qtd->qtd_status); 1677 1678 DPRINTFN(10, 1679 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1680 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1681 DPRINTFN(10, 1682 " toggle = %d ioc = %d bytes = %#x " 1683 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1684 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1685 DPRINTFN(10, 1686 " cerr = %d pid = %d stat = %x", 1687 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1688 0); 1689 DPRINTFN(10, 1690 "active =%d halted=%d buferr=%d babble=%d", 1691 s & EHCI_QTD_ACTIVE ? 1 : 0, 1692 s & EHCI_QTD_HALTED ? 1 : 0, 1693 s & EHCI_QTD_BUFERR ? 1 : 0, 1694 s & EHCI_QTD_BABBLE ? 1 : 0); 1695 DPRINTFN(10, 1696 "xacterr=%d missed=%d split =%d ping =%d", 1697 s & EHCI_QTD_XACTERR ? 1 : 0, 1698 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1699 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1700 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1701 DPRINTFN(10, 1702 "buffer[0] = %#x buffer[1] = %#x " 1703 "buffer[2] = %#x buffer[3] = %#x", 1704 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1705 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1706 DPRINTFN(10, 1707 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1708 } 1709 1710 Static void 1711 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1712 { 1713 ehci_qh_t *qh = &sqh->qh; 1714 ehci_link_t link; 1715 uint32_t endp, endphub; 1716 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1717 1718 usb_syncmem(&sqh->dma, sqh->offs, 1719 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1720 1721 DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1722 link = le32toh(qh->qh_link); 1723 ehci_dump_link(link, true); 1724 1725 endp = le32toh(qh->qh_endp); 1726 DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); 1727 DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", 1728 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1729 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1730 DPRINTFN(10, " dtc = %d hrecl = %d", 1731 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1732 DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", 1733 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1734 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1735 1736 endphub = le32toh(qh->qh_endphub); 1737 DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); 1738 DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", 1739 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1740 DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", 1741 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1742 EHCI_QH_GET_MULT(endphub), 0); 1743 1744 link = le32toh(qh->qh_curqtd); 1745 ehci_dump_link(link, false); 1746 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1747 ehci_dump_qtd(&qh->qh_qtd); 1748 1749 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1750 BUS_DMASYNC_PREREAD); 1751 } 1752 1753 Static void 1754 ehci_dump_itds(ehci_soft_itd_t *itd) 1755 { 1756 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1757 int i; 1758 uint32_t stop = 0; 1759 1760 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1761 ehci_dump_itd(itd); 1762 usb_syncmem(&itd->dma, 1763 itd->offs + offsetof(ehci_itd_t, itd_next), 1764 sizeof(itd->itd), 1765 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1766 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1767 usb_syncmem(&itd->dma, 1768 itd->offs + offsetof(ehci_itd_t, itd_next), 1769 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1770 } 1771 if (!stop) 1772 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1773 } 1774 1775 Static void 1776 ehci_dump_itd(struct ehci_soft_itd *itd) 1777 { 1778 ehci_isoc_trans_t t; 1779 ehci_isoc_bufr_ptr_t b, b2, b3; 1780 int i; 1781 1782 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1783 1784 DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); 1785 1786 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1787 t = le32toh(itd->itd.itd_ctl[i]); 1788 DPRINTF("ITDctl %d: stat = %x len = %x", 1789 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1790 DPRINTF(" ioc = %x pg = %x offs = %x", 1791 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1792 EHCI_ITD_GET_OFFS(t), 0); 1793 } 1794 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1795 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1796 DPRINTF(" %x", 1797 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1798 1799 b = le32toh(itd->itd.itd_bufr[0]); 1800 b2 = le32toh(itd->itd.itd_bufr[1]); 1801 b3 = le32toh(itd->itd.itd_bufr[2]); 1802 DPRINTF(" ep = %x daddr = %x dir = %d", 1803 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1804 DPRINTF(" maxpkt = %x multi = %x", 1805 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1806 } 1807 1808 Static void 1809 ehci_dump_sitd(struct ehci_soft_itd *itd) 1810 { 1811 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1812 1813 DPRINTF("SITD %p next = %p prev = %p", 1814 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1815 DPRINTF(" xfernext=%p physaddr=%X slot=%d", 1816 itd->xfer_next, itd->physaddr, itd->slot, 0); 1817 } 1818 1819 Static void 1820 ehci_dump_exfer(struct ehci_xfer *ex) 1821 { 1822 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1823 1824 DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, 1825 ex->ex_isdone, 0); 1826 1827 switch (ex->ex_type) { 1828 case EX_CTRL: 1829 DPRINTF(" setup = %p data = %p status = %p", 1830 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1831 break; 1832 case EX_BULK: 1833 case EX_INTR: 1834 DPRINTF(" qtdstart = %p qtdend = %p", 1835 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1836 break; 1837 case EX_ISOC: 1838 DPRINTF(" itdstart = %p itdend = %p", 1839 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1840 break; 1841 case EX_FS_ISOC: 1842 DPRINTF(" sitdstart = %p sitdend = %p", 1843 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1844 break; 1845 default: 1846 DPRINTF(" unknown type", 0, 0, 0, 0); 1847 } 1848 } 1849 #endif 1850 1851 Static usbd_status 1852 ehci_open(struct usbd_pipe *pipe) 1853 { 1854 struct usbd_device *dev = pipe->up_dev; 1855 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1856 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1857 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1858 uint8_t addr = dev->ud_addr; 1859 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1860 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1861 ehci_soft_qh_t *sqh; 1862 usbd_status err; 1863 int ival, speed, naks; 1864 int hshubaddr, hshubport; 1865 1866 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1867 1868 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1869 ed->bEndpointAddress, rhaddr); 1870 1871 if (dev->ud_myhsport) { 1872 /* 1873 * When directly attached FS/LS device while doing embedded 1874 * transaction translations and we are the hub, set the hub 1875 * address to 0 (us). 1876 */ 1877 if (!(sc->sc_flags & EHCIF_ETTF) 1878 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1879 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1880 } else { 1881 hshubaddr = 0; 1882 } 1883 hshubport = dev->ud_myhsport->up_portno; 1884 } else { 1885 hshubaddr = 0; 1886 hshubport = 0; 1887 } 1888 1889 if (sc->sc_dying) 1890 return USBD_IOERROR; 1891 1892 /* toggle state needed for bulk endpoints */ 1893 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1894 1895 if (addr == rhaddr) { 1896 switch (ed->bEndpointAddress) { 1897 case USB_CONTROL_ENDPOINT: 1898 pipe->up_methods = &roothub_ctrl_methods; 1899 break; 1900 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1901 pipe->up_methods = &ehci_root_intr_methods; 1902 break; 1903 default: 1904 DPRINTF("bad bEndpointAddress 0x%02x", 1905 ed->bEndpointAddress, 0, 0, 0); 1906 return USBD_INVAL; 1907 } 1908 return USBD_NORMAL_COMPLETION; 1909 } 1910 1911 /* XXX All this stuff is only valid for async. */ 1912 switch (dev->ud_speed) { 1913 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1914 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1915 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1916 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1917 } 1918 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1919 DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, 1920 0); 1921 return USBD_INVAL; 1922 } 1923 1924 /* 1925 * For interrupt transfer, nak throttling must be disabled, but for 1926 * the other transfer type, nak throttling should be enabled from the 1927 * viewpoint that avoids the memory thrashing. 1928 */ 1929 naks = (xfertype == UE_INTERRUPT) ? 0 1930 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1931 1932 /* Allocate sqh for everything, save isoc xfers */ 1933 if (xfertype != UE_ISOCHRONOUS) { 1934 sqh = ehci_alloc_sqh(sc); 1935 if (sqh == NULL) 1936 return USBD_NOMEM; 1937 /* qh_link filled when the QH is added */ 1938 sqh->qh.qh_endp = htole32( 1939 EHCI_QH_SET_ADDR(addr) | 1940 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1941 EHCI_QH_SET_EPS(speed) | 1942 EHCI_QH_DTC | 1943 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1944 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1945 EHCI_QH_CTL : 0) | 1946 EHCI_QH_SET_NRL(naks) 1947 ); 1948 sqh->qh.qh_endphub = htole32( 1949 EHCI_QH_SET_MULT(1) | 1950 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1951 ); 1952 if (speed != EHCI_QH_SPEED_HIGH) 1953 sqh->qh.qh_endphub |= htole32( 1954 EHCI_QH_SET_PORT(hshubport) | 1955 EHCI_QH_SET_HUBA(hshubaddr) | 1956 (xfertype == UE_INTERRUPT ? 1957 EHCI_QH_SET_CMASK(0x08) : 0) 1958 ); 1959 sqh->qh.qh_curqtd = EHCI_NULL; 1960 /* Fill the overlay qTD */ 1961 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1962 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1963 sqh->qh.qh_qtd.qtd_status = htole32(0); 1964 1965 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1966 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1967 epipe->sqh = sqh; 1968 } else { 1969 sqh = NULL; 1970 } /*xfertype == UE_ISOC*/ 1971 1972 switch (xfertype) { 1973 case UE_CONTROL: 1974 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1975 0, &epipe->ctrl.reqdma); 1976 #ifdef EHCI_DEBUG 1977 if (err) 1978 printf("ehci_open: usb_allocmem()=%d\n", err); 1979 #endif 1980 if (err) 1981 goto bad; 1982 pipe->up_methods = &ehci_device_ctrl_methods; 1983 mutex_enter(&sc->sc_lock); 1984 ehci_add_qh(sc, sqh, sc->sc_async_head); 1985 mutex_exit(&sc->sc_lock); 1986 break; 1987 case UE_BULK: 1988 pipe->up_methods = &ehci_device_bulk_methods; 1989 mutex_enter(&sc->sc_lock); 1990 ehci_add_qh(sc, sqh, sc->sc_async_head); 1991 mutex_exit(&sc->sc_lock); 1992 break; 1993 case UE_INTERRUPT: 1994 pipe->up_methods = &ehci_device_intr_methods; 1995 ival = pipe->up_interval; 1996 if (ival == USBD_DEFAULT_INTERVAL) { 1997 if (speed == EHCI_QH_SPEED_HIGH) { 1998 if (ed->bInterval > 16) { 1999 /* 2000 * illegal with high-speed, but there 2001 * were documentation bugs in the spec, 2002 * so be generous 2003 */ 2004 ival = 256; 2005 } else 2006 ival = (1 << (ed->bInterval - 1)) / 8; 2007 } else 2008 ival = ed->bInterval; 2009 } 2010 err = ehci_device_setintr(sc, sqh, ival); 2011 if (err) 2012 goto bad; 2013 break; 2014 case UE_ISOCHRONOUS: 2015 pipe->up_serialise = false; 2016 if (speed == EHCI_QH_SPEED_HIGH) 2017 pipe->up_methods = &ehci_device_isoc_methods; 2018 else 2019 pipe->up_methods = &ehci_device_fs_isoc_methods; 2020 if (ed->bInterval == 0 || ed->bInterval > 16) { 2021 printf("ehci: opening pipe with invalid bInterval\n"); 2022 err = USBD_INVAL; 2023 goto bad; 2024 } 2025 if (UGETW(ed->wMaxPacketSize) == 0) { 2026 printf("ehci: zero length endpoint open request\n"); 2027 err = USBD_INVAL; 2028 goto bad; 2029 } 2030 epipe->isoc.next_frame = 0; 2031 epipe->isoc.cur_xfers = 0; 2032 break; 2033 default: 2034 DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); 2035 err = USBD_INVAL; 2036 goto bad; 2037 } 2038 return USBD_NORMAL_COMPLETION; 2039 2040 bad: 2041 if (sqh != NULL) { 2042 mutex_enter(&sc->sc_lock); 2043 ehci_free_sqh(sc, sqh); 2044 mutex_exit(&sc->sc_lock); 2045 } 2046 return err; 2047 } 2048 2049 /* 2050 * Add an ED to the schedule. Called with USB lock held. 2051 */ 2052 Static void 2053 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2054 { 2055 2056 KASSERT(mutex_owned(&sc->sc_lock)); 2057 2058 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2059 2060 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2061 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2062 2063 sqh->next = head->next; 2064 sqh->qh.qh_link = head->qh.qh_link; 2065 2066 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2067 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2068 2069 head->next = sqh; 2070 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2071 2072 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2073 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2074 2075 #ifdef EHCI_DEBUG 2076 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2077 ehci_dump_sqh(sqh); 2078 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2079 #endif 2080 } 2081 2082 /* 2083 * Remove an ED from the schedule. Called with USB lock held. 2084 */ 2085 Static void 2086 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2087 { 2088 ehci_soft_qh_t *p; 2089 2090 KASSERT(mutex_owned(&sc->sc_lock)); 2091 2092 /* XXX */ 2093 for (p = head; p != NULL && p->next != sqh; p = p->next) 2094 ; 2095 if (p == NULL) 2096 panic("ehci_rem_qh: ED not found"); 2097 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2098 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2099 p->next = sqh->next; 2100 p->qh.qh_link = sqh->qh.qh_link; 2101 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2102 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2103 2104 ehci_sync_hc(sc); 2105 } 2106 2107 Static void 2108 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2109 { 2110 int i; 2111 uint32_t status; 2112 2113 /* Save toggle bit and ping status. */ 2114 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2115 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2116 status = sqh->qh.qh_qtd.qtd_status & 2117 htole32(EHCI_QTD_TOGGLE_MASK | 2118 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2119 /* Set HALTED to make hw leave it alone. */ 2120 sqh->qh.qh_qtd.qtd_status = 2121 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2122 usb_syncmem(&sqh->dma, 2123 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2124 sizeof(sqh->qh.qh_qtd.qtd_status), 2125 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2126 sqh->qh.qh_curqtd = 0; 2127 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2128 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2129 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2130 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2131 sqh->sqtd = sqtd; 2132 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2133 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2134 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2135 sqh->qh.qh_qtd.qtd_status = status; 2136 usb_syncmem(&sqh->dma, 2137 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2138 sizeof(sqh->qh.qh_qtd.qtd_status), 2139 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2140 } 2141 2142 /* 2143 * Ensure that the HC has released all references to the QH. We do this 2144 * by asking for a Async Advance Doorbell interrupt and then we wait for 2145 * the interrupt. 2146 * To make this easier we first obtain exclusive use of the doorbell. 2147 */ 2148 Static void 2149 ehci_sync_hc(ehci_softc_t *sc) 2150 { 2151 int error __diagused; 2152 2153 KASSERT(mutex_owned(&sc->sc_lock)); 2154 2155 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2156 2157 if (sc->sc_dying) { 2158 DPRINTF("dying", 0, 0, 0, 0); 2159 return; 2160 } 2161 /* ask for doorbell */ 2162 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2163 DPRINTF("cmd = 0x%08x sts = 0x%08x", 2164 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2165 2166 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2167 2168 DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", 2169 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2170 #ifdef DIAGNOSTIC 2171 if (error) 2172 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2173 #endif 2174 } 2175 2176 Static void 2177 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2178 { 2179 2180 KASSERT(mutex_owned(&sc->sc_lock)); 2181 2182 for (; itd != NULL; itd = itd->xfer_next) { 2183 struct ehci_soft_itd *prev = itd->frame_list.prev; 2184 2185 /* Unlink itd from hardware chain, or frame array */ 2186 if (prev == NULL) { /* We're at the table head */ 2187 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2188 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2189 usb_syncmem(&sc->sc_fldma, 2190 sizeof(ehci_link_t) * itd->slot, 2191 sizeof(ehci_link_t), 2192 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2193 2194 if (itd->frame_list.next != NULL) 2195 itd->frame_list.next->frame_list.prev = NULL; 2196 } else { 2197 /* XXX this part is untested... */ 2198 prev->itd.itd_next = itd->itd.itd_next; 2199 usb_syncmem(&itd->dma, 2200 itd->offs + offsetof(ehci_itd_t, itd_next), 2201 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2202 2203 prev->frame_list.next = itd->frame_list.next; 2204 if (itd->frame_list.next != NULL) 2205 itd->frame_list.next->frame_list.prev = prev; 2206 } 2207 } 2208 } 2209 2210 Static void 2211 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2212 { 2213 struct ehci_soft_itd *next; 2214 2215 mutex_enter(&sc->sc_lock); 2216 next = NULL; 2217 for (; itd != NULL; itd = next) { 2218 next = itd->xfer_next; 2219 ehci_free_itd_locked(sc, itd); 2220 } 2221 mutex_exit(&sc->sc_lock); 2222 } 2223 2224 Static void 2225 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2226 { 2227 2228 KASSERT(mutex_owned(&sc->sc_lock)); 2229 2230 for (; sitd != NULL; sitd = sitd->xfer_next) { 2231 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2232 2233 /* Unlink sitd from hardware chain, or frame array */ 2234 if (prev == NULL) { /* We're at the table head */ 2235 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2236 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2237 usb_syncmem(&sc->sc_fldma, 2238 sizeof(ehci_link_t) * sitd->slot, 2239 sizeof(ehci_link_t), 2240 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2241 2242 if (sitd->frame_list.next != NULL) 2243 sitd->frame_list.next->frame_list.prev = NULL; 2244 } else { 2245 /* XXX this part is untested... */ 2246 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2247 usb_syncmem(&sitd->dma, 2248 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2249 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2250 2251 prev->frame_list.next = sitd->frame_list.next; 2252 if (sitd->frame_list.next != NULL) 2253 sitd->frame_list.next->frame_list.prev = prev; 2254 } 2255 } 2256 } 2257 2258 Static void 2259 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2260 { 2261 2262 mutex_enter(&sc->sc_lock); 2263 struct ehci_soft_sitd *next = NULL; 2264 for (; sitd != NULL; sitd = next) { 2265 next = sitd->xfer_next; 2266 ehci_free_sitd_locked(sc, sitd); 2267 } 2268 mutex_exit(&sc->sc_lock); 2269 } 2270 2271 /***********/ 2272 2273 Static int 2274 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2275 void *buf, int buflen) 2276 { 2277 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2278 usb_hub_descriptor_t hubd; 2279 usb_port_status_t ps; 2280 uint16_t len, value, index; 2281 int l, totlen = 0; 2282 int port, i; 2283 uint32_t v; 2284 2285 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2286 2287 if (sc->sc_dying) 2288 return -1; 2289 2290 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, 2291 0, 0); 2292 2293 len = UGETW(req->wLength); 2294 value = UGETW(req->wValue); 2295 index = UGETW(req->wIndex); 2296 2297 #define C(x,y) ((x) | ((y) << 8)) 2298 switch (C(req->bRequest, req->bmRequestType)) { 2299 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2300 if (len == 0) 2301 break; 2302 switch (value) { 2303 case C(0, UDESC_DEVICE): { 2304 usb_device_descriptor_t devd; 2305 totlen = min(buflen, sizeof(devd)); 2306 memcpy(&devd, buf, totlen); 2307 USETW(devd.idVendor, sc->sc_id_vendor); 2308 memcpy(buf, &devd, totlen); 2309 break; 2310 2311 } 2312 #define sd ((usb_string_descriptor_t *)buf) 2313 case C(1, UDESC_STRING): 2314 /* Vendor */ 2315 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2316 break; 2317 case C(2, UDESC_STRING): 2318 /* Product */ 2319 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2320 break; 2321 #undef sd 2322 default: 2323 /* default from usbroothub */ 2324 return buflen; 2325 } 2326 break; 2327 2328 /* Hub requests */ 2329 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2330 break; 2331 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2332 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 2333 value, 0, 0); 2334 if (index < 1 || index > sc->sc_noport) { 2335 return -1; 2336 } 2337 port = EHCI_PORTSC(index); 2338 v = EOREAD4(sc, port); 2339 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2340 v &= ~EHCI_PS_CLEAR; 2341 switch (value) { 2342 case UHF_PORT_ENABLE: 2343 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2344 break; 2345 case UHF_PORT_SUSPEND: 2346 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2347 break; 2348 v &= ~EHCI_PS_SUSP; 2349 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2350 /* see USB2 spec ch. 7.1.7.7 */ 2351 usb_delay_ms(&sc->sc_bus, 20); 2352 EOWRITE4(sc, port, v); 2353 usb_delay_ms(&sc->sc_bus, 2); 2354 #ifdef DEBUG 2355 v = EOREAD4(sc, port); 2356 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2357 printf("ehci: resume failed: %x\n", v); 2358 #endif 2359 break; 2360 case UHF_PORT_POWER: 2361 if (sc->sc_hasppc) 2362 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2363 break; 2364 case UHF_PORT_TEST: 2365 DPRINTF("clear port test %d", index, 0, 0, 0); 2366 break; 2367 case UHF_PORT_INDICATOR: 2368 DPRINTF("clear port ind %d", index, 0, 0, 0); 2369 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2370 break; 2371 case UHF_C_PORT_CONNECTION: 2372 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2373 break; 2374 case UHF_C_PORT_ENABLE: 2375 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2376 break; 2377 case UHF_C_PORT_SUSPEND: 2378 /* how? */ 2379 break; 2380 case UHF_C_PORT_OVER_CURRENT: 2381 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2382 break; 2383 case UHF_C_PORT_RESET: 2384 sc->sc_isreset[index] = 0; 2385 break; 2386 default: 2387 return -1; 2388 } 2389 #if 0 2390 switch(value) { 2391 case UHF_C_PORT_CONNECTION: 2392 case UHF_C_PORT_ENABLE: 2393 case UHF_C_PORT_SUSPEND: 2394 case UHF_C_PORT_OVER_CURRENT: 2395 case UHF_C_PORT_RESET: 2396 default: 2397 break; 2398 } 2399 #endif 2400 break; 2401 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2402 if (len == 0) 2403 break; 2404 if ((value & 0xff) != 0) { 2405 return -1; 2406 } 2407 totlen = min(buflen, sizeof(hubd)); 2408 memcpy(&hubd, buf, totlen); 2409 hubd.bNbrPorts = sc->sc_noport; 2410 v = EOREAD4(sc, EHCI_HCSPARAMS); 2411 USETW(hubd.wHubCharacteristics, 2412 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2413 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2414 ? UHD_PORT_IND : 0); 2415 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2416 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2417 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2418 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2419 totlen = min(totlen, hubd.bDescLength); 2420 memcpy(buf, &hubd, totlen); 2421 break; 2422 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2423 if (len != 4) { 2424 return -1; 2425 } 2426 memset(buf, 0, len); /* ? XXX */ 2427 totlen = len; 2428 break; 2429 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2430 DPRINTF("get port status i=%d", index, 0, 0, 0); 2431 if (index < 1 || index > sc->sc_noport) { 2432 return -1; 2433 } 2434 if (len != 4) { 2435 return -1; 2436 } 2437 v = EOREAD4(sc, EHCI_PORTSC(index)); 2438 DPRINTF("port status=0x%04x", v, 0, 0, 0); 2439 2440 i = UPS_HIGH_SPEED; 2441 if (sc->sc_flags & EHCIF_ETTF) { 2442 /* 2443 * If we are doing embedded transaction translation, 2444 * then directly attached LS/FS devices are reset by 2445 * the EHCI controller itself. PSPD is encoded 2446 * the same way as in USBSTATUS. 2447 */ 2448 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2449 } 2450 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2451 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2452 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2453 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2454 if (v & EHCI_PS_PR) i |= UPS_RESET; 2455 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2456 if (sc->sc_vendor_port_status) 2457 i = sc->sc_vendor_port_status(sc, v, i); 2458 USETW(ps.wPortStatus, i); 2459 i = 0; 2460 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2461 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2462 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2463 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2464 USETW(ps.wPortChange, i); 2465 totlen = min(len, sizeof(ps)); 2466 memcpy(buf, &ps, totlen); 2467 break; 2468 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2469 return -1; 2470 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2471 break; 2472 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2473 if (index < 1 || index > sc->sc_noport) { 2474 return -1; 2475 } 2476 port = EHCI_PORTSC(index); 2477 v = EOREAD4(sc, port); 2478 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2479 v &= ~EHCI_PS_CLEAR; 2480 switch(value) { 2481 case UHF_PORT_ENABLE: 2482 EOWRITE4(sc, port, v | EHCI_PS_PE); 2483 break; 2484 case UHF_PORT_SUSPEND: 2485 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2486 break; 2487 case UHF_PORT_RESET: 2488 DPRINTF("reset port %d", index, 0, 0, 0); 2489 if (EHCI_PS_IS_LOWSPEED(v) 2490 && sc->sc_ncomp > 0 2491 && !(sc->sc_flags & EHCIF_ETTF)) { 2492 /* 2493 * Low speed device on non-ETTF controller or 2494 * unaccompanied controller, give up ownership. 2495 */ 2496 ehci_disown(sc, index, 1); 2497 break; 2498 } 2499 /* Start reset sequence. */ 2500 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2501 EOWRITE4(sc, port, v | EHCI_PS_PR); 2502 /* Wait for reset to complete. */ 2503 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2504 if (sc->sc_dying) { 2505 return -1; 2506 } 2507 /* 2508 * An embedded transaction translator will automatically 2509 * terminate the reset sequence so there's no need to 2510 * it. 2511 */ 2512 v = EOREAD4(sc, port); 2513 if (v & EHCI_PS_PR) { 2514 /* Terminate reset sequence. */ 2515 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2516 /* Wait for HC to complete reset. */ 2517 usb_delay_ms(&sc->sc_bus, 2518 EHCI_PORT_RESET_COMPLETE); 2519 if (sc->sc_dying) { 2520 return -1; 2521 } 2522 } 2523 2524 v = EOREAD4(sc, port); 2525 DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); 2526 if (v & EHCI_PS_PR) { 2527 printf("%s: port reset timeout\n", 2528 device_xname(sc->sc_dev)); 2529 return USBD_TIMEOUT; 2530 } 2531 if (!(v & EHCI_PS_PE)) { 2532 /* Not a high speed device, give up ownership.*/ 2533 ehci_disown(sc, index, 0); 2534 break; 2535 } 2536 sc->sc_isreset[index] = 1; 2537 DPRINTF("ehci port %d reset, status = 0x%08x", index, 2538 v, 0, 0); 2539 break; 2540 case UHF_PORT_POWER: 2541 DPRINTF("set port power %d (has PPC = %d)", index, 2542 sc->sc_hasppc, 0, 0); 2543 if (sc->sc_hasppc) 2544 EOWRITE4(sc, port, v | EHCI_PS_PP); 2545 break; 2546 case UHF_PORT_TEST: 2547 DPRINTF("set port test %d", index, 0, 0, 0); 2548 break; 2549 case UHF_PORT_INDICATOR: 2550 DPRINTF("set port ind %d", index, 0, 0, 0); 2551 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2552 break; 2553 default: 2554 return -1; 2555 } 2556 break; 2557 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2558 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2559 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2560 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2561 break; 2562 default: 2563 /* default from usbroothub */ 2564 DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); 2565 2566 return buflen; 2567 } 2568 2569 DPRINTF("returning %d", totlen, 0, 0, 0); 2570 2571 return totlen; 2572 } 2573 2574 Static void 2575 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2576 { 2577 int port; 2578 uint32_t v; 2579 2580 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2581 2582 DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); 2583 #ifdef DIAGNOSTIC 2584 if (sc->sc_npcomp != 0) { 2585 int i = (index-1) / sc->sc_npcomp; 2586 if (i >= sc->sc_ncomp) 2587 printf("%s: strange port\n", 2588 device_xname(sc->sc_dev)); 2589 else 2590 printf("%s: handing over %s speed device on " 2591 "port %d to %s\n", 2592 device_xname(sc->sc_dev), 2593 lowspeed ? "low" : "full", 2594 index, device_xname(sc->sc_comps[i])); 2595 } else { 2596 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2597 } 2598 #endif 2599 port = EHCI_PORTSC(index); 2600 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2601 EOWRITE4(sc, port, v | EHCI_PS_PO); 2602 } 2603 2604 Static usbd_status 2605 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2606 { 2607 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2608 usbd_status err; 2609 2610 /* Insert last in queue. */ 2611 mutex_enter(&sc->sc_lock); 2612 err = usb_insert_transfer(xfer); 2613 mutex_exit(&sc->sc_lock); 2614 if (err) 2615 return err; 2616 2617 /* Pipe isn't running, start first */ 2618 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2619 } 2620 2621 Static usbd_status 2622 ehci_root_intr_start(struct usbd_xfer *xfer) 2623 { 2624 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2625 2626 if (sc->sc_dying) 2627 return USBD_IOERROR; 2628 2629 mutex_enter(&sc->sc_lock); 2630 sc->sc_intrxfer = xfer; 2631 mutex_exit(&sc->sc_lock); 2632 2633 return USBD_IN_PROGRESS; 2634 } 2635 2636 /* Abort a root interrupt request. */ 2637 Static void 2638 ehci_root_intr_abort(struct usbd_xfer *xfer) 2639 { 2640 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2641 2642 KASSERT(mutex_owned(&sc->sc_lock)); 2643 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2644 2645 sc->sc_intrxfer = NULL; 2646 2647 xfer->ux_status = USBD_CANCELLED; 2648 usb_transfer_complete(xfer); 2649 } 2650 2651 /* Close the root pipe. */ 2652 Static void 2653 ehci_root_intr_close(struct usbd_pipe *pipe) 2654 { 2655 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2656 2657 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2658 2659 KASSERT(mutex_owned(&sc->sc_lock)); 2660 2661 sc->sc_intrxfer = NULL; 2662 } 2663 2664 Static void 2665 ehci_root_intr_done(struct usbd_xfer *xfer) 2666 { 2667 } 2668 2669 /************************/ 2670 2671 Static ehci_soft_qh_t * 2672 ehci_alloc_sqh(ehci_softc_t *sc) 2673 { 2674 ehci_soft_qh_t *sqh; 2675 usbd_status err; 2676 int i, offs; 2677 usb_dma_t dma; 2678 2679 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2680 2681 mutex_enter(&sc->sc_lock); 2682 if (sc->sc_freeqhs == NULL) { 2683 DPRINTF("allocating chunk", 0, 0, 0, 0); 2684 mutex_exit(&sc->sc_lock); 2685 2686 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2687 EHCI_PAGE_SIZE, &dma); 2688 #ifdef EHCI_DEBUG 2689 if (err) 2690 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2691 #endif 2692 if (err) 2693 return NULL; 2694 2695 mutex_enter(&sc->sc_lock); 2696 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2697 offs = i * EHCI_SQH_SIZE; 2698 sqh = KERNADDR(&dma, offs); 2699 sqh->physaddr = DMAADDR(&dma, offs); 2700 sqh->dma = dma; 2701 sqh->offs = offs; 2702 sqh->next = sc->sc_freeqhs; 2703 sc->sc_freeqhs = sqh; 2704 } 2705 } 2706 sqh = sc->sc_freeqhs; 2707 sc->sc_freeqhs = sqh->next; 2708 mutex_exit(&sc->sc_lock); 2709 2710 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2711 sqh->next = NULL; 2712 return sqh; 2713 } 2714 2715 Static void 2716 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2717 { 2718 KASSERT(mutex_owned(&sc->sc_lock)); 2719 2720 sqh->next = sc->sc_freeqhs; 2721 sc->sc_freeqhs = sqh; 2722 } 2723 2724 Static ehci_soft_qtd_t * 2725 ehci_alloc_sqtd(ehci_softc_t *sc) 2726 { 2727 ehci_soft_qtd_t *sqtd = NULL; 2728 usbd_status err; 2729 int i, offs; 2730 usb_dma_t dma; 2731 2732 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2733 2734 mutex_enter(&sc->sc_lock); 2735 if (sc->sc_freeqtds == NULL) { 2736 DPRINTF("allocating chunk", 0, 0, 0, 0); 2737 mutex_exit(&sc->sc_lock); 2738 2739 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2740 EHCI_PAGE_SIZE, &dma); 2741 #ifdef EHCI_DEBUG 2742 if (err) 2743 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2744 #endif 2745 if (err) 2746 goto done; 2747 2748 mutex_enter(&sc->sc_lock); 2749 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2750 offs = i * EHCI_SQTD_SIZE; 2751 sqtd = KERNADDR(&dma, offs); 2752 sqtd->physaddr = DMAADDR(&dma, offs); 2753 sqtd->dma = dma; 2754 sqtd->offs = offs; 2755 2756 sqtd->nextqtd = sc->sc_freeqtds; 2757 sc->sc_freeqtds = sqtd; 2758 } 2759 } 2760 2761 sqtd = sc->sc_freeqtds; 2762 sc->sc_freeqtds = sqtd->nextqtd; 2763 mutex_exit(&sc->sc_lock); 2764 2765 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2766 sqtd->nextqtd = NULL; 2767 sqtd->xfer = NULL; 2768 2769 done: 2770 return sqtd; 2771 } 2772 2773 Static void 2774 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2775 { 2776 2777 mutex_enter(&sc->sc_lock); 2778 sqtd->nextqtd = sc->sc_freeqtds; 2779 sc->sc_freeqtds = sqtd; 2780 mutex_exit(&sc->sc_lock); 2781 } 2782 2783 Static int 2784 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2785 int alen, int rd, ehci_soft_qtd_t **sp) 2786 { 2787 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2788 uint16_t flags = xfer->ux_flags; 2789 2790 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2791 2792 ASSERT_SLEEPABLE(); 2793 KASSERT(sp); 2794 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2795 2796 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2797 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2798 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2799 KM_SLEEP); 2800 exfer->ex_nsqtd = nsqtd; 2801 2802 DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); 2803 2804 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2805 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2806 if (cur == NULL) 2807 goto nomem; 2808 exfer->ex_sqtds[j++] = cur; 2809 2810 cur->xfer = xfer; 2811 cur->len = 0; 2812 2813 } 2814 2815 *sp = exfer->ex_sqtds[0]; 2816 DPRINTF("return sqtd=%p", *sp, 0, 0, 0); 2817 2818 return 0; 2819 2820 nomem: 2821 ehci_free_sqtds(sc, exfer); 2822 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2823 DPRINTF("no memory", 0, 0, 0, 0); 2824 return ENOMEM; 2825 } 2826 2827 Static void 2828 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2829 { 2830 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2831 DPRINTF("exfer=%p", exfer, 0, 0, 0); 2832 2833 mutex_enter(&sc->sc_lock); 2834 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2835 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2836 2837 if (sqtd == NULL) 2838 break; 2839 2840 sqtd->nextqtd = sc->sc_freeqtds; 2841 sc->sc_freeqtds = sqtd; 2842 } 2843 mutex_exit(&sc->sc_lock); 2844 } 2845 2846 Static void 2847 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2848 { 2849 if (prev) { 2850 prev->nextqtd = sqtd; 2851 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2852 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2853 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2854 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2855 } 2856 } 2857 2858 Static void 2859 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2860 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2861 { 2862 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2863 usb_dma_t *dma = &xfer->ux_dmabuf; 2864 uint16_t flags = xfer->ux_flags; 2865 ehci_soft_qtd_t *sqtd, *prev; 2866 int tog = *toggle; 2867 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2868 int len = length; 2869 2870 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2871 DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); 2872 DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); 2873 2874 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2875 2876 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2877 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2878 EHCI_QTD_SET_CERR(3) 2879 ; 2880 2881 sqtd = prev = NULL; 2882 size_t curoffs = 0; 2883 size_t j = 0; 2884 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2885 sqtd = exfer->ex_sqtds[j++]; 2886 DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); 2887 2888 /* 2889 * The EHCI hardware can handle at most 5 pages and they do 2890 * not have to be contiguous 2891 */ 2892 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2893 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2894 size_t curlen = len; 2895 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2896 /* must use multiple TDs, fill as much as possible. */ 2897 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2898 2899 /* the length must be a multiple of the max size */ 2900 curlen -= curlen % mps; 2901 } 2902 KASSERT(curlen != 0); 2903 DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, 2904 curoffs, 0); 2905 2906 /* Fill the qTD */ 2907 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2908 sqtd->qtd.qtd_status = htole32( 2909 qtdstatus | 2910 EHCI_QTD_SET_BYTES(curlen) | 2911 EHCI_QTD_SET_TOGGLE(tog)); 2912 2913 /* Find number of pages we'll be using, insert dma addresses */ 2914 size_t pages = EHCI_NPAGES(curlen); 2915 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2916 size_t pageoffs = EHCI_PAGE(curoffs); 2917 for (size_t i = 0; i < pages; i++) { 2918 paddr_t a = DMAADDR(dma, 2919 pageoffs + i * EHCI_PAGE_SIZE); 2920 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2921 /* Cast up to avoid compiler warnings */ 2922 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2923 DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, 2924 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2925 le32toh(sqtd->qtd.qtd_buffer[i])); 2926 } 2927 /* First buffer pointer requires a page offset to start at */ 2928 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2929 2930 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2931 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2932 2933 sqtd->len = curlen; 2934 2935 DPRINTF(" va %p pa %p len %d", va, 2936 DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2937 2938 ehci_append_sqtd(sqtd, prev); 2939 2940 if (((curlen + mps - 1) / mps) & 1) { 2941 tog ^= 1; 2942 } 2943 2944 curoffs += curlen; 2945 len -= curlen; 2946 } 2947 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2948 xfer, length, len, mps, exfer->ex_nsqtd, j); 2949 2950 if (!isread && 2951 (flags & USBD_FORCE_SHORT_XFER) && 2952 length % mps == 0) { 2953 /* Force a 0 length transfer at the end. */ 2954 2955 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2956 exfer->ex_nsqtd); 2957 prev = sqtd; 2958 sqtd = exfer->ex_sqtds[j++]; 2959 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 2960 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2961 sqtd->qtd.qtd_status = htole32( 2962 qtdstatus | 2963 EHCI_QTD_SET_BYTES(0) | 2964 EHCI_QTD_SET_TOGGLE(tog)); 2965 2966 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2967 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2968 2969 ehci_append_sqtd(sqtd, prev); 2970 tog ^= 1; 2971 } 2972 2973 *lsqtd = sqtd; 2974 *toggle = tog; 2975 } 2976 2977 Static ehci_soft_itd_t * 2978 ehci_alloc_itd(ehci_softc_t *sc) 2979 { 2980 struct ehci_soft_itd *itd, *freeitd; 2981 usbd_status err; 2982 usb_dma_t dma; 2983 2984 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2985 2986 mutex_enter(&sc->sc_lock); 2987 2988 freeitd = LIST_FIRST(&sc->sc_freeitds); 2989 if (freeitd == NULL) { 2990 DPRINTF("allocating chunk", 0, 0, 0, 0); 2991 mutex_exit(&sc->sc_lock); 2992 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2993 EHCI_PAGE_SIZE, &dma); 2994 2995 if (err) { 2996 DPRINTF("alloc returned %d", err, 0, 0, 0); 2997 return NULL; 2998 } 2999 mutex_enter(&sc->sc_lock); 3000 3001 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3002 int offs = i * EHCI_ITD_SIZE; 3003 itd = KERNADDR(&dma, offs); 3004 itd->physaddr = DMAADDR(&dma, offs); 3005 itd->dma = dma; 3006 itd->offs = offs; 3007 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3008 } 3009 freeitd = LIST_FIRST(&sc->sc_freeitds); 3010 } 3011 3012 itd = freeitd; 3013 LIST_REMOVE(itd, free_list); 3014 mutex_exit(&sc->sc_lock); 3015 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3016 3017 itd->frame_list.next = NULL; 3018 itd->frame_list.prev = NULL; 3019 itd->xfer_next = NULL; 3020 itd->slot = 0; 3021 3022 return itd; 3023 } 3024 3025 Static ehci_soft_sitd_t * 3026 ehci_alloc_sitd(ehci_softc_t *sc) 3027 { 3028 struct ehci_soft_sitd *sitd, *freesitd; 3029 usbd_status err; 3030 int i, offs; 3031 usb_dma_t dma; 3032 3033 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3034 3035 mutex_enter(&sc->sc_lock); 3036 freesitd = LIST_FIRST(&sc->sc_freesitds); 3037 if (freesitd == NULL) { 3038 DPRINTF("allocating chunk", 0, 0, 0, 0); 3039 mutex_exit(&sc->sc_lock); 3040 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3041 EHCI_PAGE_SIZE, &dma); 3042 3043 if (err) { 3044 DPRINTF("alloc returned %d", err, 0, 0, 3045 0); 3046 return NULL; 3047 } 3048 3049 mutex_enter(&sc->sc_lock); 3050 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3051 offs = i * EHCI_SITD_SIZE; 3052 sitd = KERNADDR(&dma, offs); 3053 sitd->physaddr = DMAADDR(&dma, offs); 3054 sitd->dma = dma; 3055 sitd->offs = offs; 3056 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3057 } 3058 freesitd = LIST_FIRST(&sc->sc_freesitds); 3059 } 3060 3061 sitd = freesitd; 3062 LIST_REMOVE(sitd, free_list); 3063 mutex_exit(&sc->sc_lock); 3064 3065 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3066 3067 sitd->frame_list.next = NULL; 3068 sitd->frame_list.prev = NULL; 3069 sitd->xfer_next = NULL; 3070 sitd->slot = 0; 3071 3072 return sitd; 3073 } 3074 3075 /****************/ 3076 3077 /* 3078 * Close a reqular pipe. 3079 * Assumes that there are no pending transactions. 3080 */ 3081 Static void 3082 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3083 { 3084 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3085 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3086 ehci_soft_qh_t *sqh = epipe->sqh; 3087 3088 KASSERT(mutex_owned(&sc->sc_lock)); 3089 3090 ehci_rem_qh(sc, sqh, head); 3091 ehci_free_sqh(sc, epipe->sqh); 3092 } 3093 3094 /* 3095 * Abort a device request. 3096 * If this routine is called at splusb() it guarantees that the request 3097 * will be removed from the hardware scheduling and that the callback 3098 * for it will be called with USBD_CANCELLED status. 3099 * It's impossible to guarantee that the requested transfer will not 3100 * have happened since the hardware runs concurrently. 3101 * If the transaction has already happened we rely on the ordinary 3102 * interrupt processing to process it. 3103 * XXX This is most probably wrong. 3104 * XXXMRG this doesn't make sense anymore. 3105 */ 3106 Static void 3107 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3108 { 3109 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3110 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3111 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3112 ehci_soft_qh_t *sqh = epipe->sqh; 3113 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3114 ehci_physaddr_t cur; 3115 uint32_t qhstatus; 3116 int hit; 3117 int wake; 3118 3119 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3120 3121 DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); 3122 3123 KASSERT(mutex_owned(&sc->sc_lock)); 3124 ASSERT_SLEEPABLE(); 3125 3126 if (sc->sc_dying) { 3127 /* If we're dying, just do the software part. */ 3128 xfer->ux_status = status; /* make software ignore it */ 3129 callout_stop(&xfer->ux_callout); 3130 usb_transfer_complete(xfer); 3131 return; 3132 } 3133 3134 /* 3135 * If an abort is already in progress then just wait for it to 3136 * complete and return. 3137 */ 3138 if (xfer->ux_hcflags & UXFER_ABORTING) { 3139 DPRINTF("already aborting", 0, 0, 0, 0); 3140 #ifdef DIAGNOSTIC 3141 if (status == USBD_TIMEOUT) 3142 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3143 #endif 3144 /* Override the status which might be USBD_TIMEOUT. */ 3145 xfer->ux_status = status; 3146 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3147 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3148 while (xfer->ux_hcflags & UXFER_ABORTING) 3149 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3150 return; 3151 } 3152 xfer->ux_hcflags |= UXFER_ABORTING; 3153 3154 /* 3155 * Step 1: Make interrupt routine and hardware ignore xfer. 3156 */ 3157 xfer->ux_status = status; /* make software ignore it */ 3158 callout_stop(&xfer->ux_callout); 3159 ehci_del_intr_list(sc, exfer); 3160 3161 usb_syncmem(&sqh->dma, 3162 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3163 sizeof(sqh->qh.qh_qtd.qtd_status), 3164 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3165 qhstatus = sqh->qh.qh_qtd.qtd_status; 3166 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3167 usb_syncmem(&sqh->dma, 3168 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3169 sizeof(sqh->qh.qh_qtd.qtd_status), 3170 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3171 3172 if (exfer->ex_type == EX_CTRL) { 3173 fsqtd = exfer->ex_setup; 3174 lsqtd = exfer->ex_status; 3175 } else { 3176 fsqtd = exfer->ex_sqtdstart; 3177 lsqtd = exfer->ex_sqtdend; 3178 } 3179 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3180 usb_syncmem(&sqtd->dma, 3181 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3182 sizeof(sqtd->qtd.qtd_status), 3183 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3184 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3185 usb_syncmem(&sqtd->dma, 3186 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3187 sizeof(sqtd->qtd.qtd_status), 3188 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3189 if (sqtd == lsqtd) 3190 break; 3191 } 3192 3193 /* 3194 * Step 2: Wait until we know hardware has finished any possible 3195 * use of the xfer. Also make sure the soft interrupt routine 3196 * has run. 3197 */ 3198 ehci_sync_hc(sc); 3199 sc->sc_softwake = 1; 3200 usb_schedsoftintr(&sc->sc_bus); 3201 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3202 3203 /* 3204 * Step 3: Remove any vestiges of the xfer from the hardware. 3205 * The complication here is that the hardware may have executed 3206 * beyond the xfer we're trying to abort. So as we're scanning 3207 * the TDs of this xfer we check if the hardware points to 3208 * any of them. 3209 */ 3210 3211 usb_syncmem(&sqh->dma, 3212 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3213 sizeof(sqh->qh.qh_curqtd), 3214 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3215 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3216 hit = 0; 3217 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3218 hit |= cur == sqtd->physaddr; 3219 if (sqtd == lsqtd) 3220 break; 3221 } 3222 sqtd = sqtd->nextqtd; 3223 /* Zap curqtd register if hardware pointed inside the xfer. */ 3224 if (hit && sqtd != NULL) { 3225 DPRINTF("cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3226 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3227 usb_syncmem(&sqh->dma, 3228 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3229 sizeof(sqh->qh.qh_curqtd), 3230 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3231 sqh->qh.qh_qtd.qtd_status = qhstatus; 3232 usb_syncmem(&sqh->dma, 3233 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3234 sizeof(sqh->qh.qh_qtd.qtd_status), 3235 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3236 } else { 3237 DPRINTF("no hit", 0, 0, 0, 0); 3238 usb_syncmem(&sqh->dma, 3239 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3240 sizeof(sqh->qh.qh_curqtd), 3241 BUS_DMASYNC_PREREAD); 3242 } 3243 3244 /* 3245 * Step 4: Execute callback. 3246 */ 3247 #ifdef DIAGNOSTIC 3248 exfer->ex_isdone = true; 3249 #endif 3250 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3251 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3252 usb_transfer_complete(xfer); 3253 if (wake) { 3254 cv_broadcast(&xfer->ux_hccv); 3255 } 3256 3257 KASSERT(mutex_owned(&sc->sc_lock)); 3258 } 3259 3260 Static void 3261 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3262 { 3263 ehci_isoc_trans_t trans_status; 3264 struct ehci_xfer *exfer; 3265 ehci_softc_t *sc; 3266 struct ehci_soft_itd *itd; 3267 struct ehci_soft_sitd *sitd; 3268 int i, wake; 3269 3270 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3271 3272 exfer = EHCI_XFER2EXFER(xfer); 3273 sc = EHCI_XFER2SC(xfer); 3274 3275 DPRINTF("xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3276 3277 KASSERT(mutex_owned(&sc->sc_lock)); 3278 3279 if (sc->sc_dying) { 3280 xfer->ux_status = status; 3281 callout_stop(&xfer->ux_callout); 3282 usb_transfer_complete(xfer); 3283 return; 3284 } 3285 3286 if (xfer->ux_hcflags & UXFER_ABORTING) { 3287 DPRINTF("already aborting", 0, 0, 0, 0); 3288 3289 #ifdef DIAGNOSTIC 3290 if (status == USBD_TIMEOUT) 3291 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3292 #endif 3293 3294 xfer->ux_status = status; 3295 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3296 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3297 while (xfer->ux_hcflags & UXFER_ABORTING) 3298 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3299 goto done; 3300 } 3301 xfer->ux_hcflags |= UXFER_ABORTING; 3302 3303 xfer->ux_status = status; 3304 callout_stop(&xfer->ux_callout); 3305 ehci_del_intr_list(sc, exfer); 3306 3307 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3308 for (itd = exfer->ex_itdstart; itd != NULL; 3309 itd = itd->xfer_next) { 3310 usb_syncmem(&itd->dma, 3311 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3312 sizeof(itd->itd.itd_ctl), 3313 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3314 3315 for (i = 0; i < 8; i++) { 3316 trans_status = le32toh(itd->itd.itd_ctl[i]); 3317 trans_status &= ~EHCI_ITD_ACTIVE; 3318 itd->itd.itd_ctl[i] = htole32(trans_status); 3319 } 3320 3321 usb_syncmem(&itd->dma, 3322 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3323 sizeof(itd->itd.itd_ctl), 3324 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3325 } 3326 } else { 3327 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3328 sitd = sitd->xfer_next) { 3329 usb_syncmem(&sitd->dma, 3330 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3331 sizeof(sitd->sitd.sitd_buffer), 3332 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3333 3334 trans_status = le32toh(sitd->sitd.sitd_trans); 3335 trans_status &= ~EHCI_SITD_ACTIVE; 3336 sitd->sitd.sitd_trans = htole32(trans_status); 3337 3338 usb_syncmem(&sitd->dma, 3339 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3340 sizeof(sitd->sitd.sitd_buffer), 3341 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3342 } 3343 } 3344 3345 sc->sc_softwake = 1; 3346 usb_schedsoftintr(&sc->sc_bus); 3347 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3348 3349 #ifdef DIAGNOSTIC 3350 exfer->ex_isdone = true; 3351 #endif 3352 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3353 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3354 usb_transfer_complete(xfer); 3355 if (wake) { 3356 cv_broadcast(&xfer->ux_hccv); 3357 } 3358 3359 done: 3360 KASSERT(mutex_owned(&sc->sc_lock)); 3361 return; 3362 } 3363 3364 Static void 3365 ehci_timeout(void *addr) 3366 { 3367 struct usbd_xfer *xfer = addr; 3368 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3369 struct usbd_pipe *pipe = xfer->ux_pipe; 3370 struct usbd_device *dev = pipe->up_dev; 3371 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3372 3373 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3374 3375 DPRINTF("exfer %p", exfer, 0, 0, 0); 3376 #ifdef EHCI_DEBUG 3377 if (ehcidebug >= 2) 3378 usbd_dump_pipe(pipe); 3379 #endif 3380 3381 if (sc->sc_dying) { 3382 mutex_enter(&sc->sc_lock); 3383 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3384 mutex_exit(&sc->sc_lock); 3385 return; 3386 } 3387 3388 /* Execute the abort in a process context. */ 3389 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3390 USB_TASKQ_MPSAFE); 3391 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3392 } 3393 3394 Static void 3395 ehci_timeout_task(void *addr) 3396 { 3397 struct usbd_xfer *xfer = addr; 3398 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3399 3400 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3401 3402 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3403 3404 mutex_enter(&sc->sc_lock); 3405 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3406 mutex_exit(&sc->sc_lock); 3407 } 3408 3409 /************************/ 3410 3411 Static int 3412 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3413 { 3414 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3415 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3416 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3417 usb_device_request_t *req = &xfer->ux_request; 3418 ehci_soft_qtd_t *setup, *status, *next; 3419 int isread = req->bmRequestType & UT_READ; 3420 int len = xfer->ux_bufsize; 3421 int err; 3422 3423 exfer->ex_type = EX_CTRL; 3424 exfer->ex_status = NULL; 3425 exfer->ex_data = NULL; 3426 exfer->ex_setup = ehci_alloc_sqtd(sc); 3427 if (exfer->ex_setup == NULL) { 3428 err = ENOMEM; 3429 goto bad1; 3430 } 3431 exfer->ex_status = ehci_alloc_sqtd(sc); 3432 if (exfer->ex_status == NULL) { 3433 err = ENOMEM; 3434 goto bad2; 3435 } 3436 setup = exfer->ex_setup; 3437 status = exfer->ex_status; 3438 exfer->ex_nsqtd = 0; 3439 next = status; 3440 /* Set up data transaction */ 3441 if (len != 0) { 3442 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3443 &exfer->ex_data); 3444 if (err) 3445 goto bad3; 3446 next = exfer->ex_data; 3447 } 3448 3449 /* Clear toggle */ 3450 setup->qtd.qtd_status = htole32( 3451 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3452 EHCI_QTD_SET_TOGGLE(0) | 3453 EHCI_QTD_SET_BYTES(sizeof(*req)) 3454 ); 3455 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3456 setup->qtd.qtd_buffer_hi[0] = 0; 3457 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3458 setup->nextqtd = next; 3459 setup->xfer = xfer; 3460 setup->len = sizeof(*req); 3461 3462 status->qtd.qtd_status = htole32( 3463 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3464 EHCI_QTD_SET_TOGGLE(1) | 3465 EHCI_QTD_IOC 3466 ); 3467 status->qtd.qtd_buffer[0] = 0; 3468 status->qtd.qtd_buffer_hi[0] = 0; 3469 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3470 status->nextqtd = NULL; 3471 status->xfer = xfer; 3472 status->len = 0; 3473 3474 return 0; 3475 bad3: 3476 ehci_free_sqtd(sc, exfer->ex_status); 3477 bad2: 3478 ehci_free_sqtd(sc, exfer->ex_setup); 3479 bad1: 3480 return err; 3481 } 3482 3483 Static void 3484 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3485 { 3486 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3487 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3488 3489 KASSERT(ex->ex_type == EX_CTRL); 3490 3491 ehci_free_sqtd(sc, ex->ex_setup); 3492 ehci_free_sqtd(sc, ex->ex_status); 3493 ehci_free_sqtds(sc, ex); 3494 if (ex->ex_nsqtd) 3495 kmem_free(ex->ex_sqtds, 3496 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3497 } 3498 3499 Static usbd_status 3500 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3501 { 3502 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3503 usbd_status err; 3504 3505 /* Insert last in queue. */ 3506 mutex_enter(&sc->sc_lock); 3507 err = usb_insert_transfer(xfer); 3508 mutex_exit(&sc->sc_lock); 3509 if (err) 3510 return err; 3511 3512 /* Pipe isn't running, start first */ 3513 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3514 } 3515 3516 Static usbd_status 3517 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3518 { 3519 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3520 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3521 usb_device_request_t *req = &xfer->ux_request; 3522 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3523 ehci_soft_qtd_t *setup, *status, *next; 3524 ehci_soft_qh_t *sqh; 3525 3526 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3527 3528 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3529 3530 if (sc->sc_dying) 3531 return USBD_IOERROR; 3532 3533 const int isread = req->bmRequestType & UT_READ; 3534 const int len = UGETW(req->wLength); 3535 3536 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 3537 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3538 UGETW(req->wIndex)); 3539 DPRINTF("len=%d, addr=%d, endpt=%d", len, epipe->pipe.up_dev->ud_addr, 3540 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3541 3542 sqh = epipe->sqh; 3543 3544 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3545 "address QH %" __PRIuBIT " pipe %d\n", 3546 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3547 epipe->pipe.up_dev->ud_addr); 3548 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3549 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3550 "MPS QH %" __PRIuBIT " pipe %d\n", 3551 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3552 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3553 3554 setup = exfer->ex_setup; 3555 status = exfer->ex_status; 3556 3557 DPRINTF("setup %p status %p data %p", setup, status, exfer->ex_data, 0); 3558 KASSERTMSG(setup != NULL && status != NULL, 3559 "Failed memory allocation, setup %p status %p", 3560 setup, status); 3561 3562 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3563 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3564 3565 /* Clear toggle */ 3566 setup->qtd.qtd_status &= ~htole32( 3567 EHCI_QTD_STATUS_MASK | 3568 EHCI_QTD_BYTES_MASK | 3569 EHCI_QTD_TOGGLE_MASK | 3570 EHCI_QTD_CERR_MASK 3571 ); 3572 setup->qtd.qtd_status |= htole32( 3573 EHCI_QTD_ACTIVE | 3574 EHCI_QTD_SET_CERR(3) | 3575 EHCI_QTD_SET_TOGGLE(0) | 3576 EHCI_QTD_SET_BYTES(sizeof(*req)) 3577 ); 3578 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3579 setup->qtd.qtd_buffer_hi[0] = 0; 3580 3581 next = status; 3582 status->qtd.qtd_status &= ~htole32( 3583 EHCI_QTD_STATUS_MASK | 3584 EHCI_QTD_PID_MASK | 3585 EHCI_QTD_BYTES_MASK | 3586 EHCI_QTD_TOGGLE_MASK | 3587 EHCI_QTD_CERR_MASK 3588 ); 3589 status->qtd.qtd_status |= htole32( 3590 EHCI_QTD_ACTIVE | 3591 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3592 EHCI_QTD_SET_CERR(3) | 3593 EHCI_QTD_SET_TOGGLE(1) | 3594 EHCI_QTD_SET_BYTES(0) | 3595 EHCI_QTD_IOC 3596 ); 3597 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3598 3599 KASSERT(exfer->ex_isdone); 3600 #ifdef DIAGNOSTIC 3601 exfer->ex_isdone = false; 3602 #endif 3603 3604 /* Set up data transaction */ 3605 if (len != 0) { 3606 ehci_soft_qtd_t *end; 3607 3608 /* Start toggle at 1. */ 3609 int toggle = 1; 3610 next = exfer->ex_data; 3611 KASSERTMSG(next != NULL, "Failed memory allocation"); 3612 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3613 end->nextqtd = status; 3614 end->qtd.qtd_next = end->qtd.qtd_altnext = 3615 htole32(status->physaddr); 3616 3617 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3618 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3619 3620 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3621 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3622 } 3623 3624 setup->nextqtd = next; 3625 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3626 3627 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3628 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3629 3630 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3631 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3632 3633 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3634 3635 #ifdef EHCI_DEBUG 3636 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3637 ehci_dump_sqh(sqh); 3638 ehci_dump_sqtds(setup); 3639 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3640 #endif 3641 3642 mutex_enter(&sc->sc_lock); 3643 3644 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3645 ehci_set_qh_qtd(sqh, setup); 3646 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3647 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3648 ehci_timeout, xfer); 3649 } 3650 ehci_add_intr_list(sc, exfer); 3651 xfer->ux_status = USBD_IN_PROGRESS; 3652 mutex_exit(&sc->sc_lock); 3653 3654 #if 0 3655 #ifdef EHCI_DEBUG 3656 DPRINTFN(10, "status=%x, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3657 // delay(10000); 3658 ehci_dump_regs(sc); 3659 ehci_dump_sqh(sc->sc_async_head); 3660 ehci_dump_sqh(sqh); 3661 ehci_dump_sqtds(setup); 3662 #endif 3663 #endif 3664 3665 return USBD_IN_PROGRESS; 3666 } 3667 3668 Static void 3669 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3670 { 3671 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3672 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3673 usb_device_request_t *req = &xfer->ux_request; 3674 int len = UGETW(req->wLength); 3675 int rd = req->bmRequestType & UT_READ; 3676 3677 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3678 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3679 3680 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3681 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3682 3683 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3684 BUS_DMASYNC_POSTWRITE); 3685 if (len) 3686 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3687 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3688 3689 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3690 } 3691 3692 /* Abort a device control request. */ 3693 Static void 3694 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3695 { 3696 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3697 3698 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3699 ehci_abort_xfer(xfer, USBD_CANCELLED); 3700 } 3701 3702 /* Close a device control pipe. */ 3703 Static void 3704 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3705 { 3706 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3707 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3708 3709 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3710 3711 KASSERT(mutex_owned(&sc->sc_lock)); 3712 3713 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3714 3715 ehci_close_pipe(pipe, sc->sc_async_head); 3716 } 3717 3718 /* 3719 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3720 * qTD status, or miss signalling occasionally under heavy load. If the host 3721 * machine is too fast, we we can miss transaction completion - when we scan 3722 * the active list the transaction still seems to be active. This generally 3723 * exhibits itself as a umass stall that never recovers. 3724 * 3725 * We work around this behaviour by setting up this callback after any softintr 3726 * that completes with transactions still pending, giving us another chance to 3727 * check for completion after the writeback has taken place. 3728 */ 3729 Static void 3730 ehci_intrlist_timeout(void *arg) 3731 { 3732 ehci_softc_t *sc = arg; 3733 3734 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3735 3736 usb_schedsoftintr(&sc->sc_bus); 3737 } 3738 3739 /************************/ 3740 3741 Static int 3742 ehci_device_bulk_init(struct usbd_xfer *xfer) 3743 { 3744 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3745 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3746 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3747 int endpt = ed->bEndpointAddress; 3748 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3749 int len = xfer->ux_bufsize; 3750 int err = 0; 3751 3752 exfer->ex_type = EX_BULK; 3753 exfer->ex_nsqtd = 0; 3754 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3755 &exfer->ex_sqtdstart); 3756 3757 return err; 3758 } 3759 3760 Static void 3761 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3762 { 3763 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3764 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3765 3766 KASSERT(ex->ex_type == EX_BULK); 3767 3768 ehci_free_sqtds(sc, ex); 3769 if (ex->ex_nsqtd) 3770 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3771 } 3772 3773 Static usbd_status 3774 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3775 { 3776 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3777 usbd_status err; 3778 3779 /* Insert last in queue. */ 3780 mutex_enter(&sc->sc_lock); 3781 err = usb_insert_transfer(xfer); 3782 mutex_exit(&sc->sc_lock); 3783 if (err) 3784 return err; 3785 3786 /* Pipe isn't running, start first */ 3787 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3788 } 3789 3790 Static usbd_status 3791 ehci_device_bulk_start(struct usbd_xfer *xfer) 3792 { 3793 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3794 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3795 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3796 ehci_soft_qh_t *sqh; 3797 ehci_soft_qtd_t *end; 3798 int len, isread, endpt; 3799 3800 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3801 3802 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3803 xfer->ux_flags, 0); 3804 3805 if (sc->sc_dying) 3806 return USBD_IOERROR; 3807 3808 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3809 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3810 3811 len = xfer->ux_length; 3812 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3813 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3814 sqh = epipe->sqh; 3815 3816 KASSERT(exfer->ex_isdone); 3817 #ifdef DIAGNOSTIC 3818 exfer->ex_isdone = false; 3819 #endif 3820 3821 /* Take lock here to protect nexttoggle */ 3822 mutex_enter(&sc->sc_lock); 3823 3824 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3825 3826 exfer->ex_sqtdend = end; 3827 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3828 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3829 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3830 3831 #ifdef EHCI_DEBUG 3832 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3833 ehci_dump_sqh(sqh); 3834 ehci_dump_sqtds(exfer->ex_sqtdstart); 3835 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3836 #endif 3837 3838 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3839 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3840 3841 /* also does usb_syncmem(sqh) */ 3842 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3843 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3844 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3845 ehci_timeout, xfer); 3846 } 3847 ehci_add_intr_list(sc, exfer); 3848 xfer->ux_status = USBD_IN_PROGRESS; 3849 mutex_exit(&sc->sc_lock); 3850 3851 #if 0 3852 #ifdef EHCI_DEBUG 3853 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3854 // delay(10000); 3855 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3856 ehci_dump_regs(sc); 3857 #if 0 3858 printf("async_head:\n"); 3859 ehci_dump_sqh(sc->sc_async_head); 3860 #endif 3861 DPRINTF("sqh:", 0, 0, 0, 0); 3862 ehci_dump_sqh(sqh); 3863 ehci_dump_sqtds(exfer->ex_sqtdstart); 3864 #endif 3865 #endif 3866 3867 return USBD_IN_PROGRESS; 3868 } 3869 3870 Static void 3871 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3872 { 3873 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3874 3875 DPRINTF("xfer %p", xfer, 0, 0, 0); 3876 ehci_abort_xfer(xfer, USBD_CANCELLED); 3877 } 3878 3879 /* 3880 * Close a device bulk pipe. 3881 */ 3882 Static void 3883 ehci_device_bulk_close(struct usbd_pipe *pipe) 3884 { 3885 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3886 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3887 3888 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3889 3890 KASSERT(mutex_owned(&sc->sc_lock)); 3891 3892 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3893 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3894 ehci_close_pipe(pipe, sc->sc_async_head); 3895 } 3896 3897 Static void 3898 ehci_device_bulk_done(struct usbd_xfer *xfer) 3899 { 3900 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3901 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3902 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3903 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3904 3905 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3906 3907 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 3908 3909 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3910 3911 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3912 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3913 3914 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3915 } 3916 3917 /************************/ 3918 3919 Static usbd_status 3920 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3921 { 3922 struct ehci_soft_islot *isp; 3923 int islot, lev; 3924 3925 /* Find a poll rate that is large enough. */ 3926 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3927 if (EHCI_ILEV_IVAL(lev) <= ival) 3928 break; 3929 3930 /* Pick an interrupt slot at the right level. */ 3931 /* XXX could do better than picking at random */ 3932 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3933 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3934 3935 sqh->islot = islot; 3936 isp = &sc->sc_islots[islot]; 3937 mutex_enter(&sc->sc_lock); 3938 ehci_add_qh(sc, sqh, isp->sqh); 3939 mutex_exit(&sc->sc_lock); 3940 3941 return USBD_NORMAL_COMPLETION; 3942 } 3943 3944 3945 Static int 3946 ehci_device_intr_init(struct usbd_xfer *xfer) 3947 { 3948 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3949 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3950 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3951 int endpt = ed->bEndpointAddress; 3952 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3953 int len = xfer->ux_bufsize; 3954 int err; 3955 3956 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3957 3958 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3959 xfer->ux_flags, 0); 3960 3961 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3962 KASSERT(len != 0); 3963 3964 exfer->ex_type = EX_INTR; 3965 exfer->ex_nsqtd = 0; 3966 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3967 &exfer->ex_sqtdstart); 3968 3969 return err; 3970 } 3971 3972 Static void 3973 ehci_device_intr_fini(struct usbd_xfer *xfer) 3974 { 3975 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3976 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3977 3978 KASSERT(ex->ex_type == EX_INTR); 3979 3980 ehci_free_sqtds(sc, ex); 3981 if (ex->ex_nsqtd) 3982 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3983 } 3984 3985 Static usbd_status 3986 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3987 { 3988 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3989 usbd_status err; 3990 3991 /* Insert last in queue. */ 3992 mutex_enter(&sc->sc_lock); 3993 err = usb_insert_transfer(xfer); 3994 mutex_exit(&sc->sc_lock); 3995 if (err) 3996 return err; 3997 3998 /* 3999 * Pipe isn't running (otherwise err would be USBD_INPROG), 4000 * so start it first. 4001 */ 4002 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4003 } 4004 4005 Static usbd_status 4006 ehci_device_intr_start(struct usbd_xfer *xfer) 4007 { 4008 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4009 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4010 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4011 ehci_soft_qtd_t *end; 4012 ehci_soft_qh_t *sqh; 4013 int len, isread, endpt; 4014 4015 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4016 4017 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4018 xfer->ux_flags, 0); 4019 4020 if (sc->sc_dying) 4021 return USBD_IOERROR; 4022 4023 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4024 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4025 4026 len = xfer->ux_length; 4027 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4028 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4029 sqh = epipe->sqh; 4030 4031 KASSERT(exfer->ex_isdone); 4032 #ifdef DIAGNOSTIC 4033 exfer->ex_isdone = false; 4034 #endif 4035 4036 /* Take lock to protect nexttoggle */ 4037 mutex_enter(&sc->sc_lock); 4038 4039 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4040 4041 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4042 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4043 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4044 exfer->ex_sqtdend = end; 4045 4046 #ifdef EHCI_DEBUG 4047 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4048 ehci_dump_sqh(sqh); 4049 ehci_dump_sqtds(exfer->ex_sqtdstart); 4050 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4051 #endif 4052 4053 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4054 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4055 4056 /* also does usb_syncmem(sqh) */ 4057 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4058 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4059 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4060 ehci_timeout, xfer); 4061 } 4062 ehci_add_intr_list(sc, exfer); 4063 xfer->ux_status = USBD_IN_PROGRESS; 4064 mutex_exit(&sc->sc_lock); 4065 4066 #if 0 4067 #ifdef EHCI_DEBUG 4068 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4069 // delay(10000); 4070 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4071 ehci_dump_regs(sc); 4072 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4073 ehci_dump_sqh(sqh); 4074 ehci_dump_sqtds(exfer->ex_sqtdstart); 4075 #endif 4076 #endif 4077 4078 return USBD_IN_PROGRESS; 4079 } 4080 4081 Static void 4082 ehci_device_intr_abort(struct usbd_xfer *xfer) 4083 { 4084 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4085 4086 DPRINTF("xfer=%p", xfer, 0, 0, 0); 4087 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4088 4089 /* 4090 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4091 * async doorbell. That's dependent on the async list, wheras 4092 * intr xfers are periodic, should not use this? 4093 */ 4094 ehci_abort_xfer(xfer, USBD_CANCELLED); 4095 } 4096 4097 Static void 4098 ehci_device_intr_close(struct usbd_pipe *pipe) 4099 { 4100 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4101 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4102 struct ehci_soft_islot *isp; 4103 4104 KASSERT(mutex_owned(&sc->sc_lock)); 4105 4106 isp = &sc->sc_islots[epipe->sqh->islot]; 4107 ehci_close_pipe(pipe, isp->sqh); 4108 } 4109 4110 Static void 4111 ehci_device_intr_done(struct usbd_xfer *xfer) 4112 { 4113 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4114 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4115 int isread, endpt; 4116 4117 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4118 4119 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4120 0, 0); 4121 4122 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4123 4124 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4125 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4126 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4127 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4128 } 4129 4130 /************************/ 4131 Static int 4132 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4133 { 4134 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4135 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4136 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4137 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4138 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4139 int i, k, frames; 4140 u_int huba, dir; 4141 int err; 4142 4143 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4144 4145 start = NULL; 4146 sitd = NULL; 4147 4148 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4149 xfer->ux_flags, 0); 4150 4151 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4152 KASSERT(xfer->ux_nframes != 0); 4153 KASSERT(exfer->ex_isdone); 4154 4155 exfer->ex_type = EX_FS_ISOC; 4156 /* 4157 * Step 1: Allocate and initialize sitds. 4158 */ 4159 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4160 if (i > 16 || i == 0) { 4161 /* Spec page 271 says intervals > 16 are invalid */ 4162 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4163 4164 return EINVAL; 4165 } 4166 4167 frames = xfer->ux_nframes; 4168 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4169 sitd = ehci_alloc_sitd(sc); 4170 if (sitd == NULL) { 4171 err = ENOMEM; 4172 goto fail; 4173 } 4174 4175 if (prev) 4176 prev->xfer_next = sitd; 4177 else 4178 start = sitd; 4179 4180 huba = dev->ud_myhsport->up_parent->ud_addr; 4181 4182 #if 0 4183 if (sc->sc_flags & EHCIF_FREESCALE) { 4184 // Set hub address to 0 if embedded TT is used. 4185 if (huba == sc->sc_addr) 4186 huba = 0; 4187 } 4188 #endif 4189 4190 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4191 dir = UE_GET_DIR(k) ? 1 : 0; 4192 sitd->sitd.sitd_endp = 4193 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4194 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4195 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4196 EHCI_SITD_SET_HUBA(huba) | 4197 EHCI_SITD_SET_DIR(dir)); 4198 4199 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4200 } /* End of frame */ 4201 4202 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4203 4204 stop = sitd; 4205 stop->xfer_next = NULL; 4206 exfer->ex_sitdstart = start; 4207 exfer->ex_sitdend = stop; 4208 4209 return 0; 4210 4211 fail: 4212 mutex_enter(&sc->sc_lock); 4213 ehci_soft_sitd_t *next; 4214 for (sitd = start; sitd; sitd = next) { 4215 next = sitd->xfer_next; 4216 ehci_free_sitd_locked(sc, sitd); 4217 } 4218 mutex_exit(&sc->sc_lock); 4219 4220 return err; 4221 } 4222 4223 Static void 4224 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4225 { 4226 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4227 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4228 4229 KASSERT(ex->ex_type == EX_FS_ISOC); 4230 4231 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4232 } 4233 4234 Static usbd_status 4235 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4236 { 4237 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4238 usbd_status __diagused err; 4239 4240 mutex_enter(&sc->sc_lock); 4241 err = usb_insert_transfer(xfer); 4242 mutex_exit(&sc->sc_lock); 4243 4244 KASSERT(err == USBD_NORMAL_COMPLETION); 4245 4246 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4247 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4248 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4249 ehci_soft_sitd_t *sitd; 4250 usb_dma_t *dma_buf; 4251 int i, j, k, frames; 4252 int offs, total_length; 4253 int frindex; 4254 u_int dir; 4255 4256 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4257 4258 sitd = NULL; 4259 total_length = 0; 4260 4261 4262 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4263 xfer->ux_flags, 0); 4264 4265 if (sc->sc_dying) 4266 return USBD_IOERROR; 4267 4268 /* 4269 * To avoid complication, don't allow a request right now that'll span 4270 * the entire frame table. To within 4 frames, to allow some leeway 4271 * on either side of where the hc currently is. 4272 */ 4273 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4274 xfer->ux_nframes >= sc->sc_flsize - 4) { 4275 printf("ehci: isoc descriptor requested that spans the entire" 4276 "frametable, too many frames\n"); 4277 return USBD_INVAL; 4278 } 4279 4280 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4281 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4282 KASSERT(exfer->ex_isdone); 4283 #ifdef DIAGNOSTIC 4284 exfer->ex_isdone = false; 4285 #endif 4286 4287 /* 4288 * Step 1: Initialize sitds. 4289 */ 4290 4291 frames = xfer->ux_nframes; 4292 dma_buf = &xfer->ux_dmabuf; 4293 offs = 0; 4294 4295 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4296 i++, sitd = sitd->xfer_next) { 4297 KASSERT(sitd != NULL); 4298 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4299 4300 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4301 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4302 4303 /* Set page0 index and offset - TP and T-offset are set below */ 4304 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4305 4306 total_length += xfer->ux_frlengths[i]; 4307 offs += xfer->ux_frlengths[i]; 4308 4309 sitd->sitd.sitd_buffer[1] = 4310 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4311 4312 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4313 4314 #if 0 4315 if (sc->sc_flags & EHCIF_FREESCALE) { 4316 // Set hub address to 0 if embedded TT is used. 4317 if (huba == sc->sc_addr) 4318 huba = 0; 4319 } 4320 #endif 4321 4322 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4323 dir = UE_GET_DIR(k) ? 1 : 0; 4324 KASSERT(sitd->sitd.sitd_endp == htole32( 4325 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4326 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4327 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4328 EHCI_SITD_SET_HUBA(huba) | 4329 EHCI_SITD_SET_DIR(dir))); 4330 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4331 4332 uint8_t sa = 0; 4333 uint8_t sb = 0; 4334 u_int temp, tlen; 4335 4336 if (dir == 0) { /* OUT */ 4337 temp = 0; 4338 tlen = xfer->ux_frlengths[i]; 4339 if (tlen <= 188) { 4340 temp |= 1; /* T-count = 1, TP = ALL */ 4341 tlen = 1; 4342 } else { 4343 tlen += 187; 4344 tlen /= 188; 4345 temp |= tlen; /* T-count = [1..6] */ 4346 temp |= 8; /* TP = Begin */ 4347 } 4348 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4349 4350 tlen += sa; 4351 4352 if (tlen >= 8) { 4353 sb = 0; 4354 } else { 4355 sb = (1 << tlen); 4356 } 4357 4358 sa = (1 << sa); 4359 sa = (sb - sa) & 0x3F; 4360 sb = 0; 4361 } else { 4362 sb = (-(4 << sa)) & 0xFE; 4363 sa = (1 << sa) & 0x3F; 4364 sa = 0x01; 4365 sb = 0xfc; 4366 } 4367 4368 sitd->sitd.sitd_sched = htole32( 4369 EHCI_SITD_SET_SMASK(sa) | 4370 EHCI_SITD_SET_CMASK(sb) 4371 ); 4372 4373 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4374 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4375 } /* End of frame */ 4376 4377 sitd = exfer->ex_sitdend; 4378 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4379 4380 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4381 sizeof(sitd->sitd.sitd_trans), 4382 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4383 4384 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4386 4387 /* 4388 * Part 2: Transfer descriptors have now been set up, now they must 4389 * be scheduled into the periodic frame list. Erk. Not wanting to 4390 * complicate matters, transfer is denied if the transfer spans 4391 * more than the period frame list. 4392 */ 4393 4394 mutex_enter(&sc->sc_lock); 4395 4396 /* Start inserting frames */ 4397 if (epipe->isoc.cur_xfers > 0) { 4398 frindex = epipe->isoc.next_frame; 4399 } else { 4400 frindex = EOREAD4(sc, EHCI_FRINDEX); 4401 frindex = frindex >> 3; /* Erase microframe index */ 4402 frindex += 2; 4403 } 4404 4405 if (frindex >= sc->sc_flsize) 4406 frindex &= (sc->sc_flsize - 1); 4407 4408 /* Whats the frame interval? */ 4409 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4410 4411 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4412 j++, sitd = sitd->xfer_next) { 4413 KASSERT(sitd); 4414 4415 usb_syncmem(&sc->sc_fldma, 4416 sizeof(ehci_link_t) * frindex, 4417 sizeof(ehci_link_t), 4418 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4419 4420 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4421 if (sitd->sitd.sitd_next == 0) 4422 /* 4423 * FIXME: frindex table gets initialized to NULL 4424 * or EHCI_NULL? 4425 */ 4426 sitd->sitd.sitd_next = EHCI_NULL; 4427 4428 usb_syncmem(&sitd->dma, 4429 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4430 sizeof(ehci_sitd_t), 4431 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4432 4433 sc->sc_flist[frindex] = 4434 htole32(EHCI_LINK_SITD | sitd->physaddr); 4435 4436 usb_syncmem(&sc->sc_fldma, 4437 sizeof(ehci_link_t) * frindex, 4438 sizeof(ehci_link_t), 4439 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4440 4441 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4442 sc->sc_softsitds[frindex] = sitd; 4443 if (sitd->frame_list.next != NULL) 4444 sitd->frame_list.next->frame_list.prev = sitd; 4445 sitd->slot = frindex; 4446 sitd->frame_list.prev = NULL; 4447 4448 frindex += i; 4449 if (frindex >= sc->sc_flsize) 4450 frindex -= sc->sc_flsize; 4451 } 4452 4453 epipe->isoc.cur_xfers++; 4454 epipe->isoc.next_frame = frindex; 4455 4456 ehci_add_intr_list(sc, exfer); 4457 xfer->ux_status = USBD_IN_PROGRESS; 4458 4459 mutex_exit(&sc->sc_lock); 4460 4461 return USBD_IN_PROGRESS; 4462 } 4463 4464 Static void 4465 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4466 { 4467 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4468 4469 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4470 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4471 } 4472 4473 Static void 4474 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4475 { 4476 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4477 4478 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4479 } 4480 4481 Static void 4482 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4483 { 4484 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4485 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4486 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4487 4488 KASSERT(mutex_owned(&sc->sc_lock)); 4489 4490 epipe->isoc.cur_xfers--; 4491 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4492 4493 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4494 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4495 } 4496 4497 4498 /************************/ 4499 4500 4501 Static int 4502 ehci_device_isoc_init(struct usbd_xfer *xfer) 4503 { 4504 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4505 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4506 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4507 ehci_soft_itd_t *itd, *prev, *start, *stop; 4508 int i, j, k; 4509 int frames, ufrperframe; 4510 int err; 4511 4512 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4513 4514 start = NULL; 4515 prev = NULL; 4516 itd = NULL; 4517 4518 KASSERT(xfer->ux_nframes != 0); 4519 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4520 KASSERT(exfer->ex_isdone); 4521 4522 exfer->ex_type = EX_ISOC; 4523 4524 /* 4525 * Step 1: Allocate and initialize itds, how many do we need? 4526 * One per transfer if interval >= 8 microframes, less if we use 4527 * multiple microframes per frame. 4528 */ 4529 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4530 if (i > 16 || i == 0) { 4531 /* Spec page 271 says intervals > 16 are invalid */ 4532 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4533 return USBD_INVAL; 4534 } 4535 4536 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4537 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4538 4539 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4540 itd = ehci_alloc_itd(sc); 4541 if (itd == NULL) { 4542 err = ENOMEM; 4543 goto fail; 4544 } 4545 4546 if (prev != NULL) { 4547 /* Maybe not as it's updated by the scheduling? */ 4548 prev->itd.itd_next = 4549 htole32(itd->physaddr | EHCI_LINK_ITD); 4550 4551 prev->xfer_next = itd; 4552 } else { 4553 start = itd; 4554 } 4555 4556 /* 4557 * Other special values 4558 */ 4559 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4560 itd->itd.itd_bufr[0] = htole32( 4561 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4562 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4563 4564 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4565 ? 1 : 0; 4566 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4567 itd->itd.itd_bufr[1] |= htole32( 4568 EHCI_ITD_SET_DIR(k) | 4569 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4570 4571 /* FIXME: handle invalid trans - should be done in openpipe */ 4572 itd->itd.itd_bufr[2] |= 4573 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4574 } /* End of frame */ 4575 4576 stop = itd; 4577 stop->xfer_next = NULL; 4578 4579 exfer->ex_itdstart = start; 4580 exfer->ex_itdend = stop; 4581 4582 return 0; 4583 fail: 4584 mutex_enter(&sc->sc_lock); 4585 ehci_soft_itd_t *next; 4586 for (itd = start; itd; itd = next) { 4587 next = itd->xfer_next; 4588 ehci_free_itd_locked(sc, itd); 4589 } 4590 mutex_exit(&sc->sc_lock); 4591 4592 return err; 4593 4594 } 4595 4596 Static void 4597 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4598 { 4599 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4600 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4601 4602 KASSERT(ex->ex_type == EX_ISOC); 4603 4604 ehci_free_itd_chain(sc, ex->ex_itdstart); 4605 } 4606 4607 Static usbd_status 4608 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4609 { 4610 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4611 usbd_status __diagused err; 4612 4613 mutex_enter(&sc->sc_lock); 4614 err = usb_insert_transfer(xfer); 4615 mutex_exit(&sc->sc_lock); 4616 4617 KASSERT(err == USBD_NORMAL_COMPLETION); 4618 4619 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4620 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4621 ehci_soft_itd_t *itd, *prev; 4622 usb_dma_t *dma_buf; 4623 int i, j; 4624 int frames, uframes, ufrperframe; 4625 int trans_count, offs, total_length; 4626 int frindex; 4627 4628 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4629 4630 prev = NULL; 4631 itd = NULL; 4632 trans_count = 0; 4633 total_length = 0; 4634 4635 DPRINTF("xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4636 4637 if (sc->sc_dying) 4638 return USBD_IOERROR; 4639 4640 /* 4641 * To avoid complication, don't allow a request right now that'll span 4642 * the entire frame table. To within 4 frames, to allow some leeway 4643 * on either side of where the hc currently is. 4644 */ 4645 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4646 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4647 DPRINTF( 4648 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4649 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4650 return USBD_INVAL; 4651 } 4652 4653 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4654 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4655 KASSERT(exfer->ex_isdone); 4656 #ifdef DIAGNOSTIC 4657 exfer->ex_isdone = false; 4658 #endif 4659 4660 /* 4661 * Step 1: Re-Initialize itds 4662 */ 4663 4664 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4665 if (i > 16 || i == 0) { 4666 /* Spec page 271 says intervals > 16 are invalid */ 4667 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4668 return USBD_INVAL; 4669 } 4670 4671 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4672 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4673 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4674 4675 if (frames == 0) { 4676 DPRINTF("frames == 0", 0, 0, 0, 0); 4677 return USBD_INVAL; 4678 } 4679 4680 dma_buf = &xfer->ux_dmabuf; 4681 offs = 0; 4682 4683 itd = exfer->ex_itdstart; 4684 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4685 int froffs = offs; 4686 4687 if (prev != NULL) { 4688 prev->itd.itd_next = 4689 htole32(itd->physaddr | EHCI_LINK_ITD); 4690 usb_syncmem(&prev->dma, 4691 prev->offs + offsetof(ehci_itd_t, itd_next), 4692 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4693 prev->xfer_next = itd; 4694 } 4695 4696 /* 4697 * Step 1.5, initialize uframes 4698 */ 4699 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4700 /* Calculate which page in the list this starts in */ 4701 int addr = DMAADDR(dma_buf, froffs); 4702 addr = EHCI_PAGE_OFFSET(addr); 4703 addr += (offs - froffs); 4704 addr = EHCI_PAGE(addr); 4705 addr /= EHCI_PAGE_SIZE; 4706 4707 /* 4708 * This gets the initial offset into the first page, 4709 * looks how far further along the current uframe 4710 * offset is. Works out how many pages that is. 4711 */ 4712 4713 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4714 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4715 EHCI_ITD_SET_PG(addr) | 4716 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4717 4718 total_length += xfer->ux_frlengths[trans_count]; 4719 offs += xfer->ux_frlengths[trans_count]; 4720 trans_count++; 4721 4722 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4723 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4724 break; 4725 } 4726 } 4727 4728 /* 4729 * Step 1.75, set buffer pointers. To simplify matters, all 4730 * pointers are filled out for the next 7 hardware pages in 4731 * the dma block, so no need to worry what pages to cover 4732 * and what to not. 4733 */ 4734 4735 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4736 /* 4737 * Don't try to lookup a page that's past the end 4738 * of buffer 4739 */ 4740 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4741 if (page_offs >= dma_buf->udma_block->size) 4742 break; 4743 4744 uint64_t page = DMAADDR(dma_buf, page_offs); 4745 page = EHCI_PAGE(page); 4746 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4747 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4748 } 4749 /* 4750 * Other special values 4751 */ 4752 4753 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4754 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4755 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4756 4757 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4758 ? 1 : 0; 4759 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4760 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4761 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4762 4763 /* FIXME: handle invalid trans */ 4764 itd->itd.itd_bufr[2] |= 4765 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4766 4767 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4768 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4769 4770 prev = itd; 4771 } /* End of frame */ 4772 4773 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4774 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4775 4776 /* 4777 * Part 2: Transfer descriptors have now been set up, now they must 4778 * be scheduled into the period frame list. Erk. Not wanting to 4779 * complicate matters, transfer is denied if the transfer spans 4780 * more than the period frame list. 4781 */ 4782 4783 mutex_enter(&sc->sc_lock); 4784 4785 /* Start inserting frames */ 4786 if (epipe->isoc.cur_xfers > 0) { 4787 frindex = epipe->isoc.next_frame; 4788 } else { 4789 frindex = EOREAD4(sc, EHCI_FRINDEX); 4790 frindex = frindex >> 3; /* Erase microframe index */ 4791 frindex += 2; 4792 } 4793 4794 if (frindex >= sc->sc_flsize) 4795 frindex &= (sc->sc_flsize - 1); 4796 4797 /* What's the frame interval? */ 4798 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4799 if (i / USB_UFRAMES_PER_FRAME == 0) 4800 i = 1; 4801 else 4802 i /= USB_UFRAMES_PER_FRAME; 4803 4804 itd = exfer->ex_itdstart; 4805 for (j = 0; j < frames; j++) { 4806 KASSERTMSG(itd != NULL, "frame %d\n", j); 4807 4808 usb_syncmem(&sc->sc_fldma, 4809 sizeof(ehci_link_t) * frindex, 4810 sizeof(ehci_link_t), 4811 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4812 4813 itd->itd.itd_next = sc->sc_flist[frindex]; 4814 if (itd->itd.itd_next == 0) 4815 /* 4816 * FIXME: frindex table gets initialized to NULL 4817 * or EHCI_NULL? 4818 */ 4819 itd->itd.itd_next = EHCI_NULL; 4820 4821 usb_syncmem(&itd->dma, 4822 itd->offs + offsetof(ehci_itd_t, itd_next), 4823 sizeof(itd->itd.itd_next), 4824 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4825 4826 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4827 4828 usb_syncmem(&sc->sc_fldma, 4829 sizeof(ehci_link_t) * frindex, 4830 sizeof(ehci_link_t), 4831 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4832 4833 itd->frame_list.next = sc->sc_softitds[frindex]; 4834 sc->sc_softitds[frindex] = itd; 4835 if (itd->frame_list.next != NULL) 4836 itd->frame_list.next->frame_list.prev = itd; 4837 itd->slot = frindex; 4838 itd->frame_list.prev = NULL; 4839 4840 frindex += i; 4841 if (frindex >= sc->sc_flsize) 4842 frindex -= sc->sc_flsize; 4843 4844 itd = itd->xfer_next; 4845 } 4846 4847 epipe->isoc.cur_xfers++; 4848 epipe->isoc.next_frame = frindex; 4849 4850 ehci_add_intr_list(sc, exfer); 4851 xfer->ux_status = USBD_IN_PROGRESS; 4852 4853 mutex_exit(&sc->sc_lock); 4854 4855 return USBD_IN_PROGRESS; 4856 } 4857 4858 Static void 4859 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4860 { 4861 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4862 4863 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4864 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4865 } 4866 4867 Static void 4868 ehci_device_isoc_close(struct usbd_pipe *pipe) 4869 { 4870 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4871 4872 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4873 } 4874 4875 Static void 4876 ehci_device_isoc_done(struct usbd_xfer *xfer) 4877 { 4878 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4879 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4880 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4881 4882 KASSERT(mutex_owned(&sc->sc_lock)); 4883 4884 epipe->isoc.cur_xfers--; 4885 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4886 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4887 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4888 } 4889
Indexes created Tue Sep 23 07:09:52 GMT 2025