ehci.c revision 1.254.8.4
1 /* $NetBSD: ehci.c,v 1.254.8.4 2018/08/25 11:29:52 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.254.8.4 2018/08/25 11:29:52 martin Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static void ehci_intrlist_timeout(void *); 172 Static void ehci_doorbell(void *); 173 Static void ehci_pcd(void *); 174 175 Static struct usbd_xfer * 176 ehci_allocx(struct usbd_bus *, unsigned int); 177 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 178 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_doorbell, "ehcidb"); 416 417 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 418 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 419 420 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 421 ehci_doorbell, sc); 422 KASSERT(sc->sc_doorbell_si != NULL); 423 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 424 ehci_pcd, sc); 425 KASSERT(sc->sc_pcd_si != NULL); 426 427 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 428 429 vers = EREAD2(sc, EHCI_HCIVERSION); 430 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 431 vers >> 8, vers & 0xff); 432 433 sparams = EREAD4(sc, EHCI_HCSPARAMS); 434 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 435 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 436 ncomp = EHCI_HCS_N_CC(sparams); 437 if (ncomp != sc->sc_ncomp) { 438 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 439 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 440 #if NOHCI == 0 || NUHCI == 0 441 aprint_error("%s: ohci or uhci probably not configured\n", 442 device_xname(sc->sc_dev)); 443 #endif 444 if (ncomp < sc->sc_ncomp) 445 sc->sc_ncomp = ncomp; 446 } 447 if (sc->sc_ncomp > 0) { 448 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 449 aprint_normal("%s: %d companion controller%s, %d port%s%s", 450 device_xname(sc->sc_dev), sc->sc_ncomp, 451 sc->sc_ncomp!=1 ? "s" : "", 452 EHCI_HCS_N_PCC(sparams), 453 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 454 sc->sc_ncomp!=1 ? " each" : ""); 455 if (sc->sc_comps[0]) { 456 aprint_normal(":"); 457 for (i = 0; i < sc->sc_ncomp; i++) 458 aprint_normal(" %s", 459 device_xname(sc->sc_comps[i])); 460 } 461 aprint_normal("\n"); 462 } 463 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 464 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 465 466 cparams = EREAD4(sc, EHCI_HCCPARAMS); 467 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 468 469 if (EHCI_HCC_64BIT(cparams)) { 470 /* MUST clear segment register if 64 bit capable. */ 471 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 472 } 473 474 if (cparams & EHCI_HCC_IST_FULLFRAME) { 475 sc->sc_istthreshold = 0; 476 } else { 477 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 478 } 479 480 sc->sc_bus.ub_revision = USBREV_2_0; 481 sc->sc_bus.ub_usedma = true; 482 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 483 484 /* Reset the controller */ 485 DPRINTF("resetting", 0, 0, 0, 0); 486 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 487 usb_delay_ms(&sc->sc_bus, 1); 488 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 489 for (i = 0; i < 100; i++) { 490 usb_delay_ms(&sc->sc_bus, 1); 491 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 492 if (!hcr) 493 break; 494 } 495 if (hcr) { 496 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 497 return EIO; 498 } 499 if (sc->sc_vendor_init) 500 sc->sc_vendor_init(sc); 501 502 /* XXX need proper intr scheduling */ 503 sc->sc_rand = 96; 504 505 /* frame list size at default, read back what we got and use that */ 506 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 507 case 0: sc->sc_flsize = 1024; break; 508 case 1: sc->sc_flsize = 512; break; 509 case 2: sc->sc_flsize = 256; break; 510 case 3: return EIO; 511 } 512 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 513 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 514 if (err) 515 return err; 516 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 517 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 518 519 for (i = 0; i < sc->sc_flsize; i++) { 520 sc->sc_flist[i] = EHCI_NULL; 521 } 522 523 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 524 525 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 526 KM_SLEEP); 527 if (sc->sc_softitds == NULL) 528 return ENOMEM; 529 LIST_INIT(&sc->sc_freeitds); 530 LIST_INIT(&sc->sc_freesitds); 531 TAILQ_INIT(&sc->sc_intrhead); 532 533 /* Set up the bus struct. */ 534 sc->sc_bus.ub_methods = &ehci_bus_methods; 535 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 536 537 sc->sc_eintrs = EHCI_NORMAL_INTRS; 538 539 /* 540 * Allocate the interrupt dummy QHs. These are arranged to give poll 541 * intervals that are powers of 2 times 1ms. 542 */ 543 for (i = 0; i < EHCI_INTRQHS; i++) { 544 sqh = ehci_alloc_sqh(sc); 545 if (sqh == NULL) { 546 err = ENOMEM; 547 goto bad1; 548 } 549 sc->sc_islots[i].sqh = sqh; 550 } 551 for (i = 0; i < EHCI_INTRQHS; i++) { 552 sqh = sc->sc_islots[i].sqh; 553 if (i == 0) { 554 /* The last (1ms) QH terminates. */ 555 sqh->qh.qh_link = EHCI_NULL; 556 sqh->next = NULL; 557 } else { 558 /* Otherwise the next QH has half the poll interval */ 559 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 560 sqh->qh.qh_link = htole32(sqh->next->physaddr | 561 EHCI_LINK_QH); 562 } 563 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 564 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 565 sqh->qh.qh_curqtd = EHCI_NULL; 566 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 567 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 568 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 569 sqh->sqtd = NULL; 570 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 572 } 573 /* Point the frame list at the last level (128ms). */ 574 for (i = 0; i < sc->sc_flsize; i++) { 575 int j; 576 577 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 578 revbits[i & (EHCI_MAX_POLLRATE-1)]; 579 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 580 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 581 i)].sqh->physaddr); 582 } 583 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 584 BUS_DMASYNC_PREWRITE); 585 586 /* Allocate dummy QH that starts the async list. */ 587 sqh = ehci_alloc_sqh(sc); 588 if (sqh == NULL) { 589 err = ENOMEM; 590 goto bad1; 591 } 592 /* Fill the QH */ 593 sqh->qh.qh_endp = 594 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 595 sqh->qh.qh_link = 596 htole32(sqh->physaddr | EHCI_LINK_QH); 597 sqh->qh.qh_curqtd = EHCI_NULL; 598 sqh->next = NULL; 599 /* Fill the overlay qTD */ 600 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 601 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 602 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 603 sqh->sqtd = NULL; 604 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 605 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 606 #ifdef EHCI_DEBUG 607 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 608 ehci_dump_sqh(sqh); 609 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 610 #endif 611 612 /* Point to async list */ 613 sc->sc_async_head = sqh; 614 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 615 616 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 617 618 /* Turn on controller */ 619 EOWRITE4(sc, EHCI_USBCMD, 620 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 621 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 622 EHCI_CMD_ASE | 623 EHCI_CMD_PSE | 624 EHCI_CMD_RS); 625 626 /* Take over port ownership */ 627 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 628 629 for (i = 0; i < 100; i++) { 630 usb_delay_ms(&sc->sc_bus, 1); 631 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 632 if (!hcr) 633 break; 634 } 635 if (hcr) { 636 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 637 return EIO; 638 } 639 640 /* Enable interrupts */ 641 DPRINTF("enabling interupts", 0, 0, 0, 0); 642 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 643 644 return 0; 645 646 #if 0 647 bad2: 648 ehci_free_sqh(sc, sc->sc_async_head); 649 #endif 650 bad1: 651 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 652 return err; 653 } 654 655 int 656 ehci_intr(void *v) 657 { 658 ehci_softc_t *sc = v; 659 int ret = 0; 660 661 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 662 663 if (sc == NULL) 664 return 0; 665 666 mutex_spin_enter(&sc->sc_intr_lock); 667 668 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 669 goto done; 670 671 /* If we get an interrupt while polling, then just ignore it. */ 672 if (sc->sc_bus.ub_usepolling) { 673 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 674 675 if (intrs) 676 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 677 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 678 goto done; 679 } 680 681 ret = ehci_intr1(sc); 682 683 done: 684 mutex_spin_exit(&sc->sc_intr_lock); 685 return ret; 686 } 687 688 Static int 689 ehci_intr1(ehci_softc_t *sc) 690 { 691 uint32_t intrs, eintrs; 692 693 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 694 695 /* In case the interrupt occurs before initialization has completed. */ 696 if (sc == NULL) { 697 #ifdef DIAGNOSTIC 698 printf("ehci_intr1: sc == NULL\n"); 699 #endif 700 return 0; 701 } 702 703 KASSERT(mutex_owned(&sc->sc_intr_lock)); 704 705 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 706 if (!intrs) 707 return 0; 708 709 eintrs = intrs & sc->sc_eintrs; 710 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 711 EOREAD4(sc, EHCI_USBSTS), eintrs); 712 if (!eintrs) 713 return 0; 714 715 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 716 if (eintrs & EHCI_STS_IAA) { 717 DPRINTF("door bell", 0, 0, 0, 0); 718 kpreempt_disable(); 719 KASSERT(sc->sc_doorbell_si != NULL); 720 softint_schedule(sc->sc_doorbell_si); 721 kpreempt_enable(); 722 eintrs &= ~EHCI_STS_IAA; 723 } 724 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 725 DPRINTF("INT=%jd ERRINT=%jd", 726 eintrs & EHCI_STS_INT ? 1 : 0, 727 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 728 usb_schedsoftintr(&sc->sc_bus); 729 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 730 } 731 if (eintrs & EHCI_STS_HSE) { 732 printf("%s: unrecoverable error, controller halted\n", 733 device_xname(sc->sc_dev)); 734 /* XXX what else */ 735 } 736 if (eintrs & EHCI_STS_PCD) { 737 kpreempt_disable(); 738 KASSERT(sc->sc_pcd_si != NULL); 739 softint_schedule(sc->sc_pcd_si); 740 kpreempt_enable(); 741 eintrs &= ~EHCI_STS_PCD; 742 } 743 744 if (eintrs != 0) { 745 /* Block unprocessed interrupts. */ 746 sc->sc_eintrs &= ~eintrs; 747 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 748 printf("%s: blocking intrs 0x%x\n", 749 device_xname(sc->sc_dev), eintrs); 750 } 751 752 return 1; 753 } 754 755 Static void 756 ehci_doorbell(void *addr) 757 { 758 ehci_softc_t *sc = addr; 759 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 760 761 mutex_enter(&sc->sc_lock); 762 cv_broadcast(&sc->sc_doorbell); 763 mutex_exit(&sc->sc_lock); 764 } 765 766 Static void 767 ehci_pcd(void *addr) 768 { 769 ehci_softc_t *sc = addr; 770 struct usbd_xfer *xfer; 771 u_char *p; 772 int i, m; 773 774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 775 776 mutex_enter(&sc->sc_lock); 777 xfer = sc->sc_intrxfer; 778 779 if (xfer == NULL) { 780 /* Just ignore the change. */ 781 goto done; 782 } 783 784 p = xfer->ux_buf; 785 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 786 memset(p, 0, xfer->ux_length); 787 for (i = 1; i <= m; i++) { 788 /* Pick out CHANGE bits from the status reg. */ 789 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 790 p[i/8] |= 1 << (i%8); 791 if (i % 8 == 7) 792 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 793 } 794 xfer->ux_actlen = xfer->ux_length; 795 xfer->ux_status = USBD_NORMAL_COMPLETION; 796 797 usb_transfer_complete(xfer); 798 799 done: 800 mutex_exit(&sc->sc_lock); 801 } 802 803 Static void 804 ehci_softintr(void *v) 805 { 806 struct usbd_bus *bus = v; 807 ehci_softc_t *sc = EHCI_BUS2SC(bus); 808 struct ehci_xfer *ex, *nextex; 809 810 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 811 812 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 813 814 ex_completeq_t cq; 815 TAILQ_INIT(&cq); 816 817 /* 818 * The only explanation I can think of for why EHCI is as brain dead 819 * as UHCI interrupt-wise is that Intel was involved in both. 820 * An interrupt just tells us that something is done, we have no 821 * clue what, so we need to scan through all active transfers. :-( 822 */ 823 824 /* 825 * ehci_idone will remove transfer from sc->sc_intrhead if it's 826 * complete and add to our cq list 827 * 828 */ 829 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 830 switch (ex->ex_type) { 831 case EX_CTRL: 832 case EX_BULK: 833 case EX_INTR: 834 ehci_check_qh_intr(sc, ex, &cq); 835 break; 836 case EX_ISOC: 837 ehci_check_itd_intr(sc, ex, &cq); 838 break; 839 case EX_FS_ISOC: 840 ehci_check_sitd_intr(sc, ex, &cq); 841 break; 842 default: 843 KASSERT(false); 844 } 845 846 } 847 848 /* 849 * We abuse ex_next for the interrupt and complete lists and 850 * interrupt transfers will get re-added here so use 851 * the _SAFE version of TAILQ_FOREACH. 852 */ 853 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 854 usb_transfer_complete(&ex->ex_xfer); 855 } 856 857 /* Schedule a callout to catch any dropped transactions. */ 858 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 859 !TAILQ_EMPTY(&sc->sc_intrhead)) 860 callout_reset(&sc->sc_tmo_intrlist, 861 hz, ehci_intrlist_timeout, sc); 862 } 863 864 Static void 865 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 866 { 867 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 868 uint32_t status; 869 870 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 871 872 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 873 874 if (ex->ex_type == EX_CTRL) { 875 fsqtd = ex->ex_setup; 876 lsqtd = ex->ex_status; 877 } else { 878 fsqtd = ex->ex_sqtdstart; 879 lsqtd = ex->ex_sqtdend; 880 } 881 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 882 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 883 884 /* 885 * If the last TD is still active we need to check whether there 886 * is an error somewhere in the middle, or whether there was a 887 * short packet (SPD and not ACTIVE). 888 */ 889 usb_syncmem(&lsqtd->dma, 890 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 891 sizeof(lsqtd->qtd.qtd_status), 892 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 893 status = le32toh(lsqtd->qtd.qtd_status); 894 usb_syncmem(&lsqtd->dma, 895 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 896 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 897 if (status & EHCI_QTD_ACTIVE) { 898 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 899 900 /* last qTD has already been checked */ 901 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 902 usb_syncmem(&sqtd->dma, 903 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 904 sizeof(sqtd->qtd.qtd_status), 905 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 906 status = le32toh(sqtd->qtd.qtd_status); 907 usb_syncmem(&sqtd->dma, 908 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 909 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 910 /* If there's an active QTD the xfer isn't done. */ 911 if (status & EHCI_QTD_ACTIVE) 912 break; 913 /* Any kind of error makes the xfer done. */ 914 if (status & EHCI_QTD_HALTED) 915 goto done; 916 /* Handle short packets */ 917 if (EHCI_QTD_GET_BYTES(status) != 0) { 918 /* 919 * If we get here for a control transfer then 920 * we need to let the hardware complete the 921 * status phase. That is, we're not done 922 * quite yet. 923 * 924 * Otherwise, we're done. 925 */ 926 if (ex->ex_type == EX_CTRL) { 927 break; 928 } 929 goto done; 930 } 931 } 932 DPRINTFN(10, "ex=%#jx std=%#jx still active", 933 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 934 #ifdef EHCI_DEBUG 935 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 936 ehci_dump_sqtds(ex->ex_sqtdstart); 937 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 938 #endif 939 return; 940 } 941 done: 942 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 943 ehci_idone(ex, cq); 944 } 945 946 Static void 947 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 948 { 949 ehci_soft_itd_t *itd; 950 int i; 951 952 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 953 954 KASSERT(mutex_owned(&sc->sc_lock)); 955 956 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 957 return; 958 959 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 960 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 961 962 itd = ex->ex_itdend; 963 964 /* 965 * check no active transfers in last itd, meaning we're finished 966 */ 967 968 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 969 sizeof(itd->itd.itd_ctl), 970 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 971 972 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 973 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 974 break; 975 } 976 977 if (i == EHCI_ITD_NUFRAMES) { 978 goto done; /* All 8 descriptors inactive, it's done */ 979 } 980 981 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 982 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 983 984 DPRINTFN(10, "ex %#jx itd %#jx still active", 985 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 986 return; 987 done: 988 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 989 ehci_idone(ex, cq); 990 } 991 992 void 993 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 994 { 995 ehci_soft_sitd_t *sitd; 996 997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 998 999 KASSERT(mutex_owned(&sc->sc_lock)); 1000 1001 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1002 return; 1003 1004 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1005 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1006 1007 sitd = ex->ex_sitdend; 1008 1009 /* 1010 * check no active transfers in last sitd, meaning we're finished 1011 */ 1012 1013 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1014 sizeof(sitd->sitd.sitd_trans), 1015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1016 1017 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1021 1022 if (active) 1023 return; 1024 1025 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1026 ehci_idone(ex, cq); 1027 } 1028 1029 1030 Static void 1031 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1032 { 1033 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1034 struct usbd_xfer *xfer = &ex->ex_xfer; 1035 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1036 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1037 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1038 uint32_t status = 0, nstatus = 0; 1039 int actlen = 0; 1040 1041 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1042 1043 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1044 1045 /* 1046 * If software has completed it, either by cancellation 1047 * or timeout, drop it on the floor. 1048 */ 1049 if (xfer->ux_status != USBD_IN_PROGRESS) { 1050 KASSERT(xfer->ux_status == USBD_CANCELLED || 1051 xfer->ux_status == USBD_TIMEOUT); 1052 DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1053 return; 1054 } 1055 1056 /* 1057 * Cancel the timeout and the task, which have not yet 1058 * run. If they have already fired, at worst they are 1059 * waiting for the lock. They will see that the xfer 1060 * is no longer in progress and give up. 1061 */ 1062 callout_stop(&xfer->ux_callout); 1063 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 1064 1065 #ifdef DIAGNOSTIC 1066 #ifdef EHCI_DEBUG 1067 if (ex->ex_isdone) { 1068 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1069 ehci_dump_exfer(ex); 1070 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1071 } 1072 #endif 1073 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1074 ex->ex_type, xfer->ux_status); 1075 ex->ex_isdone = true; 1076 #endif 1077 1078 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1079 (uintptr_t)epipe, 0, 0); 1080 1081 /* The transfer is done, compute actual length and status. */ 1082 if (ex->ex_type == EX_ISOC) { 1083 /* HS isoc transfer */ 1084 1085 struct ehci_soft_itd *itd; 1086 int i, nframes, len, uframes; 1087 1088 nframes = 0; 1089 1090 #ifdef EHCI_DEBUG 1091 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1092 ehci_dump_itds(ex->ex_itdstart); 1093 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1094 #endif 1095 1096 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1097 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1098 1099 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1100 usb_syncmem(&itd->dma, 1101 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1102 sizeof(itd->itd.itd_ctl), 1103 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1104 1105 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1106 /* 1107 * XXX - driver didn't fill in the frame full 1108 * of uframes. This leads to scheduling 1109 * inefficiencies, but working around 1110 * this doubles complexity of tracking 1111 * an xfer. 1112 */ 1113 if (nframes >= xfer->ux_nframes) 1114 break; 1115 1116 status = le32toh(itd->itd.itd_ctl[i]); 1117 len = EHCI_ITD_GET_LEN(status); 1118 if (EHCI_ITD_GET_STATUS(status) != 0) 1119 len = 0; /*No valid data on error*/ 1120 1121 xfer->ux_frlengths[nframes++] = len; 1122 actlen += len; 1123 } 1124 usb_syncmem(&itd->dma, 1125 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1126 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1127 1128 if (nframes >= xfer->ux_nframes) 1129 break; 1130 } 1131 1132 xfer->ux_actlen = actlen; 1133 xfer->ux_status = USBD_NORMAL_COMPLETION; 1134 goto end; 1135 } else if (ex->ex_type == EX_FS_ISOC) { 1136 /* FS isoc transfer */ 1137 struct ehci_soft_sitd *sitd; 1138 int nframes, len; 1139 1140 nframes = 0; 1141 1142 for (sitd = ex->ex_sitdstart; sitd != NULL; 1143 sitd = sitd->xfer_next) { 1144 usb_syncmem(&sitd->dma, 1145 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1146 sizeof(sitd->sitd.sitd_trans), 1147 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1148 1149 /* 1150 * XXX - driver didn't fill in the frame full 1151 * of uframes. This leads to scheduling 1152 * inefficiencies, but working around 1153 * this doubles complexity of tracking 1154 * an xfer. 1155 */ 1156 if (nframes >= xfer->ux_nframes) 1157 break; 1158 1159 status = le32toh(sitd->sitd.sitd_trans); 1160 usb_syncmem(&sitd->dma, 1161 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1162 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1163 1164 len = EHCI_SITD_GET_LEN(status); 1165 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1166 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1167 /* No valid data on error */ 1168 len = xfer->ux_frlengths[nframes]; 1169 } 1170 1171 /* 1172 * frlengths[i]: # of bytes to send 1173 * len: # of bytes host didn't send 1174 */ 1175 xfer->ux_frlengths[nframes] -= len; 1176 /* frlengths[i]: # of bytes host sent */ 1177 actlen += xfer->ux_frlengths[nframes++]; 1178 1179 if (nframes >= xfer->ux_nframes) 1180 break; 1181 } 1182 1183 xfer->ux_actlen = actlen; 1184 xfer->ux_status = USBD_NORMAL_COMPLETION; 1185 goto end; 1186 } 1187 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1188 ex->ex_type == EX_BULK); 1189 1190 /* Continue processing xfers using queue heads */ 1191 if (ex->ex_type == EX_CTRL) { 1192 fsqtd = ex->ex_setup; 1193 lsqtd = ex->ex_status; 1194 } else { 1195 fsqtd = ex->ex_sqtdstart; 1196 lsqtd = ex->ex_sqtdend; 1197 } 1198 #ifdef EHCI_DEBUG 1199 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1200 ehci_dump_sqtds(fsqtd); 1201 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1202 #endif 1203 1204 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1205 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1206 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1207 nstatus = le32toh(sqtd->qtd.qtd_status); 1208 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1209 BUS_DMASYNC_PREREAD); 1210 if (nstatus & EHCI_QTD_ACTIVE) 1211 break; 1212 1213 status = nstatus; 1214 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1215 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1216 } 1217 1218 /* 1219 * If there are left over TDs we need to update the toggle. 1220 * The default pipe doesn't need it since control transfers 1221 * start the toggle at 0 every time. 1222 * For a short transfer we need to update the toggle for the missing 1223 * packets within the qTD. 1224 */ 1225 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1226 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1227 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1228 status, nstatus, 0, 0); 1229 #if 0 1230 ehci_dump_sqh(epipe->sqh); 1231 ehci_dump_sqtds(ex->ex_sqtdstart); 1232 #endif 1233 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1234 } 1235 1236 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1237 status, 0); 1238 xfer->ux_actlen = actlen; 1239 if (status & EHCI_QTD_HALTED) { 1240 #ifdef EHCI_DEBUG 1241 DPRINTF("halted addr=%jd endpt=0x%02jx", 1242 xfer->ux_pipe->up_dev->ud_addr, 1243 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1244 0, 0); 1245 DPRINTF("cerr=%jd pid=%jd", 1246 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1247 0, 0); 1248 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1249 status & EHCI_QTD_ACTIVE ? 1 : 0, 1250 status & EHCI_QTD_HALTED ? 1 : 0, 1251 status & EHCI_QTD_BUFERR ? 1 : 0, 1252 status & EHCI_QTD_BABBLE ? 1 : 0); 1253 1254 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1255 status & EHCI_QTD_XACTERR ? 1 : 0, 1256 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1257 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1258 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1259 1260 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1261 ehci_dump_sqh(epipe->sqh); 1262 ehci_dump_sqtds(ex->ex_sqtdstart); 1263 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1264 #endif 1265 /* low&full speed has an extra error flag */ 1266 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1267 EHCI_QH_SPEED_HIGH) 1268 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1269 else 1270 status &= EHCI_QTD_STATERRS; 1271 if (status == 0) /* no other errors means a stall */ { 1272 xfer->ux_status = USBD_STALLED; 1273 } else { 1274 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1275 } 1276 /* XXX need to reset TT on missed microframe */ 1277 if (status & EHCI_QTD_MISSEDMICRO) { 1278 printf("%s: missed microframe, TT reset not " 1279 "implemented, hub might be inoperational\n", 1280 device_xname(sc->sc_dev)); 1281 } 1282 } else { 1283 xfer->ux_status = USBD_NORMAL_COMPLETION; 1284 } 1285 1286 end: 1287 1288 ehci_del_intr_list(sc, ex); 1289 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1290 1291 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1292 } 1293 1294 Static void 1295 ehci_poll(struct usbd_bus *bus) 1296 { 1297 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1298 1299 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1300 1301 #ifdef EHCI_DEBUG 1302 static int last; 1303 int new; 1304 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1305 if (new != last) { 1306 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1307 last = new; 1308 } 1309 #endif 1310 1311 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1312 mutex_spin_enter(&sc->sc_intr_lock); 1313 ehci_intr1(sc); 1314 mutex_spin_exit(&sc->sc_intr_lock); 1315 } 1316 } 1317 1318 void 1319 ehci_childdet(device_t self, device_t child) 1320 { 1321 struct ehci_softc *sc = device_private(self); 1322 1323 KASSERT(sc->sc_child == child); 1324 sc->sc_child = NULL; 1325 } 1326 1327 int 1328 ehci_detach(struct ehci_softc *sc, int flags) 1329 { 1330 int rv = 0; 1331 1332 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1333 1334 if (sc->sc_child != NULL) 1335 rv = config_detach(sc->sc_child, flags); 1336 1337 if (rv != 0) 1338 return rv; 1339 1340 callout_halt(&sc->sc_tmo_intrlist, NULL); 1341 callout_destroy(&sc->sc_tmo_intrlist); 1342 1343 /* XXX free other data structures XXX */ 1344 if (sc->sc_softitds) 1345 kmem_free(sc->sc_softitds, 1346 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1347 cv_destroy(&sc->sc_doorbell); 1348 1349 #if 0 1350 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1351 1352 softint_disestablish(sc->sc_doorbell_si); 1353 softint_disestablish(sc->sc_pcd_si); 1354 1355 mutex_destroy(&sc->sc_lock); 1356 mutex_destroy(&sc->sc_intr_lock); 1357 #endif 1358 1359 pool_cache_destroy(sc->sc_xferpool); 1360 1361 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1362 1363 return rv; 1364 } 1365 1366 1367 int 1368 ehci_activate(device_t self, enum devact act) 1369 { 1370 struct ehci_softc *sc = device_private(self); 1371 1372 switch (act) { 1373 case DVACT_DEACTIVATE: 1374 sc->sc_dying = 1; 1375 return 0; 1376 default: 1377 return EOPNOTSUPP; 1378 } 1379 } 1380 1381 /* 1382 * Handle suspend/resume. 1383 * 1384 * We need to switch to polling mode here, because this routine is 1385 * called from an interrupt context. This is all right since we 1386 * are almost suspended anyway. 1387 * 1388 * Note that this power handler isn't to be registered directly; the 1389 * bus glue needs to call out to it. 1390 */ 1391 bool 1392 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1393 { 1394 ehci_softc_t *sc = device_private(dv); 1395 int i; 1396 uint32_t cmd, hcr; 1397 1398 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1399 1400 mutex_spin_enter(&sc->sc_intr_lock); 1401 sc->sc_bus.ub_usepolling++; 1402 mutex_spin_exit(&sc->sc_intr_lock); 1403 1404 for (i = 1; i <= sc->sc_noport; i++) { 1405 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1406 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1407 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1408 } 1409 1410 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1411 1412 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1413 EOWRITE4(sc, EHCI_USBCMD, cmd); 1414 1415 for (i = 0; i < 100; i++) { 1416 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1417 if (hcr == 0) 1418 break; 1419 1420 usb_delay_ms(&sc->sc_bus, 1); 1421 } 1422 if (hcr != 0) 1423 printf("%s: reset timeout\n", device_xname(dv)); 1424 1425 cmd &= ~EHCI_CMD_RS; 1426 EOWRITE4(sc, EHCI_USBCMD, cmd); 1427 1428 for (i = 0; i < 100; i++) { 1429 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1430 if (hcr == EHCI_STS_HCH) 1431 break; 1432 1433 usb_delay_ms(&sc->sc_bus, 1); 1434 } 1435 if (hcr != EHCI_STS_HCH) 1436 printf("%s: config timeout\n", device_xname(dv)); 1437 1438 mutex_spin_enter(&sc->sc_intr_lock); 1439 sc->sc_bus.ub_usepolling--; 1440 mutex_spin_exit(&sc->sc_intr_lock); 1441 1442 return true; 1443 } 1444 1445 bool 1446 ehci_resume(device_t dv, const pmf_qual_t *qual) 1447 { 1448 ehci_softc_t *sc = device_private(dv); 1449 int i; 1450 uint32_t cmd, hcr; 1451 1452 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1453 1454 /* restore things in case the bios sucks */ 1455 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1456 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1457 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1458 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1459 1460 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1461 1462 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1463 1464 hcr = 0; 1465 for (i = 1; i <= sc->sc_noport; i++) { 1466 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1467 if ((cmd & EHCI_PS_PO) == 0 && 1468 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1469 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1470 hcr = 1; 1471 } 1472 } 1473 1474 if (hcr) { 1475 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1476 1477 for (i = 1; i <= sc->sc_noport; i++) { 1478 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1479 if ((cmd & EHCI_PS_PO) == 0 && 1480 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1481 EOWRITE4(sc, EHCI_PORTSC(i), 1482 cmd & ~EHCI_PS_FPR); 1483 } 1484 } 1485 1486 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1487 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1488 1489 for (i = 0; i < 100; i++) { 1490 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1491 if (hcr != EHCI_STS_HCH) 1492 break; 1493 1494 usb_delay_ms(&sc->sc_bus, 1); 1495 } 1496 if (hcr == EHCI_STS_HCH) 1497 printf("%s: config timeout\n", device_xname(dv)); 1498 1499 return true; 1500 } 1501 1502 /* 1503 * Shut down the controller when the system is going down. 1504 */ 1505 bool 1506 ehci_shutdown(device_t self, int flags) 1507 { 1508 ehci_softc_t *sc = device_private(self); 1509 1510 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1511 1512 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1513 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1514 return true; 1515 } 1516 1517 Static struct usbd_xfer * 1518 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1519 { 1520 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1521 struct usbd_xfer *xfer; 1522 1523 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1524 if (xfer != NULL) { 1525 memset(xfer, 0, sizeof(struct ehci_xfer)); 1526 1527 /* Initialise this always so we can call remove on it. */ 1528 usb_init_task(&xfer->ux_aborttask, ehci_timeout_task, xfer, 1529 USB_TASKQ_MPSAFE); 1530 #ifdef DIAGNOSTIC 1531 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1532 ex->ex_isdone = true; 1533 xfer->ux_state = XFER_BUSY; 1534 #endif 1535 } 1536 return xfer; 1537 } 1538 1539 Static void 1540 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1541 { 1542 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1543 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1544 1545 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1546 xfer->ux_state); 1547 KASSERT(ex->ex_isdone); 1548 1549 #ifdef DIAGNOSTIC 1550 xfer->ux_state = XFER_FREE; 1551 #endif 1552 1553 pool_cache_put(sc->sc_xferpool, xfer); 1554 } 1555 1556 Static void 1557 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1558 { 1559 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1560 1561 *lock = &sc->sc_lock; 1562 } 1563 1564 Static void 1565 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1566 { 1567 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1568 1569 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1570 1571 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1572 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1573 #ifdef EHCI_DEBUG 1574 if (ehcidebug) 1575 usbd_dump_pipe(pipe); 1576 #endif 1577 epipe->nexttoggle = 0; 1578 } 1579 1580 Static void 1581 ehci_noop(struct usbd_pipe *pipe) 1582 { 1583 } 1584 1585 #ifdef EHCI_DEBUG 1586 /* 1587 * Unused function - this is meant to be called from a kernel 1588 * debugger. 1589 */ 1590 void 1591 ehci_dump(void) 1592 { 1593 ehci_softc_t *sc = theehci; 1594 int i; 1595 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1596 EOREAD4(sc, EHCI_USBCMD), 1597 EOREAD4(sc, EHCI_USBSTS), 1598 EOREAD4(sc, EHCI_USBINTR)); 1599 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1600 EOREAD4(sc, EHCI_FRINDEX), 1601 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1602 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1603 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1604 for (i = 1; i <= sc->sc_noport; i++) 1605 printf("port %d status=0x%08x\n", i, 1606 EOREAD4(sc, EHCI_PORTSC(i))); 1607 } 1608 1609 Static void 1610 ehci_dump_regs(ehci_softc_t *sc) 1611 { 1612 int i; 1613 1614 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1615 1616 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1617 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1618 EOREAD4(sc, EHCI_USBINTR), 0); 1619 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1620 "async = 0x%08jx", 1621 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1622 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1623 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1624 for (i = 1; i <= sc->sc_noport; i += 2) { 1625 if (i == sc->sc_noport) { 1626 DPRINTF("port %jd status = 0x%08jx", i, 1627 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1628 } else { 1629 DPRINTF("port %jd status = 0x%08jx port %jd " 1630 "status = 0x%08jx", 1631 i, EOREAD4(sc, EHCI_PORTSC(i)), 1632 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1633 } 1634 } 1635 } 1636 1637 #define ehci_dump_link(link, type) do { \ 1638 DPRINTF(" link 0x%08jx (T = %jd):", \ 1639 link, \ 1640 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1641 if (type) { \ 1642 DPRINTF( \ 1643 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1644 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1645 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1646 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1647 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1648 } \ 1649 } while(0) 1650 1651 Static void 1652 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1653 { 1654 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1655 int i; 1656 uint32_t stop = 0; 1657 1658 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1659 ehci_dump_sqtd(sqtd); 1660 usb_syncmem(&sqtd->dma, 1661 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1662 sizeof(sqtd->qtd), 1663 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1664 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1665 usb_syncmem(&sqtd->dma, 1666 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1667 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1668 } 1669 if (!stop) 1670 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1671 } 1672 1673 Static void 1674 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1675 { 1676 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1677 1678 usb_syncmem(&sqtd->dma, sqtd->offs, 1679 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1680 1681 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1682 0, 0); 1683 ehci_dump_qtd(&sqtd->qtd); 1684 1685 usb_syncmem(&sqtd->dma, sqtd->offs, 1686 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1687 } 1688 1689 Static void 1690 ehci_dump_qtd(ehci_qtd_t *qtd) 1691 { 1692 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1693 uint32_t s = le32toh(qtd->qtd_status); 1694 1695 DPRINTFN(10, 1696 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1697 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1698 DPRINTFN(10, 1699 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1700 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1701 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1702 DPRINTFN(10, 1703 " cerr = %jd pid = %jd stat = %jx", 1704 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1705 0); 1706 DPRINTFN(10, 1707 "active =%jd halted=%jd buferr=%jd babble=%jd", 1708 s & EHCI_QTD_ACTIVE ? 1 : 0, 1709 s & EHCI_QTD_HALTED ? 1 : 0, 1710 s & EHCI_QTD_BUFERR ? 1 : 0, 1711 s & EHCI_QTD_BABBLE ? 1 : 0); 1712 DPRINTFN(10, 1713 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1714 s & EHCI_QTD_XACTERR ? 1 : 0, 1715 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1716 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1717 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1718 DPRINTFN(10, 1719 "buffer[0] = %#jx buffer[1] = %#jx " 1720 "buffer[2] = %#jx buffer[3] = %#jx", 1721 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1722 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1723 DPRINTFN(10, 1724 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1725 } 1726 1727 Static void 1728 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1729 { 1730 ehci_qh_t *qh = &sqh->qh; 1731 ehci_link_t link; 1732 uint32_t endp, endphub; 1733 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1734 1735 usb_syncmem(&sqh->dma, sqh->offs, 1736 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1737 1738 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1739 link = le32toh(qh->qh_link); 1740 ehci_dump_link(link, true); 1741 1742 endp = le32toh(qh->qh_endp); 1743 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1744 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1745 "eps = %jd", 1746 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1747 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1748 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1749 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1750 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1751 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1752 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1753 1754 endphub = le32toh(qh->qh_endphub); 1755 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1756 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1757 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1758 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1759 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1760 EHCI_QH_GET_MULT(endphub), 0); 1761 1762 link = le32toh(qh->qh_curqtd); 1763 ehci_dump_link(link, false); 1764 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1765 ehci_dump_qtd(&qh->qh_qtd); 1766 1767 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1768 BUS_DMASYNC_PREREAD); 1769 } 1770 1771 Static void 1772 ehci_dump_itds(ehci_soft_itd_t *itd) 1773 { 1774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1775 int i; 1776 uint32_t stop = 0; 1777 1778 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1779 ehci_dump_itd(itd); 1780 usb_syncmem(&itd->dma, 1781 itd->offs + offsetof(ehci_itd_t, itd_next), 1782 sizeof(itd->itd), 1783 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1784 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1785 usb_syncmem(&itd->dma, 1786 itd->offs + offsetof(ehci_itd_t, itd_next), 1787 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1788 } 1789 if (!stop) 1790 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1791 } 1792 1793 Static void 1794 ehci_dump_itd(struct ehci_soft_itd *itd) 1795 { 1796 ehci_isoc_trans_t t; 1797 ehci_isoc_bufr_ptr_t b, b2, b3; 1798 int i; 1799 1800 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1801 1802 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1803 1804 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1805 t = le32toh(itd->itd.itd_ctl[i]); 1806 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1807 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1808 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1809 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1810 EHCI_ITD_GET_OFFS(t), 0); 1811 } 1812 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1813 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1814 DPRINTF(" %jx", 1815 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1816 1817 b = le32toh(itd->itd.itd_bufr[0]); 1818 b2 = le32toh(itd->itd.itd_bufr[1]); 1819 b3 = le32toh(itd->itd.itd_bufr[2]); 1820 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1821 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1822 DPRINTF(" maxpkt = %jx multi = %jx", 1823 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1824 } 1825 1826 Static void 1827 ehci_dump_sitd(struct ehci_soft_itd *itd) 1828 { 1829 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1830 1831 DPRINTF("SITD %#jx next = %p prev = %#jx", 1832 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1833 (uintptr_t)itd->frame_list.prev, 0); 1834 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1835 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1836 } 1837 1838 Static void 1839 ehci_dump_exfer(struct ehci_xfer *ex) 1840 { 1841 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1842 1843 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1844 ex->ex_isdone, 0); 1845 1846 switch (ex->ex_type) { 1847 case EX_CTRL: 1848 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1849 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1850 (uintptr_t)ex->ex_status, 0); 1851 break; 1852 case EX_BULK: 1853 case EX_INTR: 1854 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1855 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1856 0, 0); 1857 break; 1858 case EX_ISOC: 1859 DPRINTF(" itdstart = %#jx itdend = %#jx", 1860 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1861 break; 1862 case EX_FS_ISOC: 1863 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1864 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1865 0, 0); 1866 break; 1867 default: 1868 DPRINTF(" unknown type", 0, 0, 0, 0); 1869 } 1870 } 1871 #endif 1872 1873 Static usbd_status 1874 ehci_open(struct usbd_pipe *pipe) 1875 { 1876 struct usbd_device *dev = pipe->up_dev; 1877 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1878 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1879 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1880 uint8_t addr = dev->ud_addr; 1881 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1882 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1883 ehci_soft_qh_t *sqh; 1884 usbd_status err; 1885 int ival, speed, naks; 1886 int hshubaddr, hshubport; 1887 1888 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1889 1890 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1891 ed->bEndpointAddress, rhaddr); 1892 1893 if (dev->ud_myhsport) { 1894 /* 1895 * When directly attached FS/LS device while doing embedded 1896 * transaction translations and we are the hub, set the hub 1897 * address to 0 (us). 1898 */ 1899 if (!(sc->sc_flags & EHCIF_ETTF) 1900 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1901 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1902 } else { 1903 hshubaddr = 0; 1904 } 1905 hshubport = dev->ud_myhsport->up_portno; 1906 } else { 1907 hshubaddr = 0; 1908 hshubport = 0; 1909 } 1910 1911 if (sc->sc_dying) 1912 return USBD_IOERROR; 1913 1914 /* toggle state needed for bulk endpoints */ 1915 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1916 1917 if (addr == rhaddr) { 1918 switch (ed->bEndpointAddress) { 1919 case USB_CONTROL_ENDPOINT: 1920 pipe->up_methods = &roothub_ctrl_methods; 1921 break; 1922 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1923 pipe->up_methods = &ehci_root_intr_methods; 1924 break; 1925 default: 1926 DPRINTF("bad bEndpointAddress 0x%02jx", 1927 ed->bEndpointAddress, 0, 0, 0); 1928 return USBD_INVAL; 1929 } 1930 return USBD_NORMAL_COMPLETION; 1931 } 1932 1933 /* XXX All this stuff is only valid for async. */ 1934 switch (dev->ud_speed) { 1935 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1936 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1937 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1938 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1939 } 1940 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1941 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1942 0); 1943 return USBD_INVAL; 1944 } 1945 1946 /* 1947 * For interrupt transfer, nak throttling must be disabled, but for 1948 * the other transfer type, nak throttling should be enabled from the 1949 * viewpoint that avoids the memory thrashing. 1950 */ 1951 naks = (xfertype == UE_INTERRUPT) ? 0 1952 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1953 1954 /* Allocate sqh for everything, save isoc xfers */ 1955 if (xfertype != UE_ISOCHRONOUS) { 1956 sqh = ehci_alloc_sqh(sc); 1957 if (sqh == NULL) 1958 return USBD_NOMEM; 1959 /* qh_link filled when the QH is added */ 1960 sqh->qh.qh_endp = htole32( 1961 EHCI_QH_SET_ADDR(addr) | 1962 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1963 EHCI_QH_SET_EPS(speed) | 1964 EHCI_QH_DTC | 1965 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1966 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1967 EHCI_QH_CTL : 0) | 1968 EHCI_QH_SET_NRL(naks) 1969 ); 1970 sqh->qh.qh_endphub = htole32( 1971 EHCI_QH_SET_MULT(1) | 1972 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1973 ); 1974 if (speed != EHCI_QH_SPEED_HIGH) 1975 sqh->qh.qh_endphub |= htole32( 1976 EHCI_QH_SET_PORT(hshubport) | 1977 EHCI_QH_SET_HUBA(hshubaddr) | 1978 (xfertype == UE_INTERRUPT ? 1979 EHCI_QH_SET_CMASK(0x08) : 0) 1980 ); 1981 sqh->qh.qh_curqtd = EHCI_NULL; 1982 /* Fill the overlay qTD */ 1983 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1984 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1985 sqh->qh.qh_qtd.qtd_status = htole32(0); 1986 1987 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1989 epipe->sqh = sqh; 1990 } else { 1991 sqh = NULL; 1992 } /*xfertype == UE_ISOC*/ 1993 1994 switch (xfertype) { 1995 case UE_CONTROL: 1996 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1997 0, &epipe->ctrl.reqdma); 1998 #ifdef EHCI_DEBUG 1999 if (err) 2000 printf("ehci_open: usb_allocmem()=%d\n", err); 2001 #endif 2002 if (err) 2003 goto bad; 2004 pipe->up_methods = &ehci_device_ctrl_methods; 2005 mutex_enter(&sc->sc_lock); 2006 ehci_add_qh(sc, sqh, sc->sc_async_head); 2007 mutex_exit(&sc->sc_lock); 2008 break; 2009 case UE_BULK: 2010 pipe->up_methods = &ehci_device_bulk_methods; 2011 mutex_enter(&sc->sc_lock); 2012 ehci_add_qh(sc, sqh, sc->sc_async_head); 2013 mutex_exit(&sc->sc_lock); 2014 break; 2015 case UE_INTERRUPT: 2016 pipe->up_methods = &ehci_device_intr_methods; 2017 ival = pipe->up_interval; 2018 if (ival == USBD_DEFAULT_INTERVAL) { 2019 if (speed == EHCI_QH_SPEED_HIGH) { 2020 if (ed->bInterval > 16) { 2021 /* 2022 * illegal with high-speed, but there 2023 * were documentation bugs in the spec, 2024 * so be generous 2025 */ 2026 ival = 256; 2027 } else 2028 ival = (1 << (ed->bInterval - 1)) / 8; 2029 } else 2030 ival = ed->bInterval; 2031 } 2032 err = ehci_device_setintr(sc, sqh, ival); 2033 if (err) 2034 goto bad; 2035 break; 2036 case UE_ISOCHRONOUS: 2037 pipe->up_serialise = false; 2038 if (speed == EHCI_QH_SPEED_HIGH) 2039 pipe->up_methods = &ehci_device_isoc_methods; 2040 else 2041 pipe->up_methods = &ehci_device_fs_isoc_methods; 2042 if (ed->bInterval == 0 || ed->bInterval > 16) { 2043 printf("ehci: opening pipe with invalid bInterval\n"); 2044 err = USBD_INVAL; 2045 goto bad; 2046 } 2047 if (UGETW(ed->wMaxPacketSize) == 0) { 2048 printf("ehci: zero length endpoint open request\n"); 2049 err = USBD_INVAL; 2050 goto bad; 2051 } 2052 epipe->isoc.next_frame = 0; 2053 epipe->isoc.cur_xfers = 0; 2054 break; 2055 default: 2056 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2057 err = USBD_INVAL; 2058 goto bad; 2059 } 2060 return USBD_NORMAL_COMPLETION; 2061 2062 bad: 2063 if (sqh != NULL) { 2064 mutex_enter(&sc->sc_lock); 2065 ehci_free_sqh(sc, sqh); 2066 mutex_exit(&sc->sc_lock); 2067 } 2068 return err; 2069 } 2070 2071 /* 2072 * Add an ED to the schedule. Called with USB lock held. 2073 */ 2074 Static void 2075 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2076 { 2077 2078 KASSERT(mutex_owned(&sc->sc_lock)); 2079 2080 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2081 2082 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2083 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2084 2085 sqh->next = head->next; 2086 sqh->qh.qh_link = head->qh.qh_link; 2087 2088 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2089 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2090 2091 head->next = sqh; 2092 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2093 2094 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2095 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2096 2097 #ifdef EHCI_DEBUG 2098 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2099 ehci_dump_sqh(sqh); 2100 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2101 #endif 2102 } 2103 2104 /* 2105 * Remove an ED from the schedule. Called with USB lock held. 2106 */ 2107 Static void 2108 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2109 { 2110 ehci_soft_qh_t *p; 2111 2112 KASSERT(mutex_owned(&sc->sc_lock)); 2113 2114 /* XXX */ 2115 for (p = head; p != NULL && p->next != sqh; p = p->next) 2116 ; 2117 if (p == NULL) 2118 panic("ehci_rem_qh: ED not found"); 2119 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2120 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2121 p->next = sqh->next; 2122 p->qh.qh_link = sqh->qh.qh_link; 2123 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2124 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2125 2126 ehci_sync_hc(sc); 2127 } 2128 2129 Static void 2130 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2131 { 2132 int i; 2133 uint32_t status; 2134 2135 /* Save toggle bit and ping status. */ 2136 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2137 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2138 status = sqh->qh.qh_qtd.qtd_status & 2139 htole32(EHCI_QTD_TOGGLE_MASK | 2140 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2141 /* Set HALTED to make hw leave it alone. */ 2142 sqh->qh.qh_qtd.qtd_status = 2143 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2144 usb_syncmem(&sqh->dma, 2145 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2146 sizeof(sqh->qh.qh_qtd.qtd_status), 2147 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2148 sqh->qh.qh_curqtd = 0; 2149 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2150 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2151 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2152 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2153 sqh->sqtd = sqtd; 2154 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2155 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2156 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2157 sqh->qh.qh_qtd.qtd_status = status; 2158 usb_syncmem(&sqh->dma, 2159 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2160 sizeof(sqh->qh.qh_qtd.qtd_status), 2161 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2162 } 2163 2164 /* 2165 * Ensure that the HC has released all references to the QH. We do this 2166 * by asking for a Async Advance Doorbell interrupt and then we wait for 2167 * the interrupt. 2168 * To make this easier we first obtain exclusive use of the doorbell. 2169 */ 2170 Static void 2171 ehci_sync_hc(ehci_softc_t *sc) 2172 { 2173 int error __diagused; 2174 2175 KASSERT(mutex_owned(&sc->sc_lock)); 2176 2177 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2178 2179 if (sc->sc_dying) { 2180 DPRINTF("dying", 0, 0, 0, 0); 2181 return; 2182 } 2183 2184 /* ask for doorbell */ 2185 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2186 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2187 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2188 2189 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2190 2191 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2192 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2193 #ifdef DIAGNOSTIC 2194 if (error == EWOULDBLOCK) { 2195 printf("ehci_sync_hc: timed out\n"); 2196 } else if (error) { 2197 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2198 } 2199 #endif 2200 } 2201 2202 Static void 2203 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2204 { 2205 2206 KASSERT(mutex_owned(&sc->sc_lock)); 2207 2208 for (; itd != NULL; itd = itd->xfer_next) { 2209 struct ehci_soft_itd *prev = itd->frame_list.prev; 2210 2211 /* Unlink itd from hardware chain, or frame array */ 2212 if (prev == NULL) { /* We're at the table head */ 2213 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2214 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2215 usb_syncmem(&sc->sc_fldma, 2216 sizeof(ehci_link_t) * itd->slot, 2217 sizeof(ehci_link_t), 2218 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2219 2220 if (itd->frame_list.next != NULL) 2221 itd->frame_list.next->frame_list.prev = NULL; 2222 } else { 2223 /* XXX this part is untested... */ 2224 prev->itd.itd_next = itd->itd.itd_next; 2225 usb_syncmem(&itd->dma, 2226 itd->offs + offsetof(ehci_itd_t, itd_next), 2227 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2228 2229 prev->frame_list.next = itd->frame_list.next; 2230 if (itd->frame_list.next != NULL) 2231 itd->frame_list.next->frame_list.prev = prev; 2232 } 2233 } 2234 } 2235 2236 Static void 2237 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2238 { 2239 struct ehci_soft_itd *next; 2240 2241 mutex_enter(&sc->sc_lock); 2242 next = NULL; 2243 for (; itd != NULL; itd = next) { 2244 next = itd->xfer_next; 2245 ehci_free_itd_locked(sc, itd); 2246 } 2247 mutex_exit(&sc->sc_lock); 2248 } 2249 2250 Static void 2251 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2252 { 2253 2254 KASSERT(mutex_owned(&sc->sc_lock)); 2255 2256 for (; sitd != NULL; sitd = sitd->xfer_next) { 2257 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2258 2259 /* Unlink sitd from hardware chain, or frame array */ 2260 if (prev == NULL) { /* We're at the table head */ 2261 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2262 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2263 usb_syncmem(&sc->sc_fldma, 2264 sizeof(ehci_link_t) * sitd->slot, 2265 sizeof(ehci_link_t), 2266 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2267 2268 if (sitd->frame_list.next != NULL) 2269 sitd->frame_list.next->frame_list.prev = NULL; 2270 } else { 2271 /* XXX this part is untested... */ 2272 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2273 usb_syncmem(&sitd->dma, 2274 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2275 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2276 2277 prev->frame_list.next = sitd->frame_list.next; 2278 if (sitd->frame_list.next != NULL) 2279 sitd->frame_list.next->frame_list.prev = prev; 2280 } 2281 } 2282 } 2283 2284 Static void 2285 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2286 { 2287 2288 mutex_enter(&sc->sc_lock); 2289 struct ehci_soft_sitd *next = NULL; 2290 for (; sitd != NULL; sitd = next) { 2291 next = sitd->xfer_next; 2292 ehci_free_sitd_locked(sc, sitd); 2293 } 2294 mutex_exit(&sc->sc_lock); 2295 } 2296 2297 /***********/ 2298 2299 Static int 2300 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2301 void *buf, int buflen) 2302 { 2303 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2304 usb_hub_descriptor_t hubd; 2305 usb_port_status_t ps; 2306 uint16_t len, value, index; 2307 int l, totlen = 0; 2308 int port, i; 2309 uint32_t v; 2310 2311 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2312 2313 if (sc->sc_dying) 2314 return -1; 2315 2316 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2317 0, 0); 2318 2319 len = UGETW(req->wLength); 2320 value = UGETW(req->wValue); 2321 index = UGETW(req->wIndex); 2322 2323 #define C(x,y) ((x) | ((y) << 8)) 2324 switch (C(req->bRequest, req->bmRequestType)) { 2325 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2326 if (len == 0) 2327 break; 2328 switch (value) { 2329 case C(0, UDESC_DEVICE): { 2330 usb_device_descriptor_t devd; 2331 totlen = min(buflen, sizeof(devd)); 2332 memcpy(&devd, buf, totlen); 2333 USETW(devd.idVendor, sc->sc_id_vendor); 2334 memcpy(buf, &devd, totlen); 2335 break; 2336 2337 } 2338 #define sd ((usb_string_descriptor_t *)buf) 2339 case C(1, UDESC_STRING): 2340 /* Vendor */ 2341 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2342 break; 2343 case C(2, UDESC_STRING): 2344 /* Product */ 2345 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2346 break; 2347 #undef sd 2348 default: 2349 /* default from usbroothub */ 2350 return buflen; 2351 } 2352 break; 2353 2354 /* Hub requests */ 2355 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2356 break; 2357 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2358 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2359 value, 0, 0); 2360 if (index < 1 || index > sc->sc_noport) { 2361 return -1; 2362 } 2363 port = EHCI_PORTSC(index); 2364 v = EOREAD4(sc, port); 2365 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2366 v &= ~EHCI_PS_CLEAR; 2367 switch (value) { 2368 case UHF_PORT_ENABLE: 2369 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2370 break; 2371 case UHF_PORT_SUSPEND: 2372 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2373 break; 2374 v &= ~EHCI_PS_SUSP; 2375 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2376 /* see USB2 spec ch. 7.1.7.7 */ 2377 usb_delay_ms(&sc->sc_bus, 20); 2378 EOWRITE4(sc, port, v); 2379 usb_delay_ms(&sc->sc_bus, 2); 2380 #ifdef DEBUG 2381 v = EOREAD4(sc, port); 2382 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2383 printf("ehci: resume failed: %x\n", v); 2384 #endif 2385 break; 2386 case UHF_PORT_POWER: 2387 if (sc->sc_hasppc) 2388 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2389 break; 2390 case UHF_PORT_TEST: 2391 DPRINTF("clear port test %jd", index, 0, 0, 0); 2392 break; 2393 case UHF_PORT_INDICATOR: 2394 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2395 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2396 break; 2397 case UHF_C_PORT_CONNECTION: 2398 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2399 break; 2400 case UHF_C_PORT_ENABLE: 2401 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2402 break; 2403 case UHF_C_PORT_SUSPEND: 2404 /* how? */ 2405 break; 2406 case UHF_C_PORT_OVER_CURRENT: 2407 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2408 break; 2409 case UHF_C_PORT_RESET: 2410 sc->sc_isreset[index] = 0; 2411 break; 2412 default: 2413 return -1; 2414 } 2415 #if 0 2416 switch(value) { 2417 case UHF_C_PORT_CONNECTION: 2418 case UHF_C_PORT_ENABLE: 2419 case UHF_C_PORT_SUSPEND: 2420 case UHF_C_PORT_OVER_CURRENT: 2421 case UHF_C_PORT_RESET: 2422 default: 2423 break; 2424 } 2425 #endif 2426 break; 2427 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2428 if (len == 0) 2429 break; 2430 if ((value & 0xff) != 0) { 2431 return -1; 2432 } 2433 totlen = min(buflen, sizeof(hubd)); 2434 memcpy(&hubd, buf, totlen); 2435 hubd.bNbrPorts = sc->sc_noport; 2436 v = EOREAD4(sc, EHCI_HCSPARAMS); 2437 USETW(hubd.wHubCharacteristics, 2438 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2439 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2440 ? UHD_PORT_IND : 0); 2441 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2442 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2443 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2444 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2445 totlen = min(totlen, hubd.bDescLength); 2446 memcpy(buf, &hubd, totlen); 2447 break; 2448 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2449 if (len != 4) { 2450 return -1; 2451 } 2452 memset(buf, 0, len); /* ? XXX */ 2453 totlen = len; 2454 break; 2455 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2456 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2457 if (index < 1 || index > sc->sc_noport) { 2458 return -1; 2459 } 2460 if (len != 4) { 2461 return -1; 2462 } 2463 v = EOREAD4(sc, EHCI_PORTSC(index)); 2464 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2465 2466 i = UPS_HIGH_SPEED; 2467 if (sc->sc_flags & EHCIF_ETTF) { 2468 /* 2469 * If we are doing embedded transaction translation, 2470 * then directly attached LS/FS devices are reset by 2471 * the EHCI controller itself. PSPD is encoded 2472 * the same way as in USBSTATUS. 2473 */ 2474 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2475 } 2476 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2477 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2478 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2479 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2480 if (v & EHCI_PS_PR) i |= UPS_RESET; 2481 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2482 if (sc->sc_vendor_port_status) 2483 i = sc->sc_vendor_port_status(sc, v, i); 2484 USETW(ps.wPortStatus, i); 2485 i = 0; 2486 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2487 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2488 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2489 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2490 USETW(ps.wPortChange, i); 2491 totlen = min(len, sizeof(ps)); 2492 memcpy(buf, &ps, totlen); 2493 break; 2494 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2495 return -1; 2496 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2497 break; 2498 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2499 if (index < 1 || index > sc->sc_noport) { 2500 return -1; 2501 } 2502 port = EHCI_PORTSC(index); 2503 v = EOREAD4(sc, port); 2504 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2505 v &= ~EHCI_PS_CLEAR; 2506 switch(value) { 2507 case UHF_PORT_ENABLE: 2508 EOWRITE4(sc, port, v | EHCI_PS_PE); 2509 break; 2510 case UHF_PORT_SUSPEND: 2511 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2512 break; 2513 case UHF_PORT_RESET: 2514 DPRINTF("reset port %jd", index, 0, 0, 0); 2515 if (EHCI_PS_IS_LOWSPEED(v) 2516 && sc->sc_ncomp > 0 2517 && !(sc->sc_flags & EHCIF_ETTF)) { 2518 /* 2519 * Low speed device on non-ETTF controller or 2520 * unaccompanied controller, give up ownership. 2521 */ 2522 ehci_disown(sc, index, 1); 2523 break; 2524 } 2525 /* Start reset sequence. */ 2526 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2527 EOWRITE4(sc, port, v | EHCI_PS_PR); 2528 /* Wait for reset to complete. */ 2529 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2530 if (sc->sc_dying) { 2531 return -1; 2532 } 2533 /* 2534 * An embedded transaction translator will automatically 2535 * terminate the reset sequence so there's no need to 2536 * it. 2537 */ 2538 v = EOREAD4(sc, port); 2539 if (v & EHCI_PS_PR) { 2540 /* Terminate reset sequence. */ 2541 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2542 /* Wait for HC to complete reset. */ 2543 usb_delay_ms(&sc->sc_bus, 2544 EHCI_PORT_RESET_COMPLETE); 2545 if (sc->sc_dying) { 2546 return -1; 2547 } 2548 } 2549 2550 v = EOREAD4(sc, port); 2551 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2552 if (v & EHCI_PS_PR) { 2553 printf("%s: port reset timeout\n", 2554 device_xname(sc->sc_dev)); 2555 return USBD_TIMEOUT; 2556 } 2557 if (!(v & EHCI_PS_PE)) { 2558 /* Not a high speed device, give up ownership.*/ 2559 ehci_disown(sc, index, 0); 2560 break; 2561 } 2562 sc->sc_isreset[index] = 1; 2563 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2564 v, 0, 0); 2565 break; 2566 case UHF_PORT_POWER: 2567 DPRINTF("set port power %jd (has PPC = %jd)", index, 2568 sc->sc_hasppc, 0, 0); 2569 if (sc->sc_hasppc) 2570 EOWRITE4(sc, port, v | EHCI_PS_PP); 2571 break; 2572 case UHF_PORT_TEST: 2573 DPRINTF("set port test %jd", index, 0, 0, 0); 2574 break; 2575 case UHF_PORT_INDICATOR: 2576 DPRINTF("set port ind %jd", index, 0, 0, 0); 2577 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2578 break; 2579 default: 2580 return -1; 2581 } 2582 break; 2583 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2584 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2585 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2586 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2587 break; 2588 default: 2589 /* default from usbroothub */ 2590 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2591 2592 return buflen; 2593 } 2594 2595 DPRINTF("returning %jd", totlen, 0, 0, 0); 2596 2597 return totlen; 2598 } 2599 2600 Static void 2601 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2602 { 2603 int port; 2604 uint32_t v; 2605 2606 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2607 2608 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2609 #ifdef DIAGNOSTIC 2610 if (sc->sc_npcomp != 0) { 2611 int i = (index-1) / sc->sc_npcomp; 2612 if (i >= sc->sc_ncomp) 2613 printf("%s: strange port\n", 2614 device_xname(sc->sc_dev)); 2615 else 2616 printf("%s: handing over %s speed device on " 2617 "port %d to %s\n", 2618 device_xname(sc->sc_dev), 2619 lowspeed ? "low" : "full", 2620 index, sc->sc_comps[i] ? 2621 device_xname(sc->sc_comps[i]) : 2622 "companion controller"); 2623 } else { 2624 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2625 } 2626 #endif 2627 port = EHCI_PORTSC(index); 2628 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2629 EOWRITE4(sc, port, v | EHCI_PS_PO); 2630 } 2631 2632 Static usbd_status 2633 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2634 { 2635 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2636 usbd_status err; 2637 2638 /* Insert last in queue. */ 2639 mutex_enter(&sc->sc_lock); 2640 err = usb_insert_transfer(xfer); 2641 mutex_exit(&sc->sc_lock); 2642 if (err) 2643 return err; 2644 2645 /* Pipe isn't running, start first */ 2646 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2647 } 2648 2649 Static usbd_status 2650 ehci_root_intr_start(struct usbd_xfer *xfer) 2651 { 2652 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2653 2654 if (sc->sc_dying) 2655 return USBD_IOERROR; 2656 2657 mutex_enter(&sc->sc_lock); 2658 sc->sc_intrxfer = xfer; 2659 mutex_exit(&sc->sc_lock); 2660 2661 return USBD_IN_PROGRESS; 2662 } 2663 2664 /* Abort a root interrupt request. */ 2665 Static void 2666 ehci_root_intr_abort(struct usbd_xfer *xfer) 2667 { 2668 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2669 2670 KASSERT(mutex_owned(&sc->sc_lock)); 2671 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2672 2673 sc->sc_intrxfer = NULL; 2674 2675 xfer->ux_status = USBD_CANCELLED; 2676 usb_transfer_complete(xfer); 2677 } 2678 2679 /* Close the root pipe. */ 2680 Static void 2681 ehci_root_intr_close(struct usbd_pipe *pipe) 2682 { 2683 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2684 2685 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2686 2687 KASSERT(mutex_owned(&sc->sc_lock)); 2688 2689 sc->sc_intrxfer = NULL; 2690 } 2691 2692 Static void 2693 ehci_root_intr_done(struct usbd_xfer *xfer) 2694 { 2695 } 2696 2697 /************************/ 2698 2699 Static ehci_soft_qh_t * 2700 ehci_alloc_sqh(ehci_softc_t *sc) 2701 { 2702 ehci_soft_qh_t *sqh; 2703 usbd_status err; 2704 int i, offs; 2705 usb_dma_t dma; 2706 2707 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2708 2709 mutex_enter(&sc->sc_lock); 2710 if (sc->sc_freeqhs == NULL) { 2711 DPRINTF("allocating chunk", 0, 0, 0, 0); 2712 mutex_exit(&sc->sc_lock); 2713 2714 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2715 EHCI_PAGE_SIZE, &dma); 2716 #ifdef EHCI_DEBUG 2717 if (err) 2718 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2719 #endif 2720 if (err) 2721 return NULL; 2722 2723 mutex_enter(&sc->sc_lock); 2724 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2725 offs = i * EHCI_SQH_SIZE; 2726 sqh = KERNADDR(&dma, offs); 2727 sqh->physaddr = DMAADDR(&dma, offs); 2728 sqh->dma = dma; 2729 sqh->offs = offs; 2730 sqh->next = sc->sc_freeqhs; 2731 sc->sc_freeqhs = sqh; 2732 } 2733 } 2734 sqh = sc->sc_freeqhs; 2735 sc->sc_freeqhs = sqh->next; 2736 mutex_exit(&sc->sc_lock); 2737 2738 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2739 sqh->next = NULL; 2740 return sqh; 2741 } 2742 2743 Static void 2744 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2745 { 2746 KASSERT(mutex_owned(&sc->sc_lock)); 2747 2748 sqh->next = sc->sc_freeqhs; 2749 sc->sc_freeqhs = sqh; 2750 } 2751 2752 Static ehci_soft_qtd_t * 2753 ehci_alloc_sqtd(ehci_softc_t *sc) 2754 { 2755 ehci_soft_qtd_t *sqtd = NULL; 2756 usbd_status err; 2757 int i, offs; 2758 usb_dma_t dma; 2759 2760 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2761 2762 mutex_enter(&sc->sc_lock); 2763 if (sc->sc_freeqtds == NULL) { 2764 DPRINTF("allocating chunk", 0, 0, 0, 0); 2765 mutex_exit(&sc->sc_lock); 2766 2767 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2768 EHCI_PAGE_SIZE, &dma); 2769 #ifdef EHCI_DEBUG 2770 if (err) 2771 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2772 #endif 2773 if (err) 2774 goto done; 2775 2776 mutex_enter(&sc->sc_lock); 2777 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2778 offs = i * EHCI_SQTD_SIZE; 2779 sqtd = KERNADDR(&dma, offs); 2780 sqtd->physaddr = DMAADDR(&dma, offs); 2781 sqtd->dma = dma; 2782 sqtd->offs = offs; 2783 2784 sqtd->nextqtd = sc->sc_freeqtds; 2785 sc->sc_freeqtds = sqtd; 2786 } 2787 } 2788 2789 sqtd = sc->sc_freeqtds; 2790 sc->sc_freeqtds = sqtd->nextqtd; 2791 mutex_exit(&sc->sc_lock); 2792 2793 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2794 sqtd->nextqtd = NULL; 2795 sqtd->xfer = NULL; 2796 2797 done: 2798 return sqtd; 2799 } 2800 2801 Static void 2802 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2803 { 2804 2805 mutex_enter(&sc->sc_lock); 2806 sqtd->nextqtd = sc->sc_freeqtds; 2807 sc->sc_freeqtds = sqtd; 2808 mutex_exit(&sc->sc_lock); 2809 } 2810 2811 Static int 2812 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2813 int alen, int rd, ehci_soft_qtd_t **sp) 2814 { 2815 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2816 uint16_t flags = xfer->ux_flags; 2817 2818 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2819 2820 ASSERT_SLEEPABLE(); 2821 KASSERT(sp); 2822 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2823 2824 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2825 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2826 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2827 KM_SLEEP); 2828 exfer->ex_nsqtd = nsqtd; 2829 2830 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2831 alen, nsqtd, flags); 2832 2833 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2834 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2835 if (cur == NULL) 2836 goto nomem; 2837 exfer->ex_sqtds[j++] = cur; 2838 2839 cur->xfer = xfer; 2840 cur->len = 0; 2841 2842 } 2843 2844 *sp = exfer->ex_sqtds[0]; 2845 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2846 2847 return 0; 2848 2849 nomem: 2850 ehci_free_sqtds(sc, exfer); 2851 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2852 DPRINTF("no memory", 0, 0, 0, 0); 2853 return ENOMEM; 2854 } 2855 2856 Static void 2857 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2858 { 2859 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2860 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2861 2862 mutex_enter(&sc->sc_lock); 2863 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2864 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2865 2866 if (sqtd == NULL) 2867 break; 2868 2869 sqtd->nextqtd = sc->sc_freeqtds; 2870 sc->sc_freeqtds = sqtd; 2871 } 2872 mutex_exit(&sc->sc_lock); 2873 } 2874 2875 Static void 2876 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2877 { 2878 if (prev) { 2879 prev->nextqtd = sqtd; 2880 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2881 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2882 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2883 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2884 } 2885 } 2886 2887 Static void 2888 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2889 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2890 { 2891 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2892 usb_dma_t *dma = &xfer->ux_dmabuf; 2893 uint16_t flags = xfer->ux_flags; 2894 ehci_soft_qtd_t *sqtd, *prev; 2895 int tog = *toggle; 2896 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2897 int len = length; 2898 2899 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2900 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2901 len, isread, tog); 2902 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2903 0, 0, 0); 2904 2905 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2906 2907 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2908 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2909 EHCI_QTD_SET_CERR(3) 2910 ; 2911 2912 sqtd = prev = NULL; 2913 size_t curoffs = 0; 2914 size_t j = 0; 2915 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2916 sqtd = exfer->ex_sqtds[j++]; 2917 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 2918 (uintptr_t)prev, 0); 2919 2920 /* 2921 * The EHCI hardware can handle at most 5 pages and they do 2922 * not have to be contiguous 2923 */ 2924 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2925 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2926 size_t curlen = len; 2927 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2928 /* must use multiple TDs, fill as much as possible. */ 2929 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2930 2931 /* the length must be a multiple of the max size */ 2932 curlen -= curlen % mps; 2933 } 2934 KASSERT(curlen != 0); 2935 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 2936 curoffs, 0); 2937 2938 /* Fill the qTD */ 2939 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2940 sqtd->qtd.qtd_status = htole32( 2941 qtdstatus | 2942 EHCI_QTD_SET_BYTES(curlen) | 2943 EHCI_QTD_SET_TOGGLE(tog)); 2944 2945 /* Find number of pages we'll be using, insert dma addresses */ 2946 size_t pages = EHCI_NPAGES(curlen); 2947 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2948 size_t pageoffs = EHCI_PAGE(curoffs); 2949 for (size_t i = 0; i < pages; i++) { 2950 paddr_t a = DMAADDR(dma, 2951 pageoffs + i * EHCI_PAGE_SIZE); 2952 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2953 /* Cast up to avoid compiler warnings */ 2954 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2955 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 2956 i, pages, 2957 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2958 le32toh(sqtd->qtd.qtd_buffer[i])); 2959 } 2960 /* First buffer pointer requires a page offset to start at */ 2961 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2962 2963 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2964 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2965 2966 sqtd->len = curlen; 2967 2968 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 2969 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2970 2971 ehci_append_sqtd(sqtd, prev); 2972 2973 if (((curlen + mps - 1) / mps) & 1) { 2974 tog ^= 1; 2975 } 2976 2977 curoffs += curlen; 2978 len -= curlen; 2979 } 2980 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2981 xfer, length, len, mps, exfer->ex_nsqtd, j); 2982 2983 if (!isread && 2984 (flags & USBD_FORCE_SHORT_XFER) && 2985 length % mps == 0) { 2986 /* Force a 0 length transfer at the end. */ 2987 2988 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2989 exfer->ex_nsqtd); 2990 prev = sqtd; 2991 sqtd = exfer->ex_sqtds[j++]; 2992 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 2993 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2994 sqtd->qtd.qtd_status = htole32( 2995 qtdstatus | 2996 EHCI_QTD_SET_BYTES(0) | 2997 EHCI_QTD_SET_TOGGLE(tog)); 2998 2999 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3000 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3001 3002 ehci_append_sqtd(sqtd, prev); 3003 tog ^= 1; 3004 } 3005 3006 *lsqtd = sqtd; 3007 *toggle = tog; 3008 } 3009 3010 Static ehci_soft_itd_t * 3011 ehci_alloc_itd(ehci_softc_t *sc) 3012 { 3013 struct ehci_soft_itd *itd, *freeitd; 3014 usbd_status err; 3015 usb_dma_t dma; 3016 3017 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3018 3019 mutex_enter(&sc->sc_lock); 3020 3021 freeitd = LIST_FIRST(&sc->sc_freeitds); 3022 if (freeitd == NULL) { 3023 DPRINTF("allocating chunk", 0, 0, 0, 0); 3024 mutex_exit(&sc->sc_lock); 3025 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3026 EHCI_PAGE_SIZE, &dma); 3027 3028 if (err) { 3029 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3030 return NULL; 3031 } 3032 mutex_enter(&sc->sc_lock); 3033 3034 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3035 int offs = i * EHCI_ITD_SIZE; 3036 itd = KERNADDR(&dma, offs); 3037 itd->physaddr = DMAADDR(&dma, offs); 3038 itd->dma = dma; 3039 itd->offs = offs; 3040 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3041 } 3042 freeitd = LIST_FIRST(&sc->sc_freeitds); 3043 } 3044 3045 itd = freeitd; 3046 LIST_REMOVE(itd, free_list); 3047 mutex_exit(&sc->sc_lock); 3048 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3049 3050 itd->frame_list.next = NULL; 3051 itd->frame_list.prev = NULL; 3052 itd->xfer_next = NULL; 3053 itd->slot = 0; 3054 3055 return itd; 3056 } 3057 3058 Static ehci_soft_sitd_t * 3059 ehci_alloc_sitd(ehci_softc_t *sc) 3060 { 3061 struct ehci_soft_sitd *sitd, *freesitd; 3062 usbd_status err; 3063 int i, offs; 3064 usb_dma_t dma; 3065 3066 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3067 3068 mutex_enter(&sc->sc_lock); 3069 freesitd = LIST_FIRST(&sc->sc_freesitds); 3070 if (freesitd == NULL) { 3071 DPRINTF("allocating chunk", 0, 0, 0, 0); 3072 mutex_exit(&sc->sc_lock); 3073 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3074 EHCI_PAGE_SIZE, &dma); 3075 3076 if (err) { 3077 DPRINTF("alloc returned %jd", err, 0, 0, 3078 0); 3079 return NULL; 3080 } 3081 3082 mutex_enter(&sc->sc_lock); 3083 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3084 offs = i * EHCI_SITD_SIZE; 3085 sitd = KERNADDR(&dma, offs); 3086 sitd->physaddr = DMAADDR(&dma, offs); 3087 sitd->dma = dma; 3088 sitd->offs = offs; 3089 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3090 } 3091 freesitd = LIST_FIRST(&sc->sc_freesitds); 3092 } 3093 3094 sitd = freesitd; 3095 LIST_REMOVE(sitd, free_list); 3096 mutex_exit(&sc->sc_lock); 3097 3098 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3099 3100 sitd->frame_list.next = NULL; 3101 sitd->frame_list.prev = NULL; 3102 sitd->xfer_next = NULL; 3103 sitd->slot = 0; 3104 3105 return sitd; 3106 } 3107 3108 /****************/ 3109 3110 /* 3111 * Close a reqular pipe. 3112 * Assumes that there are no pending transactions. 3113 */ 3114 Static void 3115 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3116 { 3117 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3118 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3119 ehci_soft_qh_t *sqh = epipe->sqh; 3120 3121 KASSERT(mutex_owned(&sc->sc_lock)); 3122 3123 ehci_rem_qh(sc, sqh, head); 3124 ehci_free_sqh(sc, epipe->sqh); 3125 } 3126 3127 /* 3128 * Cancel or timeout a device request. We have two cases to deal with 3129 * 3130 * 1) A driver wants to stop scheduled or inflight transfers 3131 * 2) A transfer has timed out 3132 * 3133 * have (partially) happened since the hardware runs concurrently. 3134 * 3135 * Transfer state is protected by the bus lock and we set the transfer status 3136 * as soon as either of the above happens (with bus lock held). 3137 * 3138 * Then we arrange for the hardware to tells us that it is not still 3139 * processing the TDs by setting the QH halted bit and wait for the ehci 3140 * door bell 3141 */ 3142 Static void 3143 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3144 { 3145 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3146 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3147 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3148 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3149 ehci_soft_qh_t *sqh = epipe->sqh; 3150 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3151 ehci_physaddr_t cur; 3152 uint32_t qhstatus; 3153 int hit; 3154 3155 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 3156 "invalid status for abort: %d", (int)status); 3157 3158 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3159 3160 KASSERT(mutex_owned(&sc->sc_lock)); 3161 ASSERT_SLEEPABLE(); 3162 3163 if (status == USBD_CANCELLED) { 3164 /* 3165 * We are synchronously aborting. Try to stop the 3166 * callout and task, but if we can't, wait for them to 3167 * complete. 3168 */ 3169 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3170 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 3171 USB_TASKQ_HC, &sc->sc_lock); 3172 } else { 3173 /* Otherwise, we are timing out. */ 3174 KASSERT(status == USBD_TIMEOUT); 3175 } 3176 3177 /* 3178 * The xfer cannot have been cancelled already. It is the 3179 * responsibility of the caller of usbd_abort_pipe not to try 3180 * to abort a pipe multiple times, whether concurrently or 3181 * sequentially. 3182 */ 3183 KASSERT(xfer->ux_status != USBD_CANCELLED); 3184 3185 /* Only the timeout, which runs only once, can time it out. */ 3186 KASSERT(xfer->ux_status != USBD_TIMEOUT); 3187 3188 /* If anyone else beat us, we're done. */ 3189 if (xfer->ux_status != USBD_IN_PROGRESS) 3190 return; 3191 3192 /* We beat everyone else. Claim the status. */ 3193 xfer->ux_status = status; 3194 3195 /* 3196 * If we're dying, skip the hardware action and just notify the 3197 * software that we're done. 3198 */ 3199 if (sc->sc_dying) { 3200 goto dying; 3201 } 3202 3203 /* 3204 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3205 */ 3206 ehci_del_intr_list(sc, exfer); 3207 3208 usb_syncmem(&sqh->dma, 3209 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3210 sizeof(sqh->qh.qh_qtd.qtd_status), 3211 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3212 qhstatus = sqh->qh.qh_qtd.qtd_status; 3213 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3214 usb_syncmem(&sqh->dma, 3215 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3216 sizeof(sqh->qh.qh_qtd.qtd_status), 3217 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3218 3219 if (exfer->ex_type == EX_CTRL) { 3220 fsqtd = exfer->ex_setup; 3221 lsqtd = exfer->ex_status; 3222 } else { 3223 fsqtd = exfer->ex_sqtdstart; 3224 lsqtd = exfer->ex_sqtdend; 3225 } 3226 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3227 usb_syncmem(&sqtd->dma, 3228 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3229 sizeof(sqtd->qtd.qtd_status), 3230 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3231 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3232 usb_syncmem(&sqtd->dma, 3233 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3234 sizeof(sqtd->qtd.qtd_status), 3235 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3236 if (sqtd == lsqtd) 3237 break; 3238 } 3239 3240 /* 3241 * HC Step 2: Wait until we know hardware has finished any possible 3242 * use of the xfer. 3243 */ 3244 ehci_sync_hc(sc); 3245 3246 /* 3247 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3248 * The complication here is that the hardware may have executed 3249 * beyond the xfer we're trying to abort. So as we're scanning 3250 * the TDs of this xfer we check if the hardware points to 3251 * any of them. 3252 */ 3253 3254 usb_syncmem(&sqh->dma, 3255 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3256 sizeof(sqh->qh.qh_curqtd), 3257 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3258 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3259 hit = 0; 3260 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3261 hit |= cur == sqtd->physaddr; 3262 if (sqtd == lsqtd) 3263 break; 3264 } 3265 sqtd = sqtd->nextqtd; 3266 /* Zap curqtd register if hardware pointed inside the xfer. */ 3267 if (hit && sqtd != NULL) { 3268 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3269 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3270 usb_syncmem(&sqh->dma, 3271 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3272 sizeof(sqh->qh.qh_curqtd), 3273 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3274 sqh->qh.qh_qtd.qtd_status = qhstatus; 3275 usb_syncmem(&sqh->dma, 3276 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3277 sizeof(sqh->qh.qh_qtd.qtd_status), 3278 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3279 } else { 3280 DPRINTF("no hit", 0, 0, 0, 0); 3281 usb_syncmem(&sqh->dma, 3282 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3283 sizeof(sqh->qh.qh_curqtd), 3284 BUS_DMASYNC_PREREAD); 3285 } 3286 3287 /* 3288 * Final step: Notify completion to waiting xfers. 3289 */ 3290 dying: 3291 #ifdef DIAGNOSTIC 3292 exfer->ex_isdone = true; 3293 #endif 3294 usb_transfer_complete(xfer); 3295 DPRINTFN(14, "end", 0, 0, 0, 0); 3296 3297 KASSERT(mutex_owned(&sc->sc_lock)); 3298 } 3299 3300 Static void 3301 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3302 { 3303 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3304 ehci_isoc_trans_t trans_status; 3305 struct ehci_xfer *exfer; 3306 ehci_softc_t *sc; 3307 struct ehci_soft_itd *itd; 3308 struct ehci_soft_sitd *sitd; 3309 int i; 3310 3311 KASSERTMSG(status == USBD_CANCELLED, 3312 "invalid status for abort: %d", (int)status); 3313 3314 exfer = EHCI_XFER2EXFER(xfer); 3315 sc = EHCI_XFER2SC(xfer); 3316 3317 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3318 (uintptr_t)xfer->ux_pipe, 0, 0); 3319 3320 KASSERT(mutex_owned(&sc->sc_lock)); 3321 ASSERT_SLEEPABLE(); 3322 3323 /* No timeout or task here. */ 3324 3325 /* 3326 * The xfer cannot have been cancelled already. It is the 3327 * responsibility of the caller of usbd_abort_pipe not to try 3328 * to abort a pipe multiple times, whether concurrently or 3329 * sequentially. 3330 */ 3331 KASSERT(xfer->ux_status != USBD_CANCELLED); 3332 3333 /* If anyone else beat us, we're done. */ 3334 if (xfer->ux_status != USBD_IN_PROGRESS) 3335 return; 3336 3337 /* We beat everyone else. Claim the status. */ 3338 xfer->ux_status = status; 3339 3340 /* 3341 * If we're dying, skip the hardware action and just notify the 3342 * software that we're done. 3343 */ 3344 if (sc->sc_dying) { 3345 goto dying; 3346 } 3347 3348 /* 3349 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3350 */ 3351 ehci_del_intr_list(sc, exfer); 3352 3353 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3354 for (itd = exfer->ex_itdstart; itd != NULL; 3355 itd = itd->xfer_next) { 3356 usb_syncmem(&itd->dma, 3357 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3358 sizeof(itd->itd.itd_ctl), 3359 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3360 3361 for (i = 0; i < 8; i++) { 3362 trans_status = le32toh(itd->itd.itd_ctl[i]); 3363 trans_status &= ~EHCI_ITD_ACTIVE; 3364 itd->itd.itd_ctl[i] = htole32(trans_status); 3365 } 3366 3367 usb_syncmem(&itd->dma, 3368 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3369 sizeof(itd->itd.itd_ctl), 3370 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3371 } 3372 } else { 3373 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3374 sitd = sitd->xfer_next) { 3375 usb_syncmem(&sitd->dma, 3376 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3377 sizeof(sitd->sitd.sitd_buffer), 3378 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3379 3380 trans_status = le32toh(sitd->sitd.sitd_trans); 3381 trans_status &= ~EHCI_SITD_ACTIVE; 3382 sitd->sitd.sitd_trans = htole32(trans_status); 3383 3384 usb_syncmem(&sitd->dma, 3385 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3386 sizeof(sitd->sitd.sitd_buffer), 3387 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3388 } 3389 } 3390 3391 dying: 3392 #ifdef DIAGNOSTIC 3393 exfer->ex_isdone = true; 3394 #endif 3395 usb_transfer_complete(xfer); 3396 DPRINTFN(14, "end", 0, 0, 0, 0); 3397 3398 KASSERT(mutex_owned(&sc->sc_lock)); 3399 } 3400 3401 Static void 3402 ehci_timeout(void *addr) 3403 { 3404 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3405 struct usbd_xfer *xfer = addr; 3406 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3407 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3408 3409 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3410 #ifdef EHCI_DEBUG 3411 if (ehcidebug >= 2) { 3412 struct usbd_pipe *pipe = xfer->ux_pipe; 3413 usbd_dump_pipe(pipe); 3414 } 3415 #endif 3416 3417 mutex_enter(&sc->sc_lock); 3418 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 3419 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3420 mutex_exit(&sc->sc_lock); 3421 } 3422 3423 Static void 3424 ehci_timeout_task(void *addr) 3425 { 3426 struct usbd_xfer *xfer = addr; 3427 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3428 3429 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3430 3431 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3432 3433 mutex_enter(&sc->sc_lock); 3434 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3435 mutex_exit(&sc->sc_lock); 3436 } 3437 3438 /************************/ 3439 3440 Static int 3441 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3442 { 3443 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3444 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3445 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3446 usb_device_request_t *req = &xfer->ux_request; 3447 ehci_soft_qtd_t *setup, *status, *next; 3448 int isread = req->bmRequestType & UT_READ; 3449 int len = xfer->ux_bufsize; 3450 int err; 3451 3452 exfer->ex_type = EX_CTRL; 3453 exfer->ex_status = NULL; 3454 exfer->ex_data = NULL; 3455 exfer->ex_setup = ehci_alloc_sqtd(sc); 3456 if (exfer->ex_setup == NULL) { 3457 err = ENOMEM; 3458 goto bad1; 3459 } 3460 exfer->ex_status = ehci_alloc_sqtd(sc); 3461 if (exfer->ex_status == NULL) { 3462 err = ENOMEM; 3463 goto bad2; 3464 } 3465 setup = exfer->ex_setup; 3466 status = exfer->ex_status; 3467 exfer->ex_nsqtd = 0; 3468 next = status; 3469 /* Set up data transaction */ 3470 if (len != 0) { 3471 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3472 &exfer->ex_data); 3473 if (err) 3474 goto bad3; 3475 next = exfer->ex_data; 3476 } 3477 3478 /* Clear toggle */ 3479 setup->qtd.qtd_status = htole32( 3480 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3481 EHCI_QTD_SET_TOGGLE(0) | 3482 EHCI_QTD_SET_BYTES(sizeof(*req)) 3483 ); 3484 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3485 setup->qtd.qtd_buffer_hi[0] = 0; 3486 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3487 setup->nextqtd = next; 3488 setup->xfer = xfer; 3489 setup->len = sizeof(*req); 3490 3491 status->qtd.qtd_status = htole32( 3492 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3493 EHCI_QTD_SET_TOGGLE(1) | 3494 EHCI_QTD_IOC 3495 ); 3496 status->qtd.qtd_buffer[0] = 0; 3497 status->qtd.qtd_buffer_hi[0] = 0; 3498 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3499 status->nextqtd = NULL; 3500 status->xfer = xfer; 3501 status->len = 0; 3502 3503 return 0; 3504 bad3: 3505 ehci_free_sqtd(sc, exfer->ex_status); 3506 bad2: 3507 ehci_free_sqtd(sc, exfer->ex_setup); 3508 bad1: 3509 return err; 3510 } 3511 3512 Static void 3513 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3514 { 3515 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3516 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3517 3518 KASSERT(ex->ex_type == EX_CTRL); 3519 3520 ehci_free_sqtd(sc, ex->ex_setup); 3521 ehci_free_sqtd(sc, ex->ex_status); 3522 ehci_free_sqtds(sc, ex); 3523 if (ex->ex_nsqtd) 3524 kmem_free(ex->ex_sqtds, 3525 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3526 } 3527 3528 Static usbd_status 3529 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3530 { 3531 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3532 usbd_status err; 3533 3534 /* Insert last in queue. */ 3535 mutex_enter(&sc->sc_lock); 3536 err = usb_insert_transfer(xfer); 3537 mutex_exit(&sc->sc_lock); 3538 if (err) 3539 return err; 3540 3541 /* Pipe isn't running, start first */ 3542 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3543 } 3544 3545 Static usbd_status 3546 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3547 { 3548 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3549 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3550 usb_device_request_t *req = &xfer->ux_request; 3551 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3552 ehci_soft_qtd_t *setup, *status, *next; 3553 ehci_soft_qh_t *sqh; 3554 3555 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3556 3557 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3558 3559 if (sc->sc_dying) 3560 return USBD_IOERROR; 3561 3562 const int isread = req->bmRequestType & UT_READ; 3563 const int len = UGETW(req->wLength); 3564 3565 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3566 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3567 UGETW(req->wIndex)); 3568 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3569 len, epipe->pipe.up_dev->ud_addr, 3570 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3571 3572 sqh = epipe->sqh; 3573 3574 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3575 "address QH %" __PRIuBIT " pipe %d\n", 3576 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3577 epipe->pipe.up_dev->ud_addr); 3578 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3579 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3580 "MPS QH %" __PRIuBIT " pipe %d\n", 3581 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3582 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3583 3584 setup = exfer->ex_setup; 3585 status = exfer->ex_status; 3586 3587 DPRINTF("setup %#jx status %#jx data %#jx", 3588 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3589 KASSERTMSG(setup != NULL && status != NULL, 3590 "Failed memory allocation, setup %p status %p", 3591 setup, status); 3592 3593 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3594 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3595 3596 /* Clear toggle */ 3597 setup->qtd.qtd_status &= ~htole32( 3598 EHCI_QTD_STATUS_MASK | 3599 EHCI_QTD_BYTES_MASK | 3600 EHCI_QTD_TOGGLE_MASK | 3601 EHCI_QTD_CERR_MASK 3602 ); 3603 setup->qtd.qtd_status |= htole32( 3604 EHCI_QTD_ACTIVE | 3605 EHCI_QTD_SET_CERR(3) | 3606 EHCI_QTD_SET_TOGGLE(0) | 3607 EHCI_QTD_SET_BYTES(sizeof(*req)) 3608 ); 3609 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3610 setup->qtd.qtd_buffer_hi[0] = 0; 3611 3612 next = status; 3613 status->qtd.qtd_status &= ~htole32( 3614 EHCI_QTD_STATUS_MASK | 3615 EHCI_QTD_PID_MASK | 3616 EHCI_QTD_BYTES_MASK | 3617 EHCI_QTD_TOGGLE_MASK | 3618 EHCI_QTD_CERR_MASK 3619 ); 3620 status->qtd.qtd_status |= htole32( 3621 EHCI_QTD_ACTIVE | 3622 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3623 EHCI_QTD_SET_CERR(3) | 3624 EHCI_QTD_SET_TOGGLE(1) | 3625 EHCI_QTD_SET_BYTES(0) | 3626 EHCI_QTD_IOC 3627 ); 3628 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3629 3630 KASSERT(exfer->ex_isdone); 3631 #ifdef DIAGNOSTIC 3632 exfer->ex_isdone = false; 3633 #endif 3634 3635 /* Set up data transaction */ 3636 if (len != 0) { 3637 ehci_soft_qtd_t *end; 3638 3639 /* Start toggle at 1. */ 3640 int toggle = 1; 3641 next = exfer->ex_data; 3642 KASSERTMSG(next != NULL, "Failed memory allocation"); 3643 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3644 end->nextqtd = status; 3645 end->qtd.qtd_next = end->qtd.qtd_altnext = 3646 htole32(status->physaddr); 3647 3648 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3649 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3650 3651 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3652 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3653 } 3654 3655 setup->nextqtd = next; 3656 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3657 3658 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3659 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3660 3661 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3662 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3663 3664 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3665 3666 #ifdef EHCI_DEBUG 3667 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3668 ehci_dump_sqh(sqh); 3669 ehci_dump_sqtds(setup); 3670 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3671 #endif 3672 3673 mutex_enter(&sc->sc_lock); 3674 3675 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3676 ehci_set_qh_qtd(sqh, setup); 3677 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3678 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3679 ehci_timeout, xfer); 3680 } 3681 ehci_add_intr_list(sc, exfer); 3682 xfer->ux_status = USBD_IN_PROGRESS; 3683 mutex_exit(&sc->sc_lock); 3684 3685 #if 0 3686 #ifdef EHCI_DEBUG 3687 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3688 // delay(10000); 3689 ehci_dump_regs(sc); 3690 ehci_dump_sqh(sc->sc_async_head); 3691 ehci_dump_sqh(sqh); 3692 ehci_dump_sqtds(setup); 3693 #endif 3694 #endif 3695 3696 return USBD_IN_PROGRESS; 3697 } 3698 3699 Static void 3700 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3701 { 3702 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3703 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3704 usb_device_request_t *req = &xfer->ux_request; 3705 int len = UGETW(req->wLength); 3706 int rd = req->bmRequestType & UT_READ; 3707 3708 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3709 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3710 3711 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3712 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3713 3714 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3715 BUS_DMASYNC_POSTWRITE); 3716 if (len) 3717 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3718 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3719 3720 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3721 } 3722 3723 /* Abort a device control request. */ 3724 Static void 3725 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3726 { 3727 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3728 3729 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3730 ehci_abort_xfer(xfer, USBD_CANCELLED); 3731 } 3732 3733 /* Close a device control pipe. */ 3734 Static void 3735 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3736 { 3737 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3738 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3739 3740 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3741 3742 KASSERT(mutex_owned(&sc->sc_lock)); 3743 3744 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3745 3746 ehci_close_pipe(pipe, sc->sc_async_head); 3747 } 3748 3749 /* 3750 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3751 * qTD status, or miss signalling occasionally under heavy load. If the host 3752 * machine is too fast, we we can miss transaction completion - when we scan 3753 * the active list the transaction still seems to be active. This generally 3754 * exhibits itself as a umass stall that never recovers. 3755 * 3756 * We work around this behaviour by setting up this callback after any softintr 3757 * that completes with transactions still pending, giving us another chance to 3758 * check for completion after the writeback has taken place. 3759 */ 3760 Static void 3761 ehci_intrlist_timeout(void *arg) 3762 { 3763 ehci_softc_t *sc = arg; 3764 3765 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3766 3767 usb_schedsoftintr(&sc->sc_bus); 3768 } 3769 3770 /************************/ 3771 3772 Static int 3773 ehci_device_bulk_init(struct usbd_xfer *xfer) 3774 { 3775 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3776 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3777 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3778 int endpt = ed->bEndpointAddress; 3779 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3780 int len = xfer->ux_bufsize; 3781 int err = 0; 3782 3783 exfer->ex_type = EX_BULK; 3784 exfer->ex_nsqtd = 0; 3785 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3786 &exfer->ex_sqtdstart); 3787 3788 return err; 3789 } 3790 3791 Static void 3792 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3793 { 3794 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3795 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3796 3797 KASSERT(ex->ex_type == EX_BULK); 3798 3799 ehci_free_sqtds(sc, ex); 3800 if (ex->ex_nsqtd) 3801 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3802 } 3803 3804 Static usbd_status 3805 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3806 { 3807 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3808 usbd_status err; 3809 3810 /* Insert last in queue. */ 3811 mutex_enter(&sc->sc_lock); 3812 err = usb_insert_transfer(xfer); 3813 mutex_exit(&sc->sc_lock); 3814 if (err) 3815 return err; 3816 3817 /* Pipe isn't running, start first */ 3818 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3819 } 3820 3821 Static usbd_status 3822 ehci_device_bulk_start(struct usbd_xfer *xfer) 3823 { 3824 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3825 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3826 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3827 ehci_soft_qh_t *sqh; 3828 ehci_soft_qtd_t *end; 3829 int len, isread, endpt; 3830 3831 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3832 3833 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3834 xfer->ux_flags, 0); 3835 3836 if (sc->sc_dying) 3837 return USBD_IOERROR; 3838 3839 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3840 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3841 3842 len = xfer->ux_length; 3843 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3844 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3845 sqh = epipe->sqh; 3846 3847 KASSERT(exfer->ex_isdone); 3848 #ifdef DIAGNOSTIC 3849 exfer->ex_isdone = false; 3850 #endif 3851 3852 /* Take lock here to protect nexttoggle */ 3853 mutex_enter(&sc->sc_lock); 3854 3855 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3856 3857 exfer->ex_sqtdend = end; 3858 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3859 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3860 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3861 3862 #ifdef EHCI_DEBUG 3863 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3864 ehci_dump_sqh(sqh); 3865 ehci_dump_sqtds(exfer->ex_sqtdstart); 3866 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3867 #endif 3868 3869 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3870 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3871 3872 /* also does usb_syncmem(sqh) */ 3873 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3874 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3875 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3876 ehci_timeout, xfer); 3877 } 3878 ehci_add_intr_list(sc, exfer); 3879 xfer->ux_status = USBD_IN_PROGRESS; 3880 mutex_exit(&sc->sc_lock); 3881 3882 #if 0 3883 #ifdef EHCI_DEBUG 3884 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3885 // delay(10000); 3886 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3887 ehci_dump_regs(sc); 3888 #if 0 3889 printf("async_head:\n"); 3890 ehci_dump_sqh(sc->sc_async_head); 3891 #endif 3892 DPRINTF("sqh:", 0, 0, 0, 0); 3893 ehci_dump_sqh(sqh); 3894 ehci_dump_sqtds(exfer->ex_sqtdstart); 3895 #endif 3896 #endif 3897 3898 return USBD_IN_PROGRESS; 3899 } 3900 3901 Static void 3902 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3903 { 3904 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3905 3906 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3907 ehci_abort_xfer(xfer, USBD_CANCELLED); 3908 } 3909 3910 /* 3911 * Close a device bulk pipe. 3912 */ 3913 Static void 3914 ehci_device_bulk_close(struct usbd_pipe *pipe) 3915 { 3916 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3917 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3918 3919 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3920 3921 KASSERT(mutex_owned(&sc->sc_lock)); 3922 3923 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3924 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3925 ehci_close_pipe(pipe, sc->sc_async_head); 3926 } 3927 3928 Static void 3929 ehci_device_bulk_done(struct usbd_xfer *xfer) 3930 { 3931 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3932 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3933 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3934 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3935 3936 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3937 3938 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 3939 3940 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3941 3942 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3943 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3944 3945 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3946 } 3947 3948 /************************/ 3949 3950 Static usbd_status 3951 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3952 { 3953 struct ehci_soft_islot *isp; 3954 int islot, lev; 3955 3956 /* Find a poll rate that is large enough. */ 3957 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3958 if (EHCI_ILEV_IVAL(lev) <= ival) 3959 break; 3960 3961 /* Pick an interrupt slot at the right level. */ 3962 /* XXX could do better than picking at random */ 3963 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3964 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3965 3966 sqh->islot = islot; 3967 isp = &sc->sc_islots[islot]; 3968 mutex_enter(&sc->sc_lock); 3969 ehci_add_qh(sc, sqh, isp->sqh); 3970 mutex_exit(&sc->sc_lock); 3971 3972 return USBD_NORMAL_COMPLETION; 3973 } 3974 3975 3976 Static int 3977 ehci_device_intr_init(struct usbd_xfer *xfer) 3978 { 3979 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3980 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3981 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3982 int endpt = ed->bEndpointAddress; 3983 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3984 int len = xfer->ux_bufsize; 3985 int err; 3986 3987 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3988 3989 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3990 xfer->ux_flags, 0); 3991 3992 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3993 KASSERT(len != 0); 3994 3995 exfer->ex_type = EX_INTR; 3996 exfer->ex_nsqtd = 0; 3997 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3998 &exfer->ex_sqtdstart); 3999 4000 return err; 4001 } 4002 4003 Static void 4004 ehci_device_intr_fini(struct usbd_xfer *xfer) 4005 { 4006 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4007 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4008 4009 KASSERT(ex->ex_type == EX_INTR); 4010 4011 ehci_free_sqtds(sc, ex); 4012 if (ex->ex_nsqtd) 4013 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4014 } 4015 4016 Static usbd_status 4017 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4018 { 4019 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4020 usbd_status err; 4021 4022 /* Insert last in queue. */ 4023 mutex_enter(&sc->sc_lock); 4024 err = usb_insert_transfer(xfer); 4025 mutex_exit(&sc->sc_lock); 4026 if (err) 4027 return err; 4028 4029 /* 4030 * Pipe isn't running (otherwise err would be USBD_INPROG), 4031 * so start it first. 4032 */ 4033 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4034 } 4035 4036 Static usbd_status 4037 ehci_device_intr_start(struct usbd_xfer *xfer) 4038 { 4039 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4040 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4041 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4042 ehci_soft_qtd_t *end; 4043 ehci_soft_qh_t *sqh; 4044 int len, isread, endpt; 4045 4046 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4047 4048 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4049 xfer->ux_flags, 0); 4050 4051 if (sc->sc_dying) 4052 return USBD_IOERROR; 4053 4054 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4055 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4056 4057 len = xfer->ux_length; 4058 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4059 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4060 sqh = epipe->sqh; 4061 4062 KASSERT(exfer->ex_isdone); 4063 #ifdef DIAGNOSTIC 4064 exfer->ex_isdone = false; 4065 #endif 4066 4067 /* Take lock to protect nexttoggle */ 4068 mutex_enter(&sc->sc_lock); 4069 4070 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4071 4072 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4073 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4074 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4075 exfer->ex_sqtdend = end; 4076 4077 #ifdef EHCI_DEBUG 4078 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4079 ehci_dump_sqh(sqh); 4080 ehci_dump_sqtds(exfer->ex_sqtdstart); 4081 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4082 #endif 4083 4084 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4085 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4086 4087 /* also does usb_syncmem(sqh) */ 4088 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4089 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4090 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4091 ehci_timeout, xfer); 4092 } 4093 ehci_add_intr_list(sc, exfer); 4094 xfer->ux_status = USBD_IN_PROGRESS; 4095 mutex_exit(&sc->sc_lock); 4096 4097 #if 0 4098 #ifdef EHCI_DEBUG 4099 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4100 // delay(10000); 4101 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4102 ehci_dump_regs(sc); 4103 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4104 ehci_dump_sqh(sqh); 4105 ehci_dump_sqtds(exfer->ex_sqtdstart); 4106 #endif 4107 #endif 4108 4109 return USBD_IN_PROGRESS; 4110 } 4111 4112 Static void 4113 ehci_device_intr_abort(struct usbd_xfer *xfer) 4114 { 4115 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4116 4117 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4118 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4119 4120 /* 4121 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4122 * async doorbell. That's dependent on the async list, wheras 4123 * intr xfers are periodic, should not use this? 4124 */ 4125 ehci_abort_xfer(xfer, USBD_CANCELLED); 4126 } 4127 4128 Static void 4129 ehci_device_intr_close(struct usbd_pipe *pipe) 4130 { 4131 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4132 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4133 struct ehci_soft_islot *isp; 4134 4135 KASSERT(mutex_owned(&sc->sc_lock)); 4136 4137 isp = &sc->sc_islots[epipe->sqh->islot]; 4138 ehci_close_pipe(pipe, isp->sqh); 4139 } 4140 4141 Static void 4142 ehci_device_intr_done(struct usbd_xfer *xfer) 4143 { 4144 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4145 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4146 int isread, endpt; 4147 4148 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4149 4150 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4151 4152 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4153 4154 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4155 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4156 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4157 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4158 } 4159 4160 /************************/ 4161 Static int 4162 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4163 { 4164 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4165 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4166 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4167 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4168 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4169 int i, k, frames; 4170 u_int huba, dir; 4171 int err; 4172 4173 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4174 4175 start = NULL; 4176 sitd = NULL; 4177 4178 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4179 xfer->ux_flags, 0); 4180 4181 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4182 KASSERT(xfer->ux_nframes != 0); 4183 KASSERT(exfer->ex_isdone); 4184 4185 exfer->ex_type = EX_FS_ISOC; 4186 /* 4187 * Step 1: Allocate and initialize sitds. 4188 */ 4189 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4190 if (i > 16 || i == 0) { 4191 /* Spec page 271 says intervals > 16 are invalid */ 4192 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4193 4194 return EINVAL; 4195 } 4196 4197 frames = xfer->ux_nframes; 4198 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4199 sitd = ehci_alloc_sitd(sc); 4200 if (sitd == NULL) { 4201 err = ENOMEM; 4202 goto fail; 4203 } 4204 4205 if (prev) 4206 prev->xfer_next = sitd; 4207 else 4208 start = sitd; 4209 4210 huba = dev->ud_myhsport->up_parent->ud_addr; 4211 4212 #if 0 4213 if (sc->sc_flags & EHCIF_FREESCALE) { 4214 // Set hub address to 0 if embedded TT is used. 4215 if (huba == sc->sc_addr) 4216 huba = 0; 4217 } 4218 #endif 4219 4220 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4221 dir = UE_GET_DIR(k) ? 1 : 0; 4222 sitd->sitd.sitd_endp = 4223 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4224 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4225 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4226 EHCI_SITD_SET_HUBA(huba) | 4227 EHCI_SITD_SET_DIR(dir)); 4228 4229 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4230 } /* End of frame */ 4231 4232 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4233 4234 stop = sitd; 4235 stop->xfer_next = NULL; 4236 exfer->ex_sitdstart = start; 4237 exfer->ex_sitdend = stop; 4238 4239 return 0; 4240 4241 fail: 4242 mutex_enter(&sc->sc_lock); 4243 ehci_soft_sitd_t *next; 4244 for (sitd = start; sitd; sitd = next) { 4245 next = sitd->xfer_next; 4246 ehci_free_sitd_locked(sc, sitd); 4247 } 4248 mutex_exit(&sc->sc_lock); 4249 4250 return err; 4251 } 4252 4253 Static void 4254 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4255 { 4256 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4257 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4258 4259 KASSERT(ex->ex_type == EX_FS_ISOC); 4260 4261 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4262 } 4263 4264 Static usbd_status 4265 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4266 { 4267 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4268 usbd_status __diagused err; 4269 4270 mutex_enter(&sc->sc_lock); 4271 err = usb_insert_transfer(xfer); 4272 mutex_exit(&sc->sc_lock); 4273 4274 KASSERT(err == USBD_NORMAL_COMPLETION); 4275 4276 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4277 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4278 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4279 ehci_soft_sitd_t *sitd; 4280 usb_dma_t *dma_buf; 4281 int i, j, k, frames; 4282 int offs, total_length; 4283 int frindex; 4284 u_int dir; 4285 4286 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4287 4288 sitd = NULL; 4289 total_length = 0; 4290 4291 4292 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4293 xfer->ux_flags, 0); 4294 4295 if (sc->sc_dying) 4296 return USBD_IOERROR; 4297 4298 /* 4299 * To avoid complication, don't allow a request right now that'll span 4300 * the entire frame table. To within 4 frames, to allow some leeway 4301 * on either side of where the hc currently is. 4302 */ 4303 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4304 xfer->ux_nframes >= sc->sc_flsize - 4) { 4305 printf("ehci: isoc descriptor requested that spans the entire" 4306 "frametable, too many frames\n"); 4307 return USBD_INVAL; 4308 } 4309 4310 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4311 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4312 KASSERT(exfer->ex_isdone); 4313 #ifdef DIAGNOSTIC 4314 exfer->ex_isdone = false; 4315 #endif 4316 4317 /* 4318 * Step 1: Initialize sitds. 4319 */ 4320 4321 frames = xfer->ux_nframes; 4322 dma_buf = &xfer->ux_dmabuf; 4323 offs = 0; 4324 4325 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4326 i++, sitd = sitd->xfer_next) { 4327 KASSERT(sitd != NULL); 4328 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4329 4330 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4331 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4332 4333 /* Set page0 index and offset - TP and T-offset are set below */ 4334 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4335 4336 total_length += xfer->ux_frlengths[i]; 4337 offs += xfer->ux_frlengths[i]; 4338 4339 sitd->sitd.sitd_buffer[1] = 4340 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4341 4342 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4343 4344 #if 0 4345 if (sc->sc_flags & EHCIF_FREESCALE) { 4346 // Set hub address to 0 if embedded TT is used. 4347 if (huba == sc->sc_addr) 4348 huba = 0; 4349 } 4350 #endif 4351 4352 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4353 dir = UE_GET_DIR(k) ? 1 : 0; 4354 KASSERT(sitd->sitd.sitd_endp == htole32( 4355 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4356 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4357 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4358 EHCI_SITD_SET_HUBA(huba) | 4359 EHCI_SITD_SET_DIR(dir))); 4360 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4361 4362 uint8_t sa = 0; 4363 uint8_t sb = 0; 4364 u_int temp, tlen; 4365 4366 if (dir == 0) { /* OUT */ 4367 temp = 0; 4368 tlen = xfer->ux_frlengths[i]; 4369 if (tlen <= 188) { 4370 temp |= 1; /* T-count = 1, TP = ALL */ 4371 tlen = 1; 4372 } else { 4373 tlen += 187; 4374 tlen /= 188; 4375 temp |= tlen; /* T-count = [1..6] */ 4376 temp |= 8; /* TP = Begin */ 4377 } 4378 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4379 4380 tlen += sa; 4381 4382 if (tlen >= 8) { 4383 sb = 0; 4384 } else { 4385 sb = (1 << tlen); 4386 } 4387 4388 sa = (1 << sa); 4389 sa = (sb - sa) & 0x3F; 4390 sb = 0; 4391 } else { 4392 sb = (-(4 << sa)) & 0xFE; 4393 sa = (1 << sa) & 0x3F; 4394 sa = 0x01; 4395 sb = 0xfc; 4396 } 4397 4398 sitd->sitd.sitd_sched = htole32( 4399 EHCI_SITD_SET_SMASK(sa) | 4400 EHCI_SITD_SET_CMASK(sb) 4401 ); 4402 4403 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4404 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4405 } /* End of frame */ 4406 4407 sitd = exfer->ex_sitdend; 4408 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4409 4410 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4411 sizeof(sitd->sitd.sitd_trans), 4412 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4413 4414 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4415 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4416 4417 /* 4418 * Part 2: Transfer descriptors have now been set up, now they must 4419 * be scheduled into the periodic frame list. Erk. Not wanting to 4420 * complicate matters, transfer is denied if the transfer spans 4421 * more than the period frame list. 4422 */ 4423 4424 mutex_enter(&sc->sc_lock); 4425 4426 /* Start inserting frames */ 4427 if (epipe->isoc.cur_xfers > 0) { 4428 frindex = epipe->isoc.next_frame; 4429 } else { 4430 frindex = EOREAD4(sc, EHCI_FRINDEX); 4431 frindex = frindex >> 3; /* Erase microframe index */ 4432 frindex += 2; 4433 } 4434 4435 if (frindex >= sc->sc_flsize) 4436 frindex &= (sc->sc_flsize - 1); 4437 4438 /* Whats the frame interval? */ 4439 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4440 4441 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4442 j++, sitd = sitd->xfer_next) { 4443 KASSERT(sitd); 4444 4445 usb_syncmem(&sc->sc_fldma, 4446 sizeof(ehci_link_t) * frindex, 4447 sizeof(ehci_link_t), 4448 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4449 4450 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4451 if (sitd->sitd.sitd_next == 0) 4452 /* 4453 * FIXME: frindex table gets initialized to NULL 4454 * or EHCI_NULL? 4455 */ 4456 sitd->sitd.sitd_next = EHCI_NULL; 4457 4458 usb_syncmem(&sitd->dma, 4459 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4460 sizeof(ehci_sitd_t), 4461 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4462 4463 sc->sc_flist[frindex] = 4464 htole32(EHCI_LINK_SITD | sitd->physaddr); 4465 4466 usb_syncmem(&sc->sc_fldma, 4467 sizeof(ehci_link_t) * frindex, 4468 sizeof(ehci_link_t), 4469 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4470 4471 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4472 sc->sc_softsitds[frindex] = sitd; 4473 if (sitd->frame_list.next != NULL) 4474 sitd->frame_list.next->frame_list.prev = sitd; 4475 sitd->slot = frindex; 4476 sitd->frame_list.prev = NULL; 4477 4478 frindex += i; 4479 if (frindex >= sc->sc_flsize) 4480 frindex -= sc->sc_flsize; 4481 } 4482 4483 epipe->isoc.cur_xfers++; 4484 epipe->isoc.next_frame = frindex; 4485 4486 ehci_add_intr_list(sc, exfer); 4487 xfer->ux_status = USBD_IN_PROGRESS; 4488 mutex_exit(&sc->sc_lock); 4489 4490 return USBD_IN_PROGRESS; 4491 } 4492 4493 Static void 4494 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4495 { 4496 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4497 4498 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4499 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4500 } 4501 4502 Static void 4503 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4504 { 4505 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4506 4507 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4508 } 4509 4510 Static void 4511 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4512 { 4513 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4514 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4515 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4516 4517 KASSERT(mutex_owned(&sc->sc_lock)); 4518 4519 epipe->isoc.cur_xfers--; 4520 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4521 4522 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4523 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4524 } 4525 4526 4527 /************************/ 4528 4529 4530 Static int 4531 ehci_device_isoc_init(struct usbd_xfer *xfer) 4532 { 4533 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4534 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4535 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4536 ehci_soft_itd_t *itd, *prev, *start, *stop; 4537 int i, j, k; 4538 int frames, ufrperframe; 4539 int err; 4540 4541 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4542 4543 start = NULL; 4544 prev = NULL; 4545 itd = NULL; 4546 4547 KASSERT(xfer->ux_nframes != 0); 4548 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4549 KASSERT(exfer->ex_isdone); 4550 4551 exfer->ex_type = EX_ISOC; 4552 4553 /* 4554 * Step 1: Allocate and initialize itds, how many do we need? 4555 * One per transfer if interval >= 8 microframes, less if we use 4556 * multiple microframes per frame. 4557 */ 4558 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4559 if (i > 16 || i == 0) { 4560 /* Spec page 271 says intervals > 16 are invalid */ 4561 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4562 return USBD_INVAL; 4563 } 4564 4565 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4566 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4567 4568 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4569 itd = ehci_alloc_itd(sc); 4570 if (itd == NULL) { 4571 err = ENOMEM; 4572 goto fail; 4573 } 4574 4575 if (prev != NULL) { 4576 /* Maybe not as it's updated by the scheduling? */ 4577 prev->itd.itd_next = 4578 htole32(itd->physaddr | EHCI_LINK_ITD); 4579 4580 prev->xfer_next = itd; 4581 } else { 4582 start = itd; 4583 } 4584 4585 /* 4586 * Other special values 4587 */ 4588 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4589 itd->itd.itd_bufr[0] = htole32( 4590 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4591 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4592 4593 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4594 ? 1 : 0; 4595 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4596 itd->itd.itd_bufr[1] |= htole32( 4597 EHCI_ITD_SET_DIR(k) | 4598 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4599 4600 /* FIXME: handle invalid trans - should be done in openpipe */ 4601 itd->itd.itd_bufr[2] |= 4602 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4603 } /* End of frame */ 4604 4605 stop = itd; 4606 stop->xfer_next = NULL; 4607 4608 exfer->ex_itdstart = start; 4609 exfer->ex_itdend = stop; 4610 4611 return 0; 4612 fail: 4613 mutex_enter(&sc->sc_lock); 4614 ehci_soft_itd_t *next; 4615 for (itd = start; itd; itd = next) { 4616 next = itd->xfer_next; 4617 ehci_free_itd_locked(sc, itd); 4618 } 4619 mutex_exit(&sc->sc_lock); 4620 4621 return err; 4622 4623 } 4624 4625 Static void 4626 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4627 { 4628 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4629 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4630 4631 KASSERT(ex->ex_type == EX_ISOC); 4632 4633 ehci_free_itd_chain(sc, ex->ex_itdstart); 4634 } 4635 4636 Static usbd_status 4637 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4638 { 4639 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4640 usbd_status __diagused err; 4641 4642 mutex_enter(&sc->sc_lock); 4643 err = usb_insert_transfer(xfer); 4644 mutex_exit(&sc->sc_lock); 4645 4646 KASSERT(err == USBD_NORMAL_COMPLETION); 4647 4648 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4649 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4650 ehci_soft_itd_t *itd, *prev; 4651 usb_dma_t *dma_buf; 4652 int i, j; 4653 int frames, uframes, ufrperframe; 4654 int trans_count, offs, total_length; 4655 int frindex; 4656 4657 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4658 4659 prev = NULL; 4660 itd = NULL; 4661 trans_count = 0; 4662 total_length = 0; 4663 4664 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4665 4666 if (sc->sc_dying) 4667 return USBD_IOERROR; 4668 4669 /* 4670 * To avoid complication, don't allow a request right now that'll span 4671 * the entire frame table. To within 4 frames, to allow some leeway 4672 * on either side of where the hc currently is. 4673 */ 4674 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4675 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4676 DPRINTF( 4677 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4678 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4679 return USBD_INVAL; 4680 } 4681 4682 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4683 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4684 KASSERT(exfer->ex_isdone); 4685 #ifdef DIAGNOSTIC 4686 exfer->ex_isdone = false; 4687 #endif 4688 4689 /* 4690 * Step 1: Re-Initialize itds 4691 */ 4692 4693 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4694 if (i > 16 || i == 0) { 4695 /* Spec page 271 says intervals > 16 are invalid */ 4696 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4697 return USBD_INVAL; 4698 } 4699 4700 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4701 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4702 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4703 4704 if (frames == 0) { 4705 DPRINTF("frames == 0", 0, 0, 0, 0); 4706 return USBD_INVAL; 4707 } 4708 4709 dma_buf = &xfer->ux_dmabuf; 4710 offs = 0; 4711 4712 itd = exfer->ex_itdstart; 4713 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4714 int froffs = offs; 4715 4716 if (prev != NULL) { 4717 prev->itd.itd_next = 4718 htole32(itd->physaddr | EHCI_LINK_ITD); 4719 usb_syncmem(&prev->dma, 4720 prev->offs + offsetof(ehci_itd_t, itd_next), 4721 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4722 prev->xfer_next = itd; 4723 } 4724 4725 /* 4726 * Step 1.5, initialize uframes 4727 */ 4728 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4729 /* Calculate which page in the list this starts in */ 4730 int addr = DMAADDR(dma_buf, froffs); 4731 addr = EHCI_PAGE_OFFSET(addr); 4732 addr += (offs - froffs); 4733 addr = EHCI_PAGE(addr); 4734 addr /= EHCI_PAGE_SIZE; 4735 4736 /* 4737 * This gets the initial offset into the first page, 4738 * looks how far further along the current uframe 4739 * offset is. Works out how many pages that is. 4740 */ 4741 4742 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4743 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4744 EHCI_ITD_SET_PG(addr) | 4745 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4746 4747 total_length += xfer->ux_frlengths[trans_count]; 4748 offs += xfer->ux_frlengths[trans_count]; 4749 trans_count++; 4750 4751 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4752 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4753 break; 4754 } 4755 } 4756 4757 /* 4758 * Step 1.75, set buffer pointers. To simplify matters, all 4759 * pointers are filled out for the next 7 hardware pages in 4760 * the dma block, so no need to worry what pages to cover 4761 * and what to not. 4762 */ 4763 4764 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4765 /* 4766 * Don't try to lookup a page that's past the end 4767 * of buffer 4768 */ 4769 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4770 if (page_offs >= dma_buf->udma_block->size) 4771 break; 4772 4773 uint64_t page = DMAADDR(dma_buf, page_offs); 4774 page = EHCI_PAGE(page); 4775 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4776 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4777 } 4778 /* 4779 * Other special values 4780 */ 4781 4782 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4783 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4784 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4785 4786 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4787 ? 1 : 0; 4788 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4789 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4790 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4791 4792 /* FIXME: handle invalid trans */ 4793 itd->itd.itd_bufr[2] |= 4794 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4795 4796 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4797 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4798 4799 prev = itd; 4800 } /* End of frame */ 4801 4802 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4804 4805 /* 4806 * Part 2: Transfer descriptors have now been set up, now they must 4807 * be scheduled into the period frame list. Erk. Not wanting to 4808 * complicate matters, transfer is denied if the transfer spans 4809 * more than the period frame list. 4810 */ 4811 4812 mutex_enter(&sc->sc_lock); 4813 4814 /* Start inserting frames */ 4815 if (epipe->isoc.cur_xfers > 0) { 4816 frindex = epipe->isoc.next_frame; 4817 } else { 4818 frindex = EOREAD4(sc, EHCI_FRINDEX); 4819 frindex = frindex >> 3; /* Erase microframe index */ 4820 frindex += 2; 4821 } 4822 4823 if (frindex >= sc->sc_flsize) 4824 frindex &= (sc->sc_flsize - 1); 4825 4826 /* What's the frame interval? */ 4827 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4828 if (i / USB_UFRAMES_PER_FRAME == 0) 4829 i = 1; 4830 else 4831 i /= USB_UFRAMES_PER_FRAME; 4832 4833 itd = exfer->ex_itdstart; 4834 for (j = 0; j < frames; j++) { 4835 KASSERTMSG(itd != NULL, "frame %d\n", j); 4836 4837 usb_syncmem(&sc->sc_fldma, 4838 sizeof(ehci_link_t) * frindex, 4839 sizeof(ehci_link_t), 4840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4841 4842 itd->itd.itd_next = sc->sc_flist[frindex]; 4843 if (itd->itd.itd_next == 0) 4844 /* 4845 * FIXME: frindex table gets initialized to NULL 4846 * or EHCI_NULL? 4847 */ 4848 itd->itd.itd_next = EHCI_NULL; 4849 4850 usb_syncmem(&itd->dma, 4851 itd->offs + offsetof(ehci_itd_t, itd_next), 4852 sizeof(itd->itd.itd_next), 4853 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4854 4855 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4856 4857 usb_syncmem(&sc->sc_fldma, 4858 sizeof(ehci_link_t) * frindex, 4859 sizeof(ehci_link_t), 4860 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4861 4862 itd->frame_list.next = sc->sc_softitds[frindex]; 4863 sc->sc_softitds[frindex] = itd; 4864 if (itd->frame_list.next != NULL) 4865 itd->frame_list.next->frame_list.prev = itd; 4866 itd->slot = frindex; 4867 itd->frame_list.prev = NULL; 4868 4869 frindex += i; 4870 if (frindex >= sc->sc_flsize) 4871 frindex -= sc->sc_flsize; 4872 4873 itd = itd->xfer_next; 4874 } 4875 4876 epipe->isoc.cur_xfers++; 4877 epipe->isoc.next_frame = frindex; 4878 4879 ehci_add_intr_list(sc, exfer); 4880 xfer->ux_status = USBD_IN_PROGRESS; 4881 mutex_exit(&sc->sc_lock); 4882 4883 return USBD_IN_PROGRESS; 4884 } 4885 4886 Static void 4887 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4888 { 4889 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4890 4891 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4892 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4893 } 4894 4895 Static void 4896 ehci_device_isoc_close(struct usbd_pipe *pipe) 4897 { 4898 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4899 4900 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4901 } 4902 4903 Static void 4904 ehci_device_isoc_done(struct usbd_xfer *xfer) 4905 { 4906 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4907 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4908 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4909 4910 KASSERT(mutex_owned(&sc->sc_lock)); 4911 4912 epipe->isoc.cur_xfers--; 4913 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4914 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4915 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4916 } 4917
Indexes created Wed Oct 01 19:09:53 GMT 2025