ehci.c revision 1.254.8.6
1 /* $NetBSD: ehci.c,v 1.254.8.6 2018/09/28 08:33:43 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.254.8.6 2018/09/28 08:33:43 martin Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 #include <sys/reboot.h> 79 80 #include <machine/endian.h> 81 82 #include <dev/usb/usb.h> 83 #include <dev/usb/usbdi.h> 84 #include <dev/usb/usbdivar.h> 85 #include <dev/usb/usbhist.h> 86 #include <dev/usb/usb_mem.h> 87 #include <dev/usb/usb_quirks.h> 88 89 #include <dev/usb/ehcireg.h> 90 #include <dev/usb/ehcivar.h> 91 #include <dev/usb/usbroothub.h> 92 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 static int ehcidebug = 0; 99 100 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 101 { 102 int err; 103 const struct sysctlnode *rnode; 104 const struct sysctlnode *cnode; 105 106 err = sysctl_createv(clog, 0, NULL, &rnode, 107 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 108 SYSCTL_DESCR("ehci global controls"), 109 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 110 111 if (err) 112 goto fail; 113 114 /* control debugging printfs */ 115 err = sysctl_createv(clog, 0, &rnode, &cnode, 116 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 117 "debug", SYSCTL_DESCR("Enable debugging output"), 118 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 119 if (err) 120 goto fail; 121 122 return; 123 fail: 124 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 125 } 126 127 #endif /* EHCI_DEBUG */ 128 #endif /* USB_DEBUG */ 129 130 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 131 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 132 #define EHCIHIST_FUNC() USBHIST_FUNC() 133 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 134 135 struct ehci_pipe { 136 struct usbd_pipe pipe; 137 int nexttoggle; 138 139 ehci_soft_qh_t *sqh; 140 union { 141 /* Control pipe */ 142 struct { 143 usb_dma_t reqdma; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 u_int length; 148 } intr; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 }; 155 }; 156 157 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 158 159 Static usbd_status ehci_open(struct usbd_pipe *); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_timeout(void *); 171 Static void ehci_timeout_task(void *); 172 Static void ehci_intrlist_timeout(void *); 173 Static void ehci_doorbell(void *); 174 Static void ehci_pcd(void *); 175 176 Static struct usbd_xfer * 177 ehci_allocx(struct usbd_bus *, unsigned int); 178 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 179 180 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 181 Static int ehci_roothub_ctrl(struct usbd_bus *, 182 usb_device_request_t *, void *, int); 183 184 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 185 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 186 Static void ehci_root_intr_abort(struct usbd_xfer *); 187 Static void ehci_root_intr_close(struct usbd_pipe *); 188 Static void ehci_root_intr_done(struct usbd_xfer *); 189 190 Static int ehci_device_ctrl_init(struct usbd_xfer *); 191 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 193 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 194 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 195 Static void ehci_device_ctrl_close(struct usbd_pipe *); 196 Static void ehci_device_ctrl_done(struct usbd_xfer *); 197 198 Static int ehci_device_bulk_init(struct usbd_xfer *); 199 Static void ehci_device_bulk_fini(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 201 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 202 Static void ehci_device_bulk_abort(struct usbd_xfer *); 203 Static void ehci_device_bulk_close(struct usbd_pipe *); 204 Static void ehci_device_bulk_done(struct usbd_xfer *); 205 206 Static int ehci_device_intr_init(struct usbd_xfer *); 207 Static void ehci_device_intr_fini(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 209 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 210 Static void ehci_device_intr_abort(struct usbd_xfer *); 211 Static void ehci_device_intr_close(struct usbd_pipe *); 212 Static void ehci_device_intr_done(struct usbd_xfer *); 213 214 Static int ehci_device_isoc_init(struct usbd_xfer *); 215 Static void ehci_device_isoc_fini(struct usbd_xfer *); 216 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 217 Static void ehci_device_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_isoc_done(struct usbd_xfer *); 220 221 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 223 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 225 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 226 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 227 228 Static void ehci_device_clear_toggle(struct usbd_pipe *); 229 Static void ehci_noop(struct usbd_pipe *); 230 231 Static void ehci_disown(ehci_softc_t *, int, int); 232 233 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 234 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 235 236 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 237 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 238 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 239 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 240 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 241 242 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 243 int, int, int *, ehci_soft_qtd_t **); 244 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 245 246 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 247 Static ehci_soft_sitd_t * 248 ehci_alloc_sitd(ehci_softc_t *); 249 250 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 251 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 252 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 253 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 254 255 static inline void 256 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 257 { 258 259 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 260 } 261 262 static inline void 263 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 264 { 265 266 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 267 } 268 269 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 270 271 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 272 int); 273 274 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 275 ehci_soft_qh_t *); 276 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 277 ehci_soft_qh_t *); 278 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 279 Static void ehci_sync_hc(ehci_softc_t *); 280 281 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 282 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 283 284 #ifdef EHCI_DEBUG 285 Static ehci_softc_t *theehci; 286 void ehci_dump(void); 287 #endif 288 289 #ifdef EHCI_DEBUG 290 Static void ehci_dump_regs(ehci_softc_t *); 291 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 292 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 293 Static void ehci_dump_qtd(ehci_qtd_t *); 294 Static void ehci_dump_sqh(ehci_soft_qh_t *); 295 Static void ehci_dump_sitd(struct ehci_soft_itd *); 296 Static void ehci_dump_itds(ehci_soft_itd_t *); 297 Static void ehci_dump_itd(struct ehci_soft_itd *); 298 Static void ehci_dump_exfer(struct ehci_xfer *); 299 #endif 300 301 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 302 303 static inline void 304 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 305 { 306 307 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 308 } 309 310 static inline void 311 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 312 { 313 314 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 315 } 316 317 Static const struct usbd_bus_methods ehci_bus_methods = { 318 .ubm_open = ehci_open, 319 .ubm_softint = ehci_softintr, 320 .ubm_dopoll = ehci_poll, 321 .ubm_allocx = ehci_allocx, 322 .ubm_freex = ehci_freex, 323 .ubm_getlock = ehci_get_lock, 324 .ubm_rhctrl = ehci_roothub_ctrl, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 328 .upm_transfer = ehci_root_intr_transfer, 329 .upm_start = ehci_root_intr_start, 330 .upm_abort = ehci_root_intr_abort, 331 .upm_close = ehci_root_intr_close, 332 .upm_cleartoggle = ehci_noop, 333 .upm_done = ehci_root_intr_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 337 .upm_init = ehci_device_ctrl_init, 338 .upm_fini = ehci_device_ctrl_fini, 339 .upm_transfer = ehci_device_ctrl_transfer, 340 .upm_start = ehci_device_ctrl_start, 341 .upm_abort = ehci_device_ctrl_abort, 342 .upm_close = ehci_device_ctrl_close, 343 .upm_cleartoggle = ehci_noop, 344 .upm_done = ehci_device_ctrl_done, 345 }; 346 347 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 348 .upm_init = ehci_device_intr_init, 349 .upm_fini = ehci_device_intr_fini, 350 .upm_transfer = ehci_device_intr_transfer, 351 .upm_start = ehci_device_intr_start, 352 .upm_abort = ehci_device_intr_abort, 353 .upm_close = ehci_device_intr_close, 354 .upm_cleartoggle = ehci_device_clear_toggle, 355 .upm_done = ehci_device_intr_done, 356 }; 357 358 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 359 .upm_init = ehci_device_bulk_init, 360 .upm_fini = ehci_device_bulk_fini, 361 .upm_transfer = ehci_device_bulk_transfer, 362 .upm_start = ehci_device_bulk_start, 363 .upm_abort = ehci_device_bulk_abort, 364 .upm_close = ehci_device_bulk_close, 365 .upm_cleartoggle = ehci_device_clear_toggle, 366 .upm_done = ehci_device_bulk_done, 367 }; 368 369 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 370 .upm_init = ehci_device_isoc_init, 371 .upm_fini = ehci_device_isoc_fini, 372 .upm_transfer = ehci_device_isoc_transfer, 373 .upm_abort = ehci_device_isoc_abort, 374 .upm_close = ehci_device_isoc_close, 375 .upm_cleartoggle = ehci_noop, 376 .upm_done = ehci_device_isoc_done, 377 }; 378 379 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 380 .upm_init = ehci_device_fs_isoc_init, 381 .upm_fini = ehci_device_fs_isoc_fini, 382 .upm_transfer = ehci_device_fs_isoc_transfer, 383 .upm_abort = ehci_device_fs_isoc_abort, 384 .upm_close = ehci_device_fs_isoc_close, 385 .upm_cleartoggle = ehci_noop, 386 .upm_done = ehci_device_fs_isoc_done, 387 }; 388 389 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 390 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 391 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 392 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 393 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 394 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 395 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 396 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 397 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 398 }; 399 400 int 401 ehci_init(ehci_softc_t *sc) 402 { 403 uint32_t vers, sparams, cparams, hcr; 404 u_int i; 405 usbd_status err; 406 ehci_soft_qh_t *sqh; 407 u_int ncomp; 408 409 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 410 #ifdef EHCI_DEBUG 411 theehci = sc; 412 #endif 413 414 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 415 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 416 cv_init(&sc->sc_doorbell, "ehcidb"); 417 418 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 419 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 420 421 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 422 ehci_doorbell, sc); 423 KASSERT(sc->sc_doorbell_si != NULL); 424 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 425 ehci_pcd, sc); 426 KASSERT(sc->sc_pcd_si != NULL); 427 428 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 429 430 vers = EREAD2(sc, EHCI_HCIVERSION); 431 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 432 vers >> 8, vers & 0xff); 433 434 sparams = EREAD4(sc, EHCI_HCSPARAMS); 435 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 436 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 437 ncomp = EHCI_HCS_N_CC(sparams); 438 if (ncomp != sc->sc_ncomp) { 439 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 440 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 441 #if NOHCI == 0 || NUHCI == 0 442 aprint_error("%s: ohci or uhci probably not configured\n", 443 device_xname(sc->sc_dev)); 444 #endif 445 if (ncomp < sc->sc_ncomp) 446 sc->sc_ncomp = ncomp; 447 } 448 if (sc->sc_ncomp > 0) { 449 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 450 aprint_normal_dev(sc->sc_dev, 451 "%d companion controller%s, %d port%s%s", 452 sc->sc_ncomp, 453 sc->sc_ncomp!=1 ? "s" : "", 454 EHCI_HCS_N_PCC(sparams), 455 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 456 sc->sc_ncomp!=1 ? " each" : ""); 457 if (sc->sc_comps[0]) { 458 aprint_normal(":"); 459 for (i = 0; i < sc->sc_ncomp; i++) 460 aprint_normal(" %s", 461 device_xname(sc->sc_comps[i])); 462 } 463 aprint_normal("\n"); 464 465 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 466 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 467 cv_init(&sc->sc_compcv, "ehciccv"); 468 sc->sc_comp_state = CO_EARLY; 469 } 470 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 471 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 472 473 cparams = EREAD4(sc, EHCI_HCCPARAMS); 474 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 475 476 if (EHCI_HCC_64BIT(cparams)) { 477 /* MUST clear segment register if 64 bit capable. */ 478 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 479 } 480 481 if (cparams & EHCI_HCC_IST_FULLFRAME) { 482 sc->sc_istthreshold = 0; 483 } else { 484 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 485 } 486 487 sc->sc_bus.ub_revision = USBREV_2_0; 488 sc->sc_bus.ub_usedma = true; 489 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 490 491 /* Reset the controller */ 492 DPRINTF("resetting", 0, 0, 0, 0); 493 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 494 usb_delay_ms(&sc->sc_bus, 1); 495 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 496 for (i = 0; i < 100; i++) { 497 usb_delay_ms(&sc->sc_bus, 1); 498 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 499 if (!hcr) 500 break; 501 } 502 if (hcr) { 503 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 504 return EIO; 505 } 506 if (sc->sc_vendor_init) 507 sc->sc_vendor_init(sc); 508 509 /* XXX need proper intr scheduling */ 510 sc->sc_rand = 96; 511 512 /* frame list size at default, read back what we got and use that */ 513 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 514 case 0: sc->sc_flsize = 1024; break; 515 case 1: sc->sc_flsize = 512; break; 516 case 2: sc->sc_flsize = 256; break; 517 case 3: return EIO; 518 } 519 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 520 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 521 if (err) 522 return err; 523 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 524 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 525 526 for (i = 0; i < sc->sc_flsize; i++) { 527 sc->sc_flist[i] = EHCI_NULL; 528 } 529 530 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 531 532 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 533 KM_SLEEP); 534 if (sc->sc_softitds == NULL) 535 return ENOMEM; 536 LIST_INIT(&sc->sc_freeitds); 537 LIST_INIT(&sc->sc_freesitds); 538 TAILQ_INIT(&sc->sc_intrhead); 539 540 /* Set up the bus struct. */ 541 sc->sc_bus.ub_methods = &ehci_bus_methods; 542 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 543 544 sc->sc_eintrs = EHCI_NORMAL_INTRS; 545 546 /* 547 * Allocate the interrupt dummy QHs. These are arranged to give poll 548 * intervals that are powers of 2 times 1ms. 549 */ 550 for (i = 0; i < EHCI_INTRQHS; i++) { 551 sqh = ehci_alloc_sqh(sc); 552 if (sqh == NULL) { 553 err = ENOMEM; 554 goto bad1; 555 } 556 sc->sc_islots[i].sqh = sqh; 557 } 558 for (i = 0; i < EHCI_INTRQHS; i++) { 559 sqh = sc->sc_islots[i].sqh; 560 if (i == 0) { 561 /* The last (1ms) QH terminates. */ 562 sqh->qh.qh_link = EHCI_NULL; 563 sqh->next = NULL; 564 } else { 565 /* Otherwise the next QH has half the poll interval */ 566 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 567 sqh->qh.qh_link = htole32(sqh->next->physaddr | 568 EHCI_LINK_QH); 569 } 570 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 571 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 572 sqh->qh.qh_curqtd = EHCI_NULL; 573 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 574 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 575 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 576 sqh->sqtd = NULL; 577 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 578 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 579 } 580 /* Point the frame list at the last level (128ms). */ 581 for (i = 0; i < sc->sc_flsize; i++) { 582 int j; 583 584 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 585 revbits[i & (EHCI_MAX_POLLRATE-1)]; 586 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 587 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 588 i)].sqh->physaddr); 589 } 590 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 591 BUS_DMASYNC_PREWRITE); 592 593 /* Allocate dummy QH that starts the async list. */ 594 sqh = ehci_alloc_sqh(sc); 595 if (sqh == NULL) { 596 err = ENOMEM; 597 goto bad1; 598 } 599 /* Fill the QH */ 600 sqh->qh.qh_endp = 601 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 602 sqh->qh.qh_link = 603 htole32(sqh->physaddr | EHCI_LINK_QH); 604 sqh->qh.qh_curqtd = EHCI_NULL; 605 sqh->next = NULL; 606 /* Fill the overlay qTD */ 607 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 608 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 609 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 610 sqh->sqtd = NULL; 611 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 612 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 613 #ifdef EHCI_DEBUG 614 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 615 ehci_dump_sqh(sqh); 616 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 617 #endif 618 619 /* Point to async list */ 620 sc->sc_async_head = sqh; 621 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 622 623 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 624 625 /* Turn on controller */ 626 EOWRITE4(sc, EHCI_USBCMD, 627 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 628 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 629 EHCI_CMD_ASE | 630 EHCI_CMD_PSE | 631 EHCI_CMD_RS); 632 633 /* Take over port ownership */ 634 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 635 636 for (i = 0; i < 100; i++) { 637 usb_delay_ms(&sc->sc_bus, 1); 638 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 639 if (!hcr) 640 break; 641 } 642 if (hcr) { 643 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 644 return EIO; 645 } 646 647 /* Enable interrupts */ 648 DPRINTF("enabling interupts", 0, 0, 0, 0); 649 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 650 651 return 0; 652 653 #if 0 654 bad2: 655 ehci_free_sqh(sc, sc->sc_async_head); 656 #endif 657 bad1: 658 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 659 return err; 660 } 661 662 int 663 ehci_intr(void *v) 664 { 665 ehci_softc_t *sc = v; 666 int ret = 0; 667 668 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 669 670 if (sc == NULL) 671 return 0; 672 673 mutex_spin_enter(&sc->sc_intr_lock); 674 675 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 676 goto done; 677 678 /* If we get an interrupt while polling, then just ignore it. */ 679 if (sc->sc_bus.ub_usepolling) { 680 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 681 682 if (intrs) 683 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 684 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 685 goto done; 686 } 687 688 ret = ehci_intr1(sc); 689 690 done: 691 mutex_spin_exit(&sc->sc_intr_lock); 692 return ret; 693 } 694 695 Static int 696 ehci_intr1(ehci_softc_t *sc) 697 { 698 uint32_t intrs, eintrs; 699 700 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 701 702 /* In case the interrupt occurs before initialization has completed. */ 703 if (sc == NULL) { 704 #ifdef DIAGNOSTIC 705 printf("ehci_intr1: sc == NULL\n"); 706 #endif 707 return 0; 708 } 709 710 KASSERT(mutex_owned(&sc->sc_intr_lock)); 711 712 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 713 if (!intrs) 714 return 0; 715 716 eintrs = intrs & sc->sc_eintrs; 717 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 718 EOREAD4(sc, EHCI_USBSTS), eintrs); 719 if (!eintrs) 720 return 0; 721 722 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 723 if (eintrs & EHCI_STS_IAA) { 724 DPRINTF("door bell", 0, 0, 0, 0); 725 kpreempt_disable(); 726 KASSERT(sc->sc_doorbell_si != NULL); 727 softint_schedule(sc->sc_doorbell_si); 728 kpreempt_enable(); 729 eintrs &= ~EHCI_STS_IAA; 730 } 731 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 732 DPRINTF("INT=%jd ERRINT=%jd", 733 eintrs & EHCI_STS_INT ? 1 : 0, 734 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 735 usb_schedsoftintr(&sc->sc_bus); 736 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 737 } 738 if (eintrs & EHCI_STS_HSE) { 739 printf("%s: unrecoverable error, controller halted\n", 740 device_xname(sc->sc_dev)); 741 /* XXX what else */ 742 } 743 if (eintrs & EHCI_STS_PCD) { 744 kpreempt_disable(); 745 KASSERT(sc->sc_pcd_si != NULL); 746 softint_schedule(sc->sc_pcd_si); 747 kpreempt_enable(); 748 eintrs &= ~EHCI_STS_PCD; 749 } 750 751 if (eintrs != 0) { 752 /* Block unprocessed interrupts. */ 753 sc->sc_eintrs &= ~eintrs; 754 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 755 printf("%s: blocking intrs 0x%x\n", 756 device_xname(sc->sc_dev), eintrs); 757 } 758 759 return 1; 760 } 761 762 Static void 763 ehci_doorbell(void *addr) 764 { 765 ehci_softc_t *sc = addr; 766 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 cv_broadcast(&sc->sc_doorbell); 770 mutex_exit(&sc->sc_lock); 771 } 772 773 Static void 774 ehci_pcd(void *addr) 775 { 776 ehci_softc_t *sc = addr; 777 struct usbd_xfer *xfer; 778 u_char *p; 779 int i, m; 780 781 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 782 783 mutex_enter(&sc->sc_lock); 784 xfer = sc->sc_intrxfer; 785 786 if (xfer == NULL) { 787 /* Just ignore the change. */ 788 goto done; 789 } 790 791 p = xfer->ux_buf; 792 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 793 memset(p, 0, xfer->ux_length); 794 for (i = 1; i <= m; i++) { 795 /* Pick out CHANGE bits from the status reg. */ 796 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 797 p[i/8] |= 1 << (i%8); 798 if (i % 8 == 7) 799 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 800 } 801 xfer->ux_actlen = xfer->ux_length; 802 xfer->ux_status = USBD_NORMAL_COMPLETION; 803 804 usb_transfer_complete(xfer); 805 806 done: 807 mutex_exit(&sc->sc_lock); 808 } 809 810 Static void 811 ehci_softintr(void *v) 812 { 813 struct usbd_bus *bus = v; 814 ehci_softc_t *sc = EHCI_BUS2SC(bus); 815 struct ehci_xfer *ex, *nextex; 816 817 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 818 819 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 820 821 ex_completeq_t cq; 822 TAILQ_INIT(&cq); 823 824 /* 825 * The only explanation I can think of for why EHCI is as brain dead 826 * as UHCI interrupt-wise is that Intel was involved in both. 827 * An interrupt just tells us that something is done, we have no 828 * clue what, so we need to scan through all active transfers. :-( 829 */ 830 831 /* 832 * ehci_idone will remove transfer from sc->sc_intrhead if it's 833 * complete and add to our cq list 834 * 835 */ 836 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 837 switch (ex->ex_type) { 838 case EX_CTRL: 839 case EX_BULK: 840 case EX_INTR: 841 ehci_check_qh_intr(sc, ex, &cq); 842 break; 843 case EX_ISOC: 844 ehci_check_itd_intr(sc, ex, &cq); 845 break; 846 case EX_FS_ISOC: 847 ehci_check_sitd_intr(sc, ex, &cq); 848 break; 849 default: 850 KASSERT(false); 851 } 852 853 } 854 855 /* 856 * We abuse ex_next for the interrupt and complete lists and 857 * interrupt transfers will get re-added here so use 858 * the _SAFE version of TAILQ_FOREACH. 859 */ 860 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 861 usb_transfer_complete(&ex->ex_xfer); 862 } 863 864 /* Schedule a callout to catch any dropped transactions. */ 865 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 866 !TAILQ_EMPTY(&sc->sc_intrhead)) 867 callout_reset(&sc->sc_tmo_intrlist, 868 hz, ehci_intrlist_timeout, sc); 869 } 870 871 Static void 872 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 873 { 874 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 875 uint32_t status; 876 877 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 878 879 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 880 881 if (ex->ex_type == EX_CTRL) { 882 fsqtd = ex->ex_setup; 883 lsqtd = ex->ex_status; 884 } else { 885 fsqtd = ex->ex_sqtdstart; 886 lsqtd = ex->ex_sqtdend; 887 } 888 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 889 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 890 891 /* 892 * If the last TD is still active we need to check whether there 893 * is an error somewhere in the middle, or whether there was a 894 * short packet (SPD and not ACTIVE). 895 */ 896 usb_syncmem(&lsqtd->dma, 897 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 898 sizeof(lsqtd->qtd.qtd_status), 899 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 900 status = le32toh(lsqtd->qtd.qtd_status); 901 usb_syncmem(&lsqtd->dma, 902 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 903 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 904 if (status & EHCI_QTD_ACTIVE) { 905 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 906 907 /* last qTD has already been checked */ 908 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 909 usb_syncmem(&sqtd->dma, 910 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 911 sizeof(sqtd->qtd.qtd_status), 912 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 913 status = le32toh(sqtd->qtd.qtd_status); 914 usb_syncmem(&sqtd->dma, 915 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 916 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 917 /* If there's an active QTD the xfer isn't done. */ 918 if (status & EHCI_QTD_ACTIVE) 919 break; 920 /* Any kind of error makes the xfer done. */ 921 if (status & EHCI_QTD_HALTED) 922 goto done; 923 /* Handle short packets */ 924 if (EHCI_QTD_GET_BYTES(status) != 0) { 925 /* 926 * If we get here for a control transfer then 927 * we need to let the hardware complete the 928 * status phase. That is, we're not done 929 * quite yet. 930 * 931 * Otherwise, we're done. 932 */ 933 if (ex->ex_type == EX_CTRL) { 934 break; 935 } 936 goto done; 937 } 938 } 939 DPRINTFN(10, "ex=%#jx std=%#jx still active", 940 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 941 #ifdef EHCI_DEBUG 942 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 943 ehci_dump_sqtds(ex->ex_sqtdstart); 944 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 945 #endif 946 return; 947 } 948 done: 949 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 950 ehci_idone(ex, cq); 951 } 952 953 Static void 954 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 955 { 956 ehci_soft_itd_t *itd; 957 int i; 958 959 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 960 961 KASSERT(mutex_owned(&sc->sc_lock)); 962 963 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 964 return; 965 966 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 967 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 968 969 itd = ex->ex_itdend; 970 971 /* 972 * check no active transfers in last itd, meaning we're finished 973 */ 974 975 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 976 sizeof(itd->itd.itd_ctl), 977 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 978 979 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 980 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 981 break; 982 } 983 984 if (i == EHCI_ITD_NUFRAMES) { 985 goto done; /* All 8 descriptors inactive, it's done */ 986 } 987 988 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 989 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 990 991 DPRINTFN(10, "ex %#jx itd %#jx still active", 992 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 993 return; 994 done: 995 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 996 ehci_idone(ex, cq); 997 } 998 999 void 1000 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1001 { 1002 ehci_soft_sitd_t *sitd; 1003 1004 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1005 1006 KASSERT(mutex_owned(&sc->sc_lock)); 1007 1008 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1009 return; 1010 1011 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1012 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1013 1014 sitd = ex->ex_sitdend; 1015 1016 /* 1017 * check no active transfers in last sitd, meaning we're finished 1018 */ 1019 1020 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1021 sizeof(sitd->sitd.sitd_trans), 1022 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1023 1024 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1025 1026 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1027 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1028 1029 if (active) 1030 return; 1031 1032 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1033 ehci_idone(ex, cq); 1034 } 1035 1036 1037 Static void 1038 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1039 { 1040 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1041 struct usbd_xfer *xfer = &ex->ex_xfer; 1042 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1043 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1044 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1045 uint32_t status = 0, nstatus = 0; 1046 int actlen = 0; 1047 1048 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1049 1050 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1051 1052 /* 1053 * If software has completed it, either by cancellation 1054 * or timeout, drop it on the floor. 1055 */ 1056 if (xfer->ux_status != USBD_IN_PROGRESS) { 1057 KASSERT(xfer->ux_status == USBD_CANCELLED || 1058 xfer->ux_status == USBD_TIMEOUT); 1059 DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1060 return; 1061 } 1062 1063 /* 1064 * Cancel the timeout and the task, which have not yet 1065 * run. If they have already fired, at worst they are 1066 * waiting for the lock. They will see that the xfer 1067 * is no longer in progress and give up. 1068 */ 1069 callout_stop(&xfer->ux_callout); 1070 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 1071 1072 #ifdef DIAGNOSTIC 1073 #ifdef EHCI_DEBUG 1074 if (ex->ex_isdone) { 1075 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1076 ehci_dump_exfer(ex); 1077 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1078 } 1079 #endif 1080 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1081 ex->ex_type, xfer->ux_status); 1082 ex->ex_isdone = true; 1083 #endif 1084 1085 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1086 (uintptr_t)epipe, 0, 0); 1087 1088 /* The transfer is done, compute actual length and status. */ 1089 if (ex->ex_type == EX_ISOC) { 1090 /* HS isoc transfer */ 1091 1092 struct ehci_soft_itd *itd; 1093 int i, nframes, len, uframes; 1094 1095 nframes = 0; 1096 1097 #ifdef EHCI_DEBUG 1098 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1099 ehci_dump_itds(ex->ex_itdstart); 1100 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1101 #endif 1102 1103 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1104 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1105 1106 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1107 usb_syncmem(&itd->dma, 1108 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1109 sizeof(itd->itd.itd_ctl), 1110 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1111 1112 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1113 /* 1114 * XXX - driver didn't fill in the frame full 1115 * of uframes. This leads to scheduling 1116 * inefficiencies, but working around 1117 * this doubles complexity of tracking 1118 * an xfer. 1119 */ 1120 if (nframes >= xfer->ux_nframes) 1121 break; 1122 1123 status = le32toh(itd->itd.itd_ctl[i]); 1124 len = EHCI_ITD_GET_LEN(status); 1125 if (EHCI_ITD_GET_STATUS(status) != 0) 1126 len = 0; /*No valid data on error*/ 1127 1128 xfer->ux_frlengths[nframes++] = len; 1129 actlen += len; 1130 } 1131 usb_syncmem(&itd->dma, 1132 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1133 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1134 1135 if (nframes >= xfer->ux_nframes) 1136 break; 1137 } 1138 1139 xfer->ux_actlen = actlen; 1140 xfer->ux_status = USBD_NORMAL_COMPLETION; 1141 goto end; 1142 } else if (ex->ex_type == EX_FS_ISOC) { 1143 /* FS isoc transfer */ 1144 struct ehci_soft_sitd *sitd; 1145 int nframes, len; 1146 1147 nframes = 0; 1148 1149 for (sitd = ex->ex_sitdstart; sitd != NULL; 1150 sitd = sitd->xfer_next) { 1151 usb_syncmem(&sitd->dma, 1152 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1153 sizeof(sitd->sitd.sitd_trans), 1154 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1155 1156 /* 1157 * XXX - driver didn't fill in the frame full 1158 * of uframes. This leads to scheduling 1159 * inefficiencies, but working around 1160 * this doubles complexity of tracking 1161 * an xfer. 1162 */ 1163 if (nframes >= xfer->ux_nframes) 1164 break; 1165 1166 status = le32toh(sitd->sitd.sitd_trans); 1167 usb_syncmem(&sitd->dma, 1168 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1169 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1170 1171 len = EHCI_SITD_GET_LEN(status); 1172 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1173 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1174 /* No valid data on error */ 1175 len = xfer->ux_frlengths[nframes]; 1176 } 1177 1178 /* 1179 * frlengths[i]: # of bytes to send 1180 * len: # of bytes host didn't send 1181 */ 1182 xfer->ux_frlengths[nframes] -= len; 1183 /* frlengths[i]: # of bytes host sent */ 1184 actlen += xfer->ux_frlengths[nframes++]; 1185 1186 if (nframes >= xfer->ux_nframes) 1187 break; 1188 } 1189 1190 xfer->ux_actlen = actlen; 1191 xfer->ux_status = USBD_NORMAL_COMPLETION; 1192 goto end; 1193 } 1194 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1195 ex->ex_type == EX_BULK); 1196 1197 /* Continue processing xfers using queue heads */ 1198 if (ex->ex_type == EX_CTRL) { 1199 fsqtd = ex->ex_setup; 1200 lsqtd = ex->ex_status; 1201 } else { 1202 fsqtd = ex->ex_sqtdstart; 1203 lsqtd = ex->ex_sqtdend; 1204 } 1205 #ifdef EHCI_DEBUG 1206 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1207 ehci_dump_sqtds(fsqtd); 1208 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1209 #endif 1210 1211 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1212 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1213 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1214 nstatus = le32toh(sqtd->qtd.qtd_status); 1215 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1216 BUS_DMASYNC_PREREAD); 1217 if (nstatus & EHCI_QTD_ACTIVE) 1218 break; 1219 1220 status = nstatus; 1221 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1222 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1223 } 1224 1225 /* 1226 * If there are left over TDs we need to update the toggle. 1227 * The default pipe doesn't need it since control transfers 1228 * start the toggle at 0 every time. 1229 * For a short transfer we need to update the toggle for the missing 1230 * packets within the qTD. 1231 */ 1232 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1233 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1234 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1235 status, nstatus, 0, 0); 1236 #if 0 1237 ehci_dump_sqh(epipe->sqh); 1238 ehci_dump_sqtds(ex->ex_sqtdstart); 1239 #endif 1240 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1241 } 1242 1243 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1244 status, 0); 1245 xfer->ux_actlen = actlen; 1246 if (status & EHCI_QTD_HALTED) { 1247 #ifdef EHCI_DEBUG 1248 DPRINTF("halted addr=%jd endpt=0x%02jx", 1249 xfer->ux_pipe->up_dev->ud_addr, 1250 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1251 0, 0); 1252 DPRINTF("cerr=%jd pid=%jd", 1253 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1254 0, 0); 1255 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1256 status & EHCI_QTD_ACTIVE ? 1 : 0, 1257 status & EHCI_QTD_HALTED ? 1 : 0, 1258 status & EHCI_QTD_BUFERR ? 1 : 0, 1259 status & EHCI_QTD_BABBLE ? 1 : 0); 1260 1261 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1262 status & EHCI_QTD_XACTERR ? 1 : 0, 1263 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1264 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1265 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1266 1267 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1268 ehci_dump_sqh(epipe->sqh); 1269 ehci_dump_sqtds(ex->ex_sqtdstart); 1270 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1271 #endif 1272 /* low&full speed has an extra error flag */ 1273 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1274 EHCI_QH_SPEED_HIGH) 1275 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1276 else 1277 status &= EHCI_QTD_STATERRS; 1278 if (status == 0) /* no other errors means a stall */ { 1279 xfer->ux_status = USBD_STALLED; 1280 } else { 1281 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1282 } 1283 /* XXX need to reset TT on missed microframe */ 1284 if (status & EHCI_QTD_MISSEDMICRO) { 1285 printf("%s: missed microframe, TT reset not " 1286 "implemented, hub might be inoperational\n", 1287 device_xname(sc->sc_dev)); 1288 } 1289 } else { 1290 xfer->ux_status = USBD_NORMAL_COMPLETION; 1291 } 1292 1293 end: 1294 1295 ehci_del_intr_list(sc, ex); 1296 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1297 1298 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1299 } 1300 1301 Static void 1302 ehci_poll(struct usbd_bus *bus) 1303 { 1304 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1305 1306 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1307 1308 #ifdef EHCI_DEBUG 1309 static int last; 1310 int new; 1311 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1312 if (new != last) { 1313 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1314 last = new; 1315 } 1316 #endif 1317 1318 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1319 mutex_spin_enter(&sc->sc_intr_lock); 1320 ehci_intr1(sc); 1321 mutex_spin_exit(&sc->sc_intr_lock); 1322 } 1323 } 1324 1325 void 1326 ehci_childdet(device_t self, device_t child) 1327 { 1328 struct ehci_softc *sc = device_private(self); 1329 1330 KASSERT(sc->sc_child == child); 1331 sc->sc_child = NULL; 1332 } 1333 1334 int 1335 ehci_detach(struct ehci_softc *sc, int flags) 1336 { 1337 int rv = 0; 1338 1339 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1340 1341 if (sc->sc_child != NULL) 1342 rv = config_detach(sc->sc_child, flags); 1343 1344 if (rv != 0) 1345 return rv; 1346 1347 if (sc->sc_ncomp > 0) { 1348 mutex_enter(&sc->sc_complock); 1349 /* XXX try to halt callout instead of waiting */ 1350 while (sc->sc_comp_state == CO_SCHED) 1351 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1352 mutex_exit(&sc->sc_complock); 1353 1354 callout_halt(&sc->sc_compcallout, NULL); 1355 callout_destroy(&sc->sc_compcallout); 1356 cv_destroy(&sc->sc_compcv); 1357 mutex_destroy(&sc->sc_complock); 1358 } 1359 1360 callout_halt(&sc->sc_tmo_intrlist, NULL); 1361 callout_destroy(&sc->sc_tmo_intrlist); 1362 1363 /* XXX free other data structures XXX */ 1364 if (sc->sc_softitds) 1365 kmem_free(sc->sc_softitds, 1366 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1367 cv_destroy(&sc->sc_doorbell); 1368 1369 #if 0 1370 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1371 1372 softint_disestablish(sc->sc_doorbell_si); 1373 softint_disestablish(sc->sc_pcd_si); 1374 1375 mutex_destroy(&sc->sc_lock); 1376 mutex_destroy(&sc->sc_intr_lock); 1377 #endif 1378 1379 pool_cache_destroy(sc->sc_xferpool); 1380 1381 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1382 1383 return rv; 1384 } 1385 1386 1387 int 1388 ehci_activate(device_t self, enum devact act) 1389 { 1390 struct ehci_softc *sc = device_private(self); 1391 1392 switch (act) { 1393 case DVACT_DEACTIVATE: 1394 sc->sc_dying = 1; 1395 return 0; 1396 default: 1397 return EOPNOTSUPP; 1398 } 1399 } 1400 1401 /* 1402 * Handle suspend/resume. 1403 * 1404 * We need to switch to polling mode here, because this routine is 1405 * called from an interrupt context. This is all right since we 1406 * are almost suspended anyway. 1407 * 1408 * Note that this power handler isn't to be registered directly; the 1409 * bus glue needs to call out to it. 1410 */ 1411 bool 1412 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1413 { 1414 ehci_softc_t *sc = device_private(dv); 1415 int i; 1416 uint32_t cmd, hcr; 1417 1418 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1419 1420 mutex_spin_enter(&sc->sc_intr_lock); 1421 sc->sc_bus.ub_usepolling++; 1422 mutex_spin_exit(&sc->sc_intr_lock); 1423 1424 for (i = 1; i <= sc->sc_noport; i++) { 1425 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1426 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1427 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1428 } 1429 1430 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1431 1432 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1433 EOWRITE4(sc, EHCI_USBCMD, cmd); 1434 1435 for (i = 0; i < 100; i++) { 1436 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1437 if (hcr == 0) 1438 break; 1439 1440 usb_delay_ms(&sc->sc_bus, 1); 1441 } 1442 if (hcr != 0) 1443 printf("%s: reset timeout\n", device_xname(dv)); 1444 1445 cmd &= ~EHCI_CMD_RS; 1446 EOWRITE4(sc, EHCI_USBCMD, cmd); 1447 1448 for (i = 0; i < 100; i++) { 1449 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1450 if (hcr == EHCI_STS_HCH) 1451 break; 1452 1453 usb_delay_ms(&sc->sc_bus, 1); 1454 } 1455 if (hcr != EHCI_STS_HCH) 1456 printf("%s: config timeout\n", device_xname(dv)); 1457 1458 mutex_spin_enter(&sc->sc_intr_lock); 1459 sc->sc_bus.ub_usepolling--; 1460 mutex_spin_exit(&sc->sc_intr_lock); 1461 1462 return true; 1463 } 1464 1465 bool 1466 ehci_resume(device_t dv, const pmf_qual_t *qual) 1467 { 1468 ehci_softc_t *sc = device_private(dv); 1469 int i; 1470 uint32_t cmd, hcr; 1471 1472 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1473 1474 /* restore things in case the bios sucks */ 1475 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1476 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1477 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1478 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1479 1480 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1481 1482 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1483 1484 hcr = 0; 1485 for (i = 1; i <= sc->sc_noport; i++) { 1486 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1487 if ((cmd & EHCI_PS_PO) == 0 && 1488 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1489 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1490 hcr = 1; 1491 } 1492 } 1493 1494 if (hcr) { 1495 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1496 1497 for (i = 1; i <= sc->sc_noport; i++) { 1498 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1499 if ((cmd & EHCI_PS_PO) == 0 && 1500 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1501 EOWRITE4(sc, EHCI_PORTSC(i), 1502 cmd & ~EHCI_PS_FPR); 1503 } 1504 } 1505 1506 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1507 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1508 1509 for (i = 0; i < 100; i++) { 1510 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1511 if (hcr != EHCI_STS_HCH) 1512 break; 1513 1514 usb_delay_ms(&sc->sc_bus, 1); 1515 } 1516 if (hcr == EHCI_STS_HCH) 1517 printf("%s: config timeout\n", device_xname(dv)); 1518 1519 return true; 1520 } 1521 1522 /* 1523 * Shut down the controller when the system is going down. 1524 */ 1525 bool 1526 ehci_shutdown(device_t self, int flags) 1527 { 1528 ehci_softc_t *sc = device_private(self); 1529 1530 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1531 1532 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1533 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1534 return true; 1535 } 1536 1537 Static struct usbd_xfer * 1538 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1539 { 1540 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1541 struct usbd_xfer *xfer; 1542 1543 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1544 if (xfer != NULL) { 1545 memset(xfer, 0, sizeof(struct ehci_xfer)); 1546 1547 /* Initialise this always so we can call remove on it. */ 1548 usb_init_task(&xfer->ux_aborttask, ehci_timeout_task, xfer, 1549 USB_TASKQ_MPSAFE); 1550 #ifdef DIAGNOSTIC 1551 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1552 ex->ex_isdone = true; 1553 xfer->ux_state = XFER_BUSY; 1554 #endif 1555 } 1556 return xfer; 1557 } 1558 1559 Static void 1560 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1561 { 1562 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1563 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1564 1565 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1566 xfer->ux_state); 1567 KASSERT(ex->ex_isdone); 1568 1569 #ifdef DIAGNOSTIC 1570 xfer->ux_state = XFER_FREE; 1571 #endif 1572 1573 pool_cache_put(sc->sc_xferpool, xfer); 1574 } 1575 1576 Static void 1577 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1578 { 1579 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1580 1581 *lock = &sc->sc_lock; 1582 } 1583 1584 Static void 1585 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1586 { 1587 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1588 1589 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1590 1591 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1592 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1593 #ifdef EHCI_DEBUG 1594 if (ehcidebug) 1595 usbd_dump_pipe(pipe); 1596 #endif 1597 epipe->nexttoggle = 0; 1598 } 1599 1600 Static void 1601 ehci_noop(struct usbd_pipe *pipe) 1602 { 1603 } 1604 1605 #ifdef EHCI_DEBUG 1606 /* 1607 * Unused function - this is meant to be called from a kernel 1608 * debugger. 1609 */ 1610 void 1611 ehci_dump(void) 1612 { 1613 ehci_softc_t *sc = theehci; 1614 int i; 1615 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1616 EOREAD4(sc, EHCI_USBCMD), 1617 EOREAD4(sc, EHCI_USBSTS), 1618 EOREAD4(sc, EHCI_USBINTR)); 1619 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1620 EOREAD4(sc, EHCI_FRINDEX), 1621 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1622 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1623 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1624 for (i = 1; i <= sc->sc_noport; i++) 1625 printf("port %d status=0x%08x\n", i, 1626 EOREAD4(sc, EHCI_PORTSC(i))); 1627 } 1628 1629 Static void 1630 ehci_dump_regs(ehci_softc_t *sc) 1631 { 1632 int i; 1633 1634 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1635 1636 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1637 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1638 EOREAD4(sc, EHCI_USBINTR), 0); 1639 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1640 "async = 0x%08jx", 1641 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1642 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1643 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1644 for (i = 1; i <= sc->sc_noport; i += 2) { 1645 if (i == sc->sc_noport) { 1646 DPRINTF("port %jd status = 0x%08jx", i, 1647 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1648 } else { 1649 DPRINTF("port %jd status = 0x%08jx port %jd " 1650 "status = 0x%08jx", 1651 i, EOREAD4(sc, EHCI_PORTSC(i)), 1652 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1653 } 1654 } 1655 } 1656 1657 #define ehci_dump_link(link, type) do { \ 1658 DPRINTF(" link 0x%08jx (T = %jd):", \ 1659 link, \ 1660 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1661 if (type) { \ 1662 DPRINTF( \ 1663 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1664 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1665 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1666 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1667 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1668 } \ 1669 } while(0) 1670 1671 Static void 1672 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1673 { 1674 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1675 int i; 1676 uint32_t stop = 0; 1677 1678 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1679 ehci_dump_sqtd(sqtd); 1680 usb_syncmem(&sqtd->dma, 1681 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1682 sizeof(sqtd->qtd), 1683 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1684 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1685 usb_syncmem(&sqtd->dma, 1686 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1687 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1688 } 1689 if (!stop) 1690 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1691 } 1692 1693 Static void 1694 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1695 { 1696 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1697 1698 usb_syncmem(&sqtd->dma, sqtd->offs, 1699 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1700 1701 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1702 0, 0); 1703 ehci_dump_qtd(&sqtd->qtd); 1704 1705 usb_syncmem(&sqtd->dma, sqtd->offs, 1706 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1707 } 1708 1709 Static void 1710 ehci_dump_qtd(ehci_qtd_t *qtd) 1711 { 1712 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1713 uint32_t s = le32toh(qtd->qtd_status); 1714 1715 DPRINTFN(10, 1716 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1717 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1718 DPRINTFN(10, 1719 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1720 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1721 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1722 DPRINTFN(10, 1723 " cerr = %jd pid = %jd stat = %jx", 1724 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1725 0); 1726 DPRINTFN(10, 1727 "active =%jd halted=%jd buferr=%jd babble=%jd", 1728 s & EHCI_QTD_ACTIVE ? 1 : 0, 1729 s & EHCI_QTD_HALTED ? 1 : 0, 1730 s & EHCI_QTD_BUFERR ? 1 : 0, 1731 s & EHCI_QTD_BABBLE ? 1 : 0); 1732 DPRINTFN(10, 1733 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1734 s & EHCI_QTD_XACTERR ? 1 : 0, 1735 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1736 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1737 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1738 DPRINTFN(10, 1739 "buffer[0] = %#jx buffer[1] = %#jx " 1740 "buffer[2] = %#jx buffer[3] = %#jx", 1741 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1742 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1743 DPRINTFN(10, 1744 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1745 } 1746 1747 Static void 1748 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1749 { 1750 ehci_qh_t *qh = &sqh->qh; 1751 ehci_link_t link; 1752 uint32_t endp, endphub; 1753 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1754 1755 usb_syncmem(&sqh->dma, sqh->offs, 1756 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1757 1758 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1759 link = le32toh(qh->qh_link); 1760 ehci_dump_link(link, true); 1761 1762 endp = le32toh(qh->qh_endp); 1763 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1764 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1765 "eps = %jd", 1766 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1767 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1768 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1769 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1770 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1771 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1772 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1773 1774 endphub = le32toh(qh->qh_endphub); 1775 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1776 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1777 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1778 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1779 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1780 EHCI_QH_GET_MULT(endphub), 0); 1781 1782 link = le32toh(qh->qh_curqtd); 1783 ehci_dump_link(link, false); 1784 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1785 ehci_dump_qtd(&qh->qh_qtd); 1786 1787 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1788 BUS_DMASYNC_PREREAD); 1789 } 1790 1791 Static void 1792 ehci_dump_itds(ehci_soft_itd_t *itd) 1793 { 1794 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1795 int i; 1796 uint32_t stop = 0; 1797 1798 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1799 ehci_dump_itd(itd); 1800 usb_syncmem(&itd->dma, 1801 itd->offs + offsetof(ehci_itd_t, itd_next), 1802 sizeof(itd->itd), 1803 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1804 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1805 usb_syncmem(&itd->dma, 1806 itd->offs + offsetof(ehci_itd_t, itd_next), 1807 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1808 } 1809 if (!stop) 1810 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1811 } 1812 1813 Static void 1814 ehci_dump_itd(struct ehci_soft_itd *itd) 1815 { 1816 ehci_isoc_trans_t t; 1817 ehci_isoc_bufr_ptr_t b, b2, b3; 1818 int i; 1819 1820 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1821 1822 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1823 1824 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1825 t = le32toh(itd->itd.itd_ctl[i]); 1826 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1827 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1828 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1829 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1830 EHCI_ITD_GET_OFFS(t), 0); 1831 } 1832 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1833 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1834 DPRINTF(" %jx", 1835 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1836 1837 b = le32toh(itd->itd.itd_bufr[0]); 1838 b2 = le32toh(itd->itd.itd_bufr[1]); 1839 b3 = le32toh(itd->itd.itd_bufr[2]); 1840 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1841 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1842 DPRINTF(" maxpkt = %jx multi = %jx", 1843 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1844 } 1845 1846 Static void 1847 ehci_dump_sitd(struct ehci_soft_itd *itd) 1848 { 1849 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1850 1851 DPRINTF("SITD %#jx next = %p prev = %#jx", 1852 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1853 (uintptr_t)itd->frame_list.prev, 0); 1854 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1855 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1856 } 1857 1858 Static void 1859 ehci_dump_exfer(struct ehci_xfer *ex) 1860 { 1861 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1862 1863 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1864 ex->ex_isdone, 0); 1865 1866 switch (ex->ex_type) { 1867 case EX_CTRL: 1868 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1869 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1870 (uintptr_t)ex->ex_status, 0); 1871 break; 1872 case EX_BULK: 1873 case EX_INTR: 1874 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1875 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1876 0, 0); 1877 break; 1878 case EX_ISOC: 1879 DPRINTF(" itdstart = %#jx itdend = %#jx", 1880 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1881 break; 1882 case EX_FS_ISOC: 1883 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1884 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1885 0, 0); 1886 break; 1887 default: 1888 DPRINTF(" unknown type", 0, 0, 0, 0); 1889 } 1890 } 1891 #endif 1892 1893 Static usbd_status 1894 ehci_open(struct usbd_pipe *pipe) 1895 { 1896 struct usbd_device *dev = pipe->up_dev; 1897 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1898 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1899 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1900 uint8_t addr = dev->ud_addr; 1901 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1902 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1903 ehci_soft_qh_t *sqh; 1904 usbd_status err; 1905 int ival, speed, naks; 1906 int hshubaddr, hshubport; 1907 1908 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1909 1910 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1911 ed->bEndpointAddress, rhaddr); 1912 1913 if (dev->ud_myhsport) { 1914 /* 1915 * When directly attached FS/LS device while doing embedded 1916 * transaction translations and we are the hub, set the hub 1917 * address to 0 (us). 1918 */ 1919 if (!(sc->sc_flags & EHCIF_ETTF) 1920 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1921 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1922 } else { 1923 hshubaddr = 0; 1924 } 1925 hshubport = dev->ud_myhsport->up_portno; 1926 } else { 1927 hshubaddr = 0; 1928 hshubport = 0; 1929 } 1930 1931 if (sc->sc_dying) 1932 return USBD_IOERROR; 1933 1934 /* toggle state needed for bulk endpoints */ 1935 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1936 1937 if (addr == rhaddr) { 1938 switch (ed->bEndpointAddress) { 1939 case USB_CONTROL_ENDPOINT: 1940 pipe->up_methods = &roothub_ctrl_methods; 1941 break; 1942 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1943 pipe->up_methods = &ehci_root_intr_methods; 1944 break; 1945 default: 1946 DPRINTF("bad bEndpointAddress 0x%02jx", 1947 ed->bEndpointAddress, 0, 0, 0); 1948 return USBD_INVAL; 1949 } 1950 return USBD_NORMAL_COMPLETION; 1951 } 1952 1953 /* XXX All this stuff is only valid for async. */ 1954 switch (dev->ud_speed) { 1955 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1956 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1957 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1958 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1959 } 1960 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1961 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1962 0); 1963 return USBD_INVAL; 1964 } 1965 1966 /* 1967 * For interrupt transfer, nak throttling must be disabled, but for 1968 * the other transfer type, nak throttling should be enabled from the 1969 * viewpoint that avoids the memory thrashing. 1970 */ 1971 naks = (xfertype == UE_INTERRUPT) ? 0 1972 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1973 1974 /* Allocate sqh for everything, save isoc xfers */ 1975 if (xfertype != UE_ISOCHRONOUS) { 1976 sqh = ehci_alloc_sqh(sc); 1977 if (sqh == NULL) 1978 return USBD_NOMEM; 1979 /* qh_link filled when the QH is added */ 1980 sqh->qh.qh_endp = htole32( 1981 EHCI_QH_SET_ADDR(addr) | 1982 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1983 EHCI_QH_SET_EPS(speed) | 1984 EHCI_QH_DTC | 1985 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1986 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1987 EHCI_QH_CTL : 0) | 1988 EHCI_QH_SET_NRL(naks) 1989 ); 1990 sqh->qh.qh_endphub = htole32( 1991 EHCI_QH_SET_MULT(1) | 1992 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1993 ); 1994 if (speed != EHCI_QH_SPEED_HIGH) 1995 sqh->qh.qh_endphub |= htole32( 1996 EHCI_QH_SET_PORT(hshubport) | 1997 EHCI_QH_SET_HUBA(hshubaddr) | 1998 (xfertype == UE_INTERRUPT ? 1999 EHCI_QH_SET_CMASK(0x08) : 0) 2000 ); 2001 sqh->qh.qh_curqtd = EHCI_NULL; 2002 /* Fill the overlay qTD */ 2003 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2004 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2005 sqh->qh.qh_qtd.qtd_status = htole32(0); 2006 2007 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2008 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2009 epipe->sqh = sqh; 2010 } else { 2011 sqh = NULL; 2012 } /*xfertype == UE_ISOC*/ 2013 2014 switch (xfertype) { 2015 case UE_CONTROL: 2016 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2017 0, &epipe->ctrl.reqdma); 2018 #ifdef EHCI_DEBUG 2019 if (err) 2020 printf("ehci_open: usb_allocmem()=%d\n", err); 2021 #endif 2022 if (err) 2023 goto bad; 2024 pipe->up_methods = &ehci_device_ctrl_methods; 2025 mutex_enter(&sc->sc_lock); 2026 ehci_add_qh(sc, sqh, sc->sc_async_head); 2027 mutex_exit(&sc->sc_lock); 2028 break; 2029 case UE_BULK: 2030 pipe->up_methods = &ehci_device_bulk_methods; 2031 mutex_enter(&sc->sc_lock); 2032 ehci_add_qh(sc, sqh, sc->sc_async_head); 2033 mutex_exit(&sc->sc_lock); 2034 break; 2035 case UE_INTERRUPT: 2036 pipe->up_methods = &ehci_device_intr_methods; 2037 ival = pipe->up_interval; 2038 if (ival == USBD_DEFAULT_INTERVAL) { 2039 if (speed == EHCI_QH_SPEED_HIGH) { 2040 if (ed->bInterval > 16) { 2041 /* 2042 * illegal with high-speed, but there 2043 * were documentation bugs in the spec, 2044 * so be generous 2045 */ 2046 ival = 256; 2047 } else 2048 ival = (1 << (ed->bInterval - 1)) / 8; 2049 } else 2050 ival = ed->bInterval; 2051 } 2052 err = ehci_device_setintr(sc, sqh, ival); 2053 if (err) 2054 goto bad; 2055 break; 2056 case UE_ISOCHRONOUS: 2057 pipe->up_serialise = false; 2058 if (speed == EHCI_QH_SPEED_HIGH) 2059 pipe->up_methods = &ehci_device_isoc_methods; 2060 else 2061 pipe->up_methods = &ehci_device_fs_isoc_methods; 2062 if (ed->bInterval == 0 || ed->bInterval > 16) { 2063 printf("ehci: opening pipe with invalid bInterval\n"); 2064 err = USBD_INVAL; 2065 goto bad; 2066 } 2067 if (UGETW(ed->wMaxPacketSize) == 0) { 2068 printf("ehci: zero length endpoint open request\n"); 2069 err = USBD_INVAL; 2070 goto bad; 2071 } 2072 epipe->isoc.next_frame = 0; 2073 epipe->isoc.cur_xfers = 0; 2074 break; 2075 default: 2076 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2077 err = USBD_INVAL; 2078 goto bad; 2079 } 2080 return USBD_NORMAL_COMPLETION; 2081 2082 bad: 2083 if (sqh != NULL) { 2084 mutex_enter(&sc->sc_lock); 2085 ehci_free_sqh(sc, sqh); 2086 mutex_exit(&sc->sc_lock); 2087 } 2088 return err; 2089 } 2090 2091 /* 2092 * Add an ED to the schedule. Called with USB lock held. 2093 */ 2094 Static void 2095 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2096 { 2097 2098 KASSERT(mutex_owned(&sc->sc_lock)); 2099 2100 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2101 2102 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2103 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2104 2105 sqh->next = head->next; 2106 sqh->qh.qh_link = head->qh.qh_link; 2107 2108 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2109 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2110 2111 head->next = sqh; 2112 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2113 2114 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2115 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2116 2117 #ifdef EHCI_DEBUG 2118 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2119 ehci_dump_sqh(sqh); 2120 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2121 #endif 2122 } 2123 2124 /* 2125 * Remove an ED from the schedule. Called with USB lock held. 2126 */ 2127 Static void 2128 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2129 { 2130 ehci_soft_qh_t *p; 2131 2132 KASSERT(mutex_owned(&sc->sc_lock)); 2133 2134 /* XXX */ 2135 for (p = head; p != NULL && p->next != sqh; p = p->next) 2136 ; 2137 if (p == NULL) 2138 panic("ehci_rem_qh: ED not found"); 2139 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2140 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2141 p->next = sqh->next; 2142 p->qh.qh_link = sqh->qh.qh_link; 2143 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2144 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2145 2146 ehci_sync_hc(sc); 2147 } 2148 2149 Static void 2150 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2151 { 2152 int i; 2153 uint32_t status; 2154 2155 /* Save toggle bit and ping status. */ 2156 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2157 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2158 status = sqh->qh.qh_qtd.qtd_status & 2159 htole32(EHCI_QTD_TOGGLE_MASK | 2160 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2161 /* Set HALTED to make hw leave it alone. */ 2162 sqh->qh.qh_qtd.qtd_status = 2163 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2164 usb_syncmem(&sqh->dma, 2165 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2166 sizeof(sqh->qh.qh_qtd.qtd_status), 2167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2168 sqh->qh.qh_curqtd = 0; 2169 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2170 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2171 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2172 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2173 sqh->sqtd = sqtd; 2174 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2175 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2176 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2177 sqh->qh.qh_qtd.qtd_status = status; 2178 usb_syncmem(&sqh->dma, 2179 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2180 sizeof(sqh->qh.qh_qtd.qtd_status), 2181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2182 } 2183 2184 /* 2185 * Ensure that the HC has released all references to the QH. We do this 2186 * by asking for a Async Advance Doorbell interrupt and then we wait for 2187 * the interrupt. 2188 * To make this easier we first obtain exclusive use of the doorbell. 2189 */ 2190 Static void 2191 ehci_sync_hc(ehci_softc_t *sc) 2192 { 2193 int error __diagused; 2194 2195 KASSERT(mutex_owned(&sc->sc_lock)); 2196 2197 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2198 2199 if (sc->sc_dying) { 2200 DPRINTF("dying", 0, 0, 0, 0); 2201 return; 2202 } 2203 2204 /* ask for doorbell */ 2205 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2206 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2207 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2208 2209 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2210 2211 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2212 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2213 #ifdef DIAGNOSTIC 2214 if (error == EWOULDBLOCK) { 2215 printf("ehci_sync_hc: timed out\n"); 2216 } else if (error) { 2217 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2218 } 2219 #endif 2220 } 2221 2222 Static void 2223 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2224 { 2225 2226 KASSERT(mutex_owned(&sc->sc_lock)); 2227 2228 for (; itd != NULL; itd = itd->xfer_next) { 2229 struct ehci_soft_itd *prev = itd->frame_list.prev; 2230 2231 /* Unlink itd from hardware chain, or frame array */ 2232 if (prev == NULL) { /* We're at the table head */ 2233 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2234 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2235 usb_syncmem(&sc->sc_fldma, 2236 sizeof(ehci_link_t) * itd->slot, 2237 sizeof(ehci_link_t), 2238 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2239 2240 if (itd->frame_list.next != NULL) 2241 itd->frame_list.next->frame_list.prev = NULL; 2242 } else { 2243 /* XXX this part is untested... */ 2244 prev->itd.itd_next = itd->itd.itd_next; 2245 usb_syncmem(&itd->dma, 2246 itd->offs + offsetof(ehci_itd_t, itd_next), 2247 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2248 2249 prev->frame_list.next = itd->frame_list.next; 2250 if (itd->frame_list.next != NULL) 2251 itd->frame_list.next->frame_list.prev = prev; 2252 } 2253 } 2254 } 2255 2256 Static void 2257 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2258 { 2259 struct ehci_soft_itd *next; 2260 2261 mutex_enter(&sc->sc_lock); 2262 next = NULL; 2263 for (; itd != NULL; itd = next) { 2264 next = itd->xfer_next; 2265 ehci_free_itd_locked(sc, itd); 2266 } 2267 mutex_exit(&sc->sc_lock); 2268 } 2269 2270 Static void 2271 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2272 { 2273 2274 KASSERT(mutex_owned(&sc->sc_lock)); 2275 2276 for (; sitd != NULL; sitd = sitd->xfer_next) { 2277 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2278 2279 /* Unlink sitd from hardware chain, or frame array */ 2280 if (prev == NULL) { /* We're at the table head */ 2281 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2282 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2283 usb_syncmem(&sc->sc_fldma, 2284 sizeof(ehci_link_t) * sitd->slot, 2285 sizeof(ehci_link_t), 2286 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2287 2288 if (sitd->frame_list.next != NULL) 2289 sitd->frame_list.next->frame_list.prev = NULL; 2290 } else { 2291 /* XXX this part is untested... */ 2292 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2293 usb_syncmem(&sitd->dma, 2294 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2295 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2296 2297 prev->frame_list.next = sitd->frame_list.next; 2298 if (sitd->frame_list.next != NULL) 2299 sitd->frame_list.next->frame_list.prev = prev; 2300 } 2301 } 2302 } 2303 2304 Static void 2305 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2306 { 2307 2308 mutex_enter(&sc->sc_lock); 2309 struct ehci_soft_sitd *next = NULL; 2310 for (; sitd != NULL; sitd = next) { 2311 next = sitd->xfer_next; 2312 ehci_free_sitd_locked(sc, sitd); 2313 } 2314 mutex_exit(&sc->sc_lock); 2315 } 2316 2317 /***********/ 2318 2319 Static int 2320 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2321 void *buf, int buflen) 2322 { 2323 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2324 usb_hub_descriptor_t hubd; 2325 usb_port_status_t ps; 2326 uint16_t len, value, index; 2327 int l, totlen = 0; 2328 int port, i; 2329 uint32_t v; 2330 2331 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2332 2333 if (sc->sc_dying) 2334 return -1; 2335 2336 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2337 0, 0); 2338 2339 len = UGETW(req->wLength); 2340 value = UGETW(req->wValue); 2341 index = UGETW(req->wIndex); 2342 2343 #define C(x,y) ((x) | ((y) << 8)) 2344 switch (C(req->bRequest, req->bmRequestType)) { 2345 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2346 if (len == 0) 2347 break; 2348 switch (value) { 2349 case C(0, UDESC_DEVICE): { 2350 usb_device_descriptor_t devd; 2351 totlen = min(buflen, sizeof(devd)); 2352 memcpy(&devd, buf, totlen); 2353 USETW(devd.idVendor, sc->sc_id_vendor); 2354 memcpy(buf, &devd, totlen); 2355 break; 2356 2357 } 2358 #define sd ((usb_string_descriptor_t *)buf) 2359 case C(1, UDESC_STRING): 2360 /* Vendor */ 2361 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2362 break; 2363 case C(2, UDESC_STRING): 2364 /* Product */ 2365 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2366 break; 2367 #undef sd 2368 default: 2369 /* default from usbroothub */ 2370 return buflen; 2371 } 2372 break; 2373 2374 /* Hub requests */ 2375 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2376 break; 2377 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2378 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2379 value, 0, 0); 2380 if (index < 1 || index > sc->sc_noport) { 2381 return -1; 2382 } 2383 port = EHCI_PORTSC(index); 2384 v = EOREAD4(sc, port); 2385 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2386 v &= ~EHCI_PS_CLEAR; 2387 switch (value) { 2388 case UHF_PORT_ENABLE: 2389 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2390 break; 2391 case UHF_PORT_SUSPEND: 2392 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2393 break; 2394 v &= ~EHCI_PS_SUSP; 2395 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2396 /* see USB2 spec ch. 7.1.7.7 */ 2397 usb_delay_ms(&sc->sc_bus, 20); 2398 EOWRITE4(sc, port, v); 2399 usb_delay_ms(&sc->sc_bus, 2); 2400 #ifdef DEBUG 2401 v = EOREAD4(sc, port); 2402 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2403 printf("ehci: resume failed: %x\n", v); 2404 #endif 2405 break; 2406 case UHF_PORT_POWER: 2407 if (sc->sc_hasppc) 2408 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2409 break; 2410 case UHF_PORT_TEST: 2411 DPRINTF("clear port test %jd", index, 0, 0, 0); 2412 break; 2413 case UHF_PORT_INDICATOR: 2414 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2415 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2416 break; 2417 case UHF_C_PORT_CONNECTION: 2418 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2419 break; 2420 case UHF_C_PORT_ENABLE: 2421 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2422 break; 2423 case UHF_C_PORT_SUSPEND: 2424 /* how? */ 2425 break; 2426 case UHF_C_PORT_OVER_CURRENT: 2427 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2428 break; 2429 case UHF_C_PORT_RESET: 2430 sc->sc_isreset[index] = 0; 2431 break; 2432 default: 2433 return -1; 2434 } 2435 #if 0 2436 switch(value) { 2437 case UHF_C_PORT_CONNECTION: 2438 case UHF_C_PORT_ENABLE: 2439 case UHF_C_PORT_SUSPEND: 2440 case UHF_C_PORT_OVER_CURRENT: 2441 case UHF_C_PORT_RESET: 2442 default: 2443 break; 2444 } 2445 #endif 2446 break; 2447 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2448 if (len == 0) 2449 break; 2450 if ((value & 0xff) != 0) { 2451 return -1; 2452 } 2453 totlen = min(buflen, sizeof(hubd)); 2454 memcpy(&hubd, buf, totlen); 2455 hubd.bNbrPorts = sc->sc_noport; 2456 v = EOREAD4(sc, EHCI_HCSPARAMS); 2457 USETW(hubd.wHubCharacteristics, 2458 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2459 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2460 ? UHD_PORT_IND : 0); 2461 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2462 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2463 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2464 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2465 totlen = min(totlen, hubd.bDescLength); 2466 memcpy(buf, &hubd, totlen); 2467 break; 2468 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2469 if (len != 4) { 2470 return -1; 2471 } 2472 memset(buf, 0, len); /* ? XXX */ 2473 totlen = len; 2474 break; 2475 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2476 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2477 if (index < 1 || index > sc->sc_noport) { 2478 return -1; 2479 } 2480 if (len != 4) { 2481 return -1; 2482 } 2483 v = EOREAD4(sc, EHCI_PORTSC(index)); 2484 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2485 2486 i = UPS_HIGH_SPEED; 2487 if (sc->sc_flags & EHCIF_ETTF) { 2488 /* 2489 * If we are doing embedded transaction translation, 2490 * then directly attached LS/FS devices are reset by 2491 * the EHCI controller itself. PSPD is encoded 2492 * the same way as in USBSTATUS. 2493 */ 2494 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2495 } 2496 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2497 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2498 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2499 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2500 if (v & EHCI_PS_PR) i |= UPS_RESET; 2501 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2502 if (sc->sc_vendor_port_status) 2503 i = sc->sc_vendor_port_status(sc, v, i); 2504 USETW(ps.wPortStatus, i); 2505 i = 0; 2506 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2507 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2508 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2509 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2510 USETW(ps.wPortChange, i); 2511 totlen = min(len, sizeof(ps)); 2512 memcpy(buf, &ps, totlen); 2513 break; 2514 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2515 return -1; 2516 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2517 break; 2518 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2519 if (index < 1 || index > sc->sc_noport) { 2520 return -1; 2521 } 2522 port = EHCI_PORTSC(index); 2523 v = EOREAD4(sc, port); 2524 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2525 v &= ~EHCI_PS_CLEAR; 2526 switch(value) { 2527 case UHF_PORT_ENABLE: 2528 EOWRITE4(sc, port, v | EHCI_PS_PE); 2529 break; 2530 case UHF_PORT_SUSPEND: 2531 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2532 break; 2533 case UHF_PORT_RESET: 2534 DPRINTF("reset port %jd", index, 0, 0, 0); 2535 if (EHCI_PS_IS_LOWSPEED(v) 2536 && sc->sc_ncomp > 0 2537 && !(sc->sc_flags & EHCIF_ETTF)) { 2538 /* 2539 * Low speed device on non-ETTF controller or 2540 * unaccompanied controller, give up ownership. 2541 */ 2542 ehci_disown(sc, index, 1); 2543 break; 2544 } 2545 /* Start reset sequence. */ 2546 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2547 EOWRITE4(sc, port, v | EHCI_PS_PR); 2548 /* Wait for reset to complete. */ 2549 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2550 if (sc->sc_dying) { 2551 return -1; 2552 } 2553 /* 2554 * An embedded transaction translator will automatically 2555 * terminate the reset sequence so there's no need to 2556 * it. 2557 */ 2558 v = EOREAD4(sc, port); 2559 if (v & EHCI_PS_PR) { 2560 /* Terminate reset sequence. */ 2561 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2562 /* Wait for HC to complete reset. */ 2563 usb_delay_ms(&sc->sc_bus, 2564 EHCI_PORT_RESET_COMPLETE); 2565 if (sc->sc_dying) { 2566 return -1; 2567 } 2568 } 2569 2570 v = EOREAD4(sc, port); 2571 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2572 if (v & EHCI_PS_PR) { 2573 printf("%s: port reset timeout\n", 2574 device_xname(sc->sc_dev)); 2575 return USBD_TIMEOUT; 2576 } 2577 if (!(v & EHCI_PS_PE)) { 2578 /* Not a high speed device, give up ownership.*/ 2579 ehci_disown(sc, index, 0); 2580 break; 2581 } 2582 sc->sc_isreset[index] = 1; 2583 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2584 v, 0, 0); 2585 break; 2586 case UHF_PORT_POWER: 2587 DPRINTF("set port power %jd (has PPC = %jd)", index, 2588 sc->sc_hasppc, 0, 0); 2589 if (sc->sc_hasppc) 2590 EOWRITE4(sc, port, v | EHCI_PS_PP); 2591 break; 2592 case UHF_PORT_TEST: 2593 DPRINTF("set port test %jd", index, 0, 0, 0); 2594 break; 2595 case UHF_PORT_INDICATOR: 2596 DPRINTF("set port ind %jd", index, 0, 0, 0); 2597 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2598 break; 2599 default: 2600 return -1; 2601 } 2602 break; 2603 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2604 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2605 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2606 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2607 break; 2608 default: 2609 /* default from usbroothub */ 2610 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2611 2612 return buflen; 2613 } 2614 2615 DPRINTF("returning %jd", totlen, 0, 0, 0); 2616 2617 return totlen; 2618 } 2619 2620 /* 2621 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2622 * 2623 * This pile of garbage below works around the following problem without 2624 * holding boots with no hand-over devices present, while penalising 2625 * boots where the first ehci probe hands off devices with a 5 second 2626 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2627 * for RB_SINGLE, but the same basic issue exists. 2628 * 2629 * The way ehci hand-off works, the companion controller does not get the 2630 * device until after its' initial bus explore, so the reference dropped 2631 * after the first explore is not enough. 5 seconds should be enough, 2632 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2633 * 2634 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2635 * if the callback is scheduled. CO_DONE is set when the callout has 2636 * called config_pending_decr(). 2637 * 2638 * There's a mutex, a cv and a callout here, and we delay detach if the 2639 * callout has been set. 2640 */ 2641 #ifndef EHCI_DISOWN_DELAY_SECONDS 2642 #define EHCI_DISOWN_DELAY_SECONDS 5 2643 #endif 2644 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2645 2646 static void 2647 ehci_disown_callback(void *arg) 2648 { 2649 ehci_softc_t *sc = arg; 2650 2651 config_pending_decr(sc->sc_dev); 2652 2653 mutex_enter(&sc->sc_complock); 2654 KASSERT(sc->sc_comp_state == CO_SCHED); 2655 sc->sc_comp_state = CO_DONE; 2656 cv_signal(&sc->sc_compcv); 2657 mutex_exit(&sc->sc_complock); 2658 } 2659 2660 static void 2661 ehci_disown_sched_callback(ehci_softc_t *sc) 2662 { 2663 extern bool root_is_mounted; 2664 2665 mutex_enter(&sc->sc_complock); 2666 2667 if (root_is_mounted || 2668 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2669 sc->sc_comp_state != CO_EARLY) { 2670 mutex_exit(&sc->sc_complock); 2671 return; 2672 } 2673 2674 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2675 ehci_disown_callback, &sc->sc_dev); 2676 sc->sc_comp_state = CO_SCHED; 2677 2678 mutex_exit(&sc->sc_complock); 2679 2680 config_pending_incr(sc->sc_dev); 2681 aprint_normal("delaying %s by %u seconds due to USB owner change.", 2682 (boothowto & RB_ASKNAME) == 0 ? "ask root" : "single user", 2683 ehci_disown_delay_seconds); 2684 } 2685 2686 Static void 2687 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2688 { 2689 int port; 2690 uint32_t v; 2691 2692 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2693 2694 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2695 if (sc->sc_npcomp != 0) { 2696 int i = (index-1) / sc->sc_npcomp; 2697 if (i < sc->sc_ncomp) { 2698 ehci_disown_sched_callback(sc); 2699 #ifdef DIAGNOSTIC 2700 printf("%s: handing over %s speed device on " 2701 "port %d to %s\n", 2702 device_xname(sc->sc_dev), 2703 lowspeed ? "low" : "full", 2704 index, sc->sc_comps[i] ? 2705 device_xname(sc->sc_comps[i]) : 2706 "companion controller"); 2707 } else { 2708 printf("%s: strange port\n", 2709 device_xname(sc->sc_dev)); 2710 #endif 2711 } 2712 } else { 2713 #ifdef DIAGNOSTIC 2714 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2715 #endif 2716 } 2717 port = EHCI_PORTSC(index); 2718 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2719 EOWRITE4(sc, port, v | EHCI_PS_PO); 2720 } 2721 2722 Static usbd_status 2723 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2724 { 2725 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2726 usbd_status err; 2727 2728 /* Insert last in queue. */ 2729 mutex_enter(&sc->sc_lock); 2730 err = usb_insert_transfer(xfer); 2731 mutex_exit(&sc->sc_lock); 2732 if (err) 2733 return err; 2734 2735 /* Pipe isn't running, start first */ 2736 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2737 } 2738 2739 Static usbd_status 2740 ehci_root_intr_start(struct usbd_xfer *xfer) 2741 { 2742 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2743 const bool polling = sc->sc_bus.ub_usepolling; 2744 2745 if (sc->sc_dying) 2746 return USBD_IOERROR; 2747 2748 if (!polling) 2749 mutex_enter(&sc->sc_lock); 2750 sc->sc_intrxfer = xfer; 2751 if (!polling) 2752 mutex_exit(&sc->sc_lock); 2753 2754 return USBD_IN_PROGRESS; 2755 } 2756 2757 /* Abort a root interrupt request. */ 2758 Static void 2759 ehci_root_intr_abort(struct usbd_xfer *xfer) 2760 { 2761 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2762 2763 KASSERT(mutex_owned(&sc->sc_lock)); 2764 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2765 2766 sc->sc_intrxfer = NULL; 2767 2768 xfer->ux_status = USBD_CANCELLED; 2769 usb_transfer_complete(xfer); 2770 } 2771 2772 /* Close the root pipe. */ 2773 Static void 2774 ehci_root_intr_close(struct usbd_pipe *pipe) 2775 { 2776 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2777 2778 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2779 2780 KASSERT(mutex_owned(&sc->sc_lock)); 2781 2782 sc->sc_intrxfer = NULL; 2783 } 2784 2785 Static void 2786 ehci_root_intr_done(struct usbd_xfer *xfer) 2787 { 2788 } 2789 2790 /************************/ 2791 2792 Static ehci_soft_qh_t * 2793 ehci_alloc_sqh(ehci_softc_t *sc) 2794 { 2795 ehci_soft_qh_t *sqh; 2796 usbd_status err; 2797 int i, offs; 2798 usb_dma_t dma; 2799 2800 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2801 2802 mutex_enter(&sc->sc_lock); 2803 if (sc->sc_freeqhs == NULL) { 2804 DPRINTF("allocating chunk", 0, 0, 0, 0); 2805 mutex_exit(&sc->sc_lock); 2806 2807 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2808 EHCI_PAGE_SIZE, &dma); 2809 #ifdef EHCI_DEBUG 2810 if (err) 2811 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2812 #endif 2813 if (err) 2814 return NULL; 2815 2816 mutex_enter(&sc->sc_lock); 2817 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2818 offs = i * EHCI_SQH_SIZE; 2819 sqh = KERNADDR(&dma, offs); 2820 sqh->physaddr = DMAADDR(&dma, offs); 2821 sqh->dma = dma; 2822 sqh->offs = offs; 2823 sqh->next = sc->sc_freeqhs; 2824 sc->sc_freeqhs = sqh; 2825 } 2826 } 2827 sqh = sc->sc_freeqhs; 2828 sc->sc_freeqhs = sqh->next; 2829 mutex_exit(&sc->sc_lock); 2830 2831 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2832 sqh->next = NULL; 2833 return sqh; 2834 } 2835 2836 Static void 2837 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2838 { 2839 KASSERT(mutex_owned(&sc->sc_lock)); 2840 2841 sqh->next = sc->sc_freeqhs; 2842 sc->sc_freeqhs = sqh; 2843 } 2844 2845 Static ehci_soft_qtd_t * 2846 ehci_alloc_sqtd(ehci_softc_t *sc) 2847 { 2848 ehci_soft_qtd_t *sqtd = NULL; 2849 usbd_status err; 2850 int i, offs; 2851 usb_dma_t dma; 2852 2853 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2854 2855 mutex_enter(&sc->sc_lock); 2856 if (sc->sc_freeqtds == NULL) { 2857 DPRINTF("allocating chunk", 0, 0, 0, 0); 2858 mutex_exit(&sc->sc_lock); 2859 2860 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2861 EHCI_PAGE_SIZE, &dma); 2862 #ifdef EHCI_DEBUG 2863 if (err) 2864 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2865 #endif 2866 if (err) 2867 goto done; 2868 2869 mutex_enter(&sc->sc_lock); 2870 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2871 offs = i * EHCI_SQTD_SIZE; 2872 sqtd = KERNADDR(&dma, offs); 2873 sqtd->physaddr = DMAADDR(&dma, offs); 2874 sqtd->dma = dma; 2875 sqtd->offs = offs; 2876 2877 sqtd->nextqtd = sc->sc_freeqtds; 2878 sc->sc_freeqtds = sqtd; 2879 } 2880 } 2881 2882 sqtd = sc->sc_freeqtds; 2883 sc->sc_freeqtds = sqtd->nextqtd; 2884 mutex_exit(&sc->sc_lock); 2885 2886 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2887 sqtd->nextqtd = NULL; 2888 sqtd->xfer = NULL; 2889 2890 done: 2891 return sqtd; 2892 } 2893 2894 Static void 2895 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2896 { 2897 2898 mutex_enter(&sc->sc_lock); 2899 sqtd->nextqtd = sc->sc_freeqtds; 2900 sc->sc_freeqtds = sqtd; 2901 mutex_exit(&sc->sc_lock); 2902 } 2903 2904 Static int 2905 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2906 int alen, int rd, ehci_soft_qtd_t **sp) 2907 { 2908 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2909 uint16_t flags = xfer->ux_flags; 2910 2911 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2912 2913 ASSERT_SLEEPABLE(); 2914 KASSERT(sp); 2915 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2916 2917 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2918 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2919 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2920 KM_SLEEP); 2921 exfer->ex_nsqtd = nsqtd; 2922 2923 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2924 alen, nsqtd, flags); 2925 2926 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2927 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2928 if (cur == NULL) 2929 goto nomem; 2930 exfer->ex_sqtds[j++] = cur; 2931 2932 cur->xfer = xfer; 2933 cur->len = 0; 2934 2935 } 2936 2937 *sp = exfer->ex_sqtds[0]; 2938 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2939 2940 return 0; 2941 2942 nomem: 2943 ehci_free_sqtds(sc, exfer); 2944 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2945 DPRINTF("no memory", 0, 0, 0, 0); 2946 return ENOMEM; 2947 } 2948 2949 Static void 2950 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2951 { 2952 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2953 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2954 2955 mutex_enter(&sc->sc_lock); 2956 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2957 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2958 2959 if (sqtd == NULL) 2960 break; 2961 2962 sqtd->nextqtd = sc->sc_freeqtds; 2963 sc->sc_freeqtds = sqtd; 2964 } 2965 mutex_exit(&sc->sc_lock); 2966 } 2967 2968 Static void 2969 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2970 { 2971 if (prev) { 2972 prev->nextqtd = sqtd; 2973 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2974 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2975 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2976 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2977 } 2978 } 2979 2980 Static void 2981 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2982 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2983 { 2984 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2985 usb_dma_t *dma = &xfer->ux_dmabuf; 2986 uint16_t flags = xfer->ux_flags; 2987 ehci_soft_qtd_t *sqtd, *prev; 2988 int tog = *toggle; 2989 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2990 int len = length; 2991 2992 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2993 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2994 len, isread, tog); 2995 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2996 0, 0, 0); 2997 2998 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2999 3000 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3001 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3002 EHCI_QTD_SET_CERR(3) 3003 ; 3004 3005 sqtd = prev = NULL; 3006 size_t curoffs = 0; 3007 size_t j = 0; 3008 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3009 sqtd = exfer->ex_sqtds[j++]; 3010 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3011 (uintptr_t)prev, 0); 3012 3013 /* 3014 * The EHCI hardware can handle at most 5 pages and they do 3015 * not have to be contiguous 3016 */ 3017 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3018 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3019 size_t curlen = len; 3020 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3021 /* must use multiple TDs, fill as much as possible. */ 3022 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3023 3024 /* the length must be a multiple of the max size */ 3025 curlen -= curlen % mps; 3026 } 3027 KASSERT(curlen != 0); 3028 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3029 curoffs, 0); 3030 3031 /* Fill the qTD */ 3032 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3033 sqtd->qtd.qtd_status = htole32( 3034 qtdstatus | 3035 EHCI_QTD_SET_BYTES(curlen) | 3036 EHCI_QTD_SET_TOGGLE(tog)); 3037 3038 /* Find number of pages we'll be using, insert dma addresses */ 3039 size_t pages = EHCI_NPAGES(curlen); 3040 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3041 size_t pageoffs = EHCI_PAGE(curoffs); 3042 for (size_t i = 0; i < pages; i++) { 3043 paddr_t a = DMAADDR(dma, 3044 pageoffs + i * EHCI_PAGE_SIZE); 3045 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 3046 /* Cast up to avoid compiler warnings */ 3047 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 3048 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3049 i, pages, 3050 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3051 le32toh(sqtd->qtd.qtd_buffer[i])); 3052 } 3053 /* First buffer pointer requires a page offset to start at */ 3054 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3055 3056 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3057 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3058 3059 sqtd->len = curlen; 3060 3061 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3062 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3063 3064 ehci_append_sqtd(sqtd, prev); 3065 3066 if (((curlen + mps - 1) / mps) & 1) { 3067 tog ^= 1; 3068 } 3069 3070 curoffs += curlen; 3071 len -= curlen; 3072 } 3073 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3074 xfer, length, len, mps, exfer->ex_nsqtd, j); 3075 3076 if (!isread && 3077 (flags & USBD_FORCE_SHORT_XFER) && 3078 length % mps == 0) { 3079 /* Force a 0 length transfer at the end. */ 3080 3081 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3082 exfer->ex_nsqtd); 3083 prev = sqtd; 3084 sqtd = exfer->ex_sqtds[j++]; 3085 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3086 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3087 sqtd->qtd.qtd_status = htole32( 3088 qtdstatus | 3089 EHCI_QTD_SET_BYTES(0) | 3090 EHCI_QTD_SET_TOGGLE(tog)); 3091 3092 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3093 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3094 3095 ehci_append_sqtd(sqtd, prev); 3096 tog ^= 1; 3097 } 3098 3099 *lsqtd = sqtd; 3100 *toggle = tog; 3101 } 3102 3103 Static ehci_soft_itd_t * 3104 ehci_alloc_itd(ehci_softc_t *sc) 3105 { 3106 struct ehci_soft_itd *itd, *freeitd; 3107 usbd_status err; 3108 usb_dma_t dma; 3109 3110 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3111 3112 mutex_enter(&sc->sc_lock); 3113 3114 freeitd = LIST_FIRST(&sc->sc_freeitds); 3115 if (freeitd == NULL) { 3116 DPRINTF("allocating chunk", 0, 0, 0, 0); 3117 mutex_exit(&sc->sc_lock); 3118 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3119 EHCI_PAGE_SIZE, &dma); 3120 3121 if (err) { 3122 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3123 return NULL; 3124 } 3125 mutex_enter(&sc->sc_lock); 3126 3127 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3128 int offs = i * EHCI_ITD_SIZE; 3129 itd = KERNADDR(&dma, offs); 3130 itd->physaddr = DMAADDR(&dma, offs); 3131 itd->dma = dma; 3132 itd->offs = offs; 3133 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3134 } 3135 freeitd = LIST_FIRST(&sc->sc_freeitds); 3136 } 3137 3138 itd = freeitd; 3139 LIST_REMOVE(itd, free_list); 3140 mutex_exit(&sc->sc_lock); 3141 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3142 3143 itd->frame_list.next = NULL; 3144 itd->frame_list.prev = NULL; 3145 itd->xfer_next = NULL; 3146 itd->slot = 0; 3147 3148 return itd; 3149 } 3150 3151 Static ehci_soft_sitd_t * 3152 ehci_alloc_sitd(ehci_softc_t *sc) 3153 { 3154 struct ehci_soft_sitd *sitd, *freesitd; 3155 usbd_status err; 3156 int i, offs; 3157 usb_dma_t dma; 3158 3159 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3160 3161 mutex_enter(&sc->sc_lock); 3162 freesitd = LIST_FIRST(&sc->sc_freesitds); 3163 if (freesitd == NULL) { 3164 DPRINTF("allocating chunk", 0, 0, 0, 0); 3165 mutex_exit(&sc->sc_lock); 3166 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3167 EHCI_PAGE_SIZE, &dma); 3168 3169 if (err) { 3170 DPRINTF("alloc returned %jd", err, 0, 0, 3171 0); 3172 return NULL; 3173 } 3174 3175 mutex_enter(&sc->sc_lock); 3176 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3177 offs = i * EHCI_SITD_SIZE; 3178 sitd = KERNADDR(&dma, offs); 3179 sitd->physaddr = DMAADDR(&dma, offs); 3180 sitd->dma = dma; 3181 sitd->offs = offs; 3182 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3183 } 3184 freesitd = LIST_FIRST(&sc->sc_freesitds); 3185 } 3186 3187 sitd = freesitd; 3188 LIST_REMOVE(sitd, free_list); 3189 mutex_exit(&sc->sc_lock); 3190 3191 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3192 3193 sitd->frame_list.next = NULL; 3194 sitd->frame_list.prev = NULL; 3195 sitd->xfer_next = NULL; 3196 sitd->slot = 0; 3197 3198 return sitd; 3199 } 3200 3201 /****************/ 3202 3203 /* 3204 * Close a reqular pipe. 3205 * Assumes that there are no pending transactions. 3206 */ 3207 Static void 3208 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3209 { 3210 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3211 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3212 ehci_soft_qh_t *sqh = epipe->sqh; 3213 3214 KASSERT(mutex_owned(&sc->sc_lock)); 3215 3216 ehci_rem_qh(sc, sqh, head); 3217 ehci_free_sqh(sc, epipe->sqh); 3218 } 3219 3220 /* 3221 * Cancel or timeout a device request. We have two cases to deal with 3222 * 3223 * 1) A driver wants to stop scheduled or inflight transfers 3224 * 2) A transfer has timed out 3225 * 3226 * have (partially) happened since the hardware runs concurrently. 3227 * 3228 * Transfer state is protected by the bus lock and we set the transfer status 3229 * as soon as either of the above happens (with bus lock held). 3230 * 3231 * Then we arrange for the hardware to tells us that it is not still 3232 * processing the TDs by setting the QH halted bit and wait for the ehci 3233 * door bell 3234 */ 3235 Static void 3236 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3237 { 3238 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3239 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3240 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3241 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3242 ehci_soft_qh_t *sqh = epipe->sqh; 3243 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3244 ehci_physaddr_t cur; 3245 uint32_t qhstatus; 3246 int hit; 3247 3248 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 3249 "invalid status for abort: %d", (int)status); 3250 3251 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3252 3253 KASSERT(mutex_owned(&sc->sc_lock)); 3254 ASSERT_SLEEPABLE(); 3255 3256 if (status == USBD_CANCELLED) { 3257 /* 3258 * We are synchronously aborting. Try to stop the 3259 * callout and task, but if we can't, wait for them to 3260 * complete. 3261 */ 3262 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3263 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 3264 USB_TASKQ_HC, &sc->sc_lock); 3265 } else { 3266 /* Otherwise, we are timing out. */ 3267 KASSERT(status == USBD_TIMEOUT); 3268 } 3269 3270 /* 3271 * The xfer cannot have been cancelled already. It is the 3272 * responsibility of the caller of usbd_abort_pipe not to try 3273 * to abort a pipe multiple times, whether concurrently or 3274 * sequentially. 3275 */ 3276 KASSERT(xfer->ux_status != USBD_CANCELLED); 3277 3278 /* Only the timeout, which runs only once, can time it out. */ 3279 KASSERT(xfer->ux_status != USBD_TIMEOUT); 3280 3281 /* If anyone else beat us, we're done. */ 3282 if (xfer->ux_status != USBD_IN_PROGRESS) 3283 return; 3284 3285 /* We beat everyone else. Claim the status. */ 3286 xfer->ux_status = status; 3287 3288 /* 3289 * If we're dying, skip the hardware action and just notify the 3290 * software that we're done. 3291 */ 3292 if (sc->sc_dying) { 3293 goto dying; 3294 } 3295 3296 /* 3297 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3298 */ 3299 ehci_del_intr_list(sc, exfer); 3300 3301 usb_syncmem(&sqh->dma, 3302 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3303 sizeof(sqh->qh.qh_qtd.qtd_status), 3304 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3305 qhstatus = sqh->qh.qh_qtd.qtd_status; 3306 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3307 usb_syncmem(&sqh->dma, 3308 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3309 sizeof(sqh->qh.qh_qtd.qtd_status), 3310 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3311 3312 if (exfer->ex_type == EX_CTRL) { 3313 fsqtd = exfer->ex_setup; 3314 lsqtd = exfer->ex_status; 3315 } else { 3316 fsqtd = exfer->ex_sqtdstart; 3317 lsqtd = exfer->ex_sqtdend; 3318 } 3319 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3320 usb_syncmem(&sqtd->dma, 3321 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3322 sizeof(sqtd->qtd.qtd_status), 3323 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3324 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3325 usb_syncmem(&sqtd->dma, 3326 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3327 sizeof(sqtd->qtd.qtd_status), 3328 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3329 if (sqtd == lsqtd) 3330 break; 3331 } 3332 3333 /* 3334 * HC Step 2: Wait until we know hardware has finished any possible 3335 * use of the xfer. 3336 */ 3337 ehci_sync_hc(sc); 3338 3339 /* 3340 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3341 * The complication here is that the hardware may have executed 3342 * beyond the xfer we're trying to abort. So as we're scanning 3343 * the TDs of this xfer we check if the hardware points to 3344 * any of them. 3345 */ 3346 3347 usb_syncmem(&sqh->dma, 3348 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3349 sizeof(sqh->qh.qh_curqtd), 3350 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3351 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3352 hit = 0; 3353 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3354 hit |= cur == sqtd->physaddr; 3355 if (sqtd == lsqtd) 3356 break; 3357 } 3358 sqtd = sqtd->nextqtd; 3359 /* Zap curqtd register if hardware pointed inside the xfer. */ 3360 if (hit && sqtd != NULL) { 3361 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3362 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3363 usb_syncmem(&sqh->dma, 3364 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3365 sizeof(sqh->qh.qh_curqtd), 3366 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3367 sqh->qh.qh_qtd.qtd_status = qhstatus; 3368 usb_syncmem(&sqh->dma, 3369 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3370 sizeof(sqh->qh.qh_qtd.qtd_status), 3371 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3372 } else { 3373 DPRINTF("no hit", 0, 0, 0, 0); 3374 usb_syncmem(&sqh->dma, 3375 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3376 sizeof(sqh->qh.qh_curqtd), 3377 BUS_DMASYNC_PREREAD); 3378 } 3379 3380 /* 3381 * Final step: Notify completion to waiting xfers. 3382 */ 3383 dying: 3384 #ifdef DIAGNOSTIC 3385 exfer->ex_isdone = true; 3386 #endif 3387 usb_transfer_complete(xfer); 3388 DPRINTFN(14, "end", 0, 0, 0, 0); 3389 3390 KASSERT(mutex_owned(&sc->sc_lock)); 3391 } 3392 3393 Static void 3394 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3395 { 3396 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3397 ehci_isoc_trans_t trans_status; 3398 struct ehci_xfer *exfer; 3399 ehci_softc_t *sc; 3400 struct ehci_soft_itd *itd; 3401 struct ehci_soft_sitd *sitd; 3402 int i; 3403 3404 KASSERTMSG(status == USBD_CANCELLED, 3405 "invalid status for abort: %d", (int)status); 3406 3407 exfer = EHCI_XFER2EXFER(xfer); 3408 sc = EHCI_XFER2SC(xfer); 3409 3410 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3411 (uintptr_t)xfer->ux_pipe, 0, 0); 3412 3413 KASSERT(mutex_owned(&sc->sc_lock)); 3414 ASSERT_SLEEPABLE(); 3415 3416 /* No timeout or task here. */ 3417 3418 /* 3419 * The xfer cannot have been cancelled already. It is the 3420 * responsibility of the caller of usbd_abort_pipe not to try 3421 * to abort a pipe multiple times, whether concurrently or 3422 * sequentially. 3423 */ 3424 KASSERT(xfer->ux_status != USBD_CANCELLED); 3425 3426 /* If anyone else beat us, we're done. */ 3427 if (xfer->ux_status != USBD_IN_PROGRESS) 3428 return; 3429 3430 /* We beat everyone else. Claim the status. */ 3431 xfer->ux_status = status; 3432 3433 /* 3434 * If we're dying, skip the hardware action and just notify the 3435 * software that we're done. 3436 */ 3437 if (sc->sc_dying) { 3438 goto dying; 3439 } 3440 3441 /* 3442 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3443 */ 3444 ehci_del_intr_list(sc, exfer); 3445 3446 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3447 for (itd = exfer->ex_itdstart; itd != NULL; 3448 itd = itd->xfer_next) { 3449 usb_syncmem(&itd->dma, 3450 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3451 sizeof(itd->itd.itd_ctl), 3452 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3453 3454 for (i = 0; i < 8; i++) { 3455 trans_status = le32toh(itd->itd.itd_ctl[i]); 3456 trans_status &= ~EHCI_ITD_ACTIVE; 3457 itd->itd.itd_ctl[i] = htole32(trans_status); 3458 } 3459 3460 usb_syncmem(&itd->dma, 3461 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3462 sizeof(itd->itd.itd_ctl), 3463 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3464 } 3465 } else { 3466 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3467 sitd = sitd->xfer_next) { 3468 usb_syncmem(&sitd->dma, 3469 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3470 sizeof(sitd->sitd.sitd_buffer), 3471 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3472 3473 trans_status = le32toh(sitd->sitd.sitd_trans); 3474 trans_status &= ~EHCI_SITD_ACTIVE; 3475 sitd->sitd.sitd_trans = htole32(trans_status); 3476 3477 usb_syncmem(&sitd->dma, 3478 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3479 sizeof(sitd->sitd.sitd_buffer), 3480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3481 } 3482 } 3483 3484 dying: 3485 #ifdef DIAGNOSTIC 3486 exfer->ex_isdone = true; 3487 #endif 3488 usb_transfer_complete(xfer); 3489 DPRINTFN(14, "end", 0, 0, 0, 0); 3490 3491 KASSERT(mutex_owned(&sc->sc_lock)); 3492 } 3493 3494 Static void 3495 ehci_timeout(void *addr) 3496 { 3497 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3498 struct usbd_xfer *xfer = addr; 3499 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3500 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3501 3502 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3503 #ifdef EHCI_DEBUG 3504 if (ehcidebug >= 2) { 3505 struct usbd_pipe *pipe = xfer->ux_pipe; 3506 usbd_dump_pipe(pipe); 3507 } 3508 #endif 3509 3510 mutex_enter(&sc->sc_lock); 3511 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 3512 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3513 mutex_exit(&sc->sc_lock); 3514 } 3515 3516 Static void 3517 ehci_timeout_task(void *addr) 3518 { 3519 struct usbd_xfer *xfer = addr; 3520 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3521 3522 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3523 3524 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3525 3526 mutex_enter(&sc->sc_lock); 3527 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3528 mutex_exit(&sc->sc_lock); 3529 } 3530 3531 /************************/ 3532 3533 Static int 3534 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3535 { 3536 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3537 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3538 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3539 usb_device_request_t *req = &xfer->ux_request; 3540 ehci_soft_qtd_t *setup, *status, *next; 3541 int isread = req->bmRequestType & UT_READ; 3542 int len = xfer->ux_bufsize; 3543 int err; 3544 3545 exfer->ex_type = EX_CTRL; 3546 exfer->ex_status = NULL; 3547 exfer->ex_data = NULL; 3548 exfer->ex_setup = ehci_alloc_sqtd(sc); 3549 if (exfer->ex_setup == NULL) { 3550 err = ENOMEM; 3551 goto bad1; 3552 } 3553 exfer->ex_status = ehci_alloc_sqtd(sc); 3554 if (exfer->ex_status == NULL) { 3555 err = ENOMEM; 3556 goto bad2; 3557 } 3558 setup = exfer->ex_setup; 3559 status = exfer->ex_status; 3560 exfer->ex_nsqtd = 0; 3561 next = status; 3562 /* Set up data transaction */ 3563 if (len != 0) { 3564 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3565 &exfer->ex_data); 3566 if (err) 3567 goto bad3; 3568 next = exfer->ex_data; 3569 } 3570 3571 /* Clear toggle */ 3572 setup->qtd.qtd_status = htole32( 3573 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3574 EHCI_QTD_SET_TOGGLE(0) | 3575 EHCI_QTD_SET_BYTES(sizeof(*req)) 3576 ); 3577 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3578 setup->qtd.qtd_buffer_hi[0] = 0; 3579 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3580 setup->nextqtd = next; 3581 setup->xfer = xfer; 3582 setup->len = sizeof(*req); 3583 3584 status->qtd.qtd_status = htole32( 3585 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3586 EHCI_QTD_SET_TOGGLE(1) | 3587 EHCI_QTD_IOC 3588 ); 3589 status->qtd.qtd_buffer[0] = 0; 3590 status->qtd.qtd_buffer_hi[0] = 0; 3591 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3592 status->nextqtd = NULL; 3593 status->xfer = xfer; 3594 status->len = 0; 3595 3596 return 0; 3597 bad3: 3598 ehci_free_sqtd(sc, exfer->ex_status); 3599 bad2: 3600 ehci_free_sqtd(sc, exfer->ex_setup); 3601 bad1: 3602 return err; 3603 } 3604 3605 Static void 3606 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3607 { 3608 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3609 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3610 3611 KASSERT(ex->ex_type == EX_CTRL); 3612 3613 ehci_free_sqtd(sc, ex->ex_setup); 3614 ehci_free_sqtd(sc, ex->ex_status); 3615 ehci_free_sqtds(sc, ex); 3616 if (ex->ex_nsqtd) 3617 kmem_free(ex->ex_sqtds, 3618 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3619 } 3620 3621 Static usbd_status 3622 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3623 { 3624 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3625 usbd_status err; 3626 3627 /* Insert last in queue. */ 3628 mutex_enter(&sc->sc_lock); 3629 err = usb_insert_transfer(xfer); 3630 mutex_exit(&sc->sc_lock); 3631 if (err) 3632 return err; 3633 3634 /* Pipe isn't running, start first */ 3635 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3636 } 3637 3638 Static usbd_status 3639 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3640 { 3641 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3642 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3643 usb_device_request_t *req = &xfer->ux_request; 3644 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3645 ehci_soft_qtd_t *setup, *status, *next; 3646 ehci_soft_qh_t *sqh; 3647 const bool polling = sc->sc_bus.ub_usepolling; 3648 3649 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3650 3651 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3652 3653 if (sc->sc_dying) 3654 return USBD_IOERROR; 3655 3656 const int isread = req->bmRequestType & UT_READ; 3657 const int len = UGETW(req->wLength); 3658 3659 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3660 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3661 UGETW(req->wIndex)); 3662 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3663 len, epipe->pipe.up_dev->ud_addr, 3664 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3665 3666 sqh = epipe->sqh; 3667 3668 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3669 "address QH %" __PRIuBIT " pipe %d\n", 3670 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3671 epipe->pipe.up_dev->ud_addr); 3672 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3673 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3674 "MPS QH %" __PRIuBIT " pipe %d\n", 3675 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3676 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3677 3678 setup = exfer->ex_setup; 3679 status = exfer->ex_status; 3680 3681 DPRINTF("setup %#jx status %#jx data %#jx", 3682 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3683 KASSERTMSG(setup != NULL && status != NULL, 3684 "Failed memory allocation, setup %p status %p", 3685 setup, status); 3686 3687 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3688 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3689 3690 /* Clear toggle */ 3691 setup->qtd.qtd_status &= ~htole32( 3692 EHCI_QTD_STATUS_MASK | 3693 EHCI_QTD_BYTES_MASK | 3694 EHCI_QTD_TOGGLE_MASK | 3695 EHCI_QTD_CERR_MASK 3696 ); 3697 setup->qtd.qtd_status |= htole32( 3698 EHCI_QTD_ACTIVE | 3699 EHCI_QTD_SET_CERR(3) | 3700 EHCI_QTD_SET_TOGGLE(0) | 3701 EHCI_QTD_SET_BYTES(sizeof(*req)) 3702 ); 3703 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3704 setup->qtd.qtd_buffer_hi[0] = 0; 3705 3706 next = status; 3707 status->qtd.qtd_status &= ~htole32( 3708 EHCI_QTD_STATUS_MASK | 3709 EHCI_QTD_PID_MASK | 3710 EHCI_QTD_BYTES_MASK | 3711 EHCI_QTD_TOGGLE_MASK | 3712 EHCI_QTD_CERR_MASK 3713 ); 3714 status->qtd.qtd_status |= htole32( 3715 EHCI_QTD_ACTIVE | 3716 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3717 EHCI_QTD_SET_CERR(3) | 3718 EHCI_QTD_SET_TOGGLE(1) | 3719 EHCI_QTD_SET_BYTES(0) | 3720 EHCI_QTD_IOC 3721 ); 3722 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3723 3724 KASSERT(exfer->ex_isdone); 3725 #ifdef DIAGNOSTIC 3726 exfer->ex_isdone = false; 3727 #endif 3728 3729 /* Set up data transaction */ 3730 if (len != 0) { 3731 ehci_soft_qtd_t *end; 3732 3733 /* Start toggle at 1. */ 3734 int toggle = 1; 3735 next = exfer->ex_data; 3736 KASSERTMSG(next != NULL, "Failed memory allocation"); 3737 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3738 end->nextqtd = status; 3739 end->qtd.qtd_next = end->qtd.qtd_altnext = 3740 htole32(status->physaddr); 3741 3742 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3743 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3744 3745 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3746 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3747 } 3748 3749 setup->nextqtd = next; 3750 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3751 3752 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3753 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3754 3755 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3756 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3757 3758 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3759 3760 #ifdef EHCI_DEBUG 3761 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3762 ehci_dump_sqh(sqh); 3763 ehci_dump_sqtds(setup); 3764 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3765 #endif 3766 3767 if (!polling) 3768 mutex_enter(&sc->sc_lock); 3769 3770 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3771 ehci_set_qh_qtd(sqh, setup); 3772 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3773 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3774 ehci_timeout, xfer); 3775 } 3776 ehci_add_intr_list(sc, exfer); 3777 xfer->ux_status = USBD_IN_PROGRESS; 3778 if (!polling) 3779 mutex_exit(&sc->sc_lock); 3780 3781 #if 0 3782 #ifdef EHCI_DEBUG 3783 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3784 // delay(10000); 3785 ehci_dump_regs(sc); 3786 ehci_dump_sqh(sc->sc_async_head); 3787 ehci_dump_sqh(sqh); 3788 ehci_dump_sqtds(setup); 3789 #endif 3790 #endif 3791 3792 return USBD_IN_PROGRESS; 3793 } 3794 3795 Static void 3796 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3797 { 3798 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3799 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3800 usb_device_request_t *req = &xfer->ux_request; 3801 int len = UGETW(req->wLength); 3802 int rd = req->bmRequestType & UT_READ; 3803 3804 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3805 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3806 3807 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3808 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3809 3810 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3811 BUS_DMASYNC_POSTWRITE); 3812 if (len) 3813 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3814 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3815 3816 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3817 } 3818 3819 /* Abort a device control request. */ 3820 Static void 3821 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3822 { 3823 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3824 3825 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3826 ehci_abort_xfer(xfer, USBD_CANCELLED); 3827 } 3828 3829 /* Close a device control pipe. */ 3830 Static void 3831 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3832 { 3833 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3834 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3835 3836 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3837 3838 KASSERT(mutex_owned(&sc->sc_lock)); 3839 3840 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3841 3842 ehci_close_pipe(pipe, sc->sc_async_head); 3843 } 3844 3845 /* 3846 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3847 * qTD status, or miss signalling occasionally under heavy load. If the host 3848 * machine is too fast, we we can miss transaction completion - when we scan 3849 * the active list the transaction still seems to be active. This generally 3850 * exhibits itself as a umass stall that never recovers. 3851 * 3852 * We work around this behaviour by setting up this callback after any softintr 3853 * that completes with transactions still pending, giving us another chance to 3854 * check for completion after the writeback has taken place. 3855 */ 3856 Static void 3857 ehci_intrlist_timeout(void *arg) 3858 { 3859 ehci_softc_t *sc = arg; 3860 3861 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3862 3863 usb_schedsoftintr(&sc->sc_bus); 3864 } 3865 3866 /************************/ 3867 3868 Static int 3869 ehci_device_bulk_init(struct usbd_xfer *xfer) 3870 { 3871 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3872 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3873 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3874 int endpt = ed->bEndpointAddress; 3875 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3876 int len = xfer->ux_bufsize; 3877 int err = 0; 3878 3879 exfer->ex_type = EX_BULK; 3880 exfer->ex_nsqtd = 0; 3881 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3882 &exfer->ex_sqtdstart); 3883 3884 return err; 3885 } 3886 3887 Static void 3888 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3889 { 3890 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3891 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3892 3893 KASSERT(ex->ex_type == EX_BULK); 3894 3895 ehci_free_sqtds(sc, ex); 3896 if (ex->ex_nsqtd) 3897 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3898 } 3899 3900 Static usbd_status 3901 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3902 { 3903 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3904 usbd_status err; 3905 3906 /* Insert last in queue. */ 3907 mutex_enter(&sc->sc_lock); 3908 err = usb_insert_transfer(xfer); 3909 mutex_exit(&sc->sc_lock); 3910 if (err) 3911 return err; 3912 3913 /* Pipe isn't running, start first */ 3914 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3915 } 3916 3917 Static usbd_status 3918 ehci_device_bulk_start(struct usbd_xfer *xfer) 3919 { 3920 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3921 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3922 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3923 ehci_soft_qh_t *sqh; 3924 ehci_soft_qtd_t *end; 3925 int len, isread, endpt; 3926 const bool polling = sc->sc_bus.ub_usepolling; 3927 3928 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3929 3930 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3931 xfer->ux_flags, 0); 3932 3933 if (sc->sc_dying) 3934 return USBD_IOERROR; 3935 3936 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3937 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3938 3939 len = xfer->ux_length; 3940 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3941 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3942 sqh = epipe->sqh; 3943 3944 KASSERT(exfer->ex_isdone); 3945 #ifdef DIAGNOSTIC 3946 exfer->ex_isdone = false; 3947 #endif 3948 3949 /* Take lock here to protect nexttoggle */ 3950 if (!polling) 3951 mutex_enter(&sc->sc_lock); 3952 3953 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3954 3955 exfer->ex_sqtdend = end; 3956 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3957 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3958 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3959 3960 #ifdef EHCI_DEBUG 3961 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3962 ehci_dump_sqh(sqh); 3963 ehci_dump_sqtds(exfer->ex_sqtdstart); 3964 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3965 #endif 3966 3967 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3968 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3969 3970 /* also does usb_syncmem(sqh) */ 3971 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3972 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3973 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3974 ehci_timeout, xfer); 3975 } 3976 ehci_add_intr_list(sc, exfer); 3977 xfer->ux_status = USBD_IN_PROGRESS; 3978 if (!polling) 3979 mutex_exit(&sc->sc_lock); 3980 3981 #if 0 3982 #ifdef EHCI_DEBUG 3983 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3984 // delay(10000); 3985 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3986 ehci_dump_regs(sc); 3987 #if 0 3988 printf("async_head:\n"); 3989 ehci_dump_sqh(sc->sc_async_head); 3990 #endif 3991 DPRINTF("sqh:", 0, 0, 0, 0); 3992 ehci_dump_sqh(sqh); 3993 ehci_dump_sqtds(exfer->ex_sqtdstart); 3994 #endif 3995 #endif 3996 3997 return USBD_IN_PROGRESS; 3998 } 3999 4000 Static void 4001 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4002 { 4003 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4004 4005 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 4006 ehci_abort_xfer(xfer, USBD_CANCELLED); 4007 } 4008 4009 /* 4010 * Close a device bulk pipe. 4011 */ 4012 Static void 4013 ehci_device_bulk_close(struct usbd_pipe *pipe) 4014 { 4015 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4016 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4017 4018 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4019 4020 KASSERT(mutex_owned(&sc->sc_lock)); 4021 4022 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4023 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4024 ehci_close_pipe(pipe, sc->sc_async_head); 4025 } 4026 4027 Static void 4028 ehci_device_bulk_done(struct usbd_xfer *xfer) 4029 { 4030 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4031 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4032 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4033 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4034 4035 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4036 4037 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4038 4039 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4040 4041 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4042 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4043 4044 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4045 } 4046 4047 /************************/ 4048 4049 Static usbd_status 4050 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4051 { 4052 struct ehci_soft_islot *isp; 4053 int islot, lev; 4054 4055 /* Find a poll rate that is large enough. */ 4056 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4057 if (EHCI_ILEV_IVAL(lev) <= ival) 4058 break; 4059 4060 /* Pick an interrupt slot at the right level. */ 4061 /* XXX could do better than picking at random */ 4062 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4063 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4064 4065 sqh->islot = islot; 4066 isp = &sc->sc_islots[islot]; 4067 mutex_enter(&sc->sc_lock); 4068 ehci_add_qh(sc, sqh, isp->sqh); 4069 mutex_exit(&sc->sc_lock); 4070 4071 return USBD_NORMAL_COMPLETION; 4072 } 4073 4074 4075 Static int 4076 ehci_device_intr_init(struct usbd_xfer *xfer) 4077 { 4078 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4079 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4080 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4081 int endpt = ed->bEndpointAddress; 4082 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4083 int len = xfer->ux_bufsize; 4084 int err; 4085 4086 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4087 4088 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4089 xfer->ux_flags, 0); 4090 4091 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4092 KASSERT(len != 0); 4093 4094 exfer->ex_type = EX_INTR; 4095 exfer->ex_nsqtd = 0; 4096 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4097 &exfer->ex_sqtdstart); 4098 4099 return err; 4100 } 4101 4102 Static void 4103 ehci_device_intr_fini(struct usbd_xfer *xfer) 4104 { 4105 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4106 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4107 4108 KASSERT(ex->ex_type == EX_INTR); 4109 4110 ehci_free_sqtds(sc, ex); 4111 if (ex->ex_nsqtd) 4112 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4113 } 4114 4115 Static usbd_status 4116 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4117 { 4118 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4119 usbd_status err; 4120 4121 /* Insert last in queue. */ 4122 mutex_enter(&sc->sc_lock); 4123 err = usb_insert_transfer(xfer); 4124 mutex_exit(&sc->sc_lock); 4125 if (err) 4126 return err; 4127 4128 /* 4129 * Pipe isn't running (otherwise err would be USBD_INPROG), 4130 * so start it first. 4131 */ 4132 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4133 } 4134 4135 Static usbd_status 4136 ehci_device_intr_start(struct usbd_xfer *xfer) 4137 { 4138 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4139 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4140 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4141 ehci_soft_qtd_t *end; 4142 ehci_soft_qh_t *sqh; 4143 int len, isread, endpt; 4144 const bool polling = sc->sc_bus.ub_usepolling; 4145 4146 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4147 4148 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4149 xfer->ux_flags, 0); 4150 4151 if (sc->sc_dying) 4152 return USBD_IOERROR; 4153 4154 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4155 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4156 4157 len = xfer->ux_length; 4158 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4159 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4160 sqh = epipe->sqh; 4161 4162 KASSERT(exfer->ex_isdone); 4163 #ifdef DIAGNOSTIC 4164 exfer->ex_isdone = false; 4165 #endif 4166 4167 /* Take lock to protect nexttoggle */ 4168 if (!polling) 4169 mutex_enter(&sc->sc_lock); 4170 4171 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4172 4173 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4174 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4175 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4176 exfer->ex_sqtdend = end; 4177 4178 #ifdef EHCI_DEBUG 4179 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4180 ehci_dump_sqh(sqh); 4181 ehci_dump_sqtds(exfer->ex_sqtdstart); 4182 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4183 #endif 4184 4185 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4186 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4187 4188 /* also does usb_syncmem(sqh) */ 4189 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4190 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4191 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4192 ehci_timeout, xfer); 4193 } 4194 ehci_add_intr_list(sc, exfer); 4195 xfer->ux_status = USBD_IN_PROGRESS; 4196 if (!polling) 4197 mutex_exit(&sc->sc_lock); 4198 4199 #if 0 4200 #ifdef EHCI_DEBUG 4201 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4202 // delay(10000); 4203 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4204 ehci_dump_regs(sc); 4205 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4206 ehci_dump_sqh(sqh); 4207 ehci_dump_sqtds(exfer->ex_sqtdstart); 4208 #endif 4209 #endif 4210 4211 return USBD_IN_PROGRESS; 4212 } 4213 4214 Static void 4215 ehci_device_intr_abort(struct usbd_xfer *xfer) 4216 { 4217 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4218 4219 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4220 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4221 4222 /* 4223 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4224 * async doorbell. That's dependent on the async list, wheras 4225 * intr xfers are periodic, should not use this? 4226 */ 4227 ehci_abort_xfer(xfer, USBD_CANCELLED); 4228 } 4229 4230 Static void 4231 ehci_device_intr_close(struct usbd_pipe *pipe) 4232 { 4233 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4234 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4235 struct ehci_soft_islot *isp; 4236 4237 KASSERT(mutex_owned(&sc->sc_lock)); 4238 4239 isp = &sc->sc_islots[epipe->sqh->islot]; 4240 ehci_close_pipe(pipe, isp->sqh); 4241 } 4242 4243 Static void 4244 ehci_device_intr_done(struct usbd_xfer *xfer) 4245 { 4246 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4247 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4248 int isread, endpt; 4249 4250 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4251 4252 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4253 4254 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4255 4256 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4257 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4258 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4259 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4260 } 4261 4262 /************************/ 4263 Static int 4264 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4265 { 4266 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4267 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4268 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4269 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4270 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4271 int i, k, frames; 4272 u_int huba, dir; 4273 int err; 4274 4275 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4276 4277 start = NULL; 4278 sitd = NULL; 4279 4280 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4281 xfer->ux_flags, 0); 4282 4283 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4284 KASSERT(xfer->ux_nframes != 0); 4285 KASSERT(exfer->ex_isdone); 4286 4287 exfer->ex_type = EX_FS_ISOC; 4288 /* 4289 * Step 1: Allocate and initialize sitds. 4290 */ 4291 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4292 if (i > 16 || i == 0) { 4293 /* Spec page 271 says intervals > 16 are invalid */ 4294 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4295 4296 return EINVAL; 4297 } 4298 4299 frames = xfer->ux_nframes; 4300 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4301 sitd = ehci_alloc_sitd(sc); 4302 if (sitd == NULL) { 4303 err = ENOMEM; 4304 goto fail; 4305 } 4306 4307 if (prev) 4308 prev->xfer_next = sitd; 4309 else 4310 start = sitd; 4311 4312 huba = dev->ud_myhsport->up_parent->ud_addr; 4313 4314 #if 0 4315 if (sc->sc_flags & EHCIF_FREESCALE) { 4316 // Set hub address to 0 if embedded TT is used. 4317 if (huba == sc->sc_addr) 4318 huba = 0; 4319 } 4320 #endif 4321 4322 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4323 dir = UE_GET_DIR(k) ? 1 : 0; 4324 sitd->sitd.sitd_endp = 4325 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4326 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4327 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4328 EHCI_SITD_SET_HUBA(huba) | 4329 EHCI_SITD_SET_DIR(dir)); 4330 4331 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4332 } /* End of frame */ 4333 4334 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4335 4336 stop = sitd; 4337 stop->xfer_next = NULL; 4338 exfer->ex_sitdstart = start; 4339 exfer->ex_sitdend = stop; 4340 4341 return 0; 4342 4343 fail: 4344 mutex_enter(&sc->sc_lock); 4345 ehci_soft_sitd_t *next; 4346 for (sitd = start; sitd; sitd = next) { 4347 next = sitd->xfer_next; 4348 ehci_free_sitd_locked(sc, sitd); 4349 } 4350 mutex_exit(&sc->sc_lock); 4351 4352 return err; 4353 } 4354 4355 Static void 4356 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4357 { 4358 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4359 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4360 4361 KASSERT(ex->ex_type == EX_FS_ISOC); 4362 4363 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4364 } 4365 4366 Static usbd_status 4367 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4368 { 4369 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4370 usbd_status __diagused err; 4371 4372 mutex_enter(&sc->sc_lock); 4373 err = usb_insert_transfer(xfer); 4374 mutex_exit(&sc->sc_lock); 4375 4376 KASSERT(err == USBD_NORMAL_COMPLETION); 4377 4378 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4379 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4380 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4381 ehci_soft_sitd_t *sitd; 4382 usb_dma_t *dma_buf; 4383 int i, j, k, frames; 4384 int offs, total_length; 4385 int frindex; 4386 u_int dir; 4387 4388 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4389 4390 sitd = NULL; 4391 total_length = 0; 4392 4393 4394 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4395 xfer->ux_flags, 0); 4396 4397 if (sc->sc_dying) 4398 return USBD_IOERROR; 4399 4400 /* 4401 * To avoid complication, don't allow a request right now that'll span 4402 * the entire frame table. To within 4 frames, to allow some leeway 4403 * on either side of where the hc currently is. 4404 */ 4405 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4406 xfer->ux_nframes >= sc->sc_flsize - 4) { 4407 printf("ehci: isoc descriptor requested that spans the entire" 4408 "frametable, too many frames\n"); 4409 return USBD_INVAL; 4410 } 4411 4412 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4413 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4414 KASSERT(exfer->ex_isdone); 4415 #ifdef DIAGNOSTIC 4416 exfer->ex_isdone = false; 4417 #endif 4418 4419 /* 4420 * Step 1: Initialize sitds. 4421 */ 4422 4423 frames = xfer->ux_nframes; 4424 dma_buf = &xfer->ux_dmabuf; 4425 offs = 0; 4426 4427 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4428 i++, sitd = sitd->xfer_next) { 4429 KASSERT(sitd != NULL); 4430 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4431 4432 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4433 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4434 4435 /* Set page0 index and offset - TP and T-offset are set below */ 4436 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4437 4438 total_length += xfer->ux_frlengths[i]; 4439 offs += xfer->ux_frlengths[i]; 4440 4441 sitd->sitd.sitd_buffer[1] = 4442 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4443 4444 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4445 4446 #if 0 4447 if (sc->sc_flags & EHCIF_FREESCALE) { 4448 // Set hub address to 0 if embedded TT is used. 4449 if (huba == sc->sc_addr) 4450 huba = 0; 4451 } 4452 #endif 4453 4454 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4455 dir = UE_GET_DIR(k) ? 1 : 0; 4456 KASSERT(sitd->sitd.sitd_endp == htole32( 4457 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4458 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4459 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4460 EHCI_SITD_SET_HUBA(huba) | 4461 EHCI_SITD_SET_DIR(dir))); 4462 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4463 4464 uint8_t sa = 0; 4465 uint8_t sb = 0; 4466 u_int temp, tlen; 4467 4468 if (dir == 0) { /* OUT */ 4469 temp = 0; 4470 tlen = xfer->ux_frlengths[i]; 4471 if (tlen <= 188) { 4472 temp |= 1; /* T-count = 1, TP = ALL */ 4473 tlen = 1; 4474 } else { 4475 tlen += 187; 4476 tlen /= 188; 4477 temp |= tlen; /* T-count = [1..6] */ 4478 temp |= 8; /* TP = Begin */ 4479 } 4480 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4481 4482 tlen += sa; 4483 4484 if (tlen >= 8) { 4485 sb = 0; 4486 } else { 4487 sb = (1 << tlen); 4488 } 4489 4490 sa = (1 << sa); 4491 sa = (sb - sa) & 0x3F; 4492 sb = 0; 4493 } else { 4494 sb = (-(4 << sa)) & 0xFE; 4495 sa = (1 << sa) & 0x3F; 4496 sa = 0x01; 4497 sb = 0xfc; 4498 } 4499 4500 sitd->sitd.sitd_sched = htole32( 4501 EHCI_SITD_SET_SMASK(sa) | 4502 EHCI_SITD_SET_CMASK(sb) 4503 ); 4504 4505 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4507 } /* End of frame */ 4508 4509 sitd = exfer->ex_sitdend; 4510 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4511 4512 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4513 sizeof(sitd->sitd.sitd_trans), 4514 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4515 4516 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4517 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4518 4519 /* 4520 * Part 2: Transfer descriptors have now been set up, now they must 4521 * be scheduled into the periodic frame list. Erk. Not wanting to 4522 * complicate matters, transfer is denied if the transfer spans 4523 * more than the period frame list. 4524 */ 4525 4526 mutex_enter(&sc->sc_lock); 4527 4528 /* Start inserting frames */ 4529 if (epipe->isoc.cur_xfers > 0) { 4530 frindex = epipe->isoc.next_frame; 4531 } else { 4532 frindex = EOREAD4(sc, EHCI_FRINDEX); 4533 frindex = frindex >> 3; /* Erase microframe index */ 4534 frindex += 2; 4535 } 4536 4537 if (frindex >= sc->sc_flsize) 4538 frindex &= (sc->sc_flsize - 1); 4539 4540 /* Whats the frame interval? */ 4541 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4542 4543 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4544 j++, sitd = sitd->xfer_next) { 4545 KASSERT(sitd); 4546 4547 usb_syncmem(&sc->sc_fldma, 4548 sizeof(ehci_link_t) * frindex, 4549 sizeof(ehci_link_t), 4550 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4551 4552 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4553 if (sitd->sitd.sitd_next == 0) 4554 /* 4555 * FIXME: frindex table gets initialized to NULL 4556 * or EHCI_NULL? 4557 */ 4558 sitd->sitd.sitd_next = EHCI_NULL; 4559 4560 usb_syncmem(&sitd->dma, 4561 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4562 sizeof(ehci_sitd_t), 4563 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4564 4565 sc->sc_flist[frindex] = 4566 htole32(EHCI_LINK_SITD | sitd->physaddr); 4567 4568 usb_syncmem(&sc->sc_fldma, 4569 sizeof(ehci_link_t) * frindex, 4570 sizeof(ehci_link_t), 4571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4572 4573 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4574 sc->sc_softsitds[frindex] = sitd; 4575 if (sitd->frame_list.next != NULL) 4576 sitd->frame_list.next->frame_list.prev = sitd; 4577 sitd->slot = frindex; 4578 sitd->frame_list.prev = NULL; 4579 4580 frindex += i; 4581 if (frindex >= sc->sc_flsize) 4582 frindex -= sc->sc_flsize; 4583 } 4584 4585 epipe->isoc.cur_xfers++; 4586 epipe->isoc.next_frame = frindex; 4587 4588 ehci_add_intr_list(sc, exfer); 4589 xfer->ux_status = USBD_IN_PROGRESS; 4590 mutex_exit(&sc->sc_lock); 4591 4592 return USBD_IN_PROGRESS; 4593 } 4594 4595 Static void 4596 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4597 { 4598 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4599 4600 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4601 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4602 } 4603 4604 Static void 4605 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4606 { 4607 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4608 4609 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4610 } 4611 4612 Static void 4613 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4614 { 4615 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4616 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4617 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4618 4619 KASSERT(mutex_owned(&sc->sc_lock)); 4620 4621 epipe->isoc.cur_xfers--; 4622 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4623 4624 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4625 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4626 } 4627 4628 4629 /************************/ 4630 4631 4632 Static int 4633 ehci_device_isoc_init(struct usbd_xfer *xfer) 4634 { 4635 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4636 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4637 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4638 ehci_soft_itd_t *itd, *prev, *start, *stop; 4639 int i, j, k; 4640 int frames, ufrperframe; 4641 int err; 4642 4643 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4644 4645 start = NULL; 4646 prev = NULL; 4647 itd = NULL; 4648 4649 KASSERT(xfer->ux_nframes != 0); 4650 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4651 KASSERT(exfer->ex_isdone); 4652 4653 exfer->ex_type = EX_ISOC; 4654 4655 /* 4656 * Step 1: Allocate and initialize itds, how many do we need? 4657 * One per transfer if interval >= 8 microframes, less if we use 4658 * multiple microframes per frame. 4659 */ 4660 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4661 if (i > 16 || i == 0) { 4662 /* Spec page 271 says intervals > 16 are invalid */ 4663 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4664 return USBD_INVAL; 4665 } 4666 4667 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4668 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4669 4670 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4671 itd = ehci_alloc_itd(sc); 4672 if (itd == NULL) { 4673 err = ENOMEM; 4674 goto fail; 4675 } 4676 4677 if (prev != NULL) { 4678 /* Maybe not as it's updated by the scheduling? */ 4679 prev->itd.itd_next = 4680 htole32(itd->physaddr | EHCI_LINK_ITD); 4681 4682 prev->xfer_next = itd; 4683 } else { 4684 start = itd; 4685 } 4686 4687 /* 4688 * Other special values 4689 */ 4690 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4691 itd->itd.itd_bufr[0] = htole32( 4692 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4693 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4694 4695 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4696 ? 1 : 0; 4697 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4698 itd->itd.itd_bufr[1] |= htole32( 4699 EHCI_ITD_SET_DIR(k) | 4700 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4701 4702 /* FIXME: handle invalid trans - should be done in openpipe */ 4703 itd->itd.itd_bufr[2] |= 4704 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4705 } /* End of frame */ 4706 4707 stop = itd; 4708 stop->xfer_next = NULL; 4709 4710 exfer->ex_itdstart = start; 4711 exfer->ex_itdend = stop; 4712 4713 return 0; 4714 fail: 4715 mutex_enter(&sc->sc_lock); 4716 ehci_soft_itd_t *next; 4717 for (itd = start; itd; itd = next) { 4718 next = itd->xfer_next; 4719 ehci_free_itd_locked(sc, itd); 4720 } 4721 mutex_exit(&sc->sc_lock); 4722 4723 return err; 4724 4725 } 4726 4727 Static void 4728 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4729 { 4730 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4731 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4732 4733 KASSERT(ex->ex_type == EX_ISOC); 4734 4735 ehci_free_itd_chain(sc, ex->ex_itdstart); 4736 } 4737 4738 Static usbd_status 4739 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4740 { 4741 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4742 usbd_status __diagused err; 4743 4744 mutex_enter(&sc->sc_lock); 4745 err = usb_insert_transfer(xfer); 4746 mutex_exit(&sc->sc_lock); 4747 4748 KASSERT(err == USBD_NORMAL_COMPLETION); 4749 4750 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4751 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4752 ehci_soft_itd_t *itd, *prev; 4753 usb_dma_t *dma_buf; 4754 int i, j; 4755 int frames, uframes, ufrperframe; 4756 int trans_count, offs, total_length; 4757 int frindex; 4758 4759 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4760 4761 prev = NULL; 4762 itd = NULL; 4763 trans_count = 0; 4764 total_length = 0; 4765 4766 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4767 4768 if (sc->sc_dying) 4769 return USBD_IOERROR; 4770 4771 /* 4772 * To avoid complication, don't allow a request right now that'll span 4773 * the entire frame table. To within 4 frames, to allow some leeway 4774 * on either side of where the hc currently is. 4775 */ 4776 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4777 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4778 DPRINTF( 4779 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4780 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4781 return USBD_INVAL; 4782 } 4783 4784 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4785 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4786 KASSERT(exfer->ex_isdone); 4787 #ifdef DIAGNOSTIC 4788 exfer->ex_isdone = false; 4789 #endif 4790 4791 /* 4792 * Step 1: Re-Initialize itds 4793 */ 4794 4795 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4796 if (i > 16 || i == 0) { 4797 /* Spec page 271 says intervals > 16 are invalid */ 4798 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4799 return USBD_INVAL; 4800 } 4801 4802 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4803 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4804 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4805 4806 if (frames == 0) { 4807 DPRINTF("frames == 0", 0, 0, 0, 0); 4808 return USBD_INVAL; 4809 } 4810 4811 dma_buf = &xfer->ux_dmabuf; 4812 offs = 0; 4813 4814 itd = exfer->ex_itdstart; 4815 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4816 int froffs = offs; 4817 4818 if (prev != NULL) { 4819 prev->itd.itd_next = 4820 htole32(itd->physaddr | EHCI_LINK_ITD); 4821 usb_syncmem(&prev->dma, 4822 prev->offs + offsetof(ehci_itd_t, itd_next), 4823 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4824 prev->xfer_next = itd; 4825 } 4826 4827 /* 4828 * Step 1.5, initialize uframes 4829 */ 4830 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4831 /* Calculate which page in the list this starts in */ 4832 int addr = DMAADDR(dma_buf, froffs); 4833 addr = EHCI_PAGE_OFFSET(addr); 4834 addr += (offs - froffs); 4835 addr = EHCI_PAGE(addr); 4836 addr /= EHCI_PAGE_SIZE; 4837 4838 /* 4839 * This gets the initial offset into the first page, 4840 * looks how far further along the current uframe 4841 * offset is. Works out how many pages that is. 4842 */ 4843 4844 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4845 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4846 EHCI_ITD_SET_PG(addr) | 4847 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4848 4849 total_length += xfer->ux_frlengths[trans_count]; 4850 offs += xfer->ux_frlengths[trans_count]; 4851 trans_count++; 4852 4853 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4854 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4855 break; 4856 } 4857 } 4858 4859 /* 4860 * Step 1.75, set buffer pointers. To simplify matters, all 4861 * pointers are filled out for the next 7 hardware pages in 4862 * the dma block, so no need to worry what pages to cover 4863 * and what to not. 4864 */ 4865 4866 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4867 /* 4868 * Don't try to lookup a page that's past the end 4869 * of buffer 4870 */ 4871 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4872 if (page_offs >= dma_buf->udma_block->size) 4873 break; 4874 4875 uint64_t page = DMAADDR(dma_buf, page_offs); 4876 page = EHCI_PAGE(page); 4877 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4878 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4879 } 4880 /* 4881 * Other special values 4882 */ 4883 4884 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4885 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4886 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4887 4888 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4889 ? 1 : 0; 4890 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4891 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4892 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4893 4894 /* FIXME: handle invalid trans */ 4895 itd->itd.itd_bufr[2] |= 4896 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4897 4898 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4899 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4900 4901 prev = itd; 4902 } /* End of frame */ 4903 4904 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4905 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4906 4907 /* 4908 * Part 2: Transfer descriptors have now been set up, now they must 4909 * be scheduled into the period frame list. Erk. Not wanting to 4910 * complicate matters, transfer is denied if the transfer spans 4911 * more than the period frame list. 4912 */ 4913 4914 mutex_enter(&sc->sc_lock); 4915 4916 /* Start inserting frames */ 4917 if (epipe->isoc.cur_xfers > 0) { 4918 frindex = epipe->isoc.next_frame; 4919 } else { 4920 frindex = EOREAD4(sc, EHCI_FRINDEX); 4921 frindex = frindex >> 3; /* Erase microframe index */ 4922 frindex += 2; 4923 } 4924 4925 if (frindex >= sc->sc_flsize) 4926 frindex &= (sc->sc_flsize - 1); 4927 4928 /* What's the frame interval? */ 4929 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4930 if (i / USB_UFRAMES_PER_FRAME == 0) 4931 i = 1; 4932 else 4933 i /= USB_UFRAMES_PER_FRAME; 4934 4935 itd = exfer->ex_itdstart; 4936 for (j = 0; j < frames; j++) { 4937 KASSERTMSG(itd != NULL, "frame %d\n", j); 4938 4939 usb_syncmem(&sc->sc_fldma, 4940 sizeof(ehci_link_t) * frindex, 4941 sizeof(ehci_link_t), 4942 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4943 4944 itd->itd.itd_next = sc->sc_flist[frindex]; 4945 if (itd->itd.itd_next == 0) 4946 /* 4947 * FIXME: frindex table gets initialized to NULL 4948 * or EHCI_NULL? 4949 */ 4950 itd->itd.itd_next = EHCI_NULL; 4951 4952 usb_syncmem(&itd->dma, 4953 itd->offs + offsetof(ehci_itd_t, itd_next), 4954 sizeof(itd->itd.itd_next), 4955 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4956 4957 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4958 4959 usb_syncmem(&sc->sc_fldma, 4960 sizeof(ehci_link_t) * frindex, 4961 sizeof(ehci_link_t), 4962 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4963 4964 itd->frame_list.next = sc->sc_softitds[frindex]; 4965 sc->sc_softitds[frindex] = itd; 4966 if (itd->frame_list.next != NULL) 4967 itd->frame_list.next->frame_list.prev = itd; 4968 itd->slot = frindex; 4969 itd->frame_list.prev = NULL; 4970 4971 frindex += i; 4972 if (frindex >= sc->sc_flsize) 4973 frindex -= sc->sc_flsize; 4974 4975 itd = itd->xfer_next; 4976 } 4977 4978 epipe->isoc.cur_xfers++; 4979 epipe->isoc.next_frame = frindex; 4980 4981 ehci_add_intr_list(sc, exfer); 4982 xfer->ux_status = USBD_IN_PROGRESS; 4983 mutex_exit(&sc->sc_lock); 4984 4985 return USBD_IN_PROGRESS; 4986 } 4987 4988 Static void 4989 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4990 { 4991 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4992 4993 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4994 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4995 } 4996 4997 Static void 4998 ehci_device_isoc_close(struct usbd_pipe *pipe) 4999 { 5000 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 5001 5002 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 5003 } 5004 5005 Static void 5006 ehci_device_isoc_done(struct usbd_xfer *xfer) 5007 { 5008 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5009 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5010 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5011 5012 KASSERT(mutex_owned(&sc->sc_lock)); 5013 5014 epipe->isoc.cur_xfers--; 5015 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5016 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5017 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5018 } 5019
Indexes created Wed Oct 01 19:09:53 GMT 2025