ehci.c revision 1.255
1 /* $NetBSD: ehci.c,v 1.255 2017/07/08 16:19:20 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.255 2017/07/08 16:19:20 jmcneill Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static void ehci_intrlist_timeout(void *); 172 Static void ehci_doorbell(void *); 173 Static void ehci_pcd(void *); 174 175 Static struct usbd_xfer * 176 ehci_allocx(struct usbd_bus *, unsigned int); 177 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 178 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_softwake_cv, "ehciab"); 416 cv_init(&sc->sc_doorbell, "ehcidi"); 417 418 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 419 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 420 421 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 422 ehci_doorbell, sc); 423 KASSERT(sc->sc_doorbell_si != NULL); 424 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 425 ehci_pcd, sc); 426 KASSERT(sc->sc_pcd_si != NULL); 427 428 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 429 430 vers = EREAD2(sc, EHCI_HCIVERSION); 431 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 432 vers >> 8, vers & 0xff); 433 434 sparams = EREAD4(sc, EHCI_HCSPARAMS); 435 DPRINTF("sparams=%#x", sparams, 0, 0, 0); 436 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 437 ncomp = EHCI_HCS_N_CC(sparams); 438 if (ncomp != sc->sc_ncomp) { 439 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 440 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 441 #if NOHCI == 0 || NUHCI == 0 442 aprint_error("%s: ohci or uhci probably not configured\n", 443 device_xname(sc->sc_dev)); 444 #endif 445 if (ncomp < sc->sc_ncomp) 446 sc->sc_ncomp = ncomp; 447 } 448 if (sc->sc_ncomp > 0) { 449 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 450 aprint_normal("%s: %d companion controller%s, %d port%s%s", 451 device_xname(sc->sc_dev), sc->sc_ncomp, 452 sc->sc_ncomp!=1 ? "s" : "", 453 EHCI_HCS_N_PCC(sparams), 454 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 455 sc->sc_ncomp!=1 ? " each" : ""); 456 if (sc->sc_comps[0]) { 457 aprint_normal(":"); 458 for (i = 0; i < sc->sc_ncomp; i++) 459 aprint_normal(" %s", 460 device_xname(sc->sc_comps[i])); 461 } 462 aprint_normal("\n"); 463 } 464 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 465 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 466 467 cparams = EREAD4(sc, EHCI_HCCPARAMS); 468 DPRINTF("cparams=%#x", cparams, 0, 0, 0); 469 470 if (EHCI_HCC_64BIT(cparams)) { 471 /* MUST clear segment register if 64 bit capable. */ 472 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 473 } 474 475 if (cparams & EHCI_HCC_IST_FULLFRAME) { 476 sc->sc_istthreshold = 0; 477 } else { 478 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 479 } 480 481 sc->sc_bus.ub_revision = USBREV_2_0; 482 sc->sc_bus.ub_usedma = true; 483 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 484 485 /* Reset the controller */ 486 DPRINTF("resetting", 0, 0, 0, 0); 487 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 488 usb_delay_ms(&sc->sc_bus, 1); 489 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 490 for (i = 0; i < 100; i++) { 491 usb_delay_ms(&sc->sc_bus, 1); 492 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 493 if (!hcr) 494 break; 495 } 496 if (hcr) { 497 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 498 return EIO; 499 } 500 if (sc->sc_vendor_init) 501 sc->sc_vendor_init(sc); 502 503 /* XXX need proper intr scheduling */ 504 sc->sc_rand = 96; 505 506 /* frame list size at default, read back what we got and use that */ 507 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 508 case 0: sc->sc_flsize = 1024; break; 509 case 1: sc->sc_flsize = 512; break; 510 case 2: sc->sc_flsize = 256; break; 511 case 3: return EIO; 512 } 513 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 514 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 515 if (err) 516 return err; 517 DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); 518 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 519 520 for (i = 0; i < sc->sc_flsize; i++) { 521 sc->sc_flist[i] = EHCI_NULL; 522 } 523 524 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 525 526 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 527 KM_SLEEP); 528 if (sc->sc_softitds == NULL) 529 return ENOMEM; 530 LIST_INIT(&sc->sc_freeitds); 531 LIST_INIT(&sc->sc_freesitds); 532 TAILQ_INIT(&sc->sc_intrhead); 533 534 /* Set up the bus struct. */ 535 sc->sc_bus.ub_methods = &ehci_bus_methods; 536 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 537 538 sc->sc_eintrs = EHCI_NORMAL_INTRS; 539 540 /* 541 * Allocate the interrupt dummy QHs. These are arranged to give poll 542 * intervals that are powers of 2 times 1ms. 543 */ 544 for (i = 0; i < EHCI_INTRQHS; i++) { 545 sqh = ehci_alloc_sqh(sc); 546 if (sqh == NULL) { 547 err = ENOMEM; 548 goto bad1; 549 } 550 sc->sc_islots[i].sqh = sqh; 551 } 552 for (i = 0; i < EHCI_INTRQHS; i++) { 553 sqh = sc->sc_islots[i].sqh; 554 if (i == 0) { 555 /* The last (1ms) QH terminates. */ 556 sqh->qh.qh_link = EHCI_NULL; 557 sqh->next = NULL; 558 } else { 559 /* Otherwise the next QH has half the poll interval */ 560 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 561 sqh->qh.qh_link = htole32(sqh->next->physaddr | 562 EHCI_LINK_QH); 563 } 564 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 565 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 566 sqh->qh.qh_curqtd = EHCI_NULL; 567 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 568 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 569 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 570 sqh->sqtd = NULL; 571 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 572 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 573 } 574 /* Point the frame list at the last level (128ms). */ 575 for (i = 0; i < sc->sc_flsize; i++) { 576 int j; 577 578 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 579 revbits[i & (EHCI_MAX_POLLRATE-1)]; 580 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 581 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 582 i)].sqh->physaddr); 583 } 584 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 585 BUS_DMASYNC_PREWRITE); 586 587 /* Allocate dummy QH that starts the async list. */ 588 sqh = ehci_alloc_sqh(sc); 589 if (sqh == NULL) { 590 err = ENOMEM; 591 goto bad1; 592 } 593 /* Fill the QH */ 594 sqh->qh.qh_endp = 595 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 596 sqh->qh.qh_link = 597 htole32(sqh->physaddr | EHCI_LINK_QH); 598 sqh->qh.qh_curqtd = EHCI_NULL; 599 sqh->next = NULL; 600 /* Fill the overlay qTD */ 601 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 602 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 603 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 604 sqh->sqtd = NULL; 605 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 607 #ifdef EHCI_DEBUG 608 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 609 ehci_dump_sqh(sqh); 610 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 611 #endif 612 613 /* Point to async list */ 614 sc->sc_async_head = sqh; 615 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 616 617 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 618 619 /* Turn on controller */ 620 EOWRITE4(sc, EHCI_USBCMD, 621 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 622 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 623 EHCI_CMD_ASE | 624 EHCI_CMD_PSE | 625 EHCI_CMD_RS); 626 627 /* Take over port ownership */ 628 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 629 630 for (i = 0; i < 100; i++) { 631 usb_delay_ms(&sc->sc_bus, 1); 632 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 633 if (!hcr) 634 break; 635 } 636 if (hcr) { 637 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 638 return EIO; 639 } 640 641 /* Enable interrupts */ 642 DPRINTF("enabling interupts", 0, 0, 0, 0); 643 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 644 645 return 0; 646 647 #if 0 648 bad2: 649 ehci_free_sqh(sc, sc->sc_async_head); 650 #endif 651 bad1: 652 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 653 return err; 654 } 655 656 int 657 ehci_intr(void *v) 658 { 659 ehci_softc_t *sc = v; 660 int ret = 0; 661 662 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 663 664 if (sc == NULL) 665 return 0; 666 667 mutex_spin_enter(&sc->sc_intr_lock); 668 669 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 670 goto done; 671 672 /* If we get an interrupt while polling, then just ignore it. */ 673 if (sc->sc_bus.ub_usepolling) { 674 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 675 676 if (intrs) 677 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 678 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 679 goto done; 680 } 681 682 ret = ehci_intr1(sc); 683 684 done: 685 mutex_spin_exit(&sc->sc_intr_lock); 686 return ret; 687 } 688 689 Static int 690 ehci_intr1(ehci_softc_t *sc) 691 { 692 uint32_t intrs, eintrs; 693 694 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 695 696 /* In case the interrupt occurs before initialization has completed. */ 697 if (sc == NULL) { 698 #ifdef DIAGNOSTIC 699 printf("ehci_intr1: sc == NULL\n"); 700 #endif 701 return 0; 702 } 703 704 KASSERT(mutex_owned(&sc->sc_intr_lock)); 705 706 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 707 if (!intrs) 708 return 0; 709 710 eintrs = intrs & sc->sc_eintrs; 711 DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, 712 EOREAD4(sc, EHCI_USBSTS), eintrs); 713 if (!eintrs) 714 return 0; 715 716 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 717 if (eintrs & EHCI_STS_IAA) { 718 DPRINTF("door bell", 0, 0, 0, 0); 719 kpreempt_disable(); 720 KASSERT(sc->sc_doorbell_si != NULL); 721 softint_schedule(sc->sc_doorbell_si); 722 kpreempt_enable(); 723 eintrs &= ~EHCI_STS_IAA; 724 } 725 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 726 DPRINTF("INT=%d ERRINT=%d", 727 eintrs & EHCI_STS_INT ? 1 : 0, 728 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 729 usb_schedsoftintr(&sc->sc_bus); 730 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 731 } 732 if (eintrs & EHCI_STS_HSE) { 733 printf("%s: unrecoverable error, controller halted\n", 734 device_xname(sc->sc_dev)); 735 /* XXX what else */ 736 } 737 if (eintrs & EHCI_STS_PCD) { 738 kpreempt_disable(); 739 KASSERT(sc->sc_pcd_si != NULL); 740 softint_schedule(sc->sc_pcd_si); 741 kpreempt_enable(); 742 eintrs &= ~EHCI_STS_PCD; 743 } 744 745 if (eintrs != 0) { 746 /* Block unprocessed interrupts. */ 747 sc->sc_eintrs &= ~eintrs; 748 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 749 printf("%s: blocking intrs 0x%x\n", 750 device_xname(sc->sc_dev), eintrs); 751 } 752 753 return 1; 754 } 755 756 Static void 757 ehci_doorbell(void *addr) 758 { 759 ehci_softc_t *sc = addr; 760 761 mutex_enter(&sc->sc_lock); 762 cv_broadcast(&sc->sc_doorbell); 763 mutex_exit(&sc->sc_lock); 764 } 765 766 Static void 767 ehci_pcd(void *addr) 768 { 769 ehci_softc_t *sc = addr; 770 struct usbd_xfer *xfer; 771 u_char *p; 772 int i, m; 773 774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 775 776 mutex_enter(&sc->sc_lock); 777 xfer = sc->sc_intrxfer; 778 779 if (xfer == NULL) { 780 /* Just ignore the change. */ 781 goto done; 782 } 783 784 p = xfer->ux_buf; 785 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 786 memset(p, 0, xfer->ux_length); 787 for (i = 1; i <= m; i++) { 788 /* Pick out CHANGE bits from the status reg. */ 789 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 790 p[i/8] |= 1 << (i%8); 791 if (i % 8 == 7) 792 DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); 793 } 794 xfer->ux_actlen = xfer->ux_length; 795 xfer->ux_status = USBD_NORMAL_COMPLETION; 796 797 usb_transfer_complete(xfer); 798 799 done: 800 mutex_exit(&sc->sc_lock); 801 } 802 803 Static void 804 ehci_softintr(void *v) 805 { 806 struct usbd_bus *bus = v; 807 ehci_softc_t *sc = EHCI_BUS2SC(bus); 808 struct ehci_xfer *ex, *nextex; 809 810 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 811 812 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 813 814 ex_completeq_t cq; 815 TAILQ_INIT(&cq); 816 817 /* 818 * The only explanation I can think of for why EHCI is as brain dead 819 * as UHCI interrupt-wise is that Intel was involved in both. 820 * An interrupt just tells us that something is done, we have no 821 * clue what, so we need to scan through all active transfers. :-( 822 */ 823 824 /* 825 * ehci_idone will remove transfer from sc->sc_intrhead if it's 826 * complete and add to our cq list 827 * 828 */ 829 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 830 switch (ex->ex_type) { 831 case EX_CTRL: 832 case EX_BULK: 833 case EX_INTR: 834 ehci_check_qh_intr(sc, ex, &cq); 835 break; 836 case EX_ISOC: 837 ehci_check_itd_intr(sc, ex, &cq); 838 break; 839 case EX_FS_ISOC: 840 ehci_check_sitd_intr(sc, ex, &cq); 841 break; 842 default: 843 KASSERT(false); 844 } 845 846 } 847 848 /* 849 * We abuse ex_next for the interrupt and complete lists and 850 * interrupt transfers will get re-added here so use 851 * the _SAFE version of TAILQ_FOREACH. 852 */ 853 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 854 usb_transfer_complete(&ex->ex_xfer); 855 } 856 857 /* Schedule a callout to catch any dropped transactions. */ 858 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 859 !TAILQ_EMPTY(&sc->sc_intrhead)) 860 callout_reset(&sc->sc_tmo_intrlist, 861 hz, ehci_intrlist_timeout, sc); 862 863 if (sc->sc_softwake) { 864 sc->sc_softwake = 0; 865 cv_broadcast(&sc->sc_softwake_cv); 866 } 867 } 868 869 Static void 870 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 871 { 872 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 873 uint32_t status; 874 875 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 876 877 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 878 879 if (ex->ex_type == EX_CTRL) { 880 fsqtd = ex->ex_setup; 881 lsqtd = ex->ex_status; 882 } else { 883 fsqtd = ex->ex_sqtdstart; 884 lsqtd = ex->ex_sqtdend; 885 } 886 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 887 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 888 889 /* 890 * If the last TD is still active we need to check whether there 891 * is an error somewhere in the middle, or whether there was a 892 * short packet (SPD and not ACTIVE). 893 */ 894 usb_syncmem(&lsqtd->dma, 895 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 896 sizeof(lsqtd->qtd.qtd_status), 897 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 898 status = le32toh(lsqtd->qtd.qtd_status); 899 usb_syncmem(&lsqtd->dma, 900 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 901 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 902 if (status & EHCI_QTD_ACTIVE) { 903 DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); 904 905 /* last qTD has already been checked */ 906 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 907 usb_syncmem(&sqtd->dma, 908 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 909 sizeof(sqtd->qtd.qtd_status), 910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 911 status = le32toh(sqtd->qtd.qtd_status); 912 usb_syncmem(&sqtd->dma, 913 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 914 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 915 /* If there's an active QTD the xfer isn't done. */ 916 if (status & EHCI_QTD_ACTIVE) 917 break; 918 /* Any kind of error makes the xfer done. */ 919 if (status & EHCI_QTD_HALTED) 920 goto done; 921 /* Handle short packets */ 922 if (EHCI_QTD_GET_BYTES(status) != 0) { 923 /* 924 * If we get here for a control transfer then 925 * we need to let the hardware complete the 926 * status phase. That is, we're not done 927 * quite yet. 928 * 929 * Otherwise, we're done. 930 */ 931 if (ex->ex_type == EX_CTRL) { 932 break; 933 } 934 goto done; 935 } 936 } 937 DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, 938 0, 0); 939 #ifdef EHCI_DEBUG 940 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 941 ehci_dump_sqtds(ex->ex_sqtdstart); 942 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 943 #endif 944 return; 945 } 946 done: 947 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 948 callout_stop(&ex->ex_xfer.ux_callout); 949 ehci_idone(ex, cq); 950 } 951 952 Static void 953 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 954 { 955 ehci_soft_itd_t *itd; 956 int i; 957 958 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 959 960 KASSERT(mutex_owned(&sc->sc_lock)); 961 962 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 963 return; 964 965 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 966 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 967 968 itd = ex->ex_itdend; 969 970 /* 971 * check no active transfers in last itd, meaning we're finished 972 */ 973 974 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 975 sizeof(itd->itd.itd_ctl), 976 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 977 978 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 979 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 980 break; 981 } 982 983 if (i == EHCI_ITD_NUFRAMES) { 984 goto done; /* All 8 descriptors inactive, it's done */ 985 } 986 987 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 988 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 989 990 DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); 991 return; 992 done: 993 DPRINTF("ex %p done", ex, 0, 0, 0); 994 callout_stop(&ex->ex_xfer.ux_callout); 995 ehci_idone(ex, cq); 996 } 997 998 void 999 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1000 { 1001 ehci_soft_sitd_t *sitd; 1002 1003 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1004 1005 KASSERT(mutex_owned(&sc->sc_lock)); 1006 1007 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1008 return; 1009 1010 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1011 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1012 1013 sitd = ex->ex_sitdend; 1014 1015 /* 1016 * check no active transfers in last sitd, meaning we're finished 1017 */ 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), 1021 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1022 1023 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1024 1025 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1026 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1027 1028 if (active) 1029 return; 1030 1031 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 1032 callout_stop(&(ex->ex_xfer.ux_callout)); 1033 ehci_idone(ex, cq); 1034 } 1035 1036 1037 Static void 1038 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1039 { 1040 struct usbd_xfer *xfer = &ex->ex_xfer; 1041 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1042 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1043 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1044 uint32_t status = 0, nstatus = 0; 1045 int actlen = 0; 1046 1047 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1048 1049 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1050 1051 DPRINTF("ex=%p", ex, 0, 0, 0); 1052 1053 if (xfer->ux_status == USBD_CANCELLED || 1054 xfer->ux_status == USBD_TIMEOUT) { 1055 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1056 return; 1057 } 1058 1059 #ifdef DIAGNOSTIC 1060 #ifdef EHCI_DEBUG 1061 if (ex->ex_isdone) { 1062 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1063 ehci_dump_exfer(ex); 1064 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1065 } 1066 #endif 1067 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1068 ex->ex_type, xfer->ux_status); 1069 ex->ex_isdone = true; 1070 #endif 1071 1072 DPRINTF("xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1073 1074 /* The transfer is done, compute actual length and status. */ 1075 if (ex->ex_type == EX_ISOC) { 1076 /* HS isoc transfer */ 1077 1078 struct ehci_soft_itd *itd; 1079 int i, nframes, len, uframes; 1080 1081 nframes = 0; 1082 1083 #ifdef EHCI_DEBUG 1084 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1085 ehci_dump_itds(ex->ex_itdstart); 1086 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1087 #endif 1088 1089 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1090 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1091 1092 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1093 usb_syncmem(&itd->dma, 1094 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1095 sizeof(itd->itd.itd_ctl), 1096 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1097 1098 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1099 /* 1100 * XXX - driver didn't fill in the frame full 1101 * of uframes. This leads to scheduling 1102 * inefficiencies, but working around 1103 * this doubles complexity of tracking 1104 * an xfer. 1105 */ 1106 if (nframes >= xfer->ux_nframes) 1107 break; 1108 1109 status = le32toh(itd->itd.itd_ctl[i]); 1110 len = EHCI_ITD_GET_LEN(status); 1111 if (EHCI_ITD_GET_STATUS(status) != 0) 1112 len = 0; /*No valid data on error*/ 1113 1114 xfer->ux_frlengths[nframes++] = len; 1115 actlen += len; 1116 } 1117 usb_syncmem(&itd->dma, 1118 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1119 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1120 1121 if (nframes >= xfer->ux_nframes) 1122 break; 1123 } 1124 1125 xfer->ux_actlen = actlen; 1126 xfer->ux_status = USBD_NORMAL_COMPLETION; 1127 goto end; 1128 } else if (ex->ex_type == EX_FS_ISOC) { 1129 /* FS isoc transfer */ 1130 struct ehci_soft_sitd *sitd; 1131 int nframes, len; 1132 1133 nframes = 0; 1134 1135 for (sitd = ex->ex_sitdstart; sitd != NULL; 1136 sitd = sitd->xfer_next) { 1137 usb_syncmem(&sitd->dma, 1138 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1139 sizeof(sitd->sitd.sitd_trans), 1140 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1141 1142 /* 1143 * XXX - driver didn't fill in the frame full 1144 * of uframes. This leads to scheduling 1145 * inefficiencies, but working around 1146 * this doubles complexity of tracking 1147 * an xfer. 1148 */ 1149 if (nframes >= xfer->ux_nframes) 1150 break; 1151 1152 status = le32toh(sitd->sitd.sitd_trans); 1153 usb_syncmem(&sitd->dma, 1154 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1155 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1156 1157 len = EHCI_SITD_GET_LEN(status); 1158 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1159 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1160 /* No valid data on error */ 1161 len = xfer->ux_frlengths[nframes]; 1162 } 1163 1164 /* 1165 * frlengths[i]: # of bytes to send 1166 * len: # of bytes host didn't send 1167 */ 1168 xfer->ux_frlengths[nframes] -= len; 1169 /* frlengths[i]: # of bytes host sent */ 1170 actlen += xfer->ux_frlengths[nframes++]; 1171 1172 if (nframes >= xfer->ux_nframes) 1173 break; 1174 } 1175 1176 xfer->ux_actlen = actlen; 1177 xfer->ux_status = USBD_NORMAL_COMPLETION; 1178 goto end; 1179 } 1180 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1181 ex->ex_type == EX_BULK); 1182 1183 /* Continue processing xfers using queue heads */ 1184 if (ex->ex_type == EX_CTRL) { 1185 fsqtd = ex->ex_setup; 1186 lsqtd = ex->ex_status; 1187 } else { 1188 fsqtd = ex->ex_sqtdstart; 1189 lsqtd = ex->ex_sqtdend; 1190 } 1191 #ifdef EHCI_DEBUG 1192 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1193 ehci_dump_sqtds(fsqtd); 1194 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1195 #endif 1196 1197 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1198 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1199 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1200 nstatus = le32toh(sqtd->qtd.qtd_status); 1201 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1202 BUS_DMASYNC_PREREAD); 1203 if (nstatus & EHCI_QTD_ACTIVE) 1204 break; 1205 1206 status = nstatus; 1207 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1208 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1209 } 1210 1211 /* 1212 * If there are left over TDs we need to update the toggle. 1213 * The default pipe doesn't need it since control transfers 1214 * start the toggle at 0 every time. 1215 * For a short transfer we need to update the toggle for the missing 1216 * packets within the qTD. 1217 */ 1218 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1219 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1220 DPRINTF("toggle update status=0x%08x nstatus=0x%08x", 1221 status, nstatus, 0, 0); 1222 #if 0 1223 ehci_dump_sqh(epipe->sqh); 1224 ehci_dump_sqtds(ex->ex_sqtdstart); 1225 #endif 1226 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1227 } 1228 1229 DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, 1230 status, 0); 1231 xfer->ux_actlen = actlen; 1232 if (status & EHCI_QTD_HALTED) { 1233 #ifdef EHCI_DEBUG 1234 DPRINTF("halted addr=%d endpt=0x%02x", 1235 xfer->ux_pipe->up_dev->ud_addr, 1236 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1237 0, 0); 1238 DPRINTF("cerr=%d pid=%d", 1239 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1240 0, 0); 1241 DPRINTF("active =%d halted=%d buferr=%d babble=%d", 1242 status & EHCI_QTD_ACTIVE ? 1 : 0, 1243 status & EHCI_QTD_HALTED ? 1 : 0, 1244 status & EHCI_QTD_BUFERR ? 1 : 0, 1245 status & EHCI_QTD_BABBLE ? 1 : 0); 1246 1247 DPRINTF("xacterr=%d missed=%d split =%d ping =%d", 1248 status & EHCI_QTD_XACTERR ? 1 : 0, 1249 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1250 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1251 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1252 1253 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1254 ehci_dump_sqh(epipe->sqh); 1255 ehci_dump_sqtds(ex->ex_sqtdstart); 1256 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1257 #endif 1258 /* low&full speed has an extra error flag */ 1259 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1260 EHCI_QH_SPEED_HIGH) 1261 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1262 else 1263 status &= EHCI_QTD_STATERRS; 1264 if (status == 0) /* no other errors means a stall */ { 1265 xfer->ux_status = USBD_STALLED; 1266 } else { 1267 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1268 } 1269 /* XXX need to reset TT on missed microframe */ 1270 if (status & EHCI_QTD_MISSEDMICRO) { 1271 printf("%s: missed microframe, TT reset not " 1272 "implemented, hub might be inoperational\n", 1273 device_xname(sc->sc_dev)); 1274 } 1275 } else { 1276 xfer->ux_status = USBD_NORMAL_COMPLETION; 1277 } 1278 1279 end: 1280 1281 ehci_del_intr_list(sc, ex); 1282 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1283 1284 DPRINTF("ex=%p done", ex, 0, 0, 0); 1285 } 1286 1287 Static void 1288 ehci_poll(struct usbd_bus *bus) 1289 { 1290 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1291 1292 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1293 1294 #ifdef EHCI_DEBUG 1295 static int last; 1296 int new; 1297 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1298 if (new != last) { 1299 DPRINTF("intrs=0x%04x", new, 0, 0, 0); 1300 last = new; 1301 } 1302 #endif 1303 1304 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1305 mutex_spin_enter(&sc->sc_intr_lock); 1306 ehci_intr1(sc); 1307 mutex_spin_exit(&sc->sc_intr_lock); 1308 } 1309 } 1310 1311 void 1312 ehci_childdet(device_t self, device_t child) 1313 { 1314 struct ehci_softc *sc = device_private(self); 1315 1316 KASSERT(sc->sc_child == child); 1317 sc->sc_child = NULL; 1318 } 1319 1320 int 1321 ehci_detach(struct ehci_softc *sc, int flags) 1322 { 1323 int rv = 0; 1324 1325 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1326 1327 if (sc->sc_child != NULL) 1328 rv = config_detach(sc->sc_child, flags); 1329 1330 if (rv != 0) 1331 return rv; 1332 1333 callout_halt(&sc->sc_tmo_intrlist, NULL); 1334 callout_destroy(&sc->sc_tmo_intrlist); 1335 1336 /* XXX free other data structures XXX */ 1337 if (sc->sc_softitds) 1338 kmem_free(sc->sc_softitds, 1339 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1340 cv_destroy(&sc->sc_doorbell); 1341 cv_destroy(&sc->sc_softwake_cv); 1342 1343 #if 0 1344 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1345 1346 softint_disestablish(sc->sc_doorbell_si); 1347 softint_disestablish(sc->sc_pcd_si); 1348 1349 mutex_destroy(&sc->sc_lock); 1350 mutex_destroy(&sc->sc_intr_lock); 1351 #endif 1352 1353 pool_cache_destroy(sc->sc_xferpool); 1354 1355 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1356 1357 return rv; 1358 } 1359 1360 1361 int 1362 ehci_activate(device_t self, enum devact act) 1363 { 1364 struct ehci_softc *sc = device_private(self); 1365 1366 switch (act) { 1367 case DVACT_DEACTIVATE: 1368 sc->sc_dying = 1; 1369 return 0; 1370 default: 1371 return EOPNOTSUPP; 1372 } 1373 } 1374 1375 /* 1376 * Handle suspend/resume. 1377 * 1378 * We need to switch to polling mode here, because this routine is 1379 * called from an interrupt context. This is all right since we 1380 * are almost suspended anyway. 1381 * 1382 * Note that this power handler isn't to be registered directly; the 1383 * bus glue needs to call out to it. 1384 */ 1385 bool 1386 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1387 { 1388 ehci_softc_t *sc = device_private(dv); 1389 int i; 1390 uint32_t cmd, hcr; 1391 1392 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1393 1394 mutex_spin_enter(&sc->sc_intr_lock); 1395 sc->sc_bus.ub_usepolling++; 1396 mutex_spin_exit(&sc->sc_intr_lock); 1397 1398 for (i = 1; i <= sc->sc_noport; i++) { 1399 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1400 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1401 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1402 } 1403 1404 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1405 1406 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1407 EOWRITE4(sc, EHCI_USBCMD, cmd); 1408 1409 for (i = 0; i < 100; i++) { 1410 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1411 if (hcr == 0) 1412 break; 1413 1414 usb_delay_ms(&sc->sc_bus, 1); 1415 } 1416 if (hcr != 0) 1417 printf("%s: reset timeout\n", device_xname(dv)); 1418 1419 cmd &= ~EHCI_CMD_RS; 1420 EOWRITE4(sc, EHCI_USBCMD, cmd); 1421 1422 for (i = 0; i < 100; i++) { 1423 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1424 if (hcr == EHCI_STS_HCH) 1425 break; 1426 1427 usb_delay_ms(&sc->sc_bus, 1); 1428 } 1429 if (hcr != EHCI_STS_HCH) 1430 printf("%s: config timeout\n", device_xname(dv)); 1431 1432 mutex_spin_enter(&sc->sc_intr_lock); 1433 sc->sc_bus.ub_usepolling--; 1434 mutex_spin_exit(&sc->sc_intr_lock); 1435 1436 return true; 1437 } 1438 1439 bool 1440 ehci_resume(device_t dv, const pmf_qual_t *qual) 1441 { 1442 ehci_softc_t *sc = device_private(dv); 1443 int i; 1444 uint32_t cmd, hcr; 1445 1446 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1447 1448 /* restore things in case the bios sucks */ 1449 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1450 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1451 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1452 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1453 1454 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1455 1456 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1457 1458 hcr = 0; 1459 for (i = 1; i <= sc->sc_noport; i++) { 1460 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1461 if ((cmd & EHCI_PS_PO) == 0 && 1462 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1463 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1464 hcr = 1; 1465 } 1466 } 1467 1468 if (hcr) { 1469 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1470 1471 for (i = 1; i <= sc->sc_noport; i++) { 1472 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1473 if ((cmd & EHCI_PS_PO) == 0 && 1474 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1475 EOWRITE4(sc, EHCI_PORTSC(i), 1476 cmd & ~EHCI_PS_FPR); 1477 } 1478 } 1479 1480 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1481 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1482 1483 for (i = 0; i < 100; i++) { 1484 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1485 if (hcr != EHCI_STS_HCH) 1486 break; 1487 1488 usb_delay_ms(&sc->sc_bus, 1); 1489 } 1490 if (hcr == EHCI_STS_HCH) 1491 printf("%s: config timeout\n", device_xname(dv)); 1492 1493 return true; 1494 } 1495 1496 /* 1497 * Shut down the controller when the system is going down. 1498 */ 1499 bool 1500 ehci_shutdown(device_t self, int flags) 1501 { 1502 ehci_softc_t *sc = device_private(self); 1503 1504 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1505 1506 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1507 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1508 return true; 1509 } 1510 1511 Static struct usbd_xfer * 1512 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1513 { 1514 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1515 struct usbd_xfer *xfer; 1516 1517 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1518 if (xfer != NULL) { 1519 memset(xfer, 0, sizeof(struct ehci_xfer)); 1520 #ifdef DIAGNOSTIC 1521 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1522 ex->ex_isdone = true; 1523 xfer->ux_state = XFER_BUSY; 1524 #endif 1525 } 1526 return xfer; 1527 } 1528 1529 Static void 1530 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1531 { 1532 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1533 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1534 1535 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1536 xfer->ux_state); 1537 KASSERT(ex->ex_isdone); 1538 1539 #ifdef DIAGNOSTIC 1540 xfer->ux_state = XFER_FREE; 1541 #endif 1542 1543 pool_cache_put(sc->sc_xferpool, xfer); 1544 } 1545 1546 Static void 1547 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1548 { 1549 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1550 1551 *lock = &sc->sc_lock; 1552 } 1553 1554 Static void 1555 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1556 { 1557 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1558 1559 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1560 1561 DPRINTF("epipe=%p status=0x%08x", epipe, 1562 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1563 #ifdef EHCI_DEBUG 1564 if (ehcidebug) 1565 usbd_dump_pipe(pipe); 1566 #endif 1567 epipe->nexttoggle = 0; 1568 } 1569 1570 Static void 1571 ehci_noop(struct usbd_pipe *pipe) 1572 { 1573 } 1574 1575 #ifdef EHCI_DEBUG 1576 /* 1577 * Unused function - this is meant to be called from a kernel 1578 * debugger. 1579 */ 1580 void 1581 ehci_dump(void) 1582 { 1583 ehci_softc_t *sc = theehci; 1584 int i; 1585 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1586 EOREAD4(sc, EHCI_USBCMD), 1587 EOREAD4(sc, EHCI_USBSTS), 1588 EOREAD4(sc, EHCI_USBINTR)); 1589 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1590 EOREAD4(sc, EHCI_FRINDEX), 1591 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1592 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1593 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1594 for (i = 1; i <= sc->sc_noport; i++) 1595 printf("port %d status=0x%08x\n", i, 1596 EOREAD4(sc, EHCI_PORTSC(i))); 1597 } 1598 1599 Static void 1600 ehci_dump_regs(ehci_softc_t *sc) 1601 { 1602 int i; 1603 1604 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1605 1606 DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1607 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1608 EOREAD4(sc, EHCI_USBINTR), 0); 1609 DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1610 "async = 0x%08x", 1611 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1612 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1613 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1614 for (i = 1; i <= sc->sc_noport; i += 2) { 1615 if (i == sc->sc_noport) { 1616 DPRINTF("port %d status = 0x%08x", i, 1617 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1618 } else { 1619 DPRINTF( 1620 "port %d status = 0x%08x port %d status = 0x%08x", 1621 i, EOREAD4(sc, EHCI_PORTSC(i)), 1622 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1623 } 1624 } 1625 } 1626 1627 #define ehci_dump_link(link, type) do { \ 1628 DPRINTF(" link 0x%08x (T = %d):", \ 1629 link, \ 1630 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1631 if (type) { \ 1632 DPRINTF( \ 1633 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1634 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1635 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1636 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1637 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1638 } \ 1639 } while(0) 1640 1641 Static void 1642 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1643 { 1644 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1645 int i; 1646 uint32_t stop = 0; 1647 1648 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1649 ehci_dump_sqtd(sqtd); 1650 usb_syncmem(&sqtd->dma, 1651 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1652 sizeof(sqtd->qtd), 1653 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1654 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1655 usb_syncmem(&sqtd->dma, 1656 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1657 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1658 } 1659 if (!stop) 1660 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1661 } 1662 1663 Static void 1664 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1665 { 1666 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1667 1668 usb_syncmem(&sqtd->dma, sqtd->offs, 1669 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1670 1671 DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1672 ehci_dump_qtd(&sqtd->qtd); 1673 1674 usb_syncmem(&sqtd->dma, sqtd->offs, 1675 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1676 } 1677 1678 Static void 1679 ehci_dump_qtd(ehci_qtd_t *qtd) 1680 { 1681 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1682 uint32_t s = le32toh(qtd->qtd_status); 1683 1684 DPRINTFN(10, 1685 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1686 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1687 DPRINTFN(10, 1688 " toggle = %d ioc = %d bytes = %#x " 1689 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1690 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1691 DPRINTFN(10, 1692 " cerr = %d pid = %d stat = %x", 1693 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1694 0); 1695 DPRINTFN(10, 1696 "active =%d halted=%d buferr=%d babble=%d", 1697 s & EHCI_QTD_ACTIVE ? 1 : 0, 1698 s & EHCI_QTD_HALTED ? 1 : 0, 1699 s & EHCI_QTD_BUFERR ? 1 : 0, 1700 s & EHCI_QTD_BABBLE ? 1 : 0); 1701 DPRINTFN(10, 1702 "xacterr=%d missed=%d split =%d ping =%d", 1703 s & EHCI_QTD_XACTERR ? 1 : 0, 1704 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1705 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1706 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1707 DPRINTFN(10, 1708 "buffer[0] = %#x buffer[1] = %#x " 1709 "buffer[2] = %#x buffer[3] = %#x", 1710 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1711 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1712 DPRINTFN(10, 1713 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1714 } 1715 1716 Static void 1717 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1718 { 1719 ehci_qh_t *qh = &sqh->qh; 1720 ehci_link_t link; 1721 uint32_t endp, endphub; 1722 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1723 1724 usb_syncmem(&sqh->dma, sqh->offs, 1725 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1726 1727 DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1728 link = le32toh(qh->qh_link); 1729 ehci_dump_link(link, true); 1730 1731 endp = le32toh(qh->qh_endp); 1732 DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); 1733 DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", 1734 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1735 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1736 DPRINTFN(10, " dtc = %d hrecl = %d", 1737 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1738 DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", 1739 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1740 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1741 1742 endphub = le32toh(qh->qh_endphub); 1743 DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); 1744 DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", 1745 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1746 DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", 1747 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1748 EHCI_QH_GET_MULT(endphub), 0); 1749 1750 link = le32toh(qh->qh_curqtd); 1751 ehci_dump_link(link, false); 1752 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1753 ehci_dump_qtd(&qh->qh_qtd); 1754 1755 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1756 BUS_DMASYNC_PREREAD); 1757 } 1758 1759 Static void 1760 ehci_dump_itds(ehci_soft_itd_t *itd) 1761 { 1762 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1763 int i; 1764 uint32_t stop = 0; 1765 1766 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1767 ehci_dump_itd(itd); 1768 usb_syncmem(&itd->dma, 1769 itd->offs + offsetof(ehci_itd_t, itd_next), 1770 sizeof(itd->itd), 1771 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1772 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1773 usb_syncmem(&itd->dma, 1774 itd->offs + offsetof(ehci_itd_t, itd_next), 1775 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1776 } 1777 if (!stop) 1778 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1779 } 1780 1781 Static void 1782 ehci_dump_itd(struct ehci_soft_itd *itd) 1783 { 1784 ehci_isoc_trans_t t; 1785 ehci_isoc_bufr_ptr_t b, b2, b3; 1786 int i; 1787 1788 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1789 1790 DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); 1791 1792 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1793 t = le32toh(itd->itd.itd_ctl[i]); 1794 DPRINTF("ITDctl %d: stat = %x len = %x", 1795 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1796 DPRINTF(" ioc = %x pg = %x offs = %x", 1797 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1798 EHCI_ITD_GET_OFFS(t), 0); 1799 } 1800 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1801 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1802 DPRINTF(" %x", 1803 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1804 1805 b = le32toh(itd->itd.itd_bufr[0]); 1806 b2 = le32toh(itd->itd.itd_bufr[1]); 1807 b3 = le32toh(itd->itd.itd_bufr[2]); 1808 DPRINTF(" ep = %x daddr = %x dir = %d", 1809 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1810 DPRINTF(" maxpkt = %x multi = %x", 1811 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1812 } 1813 1814 Static void 1815 ehci_dump_sitd(struct ehci_soft_itd *itd) 1816 { 1817 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1818 1819 DPRINTF("SITD %p next = %p prev = %p", 1820 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1821 DPRINTF(" xfernext=%p physaddr=%X slot=%d", 1822 itd->xfer_next, itd->physaddr, itd->slot, 0); 1823 } 1824 1825 Static void 1826 ehci_dump_exfer(struct ehci_xfer *ex) 1827 { 1828 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1829 1830 DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, 1831 ex->ex_isdone, 0); 1832 1833 switch (ex->ex_type) { 1834 case EX_CTRL: 1835 DPRINTF(" setup = %p data = %p status = %p", 1836 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1837 break; 1838 case EX_BULK: 1839 case EX_INTR: 1840 DPRINTF(" qtdstart = %p qtdend = %p", 1841 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1842 break; 1843 case EX_ISOC: 1844 DPRINTF(" itdstart = %p itdend = %p", 1845 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1846 break; 1847 case EX_FS_ISOC: 1848 DPRINTF(" sitdstart = %p sitdend = %p", 1849 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1850 break; 1851 default: 1852 DPRINTF(" unknown type", 0, 0, 0, 0); 1853 } 1854 } 1855 #endif 1856 1857 Static usbd_status 1858 ehci_open(struct usbd_pipe *pipe) 1859 { 1860 struct usbd_device *dev = pipe->up_dev; 1861 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1862 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1863 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1864 uint8_t addr = dev->ud_addr; 1865 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1866 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1867 ehci_soft_qh_t *sqh; 1868 usbd_status err; 1869 int ival, speed, naks; 1870 int hshubaddr, hshubport; 1871 1872 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1873 1874 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1875 ed->bEndpointAddress, rhaddr); 1876 1877 if (dev->ud_myhsport) { 1878 /* 1879 * When directly attached FS/LS device while doing embedded 1880 * transaction translations and we are the hub, set the hub 1881 * address to 0 (us). 1882 */ 1883 if (!(sc->sc_flags & EHCIF_ETTF) 1884 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1885 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1886 } else { 1887 hshubaddr = 0; 1888 } 1889 hshubport = dev->ud_myhsport->up_portno; 1890 } else { 1891 hshubaddr = 0; 1892 hshubport = 0; 1893 } 1894 1895 if (sc->sc_dying) 1896 return USBD_IOERROR; 1897 1898 /* toggle state needed for bulk endpoints */ 1899 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1900 1901 if (addr == rhaddr) { 1902 switch (ed->bEndpointAddress) { 1903 case USB_CONTROL_ENDPOINT: 1904 pipe->up_methods = &roothub_ctrl_methods; 1905 break; 1906 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1907 pipe->up_methods = &ehci_root_intr_methods; 1908 break; 1909 default: 1910 DPRINTF("bad bEndpointAddress 0x%02x", 1911 ed->bEndpointAddress, 0, 0, 0); 1912 return USBD_INVAL; 1913 } 1914 return USBD_NORMAL_COMPLETION; 1915 } 1916 1917 /* XXX All this stuff is only valid for async. */ 1918 switch (dev->ud_speed) { 1919 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1920 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1921 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1922 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1923 } 1924 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1925 DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, 1926 0); 1927 return USBD_INVAL; 1928 } 1929 1930 /* 1931 * For interrupt transfer, nak throttling must be disabled, but for 1932 * the other transfer type, nak throttling should be enabled from the 1933 * viewpoint that avoids the memory thrashing. 1934 */ 1935 naks = (xfertype == UE_INTERRUPT) ? 0 1936 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1937 1938 /* Allocate sqh for everything, save isoc xfers */ 1939 if (xfertype != UE_ISOCHRONOUS) { 1940 sqh = ehci_alloc_sqh(sc); 1941 if (sqh == NULL) 1942 return USBD_NOMEM; 1943 /* qh_link filled when the QH is added */ 1944 sqh->qh.qh_endp = htole32( 1945 EHCI_QH_SET_ADDR(addr) | 1946 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1947 EHCI_QH_SET_EPS(speed) | 1948 EHCI_QH_DTC | 1949 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1950 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1951 EHCI_QH_CTL : 0) | 1952 EHCI_QH_SET_NRL(naks) 1953 ); 1954 sqh->qh.qh_endphub = htole32( 1955 EHCI_QH_SET_MULT(1) | 1956 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1957 ); 1958 if (speed != EHCI_QH_SPEED_HIGH) 1959 sqh->qh.qh_endphub |= htole32( 1960 EHCI_QH_SET_PORT(hshubport) | 1961 EHCI_QH_SET_HUBA(hshubaddr) | 1962 (xfertype == UE_INTERRUPT ? 1963 EHCI_QH_SET_CMASK(0x08) : 0) 1964 ); 1965 sqh->qh.qh_curqtd = EHCI_NULL; 1966 /* Fill the overlay qTD */ 1967 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1968 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1969 sqh->qh.qh_qtd.qtd_status = htole32(0); 1970 1971 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1973 epipe->sqh = sqh; 1974 } else { 1975 sqh = NULL; 1976 } /*xfertype == UE_ISOC*/ 1977 1978 switch (xfertype) { 1979 case UE_CONTROL: 1980 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1981 0, &epipe->ctrl.reqdma); 1982 #ifdef EHCI_DEBUG 1983 if (err) 1984 printf("ehci_open: usb_allocmem()=%d\n", err); 1985 #endif 1986 if (err) 1987 goto bad; 1988 pipe->up_methods = &ehci_device_ctrl_methods; 1989 mutex_enter(&sc->sc_lock); 1990 ehci_add_qh(sc, sqh, sc->sc_async_head); 1991 mutex_exit(&sc->sc_lock); 1992 break; 1993 case UE_BULK: 1994 pipe->up_methods = &ehci_device_bulk_methods; 1995 mutex_enter(&sc->sc_lock); 1996 ehci_add_qh(sc, sqh, sc->sc_async_head); 1997 mutex_exit(&sc->sc_lock); 1998 break; 1999 case UE_INTERRUPT: 2000 pipe->up_methods = &ehci_device_intr_methods; 2001 ival = pipe->up_interval; 2002 if (ival == USBD_DEFAULT_INTERVAL) { 2003 if (speed == EHCI_QH_SPEED_HIGH) { 2004 if (ed->bInterval > 16) { 2005 /* 2006 * illegal with high-speed, but there 2007 * were documentation bugs in the spec, 2008 * so be generous 2009 */ 2010 ival = 256; 2011 } else 2012 ival = (1 << (ed->bInterval - 1)) / 8; 2013 } else 2014 ival = ed->bInterval; 2015 } 2016 err = ehci_device_setintr(sc, sqh, ival); 2017 if (err) 2018 goto bad; 2019 break; 2020 case UE_ISOCHRONOUS: 2021 pipe->up_serialise = false; 2022 if (speed == EHCI_QH_SPEED_HIGH) 2023 pipe->up_methods = &ehci_device_isoc_methods; 2024 else 2025 pipe->up_methods = &ehci_device_fs_isoc_methods; 2026 if (ed->bInterval == 0 || ed->bInterval > 16) { 2027 printf("ehci: opening pipe with invalid bInterval\n"); 2028 err = USBD_INVAL; 2029 goto bad; 2030 } 2031 if (UGETW(ed->wMaxPacketSize) == 0) { 2032 printf("ehci: zero length endpoint open request\n"); 2033 err = USBD_INVAL; 2034 goto bad; 2035 } 2036 epipe->isoc.next_frame = 0; 2037 epipe->isoc.cur_xfers = 0; 2038 break; 2039 default: 2040 DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); 2041 err = USBD_INVAL; 2042 goto bad; 2043 } 2044 return USBD_NORMAL_COMPLETION; 2045 2046 bad: 2047 if (sqh != NULL) { 2048 mutex_enter(&sc->sc_lock); 2049 ehci_free_sqh(sc, sqh); 2050 mutex_exit(&sc->sc_lock); 2051 } 2052 return err; 2053 } 2054 2055 /* 2056 * Add an ED to the schedule. Called with USB lock held. 2057 */ 2058 Static void 2059 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2060 { 2061 2062 KASSERT(mutex_owned(&sc->sc_lock)); 2063 2064 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2065 2066 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2067 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2068 2069 sqh->next = head->next; 2070 sqh->qh.qh_link = head->qh.qh_link; 2071 2072 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2073 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2074 2075 head->next = sqh; 2076 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2077 2078 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2079 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2080 2081 #ifdef EHCI_DEBUG 2082 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2083 ehci_dump_sqh(sqh); 2084 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2085 #endif 2086 } 2087 2088 /* 2089 * Remove an ED from the schedule. Called with USB lock held. 2090 */ 2091 Static void 2092 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2093 { 2094 ehci_soft_qh_t *p; 2095 2096 KASSERT(mutex_owned(&sc->sc_lock)); 2097 2098 /* XXX */ 2099 for (p = head; p != NULL && p->next != sqh; p = p->next) 2100 ; 2101 if (p == NULL) 2102 panic("ehci_rem_qh: ED not found"); 2103 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2104 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2105 p->next = sqh->next; 2106 p->qh.qh_link = sqh->qh.qh_link; 2107 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2108 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2109 2110 ehci_sync_hc(sc); 2111 } 2112 2113 Static void 2114 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2115 { 2116 int i; 2117 uint32_t status; 2118 2119 /* Save toggle bit and ping status. */ 2120 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2121 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2122 status = sqh->qh.qh_qtd.qtd_status & 2123 htole32(EHCI_QTD_TOGGLE_MASK | 2124 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2125 /* Set HALTED to make hw leave it alone. */ 2126 sqh->qh.qh_qtd.qtd_status = 2127 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2128 usb_syncmem(&sqh->dma, 2129 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2130 sizeof(sqh->qh.qh_qtd.qtd_status), 2131 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2132 sqh->qh.qh_curqtd = 0; 2133 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2134 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2135 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2136 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2137 sqh->sqtd = sqtd; 2138 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2139 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2140 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2141 sqh->qh.qh_qtd.qtd_status = status; 2142 usb_syncmem(&sqh->dma, 2143 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2144 sizeof(sqh->qh.qh_qtd.qtd_status), 2145 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2146 } 2147 2148 /* 2149 * Ensure that the HC has released all references to the QH. We do this 2150 * by asking for a Async Advance Doorbell interrupt and then we wait for 2151 * the interrupt. 2152 * To make this easier we first obtain exclusive use of the doorbell. 2153 */ 2154 Static void 2155 ehci_sync_hc(ehci_softc_t *sc) 2156 { 2157 int error __diagused; 2158 2159 KASSERT(mutex_owned(&sc->sc_lock)); 2160 2161 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2162 2163 if (sc->sc_dying) { 2164 DPRINTF("dying", 0, 0, 0, 0); 2165 return; 2166 } 2167 /* ask for doorbell */ 2168 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2169 DPRINTF("cmd = 0x%08x sts = 0x%08x", 2170 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2171 2172 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2173 2174 DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", 2175 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2176 #ifdef DIAGNOSTIC 2177 if (error == EWOULDBLOCK) { 2178 printf("ehci_sync_hc: timed out\n"); 2179 } else if (error) { 2180 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2181 } 2182 #endif 2183 } 2184 2185 Static void 2186 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2187 { 2188 2189 KASSERT(mutex_owned(&sc->sc_lock)); 2190 2191 for (; itd != NULL; itd = itd->xfer_next) { 2192 struct ehci_soft_itd *prev = itd->frame_list.prev; 2193 2194 /* Unlink itd from hardware chain, or frame array */ 2195 if (prev == NULL) { /* We're at the table head */ 2196 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2197 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2198 usb_syncmem(&sc->sc_fldma, 2199 sizeof(ehci_link_t) * itd->slot, 2200 sizeof(ehci_link_t), 2201 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2202 2203 if (itd->frame_list.next != NULL) 2204 itd->frame_list.next->frame_list.prev = NULL; 2205 } else { 2206 /* XXX this part is untested... */ 2207 prev->itd.itd_next = itd->itd.itd_next; 2208 usb_syncmem(&itd->dma, 2209 itd->offs + offsetof(ehci_itd_t, itd_next), 2210 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2211 2212 prev->frame_list.next = itd->frame_list.next; 2213 if (itd->frame_list.next != NULL) 2214 itd->frame_list.next->frame_list.prev = prev; 2215 } 2216 } 2217 } 2218 2219 Static void 2220 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2221 { 2222 struct ehci_soft_itd *next; 2223 2224 mutex_enter(&sc->sc_lock); 2225 next = NULL; 2226 for (; itd != NULL; itd = next) { 2227 next = itd->xfer_next; 2228 ehci_free_itd_locked(sc, itd); 2229 } 2230 mutex_exit(&sc->sc_lock); 2231 } 2232 2233 Static void 2234 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2235 { 2236 2237 KASSERT(mutex_owned(&sc->sc_lock)); 2238 2239 for (; sitd != NULL; sitd = sitd->xfer_next) { 2240 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2241 2242 /* Unlink sitd from hardware chain, or frame array */ 2243 if (prev == NULL) { /* We're at the table head */ 2244 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2245 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2246 usb_syncmem(&sc->sc_fldma, 2247 sizeof(ehci_link_t) * sitd->slot, 2248 sizeof(ehci_link_t), 2249 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2250 2251 if (sitd->frame_list.next != NULL) 2252 sitd->frame_list.next->frame_list.prev = NULL; 2253 } else { 2254 /* XXX this part is untested... */ 2255 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2256 usb_syncmem(&sitd->dma, 2257 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2258 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2259 2260 prev->frame_list.next = sitd->frame_list.next; 2261 if (sitd->frame_list.next != NULL) 2262 sitd->frame_list.next->frame_list.prev = prev; 2263 } 2264 } 2265 } 2266 2267 Static void 2268 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2269 { 2270 2271 mutex_enter(&sc->sc_lock); 2272 struct ehci_soft_sitd *next = NULL; 2273 for (; sitd != NULL; sitd = next) { 2274 next = sitd->xfer_next; 2275 ehci_free_sitd_locked(sc, sitd); 2276 } 2277 mutex_exit(&sc->sc_lock); 2278 } 2279 2280 /***********/ 2281 2282 Static int 2283 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2284 void *buf, int buflen) 2285 { 2286 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2287 usb_hub_descriptor_t hubd; 2288 usb_port_status_t ps; 2289 uint16_t len, value, index; 2290 int l, totlen = 0; 2291 int port, i; 2292 uint32_t v; 2293 2294 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2295 2296 if (sc->sc_dying) 2297 return -1; 2298 2299 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, 2300 0, 0); 2301 2302 len = UGETW(req->wLength); 2303 value = UGETW(req->wValue); 2304 index = UGETW(req->wIndex); 2305 2306 #define C(x,y) ((x) | ((y) << 8)) 2307 switch (C(req->bRequest, req->bmRequestType)) { 2308 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2309 if (len == 0) 2310 break; 2311 switch (value) { 2312 case C(0, UDESC_DEVICE): { 2313 usb_device_descriptor_t devd; 2314 totlen = min(buflen, sizeof(devd)); 2315 memcpy(&devd, buf, totlen); 2316 USETW(devd.idVendor, sc->sc_id_vendor); 2317 memcpy(buf, &devd, totlen); 2318 break; 2319 2320 } 2321 #define sd ((usb_string_descriptor_t *)buf) 2322 case C(1, UDESC_STRING): 2323 /* Vendor */ 2324 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2325 break; 2326 case C(2, UDESC_STRING): 2327 /* Product */ 2328 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2329 break; 2330 #undef sd 2331 default: 2332 /* default from usbroothub */ 2333 return buflen; 2334 } 2335 break; 2336 2337 /* Hub requests */ 2338 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2339 break; 2340 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2341 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 2342 value, 0, 0); 2343 if (index < 1 || index > sc->sc_noport) { 2344 return -1; 2345 } 2346 port = EHCI_PORTSC(index); 2347 v = EOREAD4(sc, port); 2348 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2349 v &= ~EHCI_PS_CLEAR; 2350 switch (value) { 2351 case UHF_PORT_ENABLE: 2352 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2353 break; 2354 case UHF_PORT_SUSPEND: 2355 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2356 break; 2357 v &= ~EHCI_PS_SUSP; 2358 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2359 /* see USB2 spec ch. 7.1.7.7 */ 2360 usb_delay_ms(&sc->sc_bus, 20); 2361 EOWRITE4(sc, port, v); 2362 usb_delay_ms(&sc->sc_bus, 2); 2363 #ifdef DEBUG 2364 v = EOREAD4(sc, port); 2365 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2366 printf("ehci: resume failed: %x\n", v); 2367 #endif 2368 break; 2369 case UHF_PORT_POWER: 2370 if (sc->sc_hasppc) 2371 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2372 break; 2373 case UHF_PORT_TEST: 2374 DPRINTF("clear port test %d", index, 0, 0, 0); 2375 break; 2376 case UHF_PORT_INDICATOR: 2377 DPRINTF("clear port ind %d", index, 0, 0, 0); 2378 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2379 break; 2380 case UHF_C_PORT_CONNECTION: 2381 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2382 break; 2383 case UHF_C_PORT_ENABLE: 2384 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2385 break; 2386 case UHF_C_PORT_SUSPEND: 2387 /* how? */ 2388 break; 2389 case UHF_C_PORT_OVER_CURRENT: 2390 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2391 break; 2392 case UHF_C_PORT_RESET: 2393 sc->sc_isreset[index] = 0; 2394 break; 2395 default: 2396 return -1; 2397 } 2398 #if 0 2399 switch(value) { 2400 case UHF_C_PORT_CONNECTION: 2401 case UHF_C_PORT_ENABLE: 2402 case UHF_C_PORT_SUSPEND: 2403 case UHF_C_PORT_OVER_CURRENT: 2404 case UHF_C_PORT_RESET: 2405 default: 2406 break; 2407 } 2408 #endif 2409 break; 2410 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2411 if (len == 0) 2412 break; 2413 if ((value & 0xff) != 0) { 2414 return -1; 2415 } 2416 totlen = min(buflen, sizeof(hubd)); 2417 memcpy(&hubd, buf, totlen); 2418 hubd.bNbrPorts = sc->sc_noport; 2419 v = EOREAD4(sc, EHCI_HCSPARAMS); 2420 USETW(hubd.wHubCharacteristics, 2421 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2422 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2423 ? UHD_PORT_IND : 0); 2424 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2425 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2426 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2427 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2428 totlen = min(totlen, hubd.bDescLength); 2429 memcpy(buf, &hubd, totlen); 2430 break; 2431 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2432 if (len != 4) { 2433 return -1; 2434 } 2435 memset(buf, 0, len); /* ? XXX */ 2436 totlen = len; 2437 break; 2438 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2439 DPRINTF("get port status i=%d", index, 0, 0, 0); 2440 if (index < 1 || index > sc->sc_noport) { 2441 return -1; 2442 } 2443 if (len != 4) { 2444 return -1; 2445 } 2446 v = EOREAD4(sc, EHCI_PORTSC(index)); 2447 DPRINTF("port status=0x%04x", v, 0, 0, 0); 2448 2449 i = UPS_HIGH_SPEED; 2450 if (sc->sc_flags & EHCIF_ETTF) { 2451 /* 2452 * If we are doing embedded transaction translation, 2453 * then directly attached LS/FS devices are reset by 2454 * the EHCI controller itself. PSPD is encoded 2455 * the same way as in USBSTATUS. 2456 */ 2457 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2458 } 2459 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2460 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2461 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2462 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2463 if (v & EHCI_PS_PR) i |= UPS_RESET; 2464 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2465 if (sc->sc_vendor_port_status) 2466 i = sc->sc_vendor_port_status(sc, v, i); 2467 USETW(ps.wPortStatus, i); 2468 i = 0; 2469 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2470 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2471 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2472 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2473 USETW(ps.wPortChange, i); 2474 totlen = min(len, sizeof(ps)); 2475 memcpy(buf, &ps, totlen); 2476 break; 2477 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2478 return -1; 2479 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2480 break; 2481 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2482 if (index < 1 || index > sc->sc_noport) { 2483 return -1; 2484 } 2485 port = EHCI_PORTSC(index); 2486 v = EOREAD4(sc, port); 2487 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2488 v &= ~EHCI_PS_CLEAR; 2489 switch(value) { 2490 case UHF_PORT_ENABLE: 2491 EOWRITE4(sc, port, v | EHCI_PS_PE); 2492 break; 2493 case UHF_PORT_SUSPEND: 2494 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2495 break; 2496 case UHF_PORT_RESET: 2497 DPRINTF("reset port %d", index, 0, 0, 0); 2498 if (EHCI_PS_IS_LOWSPEED(v) 2499 && sc->sc_ncomp > 0 2500 && !(sc->sc_flags & EHCIF_ETTF)) { 2501 /* 2502 * Low speed device on non-ETTF controller or 2503 * unaccompanied controller, give up ownership. 2504 */ 2505 ehci_disown(sc, index, 1); 2506 break; 2507 } 2508 /* Start reset sequence. */ 2509 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2510 EOWRITE4(sc, port, v | EHCI_PS_PR); 2511 /* Wait for reset to complete. */ 2512 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2513 if (sc->sc_dying) { 2514 return -1; 2515 } 2516 /* 2517 * An embedded transaction translator will automatically 2518 * terminate the reset sequence so there's no need to 2519 * it. 2520 */ 2521 v = EOREAD4(sc, port); 2522 if (v & EHCI_PS_PR) { 2523 /* Terminate reset sequence. */ 2524 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2525 /* Wait for HC to complete reset. */ 2526 usb_delay_ms(&sc->sc_bus, 2527 EHCI_PORT_RESET_COMPLETE); 2528 if (sc->sc_dying) { 2529 return -1; 2530 } 2531 } 2532 2533 v = EOREAD4(sc, port); 2534 DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); 2535 if (v & EHCI_PS_PR) { 2536 printf("%s: port reset timeout\n", 2537 device_xname(sc->sc_dev)); 2538 return USBD_TIMEOUT; 2539 } 2540 if (!(v & EHCI_PS_PE)) { 2541 /* Not a high speed device, give up ownership.*/ 2542 ehci_disown(sc, index, 0); 2543 break; 2544 } 2545 sc->sc_isreset[index] = 1; 2546 DPRINTF("ehci port %d reset, status = 0x%08x", index, 2547 v, 0, 0); 2548 break; 2549 case UHF_PORT_POWER: 2550 DPRINTF("set port power %d (has PPC = %d)", index, 2551 sc->sc_hasppc, 0, 0); 2552 if (sc->sc_hasppc) 2553 EOWRITE4(sc, port, v | EHCI_PS_PP); 2554 break; 2555 case UHF_PORT_TEST: 2556 DPRINTF("set port test %d", index, 0, 0, 0); 2557 break; 2558 case UHF_PORT_INDICATOR: 2559 DPRINTF("set port ind %d", index, 0, 0, 0); 2560 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2561 break; 2562 default: 2563 return -1; 2564 } 2565 break; 2566 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2567 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2568 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2569 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2570 break; 2571 default: 2572 /* default from usbroothub */ 2573 DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); 2574 2575 return buflen; 2576 } 2577 2578 DPRINTF("returning %d", totlen, 0, 0, 0); 2579 2580 return totlen; 2581 } 2582 2583 Static void 2584 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2585 { 2586 int port; 2587 uint32_t v; 2588 2589 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2590 2591 DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); 2592 #ifdef DIAGNOSTIC 2593 if (sc->sc_npcomp != 0) { 2594 int i = (index-1) / sc->sc_npcomp; 2595 if (i >= sc->sc_ncomp) 2596 printf("%s: strange port\n", 2597 device_xname(sc->sc_dev)); 2598 else 2599 printf("%s: handing over %s speed device on " 2600 "port %d to %s\n", 2601 device_xname(sc->sc_dev), 2602 lowspeed ? "low" : "full", 2603 index, sc->sc_comps[i] ? 2604 device_xname(sc->sc_comps[i]) : 2605 "companion controller"); 2606 } else { 2607 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2608 } 2609 #endif 2610 port = EHCI_PORTSC(index); 2611 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2612 EOWRITE4(sc, port, v | EHCI_PS_PO); 2613 } 2614 2615 Static usbd_status 2616 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2617 { 2618 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2619 usbd_status err; 2620 2621 /* Insert last in queue. */ 2622 mutex_enter(&sc->sc_lock); 2623 err = usb_insert_transfer(xfer); 2624 mutex_exit(&sc->sc_lock); 2625 if (err) 2626 return err; 2627 2628 /* Pipe isn't running, start first */ 2629 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2630 } 2631 2632 Static usbd_status 2633 ehci_root_intr_start(struct usbd_xfer *xfer) 2634 { 2635 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2636 2637 if (sc->sc_dying) 2638 return USBD_IOERROR; 2639 2640 mutex_enter(&sc->sc_lock); 2641 sc->sc_intrxfer = xfer; 2642 mutex_exit(&sc->sc_lock); 2643 2644 return USBD_IN_PROGRESS; 2645 } 2646 2647 /* Abort a root interrupt request. */ 2648 Static void 2649 ehci_root_intr_abort(struct usbd_xfer *xfer) 2650 { 2651 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2652 2653 KASSERT(mutex_owned(&sc->sc_lock)); 2654 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2655 2656 sc->sc_intrxfer = NULL; 2657 2658 xfer->ux_status = USBD_CANCELLED; 2659 usb_transfer_complete(xfer); 2660 } 2661 2662 /* Close the root pipe. */ 2663 Static void 2664 ehci_root_intr_close(struct usbd_pipe *pipe) 2665 { 2666 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2667 2668 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2669 2670 KASSERT(mutex_owned(&sc->sc_lock)); 2671 2672 sc->sc_intrxfer = NULL; 2673 } 2674 2675 Static void 2676 ehci_root_intr_done(struct usbd_xfer *xfer) 2677 { 2678 } 2679 2680 /************************/ 2681 2682 Static ehci_soft_qh_t * 2683 ehci_alloc_sqh(ehci_softc_t *sc) 2684 { 2685 ehci_soft_qh_t *sqh; 2686 usbd_status err; 2687 int i, offs; 2688 usb_dma_t dma; 2689 2690 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2691 2692 mutex_enter(&sc->sc_lock); 2693 if (sc->sc_freeqhs == NULL) { 2694 DPRINTF("allocating chunk", 0, 0, 0, 0); 2695 mutex_exit(&sc->sc_lock); 2696 2697 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2698 EHCI_PAGE_SIZE, &dma); 2699 #ifdef EHCI_DEBUG 2700 if (err) 2701 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2702 #endif 2703 if (err) 2704 return NULL; 2705 2706 mutex_enter(&sc->sc_lock); 2707 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2708 offs = i * EHCI_SQH_SIZE; 2709 sqh = KERNADDR(&dma, offs); 2710 sqh->physaddr = DMAADDR(&dma, offs); 2711 sqh->dma = dma; 2712 sqh->offs = offs; 2713 sqh->next = sc->sc_freeqhs; 2714 sc->sc_freeqhs = sqh; 2715 } 2716 } 2717 sqh = sc->sc_freeqhs; 2718 sc->sc_freeqhs = sqh->next; 2719 mutex_exit(&sc->sc_lock); 2720 2721 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2722 sqh->next = NULL; 2723 return sqh; 2724 } 2725 2726 Static void 2727 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2728 { 2729 KASSERT(mutex_owned(&sc->sc_lock)); 2730 2731 sqh->next = sc->sc_freeqhs; 2732 sc->sc_freeqhs = sqh; 2733 } 2734 2735 Static ehci_soft_qtd_t * 2736 ehci_alloc_sqtd(ehci_softc_t *sc) 2737 { 2738 ehci_soft_qtd_t *sqtd = NULL; 2739 usbd_status err; 2740 int i, offs; 2741 usb_dma_t dma; 2742 2743 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2744 2745 mutex_enter(&sc->sc_lock); 2746 if (sc->sc_freeqtds == NULL) { 2747 DPRINTF("allocating chunk", 0, 0, 0, 0); 2748 mutex_exit(&sc->sc_lock); 2749 2750 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2751 EHCI_PAGE_SIZE, &dma); 2752 #ifdef EHCI_DEBUG 2753 if (err) 2754 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2755 #endif 2756 if (err) 2757 goto done; 2758 2759 mutex_enter(&sc->sc_lock); 2760 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2761 offs = i * EHCI_SQTD_SIZE; 2762 sqtd = KERNADDR(&dma, offs); 2763 sqtd->physaddr = DMAADDR(&dma, offs); 2764 sqtd->dma = dma; 2765 sqtd->offs = offs; 2766 2767 sqtd->nextqtd = sc->sc_freeqtds; 2768 sc->sc_freeqtds = sqtd; 2769 } 2770 } 2771 2772 sqtd = sc->sc_freeqtds; 2773 sc->sc_freeqtds = sqtd->nextqtd; 2774 mutex_exit(&sc->sc_lock); 2775 2776 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2777 sqtd->nextqtd = NULL; 2778 sqtd->xfer = NULL; 2779 2780 done: 2781 return sqtd; 2782 } 2783 2784 Static void 2785 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2786 { 2787 2788 mutex_enter(&sc->sc_lock); 2789 sqtd->nextqtd = sc->sc_freeqtds; 2790 sc->sc_freeqtds = sqtd; 2791 mutex_exit(&sc->sc_lock); 2792 } 2793 2794 Static int 2795 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2796 int alen, int rd, ehci_soft_qtd_t **sp) 2797 { 2798 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2799 uint16_t flags = xfer->ux_flags; 2800 2801 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2802 2803 ASSERT_SLEEPABLE(); 2804 KASSERT(sp); 2805 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2806 2807 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2808 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2809 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2810 KM_SLEEP); 2811 exfer->ex_nsqtd = nsqtd; 2812 2813 DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); 2814 2815 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2816 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2817 if (cur == NULL) 2818 goto nomem; 2819 exfer->ex_sqtds[j++] = cur; 2820 2821 cur->xfer = xfer; 2822 cur->len = 0; 2823 2824 } 2825 2826 *sp = exfer->ex_sqtds[0]; 2827 DPRINTF("return sqtd=%p", *sp, 0, 0, 0); 2828 2829 return 0; 2830 2831 nomem: 2832 ehci_free_sqtds(sc, exfer); 2833 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2834 DPRINTF("no memory", 0, 0, 0, 0); 2835 return ENOMEM; 2836 } 2837 2838 Static void 2839 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2840 { 2841 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2842 DPRINTF("exfer=%p", exfer, 0, 0, 0); 2843 2844 mutex_enter(&sc->sc_lock); 2845 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2846 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2847 2848 if (sqtd == NULL) 2849 break; 2850 2851 sqtd->nextqtd = sc->sc_freeqtds; 2852 sc->sc_freeqtds = sqtd; 2853 } 2854 mutex_exit(&sc->sc_lock); 2855 } 2856 2857 Static void 2858 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2859 { 2860 if (prev) { 2861 prev->nextqtd = sqtd; 2862 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2863 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2864 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2865 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2866 } 2867 } 2868 2869 Static void 2870 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2871 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2872 { 2873 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2874 usb_dma_t *dma = &xfer->ux_dmabuf; 2875 uint16_t flags = xfer->ux_flags; 2876 ehci_soft_qtd_t *sqtd, *prev; 2877 int tog = *toggle; 2878 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2879 int len = length; 2880 2881 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2882 DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); 2883 DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); 2884 2885 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2886 2887 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2888 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2889 EHCI_QTD_SET_CERR(3) 2890 ; 2891 2892 sqtd = prev = NULL; 2893 size_t curoffs = 0; 2894 size_t j = 0; 2895 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2896 sqtd = exfer->ex_sqtds[j++]; 2897 DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); 2898 2899 /* 2900 * The EHCI hardware can handle at most 5 pages and they do 2901 * not have to be contiguous 2902 */ 2903 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2904 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2905 size_t curlen = len; 2906 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2907 /* must use multiple TDs, fill as much as possible. */ 2908 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2909 2910 /* the length must be a multiple of the max size */ 2911 curlen -= curlen % mps; 2912 } 2913 KASSERT(curlen != 0); 2914 DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, 2915 curoffs, 0); 2916 2917 /* Fill the qTD */ 2918 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2919 sqtd->qtd.qtd_status = htole32( 2920 qtdstatus | 2921 EHCI_QTD_SET_BYTES(curlen) | 2922 EHCI_QTD_SET_TOGGLE(tog)); 2923 2924 /* Find number of pages we'll be using, insert dma addresses */ 2925 size_t pages = EHCI_NPAGES(curlen); 2926 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2927 size_t pageoffs = EHCI_PAGE(curoffs); 2928 for (size_t i = 0; i < pages; i++) { 2929 paddr_t a = DMAADDR(dma, 2930 pageoffs + i * EHCI_PAGE_SIZE); 2931 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2932 /* Cast up to avoid compiler warnings */ 2933 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2934 DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, 2935 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2936 le32toh(sqtd->qtd.qtd_buffer[i])); 2937 } 2938 /* First buffer pointer requires a page offset to start at */ 2939 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2940 2941 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2942 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2943 2944 sqtd->len = curlen; 2945 2946 DPRINTF(" va %p pa %p len %d", va, 2947 DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2948 2949 ehci_append_sqtd(sqtd, prev); 2950 2951 if (((curlen + mps - 1) / mps) & 1) { 2952 tog ^= 1; 2953 } 2954 2955 curoffs += curlen; 2956 len -= curlen; 2957 } 2958 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2959 xfer, length, len, mps, exfer->ex_nsqtd, j); 2960 2961 if (!isread && 2962 (flags & USBD_FORCE_SHORT_XFER) && 2963 length % mps == 0) { 2964 /* Force a 0 length transfer at the end. */ 2965 2966 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2967 exfer->ex_nsqtd); 2968 prev = sqtd; 2969 sqtd = exfer->ex_sqtds[j++]; 2970 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 2971 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2972 sqtd->qtd.qtd_status = htole32( 2973 qtdstatus | 2974 EHCI_QTD_SET_BYTES(0) | 2975 EHCI_QTD_SET_TOGGLE(tog)); 2976 2977 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2978 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2979 2980 ehci_append_sqtd(sqtd, prev); 2981 tog ^= 1; 2982 } 2983 2984 *lsqtd = sqtd; 2985 *toggle = tog; 2986 } 2987 2988 Static ehci_soft_itd_t * 2989 ehci_alloc_itd(ehci_softc_t *sc) 2990 { 2991 struct ehci_soft_itd *itd, *freeitd; 2992 usbd_status err; 2993 usb_dma_t dma; 2994 2995 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2996 2997 mutex_enter(&sc->sc_lock); 2998 2999 freeitd = LIST_FIRST(&sc->sc_freeitds); 3000 if (freeitd == NULL) { 3001 DPRINTF("allocating chunk", 0, 0, 0, 0); 3002 mutex_exit(&sc->sc_lock); 3003 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3004 EHCI_PAGE_SIZE, &dma); 3005 3006 if (err) { 3007 DPRINTF("alloc returned %d", err, 0, 0, 0); 3008 return NULL; 3009 } 3010 mutex_enter(&sc->sc_lock); 3011 3012 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3013 int offs = i * EHCI_ITD_SIZE; 3014 itd = KERNADDR(&dma, offs); 3015 itd->physaddr = DMAADDR(&dma, offs); 3016 itd->dma = dma; 3017 itd->offs = offs; 3018 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3019 } 3020 freeitd = LIST_FIRST(&sc->sc_freeitds); 3021 } 3022 3023 itd = freeitd; 3024 LIST_REMOVE(itd, free_list); 3025 mutex_exit(&sc->sc_lock); 3026 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3027 3028 itd->frame_list.next = NULL; 3029 itd->frame_list.prev = NULL; 3030 itd->xfer_next = NULL; 3031 itd->slot = 0; 3032 3033 return itd; 3034 } 3035 3036 Static ehci_soft_sitd_t * 3037 ehci_alloc_sitd(ehci_softc_t *sc) 3038 { 3039 struct ehci_soft_sitd *sitd, *freesitd; 3040 usbd_status err; 3041 int i, offs; 3042 usb_dma_t dma; 3043 3044 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3045 3046 mutex_enter(&sc->sc_lock); 3047 freesitd = LIST_FIRST(&sc->sc_freesitds); 3048 if (freesitd == NULL) { 3049 DPRINTF("allocating chunk", 0, 0, 0, 0); 3050 mutex_exit(&sc->sc_lock); 3051 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3052 EHCI_PAGE_SIZE, &dma); 3053 3054 if (err) { 3055 DPRINTF("alloc returned %d", err, 0, 0, 3056 0); 3057 return NULL; 3058 } 3059 3060 mutex_enter(&sc->sc_lock); 3061 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3062 offs = i * EHCI_SITD_SIZE; 3063 sitd = KERNADDR(&dma, offs); 3064 sitd->physaddr = DMAADDR(&dma, offs); 3065 sitd->dma = dma; 3066 sitd->offs = offs; 3067 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3068 } 3069 freesitd = LIST_FIRST(&sc->sc_freesitds); 3070 } 3071 3072 sitd = freesitd; 3073 LIST_REMOVE(sitd, free_list); 3074 mutex_exit(&sc->sc_lock); 3075 3076 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3077 3078 sitd->frame_list.next = NULL; 3079 sitd->frame_list.prev = NULL; 3080 sitd->xfer_next = NULL; 3081 sitd->slot = 0; 3082 3083 return sitd; 3084 } 3085 3086 /****************/ 3087 3088 /* 3089 * Close a reqular pipe. 3090 * Assumes that there are no pending transactions. 3091 */ 3092 Static void 3093 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3094 { 3095 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3096 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3097 ehci_soft_qh_t *sqh = epipe->sqh; 3098 3099 KASSERT(mutex_owned(&sc->sc_lock)); 3100 3101 ehci_rem_qh(sc, sqh, head); 3102 ehci_free_sqh(sc, epipe->sqh); 3103 } 3104 3105 /* 3106 * Abort a device request. 3107 * If this routine is called at splusb() it guarantees that the request 3108 * will be removed from the hardware scheduling and that the callback 3109 * for it will be called with USBD_CANCELLED status. 3110 * It's impossible to guarantee that the requested transfer will not 3111 * have happened since the hardware runs concurrently. 3112 * If the transaction has already happened we rely on the ordinary 3113 * interrupt processing to process it. 3114 * XXX This is most probably wrong. 3115 * XXXMRG this doesn't make sense anymore. 3116 */ 3117 Static void 3118 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3119 { 3120 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3121 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3122 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3123 ehci_soft_qh_t *sqh = epipe->sqh; 3124 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3125 ehci_physaddr_t cur; 3126 uint32_t qhstatus; 3127 int hit; 3128 int wake; 3129 3130 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3131 3132 DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); 3133 3134 KASSERT(mutex_owned(&sc->sc_lock)); 3135 ASSERT_SLEEPABLE(); 3136 3137 if (sc->sc_dying) { 3138 /* If we're dying, just do the software part. */ 3139 xfer->ux_status = status; /* make software ignore it */ 3140 callout_stop(&xfer->ux_callout); 3141 usb_transfer_complete(xfer); 3142 return; 3143 } 3144 3145 /* 3146 * If an abort is already in progress then just wait for it to 3147 * complete and return. 3148 */ 3149 if (xfer->ux_hcflags & UXFER_ABORTING) { 3150 DPRINTF("already aborting", 0, 0, 0, 0); 3151 #ifdef DIAGNOSTIC 3152 if (status == USBD_TIMEOUT) 3153 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3154 #endif 3155 /* Override the status which might be USBD_TIMEOUT. */ 3156 xfer->ux_status = status; 3157 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3158 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3159 while (xfer->ux_hcflags & UXFER_ABORTING) 3160 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3161 return; 3162 } 3163 xfer->ux_hcflags |= UXFER_ABORTING; 3164 3165 /* 3166 * Step 1: Make interrupt routine and hardware ignore xfer. 3167 */ 3168 xfer->ux_status = status; /* make software ignore it */ 3169 callout_stop(&xfer->ux_callout); 3170 ehci_del_intr_list(sc, exfer); 3171 3172 usb_syncmem(&sqh->dma, 3173 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3174 sizeof(sqh->qh.qh_qtd.qtd_status), 3175 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3176 qhstatus = sqh->qh.qh_qtd.qtd_status; 3177 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3178 usb_syncmem(&sqh->dma, 3179 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3180 sizeof(sqh->qh.qh_qtd.qtd_status), 3181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3182 3183 if (exfer->ex_type == EX_CTRL) { 3184 fsqtd = exfer->ex_setup; 3185 lsqtd = exfer->ex_status; 3186 } else { 3187 fsqtd = exfer->ex_sqtdstart; 3188 lsqtd = exfer->ex_sqtdend; 3189 } 3190 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3191 usb_syncmem(&sqtd->dma, 3192 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3193 sizeof(sqtd->qtd.qtd_status), 3194 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3195 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3196 usb_syncmem(&sqtd->dma, 3197 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3198 sizeof(sqtd->qtd.qtd_status), 3199 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3200 if (sqtd == lsqtd) 3201 break; 3202 } 3203 3204 /* 3205 * Step 2: Wait until we know hardware has finished any possible 3206 * use of the xfer. Also make sure the soft interrupt routine 3207 * has run. 3208 */ 3209 ehci_sync_hc(sc); 3210 sc->sc_softwake = 1; 3211 usb_schedsoftintr(&sc->sc_bus); 3212 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3213 3214 /* 3215 * Step 3: Remove any vestiges of the xfer from the hardware. 3216 * The complication here is that the hardware may have executed 3217 * beyond the xfer we're trying to abort. So as we're scanning 3218 * the TDs of this xfer we check if the hardware points to 3219 * any of them. 3220 */ 3221 3222 usb_syncmem(&sqh->dma, 3223 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3224 sizeof(sqh->qh.qh_curqtd), 3225 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3226 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3227 hit = 0; 3228 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3229 hit |= cur == sqtd->physaddr; 3230 if (sqtd == lsqtd) 3231 break; 3232 } 3233 sqtd = sqtd->nextqtd; 3234 /* Zap curqtd register if hardware pointed inside the xfer. */ 3235 if (hit && sqtd != NULL) { 3236 DPRINTF("cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3237 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3238 usb_syncmem(&sqh->dma, 3239 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3240 sizeof(sqh->qh.qh_curqtd), 3241 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3242 sqh->qh.qh_qtd.qtd_status = qhstatus; 3243 usb_syncmem(&sqh->dma, 3244 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3245 sizeof(sqh->qh.qh_qtd.qtd_status), 3246 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3247 } else { 3248 DPRINTF("no hit", 0, 0, 0, 0); 3249 usb_syncmem(&sqh->dma, 3250 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3251 sizeof(sqh->qh.qh_curqtd), 3252 BUS_DMASYNC_PREREAD); 3253 } 3254 3255 /* 3256 * Step 4: Execute callback. 3257 */ 3258 #ifdef DIAGNOSTIC 3259 exfer->ex_isdone = true; 3260 #endif 3261 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3262 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3263 usb_transfer_complete(xfer); 3264 if (wake) { 3265 cv_broadcast(&xfer->ux_hccv); 3266 } 3267 3268 KASSERT(mutex_owned(&sc->sc_lock)); 3269 } 3270 3271 Static void 3272 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3273 { 3274 ehci_isoc_trans_t trans_status; 3275 struct ehci_xfer *exfer; 3276 ehci_softc_t *sc; 3277 struct ehci_soft_itd *itd; 3278 struct ehci_soft_sitd *sitd; 3279 int i, wake; 3280 3281 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3282 3283 exfer = EHCI_XFER2EXFER(xfer); 3284 sc = EHCI_XFER2SC(xfer); 3285 3286 DPRINTF("xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3287 3288 KASSERT(mutex_owned(&sc->sc_lock)); 3289 3290 if (sc->sc_dying) { 3291 xfer->ux_status = status; 3292 callout_stop(&xfer->ux_callout); 3293 usb_transfer_complete(xfer); 3294 return; 3295 } 3296 3297 if (xfer->ux_hcflags & UXFER_ABORTING) { 3298 DPRINTF("already aborting", 0, 0, 0, 0); 3299 3300 #ifdef DIAGNOSTIC 3301 if (status == USBD_TIMEOUT) 3302 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3303 #endif 3304 3305 xfer->ux_status = status; 3306 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3307 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3308 while (xfer->ux_hcflags & UXFER_ABORTING) 3309 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3310 goto done; 3311 } 3312 xfer->ux_hcflags |= UXFER_ABORTING; 3313 3314 xfer->ux_status = status; 3315 callout_stop(&xfer->ux_callout); 3316 ehci_del_intr_list(sc, exfer); 3317 3318 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3319 for (itd = exfer->ex_itdstart; itd != NULL; 3320 itd = itd->xfer_next) { 3321 usb_syncmem(&itd->dma, 3322 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3323 sizeof(itd->itd.itd_ctl), 3324 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3325 3326 for (i = 0; i < 8; i++) { 3327 trans_status = le32toh(itd->itd.itd_ctl[i]); 3328 trans_status &= ~EHCI_ITD_ACTIVE; 3329 itd->itd.itd_ctl[i] = htole32(trans_status); 3330 } 3331 3332 usb_syncmem(&itd->dma, 3333 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3334 sizeof(itd->itd.itd_ctl), 3335 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3336 } 3337 } else { 3338 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3339 sitd = sitd->xfer_next) { 3340 usb_syncmem(&sitd->dma, 3341 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3342 sizeof(sitd->sitd.sitd_buffer), 3343 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3344 3345 trans_status = le32toh(sitd->sitd.sitd_trans); 3346 trans_status &= ~EHCI_SITD_ACTIVE; 3347 sitd->sitd.sitd_trans = htole32(trans_status); 3348 3349 usb_syncmem(&sitd->dma, 3350 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3351 sizeof(sitd->sitd.sitd_buffer), 3352 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3353 } 3354 } 3355 3356 sc->sc_softwake = 1; 3357 usb_schedsoftintr(&sc->sc_bus); 3358 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3359 3360 #ifdef DIAGNOSTIC 3361 exfer->ex_isdone = true; 3362 #endif 3363 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3364 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3365 usb_transfer_complete(xfer); 3366 if (wake) { 3367 cv_broadcast(&xfer->ux_hccv); 3368 } 3369 3370 done: 3371 KASSERT(mutex_owned(&sc->sc_lock)); 3372 return; 3373 } 3374 3375 Static void 3376 ehci_timeout(void *addr) 3377 { 3378 struct usbd_xfer *xfer = addr; 3379 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3380 struct usbd_pipe *pipe = xfer->ux_pipe; 3381 struct usbd_device *dev = pipe->up_dev; 3382 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3383 3384 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3385 3386 DPRINTF("exfer %p", exfer, 0, 0, 0); 3387 #ifdef EHCI_DEBUG 3388 if (ehcidebug >= 2) 3389 usbd_dump_pipe(pipe); 3390 #endif 3391 3392 if (sc->sc_dying) { 3393 mutex_enter(&sc->sc_lock); 3394 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3395 mutex_exit(&sc->sc_lock); 3396 return; 3397 } 3398 3399 /* Execute the abort in a process context. */ 3400 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3401 USB_TASKQ_MPSAFE); 3402 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3403 } 3404 3405 Static void 3406 ehci_timeout_task(void *addr) 3407 { 3408 struct usbd_xfer *xfer = addr; 3409 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3410 3411 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3412 3413 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3414 3415 mutex_enter(&sc->sc_lock); 3416 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3417 mutex_exit(&sc->sc_lock); 3418 } 3419 3420 /************************/ 3421 3422 Static int 3423 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3424 { 3425 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3426 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3427 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3428 usb_device_request_t *req = &xfer->ux_request; 3429 ehci_soft_qtd_t *setup, *status, *next; 3430 int isread = req->bmRequestType & UT_READ; 3431 int len = xfer->ux_bufsize; 3432 int err; 3433 3434 exfer->ex_type = EX_CTRL; 3435 exfer->ex_status = NULL; 3436 exfer->ex_data = NULL; 3437 exfer->ex_setup = ehci_alloc_sqtd(sc); 3438 if (exfer->ex_setup == NULL) { 3439 err = ENOMEM; 3440 goto bad1; 3441 } 3442 exfer->ex_status = ehci_alloc_sqtd(sc); 3443 if (exfer->ex_status == NULL) { 3444 err = ENOMEM; 3445 goto bad2; 3446 } 3447 setup = exfer->ex_setup; 3448 status = exfer->ex_status; 3449 exfer->ex_nsqtd = 0; 3450 next = status; 3451 /* Set up data transaction */ 3452 if (len != 0) { 3453 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3454 &exfer->ex_data); 3455 if (err) 3456 goto bad3; 3457 next = exfer->ex_data; 3458 } 3459 3460 /* Clear toggle */ 3461 setup->qtd.qtd_status = htole32( 3462 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3463 EHCI_QTD_SET_TOGGLE(0) | 3464 EHCI_QTD_SET_BYTES(sizeof(*req)) 3465 ); 3466 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3467 setup->qtd.qtd_buffer_hi[0] = 0; 3468 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3469 setup->nextqtd = next; 3470 setup->xfer = xfer; 3471 setup->len = sizeof(*req); 3472 3473 status->qtd.qtd_status = htole32( 3474 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3475 EHCI_QTD_SET_TOGGLE(1) | 3476 EHCI_QTD_IOC 3477 ); 3478 status->qtd.qtd_buffer[0] = 0; 3479 status->qtd.qtd_buffer_hi[0] = 0; 3480 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3481 status->nextqtd = NULL; 3482 status->xfer = xfer; 3483 status->len = 0; 3484 3485 return 0; 3486 bad3: 3487 ehci_free_sqtd(sc, exfer->ex_status); 3488 bad2: 3489 ehci_free_sqtd(sc, exfer->ex_setup); 3490 bad1: 3491 return err; 3492 } 3493 3494 Static void 3495 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3496 { 3497 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3498 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3499 3500 KASSERT(ex->ex_type == EX_CTRL); 3501 3502 ehci_free_sqtd(sc, ex->ex_setup); 3503 ehci_free_sqtd(sc, ex->ex_status); 3504 ehci_free_sqtds(sc, ex); 3505 if (ex->ex_nsqtd) 3506 kmem_free(ex->ex_sqtds, 3507 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3508 } 3509 3510 Static usbd_status 3511 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3512 { 3513 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3514 usbd_status err; 3515 3516 /* Insert last in queue. */ 3517 mutex_enter(&sc->sc_lock); 3518 err = usb_insert_transfer(xfer); 3519 mutex_exit(&sc->sc_lock); 3520 if (err) 3521 return err; 3522 3523 /* Pipe isn't running, start first */ 3524 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3525 } 3526 3527 Static usbd_status 3528 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3529 { 3530 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3531 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3532 usb_device_request_t *req = &xfer->ux_request; 3533 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3534 ehci_soft_qtd_t *setup, *status, *next; 3535 ehci_soft_qh_t *sqh; 3536 3537 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3538 3539 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3540 3541 if (sc->sc_dying) 3542 return USBD_IOERROR; 3543 3544 const int isread = req->bmRequestType & UT_READ; 3545 const int len = UGETW(req->wLength); 3546 3547 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 3548 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3549 UGETW(req->wIndex)); 3550 DPRINTF("len=%d, addr=%d, endpt=%d", len, epipe->pipe.up_dev->ud_addr, 3551 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3552 3553 sqh = epipe->sqh; 3554 3555 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3556 "address QH %" __PRIuBIT " pipe %d\n", 3557 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3558 epipe->pipe.up_dev->ud_addr); 3559 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3560 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3561 "MPS QH %" __PRIuBIT " pipe %d\n", 3562 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3563 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3564 3565 setup = exfer->ex_setup; 3566 status = exfer->ex_status; 3567 3568 DPRINTF("setup %p status %p data %p", setup, status, exfer->ex_data, 0); 3569 KASSERTMSG(setup != NULL && status != NULL, 3570 "Failed memory allocation, setup %p status %p", 3571 setup, status); 3572 3573 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3574 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3575 3576 /* Clear toggle */ 3577 setup->qtd.qtd_status &= ~htole32( 3578 EHCI_QTD_STATUS_MASK | 3579 EHCI_QTD_BYTES_MASK | 3580 EHCI_QTD_TOGGLE_MASK | 3581 EHCI_QTD_CERR_MASK 3582 ); 3583 setup->qtd.qtd_status |= htole32( 3584 EHCI_QTD_ACTIVE | 3585 EHCI_QTD_SET_CERR(3) | 3586 EHCI_QTD_SET_TOGGLE(0) | 3587 EHCI_QTD_SET_BYTES(sizeof(*req)) 3588 ); 3589 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3590 setup->qtd.qtd_buffer_hi[0] = 0; 3591 3592 next = status; 3593 status->qtd.qtd_status &= ~htole32( 3594 EHCI_QTD_STATUS_MASK | 3595 EHCI_QTD_PID_MASK | 3596 EHCI_QTD_BYTES_MASK | 3597 EHCI_QTD_TOGGLE_MASK | 3598 EHCI_QTD_CERR_MASK 3599 ); 3600 status->qtd.qtd_status |= htole32( 3601 EHCI_QTD_ACTIVE | 3602 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3603 EHCI_QTD_SET_CERR(3) | 3604 EHCI_QTD_SET_TOGGLE(1) | 3605 EHCI_QTD_SET_BYTES(0) | 3606 EHCI_QTD_IOC 3607 ); 3608 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3609 3610 KASSERT(exfer->ex_isdone); 3611 #ifdef DIAGNOSTIC 3612 exfer->ex_isdone = false; 3613 #endif 3614 3615 /* Set up data transaction */ 3616 if (len != 0) { 3617 ehci_soft_qtd_t *end; 3618 3619 /* Start toggle at 1. */ 3620 int toggle = 1; 3621 next = exfer->ex_data; 3622 KASSERTMSG(next != NULL, "Failed memory allocation"); 3623 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3624 end->nextqtd = status; 3625 end->qtd.qtd_next = end->qtd.qtd_altnext = 3626 htole32(status->physaddr); 3627 3628 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3629 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3630 3631 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3632 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3633 } 3634 3635 setup->nextqtd = next; 3636 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3637 3638 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3639 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3640 3641 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3642 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3643 3644 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3645 3646 #ifdef EHCI_DEBUG 3647 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3648 ehci_dump_sqh(sqh); 3649 ehci_dump_sqtds(setup); 3650 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3651 #endif 3652 3653 mutex_enter(&sc->sc_lock); 3654 3655 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3656 ehci_set_qh_qtd(sqh, setup); 3657 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3658 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3659 ehci_timeout, xfer); 3660 } 3661 ehci_add_intr_list(sc, exfer); 3662 xfer->ux_status = USBD_IN_PROGRESS; 3663 mutex_exit(&sc->sc_lock); 3664 3665 #if 0 3666 #ifdef EHCI_DEBUG 3667 DPRINTFN(10, "status=%x, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3668 // delay(10000); 3669 ehci_dump_regs(sc); 3670 ehci_dump_sqh(sc->sc_async_head); 3671 ehci_dump_sqh(sqh); 3672 ehci_dump_sqtds(setup); 3673 #endif 3674 #endif 3675 3676 return USBD_IN_PROGRESS; 3677 } 3678 3679 Static void 3680 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3681 { 3682 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3683 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3684 usb_device_request_t *req = &xfer->ux_request; 3685 int len = UGETW(req->wLength); 3686 int rd = req->bmRequestType & UT_READ; 3687 3688 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3689 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3690 3691 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3692 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3693 3694 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3695 BUS_DMASYNC_POSTWRITE); 3696 if (len) 3697 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3698 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3699 3700 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3701 } 3702 3703 /* Abort a device control request. */ 3704 Static void 3705 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3706 { 3707 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3708 3709 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3710 ehci_abort_xfer(xfer, USBD_CANCELLED); 3711 } 3712 3713 /* Close a device control pipe. */ 3714 Static void 3715 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3716 { 3717 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3718 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3719 3720 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3721 3722 KASSERT(mutex_owned(&sc->sc_lock)); 3723 3724 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3725 3726 ehci_close_pipe(pipe, sc->sc_async_head); 3727 } 3728 3729 /* 3730 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3731 * qTD status, or miss signalling occasionally under heavy load. If the host 3732 * machine is too fast, we we can miss transaction completion - when we scan 3733 * the active list the transaction still seems to be active. This generally 3734 * exhibits itself as a umass stall that never recovers. 3735 * 3736 * We work around this behaviour by setting up this callback after any softintr 3737 * that completes with transactions still pending, giving us another chance to 3738 * check for completion after the writeback has taken place. 3739 */ 3740 Static void 3741 ehci_intrlist_timeout(void *arg) 3742 { 3743 ehci_softc_t *sc = arg; 3744 3745 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3746 3747 usb_schedsoftintr(&sc->sc_bus); 3748 } 3749 3750 /************************/ 3751 3752 Static int 3753 ehci_device_bulk_init(struct usbd_xfer *xfer) 3754 { 3755 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3756 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3757 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3758 int endpt = ed->bEndpointAddress; 3759 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3760 int len = xfer->ux_bufsize; 3761 int err = 0; 3762 3763 exfer->ex_type = EX_BULK; 3764 exfer->ex_nsqtd = 0; 3765 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3766 &exfer->ex_sqtdstart); 3767 3768 return err; 3769 } 3770 3771 Static void 3772 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3773 { 3774 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3775 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3776 3777 KASSERT(ex->ex_type == EX_BULK); 3778 3779 ehci_free_sqtds(sc, ex); 3780 if (ex->ex_nsqtd) 3781 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3782 } 3783 3784 Static usbd_status 3785 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3786 { 3787 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3788 usbd_status err; 3789 3790 /* Insert last in queue. */ 3791 mutex_enter(&sc->sc_lock); 3792 err = usb_insert_transfer(xfer); 3793 mutex_exit(&sc->sc_lock); 3794 if (err) 3795 return err; 3796 3797 /* Pipe isn't running, start first */ 3798 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3799 } 3800 3801 Static usbd_status 3802 ehci_device_bulk_start(struct usbd_xfer *xfer) 3803 { 3804 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3805 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3806 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3807 ehci_soft_qh_t *sqh; 3808 ehci_soft_qtd_t *end; 3809 int len, isread, endpt; 3810 3811 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3812 3813 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3814 xfer->ux_flags, 0); 3815 3816 if (sc->sc_dying) 3817 return USBD_IOERROR; 3818 3819 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3820 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3821 3822 len = xfer->ux_length; 3823 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3824 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3825 sqh = epipe->sqh; 3826 3827 KASSERT(exfer->ex_isdone); 3828 #ifdef DIAGNOSTIC 3829 exfer->ex_isdone = false; 3830 #endif 3831 3832 /* Take lock here to protect nexttoggle */ 3833 mutex_enter(&sc->sc_lock); 3834 3835 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3836 3837 exfer->ex_sqtdend = end; 3838 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3839 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3840 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3841 3842 #ifdef EHCI_DEBUG 3843 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3844 ehci_dump_sqh(sqh); 3845 ehci_dump_sqtds(exfer->ex_sqtdstart); 3846 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3847 #endif 3848 3849 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3850 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3851 3852 /* also does usb_syncmem(sqh) */ 3853 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3854 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3855 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3856 ehci_timeout, xfer); 3857 } 3858 ehci_add_intr_list(sc, exfer); 3859 xfer->ux_status = USBD_IN_PROGRESS; 3860 mutex_exit(&sc->sc_lock); 3861 3862 #if 0 3863 #ifdef EHCI_DEBUG 3864 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3865 // delay(10000); 3866 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3867 ehci_dump_regs(sc); 3868 #if 0 3869 printf("async_head:\n"); 3870 ehci_dump_sqh(sc->sc_async_head); 3871 #endif 3872 DPRINTF("sqh:", 0, 0, 0, 0); 3873 ehci_dump_sqh(sqh); 3874 ehci_dump_sqtds(exfer->ex_sqtdstart); 3875 #endif 3876 #endif 3877 3878 return USBD_IN_PROGRESS; 3879 } 3880 3881 Static void 3882 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3883 { 3884 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3885 3886 DPRINTF("xfer %p", xfer, 0, 0, 0); 3887 ehci_abort_xfer(xfer, USBD_CANCELLED); 3888 } 3889 3890 /* 3891 * Close a device bulk pipe. 3892 */ 3893 Static void 3894 ehci_device_bulk_close(struct usbd_pipe *pipe) 3895 { 3896 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3897 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3898 3899 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3900 3901 KASSERT(mutex_owned(&sc->sc_lock)); 3902 3903 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3904 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3905 ehci_close_pipe(pipe, sc->sc_async_head); 3906 } 3907 3908 Static void 3909 ehci_device_bulk_done(struct usbd_xfer *xfer) 3910 { 3911 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3912 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3913 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3914 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3915 3916 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3917 3918 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 3919 3920 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3921 3922 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3923 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3924 3925 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3926 } 3927 3928 /************************/ 3929 3930 Static usbd_status 3931 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3932 { 3933 struct ehci_soft_islot *isp; 3934 int islot, lev; 3935 3936 /* Find a poll rate that is large enough. */ 3937 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3938 if (EHCI_ILEV_IVAL(lev) <= ival) 3939 break; 3940 3941 /* Pick an interrupt slot at the right level. */ 3942 /* XXX could do better than picking at random */ 3943 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3944 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3945 3946 sqh->islot = islot; 3947 isp = &sc->sc_islots[islot]; 3948 mutex_enter(&sc->sc_lock); 3949 ehci_add_qh(sc, sqh, isp->sqh); 3950 mutex_exit(&sc->sc_lock); 3951 3952 return USBD_NORMAL_COMPLETION; 3953 } 3954 3955 3956 Static int 3957 ehci_device_intr_init(struct usbd_xfer *xfer) 3958 { 3959 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3960 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3961 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3962 int endpt = ed->bEndpointAddress; 3963 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3964 int len = xfer->ux_bufsize; 3965 int err; 3966 3967 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3968 3969 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3970 xfer->ux_flags, 0); 3971 3972 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3973 KASSERT(len != 0); 3974 3975 exfer->ex_type = EX_INTR; 3976 exfer->ex_nsqtd = 0; 3977 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3978 &exfer->ex_sqtdstart); 3979 3980 return err; 3981 } 3982 3983 Static void 3984 ehci_device_intr_fini(struct usbd_xfer *xfer) 3985 { 3986 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3987 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3988 3989 KASSERT(ex->ex_type == EX_INTR); 3990 3991 ehci_free_sqtds(sc, ex); 3992 if (ex->ex_nsqtd) 3993 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3994 } 3995 3996 Static usbd_status 3997 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3998 { 3999 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4000 usbd_status err; 4001 4002 /* Insert last in queue. */ 4003 mutex_enter(&sc->sc_lock); 4004 err = usb_insert_transfer(xfer); 4005 mutex_exit(&sc->sc_lock); 4006 if (err) 4007 return err; 4008 4009 /* 4010 * Pipe isn't running (otherwise err would be USBD_INPROG), 4011 * so start it first. 4012 */ 4013 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4014 } 4015 4016 Static usbd_status 4017 ehci_device_intr_start(struct usbd_xfer *xfer) 4018 { 4019 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4020 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4021 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4022 ehci_soft_qtd_t *end; 4023 ehci_soft_qh_t *sqh; 4024 int len, isread, endpt; 4025 4026 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4027 4028 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4029 xfer->ux_flags, 0); 4030 4031 if (sc->sc_dying) 4032 return USBD_IOERROR; 4033 4034 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4035 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4036 4037 len = xfer->ux_length; 4038 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4039 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4040 sqh = epipe->sqh; 4041 4042 KASSERT(exfer->ex_isdone); 4043 #ifdef DIAGNOSTIC 4044 exfer->ex_isdone = false; 4045 #endif 4046 4047 /* Take lock to protect nexttoggle */ 4048 mutex_enter(&sc->sc_lock); 4049 4050 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4051 4052 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4053 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4054 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4055 exfer->ex_sqtdend = end; 4056 4057 #ifdef EHCI_DEBUG 4058 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4059 ehci_dump_sqh(sqh); 4060 ehci_dump_sqtds(exfer->ex_sqtdstart); 4061 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4062 #endif 4063 4064 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4065 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4066 4067 /* also does usb_syncmem(sqh) */ 4068 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4069 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4070 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4071 ehci_timeout, xfer); 4072 } 4073 ehci_add_intr_list(sc, exfer); 4074 xfer->ux_status = USBD_IN_PROGRESS; 4075 mutex_exit(&sc->sc_lock); 4076 4077 #if 0 4078 #ifdef EHCI_DEBUG 4079 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4080 // delay(10000); 4081 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4082 ehci_dump_regs(sc); 4083 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4084 ehci_dump_sqh(sqh); 4085 ehci_dump_sqtds(exfer->ex_sqtdstart); 4086 #endif 4087 #endif 4088 4089 return USBD_IN_PROGRESS; 4090 } 4091 4092 Static void 4093 ehci_device_intr_abort(struct usbd_xfer *xfer) 4094 { 4095 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4096 4097 DPRINTF("xfer=%p", xfer, 0, 0, 0); 4098 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4099 4100 /* 4101 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4102 * async doorbell. That's dependent on the async list, wheras 4103 * intr xfers are periodic, should not use this? 4104 */ 4105 ehci_abort_xfer(xfer, USBD_CANCELLED); 4106 } 4107 4108 Static void 4109 ehci_device_intr_close(struct usbd_pipe *pipe) 4110 { 4111 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4112 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4113 struct ehci_soft_islot *isp; 4114 4115 KASSERT(mutex_owned(&sc->sc_lock)); 4116 4117 isp = &sc->sc_islots[epipe->sqh->islot]; 4118 ehci_close_pipe(pipe, isp->sqh); 4119 } 4120 4121 Static void 4122 ehci_device_intr_done(struct usbd_xfer *xfer) 4123 { 4124 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4125 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4126 int isread, endpt; 4127 4128 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4129 4130 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4131 0, 0); 4132 4133 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4134 4135 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4136 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4137 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4138 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4139 } 4140 4141 /************************/ 4142 Static int 4143 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4144 { 4145 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4146 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4147 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4148 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4149 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4150 int i, k, frames; 4151 u_int huba, dir; 4152 int err; 4153 4154 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4155 4156 start = NULL; 4157 sitd = NULL; 4158 4159 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4160 xfer->ux_flags, 0); 4161 4162 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4163 KASSERT(xfer->ux_nframes != 0); 4164 KASSERT(exfer->ex_isdone); 4165 4166 exfer->ex_type = EX_FS_ISOC; 4167 /* 4168 * Step 1: Allocate and initialize sitds. 4169 */ 4170 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4171 if (i > 16 || i == 0) { 4172 /* Spec page 271 says intervals > 16 are invalid */ 4173 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4174 4175 return EINVAL; 4176 } 4177 4178 frames = xfer->ux_nframes; 4179 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4180 sitd = ehci_alloc_sitd(sc); 4181 if (sitd == NULL) { 4182 err = ENOMEM; 4183 goto fail; 4184 } 4185 4186 if (prev) 4187 prev->xfer_next = sitd; 4188 else 4189 start = sitd; 4190 4191 huba = dev->ud_myhsport->up_parent->ud_addr; 4192 4193 #if 0 4194 if (sc->sc_flags & EHCIF_FREESCALE) { 4195 // Set hub address to 0 if embedded TT is used. 4196 if (huba == sc->sc_addr) 4197 huba = 0; 4198 } 4199 #endif 4200 4201 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4202 dir = UE_GET_DIR(k) ? 1 : 0; 4203 sitd->sitd.sitd_endp = 4204 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4205 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4206 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4207 EHCI_SITD_SET_HUBA(huba) | 4208 EHCI_SITD_SET_DIR(dir)); 4209 4210 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4211 } /* End of frame */ 4212 4213 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4214 4215 stop = sitd; 4216 stop->xfer_next = NULL; 4217 exfer->ex_sitdstart = start; 4218 exfer->ex_sitdend = stop; 4219 4220 return 0; 4221 4222 fail: 4223 mutex_enter(&sc->sc_lock); 4224 ehci_soft_sitd_t *next; 4225 for (sitd = start; sitd; sitd = next) { 4226 next = sitd->xfer_next; 4227 ehci_free_sitd_locked(sc, sitd); 4228 } 4229 mutex_exit(&sc->sc_lock); 4230 4231 return err; 4232 } 4233 4234 Static void 4235 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4236 { 4237 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4238 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4239 4240 KASSERT(ex->ex_type == EX_FS_ISOC); 4241 4242 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4243 } 4244 4245 Static usbd_status 4246 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4247 { 4248 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4249 usbd_status __diagused err; 4250 4251 mutex_enter(&sc->sc_lock); 4252 err = usb_insert_transfer(xfer); 4253 mutex_exit(&sc->sc_lock); 4254 4255 KASSERT(err == USBD_NORMAL_COMPLETION); 4256 4257 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4258 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4259 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4260 ehci_soft_sitd_t *sitd; 4261 usb_dma_t *dma_buf; 4262 int i, j, k, frames; 4263 int offs, total_length; 4264 int frindex; 4265 u_int dir; 4266 4267 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4268 4269 sitd = NULL; 4270 total_length = 0; 4271 4272 4273 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4274 xfer->ux_flags, 0); 4275 4276 if (sc->sc_dying) 4277 return USBD_IOERROR; 4278 4279 /* 4280 * To avoid complication, don't allow a request right now that'll span 4281 * the entire frame table. To within 4 frames, to allow some leeway 4282 * on either side of where the hc currently is. 4283 */ 4284 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4285 xfer->ux_nframes >= sc->sc_flsize - 4) { 4286 printf("ehci: isoc descriptor requested that spans the entire" 4287 "frametable, too many frames\n"); 4288 return USBD_INVAL; 4289 } 4290 4291 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4292 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4293 KASSERT(exfer->ex_isdone); 4294 #ifdef DIAGNOSTIC 4295 exfer->ex_isdone = false; 4296 #endif 4297 4298 /* 4299 * Step 1: Initialize sitds. 4300 */ 4301 4302 frames = xfer->ux_nframes; 4303 dma_buf = &xfer->ux_dmabuf; 4304 offs = 0; 4305 4306 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4307 i++, sitd = sitd->xfer_next) { 4308 KASSERT(sitd != NULL); 4309 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4310 4311 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4312 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4313 4314 /* Set page0 index and offset - TP and T-offset are set below */ 4315 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4316 4317 total_length += xfer->ux_frlengths[i]; 4318 offs += xfer->ux_frlengths[i]; 4319 4320 sitd->sitd.sitd_buffer[1] = 4321 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4322 4323 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4324 4325 #if 0 4326 if (sc->sc_flags & EHCIF_FREESCALE) { 4327 // Set hub address to 0 if embedded TT is used. 4328 if (huba == sc->sc_addr) 4329 huba = 0; 4330 } 4331 #endif 4332 4333 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4334 dir = UE_GET_DIR(k) ? 1 : 0; 4335 KASSERT(sitd->sitd.sitd_endp == htole32( 4336 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4337 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4338 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4339 EHCI_SITD_SET_HUBA(huba) | 4340 EHCI_SITD_SET_DIR(dir))); 4341 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4342 4343 uint8_t sa = 0; 4344 uint8_t sb = 0; 4345 u_int temp, tlen; 4346 4347 if (dir == 0) { /* OUT */ 4348 temp = 0; 4349 tlen = xfer->ux_frlengths[i]; 4350 if (tlen <= 188) { 4351 temp |= 1; /* T-count = 1, TP = ALL */ 4352 tlen = 1; 4353 } else { 4354 tlen += 187; 4355 tlen /= 188; 4356 temp |= tlen; /* T-count = [1..6] */ 4357 temp |= 8; /* TP = Begin */ 4358 } 4359 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4360 4361 tlen += sa; 4362 4363 if (tlen >= 8) { 4364 sb = 0; 4365 } else { 4366 sb = (1 << tlen); 4367 } 4368 4369 sa = (1 << sa); 4370 sa = (sb - sa) & 0x3F; 4371 sb = 0; 4372 } else { 4373 sb = (-(4 << sa)) & 0xFE; 4374 sa = (1 << sa) & 0x3F; 4375 sa = 0x01; 4376 sb = 0xfc; 4377 } 4378 4379 sitd->sitd.sitd_sched = htole32( 4380 EHCI_SITD_SET_SMASK(sa) | 4381 EHCI_SITD_SET_CMASK(sb) 4382 ); 4383 4384 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4385 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4386 } /* End of frame */ 4387 4388 sitd = exfer->ex_sitdend; 4389 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4390 4391 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4392 sizeof(sitd->sitd.sitd_trans), 4393 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4394 4395 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4396 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4397 4398 /* 4399 * Part 2: Transfer descriptors have now been set up, now they must 4400 * be scheduled into the periodic frame list. Erk. Not wanting to 4401 * complicate matters, transfer is denied if the transfer spans 4402 * more than the period frame list. 4403 */ 4404 4405 mutex_enter(&sc->sc_lock); 4406 4407 /* Start inserting frames */ 4408 if (epipe->isoc.cur_xfers > 0) { 4409 frindex = epipe->isoc.next_frame; 4410 } else { 4411 frindex = EOREAD4(sc, EHCI_FRINDEX); 4412 frindex = frindex >> 3; /* Erase microframe index */ 4413 frindex += 2; 4414 } 4415 4416 if (frindex >= sc->sc_flsize) 4417 frindex &= (sc->sc_flsize - 1); 4418 4419 /* Whats the frame interval? */ 4420 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4421 4422 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4423 j++, sitd = sitd->xfer_next) { 4424 KASSERT(sitd); 4425 4426 usb_syncmem(&sc->sc_fldma, 4427 sizeof(ehci_link_t) * frindex, 4428 sizeof(ehci_link_t), 4429 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4430 4431 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4432 if (sitd->sitd.sitd_next == 0) 4433 /* 4434 * FIXME: frindex table gets initialized to NULL 4435 * or EHCI_NULL? 4436 */ 4437 sitd->sitd.sitd_next = EHCI_NULL; 4438 4439 usb_syncmem(&sitd->dma, 4440 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4441 sizeof(ehci_sitd_t), 4442 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4443 4444 sc->sc_flist[frindex] = 4445 htole32(EHCI_LINK_SITD | sitd->physaddr); 4446 4447 usb_syncmem(&sc->sc_fldma, 4448 sizeof(ehci_link_t) * frindex, 4449 sizeof(ehci_link_t), 4450 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4451 4452 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4453 sc->sc_softsitds[frindex] = sitd; 4454 if (sitd->frame_list.next != NULL) 4455 sitd->frame_list.next->frame_list.prev = sitd; 4456 sitd->slot = frindex; 4457 sitd->frame_list.prev = NULL; 4458 4459 frindex += i; 4460 if (frindex >= sc->sc_flsize) 4461 frindex -= sc->sc_flsize; 4462 } 4463 4464 epipe->isoc.cur_xfers++; 4465 epipe->isoc.next_frame = frindex; 4466 4467 ehci_add_intr_list(sc, exfer); 4468 xfer->ux_status = USBD_IN_PROGRESS; 4469 4470 mutex_exit(&sc->sc_lock); 4471 4472 return USBD_IN_PROGRESS; 4473 } 4474 4475 Static void 4476 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4477 { 4478 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4479 4480 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4481 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4482 } 4483 4484 Static void 4485 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4486 { 4487 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4488 4489 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4490 } 4491 4492 Static void 4493 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4494 { 4495 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4496 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4497 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4498 4499 KASSERT(mutex_owned(&sc->sc_lock)); 4500 4501 epipe->isoc.cur_xfers--; 4502 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4503 4504 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4505 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4506 } 4507 4508 4509 /************************/ 4510 4511 4512 Static int 4513 ehci_device_isoc_init(struct usbd_xfer *xfer) 4514 { 4515 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4516 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4517 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4518 ehci_soft_itd_t *itd, *prev, *start, *stop; 4519 int i, j, k; 4520 int frames, ufrperframe; 4521 int err; 4522 4523 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4524 4525 start = NULL; 4526 prev = NULL; 4527 itd = NULL; 4528 4529 KASSERT(xfer->ux_nframes != 0); 4530 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4531 KASSERT(exfer->ex_isdone); 4532 4533 exfer->ex_type = EX_ISOC; 4534 4535 /* 4536 * Step 1: Allocate and initialize itds, how many do we need? 4537 * One per transfer if interval >= 8 microframes, less if we use 4538 * multiple microframes per frame. 4539 */ 4540 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4541 if (i > 16 || i == 0) { 4542 /* Spec page 271 says intervals > 16 are invalid */ 4543 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4544 return USBD_INVAL; 4545 } 4546 4547 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4548 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4549 4550 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4551 itd = ehci_alloc_itd(sc); 4552 if (itd == NULL) { 4553 err = ENOMEM; 4554 goto fail; 4555 } 4556 4557 if (prev != NULL) { 4558 /* Maybe not as it's updated by the scheduling? */ 4559 prev->itd.itd_next = 4560 htole32(itd->physaddr | EHCI_LINK_ITD); 4561 4562 prev->xfer_next = itd; 4563 } else { 4564 start = itd; 4565 } 4566 4567 /* 4568 * Other special values 4569 */ 4570 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4571 itd->itd.itd_bufr[0] = htole32( 4572 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4573 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4574 4575 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4576 ? 1 : 0; 4577 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4578 itd->itd.itd_bufr[1] |= htole32( 4579 EHCI_ITD_SET_DIR(k) | 4580 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4581 4582 /* FIXME: handle invalid trans - should be done in openpipe */ 4583 itd->itd.itd_bufr[2] |= 4584 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4585 } /* End of frame */ 4586 4587 stop = itd; 4588 stop->xfer_next = NULL; 4589 4590 exfer->ex_itdstart = start; 4591 exfer->ex_itdend = stop; 4592 4593 return 0; 4594 fail: 4595 mutex_enter(&sc->sc_lock); 4596 ehci_soft_itd_t *next; 4597 for (itd = start; itd; itd = next) { 4598 next = itd->xfer_next; 4599 ehci_free_itd_locked(sc, itd); 4600 } 4601 mutex_exit(&sc->sc_lock); 4602 4603 return err; 4604 4605 } 4606 4607 Static void 4608 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4609 { 4610 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4611 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4612 4613 KASSERT(ex->ex_type == EX_ISOC); 4614 4615 ehci_free_itd_chain(sc, ex->ex_itdstart); 4616 } 4617 4618 Static usbd_status 4619 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4620 { 4621 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4622 usbd_status __diagused err; 4623 4624 mutex_enter(&sc->sc_lock); 4625 err = usb_insert_transfer(xfer); 4626 mutex_exit(&sc->sc_lock); 4627 4628 KASSERT(err == USBD_NORMAL_COMPLETION); 4629 4630 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4631 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4632 ehci_soft_itd_t *itd, *prev; 4633 usb_dma_t *dma_buf; 4634 int i, j; 4635 int frames, uframes, ufrperframe; 4636 int trans_count, offs, total_length; 4637 int frindex; 4638 4639 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4640 4641 prev = NULL; 4642 itd = NULL; 4643 trans_count = 0; 4644 total_length = 0; 4645 4646 DPRINTF("xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4647 4648 if (sc->sc_dying) 4649 return USBD_IOERROR; 4650 4651 /* 4652 * To avoid complication, don't allow a request right now that'll span 4653 * the entire frame table. To within 4 frames, to allow some leeway 4654 * on either side of where the hc currently is. 4655 */ 4656 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4657 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4658 DPRINTF( 4659 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4660 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4661 return USBD_INVAL; 4662 } 4663 4664 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4665 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4666 KASSERT(exfer->ex_isdone); 4667 #ifdef DIAGNOSTIC 4668 exfer->ex_isdone = false; 4669 #endif 4670 4671 /* 4672 * Step 1: Re-Initialize itds 4673 */ 4674 4675 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4676 if (i > 16 || i == 0) { 4677 /* Spec page 271 says intervals > 16 are invalid */ 4678 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4679 return USBD_INVAL; 4680 } 4681 4682 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4683 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4684 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4685 4686 if (frames == 0) { 4687 DPRINTF("frames == 0", 0, 0, 0, 0); 4688 return USBD_INVAL; 4689 } 4690 4691 dma_buf = &xfer->ux_dmabuf; 4692 offs = 0; 4693 4694 itd = exfer->ex_itdstart; 4695 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4696 int froffs = offs; 4697 4698 if (prev != NULL) { 4699 prev->itd.itd_next = 4700 htole32(itd->physaddr | EHCI_LINK_ITD); 4701 usb_syncmem(&prev->dma, 4702 prev->offs + offsetof(ehci_itd_t, itd_next), 4703 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4704 prev->xfer_next = itd; 4705 } 4706 4707 /* 4708 * Step 1.5, initialize uframes 4709 */ 4710 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4711 /* Calculate which page in the list this starts in */ 4712 int addr = DMAADDR(dma_buf, froffs); 4713 addr = EHCI_PAGE_OFFSET(addr); 4714 addr += (offs - froffs); 4715 addr = EHCI_PAGE(addr); 4716 addr /= EHCI_PAGE_SIZE; 4717 4718 /* 4719 * This gets the initial offset into the first page, 4720 * looks how far further along the current uframe 4721 * offset is. Works out how many pages that is. 4722 */ 4723 4724 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4725 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4726 EHCI_ITD_SET_PG(addr) | 4727 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4728 4729 total_length += xfer->ux_frlengths[trans_count]; 4730 offs += xfer->ux_frlengths[trans_count]; 4731 trans_count++; 4732 4733 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4734 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4735 break; 4736 } 4737 } 4738 4739 /* 4740 * Step 1.75, set buffer pointers. To simplify matters, all 4741 * pointers are filled out for the next 7 hardware pages in 4742 * the dma block, so no need to worry what pages to cover 4743 * and what to not. 4744 */ 4745 4746 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4747 /* 4748 * Don't try to lookup a page that's past the end 4749 * of buffer 4750 */ 4751 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4752 if (page_offs >= dma_buf->udma_block->size) 4753 break; 4754 4755 uint64_t page = DMAADDR(dma_buf, page_offs); 4756 page = EHCI_PAGE(page); 4757 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4758 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4759 } 4760 /* 4761 * Other special values 4762 */ 4763 4764 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4765 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4766 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4767 4768 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4769 ? 1 : 0; 4770 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4771 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4772 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4773 4774 /* FIXME: handle invalid trans */ 4775 itd->itd.itd_bufr[2] |= 4776 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4777 4778 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4779 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4780 4781 prev = itd; 4782 } /* End of frame */ 4783 4784 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4785 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4786 4787 /* 4788 * Part 2: Transfer descriptors have now been set up, now they must 4789 * be scheduled into the period frame list. Erk. Not wanting to 4790 * complicate matters, transfer is denied if the transfer spans 4791 * more than the period frame list. 4792 */ 4793 4794 mutex_enter(&sc->sc_lock); 4795 4796 /* Start inserting frames */ 4797 if (epipe->isoc.cur_xfers > 0) { 4798 frindex = epipe->isoc.next_frame; 4799 } else { 4800 frindex = EOREAD4(sc, EHCI_FRINDEX); 4801 frindex = frindex >> 3; /* Erase microframe index */ 4802 frindex += 2; 4803 } 4804 4805 if (frindex >= sc->sc_flsize) 4806 frindex &= (sc->sc_flsize - 1); 4807 4808 /* What's the frame interval? */ 4809 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4810 if (i / USB_UFRAMES_PER_FRAME == 0) 4811 i = 1; 4812 else 4813 i /= USB_UFRAMES_PER_FRAME; 4814 4815 itd = exfer->ex_itdstart; 4816 for (j = 0; j < frames; j++) { 4817 KASSERTMSG(itd != NULL, "frame %d\n", j); 4818 4819 usb_syncmem(&sc->sc_fldma, 4820 sizeof(ehci_link_t) * frindex, 4821 sizeof(ehci_link_t), 4822 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4823 4824 itd->itd.itd_next = sc->sc_flist[frindex]; 4825 if (itd->itd.itd_next == 0) 4826 /* 4827 * FIXME: frindex table gets initialized to NULL 4828 * or EHCI_NULL? 4829 */ 4830 itd->itd.itd_next = EHCI_NULL; 4831 4832 usb_syncmem(&itd->dma, 4833 itd->offs + offsetof(ehci_itd_t, itd_next), 4834 sizeof(itd->itd.itd_next), 4835 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4836 4837 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4838 4839 usb_syncmem(&sc->sc_fldma, 4840 sizeof(ehci_link_t) * frindex, 4841 sizeof(ehci_link_t), 4842 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4843 4844 itd->frame_list.next = sc->sc_softitds[frindex]; 4845 sc->sc_softitds[frindex] = itd; 4846 if (itd->frame_list.next != NULL) 4847 itd->frame_list.next->frame_list.prev = itd; 4848 itd->slot = frindex; 4849 itd->frame_list.prev = NULL; 4850 4851 frindex += i; 4852 if (frindex >= sc->sc_flsize) 4853 frindex -= sc->sc_flsize; 4854 4855 itd = itd->xfer_next; 4856 } 4857 4858 epipe->isoc.cur_xfers++; 4859 epipe->isoc.next_frame = frindex; 4860 4861 ehci_add_intr_list(sc, exfer); 4862 xfer->ux_status = USBD_IN_PROGRESS; 4863 4864 mutex_exit(&sc->sc_lock); 4865 4866 return USBD_IN_PROGRESS; 4867 } 4868 4869 Static void 4870 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4871 { 4872 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4873 4874 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4875 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4876 } 4877 4878 Static void 4879 ehci_device_isoc_close(struct usbd_pipe *pipe) 4880 { 4881 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4882 4883 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4884 } 4885 4886 Static void 4887 ehci_device_isoc_done(struct usbd_xfer *xfer) 4888 { 4889 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4890 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4891 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4892 4893 KASSERT(mutex_owned(&sc->sc_lock)); 4894 4895 epipe->isoc.cur_xfers--; 4896 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4897 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4898 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4899 } 4900
Indexes created Tue Sep 23 07:09:52 GMT 2025