ehci.c revision 1.257.2.2
1 /* $NetBSD: ehci.c,v 1.257.2.2 2018/06/25 07:26:02 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.257.2.2 2018/06/25 07:26:02 pgoyette Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static void ehci_intrlist_timeout(void *); 172 Static void ehci_doorbell(void *); 173 Static void ehci_pcd(void *); 174 175 Static struct usbd_xfer * 176 ehci_allocx(struct usbd_bus *, unsigned int); 177 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 178 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_softwake_cv, "ehciab"); 416 cv_init(&sc->sc_doorbell, "ehcidi"); 417 418 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 419 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 420 421 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 422 ehci_doorbell, sc); 423 KASSERT(sc->sc_doorbell_si != NULL); 424 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 425 ehci_pcd, sc); 426 KASSERT(sc->sc_pcd_si != NULL); 427 428 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 429 430 vers = EREAD2(sc, EHCI_HCIVERSION); 431 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 432 vers >> 8, vers & 0xff); 433 434 sparams = EREAD4(sc, EHCI_HCSPARAMS); 435 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 436 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 437 ncomp = EHCI_HCS_N_CC(sparams); 438 if (ncomp != sc->sc_ncomp) { 439 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 440 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 441 #if NOHCI == 0 || NUHCI == 0 442 aprint_error("%s: ohci or uhci probably not configured\n", 443 device_xname(sc->sc_dev)); 444 #endif 445 if (ncomp < sc->sc_ncomp) 446 sc->sc_ncomp = ncomp; 447 } 448 if (sc->sc_ncomp > 0) { 449 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 450 aprint_normal("%s: %d companion controller%s, %d port%s%s", 451 device_xname(sc->sc_dev), sc->sc_ncomp, 452 sc->sc_ncomp!=1 ? "s" : "", 453 EHCI_HCS_N_PCC(sparams), 454 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 455 sc->sc_ncomp!=1 ? " each" : ""); 456 if (sc->sc_comps[0]) { 457 aprint_normal(":"); 458 for (i = 0; i < sc->sc_ncomp; i++) 459 aprint_normal(" %s", 460 device_xname(sc->sc_comps[i])); 461 } 462 aprint_normal("\n"); 463 } 464 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 465 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 466 467 cparams = EREAD4(sc, EHCI_HCCPARAMS); 468 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 469 470 if (EHCI_HCC_64BIT(cparams)) { 471 /* MUST clear segment register if 64 bit capable. */ 472 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 473 } 474 475 if (cparams & EHCI_HCC_IST_FULLFRAME) { 476 sc->sc_istthreshold = 0; 477 } else { 478 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 479 } 480 481 sc->sc_bus.ub_revision = USBREV_2_0; 482 sc->sc_bus.ub_usedma = true; 483 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 484 485 /* Reset the controller */ 486 DPRINTF("resetting", 0, 0, 0, 0); 487 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 488 usb_delay_ms(&sc->sc_bus, 1); 489 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 490 for (i = 0; i < 100; i++) { 491 usb_delay_ms(&sc->sc_bus, 1); 492 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 493 if (!hcr) 494 break; 495 } 496 if (hcr) { 497 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 498 return EIO; 499 } 500 if (sc->sc_vendor_init) 501 sc->sc_vendor_init(sc); 502 503 /* XXX need proper intr scheduling */ 504 sc->sc_rand = 96; 505 506 /* frame list size at default, read back what we got and use that */ 507 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 508 case 0: sc->sc_flsize = 1024; break; 509 case 1: sc->sc_flsize = 512; break; 510 case 2: sc->sc_flsize = 256; break; 511 case 3: return EIO; 512 } 513 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 514 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 515 if (err) 516 return err; 517 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 518 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 519 520 for (i = 0; i < sc->sc_flsize; i++) { 521 sc->sc_flist[i] = EHCI_NULL; 522 } 523 524 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 525 526 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 527 KM_SLEEP); 528 if (sc->sc_softitds == NULL) 529 return ENOMEM; 530 LIST_INIT(&sc->sc_freeitds); 531 LIST_INIT(&sc->sc_freesitds); 532 TAILQ_INIT(&sc->sc_intrhead); 533 534 /* Set up the bus struct. */ 535 sc->sc_bus.ub_methods = &ehci_bus_methods; 536 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 537 538 sc->sc_eintrs = EHCI_NORMAL_INTRS; 539 540 /* 541 * Allocate the interrupt dummy QHs. These are arranged to give poll 542 * intervals that are powers of 2 times 1ms. 543 */ 544 for (i = 0; i < EHCI_INTRQHS; i++) { 545 sqh = ehci_alloc_sqh(sc); 546 if (sqh == NULL) { 547 err = ENOMEM; 548 goto bad1; 549 } 550 sc->sc_islots[i].sqh = sqh; 551 } 552 for (i = 0; i < EHCI_INTRQHS; i++) { 553 sqh = sc->sc_islots[i].sqh; 554 if (i == 0) { 555 /* The last (1ms) QH terminates. */ 556 sqh->qh.qh_link = EHCI_NULL; 557 sqh->next = NULL; 558 } else { 559 /* Otherwise the next QH has half the poll interval */ 560 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 561 sqh->qh.qh_link = htole32(sqh->next->physaddr | 562 EHCI_LINK_QH); 563 } 564 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 565 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 566 sqh->qh.qh_curqtd = EHCI_NULL; 567 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 568 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 569 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 570 sqh->sqtd = NULL; 571 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 572 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 573 } 574 /* Point the frame list at the last level (128ms). */ 575 for (i = 0; i < sc->sc_flsize; i++) { 576 int j; 577 578 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 579 revbits[i & (EHCI_MAX_POLLRATE-1)]; 580 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 581 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 582 i)].sqh->physaddr); 583 } 584 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 585 BUS_DMASYNC_PREWRITE); 586 587 /* Allocate dummy QH that starts the async list. */ 588 sqh = ehci_alloc_sqh(sc); 589 if (sqh == NULL) { 590 err = ENOMEM; 591 goto bad1; 592 } 593 /* Fill the QH */ 594 sqh->qh.qh_endp = 595 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 596 sqh->qh.qh_link = 597 htole32(sqh->physaddr | EHCI_LINK_QH); 598 sqh->qh.qh_curqtd = EHCI_NULL; 599 sqh->next = NULL; 600 /* Fill the overlay qTD */ 601 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 602 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 603 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 604 sqh->sqtd = NULL; 605 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 607 #ifdef EHCI_DEBUG 608 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 609 ehci_dump_sqh(sqh); 610 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 611 #endif 612 613 /* Point to async list */ 614 sc->sc_async_head = sqh; 615 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 616 617 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 618 619 /* Turn on controller */ 620 EOWRITE4(sc, EHCI_USBCMD, 621 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 622 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 623 EHCI_CMD_ASE | 624 EHCI_CMD_PSE | 625 EHCI_CMD_RS); 626 627 /* Take over port ownership */ 628 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 629 630 for (i = 0; i < 100; i++) { 631 usb_delay_ms(&sc->sc_bus, 1); 632 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 633 if (!hcr) 634 break; 635 } 636 if (hcr) { 637 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 638 return EIO; 639 } 640 641 /* Enable interrupts */ 642 DPRINTF("enabling interupts", 0, 0, 0, 0); 643 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 644 645 return 0; 646 647 #if 0 648 bad2: 649 ehci_free_sqh(sc, sc->sc_async_head); 650 #endif 651 bad1: 652 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 653 return err; 654 } 655 656 int 657 ehci_intr(void *v) 658 { 659 ehci_softc_t *sc = v; 660 int ret = 0; 661 662 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 663 664 if (sc == NULL) 665 return 0; 666 667 mutex_spin_enter(&sc->sc_intr_lock); 668 669 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 670 goto done; 671 672 /* If we get an interrupt while polling, then just ignore it. */ 673 if (sc->sc_bus.ub_usepolling) { 674 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 675 676 if (intrs) 677 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 678 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 679 goto done; 680 } 681 682 ret = ehci_intr1(sc); 683 684 done: 685 mutex_spin_exit(&sc->sc_intr_lock); 686 return ret; 687 } 688 689 Static int 690 ehci_intr1(ehci_softc_t *sc) 691 { 692 uint32_t intrs, eintrs; 693 694 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 695 696 /* In case the interrupt occurs before initialization has completed. */ 697 if (sc == NULL) { 698 #ifdef DIAGNOSTIC 699 printf("ehci_intr1: sc == NULL\n"); 700 #endif 701 return 0; 702 } 703 704 KASSERT(mutex_owned(&sc->sc_intr_lock)); 705 706 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 707 if (!intrs) 708 return 0; 709 710 eintrs = intrs & sc->sc_eintrs; 711 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 712 EOREAD4(sc, EHCI_USBSTS), eintrs); 713 if (!eintrs) 714 return 0; 715 716 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 717 if (eintrs & EHCI_STS_IAA) { 718 DPRINTF("door bell", 0, 0, 0, 0); 719 kpreempt_disable(); 720 KASSERT(sc->sc_doorbell_si != NULL); 721 softint_schedule(sc->sc_doorbell_si); 722 kpreempt_enable(); 723 eintrs &= ~EHCI_STS_IAA; 724 } 725 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 726 DPRINTF("INT=%jd ERRINT=%jd", 727 eintrs & EHCI_STS_INT ? 1 : 0, 728 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 729 usb_schedsoftintr(&sc->sc_bus); 730 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 731 } 732 if (eintrs & EHCI_STS_HSE) { 733 printf("%s: unrecoverable error, controller halted\n", 734 device_xname(sc->sc_dev)); 735 /* XXX what else */ 736 } 737 if (eintrs & EHCI_STS_PCD) { 738 kpreempt_disable(); 739 KASSERT(sc->sc_pcd_si != NULL); 740 softint_schedule(sc->sc_pcd_si); 741 kpreempt_enable(); 742 eintrs &= ~EHCI_STS_PCD; 743 } 744 745 if (eintrs != 0) { 746 /* Block unprocessed interrupts. */ 747 sc->sc_eintrs &= ~eintrs; 748 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 749 printf("%s: blocking intrs 0x%x\n", 750 device_xname(sc->sc_dev), eintrs); 751 } 752 753 return 1; 754 } 755 756 Static void 757 ehci_doorbell(void *addr) 758 { 759 ehci_softc_t *sc = addr; 760 761 mutex_enter(&sc->sc_lock); 762 cv_broadcast(&sc->sc_doorbell); 763 mutex_exit(&sc->sc_lock); 764 } 765 766 Static void 767 ehci_pcd(void *addr) 768 { 769 ehci_softc_t *sc = addr; 770 struct usbd_xfer *xfer; 771 u_char *p; 772 int i, m; 773 774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 775 776 mutex_enter(&sc->sc_lock); 777 xfer = sc->sc_intrxfer; 778 779 if (xfer == NULL) { 780 /* Just ignore the change. */ 781 goto done; 782 } 783 784 p = xfer->ux_buf; 785 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 786 memset(p, 0, xfer->ux_length); 787 for (i = 1; i <= m; i++) { 788 /* Pick out CHANGE bits from the status reg. */ 789 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 790 p[i/8] |= 1 << (i%8); 791 if (i % 8 == 7) 792 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 793 } 794 xfer->ux_actlen = xfer->ux_length; 795 xfer->ux_status = USBD_NORMAL_COMPLETION; 796 797 usb_transfer_complete(xfer); 798 799 done: 800 mutex_exit(&sc->sc_lock); 801 } 802 803 Static void 804 ehci_softintr(void *v) 805 { 806 struct usbd_bus *bus = v; 807 ehci_softc_t *sc = EHCI_BUS2SC(bus); 808 struct ehci_xfer *ex, *nextex; 809 810 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 811 812 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 813 814 ex_completeq_t cq; 815 TAILQ_INIT(&cq); 816 817 /* 818 * The only explanation I can think of for why EHCI is as brain dead 819 * as UHCI interrupt-wise is that Intel was involved in both. 820 * An interrupt just tells us that something is done, we have no 821 * clue what, so we need to scan through all active transfers. :-( 822 */ 823 824 /* 825 * ehci_idone will remove transfer from sc->sc_intrhead if it's 826 * complete and add to our cq list 827 * 828 */ 829 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 830 switch (ex->ex_type) { 831 case EX_CTRL: 832 case EX_BULK: 833 case EX_INTR: 834 ehci_check_qh_intr(sc, ex, &cq); 835 break; 836 case EX_ISOC: 837 ehci_check_itd_intr(sc, ex, &cq); 838 break; 839 case EX_FS_ISOC: 840 ehci_check_sitd_intr(sc, ex, &cq); 841 break; 842 default: 843 KASSERT(false); 844 } 845 846 } 847 848 /* 849 * We abuse ex_next for the interrupt and complete lists and 850 * interrupt transfers will get re-added here so use 851 * the _SAFE version of TAILQ_FOREACH. 852 */ 853 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 854 usb_transfer_complete(&ex->ex_xfer); 855 } 856 857 /* Schedule a callout to catch any dropped transactions. */ 858 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 859 !TAILQ_EMPTY(&sc->sc_intrhead)) 860 callout_reset(&sc->sc_tmo_intrlist, 861 hz, ehci_intrlist_timeout, sc); 862 863 if (sc->sc_softwake) { 864 sc->sc_softwake = 0; 865 cv_broadcast(&sc->sc_softwake_cv); 866 } 867 } 868 869 Static void 870 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 871 { 872 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 873 uint32_t status; 874 875 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 876 877 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 878 879 if (ex->ex_type == EX_CTRL) { 880 fsqtd = ex->ex_setup; 881 lsqtd = ex->ex_status; 882 } else { 883 fsqtd = ex->ex_sqtdstart; 884 lsqtd = ex->ex_sqtdend; 885 } 886 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 887 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 888 889 /* 890 * If the last TD is still active we need to check whether there 891 * is an error somewhere in the middle, or whether there was a 892 * short packet (SPD and not ACTIVE). 893 */ 894 usb_syncmem(&lsqtd->dma, 895 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 896 sizeof(lsqtd->qtd.qtd_status), 897 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 898 status = le32toh(lsqtd->qtd.qtd_status); 899 usb_syncmem(&lsqtd->dma, 900 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 901 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 902 if (status & EHCI_QTD_ACTIVE) { 903 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 904 905 /* last qTD has already been checked */ 906 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 907 usb_syncmem(&sqtd->dma, 908 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 909 sizeof(sqtd->qtd.qtd_status), 910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 911 status = le32toh(sqtd->qtd.qtd_status); 912 usb_syncmem(&sqtd->dma, 913 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 914 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 915 /* If there's an active QTD the xfer isn't done. */ 916 if (status & EHCI_QTD_ACTIVE) 917 break; 918 /* Any kind of error makes the xfer done. */ 919 if (status & EHCI_QTD_HALTED) 920 goto done; 921 /* Handle short packets */ 922 if (EHCI_QTD_GET_BYTES(status) != 0) { 923 /* 924 * If we get here for a control transfer then 925 * we need to let the hardware complete the 926 * status phase. That is, we're not done 927 * quite yet. 928 * 929 * Otherwise, we're done. 930 */ 931 if (ex->ex_type == EX_CTRL) { 932 break; 933 } 934 goto done; 935 } 936 } 937 DPRINTFN(10, "ex=%#jx std=%#jx still active", 938 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 939 #ifdef EHCI_DEBUG 940 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 941 ehci_dump_sqtds(ex->ex_sqtdstart); 942 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 943 #endif 944 return; 945 } 946 done: 947 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 948 callout_stop(&ex->ex_xfer.ux_callout); 949 ehci_idone(ex, cq); 950 } 951 952 Static void 953 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 954 { 955 ehci_soft_itd_t *itd; 956 int i; 957 958 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 959 960 KASSERT(mutex_owned(&sc->sc_lock)); 961 962 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 963 return; 964 965 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 966 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 967 968 itd = ex->ex_itdend; 969 970 /* 971 * check no active transfers in last itd, meaning we're finished 972 */ 973 974 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 975 sizeof(itd->itd.itd_ctl), 976 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 977 978 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 979 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 980 break; 981 } 982 983 if (i == EHCI_ITD_NUFRAMES) { 984 goto done; /* All 8 descriptors inactive, it's done */ 985 } 986 987 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 988 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 989 990 DPRINTFN(10, "ex %#jx itd %#jx still active", 991 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 992 return; 993 done: 994 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 995 callout_stop(&ex->ex_xfer.ux_callout); 996 ehci_idone(ex, cq); 997 } 998 999 void 1000 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1001 { 1002 ehci_soft_sitd_t *sitd; 1003 1004 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1005 1006 KASSERT(mutex_owned(&sc->sc_lock)); 1007 1008 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1009 return; 1010 1011 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1012 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1013 1014 sitd = ex->ex_sitdend; 1015 1016 /* 1017 * check no active transfers in last sitd, meaning we're finished 1018 */ 1019 1020 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1021 sizeof(sitd->sitd.sitd_trans), 1022 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1023 1024 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1025 1026 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1027 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1028 1029 if (active) 1030 return; 1031 1032 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1033 callout_stop(&(ex->ex_xfer.ux_callout)); 1034 ehci_idone(ex, cq); 1035 } 1036 1037 1038 Static void 1039 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1040 { 1041 struct usbd_xfer *xfer = &ex->ex_xfer; 1042 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1043 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1044 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1045 uint32_t status = 0, nstatus = 0; 1046 int actlen = 0; 1047 1048 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1049 1050 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1051 1052 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1053 1054 if (xfer->ux_status == USBD_CANCELLED || 1055 xfer->ux_status == USBD_TIMEOUT) { 1056 DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1057 return; 1058 } 1059 1060 #ifdef DIAGNOSTIC 1061 #ifdef EHCI_DEBUG 1062 if (ex->ex_isdone) { 1063 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1064 ehci_dump_exfer(ex); 1065 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1066 } 1067 #endif 1068 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1069 ex->ex_type, xfer->ux_status); 1070 ex->ex_isdone = true; 1071 #endif 1072 1073 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1074 (uintptr_t)epipe, 0, 0); 1075 1076 /* The transfer is done, compute actual length and status. */ 1077 if (ex->ex_type == EX_ISOC) { 1078 /* HS isoc transfer */ 1079 1080 struct ehci_soft_itd *itd; 1081 int i, nframes, len, uframes; 1082 1083 nframes = 0; 1084 1085 #ifdef EHCI_DEBUG 1086 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1087 ehci_dump_itds(ex->ex_itdstart); 1088 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1089 #endif 1090 1091 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1092 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1093 1094 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1095 usb_syncmem(&itd->dma, 1096 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1097 sizeof(itd->itd.itd_ctl), 1098 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1099 1100 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1101 /* 1102 * XXX - driver didn't fill in the frame full 1103 * of uframes. This leads to scheduling 1104 * inefficiencies, but working around 1105 * this doubles complexity of tracking 1106 * an xfer. 1107 */ 1108 if (nframes >= xfer->ux_nframes) 1109 break; 1110 1111 status = le32toh(itd->itd.itd_ctl[i]); 1112 len = EHCI_ITD_GET_LEN(status); 1113 if (EHCI_ITD_GET_STATUS(status) != 0) 1114 len = 0; /*No valid data on error*/ 1115 1116 xfer->ux_frlengths[nframes++] = len; 1117 actlen += len; 1118 } 1119 usb_syncmem(&itd->dma, 1120 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1121 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1122 1123 if (nframes >= xfer->ux_nframes) 1124 break; 1125 } 1126 1127 xfer->ux_actlen = actlen; 1128 xfer->ux_status = USBD_NORMAL_COMPLETION; 1129 goto end; 1130 } else if (ex->ex_type == EX_FS_ISOC) { 1131 /* FS isoc transfer */ 1132 struct ehci_soft_sitd *sitd; 1133 int nframes, len; 1134 1135 nframes = 0; 1136 1137 for (sitd = ex->ex_sitdstart; sitd != NULL; 1138 sitd = sitd->xfer_next) { 1139 usb_syncmem(&sitd->dma, 1140 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1141 sizeof(sitd->sitd.sitd_trans), 1142 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1143 1144 /* 1145 * XXX - driver didn't fill in the frame full 1146 * of uframes. This leads to scheduling 1147 * inefficiencies, but working around 1148 * this doubles complexity of tracking 1149 * an xfer. 1150 */ 1151 if (nframes >= xfer->ux_nframes) 1152 break; 1153 1154 status = le32toh(sitd->sitd.sitd_trans); 1155 usb_syncmem(&sitd->dma, 1156 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1157 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1158 1159 len = EHCI_SITD_GET_LEN(status); 1160 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1161 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1162 /* No valid data on error */ 1163 len = xfer->ux_frlengths[nframes]; 1164 } 1165 1166 /* 1167 * frlengths[i]: # of bytes to send 1168 * len: # of bytes host didn't send 1169 */ 1170 xfer->ux_frlengths[nframes] -= len; 1171 /* frlengths[i]: # of bytes host sent */ 1172 actlen += xfer->ux_frlengths[nframes++]; 1173 1174 if (nframes >= xfer->ux_nframes) 1175 break; 1176 } 1177 1178 xfer->ux_actlen = actlen; 1179 xfer->ux_status = USBD_NORMAL_COMPLETION; 1180 goto end; 1181 } 1182 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1183 ex->ex_type == EX_BULK); 1184 1185 /* Continue processing xfers using queue heads */ 1186 if (ex->ex_type == EX_CTRL) { 1187 fsqtd = ex->ex_setup; 1188 lsqtd = ex->ex_status; 1189 } else { 1190 fsqtd = ex->ex_sqtdstart; 1191 lsqtd = ex->ex_sqtdend; 1192 } 1193 #ifdef EHCI_DEBUG 1194 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1195 ehci_dump_sqtds(fsqtd); 1196 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1197 #endif 1198 1199 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1200 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1201 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1202 nstatus = le32toh(sqtd->qtd.qtd_status); 1203 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1204 BUS_DMASYNC_PREREAD); 1205 if (nstatus & EHCI_QTD_ACTIVE) 1206 break; 1207 1208 status = nstatus; 1209 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1210 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1211 } 1212 1213 /* 1214 * If there are left over TDs we need to update the toggle. 1215 * The default pipe doesn't need it since control transfers 1216 * start the toggle at 0 every time. 1217 * For a short transfer we need to update the toggle for the missing 1218 * packets within the qTD. 1219 */ 1220 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1221 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1222 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1223 status, nstatus, 0, 0); 1224 #if 0 1225 ehci_dump_sqh(epipe->sqh); 1226 ehci_dump_sqtds(ex->ex_sqtdstart); 1227 #endif 1228 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1229 } 1230 1231 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1232 status, 0); 1233 xfer->ux_actlen = actlen; 1234 if (status & EHCI_QTD_HALTED) { 1235 #ifdef EHCI_DEBUG 1236 DPRINTF("halted addr=%jd endpt=0x%02jx", 1237 xfer->ux_pipe->up_dev->ud_addr, 1238 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1239 0, 0); 1240 DPRINTF("cerr=%jd pid=%jd", 1241 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1242 0, 0); 1243 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1244 status & EHCI_QTD_ACTIVE ? 1 : 0, 1245 status & EHCI_QTD_HALTED ? 1 : 0, 1246 status & EHCI_QTD_BUFERR ? 1 : 0, 1247 status & EHCI_QTD_BABBLE ? 1 : 0); 1248 1249 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1250 status & EHCI_QTD_XACTERR ? 1 : 0, 1251 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1252 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1253 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1254 1255 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1256 ehci_dump_sqh(epipe->sqh); 1257 ehci_dump_sqtds(ex->ex_sqtdstart); 1258 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1259 #endif 1260 /* low&full speed has an extra error flag */ 1261 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1262 EHCI_QH_SPEED_HIGH) 1263 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1264 else 1265 status &= EHCI_QTD_STATERRS; 1266 if (status == 0) /* no other errors means a stall */ { 1267 xfer->ux_status = USBD_STALLED; 1268 } else { 1269 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1270 } 1271 /* XXX need to reset TT on missed microframe */ 1272 if (status & EHCI_QTD_MISSEDMICRO) { 1273 printf("%s: missed microframe, TT reset not " 1274 "implemented, hub might be inoperational\n", 1275 device_xname(sc->sc_dev)); 1276 } 1277 } else { 1278 xfer->ux_status = USBD_NORMAL_COMPLETION; 1279 } 1280 1281 end: 1282 1283 ehci_del_intr_list(sc, ex); 1284 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1285 1286 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1287 } 1288 1289 Static void 1290 ehci_poll(struct usbd_bus *bus) 1291 { 1292 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1293 1294 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1295 1296 #ifdef EHCI_DEBUG 1297 static int last; 1298 int new; 1299 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1300 if (new != last) { 1301 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1302 last = new; 1303 } 1304 #endif 1305 1306 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1307 mutex_spin_enter(&sc->sc_intr_lock); 1308 ehci_intr1(sc); 1309 mutex_spin_exit(&sc->sc_intr_lock); 1310 } 1311 } 1312 1313 void 1314 ehci_childdet(device_t self, device_t child) 1315 { 1316 struct ehci_softc *sc = device_private(self); 1317 1318 KASSERT(sc->sc_child == child); 1319 sc->sc_child = NULL; 1320 } 1321 1322 int 1323 ehci_detach(struct ehci_softc *sc, int flags) 1324 { 1325 int rv = 0; 1326 1327 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1328 1329 if (sc->sc_child != NULL) 1330 rv = config_detach(sc->sc_child, flags); 1331 1332 if (rv != 0) 1333 return rv; 1334 1335 callout_halt(&sc->sc_tmo_intrlist, NULL); 1336 callout_destroy(&sc->sc_tmo_intrlist); 1337 1338 /* XXX free other data structures XXX */ 1339 if (sc->sc_softitds) 1340 kmem_free(sc->sc_softitds, 1341 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1342 cv_destroy(&sc->sc_doorbell); 1343 cv_destroy(&sc->sc_softwake_cv); 1344 1345 #if 0 1346 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1347 1348 softint_disestablish(sc->sc_doorbell_si); 1349 softint_disestablish(sc->sc_pcd_si); 1350 1351 mutex_destroy(&sc->sc_lock); 1352 mutex_destroy(&sc->sc_intr_lock); 1353 #endif 1354 1355 pool_cache_destroy(sc->sc_xferpool); 1356 1357 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1358 1359 return rv; 1360 } 1361 1362 1363 int 1364 ehci_activate(device_t self, enum devact act) 1365 { 1366 struct ehci_softc *sc = device_private(self); 1367 1368 switch (act) { 1369 case DVACT_DEACTIVATE: 1370 sc->sc_dying = 1; 1371 return 0; 1372 default: 1373 return EOPNOTSUPP; 1374 } 1375 } 1376 1377 /* 1378 * Handle suspend/resume. 1379 * 1380 * We need to switch to polling mode here, because this routine is 1381 * called from an interrupt context. This is all right since we 1382 * are almost suspended anyway. 1383 * 1384 * Note that this power handler isn't to be registered directly; the 1385 * bus glue needs to call out to it. 1386 */ 1387 bool 1388 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1389 { 1390 ehci_softc_t *sc = device_private(dv); 1391 int i; 1392 uint32_t cmd, hcr; 1393 1394 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1395 1396 mutex_spin_enter(&sc->sc_intr_lock); 1397 sc->sc_bus.ub_usepolling++; 1398 mutex_spin_exit(&sc->sc_intr_lock); 1399 1400 for (i = 1; i <= sc->sc_noport; i++) { 1401 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1402 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1403 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1404 } 1405 1406 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1407 1408 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1409 EOWRITE4(sc, EHCI_USBCMD, cmd); 1410 1411 for (i = 0; i < 100; i++) { 1412 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1413 if (hcr == 0) 1414 break; 1415 1416 usb_delay_ms(&sc->sc_bus, 1); 1417 } 1418 if (hcr != 0) 1419 printf("%s: reset timeout\n", device_xname(dv)); 1420 1421 cmd &= ~EHCI_CMD_RS; 1422 EOWRITE4(sc, EHCI_USBCMD, cmd); 1423 1424 for (i = 0; i < 100; i++) { 1425 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1426 if (hcr == EHCI_STS_HCH) 1427 break; 1428 1429 usb_delay_ms(&sc->sc_bus, 1); 1430 } 1431 if (hcr != EHCI_STS_HCH) 1432 printf("%s: config timeout\n", device_xname(dv)); 1433 1434 mutex_spin_enter(&sc->sc_intr_lock); 1435 sc->sc_bus.ub_usepolling--; 1436 mutex_spin_exit(&sc->sc_intr_lock); 1437 1438 return true; 1439 } 1440 1441 bool 1442 ehci_resume(device_t dv, const pmf_qual_t *qual) 1443 { 1444 ehci_softc_t *sc = device_private(dv); 1445 int i; 1446 uint32_t cmd, hcr; 1447 1448 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1449 1450 /* restore things in case the bios sucks */ 1451 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1452 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1453 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1454 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1455 1456 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1457 1458 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1459 1460 hcr = 0; 1461 for (i = 1; i <= sc->sc_noport; i++) { 1462 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1463 if ((cmd & EHCI_PS_PO) == 0 && 1464 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1465 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1466 hcr = 1; 1467 } 1468 } 1469 1470 if (hcr) { 1471 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1472 1473 for (i = 1; i <= sc->sc_noport; i++) { 1474 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1475 if ((cmd & EHCI_PS_PO) == 0 && 1476 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1477 EOWRITE4(sc, EHCI_PORTSC(i), 1478 cmd & ~EHCI_PS_FPR); 1479 } 1480 } 1481 1482 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1483 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1484 1485 for (i = 0; i < 100; i++) { 1486 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1487 if (hcr != EHCI_STS_HCH) 1488 break; 1489 1490 usb_delay_ms(&sc->sc_bus, 1); 1491 } 1492 if (hcr == EHCI_STS_HCH) 1493 printf("%s: config timeout\n", device_xname(dv)); 1494 1495 return true; 1496 } 1497 1498 /* 1499 * Shut down the controller when the system is going down. 1500 */ 1501 bool 1502 ehci_shutdown(device_t self, int flags) 1503 { 1504 ehci_softc_t *sc = device_private(self); 1505 1506 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1507 1508 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1509 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1510 return true; 1511 } 1512 1513 Static struct usbd_xfer * 1514 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1515 { 1516 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1517 struct usbd_xfer *xfer; 1518 1519 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1520 if (xfer != NULL) { 1521 memset(xfer, 0, sizeof(struct ehci_xfer)); 1522 #ifdef DIAGNOSTIC 1523 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1524 ex->ex_isdone = true; 1525 xfer->ux_state = XFER_BUSY; 1526 #endif 1527 } 1528 return xfer; 1529 } 1530 1531 Static void 1532 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1533 { 1534 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1535 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1536 1537 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1538 xfer->ux_state); 1539 KASSERT(ex->ex_isdone); 1540 1541 #ifdef DIAGNOSTIC 1542 xfer->ux_state = XFER_FREE; 1543 #endif 1544 1545 pool_cache_put(sc->sc_xferpool, xfer); 1546 } 1547 1548 Static void 1549 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1550 { 1551 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1552 1553 *lock = &sc->sc_lock; 1554 } 1555 1556 Static void 1557 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1558 { 1559 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1560 1561 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1562 1563 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1564 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1565 #ifdef EHCI_DEBUG 1566 if (ehcidebug) 1567 usbd_dump_pipe(pipe); 1568 #endif 1569 epipe->nexttoggle = 0; 1570 } 1571 1572 Static void 1573 ehci_noop(struct usbd_pipe *pipe) 1574 { 1575 } 1576 1577 #ifdef EHCI_DEBUG 1578 /* 1579 * Unused function - this is meant to be called from a kernel 1580 * debugger. 1581 */ 1582 void 1583 ehci_dump(void) 1584 { 1585 ehci_softc_t *sc = theehci; 1586 int i; 1587 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1588 EOREAD4(sc, EHCI_USBCMD), 1589 EOREAD4(sc, EHCI_USBSTS), 1590 EOREAD4(sc, EHCI_USBINTR)); 1591 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1592 EOREAD4(sc, EHCI_FRINDEX), 1593 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1594 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1595 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1596 for (i = 1; i <= sc->sc_noport; i++) 1597 printf("port %d status=0x%08x\n", i, 1598 EOREAD4(sc, EHCI_PORTSC(i))); 1599 } 1600 1601 Static void 1602 ehci_dump_regs(ehci_softc_t *sc) 1603 { 1604 int i; 1605 1606 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1607 1608 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1609 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1610 EOREAD4(sc, EHCI_USBINTR), 0); 1611 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1612 "async = 0x%08jx", 1613 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1614 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1615 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1616 for (i = 1; i <= sc->sc_noport; i += 2) { 1617 if (i == sc->sc_noport) { 1618 DPRINTF("port %jd status = 0x%08jx", i, 1619 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1620 } else { 1621 DPRINTF("port %jd status = 0x%08jx port %jd " 1622 "status = 0x%08jx", 1623 i, EOREAD4(sc, EHCI_PORTSC(i)), 1624 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1625 } 1626 } 1627 } 1628 1629 #define ehci_dump_link(link, type) do { \ 1630 DPRINTF(" link 0x%08jx (T = %jd):", \ 1631 link, \ 1632 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1633 if (type) { \ 1634 DPRINTF( \ 1635 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1636 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1637 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1638 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1639 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1640 } \ 1641 } while(0) 1642 1643 Static void 1644 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1645 { 1646 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1647 int i; 1648 uint32_t stop = 0; 1649 1650 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1651 ehci_dump_sqtd(sqtd); 1652 usb_syncmem(&sqtd->dma, 1653 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1654 sizeof(sqtd->qtd), 1655 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1656 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1657 usb_syncmem(&sqtd->dma, 1658 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1659 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1660 } 1661 if (!stop) 1662 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1663 } 1664 1665 Static void 1666 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1667 { 1668 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1669 1670 usb_syncmem(&sqtd->dma, sqtd->offs, 1671 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1672 1673 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1674 0, 0); 1675 ehci_dump_qtd(&sqtd->qtd); 1676 1677 usb_syncmem(&sqtd->dma, sqtd->offs, 1678 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1679 } 1680 1681 Static void 1682 ehci_dump_qtd(ehci_qtd_t *qtd) 1683 { 1684 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1685 uint32_t s = le32toh(qtd->qtd_status); 1686 1687 DPRINTFN(10, 1688 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1689 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1690 DPRINTFN(10, 1691 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1692 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1693 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1694 DPRINTFN(10, 1695 " cerr = %jd pid = %jd stat = %jx", 1696 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1697 0); 1698 DPRINTFN(10, 1699 "active =%jd halted=%jd buferr=%jd babble=%jd", 1700 s & EHCI_QTD_ACTIVE ? 1 : 0, 1701 s & EHCI_QTD_HALTED ? 1 : 0, 1702 s & EHCI_QTD_BUFERR ? 1 : 0, 1703 s & EHCI_QTD_BABBLE ? 1 : 0); 1704 DPRINTFN(10, 1705 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1706 s & EHCI_QTD_XACTERR ? 1 : 0, 1707 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1708 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1709 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1710 DPRINTFN(10, 1711 "buffer[0] = %#jx buffer[1] = %#jx " 1712 "buffer[2] = %#jx buffer[3] = %#jx", 1713 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1714 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1715 DPRINTFN(10, 1716 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1717 } 1718 1719 Static void 1720 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1721 { 1722 ehci_qh_t *qh = &sqh->qh; 1723 ehci_link_t link; 1724 uint32_t endp, endphub; 1725 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1726 1727 usb_syncmem(&sqh->dma, sqh->offs, 1728 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1729 1730 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1731 link = le32toh(qh->qh_link); 1732 ehci_dump_link(link, true); 1733 1734 endp = le32toh(qh->qh_endp); 1735 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1736 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1737 "eps = %jd", 1738 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1739 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1740 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1741 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1742 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1743 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1744 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1745 1746 endphub = le32toh(qh->qh_endphub); 1747 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1748 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1749 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1750 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1751 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1752 EHCI_QH_GET_MULT(endphub), 0); 1753 1754 link = le32toh(qh->qh_curqtd); 1755 ehci_dump_link(link, false); 1756 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1757 ehci_dump_qtd(&qh->qh_qtd); 1758 1759 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1760 BUS_DMASYNC_PREREAD); 1761 } 1762 1763 Static void 1764 ehci_dump_itds(ehci_soft_itd_t *itd) 1765 { 1766 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1767 int i; 1768 uint32_t stop = 0; 1769 1770 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1771 ehci_dump_itd(itd); 1772 usb_syncmem(&itd->dma, 1773 itd->offs + offsetof(ehci_itd_t, itd_next), 1774 sizeof(itd->itd), 1775 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1776 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1777 usb_syncmem(&itd->dma, 1778 itd->offs + offsetof(ehci_itd_t, itd_next), 1779 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1780 } 1781 if (!stop) 1782 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1783 } 1784 1785 Static void 1786 ehci_dump_itd(struct ehci_soft_itd *itd) 1787 { 1788 ehci_isoc_trans_t t; 1789 ehci_isoc_bufr_ptr_t b, b2, b3; 1790 int i; 1791 1792 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1793 1794 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1795 1796 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1797 t = le32toh(itd->itd.itd_ctl[i]); 1798 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1799 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1800 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1801 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1802 EHCI_ITD_GET_OFFS(t), 0); 1803 } 1804 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1805 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1806 DPRINTF(" %jx", 1807 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1808 1809 b = le32toh(itd->itd.itd_bufr[0]); 1810 b2 = le32toh(itd->itd.itd_bufr[1]); 1811 b3 = le32toh(itd->itd.itd_bufr[2]); 1812 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1813 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1814 DPRINTF(" maxpkt = %jx multi = %jx", 1815 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1816 } 1817 1818 Static void 1819 ehci_dump_sitd(struct ehci_soft_itd *itd) 1820 { 1821 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1822 1823 DPRINTF("SITD %#jx next = %p prev = %#jx", 1824 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1825 (uintptr_t)itd->frame_list.prev, 0); 1826 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1827 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1828 } 1829 1830 Static void 1831 ehci_dump_exfer(struct ehci_xfer *ex) 1832 { 1833 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1834 1835 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1836 ex->ex_isdone, 0); 1837 1838 switch (ex->ex_type) { 1839 case EX_CTRL: 1840 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1841 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1842 (uintptr_t)ex->ex_status, 0); 1843 break; 1844 case EX_BULK: 1845 case EX_INTR: 1846 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1847 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1848 0, 0); 1849 break; 1850 case EX_ISOC: 1851 DPRINTF(" itdstart = %#jx itdend = %#jx", 1852 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1853 break; 1854 case EX_FS_ISOC: 1855 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1856 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1857 0, 0); 1858 break; 1859 default: 1860 DPRINTF(" unknown type", 0, 0, 0, 0); 1861 } 1862 } 1863 #endif 1864 1865 Static usbd_status 1866 ehci_open(struct usbd_pipe *pipe) 1867 { 1868 struct usbd_device *dev = pipe->up_dev; 1869 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1870 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1871 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1872 uint8_t addr = dev->ud_addr; 1873 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1874 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1875 ehci_soft_qh_t *sqh; 1876 usbd_status err; 1877 int ival, speed, naks; 1878 int hshubaddr, hshubport; 1879 1880 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1881 1882 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1883 ed->bEndpointAddress, rhaddr); 1884 1885 if (dev->ud_myhsport) { 1886 /* 1887 * When directly attached FS/LS device while doing embedded 1888 * transaction translations and we are the hub, set the hub 1889 * address to 0 (us). 1890 */ 1891 if (!(sc->sc_flags & EHCIF_ETTF) 1892 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1893 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1894 } else { 1895 hshubaddr = 0; 1896 } 1897 hshubport = dev->ud_myhsport->up_portno; 1898 } else { 1899 hshubaddr = 0; 1900 hshubport = 0; 1901 } 1902 1903 if (sc->sc_dying) 1904 return USBD_IOERROR; 1905 1906 /* toggle state needed for bulk endpoints */ 1907 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1908 1909 if (addr == rhaddr) { 1910 switch (ed->bEndpointAddress) { 1911 case USB_CONTROL_ENDPOINT: 1912 pipe->up_methods = &roothub_ctrl_methods; 1913 break; 1914 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1915 pipe->up_methods = &ehci_root_intr_methods; 1916 break; 1917 default: 1918 DPRINTF("bad bEndpointAddress 0x%02jx", 1919 ed->bEndpointAddress, 0, 0, 0); 1920 return USBD_INVAL; 1921 } 1922 return USBD_NORMAL_COMPLETION; 1923 } 1924 1925 /* XXX All this stuff is only valid for async. */ 1926 switch (dev->ud_speed) { 1927 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1928 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1929 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1930 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1931 } 1932 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1933 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1934 0); 1935 return USBD_INVAL; 1936 } 1937 1938 /* 1939 * For interrupt transfer, nak throttling must be disabled, but for 1940 * the other transfer type, nak throttling should be enabled from the 1941 * viewpoint that avoids the memory thrashing. 1942 */ 1943 naks = (xfertype == UE_INTERRUPT) ? 0 1944 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1945 1946 /* Allocate sqh for everything, save isoc xfers */ 1947 if (xfertype != UE_ISOCHRONOUS) { 1948 sqh = ehci_alloc_sqh(sc); 1949 if (sqh == NULL) 1950 return USBD_NOMEM; 1951 /* qh_link filled when the QH is added */ 1952 sqh->qh.qh_endp = htole32( 1953 EHCI_QH_SET_ADDR(addr) | 1954 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1955 EHCI_QH_SET_EPS(speed) | 1956 EHCI_QH_DTC | 1957 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1958 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1959 EHCI_QH_CTL : 0) | 1960 EHCI_QH_SET_NRL(naks) 1961 ); 1962 sqh->qh.qh_endphub = htole32( 1963 EHCI_QH_SET_MULT(1) | 1964 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1965 ); 1966 if (speed != EHCI_QH_SPEED_HIGH) 1967 sqh->qh.qh_endphub |= htole32( 1968 EHCI_QH_SET_PORT(hshubport) | 1969 EHCI_QH_SET_HUBA(hshubaddr) | 1970 (xfertype == UE_INTERRUPT ? 1971 EHCI_QH_SET_CMASK(0x08) : 0) 1972 ); 1973 sqh->qh.qh_curqtd = EHCI_NULL; 1974 /* Fill the overlay qTD */ 1975 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1976 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1977 sqh->qh.qh_qtd.qtd_status = htole32(0); 1978 1979 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1980 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1981 epipe->sqh = sqh; 1982 } else { 1983 sqh = NULL; 1984 } /*xfertype == UE_ISOC*/ 1985 1986 switch (xfertype) { 1987 case UE_CONTROL: 1988 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1989 0, &epipe->ctrl.reqdma); 1990 #ifdef EHCI_DEBUG 1991 if (err) 1992 printf("ehci_open: usb_allocmem()=%d\n", err); 1993 #endif 1994 if (err) 1995 goto bad; 1996 pipe->up_methods = &ehci_device_ctrl_methods; 1997 mutex_enter(&sc->sc_lock); 1998 ehci_add_qh(sc, sqh, sc->sc_async_head); 1999 mutex_exit(&sc->sc_lock); 2000 break; 2001 case UE_BULK: 2002 pipe->up_methods = &ehci_device_bulk_methods; 2003 mutex_enter(&sc->sc_lock); 2004 ehci_add_qh(sc, sqh, sc->sc_async_head); 2005 mutex_exit(&sc->sc_lock); 2006 break; 2007 case UE_INTERRUPT: 2008 pipe->up_methods = &ehci_device_intr_methods; 2009 ival = pipe->up_interval; 2010 if (ival == USBD_DEFAULT_INTERVAL) { 2011 if (speed == EHCI_QH_SPEED_HIGH) { 2012 if (ed->bInterval > 16) { 2013 /* 2014 * illegal with high-speed, but there 2015 * were documentation bugs in the spec, 2016 * so be generous 2017 */ 2018 ival = 256; 2019 } else 2020 ival = (1 << (ed->bInterval - 1)) / 8; 2021 } else 2022 ival = ed->bInterval; 2023 } 2024 err = ehci_device_setintr(sc, sqh, ival); 2025 if (err) 2026 goto bad; 2027 break; 2028 case UE_ISOCHRONOUS: 2029 pipe->up_serialise = false; 2030 if (speed == EHCI_QH_SPEED_HIGH) 2031 pipe->up_methods = &ehci_device_isoc_methods; 2032 else 2033 pipe->up_methods = &ehci_device_fs_isoc_methods; 2034 if (ed->bInterval == 0 || ed->bInterval > 16) { 2035 printf("ehci: opening pipe with invalid bInterval\n"); 2036 err = USBD_INVAL; 2037 goto bad; 2038 } 2039 if (UGETW(ed->wMaxPacketSize) == 0) { 2040 printf("ehci: zero length endpoint open request\n"); 2041 err = USBD_INVAL; 2042 goto bad; 2043 } 2044 epipe->isoc.next_frame = 0; 2045 epipe->isoc.cur_xfers = 0; 2046 break; 2047 default: 2048 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2049 err = USBD_INVAL; 2050 goto bad; 2051 } 2052 return USBD_NORMAL_COMPLETION; 2053 2054 bad: 2055 if (sqh != NULL) { 2056 mutex_enter(&sc->sc_lock); 2057 ehci_free_sqh(sc, sqh); 2058 mutex_exit(&sc->sc_lock); 2059 } 2060 return err; 2061 } 2062 2063 /* 2064 * Add an ED to the schedule. Called with USB lock held. 2065 */ 2066 Static void 2067 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2068 { 2069 2070 KASSERT(mutex_owned(&sc->sc_lock)); 2071 2072 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2073 2074 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2075 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2076 2077 sqh->next = head->next; 2078 sqh->qh.qh_link = head->qh.qh_link; 2079 2080 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2081 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2082 2083 head->next = sqh; 2084 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2085 2086 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2087 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2088 2089 #ifdef EHCI_DEBUG 2090 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2091 ehci_dump_sqh(sqh); 2092 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2093 #endif 2094 } 2095 2096 /* 2097 * Remove an ED from the schedule. Called with USB lock held. 2098 */ 2099 Static void 2100 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2101 { 2102 ehci_soft_qh_t *p; 2103 2104 KASSERT(mutex_owned(&sc->sc_lock)); 2105 2106 /* XXX */ 2107 for (p = head; p != NULL && p->next != sqh; p = p->next) 2108 ; 2109 if (p == NULL) 2110 panic("ehci_rem_qh: ED not found"); 2111 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2112 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2113 p->next = sqh->next; 2114 p->qh.qh_link = sqh->qh.qh_link; 2115 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2116 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2117 2118 ehci_sync_hc(sc); 2119 } 2120 2121 Static void 2122 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2123 { 2124 int i; 2125 uint32_t status; 2126 2127 /* Save toggle bit and ping status. */ 2128 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2129 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2130 status = sqh->qh.qh_qtd.qtd_status & 2131 htole32(EHCI_QTD_TOGGLE_MASK | 2132 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2133 /* Set HALTED to make hw leave it alone. */ 2134 sqh->qh.qh_qtd.qtd_status = 2135 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2136 usb_syncmem(&sqh->dma, 2137 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2138 sizeof(sqh->qh.qh_qtd.qtd_status), 2139 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2140 sqh->qh.qh_curqtd = 0; 2141 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2142 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2143 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2144 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2145 sqh->sqtd = sqtd; 2146 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2147 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2148 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2149 sqh->qh.qh_qtd.qtd_status = status; 2150 usb_syncmem(&sqh->dma, 2151 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2152 sizeof(sqh->qh.qh_qtd.qtd_status), 2153 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2154 } 2155 2156 /* 2157 * Ensure that the HC has released all references to the QH. We do this 2158 * by asking for a Async Advance Doorbell interrupt and then we wait for 2159 * the interrupt. 2160 * To make this easier we first obtain exclusive use of the doorbell. 2161 */ 2162 Static void 2163 ehci_sync_hc(ehci_softc_t *sc) 2164 { 2165 int error __diagused; 2166 2167 KASSERT(mutex_owned(&sc->sc_lock)); 2168 2169 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2170 2171 if (sc->sc_dying) { 2172 DPRINTF("dying", 0, 0, 0, 0); 2173 return; 2174 } 2175 /* ask for doorbell */ 2176 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2177 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2178 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2179 2180 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2181 2182 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2183 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2184 #ifdef DIAGNOSTIC 2185 if (error == EWOULDBLOCK) { 2186 printf("ehci_sync_hc: timed out\n"); 2187 } else if (error) { 2188 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2189 } 2190 #endif 2191 } 2192 2193 Static void 2194 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2195 { 2196 2197 KASSERT(mutex_owned(&sc->sc_lock)); 2198 2199 for (; itd != NULL; itd = itd->xfer_next) { 2200 struct ehci_soft_itd *prev = itd->frame_list.prev; 2201 2202 /* Unlink itd from hardware chain, or frame array */ 2203 if (prev == NULL) { /* We're at the table head */ 2204 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2205 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2206 usb_syncmem(&sc->sc_fldma, 2207 sizeof(ehci_link_t) * itd->slot, 2208 sizeof(ehci_link_t), 2209 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2210 2211 if (itd->frame_list.next != NULL) 2212 itd->frame_list.next->frame_list.prev = NULL; 2213 } else { 2214 /* XXX this part is untested... */ 2215 prev->itd.itd_next = itd->itd.itd_next; 2216 usb_syncmem(&itd->dma, 2217 itd->offs + offsetof(ehci_itd_t, itd_next), 2218 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2219 2220 prev->frame_list.next = itd->frame_list.next; 2221 if (itd->frame_list.next != NULL) 2222 itd->frame_list.next->frame_list.prev = prev; 2223 } 2224 } 2225 } 2226 2227 Static void 2228 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2229 { 2230 struct ehci_soft_itd *next; 2231 2232 mutex_enter(&sc->sc_lock); 2233 next = NULL; 2234 for (; itd != NULL; itd = next) { 2235 next = itd->xfer_next; 2236 ehci_free_itd_locked(sc, itd); 2237 } 2238 mutex_exit(&sc->sc_lock); 2239 } 2240 2241 Static void 2242 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2243 { 2244 2245 KASSERT(mutex_owned(&sc->sc_lock)); 2246 2247 for (; sitd != NULL; sitd = sitd->xfer_next) { 2248 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2249 2250 /* Unlink sitd from hardware chain, or frame array */ 2251 if (prev == NULL) { /* We're at the table head */ 2252 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2253 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2254 usb_syncmem(&sc->sc_fldma, 2255 sizeof(ehci_link_t) * sitd->slot, 2256 sizeof(ehci_link_t), 2257 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2258 2259 if (sitd->frame_list.next != NULL) 2260 sitd->frame_list.next->frame_list.prev = NULL; 2261 } else { 2262 /* XXX this part is untested... */ 2263 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2264 usb_syncmem(&sitd->dma, 2265 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2266 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2267 2268 prev->frame_list.next = sitd->frame_list.next; 2269 if (sitd->frame_list.next != NULL) 2270 sitd->frame_list.next->frame_list.prev = prev; 2271 } 2272 } 2273 } 2274 2275 Static void 2276 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2277 { 2278 2279 mutex_enter(&sc->sc_lock); 2280 struct ehci_soft_sitd *next = NULL; 2281 for (; sitd != NULL; sitd = next) { 2282 next = sitd->xfer_next; 2283 ehci_free_sitd_locked(sc, sitd); 2284 } 2285 mutex_exit(&sc->sc_lock); 2286 } 2287 2288 /***********/ 2289 2290 Static int 2291 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2292 void *buf, int buflen) 2293 { 2294 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2295 usb_hub_descriptor_t hubd; 2296 usb_port_status_t ps; 2297 uint16_t len, value, index; 2298 int l, totlen = 0; 2299 int port, i; 2300 uint32_t v; 2301 2302 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2303 2304 if (sc->sc_dying) 2305 return -1; 2306 2307 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2308 0, 0); 2309 2310 len = UGETW(req->wLength); 2311 value = UGETW(req->wValue); 2312 index = UGETW(req->wIndex); 2313 2314 #define C(x,y) ((x) | ((y) << 8)) 2315 switch (C(req->bRequest, req->bmRequestType)) { 2316 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2317 if (len == 0) 2318 break; 2319 switch (value) { 2320 #define sd ((usb_string_descriptor_t *)buf) 2321 case C(2, UDESC_STRING): 2322 /* Product */ 2323 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2324 break; 2325 #undef sd 2326 default: 2327 /* default from usbroothub */ 2328 return buflen; 2329 } 2330 break; 2331 2332 /* Hub requests */ 2333 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2334 break; 2335 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2336 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2337 value, 0, 0); 2338 if (index < 1 || index > sc->sc_noport) { 2339 return -1; 2340 } 2341 port = EHCI_PORTSC(index); 2342 v = EOREAD4(sc, port); 2343 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2344 v &= ~EHCI_PS_CLEAR; 2345 switch (value) { 2346 case UHF_PORT_ENABLE: 2347 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2348 break; 2349 case UHF_PORT_SUSPEND: 2350 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2351 break; 2352 v &= ~EHCI_PS_SUSP; 2353 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2354 /* see USB2 spec ch. 7.1.7.7 */ 2355 usb_delay_ms(&sc->sc_bus, 20); 2356 EOWRITE4(sc, port, v); 2357 usb_delay_ms(&sc->sc_bus, 2); 2358 #ifdef DEBUG 2359 v = EOREAD4(sc, port); 2360 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2361 printf("ehci: resume failed: %x\n", v); 2362 #endif 2363 break; 2364 case UHF_PORT_POWER: 2365 if (sc->sc_hasppc) 2366 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2367 break; 2368 case UHF_PORT_TEST: 2369 DPRINTF("clear port test %jd", index, 0, 0, 0); 2370 break; 2371 case UHF_PORT_INDICATOR: 2372 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2373 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2374 break; 2375 case UHF_C_PORT_CONNECTION: 2376 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2377 break; 2378 case UHF_C_PORT_ENABLE: 2379 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2380 break; 2381 case UHF_C_PORT_SUSPEND: 2382 /* how? */ 2383 break; 2384 case UHF_C_PORT_OVER_CURRENT: 2385 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2386 break; 2387 case UHF_C_PORT_RESET: 2388 sc->sc_isreset[index] = 0; 2389 break; 2390 default: 2391 return -1; 2392 } 2393 #if 0 2394 switch(value) { 2395 case UHF_C_PORT_CONNECTION: 2396 case UHF_C_PORT_ENABLE: 2397 case UHF_C_PORT_SUSPEND: 2398 case UHF_C_PORT_OVER_CURRENT: 2399 case UHF_C_PORT_RESET: 2400 default: 2401 break; 2402 } 2403 #endif 2404 break; 2405 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2406 if (len == 0) 2407 break; 2408 if ((value & 0xff) != 0) { 2409 return -1; 2410 } 2411 totlen = min(buflen, sizeof(hubd)); 2412 memcpy(&hubd, buf, totlen); 2413 hubd.bNbrPorts = sc->sc_noport; 2414 v = EOREAD4(sc, EHCI_HCSPARAMS); 2415 USETW(hubd.wHubCharacteristics, 2416 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2417 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2418 ? UHD_PORT_IND : 0); 2419 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2420 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2421 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2422 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2423 totlen = min(totlen, hubd.bDescLength); 2424 memcpy(buf, &hubd, totlen); 2425 break; 2426 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2427 if (len != 4) { 2428 return -1; 2429 } 2430 memset(buf, 0, len); /* ? XXX */ 2431 totlen = len; 2432 break; 2433 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2434 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2435 if (index < 1 || index > sc->sc_noport) { 2436 return -1; 2437 } 2438 if (len != 4) { 2439 return -1; 2440 } 2441 v = EOREAD4(sc, EHCI_PORTSC(index)); 2442 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2443 2444 i = UPS_HIGH_SPEED; 2445 if (sc->sc_flags & EHCIF_ETTF) { 2446 /* 2447 * If we are doing embedded transaction translation, 2448 * then directly attached LS/FS devices are reset by 2449 * the EHCI controller itself. PSPD is encoded 2450 * the same way as in USBSTATUS. 2451 */ 2452 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2453 } 2454 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2455 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2456 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2457 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2458 if (v & EHCI_PS_PR) i |= UPS_RESET; 2459 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2460 if (sc->sc_vendor_port_status) 2461 i = sc->sc_vendor_port_status(sc, v, i); 2462 USETW(ps.wPortStatus, i); 2463 i = 0; 2464 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2465 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2466 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2467 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2468 USETW(ps.wPortChange, i); 2469 totlen = min(len, sizeof(ps)); 2470 memcpy(buf, &ps, totlen); 2471 break; 2472 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2473 return -1; 2474 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2475 break; 2476 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2477 if (index < 1 || index > sc->sc_noport) { 2478 return -1; 2479 } 2480 port = EHCI_PORTSC(index); 2481 v = EOREAD4(sc, port); 2482 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2483 v &= ~EHCI_PS_CLEAR; 2484 switch(value) { 2485 case UHF_PORT_ENABLE: 2486 EOWRITE4(sc, port, v | EHCI_PS_PE); 2487 break; 2488 case UHF_PORT_SUSPEND: 2489 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2490 break; 2491 case UHF_PORT_RESET: 2492 DPRINTF("reset port %jd", index, 0, 0, 0); 2493 if (EHCI_PS_IS_LOWSPEED(v) 2494 && sc->sc_ncomp > 0 2495 && !(sc->sc_flags & EHCIF_ETTF)) { 2496 /* 2497 * Low speed device on non-ETTF controller or 2498 * unaccompanied controller, give up ownership. 2499 */ 2500 ehci_disown(sc, index, 1); 2501 break; 2502 } 2503 /* Start reset sequence. */ 2504 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2505 EOWRITE4(sc, port, v | EHCI_PS_PR); 2506 /* Wait for reset to complete. */ 2507 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2508 if (sc->sc_dying) { 2509 return -1; 2510 } 2511 /* 2512 * An embedded transaction translator will automatically 2513 * terminate the reset sequence so there's no need to 2514 * it. 2515 */ 2516 v = EOREAD4(sc, port); 2517 if (v & EHCI_PS_PR) { 2518 /* Terminate reset sequence. */ 2519 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2520 /* Wait for HC to complete reset. */ 2521 usb_delay_ms(&sc->sc_bus, 2522 EHCI_PORT_RESET_COMPLETE); 2523 if (sc->sc_dying) { 2524 return -1; 2525 } 2526 } 2527 2528 v = EOREAD4(sc, port); 2529 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2530 if (v & EHCI_PS_PR) { 2531 printf("%s: port reset timeout\n", 2532 device_xname(sc->sc_dev)); 2533 return USBD_TIMEOUT; 2534 } 2535 if (!(v & EHCI_PS_PE)) { 2536 /* Not a high speed device, give up ownership.*/ 2537 ehci_disown(sc, index, 0); 2538 break; 2539 } 2540 sc->sc_isreset[index] = 1; 2541 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2542 v, 0, 0); 2543 break; 2544 case UHF_PORT_POWER: 2545 DPRINTF("set port power %jd (has PPC = %jd)", index, 2546 sc->sc_hasppc, 0, 0); 2547 if (sc->sc_hasppc) 2548 EOWRITE4(sc, port, v | EHCI_PS_PP); 2549 break; 2550 case UHF_PORT_TEST: 2551 DPRINTF("set port test %jd", index, 0, 0, 0); 2552 break; 2553 case UHF_PORT_INDICATOR: 2554 DPRINTF("set port ind %jd", index, 0, 0, 0); 2555 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2556 break; 2557 default: 2558 return -1; 2559 } 2560 break; 2561 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2562 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2563 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2564 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2565 break; 2566 default: 2567 /* default from usbroothub */ 2568 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2569 2570 return buflen; 2571 } 2572 2573 DPRINTF("returning %jd", totlen, 0, 0, 0); 2574 2575 return totlen; 2576 } 2577 2578 Static void 2579 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2580 { 2581 int port; 2582 uint32_t v; 2583 2584 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2585 2586 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2587 #ifdef DIAGNOSTIC 2588 if (sc->sc_npcomp != 0) { 2589 int i = (index-1) / sc->sc_npcomp; 2590 if (i >= sc->sc_ncomp) 2591 printf("%s: strange port\n", 2592 device_xname(sc->sc_dev)); 2593 else 2594 printf("%s: handing over %s speed device on " 2595 "port %d to %s\n", 2596 device_xname(sc->sc_dev), 2597 lowspeed ? "low" : "full", 2598 index, sc->sc_comps[i] ? 2599 device_xname(sc->sc_comps[i]) : 2600 "companion controller"); 2601 } else { 2602 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2603 } 2604 #endif 2605 port = EHCI_PORTSC(index); 2606 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2607 EOWRITE4(sc, port, v | EHCI_PS_PO); 2608 } 2609 2610 Static usbd_status 2611 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2612 { 2613 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2614 usbd_status err; 2615 2616 /* Insert last in queue. */ 2617 mutex_enter(&sc->sc_lock); 2618 err = usb_insert_transfer(xfer); 2619 mutex_exit(&sc->sc_lock); 2620 if (err) 2621 return err; 2622 2623 /* Pipe isn't running, start first */ 2624 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2625 } 2626 2627 Static usbd_status 2628 ehci_root_intr_start(struct usbd_xfer *xfer) 2629 { 2630 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2631 2632 if (sc->sc_dying) 2633 return USBD_IOERROR; 2634 2635 mutex_enter(&sc->sc_lock); 2636 sc->sc_intrxfer = xfer; 2637 mutex_exit(&sc->sc_lock); 2638 2639 return USBD_IN_PROGRESS; 2640 } 2641 2642 /* Abort a root interrupt request. */ 2643 Static void 2644 ehci_root_intr_abort(struct usbd_xfer *xfer) 2645 { 2646 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2647 2648 KASSERT(mutex_owned(&sc->sc_lock)); 2649 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2650 2651 sc->sc_intrxfer = NULL; 2652 2653 xfer->ux_status = USBD_CANCELLED; 2654 usb_transfer_complete(xfer); 2655 } 2656 2657 /* Close the root pipe. */ 2658 Static void 2659 ehci_root_intr_close(struct usbd_pipe *pipe) 2660 { 2661 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2662 2663 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2664 2665 KASSERT(mutex_owned(&sc->sc_lock)); 2666 2667 sc->sc_intrxfer = NULL; 2668 } 2669 2670 Static void 2671 ehci_root_intr_done(struct usbd_xfer *xfer) 2672 { 2673 } 2674 2675 /************************/ 2676 2677 Static ehci_soft_qh_t * 2678 ehci_alloc_sqh(ehci_softc_t *sc) 2679 { 2680 ehci_soft_qh_t *sqh; 2681 usbd_status err; 2682 int i, offs; 2683 usb_dma_t dma; 2684 2685 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2686 2687 mutex_enter(&sc->sc_lock); 2688 if (sc->sc_freeqhs == NULL) { 2689 DPRINTF("allocating chunk", 0, 0, 0, 0); 2690 mutex_exit(&sc->sc_lock); 2691 2692 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2693 EHCI_PAGE_SIZE, &dma); 2694 #ifdef EHCI_DEBUG 2695 if (err) 2696 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2697 #endif 2698 if (err) 2699 return NULL; 2700 2701 mutex_enter(&sc->sc_lock); 2702 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2703 offs = i * EHCI_SQH_SIZE; 2704 sqh = KERNADDR(&dma, offs); 2705 sqh->physaddr = DMAADDR(&dma, offs); 2706 sqh->dma = dma; 2707 sqh->offs = offs; 2708 sqh->next = sc->sc_freeqhs; 2709 sc->sc_freeqhs = sqh; 2710 } 2711 } 2712 sqh = sc->sc_freeqhs; 2713 sc->sc_freeqhs = sqh->next; 2714 mutex_exit(&sc->sc_lock); 2715 2716 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2717 sqh->next = NULL; 2718 return sqh; 2719 } 2720 2721 Static void 2722 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2723 { 2724 KASSERT(mutex_owned(&sc->sc_lock)); 2725 2726 sqh->next = sc->sc_freeqhs; 2727 sc->sc_freeqhs = sqh; 2728 } 2729 2730 Static ehci_soft_qtd_t * 2731 ehci_alloc_sqtd(ehci_softc_t *sc) 2732 { 2733 ehci_soft_qtd_t *sqtd = NULL; 2734 usbd_status err; 2735 int i, offs; 2736 usb_dma_t dma; 2737 2738 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2739 2740 mutex_enter(&sc->sc_lock); 2741 if (sc->sc_freeqtds == NULL) { 2742 DPRINTF("allocating chunk", 0, 0, 0, 0); 2743 mutex_exit(&sc->sc_lock); 2744 2745 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2746 EHCI_PAGE_SIZE, &dma); 2747 #ifdef EHCI_DEBUG 2748 if (err) 2749 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2750 #endif 2751 if (err) 2752 goto done; 2753 2754 mutex_enter(&sc->sc_lock); 2755 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2756 offs = i * EHCI_SQTD_SIZE; 2757 sqtd = KERNADDR(&dma, offs); 2758 sqtd->physaddr = DMAADDR(&dma, offs); 2759 sqtd->dma = dma; 2760 sqtd->offs = offs; 2761 2762 sqtd->nextqtd = sc->sc_freeqtds; 2763 sc->sc_freeqtds = sqtd; 2764 } 2765 } 2766 2767 sqtd = sc->sc_freeqtds; 2768 sc->sc_freeqtds = sqtd->nextqtd; 2769 mutex_exit(&sc->sc_lock); 2770 2771 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2772 sqtd->nextqtd = NULL; 2773 sqtd->xfer = NULL; 2774 2775 done: 2776 return sqtd; 2777 } 2778 2779 Static void 2780 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2781 { 2782 2783 mutex_enter(&sc->sc_lock); 2784 sqtd->nextqtd = sc->sc_freeqtds; 2785 sc->sc_freeqtds = sqtd; 2786 mutex_exit(&sc->sc_lock); 2787 } 2788 2789 Static int 2790 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2791 int alen, int rd, ehci_soft_qtd_t **sp) 2792 { 2793 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2794 uint16_t flags = xfer->ux_flags; 2795 2796 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2797 2798 ASSERT_SLEEPABLE(); 2799 KASSERT(sp); 2800 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2801 2802 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2803 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2804 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2805 KM_SLEEP); 2806 exfer->ex_nsqtd = nsqtd; 2807 2808 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2809 alen, nsqtd, flags); 2810 2811 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2812 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2813 if (cur == NULL) 2814 goto nomem; 2815 exfer->ex_sqtds[j++] = cur; 2816 2817 cur->xfer = xfer; 2818 cur->len = 0; 2819 2820 } 2821 2822 *sp = exfer->ex_sqtds[0]; 2823 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2824 2825 return 0; 2826 2827 nomem: 2828 ehci_free_sqtds(sc, exfer); 2829 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2830 DPRINTF("no memory", 0, 0, 0, 0); 2831 return ENOMEM; 2832 } 2833 2834 Static void 2835 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2836 { 2837 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2838 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2839 2840 mutex_enter(&sc->sc_lock); 2841 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2842 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2843 2844 if (sqtd == NULL) 2845 break; 2846 2847 sqtd->nextqtd = sc->sc_freeqtds; 2848 sc->sc_freeqtds = sqtd; 2849 } 2850 mutex_exit(&sc->sc_lock); 2851 } 2852 2853 Static void 2854 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2855 { 2856 if (prev) { 2857 prev->nextqtd = sqtd; 2858 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2859 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2860 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2861 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2862 } 2863 } 2864 2865 Static void 2866 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2867 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2868 { 2869 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2870 usb_dma_t *dma = &xfer->ux_dmabuf; 2871 uint16_t flags = xfer->ux_flags; 2872 ehci_soft_qtd_t *sqtd, *prev; 2873 int tog = *toggle; 2874 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2875 int len = length; 2876 2877 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2878 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2879 len, isread, tog); 2880 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2881 0, 0, 0); 2882 2883 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2884 2885 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2886 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2887 EHCI_QTD_SET_CERR(3) 2888 ; 2889 2890 sqtd = prev = NULL; 2891 size_t curoffs = 0; 2892 size_t j = 0; 2893 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2894 sqtd = exfer->ex_sqtds[j++]; 2895 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 2896 (uintptr_t)prev, 0); 2897 2898 /* 2899 * The EHCI hardware can handle at most 5 pages and they do 2900 * not have to be contiguous 2901 */ 2902 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2903 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2904 size_t curlen = len; 2905 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2906 /* must use multiple TDs, fill as much as possible. */ 2907 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2908 2909 /* the length must be a multiple of the max size */ 2910 curlen -= curlen % mps; 2911 } 2912 KASSERT(curlen != 0); 2913 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 2914 curoffs, 0); 2915 2916 /* Fill the qTD */ 2917 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2918 sqtd->qtd.qtd_status = htole32( 2919 qtdstatus | 2920 EHCI_QTD_SET_BYTES(curlen) | 2921 EHCI_QTD_SET_TOGGLE(tog)); 2922 2923 /* Find number of pages we'll be using, insert dma addresses */ 2924 size_t pages = EHCI_NPAGES(curlen); 2925 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2926 size_t pageoffs = EHCI_PAGE(curoffs); 2927 for (size_t i = 0; i < pages; i++) { 2928 paddr_t a = DMAADDR(dma, 2929 pageoffs + i * EHCI_PAGE_SIZE); 2930 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2931 /* Cast up to avoid compiler warnings */ 2932 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2933 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 2934 i, pages, 2935 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2936 le32toh(sqtd->qtd.qtd_buffer[i])); 2937 } 2938 /* First buffer pointer requires a page offset to start at */ 2939 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2940 2941 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2942 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2943 2944 sqtd->len = curlen; 2945 2946 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 2947 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2948 2949 ehci_append_sqtd(sqtd, prev); 2950 2951 if (((curlen + mps - 1) / mps) & 1) { 2952 tog ^= 1; 2953 } 2954 2955 curoffs += curlen; 2956 len -= curlen; 2957 } 2958 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2959 xfer, length, len, mps, exfer->ex_nsqtd, j); 2960 2961 if (!isread && 2962 (flags & USBD_FORCE_SHORT_XFER) && 2963 length % mps == 0) { 2964 /* Force a 0 length transfer at the end. */ 2965 2966 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2967 exfer->ex_nsqtd); 2968 prev = sqtd; 2969 sqtd = exfer->ex_sqtds[j++]; 2970 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 2971 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2972 sqtd->qtd.qtd_status = htole32( 2973 qtdstatus | 2974 EHCI_QTD_SET_BYTES(0) | 2975 EHCI_QTD_SET_TOGGLE(tog)); 2976 2977 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2978 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2979 2980 ehci_append_sqtd(sqtd, prev); 2981 tog ^= 1; 2982 } 2983 2984 *lsqtd = sqtd; 2985 *toggle = tog; 2986 } 2987 2988 Static ehci_soft_itd_t * 2989 ehci_alloc_itd(ehci_softc_t *sc) 2990 { 2991 struct ehci_soft_itd *itd, *freeitd; 2992 usbd_status err; 2993 usb_dma_t dma; 2994 2995 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2996 2997 mutex_enter(&sc->sc_lock); 2998 2999 freeitd = LIST_FIRST(&sc->sc_freeitds); 3000 if (freeitd == NULL) { 3001 DPRINTF("allocating chunk", 0, 0, 0, 0); 3002 mutex_exit(&sc->sc_lock); 3003 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3004 EHCI_PAGE_SIZE, &dma); 3005 3006 if (err) { 3007 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3008 return NULL; 3009 } 3010 mutex_enter(&sc->sc_lock); 3011 3012 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3013 int offs = i * EHCI_ITD_SIZE; 3014 itd = KERNADDR(&dma, offs); 3015 itd->physaddr = DMAADDR(&dma, offs); 3016 itd->dma = dma; 3017 itd->offs = offs; 3018 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3019 } 3020 freeitd = LIST_FIRST(&sc->sc_freeitds); 3021 } 3022 3023 itd = freeitd; 3024 LIST_REMOVE(itd, free_list); 3025 mutex_exit(&sc->sc_lock); 3026 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3027 3028 itd->frame_list.next = NULL; 3029 itd->frame_list.prev = NULL; 3030 itd->xfer_next = NULL; 3031 itd->slot = 0; 3032 3033 return itd; 3034 } 3035 3036 Static ehci_soft_sitd_t * 3037 ehci_alloc_sitd(ehci_softc_t *sc) 3038 { 3039 struct ehci_soft_sitd *sitd, *freesitd; 3040 usbd_status err; 3041 int i, offs; 3042 usb_dma_t dma; 3043 3044 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3045 3046 mutex_enter(&sc->sc_lock); 3047 freesitd = LIST_FIRST(&sc->sc_freesitds); 3048 if (freesitd == NULL) { 3049 DPRINTF("allocating chunk", 0, 0, 0, 0); 3050 mutex_exit(&sc->sc_lock); 3051 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3052 EHCI_PAGE_SIZE, &dma); 3053 3054 if (err) { 3055 DPRINTF("alloc returned %jd", err, 0, 0, 3056 0); 3057 return NULL; 3058 } 3059 3060 mutex_enter(&sc->sc_lock); 3061 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3062 offs = i * EHCI_SITD_SIZE; 3063 sitd = KERNADDR(&dma, offs); 3064 sitd->physaddr = DMAADDR(&dma, offs); 3065 sitd->dma = dma; 3066 sitd->offs = offs; 3067 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3068 } 3069 freesitd = LIST_FIRST(&sc->sc_freesitds); 3070 } 3071 3072 sitd = freesitd; 3073 LIST_REMOVE(sitd, free_list); 3074 mutex_exit(&sc->sc_lock); 3075 3076 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3077 3078 sitd->frame_list.next = NULL; 3079 sitd->frame_list.prev = NULL; 3080 sitd->xfer_next = NULL; 3081 sitd->slot = 0; 3082 3083 return sitd; 3084 } 3085 3086 /****************/ 3087 3088 /* 3089 * Close a reqular pipe. 3090 * Assumes that there are no pending transactions. 3091 */ 3092 Static void 3093 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3094 { 3095 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3096 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3097 ehci_soft_qh_t *sqh = epipe->sqh; 3098 3099 KASSERT(mutex_owned(&sc->sc_lock)); 3100 3101 ehci_rem_qh(sc, sqh, head); 3102 ehci_free_sqh(sc, epipe->sqh); 3103 } 3104 3105 /* 3106 * Abort a device request. 3107 * If this routine is called at splusb() it guarantees that the request 3108 * will be removed from the hardware scheduling and that the callback 3109 * for it will be called with USBD_CANCELLED status. 3110 * It's impossible to guarantee that the requested transfer will not 3111 * have happened since the hardware runs concurrently. 3112 * If the transaction has already happened we rely on the ordinary 3113 * interrupt processing to process it. 3114 * XXX This is most probably wrong. 3115 * XXXMRG this doesn't make sense anymore. 3116 */ 3117 Static void 3118 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3119 { 3120 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3121 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3122 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3123 ehci_soft_qh_t *sqh = epipe->sqh; 3124 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3125 ehci_physaddr_t cur; 3126 uint32_t qhstatus; 3127 int hit; 3128 int wake; 3129 3130 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3131 3132 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3133 3134 KASSERT(mutex_owned(&sc->sc_lock)); 3135 ASSERT_SLEEPABLE(); 3136 3137 if (sc->sc_dying) { 3138 /* If we're dying, just do the software part. */ 3139 xfer->ux_status = status; /* make software ignore it */ 3140 callout_stop(&xfer->ux_callout); 3141 usb_transfer_complete(xfer); 3142 return; 3143 } 3144 3145 /* 3146 * If an abort is already in progress then just wait for it to 3147 * complete and return. 3148 */ 3149 if (xfer->ux_hcflags & UXFER_ABORTING) { 3150 DPRINTF("already aborting", 0, 0, 0, 0); 3151 #ifdef DIAGNOSTIC 3152 if (status == USBD_TIMEOUT) 3153 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3154 #endif 3155 /* Override the status which might be USBD_TIMEOUT. */ 3156 xfer->ux_status = status; 3157 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3158 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3159 while (xfer->ux_hcflags & UXFER_ABORTING) 3160 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3161 return; 3162 } 3163 xfer->ux_hcflags |= UXFER_ABORTING; 3164 3165 /* 3166 * Step 1: Make interrupt routine and hardware ignore xfer. 3167 */ 3168 xfer->ux_status = status; /* make software ignore it */ 3169 callout_stop(&xfer->ux_callout); 3170 ehci_del_intr_list(sc, exfer); 3171 3172 usb_syncmem(&sqh->dma, 3173 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3174 sizeof(sqh->qh.qh_qtd.qtd_status), 3175 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3176 qhstatus = sqh->qh.qh_qtd.qtd_status; 3177 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3178 usb_syncmem(&sqh->dma, 3179 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3180 sizeof(sqh->qh.qh_qtd.qtd_status), 3181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3182 3183 if (exfer->ex_type == EX_CTRL) { 3184 fsqtd = exfer->ex_setup; 3185 lsqtd = exfer->ex_status; 3186 } else { 3187 fsqtd = exfer->ex_sqtdstart; 3188 lsqtd = exfer->ex_sqtdend; 3189 } 3190 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3191 usb_syncmem(&sqtd->dma, 3192 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3193 sizeof(sqtd->qtd.qtd_status), 3194 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3195 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3196 usb_syncmem(&sqtd->dma, 3197 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3198 sizeof(sqtd->qtd.qtd_status), 3199 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3200 if (sqtd == lsqtd) 3201 break; 3202 } 3203 3204 /* 3205 * Step 2: Wait until we know hardware has finished any possible 3206 * use of the xfer. Also make sure the soft interrupt routine 3207 * has run. 3208 */ 3209 ehci_sync_hc(sc); 3210 sc->sc_softwake = 1; 3211 usb_schedsoftintr(&sc->sc_bus); 3212 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3213 3214 /* 3215 * Step 3: Remove any vestiges of the xfer from the hardware. 3216 * The complication here is that the hardware may have executed 3217 * beyond the xfer we're trying to abort. So as we're scanning 3218 * the TDs of this xfer we check if the hardware points to 3219 * any of them. 3220 */ 3221 3222 usb_syncmem(&sqh->dma, 3223 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3224 sizeof(sqh->qh.qh_curqtd), 3225 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3226 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3227 hit = 0; 3228 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3229 hit |= cur == sqtd->physaddr; 3230 if (sqtd == lsqtd) 3231 break; 3232 } 3233 sqtd = sqtd->nextqtd; 3234 /* Zap curqtd register if hardware pointed inside the xfer. */ 3235 if (hit && sqtd != NULL) { 3236 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3237 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3238 usb_syncmem(&sqh->dma, 3239 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3240 sizeof(sqh->qh.qh_curqtd), 3241 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3242 sqh->qh.qh_qtd.qtd_status = qhstatus; 3243 usb_syncmem(&sqh->dma, 3244 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3245 sizeof(sqh->qh.qh_qtd.qtd_status), 3246 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3247 } else { 3248 DPRINTF("no hit", 0, 0, 0, 0); 3249 usb_syncmem(&sqh->dma, 3250 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3251 sizeof(sqh->qh.qh_curqtd), 3252 BUS_DMASYNC_PREREAD); 3253 } 3254 3255 /* 3256 * Step 4: Execute callback. 3257 */ 3258 #ifdef DIAGNOSTIC 3259 exfer->ex_isdone = true; 3260 #endif 3261 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3262 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3263 usb_transfer_complete(xfer); 3264 if (wake) { 3265 cv_broadcast(&xfer->ux_hccv); 3266 } 3267 3268 KASSERT(mutex_owned(&sc->sc_lock)); 3269 } 3270 3271 Static void 3272 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3273 { 3274 ehci_isoc_trans_t trans_status; 3275 struct ehci_xfer *exfer; 3276 ehci_softc_t *sc; 3277 struct ehci_soft_itd *itd; 3278 struct ehci_soft_sitd *sitd; 3279 int i, wake; 3280 3281 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3282 3283 exfer = EHCI_XFER2EXFER(xfer); 3284 sc = EHCI_XFER2SC(xfer); 3285 3286 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3287 (uintptr_t)xfer->ux_pipe, 0, 0); 3288 3289 KASSERT(mutex_owned(&sc->sc_lock)); 3290 3291 if (sc->sc_dying) { 3292 xfer->ux_status = status; 3293 callout_stop(&xfer->ux_callout); 3294 usb_transfer_complete(xfer); 3295 return; 3296 } 3297 3298 if (xfer->ux_hcflags & UXFER_ABORTING) { 3299 DPRINTF("already aborting", 0, 0, 0, 0); 3300 3301 #ifdef DIAGNOSTIC 3302 if (status == USBD_TIMEOUT) 3303 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3304 #endif 3305 3306 xfer->ux_status = status; 3307 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3308 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3309 while (xfer->ux_hcflags & UXFER_ABORTING) 3310 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3311 goto done; 3312 } 3313 xfer->ux_hcflags |= UXFER_ABORTING; 3314 3315 xfer->ux_status = status; 3316 callout_stop(&xfer->ux_callout); 3317 ehci_del_intr_list(sc, exfer); 3318 3319 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3320 for (itd = exfer->ex_itdstart; itd != NULL; 3321 itd = itd->xfer_next) { 3322 usb_syncmem(&itd->dma, 3323 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3324 sizeof(itd->itd.itd_ctl), 3325 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3326 3327 for (i = 0; i < 8; i++) { 3328 trans_status = le32toh(itd->itd.itd_ctl[i]); 3329 trans_status &= ~EHCI_ITD_ACTIVE; 3330 itd->itd.itd_ctl[i] = htole32(trans_status); 3331 } 3332 3333 usb_syncmem(&itd->dma, 3334 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3335 sizeof(itd->itd.itd_ctl), 3336 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3337 } 3338 } else { 3339 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3340 sitd = sitd->xfer_next) { 3341 usb_syncmem(&sitd->dma, 3342 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3343 sizeof(sitd->sitd.sitd_buffer), 3344 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3345 3346 trans_status = le32toh(sitd->sitd.sitd_trans); 3347 trans_status &= ~EHCI_SITD_ACTIVE; 3348 sitd->sitd.sitd_trans = htole32(trans_status); 3349 3350 usb_syncmem(&sitd->dma, 3351 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3352 sizeof(sitd->sitd.sitd_buffer), 3353 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3354 } 3355 } 3356 3357 sc->sc_softwake = 1; 3358 usb_schedsoftintr(&sc->sc_bus); 3359 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3360 3361 #ifdef DIAGNOSTIC 3362 exfer->ex_isdone = true; 3363 #endif 3364 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3365 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3366 usb_transfer_complete(xfer); 3367 if (wake) { 3368 cv_broadcast(&xfer->ux_hccv); 3369 } 3370 3371 done: 3372 KASSERT(mutex_owned(&sc->sc_lock)); 3373 return; 3374 } 3375 3376 Static void 3377 ehci_timeout(void *addr) 3378 { 3379 struct usbd_xfer *xfer = addr; 3380 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3381 struct usbd_pipe *pipe = xfer->ux_pipe; 3382 struct usbd_device *dev = pipe->up_dev; 3383 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3384 3385 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3386 3387 DPRINTF("exfer %#jx", (uintptr_t)exfer, 0, 0, 0); 3388 #ifdef EHCI_DEBUG 3389 if (ehcidebug >= 2) 3390 usbd_dump_pipe(pipe); 3391 #endif 3392 3393 if (sc->sc_dying) { 3394 mutex_enter(&sc->sc_lock); 3395 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3396 mutex_exit(&sc->sc_lock); 3397 return; 3398 } 3399 3400 /* Execute the abort in a process context. */ 3401 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, xfer, 3402 USB_TASKQ_MPSAFE); 3403 usb_add_task(dev, &exfer->ex_aborttask, USB_TASKQ_HC); 3404 } 3405 3406 Static void 3407 ehci_timeout_task(void *addr) 3408 { 3409 struct usbd_xfer *xfer = addr; 3410 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3411 3412 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3413 3414 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3415 3416 mutex_enter(&sc->sc_lock); 3417 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3418 mutex_exit(&sc->sc_lock); 3419 } 3420 3421 /************************/ 3422 3423 Static int 3424 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3425 { 3426 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3427 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3428 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3429 usb_device_request_t *req = &xfer->ux_request; 3430 ehci_soft_qtd_t *setup, *status, *next; 3431 int isread = req->bmRequestType & UT_READ; 3432 int len = xfer->ux_bufsize; 3433 int err; 3434 3435 exfer->ex_type = EX_CTRL; 3436 exfer->ex_status = NULL; 3437 exfer->ex_data = NULL; 3438 exfer->ex_setup = ehci_alloc_sqtd(sc); 3439 if (exfer->ex_setup == NULL) { 3440 err = ENOMEM; 3441 goto bad1; 3442 } 3443 exfer->ex_status = ehci_alloc_sqtd(sc); 3444 if (exfer->ex_status == NULL) { 3445 err = ENOMEM; 3446 goto bad2; 3447 } 3448 setup = exfer->ex_setup; 3449 status = exfer->ex_status; 3450 exfer->ex_nsqtd = 0; 3451 next = status; 3452 /* Set up data transaction */ 3453 if (len != 0) { 3454 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3455 &exfer->ex_data); 3456 if (err) 3457 goto bad3; 3458 next = exfer->ex_data; 3459 } 3460 3461 /* Clear toggle */ 3462 setup->qtd.qtd_status = htole32( 3463 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3464 EHCI_QTD_SET_TOGGLE(0) | 3465 EHCI_QTD_SET_BYTES(sizeof(*req)) 3466 ); 3467 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3468 setup->qtd.qtd_buffer_hi[0] = 0; 3469 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3470 setup->nextqtd = next; 3471 setup->xfer = xfer; 3472 setup->len = sizeof(*req); 3473 3474 status->qtd.qtd_status = htole32( 3475 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3476 EHCI_QTD_SET_TOGGLE(1) | 3477 EHCI_QTD_IOC 3478 ); 3479 status->qtd.qtd_buffer[0] = 0; 3480 status->qtd.qtd_buffer_hi[0] = 0; 3481 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3482 status->nextqtd = NULL; 3483 status->xfer = xfer; 3484 status->len = 0; 3485 3486 return 0; 3487 bad3: 3488 ehci_free_sqtd(sc, exfer->ex_status); 3489 bad2: 3490 ehci_free_sqtd(sc, exfer->ex_setup); 3491 bad1: 3492 return err; 3493 } 3494 3495 Static void 3496 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3497 { 3498 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3499 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3500 3501 KASSERT(ex->ex_type == EX_CTRL); 3502 3503 ehci_free_sqtd(sc, ex->ex_setup); 3504 ehci_free_sqtd(sc, ex->ex_status); 3505 ehci_free_sqtds(sc, ex); 3506 if (ex->ex_nsqtd) 3507 kmem_free(ex->ex_sqtds, 3508 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3509 } 3510 3511 Static usbd_status 3512 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3513 { 3514 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3515 usbd_status err; 3516 3517 /* Insert last in queue. */ 3518 mutex_enter(&sc->sc_lock); 3519 err = usb_insert_transfer(xfer); 3520 mutex_exit(&sc->sc_lock); 3521 if (err) 3522 return err; 3523 3524 /* Pipe isn't running, start first */ 3525 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3526 } 3527 3528 Static usbd_status 3529 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3530 { 3531 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3532 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3533 usb_device_request_t *req = &xfer->ux_request; 3534 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3535 ehci_soft_qtd_t *setup, *status, *next; 3536 ehci_soft_qh_t *sqh; 3537 3538 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3539 3540 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3541 3542 if (sc->sc_dying) 3543 return USBD_IOERROR; 3544 3545 const int isread = req->bmRequestType & UT_READ; 3546 const int len = UGETW(req->wLength); 3547 3548 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3549 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3550 UGETW(req->wIndex)); 3551 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3552 len, epipe->pipe.up_dev->ud_addr, 3553 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3554 3555 sqh = epipe->sqh; 3556 3557 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3558 "address QH %" __PRIuBIT " pipe %d\n", 3559 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3560 epipe->pipe.up_dev->ud_addr); 3561 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3562 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3563 "MPS QH %" __PRIuBIT " pipe %d\n", 3564 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3565 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3566 3567 setup = exfer->ex_setup; 3568 status = exfer->ex_status; 3569 3570 DPRINTF("setup %#jx status %#jx data %#jx", 3571 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3572 KASSERTMSG(setup != NULL && status != NULL, 3573 "Failed memory allocation, setup %p status %p", 3574 setup, status); 3575 3576 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3577 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3578 3579 /* Clear toggle */ 3580 setup->qtd.qtd_status &= ~htole32( 3581 EHCI_QTD_STATUS_MASK | 3582 EHCI_QTD_BYTES_MASK | 3583 EHCI_QTD_TOGGLE_MASK | 3584 EHCI_QTD_CERR_MASK 3585 ); 3586 setup->qtd.qtd_status |= htole32( 3587 EHCI_QTD_ACTIVE | 3588 EHCI_QTD_SET_CERR(3) | 3589 EHCI_QTD_SET_TOGGLE(0) | 3590 EHCI_QTD_SET_BYTES(sizeof(*req)) 3591 ); 3592 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3593 setup->qtd.qtd_buffer_hi[0] = 0; 3594 3595 next = status; 3596 status->qtd.qtd_status &= ~htole32( 3597 EHCI_QTD_STATUS_MASK | 3598 EHCI_QTD_PID_MASK | 3599 EHCI_QTD_BYTES_MASK | 3600 EHCI_QTD_TOGGLE_MASK | 3601 EHCI_QTD_CERR_MASK 3602 ); 3603 status->qtd.qtd_status |= htole32( 3604 EHCI_QTD_ACTIVE | 3605 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3606 EHCI_QTD_SET_CERR(3) | 3607 EHCI_QTD_SET_TOGGLE(1) | 3608 EHCI_QTD_SET_BYTES(0) | 3609 EHCI_QTD_IOC 3610 ); 3611 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3612 3613 KASSERT(exfer->ex_isdone); 3614 #ifdef DIAGNOSTIC 3615 exfer->ex_isdone = false; 3616 #endif 3617 3618 /* Set up data transaction */ 3619 if (len != 0) { 3620 ehci_soft_qtd_t *end; 3621 3622 /* Start toggle at 1. */ 3623 int toggle = 1; 3624 next = exfer->ex_data; 3625 KASSERTMSG(next != NULL, "Failed memory allocation"); 3626 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3627 end->nextqtd = status; 3628 end->qtd.qtd_next = end->qtd.qtd_altnext = 3629 htole32(status->physaddr); 3630 3631 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3632 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3633 3634 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3635 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3636 } 3637 3638 setup->nextqtd = next; 3639 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3640 3641 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3642 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3643 3644 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3645 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3646 3647 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3648 3649 #ifdef EHCI_DEBUG 3650 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3651 ehci_dump_sqh(sqh); 3652 ehci_dump_sqtds(setup); 3653 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3654 #endif 3655 3656 mutex_enter(&sc->sc_lock); 3657 3658 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3659 ehci_set_qh_qtd(sqh, setup); 3660 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3661 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3662 ehci_timeout, xfer); 3663 } 3664 ehci_add_intr_list(sc, exfer); 3665 xfer->ux_status = USBD_IN_PROGRESS; 3666 mutex_exit(&sc->sc_lock); 3667 3668 #if 0 3669 #ifdef EHCI_DEBUG 3670 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3671 // delay(10000); 3672 ehci_dump_regs(sc); 3673 ehci_dump_sqh(sc->sc_async_head); 3674 ehci_dump_sqh(sqh); 3675 ehci_dump_sqtds(setup); 3676 #endif 3677 #endif 3678 3679 return USBD_IN_PROGRESS; 3680 } 3681 3682 Static void 3683 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3684 { 3685 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3686 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3687 usb_device_request_t *req = &xfer->ux_request; 3688 int len = UGETW(req->wLength); 3689 int rd = req->bmRequestType & UT_READ; 3690 3691 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3692 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3693 3694 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3695 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3696 3697 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3698 BUS_DMASYNC_POSTWRITE); 3699 if (len) 3700 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3701 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3702 3703 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3704 } 3705 3706 /* Abort a device control request. */ 3707 Static void 3708 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3709 { 3710 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3711 3712 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3713 ehci_abort_xfer(xfer, USBD_CANCELLED); 3714 } 3715 3716 /* Close a device control pipe. */ 3717 Static void 3718 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3719 { 3720 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3721 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3722 3723 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3724 3725 KASSERT(mutex_owned(&sc->sc_lock)); 3726 3727 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3728 3729 ehci_close_pipe(pipe, sc->sc_async_head); 3730 } 3731 3732 /* 3733 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3734 * qTD status, or miss signalling occasionally under heavy load. If the host 3735 * machine is too fast, we we can miss transaction completion - when we scan 3736 * the active list the transaction still seems to be active. This generally 3737 * exhibits itself as a umass stall that never recovers. 3738 * 3739 * We work around this behaviour by setting up this callback after any softintr 3740 * that completes with transactions still pending, giving us another chance to 3741 * check for completion after the writeback has taken place. 3742 */ 3743 Static void 3744 ehci_intrlist_timeout(void *arg) 3745 { 3746 ehci_softc_t *sc = arg; 3747 3748 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3749 3750 usb_schedsoftintr(&sc->sc_bus); 3751 } 3752 3753 /************************/ 3754 3755 Static int 3756 ehci_device_bulk_init(struct usbd_xfer *xfer) 3757 { 3758 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3759 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3760 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3761 int endpt = ed->bEndpointAddress; 3762 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3763 int len = xfer->ux_bufsize; 3764 int err = 0; 3765 3766 exfer->ex_type = EX_BULK; 3767 exfer->ex_nsqtd = 0; 3768 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3769 &exfer->ex_sqtdstart); 3770 3771 return err; 3772 } 3773 3774 Static void 3775 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3776 { 3777 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3778 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3779 3780 KASSERT(ex->ex_type == EX_BULK); 3781 3782 ehci_free_sqtds(sc, ex); 3783 if (ex->ex_nsqtd) 3784 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3785 } 3786 3787 Static usbd_status 3788 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3789 { 3790 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3791 usbd_status err; 3792 3793 /* Insert last in queue. */ 3794 mutex_enter(&sc->sc_lock); 3795 err = usb_insert_transfer(xfer); 3796 mutex_exit(&sc->sc_lock); 3797 if (err) 3798 return err; 3799 3800 /* Pipe isn't running, start first */ 3801 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3802 } 3803 3804 Static usbd_status 3805 ehci_device_bulk_start(struct usbd_xfer *xfer) 3806 { 3807 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3808 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3809 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3810 ehci_soft_qh_t *sqh; 3811 ehci_soft_qtd_t *end; 3812 int len, isread, endpt; 3813 3814 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3815 3816 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3817 xfer->ux_flags, 0); 3818 3819 if (sc->sc_dying) 3820 return USBD_IOERROR; 3821 3822 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3823 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3824 3825 len = xfer->ux_length; 3826 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3827 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3828 sqh = epipe->sqh; 3829 3830 KASSERT(exfer->ex_isdone); 3831 #ifdef DIAGNOSTIC 3832 exfer->ex_isdone = false; 3833 #endif 3834 3835 /* Take lock here to protect nexttoggle */ 3836 mutex_enter(&sc->sc_lock); 3837 3838 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3839 3840 exfer->ex_sqtdend = end; 3841 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3842 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3843 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3844 3845 #ifdef EHCI_DEBUG 3846 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3847 ehci_dump_sqh(sqh); 3848 ehci_dump_sqtds(exfer->ex_sqtdstart); 3849 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3850 #endif 3851 3852 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3853 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3854 3855 /* also does usb_syncmem(sqh) */ 3856 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3857 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3858 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3859 ehci_timeout, xfer); 3860 } 3861 ehci_add_intr_list(sc, exfer); 3862 xfer->ux_status = USBD_IN_PROGRESS; 3863 mutex_exit(&sc->sc_lock); 3864 3865 #if 0 3866 #ifdef EHCI_DEBUG 3867 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3868 // delay(10000); 3869 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3870 ehci_dump_regs(sc); 3871 #if 0 3872 printf("async_head:\n"); 3873 ehci_dump_sqh(sc->sc_async_head); 3874 #endif 3875 DPRINTF("sqh:", 0, 0, 0, 0); 3876 ehci_dump_sqh(sqh); 3877 ehci_dump_sqtds(exfer->ex_sqtdstart); 3878 #endif 3879 #endif 3880 3881 return USBD_IN_PROGRESS; 3882 } 3883 3884 Static void 3885 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3886 { 3887 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3888 3889 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3890 ehci_abort_xfer(xfer, USBD_CANCELLED); 3891 } 3892 3893 /* 3894 * Close a device bulk pipe. 3895 */ 3896 Static void 3897 ehci_device_bulk_close(struct usbd_pipe *pipe) 3898 { 3899 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3900 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3901 3902 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3903 3904 KASSERT(mutex_owned(&sc->sc_lock)); 3905 3906 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3907 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3908 ehci_close_pipe(pipe, sc->sc_async_head); 3909 } 3910 3911 Static void 3912 ehci_device_bulk_done(struct usbd_xfer *xfer) 3913 { 3914 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3915 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3916 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3917 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3918 3919 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3920 3921 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 3922 3923 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3924 3925 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3926 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3927 3928 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3929 } 3930 3931 /************************/ 3932 3933 Static usbd_status 3934 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3935 { 3936 struct ehci_soft_islot *isp; 3937 int islot, lev; 3938 3939 /* Find a poll rate that is large enough. */ 3940 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3941 if (EHCI_ILEV_IVAL(lev) <= ival) 3942 break; 3943 3944 /* Pick an interrupt slot at the right level. */ 3945 /* XXX could do better than picking at random */ 3946 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3947 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3948 3949 sqh->islot = islot; 3950 isp = &sc->sc_islots[islot]; 3951 mutex_enter(&sc->sc_lock); 3952 ehci_add_qh(sc, sqh, isp->sqh); 3953 mutex_exit(&sc->sc_lock); 3954 3955 return USBD_NORMAL_COMPLETION; 3956 } 3957 3958 3959 Static int 3960 ehci_device_intr_init(struct usbd_xfer *xfer) 3961 { 3962 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3963 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3964 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3965 int endpt = ed->bEndpointAddress; 3966 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3967 int len = xfer->ux_bufsize; 3968 int err; 3969 3970 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3971 3972 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3973 xfer->ux_flags, 0); 3974 3975 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3976 KASSERT(len != 0); 3977 3978 exfer->ex_type = EX_INTR; 3979 exfer->ex_nsqtd = 0; 3980 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3981 &exfer->ex_sqtdstart); 3982 3983 return err; 3984 } 3985 3986 Static void 3987 ehci_device_intr_fini(struct usbd_xfer *xfer) 3988 { 3989 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3990 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3991 3992 KASSERT(ex->ex_type == EX_INTR); 3993 3994 ehci_free_sqtds(sc, ex); 3995 if (ex->ex_nsqtd) 3996 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3997 } 3998 3999 Static usbd_status 4000 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4001 { 4002 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4003 usbd_status err; 4004 4005 /* Insert last in queue. */ 4006 mutex_enter(&sc->sc_lock); 4007 err = usb_insert_transfer(xfer); 4008 mutex_exit(&sc->sc_lock); 4009 if (err) 4010 return err; 4011 4012 /* 4013 * Pipe isn't running (otherwise err would be USBD_INPROG), 4014 * so start it first. 4015 */ 4016 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4017 } 4018 4019 Static usbd_status 4020 ehci_device_intr_start(struct usbd_xfer *xfer) 4021 { 4022 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4023 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4024 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4025 ehci_soft_qtd_t *end; 4026 ehci_soft_qh_t *sqh; 4027 int len, isread, endpt; 4028 4029 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4030 4031 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4032 xfer->ux_flags, 0); 4033 4034 if (sc->sc_dying) 4035 return USBD_IOERROR; 4036 4037 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4038 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4039 4040 len = xfer->ux_length; 4041 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4042 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4043 sqh = epipe->sqh; 4044 4045 KASSERT(exfer->ex_isdone); 4046 #ifdef DIAGNOSTIC 4047 exfer->ex_isdone = false; 4048 #endif 4049 4050 /* Take lock to protect nexttoggle */ 4051 mutex_enter(&sc->sc_lock); 4052 4053 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4054 4055 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4056 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4057 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4058 exfer->ex_sqtdend = end; 4059 4060 #ifdef EHCI_DEBUG 4061 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4062 ehci_dump_sqh(sqh); 4063 ehci_dump_sqtds(exfer->ex_sqtdstart); 4064 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4065 #endif 4066 4067 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4068 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4069 4070 /* also does usb_syncmem(sqh) */ 4071 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4072 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4073 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4074 ehci_timeout, xfer); 4075 } 4076 ehci_add_intr_list(sc, exfer); 4077 xfer->ux_status = USBD_IN_PROGRESS; 4078 mutex_exit(&sc->sc_lock); 4079 4080 #if 0 4081 #ifdef EHCI_DEBUG 4082 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4083 // delay(10000); 4084 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4085 ehci_dump_regs(sc); 4086 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4087 ehci_dump_sqh(sqh); 4088 ehci_dump_sqtds(exfer->ex_sqtdstart); 4089 #endif 4090 #endif 4091 4092 return USBD_IN_PROGRESS; 4093 } 4094 4095 Static void 4096 ehci_device_intr_abort(struct usbd_xfer *xfer) 4097 { 4098 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4099 4100 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4101 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4102 4103 /* 4104 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4105 * async doorbell. That's dependent on the async list, wheras 4106 * intr xfers are periodic, should not use this? 4107 */ 4108 ehci_abort_xfer(xfer, USBD_CANCELLED); 4109 } 4110 4111 Static void 4112 ehci_device_intr_close(struct usbd_pipe *pipe) 4113 { 4114 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4115 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4116 struct ehci_soft_islot *isp; 4117 4118 KASSERT(mutex_owned(&sc->sc_lock)); 4119 4120 isp = &sc->sc_islots[epipe->sqh->islot]; 4121 ehci_close_pipe(pipe, isp->sqh); 4122 } 4123 4124 Static void 4125 ehci_device_intr_done(struct usbd_xfer *xfer) 4126 { 4127 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4128 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4129 int isread, endpt; 4130 4131 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4132 4133 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4134 4135 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4136 4137 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4138 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4139 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4140 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4141 } 4142 4143 /************************/ 4144 Static int 4145 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4146 { 4147 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4148 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4149 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4150 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4151 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4152 int i, k, frames; 4153 u_int huba, dir; 4154 int err; 4155 4156 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4157 4158 start = NULL; 4159 sitd = NULL; 4160 4161 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4162 xfer->ux_flags, 0); 4163 4164 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4165 KASSERT(xfer->ux_nframes != 0); 4166 KASSERT(exfer->ex_isdone); 4167 4168 exfer->ex_type = EX_FS_ISOC; 4169 /* 4170 * Step 1: Allocate and initialize sitds. 4171 */ 4172 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4173 if (i > 16 || i == 0) { 4174 /* Spec page 271 says intervals > 16 are invalid */ 4175 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4176 4177 return EINVAL; 4178 } 4179 4180 frames = xfer->ux_nframes; 4181 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4182 sitd = ehci_alloc_sitd(sc); 4183 if (sitd == NULL) { 4184 err = ENOMEM; 4185 goto fail; 4186 } 4187 4188 if (prev) 4189 prev->xfer_next = sitd; 4190 else 4191 start = sitd; 4192 4193 huba = dev->ud_myhsport->up_parent->ud_addr; 4194 4195 #if 0 4196 if (sc->sc_flags & EHCIF_FREESCALE) { 4197 // Set hub address to 0 if embedded TT is used. 4198 if (huba == sc->sc_addr) 4199 huba = 0; 4200 } 4201 #endif 4202 4203 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4204 dir = UE_GET_DIR(k) ? 1 : 0; 4205 sitd->sitd.sitd_endp = 4206 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4207 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4208 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4209 EHCI_SITD_SET_HUBA(huba) | 4210 EHCI_SITD_SET_DIR(dir)); 4211 4212 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4213 } /* End of frame */ 4214 4215 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4216 4217 stop = sitd; 4218 stop->xfer_next = NULL; 4219 exfer->ex_sitdstart = start; 4220 exfer->ex_sitdend = stop; 4221 4222 return 0; 4223 4224 fail: 4225 mutex_enter(&sc->sc_lock); 4226 ehci_soft_sitd_t *next; 4227 for (sitd = start; sitd; sitd = next) { 4228 next = sitd->xfer_next; 4229 ehci_free_sitd_locked(sc, sitd); 4230 } 4231 mutex_exit(&sc->sc_lock); 4232 4233 return err; 4234 } 4235 4236 Static void 4237 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4238 { 4239 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4240 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4241 4242 KASSERT(ex->ex_type == EX_FS_ISOC); 4243 4244 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4245 } 4246 4247 Static usbd_status 4248 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4249 { 4250 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4251 usbd_status __diagused err; 4252 4253 mutex_enter(&sc->sc_lock); 4254 err = usb_insert_transfer(xfer); 4255 mutex_exit(&sc->sc_lock); 4256 4257 KASSERT(err == USBD_NORMAL_COMPLETION); 4258 4259 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4260 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4261 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4262 ehci_soft_sitd_t *sitd; 4263 usb_dma_t *dma_buf; 4264 int i, j, k, frames; 4265 int offs, total_length; 4266 int frindex; 4267 u_int dir; 4268 4269 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4270 4271 sitd = NULL; 4272 total_length = 0; 4273 4274 4275 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4276 xfer->ux_flags, 0); 4277 4278 if (sc->sc_dying) 4279 return USBD_IOERROR; 4280 4281 /* 4282 * To avoid complication, don't allow a request right now that'll span 4283 * the entire frame table. To within 4 frames, to allow some leeway 4284 * on either side of where the hc currently is. 4285 */ 4286 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4287 xfer->ux_nframes >= sc->sc_flsize - 4) { 4288 printf("ehci: isoc descriptor requested that spans the entire" 4289 "frametable, too many frames\n"); 4290 return USBD_INVAL; 4291 } 4292 4293 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4294 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4295 KASSERT(exfer->ex_isdone); 4296 #ifdef DIAGNOSTIC 4297 exfer->ex_isdone = false; 4298 #endif 4299 4300 /* 4301 * Step 1: Initialize sitds. 4302 */ 4303 4304 frames = xfer->ux_nframes; 4305 dma_buf = &xfer->ux_dmabuf; 4306 offs = 0; 4307 4308 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4309 i++, sitd = sitd->xfer_next) { 4310 KASSERT(sitd != NULL); 4311 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4312 4313 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4314 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4315 4316 /* Set page0 index and offset - TP and T-offset are set below */ 4317 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4318 4319 total_length += xfer->ux_frlengths[i]; 4320 offs += xfer->ux_frlengths[i]; 4321 4322 sitd->sitd.sitd_buffer[1] = 4323 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4324 4325 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4326 4327 #if 0 4328 if (sc->sc_flags & EHCIF_FREESCALE) { 4329 // Set hub address to 0 if embedded TT is used. 4330 if (huba == sc->sc_addr) 4331 huba = 0; 4332 } 4333 #endif 4334 4335 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4336 dir = UE_GET_DIR(k) ? 1 : 0; 4337 KASSERT(sitd->sitd.sitd_endp == htole32( 4338 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4339 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4340 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4341 EHCI_SITD_SET_HUBA(huba) | 4342 EHCI_SITD_SET_DIR(dir))); 4343 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4344 4345 uint8_t sa = 0; 4346 uint8_t sb = 0; 4347 u_int temp, tlen; 4348 4349 if (dir == 0) { /* OUT */ 4350 temp = 0; 4351 tlen = xfer->ux_frlengths[i]; 4352 if (tlen <= 188) { 4353 temp |= 1; /* T-count = 1, TP = ALL */ 4354 tlen = 1; 4355 } else { 4356 tlen += 187; 4357 tlen /= 188; 4358 temp |= tlen; /* T-count = [1..6] */ 4359 temp |= 8; /* TP = Begin */ 4360 } 4361 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4362 4363 tlen += sa; 4364 4365 if (tlen >= 8) { 4366 sb = 0; 4367 } else { 4368 sb = (1 << tlen); 4369 } 4370 4371 sa = (1 << sa); 4372 sa = (sb - sa) & 0x3F; 4373 sb = 0; 4374 } else { 4375 sb = (-(4 << sa)) & 0xFE; 4376 sa = (1 << sa) & 0x3F; 4377 sa = 0x01; 4378 sb = 0xfc; 4379 } 4380 4381 sitd->sitd.sitd_sched = htole32( 4382 EHCI_SITD_SET_SMASK(sa) | 4383 EHCI_SITD_SET_CMASK(sb) 4384 ); 4385 4386 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4387 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4388 } /* End of frame */ 4389 4390 sitd = exfer->ex_sitdend; 4391 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4392 4393 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4394 sizeof(sitd->sitd.sitd_trans), 4395 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4396 4397 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4398 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4399 4400 /* 4401 * Part 2: Transfer descriptors have now been set up, now they must 4402 * be scheduled into the periodic frame list. Erk. Not wanting to 4403 * complicate matters, transfer is denied if the transfer spans 4404 * more than the period frame list. 4405 */ 4406 4407 mutex_enter(&sc->sc_lock); 4408 4409 /* Start inserting frames */ 4410 if (epipe->isoc.cur_xfers > 0) { 4411 frindex = epipe->isoc.next_frame; 4412 } else { 4413 frindex = EOREAD4(sc, EHCI_FRINDEX); 4414 frindex = frindex >> 3; /* Erase microframe index */ 4415 frindex += 2; 4416 } 4417 4418 if (frindex >= sc->sc_flsize) 4419 frindex &= (sc->sc_flsize - 1); 4420 4421 /* Whats the frame interval? */ 4422 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4423 4424 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4425 j++, sitd = sitd->xfer_next) { 4426 KASSERT(sitd); 4427 4428 usb_syncmem(&sc->sc_fldma, 4429 sizeof(ehci_link_t) * frindex, 4430 sizeof(ehci_link_t), 4431 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4432 4433 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4434 if (sitd->sitd.sitd_next == 0) 4435 /* 4436 * FIXME: frindex table gets initialized to NULL 4437 * or EHCI_NULL? 4438 */ 4439 sitd->sitd.sitd_next = EHCI_NULL; 4440 4441 usb_syncmem(&sitd->dma, 4442 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4443 sizeof(ehci_sitd_t), 4444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4445 4446 sc->sc_flist[frindex] = 4447 htole32(EHCI_LINK_SITD | sitd->physaddr); 4448 4449 usb_syncmem(&sc->sc_fldma, 4450 sizeof(ehci_link_t) * frindex, 4451 sizeof(ehci_link_t), 4452 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4453 4454 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4455 sc->sc_softsitds[frindex] = sitd; 4456 if (sitd->frame_list.next != NULL) 4457 sitd->frame_list.next->frame_list.prev = sitd; 4458 sitd->slot = frindex; 4459 sitd->frame_list.prev = NULL; 4460 4461 frindex += i; 4462 if (frindex >= sc->sc_flsize) 4463 frindex -= sc->sc_flsize; 4464 } 4465 4466 epipe->isoc.cur_xfers++; 4467 epipe->isoc.next_frame = frindex; 4468 4469 ehci_add_intr_list(sc, exfer); 4470 xfer->ux_status = USBD_IN_PROGRESS; 4471 4472 mutex_exit(&sc->sc_lock); 4473 4474 return USBD_IN_PROGRESS; 4475 } 4476 4477 Static void 4478 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4479 { 4480 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4481 4482 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4483 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4484 } 4485 4486 Static void 4487 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4488 { 4489 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4490 4491 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4492 } 4493 4494 Static void 4495 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4496 { 4497 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4498 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4499 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4500 4501 KASSERT(mutex_owned(&sc->sc_lock)); 4502 4503 epipe->isoc.cur_xfers--; 4504 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4505 4506 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4507 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4508 } 4509 4510 4511 /************************/ 4512 4513 4514 Static int 4515 ehci_device_isoc_init(struct usbd_xfer *xfer) 4516 { 4517 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4518 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4519 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4520 ehci_soft_itd_t *itd, *prev, *start, *stop; 4521 int i, j, k; 4522 int frames, ufrperframe; 4523 int err; 4524 4525 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4526 4527 start = NULL; 4528 prev = NULL; 4529 itd = NULL; 4530 4531 KASSERT(xfer->ux_nframes != 0); 4532 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4533 KASSERT(exfer->ex_isdone); 4534 4535 exfer->ex_type = EX_ISOC; 4536 4537 /* 4538 * Step 1: Allocate and initialize itds, how many do we need? 4539 * One per transfer if interval >= 8 microframes, less if we use 4540 * multiple microframes per frame. 4541 */ 4542 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4543 if (i > 16 || i == 0) { 4544 /* Spec page 271 says intervals > 16 are invalid */ 4545 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4546 return USBD_INVAL; 4547 } 4548 4549 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4550 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4551 4552 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4553 itd = ehci_alloc_itd(sc); 4554 if (itd == NULL) { 4555 err = ENOMEM; 4556 goto fail; 4557 } 4558 4559 if (prev != NULL) { 4560 /* Maybe not as it's updated by the scheduling? */ 4561 prev->itd.itd_next = 4562 htole32(itd->physaddr | EHCI_LINK_ITD); 4563 4564 prev->xfer_next = itd; 4565 } else { 4566 start = itd; 4567 } 4568 4569 /* 4570 * Other special values 4571 */ 4572 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4573 itd->itd.itd_bufr[0] = htole32( 4574 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4575 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4576 4577 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4578 ? 1 : 0; 4579 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4580 itd->itd.itd_bufr[1] |= htole32( 4581 EHCI_ITD_SET_DIR(k) | 4582 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4583 4584 /* FIXME: handle invalid trans - should be done in openpipe */ 4585 itd->itd.itd_bufr[2] |= 4586 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4587 } /* End of frame */ 4588 4589 stop = itd; 4590 stop->xfer_next = NULL; 4591 4592 exfer->ex_itdstart = start; 4593 exfer->ex_itdend = stop; 4594 4595 return 0; 4596 fail: 4597 mutex_enter(&sc->sc_lock); 4598 ehci_soft_itd_t *next; 4599 for (itd = start; itd; itd = next) { 4600 next = itd->xfer_next; 4601 ehci_free_itd_locked(sc, itd); 4602 } 4603 mutex_exit(&sc->sc_lock); 4604 4605 return err; 4606 4607 } 4608 4609 Static void 4610 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4611 { 4612 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4613 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4614 4615 KASSERT(ex->ex_type == EX_ISOC); 4616 4617 ehci_free_itd_chain(sc, ex->ex_itdstart); 4618 } 4619 4620 Static usbd_status 4621 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4622 { 4623 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4624 usbd_status __diagused err; 4625 4626 mutex_enter(&sc->sc_lock); 4627 err = usb_insert_transfer(xfer); 4628 mutex_exit(&sc->sc_lock); 4629 4630 KASSERT(err == USBD_NORMAL_COMPLETION); 4631 4632 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4633 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4634 ehci_soft_itd_t *itd, *prev; 4635 usb_dma_t *dma_buf; 4636 int i, j; 4637 int frames, uframes, ufrperframe; 4638 int trans_count, offs, total_length; 4639 int frindex; 4640 4641 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4642 4643 prev = NULL; 4644 itd = NULL; 4645 trans_count = 0; 4646 total_length = 0; 4647 4648 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4649 4650 if (sc->sc_dying) 4651 return USBD_IOERROR; 4652 4653 /* 4654 * To avoid complication, don't allow a request right now that'll span 4655 * the entire frame table. To within 4 frames, to allow some leeway 4656 * on either side of where the hc currently is. 4657 */ 4658 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4659 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4660 DPRINTF( 4661 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4662 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4663 return USBD_INVAL; 4664 } 4665 4666 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4667 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4668 KASSERT(exfer->ex_isdone); 4669 #ifdef DIAGNOSTIC 4670 exfer->ex_isdone = false; 4671 #endif 4672 4673 /* 4674 * Step 1: Re-Initialize itds 4675 */ 4676 4677 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4678 if (i > 16 || i == 0) { 4679 /* Spec page 271 says intervals > 16 are invalid */ 4680 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4681 return USBD_INVAL; 4682 } 4683 4684 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4685 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4686 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4687 4688 if (frames == 0) { 4689 DPRINTF("frames == 0", 0, 0, 0, 0); 4690 return USBD_INVAL; 4691 } 4692 4693 dma_buf = &xfer->ux_dmabuf; 4694 offs = 0; 4695 4696 itd = exfer->ex_itdstart; 4697 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4698 int froffs = offs; 4699 4700 if (prev != NULL) { 4701 prev->itd.itd_next = 4702 htole32(itd->physaddr | EHCI_LINK_ITD); 4703 usb_syncmem(&prev->dma, 4704 prev->offs + offsetof(ehci_itd_t, itd_next), 4705 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4706 prev->xfer_next = itd; 4707 } 4708 4709 /* 4710 * Step 1.5, initialize uframes 4711 */ 4712 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4713 /* Calculate which page in the list this starts in */ 4714 int addr = DMAADDR(dma_buf, froffs); 4715 addr = EHCI_PAGE_OFFSET(addr); 4716 addr += (offs - froffs); 4717 addr = EHCI_PAGE(addr); 4718 addr /= EHCI_PAGE_SIZE; 4719 4720 /* 4721 * This gets the initial offset into the first page, 4722 * looks how far further along the current uframe 4723 * offset is. Works out how many pages that is. 4724 */ 4725 4726 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4727 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4728 EHCI_ITD_SET_PG(addr) | 4729 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4730 4731 total_length += xfer->ux_frlengths[trans_count]; 4732 offs += xfer->ux_frlengths[trans_count]; 4733 trans_count++; 4734 4735 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4736 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4737 break; 4738 } 4739 } 4740 4741 /* 4742 * Step 1.75, set buffer pointers. To simplify matters, all 4743 * pointers are filled out for the next 7 hardware pages in 4744 * the dma block, so no need to worry what pages to cover 4745 * and what to not. 4746 */ 4747 4748 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4749 /* 4750 * Don't try to lookup a page that's past the end 4751 * of buffer 4752 */ 4753 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4754 if (page_offs >= dma_buf->udma_block->size) 4755 break; 4756 4757 uint64_t page = DMAADDR(dma_buf, page_offs); 4758 page = EHCI_PAGE(page); 4759 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4760 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4761 } 4762 /* 4763 * Other special values 4764 */ 4765 4766 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4767 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4768 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4769 4770 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4771 ? 1 : 0; 4772 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4773 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4774 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4775 4776 /* FIXME: handle invalid trans */ 4777 itd->itd.itd_bufr[2] |= 4778 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4779 4780 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4781 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4782 4783 prev = itd; 4784 } /* End of frame */ 4785 4786 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4787 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4788 4789 /* 4790 * Part 2: Transfer descriptors have now been set up, now they must 4791 * be scheduled into the period frame list. Erk. Not wanting to 4792 * complicate matters, transfer is denied if the transfer spans 4793 * more than the period frame list. 4794 */ 4795 4796 mutex_enter(&sc->sc_lock); 4797 4798 /* Start inserting frames */ 4799 if (epipe->isoc.cur_xfers > 0) { 4800 frindex = epipe->isoc.next_frame; 4801 } else { 4802 frindex = EOREAD4(sc, EHCI_FRINDEX); 4803 frindex = frindex >> 3; /* Erase microframe index */ 4804 frindex += 2; 4805 } 4806 4807 if (frindex >= sc->sc_flsize) 4808 frindex &= (sc->sc_flsize - 1); 4809 4810 /* What's the frame interval? */ 4811 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4812 if (i / USB_UFRAMES_PER_FRAME == 0) 4813 i = 1; 4814 else 4815 i /= USB_UFRAMES_PER_FRAME; 4816 4817 itd = exfer->ex_itdstart; 4818 for (j = 0; j < frames; j++) { 4819 KASSERTMSG(itd != NULL, "frame %d\n", j); 4820 4821 usb_syncmem(&sc->sc_fldma, 4822 sizeof(ehci_link_t) * frindex, 4823 sizeof(ehci_link_t), 4824 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4825 4826 itd->itd.itd_next = sc->sc_flist[frindex]; 4827 if (itd->itd.itd_next == 0) 4828 /* 4829 * FIXME: frindex table gets initialized to NULL 4830 * or EHCI_NULL? 4831 */ 4832 itd->itd.itd_next = EHCI_NULL; 4833 4834 usb_syncmem(&itd->dma, 4835 itd->offs + offsetof(ehci_itd_t, itd_next), 4836 sizeof(itd->itd.itd_next), 4837 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4838 4839 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4840 4841 usb_syncmem(&sc->sc_fldma, 4842 sizeof(ehci_link_t) * frindex, 4843 sizeof(ehci_link_t), 4844 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4845 4846 itd->frame_list.next = sc->sc_softitds[frindex]; 4847 sc->sc_softitds[frindex] = itd; 4848 if (itd->frame_list.next != NULL) 4849 itd->frame_list.next->frame_list.prev = itd; 4850 itd->slot = frindex; 4851 itd->frame_list.prev = NULL; 4852 4853 frindex += i; 4854 if (frindex >= sc->sc_flsize) 4855 frindex -= sc->sc_flsize; 4856 4857 itd = itd->xfer_next; 4858 } 4859 4860 epipe->isoc.cur_xfers++; 4861 epipe->isoc.next_frame = frindex; 4862 4863 ehci_add_intr_list(sc, exfer); 4864 xfer->ux_status = USBD_IN_PROGRESS; 4865 4866 mutex_exit(&sc->sc_lock); 4867 4868 return USBD_IN_PROGRESS; 4869 } 4870 4871 Static void 4872 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4873 { 4874 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4875 4876 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4877 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4878 } 4879 4880 Static void 4881 ehci_device_isoc_close(struct usbd_pipe *pipe) 4882 { 4883 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4884 4885 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4886 } 4887 4888 Static void 4889 ehci_device_isoc_done(struct usbd_xfer *xfer) 4890 { 4891 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4892 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4893 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4894 4895 KASSERT(mutex_owned(&sc->sc_lock)); 4896 4897 epipe->isoc.cur_xfers--; 4898 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4899 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4900 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4901 } 4902
Indexes created Wed Oct 01 19:09:53 GMT 2025