ehci.c revision 1.257.2.3
1 /* $NetBSD: ehci.c,v 1.257.2.3 2018/09/06 06:56:04 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.257.2.3 2018/09/06 06:56:04 pgoyette Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static void ehci_intrlist_timeout(void *); 172 Static void ehci_doorbell(void *); 173 Static void ehci_pcd(void *); 174 175 Static struct usbd_xfer * 176 ehci_allocx(struct usbd_bus *, unsigned int); 177 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 178 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_doorbell, "ehcidb"); 416 417 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 418 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 419 420 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 421 ehci_doorbell, sc); 422 KASSERT(sc->sc_doorbell_si != NULL); 423 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 424 ehci_pcd, sc); 425 KASSERT(sc->sc_pcd_si != NULL); 426 427 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 428 429 vers = EREAD2(sc, EHCI_HCIVERSION); 430 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 431 vers >> 8, vers & 0xff); 432 433 sparams = EREAD4(sc, EHCI_HCSPARAMS); 434 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 435 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 436 ncomp = EHCI_HCS_N_CC(sparams); 437 if (ncomp != sc->sc_ncomp) { 438 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 439 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 440 #if NOHCI == 0 || NUHCI == 0 441 aprint_error("%s: ohci or uhci probably not configured\n", 442 device_xname(sc->sc_dev)); 443 #endif 444 if (ncomp < sc->sc_ncomp) 445 sc->sc_ncomp = ncomp; 446 } 447 if (sc->sc_ncomp > 0) { 448 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 449 aprint_normal("%s: %d companion controller%s, %d port%s%s", 450 device_xname(sc->sc_dev), sc->sc_ncomp, 451 sc->sc_ncomp!=1 ? "s" : "", 452 EHCI_HCS_N_PCC(sparams), 453 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 454 sc->sc_ncomp!=1 ? " each" : ""); 455 if (sc->sc_comps[0]) { 456 aprint_normal(":"); 457 for (i = 0; i < sc->sc_ncomp; i++) 458 aprint_normal(" %s", 459 device_xname(sc->sc_comps[i])); 460 } 461 aprint_normal("\n"); 462 } 463 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 464 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 465 466 cparams = EREAD4(sc, EHCI_HCCPARAMS); 467 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 468 469 if (EHCI_HCC_64BIT(cparams)) { 470 /* MUST clear segment register if 64 bit capable. */ 471 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 472 } 473 474 if (cparams & EHCI_HCC_IST_FULLFRAME) { 475 sc->sc_istthreshold = 0; 476 } else { 477 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 478 } 479 480 sc->sc_bus.ub_revision = USBREV_2_0; 481 sc->sc_bus.ub_usedma = true; 482 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 483 484 /* Reset the controller */ 485 DPRINTF("resetting", 0, 0, 0, 0); 486 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 487 usb_delay_ms(&sc->sc_bus, 1); 488 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 489 for (i = 0; i < 100; i++) { 490 usb_delay_ms(&sc->sc_bus, 1); 491 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 492 if (!hcr) 493 break; 494 } 495 if (hcr) { 496 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 497 return EIO; 498 } 499 if (sc->sc_vendor_init) 500 sc->sc_vendor_init(sc); 501 502 /* XXX need proper intr scheduling */ 503 sc->sc_rand = 96; 504 505 /* frame list size at default, read back what we got and use that */ 506 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 507 case 0: sc->sc_flsize = 1024; break; 508 case 1: sc->sc_flsize = 512; break; 509 case 2: sc->sc_flsize = 256; break; 510 case 3: return EIO; 511 } 512 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 513 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 514 if (err) 515 return err; 516 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 517 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 518 519 for (i = 0; i < sc->sc_flsize; i++) { 520 sc->sc_flist[i] = EHCI_NULL; 521 } 522 523 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 524 525 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 526 KM_SLEEP); 527 if (sc->sc_softitds == NULL) 528 return ENOMEM; 529 LIST_INIT(&sc->sc_freeitds); 530 LIST_INIT(&sc->sc_freesitds); 531 TAILQ_INIT(&sc->sc_intrhead); 532 533 /* Set up the bus struct. */ 534 sc->sc_bus.ub_methods = &ehci_bus_methods; 535 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 536 537 sc->sc_eintrs = EHCI_NORMAL_INTRS; 538 539 /* 540 * Allocate the interrupt dummy QHs. These are arranged to give poll 541 * intervals that are powers of 2 times 1ms. 542 */ 543 for (i = 0; i < EHCI_INTRQHS; i++) { 544 sqh = ehci_alloc_sqh(sc); 545 if (sqh == NULL) { 546 err = ENOMEM; 547 goto bad1; 548 } 549 sc->sc_islots[i].sqh = sqh; 550 } 551 for (i = 0; i < EHCI_INTRQHS; i++) { 552 sqh = sc->sc_islots[i].sqh; 553 if (i == 0) { 554 /* The last (1ms) QH terminates. */ 555 sqh->qh.qh_link = EHCI_NULL; 556 sqh->next = NULL; 557 } else { 558 /* Otherwise the next QH has half the poll interval */ 559 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 560 sqh->qh.qh_link = htole32(sqh->next->physaddr | 561 EHCI_LINK_QH); 562 } 563 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 564 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 565 sqh->qh.qh_curqtd = EHCI_NULL; 566 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 567 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 568 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 569 sqh->sqtd = NULL; 570 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 572 } 573 /* Point the frame list at the last level (128ms). */ 574 for (i = 0; i < sc->sc_flsize; i++) { 575 int j; 576 577 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 578 revbits[i & (EHCI_MAX_POLLRATE-1)]; 579 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 580 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 581 i)].sqh->physaddr); 582 } 583 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 584 BUS_DMASYNC_PREWRITE); 585 586 /* Allocate dummy QH that starts the async list. */ 587 sqh = ehci_alloc_sqh(sc); 588 if (sqh == NULL) { 589 err = ENOMEM; 590 goto bad1; 591 } 592 /* Fill the QH */ 593 sqh->qh.qh_endp = 594 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 595 sqh->qh.qh_link = 596 htole32(sqh->physaddr | EHCI_LINK_QH); 597 sqh->qh.qh_curqtd = EHCI_NULL; 598 sqh->next = NULL; 599 /* Fill the overlay qTD */ 600 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 601 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 602 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 603 sqh->sqtd = NULL; 604 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 605 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 606 #ifdef EHCI_DEBUG 607 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 608 ehci_dump_sqh(sqh); 609 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 610 #endif 611 612 /* Point to async list */ 613 sc->sc_async_head = sqh; 614 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 615 616 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 617 618 /* Turn on controller */ 619 EOWRITE4(sc, EHCI_USBCMD, 620 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 621 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 622 EHCI_CMD_ASE | 623 EHCI_CMD_PSE | 624 EHCI_CMD_RS); 625 626 /* Take over port ownership */ 627 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 628 629 for (i = 0; i < 100; i++) { 630 usb_delay_ms(&sc->sc_bus, 1); 631 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 632 if (!hcr) 633 break; 634 } 635 if (hcr) { 636 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 637 return EIO; 638 } 639 640 /* Enable interrupts */ 641 DPRINTF("enabling interupts", 0, 0, 0, 0); 642 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 643 644 return 0; 645 646 #if 0 647 bad2: 648 ehci_free_sqh(sc, sc->sc_async_head); 649 #endif 650 bad1: 651 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 652 return err; 653 } 654 655 int 656 ehci_intr(void *v) 657 { 658 ehci_softc_t *sc = v; 659 int ret = 0; 660 661 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 662 663 if (sc == NULL) 664 return 0; 665 666 mutex_spin_enter(&sc->sc_intr_lock); 667 668 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 669 goto done; 670 671 /* If we get an interrupt while polling, then just ignore it. */ 672 if (sc->sc_bus.ub_usepolling) { 673 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 674 675 if (intrs) 676 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 677 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 678 goto done; 679 } 680 681 ret = ehci_intr1(sc); 682 683 done: 684 mutex_spin_exit(&sc->sc_intr_lock); 685 return ret; 686 } 687 688 Static int 689 ehci_intr1(ehci_softc_t *sc) 690 { 691 uint32_t intrs, eintrs; 692 693 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 694 695 /* In case the interrupt occurs before initialization has completed. */ 696 if (sc == NULL) { 697 #ifdef DIAGNOSTIC 698 printf("ehci_intr1: sc == NULL\n"); 699 #endif 700 return 0; 701 } 702 703 KASSERT(mutex_owned(&sc->sc_intr_lock)); 704 705 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 706 if (!intrs) 707 return 0; 708 709 eintrs = intrs & sc->sc_eintrs; 710 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 711 EOREAD4(sc, EHCI_USBSTS), eintrs); 712 if (!eintrs) 713 return 0; 714 715 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 716 if (eintrs & EHCI_STS_IAA) { 717 DPRINTF("door bell", 0, 0, 0, 0); 718 kpreempt_disable(); 719 KASSERT(sc->sc_doorbell_si != NULL); 720 softint_schedule(sc->sc_doorbell_si); 721 kpreempt_enable(); 722 eintrs &= ~EHCI_STS_IAA; 723 } 724 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 725 DPRINTF("INT=%jd ERRINT=%jd", 726 eintrs & EHCI_STS_INT ? 1 : 0, 727 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 728 usb_schedsoftintr(&sc->sc_bus); 729 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 730 } 731 if (eintrs & EHCI_STS_HSE) { 732 printf("%s: unrecoverable error, controller halted\n", 733 device_xname(sc->sc_dev)); 734 /* XXX what else */ 735 } 736 if (eintrs & EHCI_STS_PCD) { 737 kpreempt_disable(); 738 KASSERT(sc->sc_pcd_si != NULL); 739 softint_schedule(sc->sc_pcd_si); 740 kpreempt_enable(); 741 eintrs &= ~EHCI_STS_PCD; 742 } 743 744 if (eintrs != 0) { 745 /* Block unprocessed interrupts. */ 746 sc->sc_eintrs &= ~eintrs; 747 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 748 printf("%s: blocking intrs 0x%x\n", 749 device_xname(sc->sc_dev), eintrs); 750 } 751 752 return 1; 753 } 754 755 Static void 756 ehci_doorbell(void *addr) 757 { 758 ehci_softc_t *sc = addr; 759 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 760 761 mutex_enter(&sc->sc_lock); 762 cv_broadcast(&sc->sc_doorbell); 763 mutex_exit(&sc->sc_lock); 764 } 765 766 Static void 767 ehci_pcd(void *addr) 768 { 769 ehci_softc_t *sc = addr; 770 struct usbd_xfer *xfer; 771 u_char *p; 772 int i, m; 773 774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 775 776 mutex_enter(&sc->sc_lock); 777 xfer = sc->sc_intrxfer; 778 779 if (xfer == NULL) { 780 /* Just ignore the change. */ 781 goto done; 782 } 783 784 p = xfer->ux_buf; 785 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 786 memset(p, 0, xfer->ux_length); 787 for (i = 1; i <= m; i++) { 788 /* Pick out CHANGE bits from the status reg. */ 789 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 790 p[i/8] |= 1 << (i%8); 791 if (i % 8 == 7) 792 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 793 } 794 xfer->ux_actlen = xfer->ux_length; 795 xfer->ux_status = USBD_NORMAL_COMPLETION; 796 797 usb_transfer_complete(xfer); 798 799 done: 800 mutex_exit(&sc->sc_lock); 801 } 802 803 Static void 804 ehci_softintr(void *v) 805 { 806 struct usbd_bus *bus = v; 807 ehci_softc_t *sc = EHCI_BUS2SC(bus); 808 struct ehci_xfer *ex, *nextex; 809 810 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 811 812 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 813 814 ex_completeq_t cq; 815 TAILQ_INIT(&cq); 816 817 /* 818 * The only explanation I can think of for why EHCI is as brain dead 819 * as UHCI interrupt-wise is that Intel was involved in both. 820 * An interrupt just tells us that something is done, we have no 821 * clue what, so we need to scan through all active transfers. :-( 822 */ 823 824 /* 825 * ehci_idone will remove transfer from sc->sc_intrhead if it's 826 * complete and add to our cq list 827 * 828 */ 829 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 830 switch (ex->ex_type) { 831 case EX_CTRL: 832 case EX_BULK: 833 case EX_INTR: 834 ehci_check_qh_intr(sc, ex, &cq); 835 break; 836 case EX_ISOC: 837 ehci_check_itd_intr(sc, ex, &cq); 838 break; 839 case EX_FS_ISOC: 840 ehci_check_sitd_intr(sc, ex, &cq); 841 break; 842 default: 843 KASSERT(false); 844 } 845 846 } 847 848 /* 849 * We abuse ex_next for the interrupt and complete lists and 850 * interrupt transfers will get re-added here so use 851 * the _SAFE version of TAILQ_FOREACH. 852 */ 853 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 854 usb_transfer_complete(&ex->ex_xfer); 855 } 856 857 /* Schedule a callout to catch any dropped transactions. */ 858 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 859 !TAILQ_EMPTY(&sc->sc_intrhead)) 860 callout_reset(&sc->sc_tmo_intrlist, 861 hz, ehci_intrlist_timeout, sc); 862 } 863 864 Static void 865 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 866 { 867 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 868 uint32_t status; 869 870 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 871 872 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 873 874 if (ex->ex_type == EX_CTRL) { 875 fsqtd = ex->ex_setup; 876 lsqtd = ex->ex_status; 877 } else { 878 fsqtd = ex->ex_sqtdstart; 879 lsqtd = ex->ex_sqtdend; 880 } 881 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 882 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 883 884 /* 885 * If the last TD is still active we need to check whether there 886 * is an error somewhere in the middle, or whether there was a 887 * short packet (SPD and not ACTIVE). 888 */ 889 usb_syncmem(&lsqtd->dma, 890 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 891 sizeof(lsqtd->qtd.qtd_status), 892 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 893 status = le32toh(lsqtd->qtd.qtd_status); 894 usb_syncmem(&lsqtd->dma, 895 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 896 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 897 if (status & EHCI_QTD_ACTIVE) { 898 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 899 900 /* last qTD has already been checked */ 901 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 902 usb_syncmem(&sqtd->dma, 903 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 904 sizeof(sqtd->qtd.qtd_status), 905 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 906 status = le32toh(sqtd->qtd.qtd_status); 907 usb_syncmem(&sqtd->dma, 908 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 909 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 910 /* If there's an active QTD the xfer isn't done. */ 911 if (status & EHCI_QTD_ACTIVE) 912 break; 913 /* Any kind of error makes the xfer done. */ 914 if (status & EHCI_QTD_HALTED) 915 goto done; 916 /* Handle short packets */ 917 if (EHCI_QTD_GET_BYTES(status) != 0) { 918 /* 919 * If we get here for a control transfer then 920 * we need to let the hardware complete the 921 * status phase. That is, we're not done 922 * quite yet. 923 * 924 * Otherwise, we're done. 925 */ 926 if (ex->ex_type == EX_CTRL) { 927 break; 928 } 929 goto done; 930 } 931 } 932 DPRINTFN(10, "ex=%#jx std=%#jx still active", 933 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 934 #ifdef EHCI_DEBUG 935 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 936 ehci_dump_sqtds(ex->ex_sqtdstart); 937 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 938 #endif 939 return; 940 } 941 done: 942 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 943 ehci_idone(ex, cq); 944 } 945 946 Static void 947 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 948 { 949 ehci_soft_itd_t *itd; 950 int i; 951 952 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 953 954 KASSERT(mutex_owned(&sc->sc_lock)); 955 956 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 957 return; 958 959 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 960 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 961 962 itd = ex->ex_itdend; 963 964 /* 965 * check no active transfers in last itd, meaning we're finished 966 */ 967 968 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 969 sizeof(itd->itd.itd_ctl), 970 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 971 972 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 973 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 974 break; 975 } 976 977 if (i == EHCI_ITD_NUFRAMES) { 978 goto done; /* All 8 descriptors inactive, it's done */ 979 } 980 981 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 982 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 983 984 DPRINTFN(10, "ex %#jx itd %#jx still active", 985 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 986 return; 987 done: 988 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 989 ehci_idone(ex, cq); 990 } 991 992 void 993 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 994 { 995 ehci_soft_sitd_t *sitd; 996 997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 998 999 KASSERT(mutex_owned(&sc->sc_lock)); 1000 1001 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1002 return; 1003 1004 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1005 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1006 1007 sitd = ex->ex_sitdend; 1008 1009 /* 1010 * check no active transfers in last sitd, meaning we're finished 1011 */ 1012 1013 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1014 sizeof(sitd->sitd.sitd_trans), 1015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1016 1017 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1021 1022 if (active) 1023 return; 1024 1025 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1026 ehci_idone(ex, cq); 1027 } 1028 1029 1030 Static void 1031 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1032 { 1033 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1034 struct usbd_xfer *xfer = &ex->ex_xfer; 1035 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1036 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1037 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1038 uint32_t status = 0, nstatus = 0; 1039 int actlen = 0; 1040 1041 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1042 1043 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1044 1045 /* 1046 * If software has completed it, either by cancellation 1047 * or timeout, drop it on the floor. 1048 */ 1049 if (xfer->ux_status != USBD_IN_PROGRESS) { 1050 KASSERT(xfer->ux_status == USBD_CANCELLED || 1051 xfer->ux_status == USBD_TIMEOUT); 1052 DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1053 return; 1054 } 1055 1056 /* 1057 * Cancel the timeout and the task, which have not yet 1058 * run. If they have already fired, at worst they are 1059 * waiting for the lock. They will see that the xfer 1060 * is no longer in progress and give up. 1061 */ 1062 callout_stop(&xfer->ux_callout); 1063 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 1064 1065 #ifdef DIAGNOSTIC 1066 #ifdef EHCI_DEBUG 1067 if (ex->ex_isdone) { 1068 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1069 ehci_dump_exfer(ex); 1070 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1071 } 1072 #endif 1073 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1074 ex->ex_type, xfer->ux_status); 1075 ex->ex_isdone = true; 1076 #endif 1077 1078 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1079 (uintptr_t)epipe, 0, 0); 1080 1081 /* The transfer is done, compute actual length and status. */ 1082 if (ex->ex_type == EX_ISOC) { 1083 /* HS isoc transfer */ 1084 1085 struct ehci_soft_itd *itd; 1086 int i, nframes, len, uframes; 1087 1088 nframes = 0; 1089 1090 #ifdef EHCI_DEBUG 1091 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1092 ehci_dump_itds(ex->ex_itdstart); 1093 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1094 #endif 1095 1096 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1097 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1098 1099 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1100 usb_syncmem(&itd->dma, 1101 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1102 sizeof(itd->itd.itd_ctl), 1103 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1104 1105 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1106 /* 1107 * XXX - driver didn't fill in the frame full 1108 * of uframes. This leads to scheduling 1109 * inefficiencies, but working around 1110 * this doubles complexity of tracking 1111 * an xfer. 1112 */ 1113 if (nframes >= xfer->ux_nframes) 1114 break; 1115 1116 status = le32toh(itd->itd.itd_ctl[i]); 1117 len = EHCI_ITD_GET_LEN(status); 1118 if (EHCI_ITD_GET_STATUS(status) != 0) 1119 len = 0; /*No valid data on error*/ 1120 1121 xfer->ux_frlengths[nframes++] = len; 1122 actlen += len; 1123 } 1124 usb_syncmem(&itd->dma, 1125 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1126 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1127 1128 if (nframes >= xfer->ux_nframes) 1129 break; 1130 } 1131 1132 xfer->ux_actlen = actlen; 1133 xfer->ux_status = USBD_NORMAL_COMPLETION; 1134 goto end; 1135 } else if (ex->ex_type == EX_FS_ISOC) { 1136 /* FS isoc transfer */ 1137 struct ehci_soft_sitd *sitd; 1138 int nframes, len; 1139 1140 nframes = 0; 1141 1142 for (sitd = ex->ex_sitdstart; sitd != NULL; 1143 sitd = sitd->xfer_next) { 1144 usb_syncmem(&sitd->dma, 1145 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1146 sizeof(sitd->sitd.sitd_trans), 1147 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1148 1149 /* 1150 * XXX - driver didn't fill in the frame full 1151 * of uframes. This leads to scheduling 1152 * inefficiencies, but working around 1153 * this doubles complexity of tracking 1154 * an xfer. 1155 */ 1156 if (nframes >= xfer->ux_nframes) 1157 break; 1158 1159 status = le32toh(sitd->sitd.sitd_trans); 1160 usb_syncmem(&sitd->dma, 1161 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1162 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1163 1164 len = EHCI_SITD_GET_LEN(status); 1165 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1166 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1167 /* No valid data on error */ 1168 len = xfer->ux_frlengths[nframes]; 1169 } 1170 1171 /* 1172 * frlengths[i]: # of bytes to send 1173 * len: # of bytes host didn't send 1174 */ 1175 xfer->ux_frlengths[nframes] -= len; 1176 /* frlengths[i]: # of bytes host sent */ 1177 actlen += xfer->ux_frlengths[nframes++]; 1178 1179 if (nframes >= xfer->ux_nframes) 1180 break; 1181 } 1182 1183 xfer->ux_actlen = actlen; 1184 xfer->ux_status = USBD_NORMAL_COMPLETION; 1185 goto end; 1186 } 1187 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1188 ex->ex_type == EX_BULK); 1189 1190 /* Continue processing xfers using queue heads */ 1191 if (ex->ex_type == EX_CTRL) { 1192 fsqtd = ex->ex_setup; 1193 lsqtd = ex->ex_status; 1194 } else { 1195 fsqtd = ex->ex_sqtdstart; 1196 lsqtd = ex->ex_sqtdend; 1197 } 1198 #ifdef EHCI_DEBUG 1199 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1200 ehci_dump_sqtds(fsqtd); 1201 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1202 #endif 1203 1204 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1205 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1206 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1207 nstatus = le32toh(sqtd->qtd.qtd_status); 1208 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1209 BUS_DMASYNC_PREREAD); 1210 if (nstatus & EHCI_QTD_ACTIVE) 1211 break; 1212 1213 status = nstatus; 1214 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1215 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1216 } 1217 1218 /* 1219 * If there are left over TDs we need to update the toggle. 1220 * The default pipe doesn't need it since control transfers 1221 * start the toggle at 0 every time. 1222 * For a short transfer we need to update the toggle for the missing 1223 * packets within the qTD. 1224 */ 1225 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1226 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1227 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1228 status, nstatus, 0, 0); 1229 #if 0 1230 ehci_dump_sqh(epipe->sqh); 1231 ehci_dump_sqtds(ex->ex_sqtdstart); 1232 #endif 1233 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1234 } 1235 1236 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1237 status, 0); 1238 xfer->ux_actlen = actlen; 1239 if (status & EHCI_QTD_HALTED) { 1240 #ifdef EHCI_DEBUG 1241 DPRINTF("halted addr=%jd endpt=0x%02jx", 1242 xfer->ux_pipe->up_dev->ud_addr, 1243 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1244 0, 0); 1245 DPRINTF("cerr=%jd pid=%jd", 1246 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1247 0, 0); 1248 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1249 status & EHCI_QTD_ACTIVE ? 1 : 0, 1250 status & EHCI_QTD_HALTED ? 1 : 0, 1251 status & EHCI_QTD_BUFERR ? 1 : 0, 1252 status & EHCI_QTD_BABBLE ? 1 : 0); 1253 1254 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1255 status & EHCI_QTD_XACTERR ? 1 : 0, 1256 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1257 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1258 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1259 1260 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1261 ehci_dump_sqh(epipe->sqh); 1262 ehci_dump_sqtds(ex->ex_sqtdstart); 1263 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1264 #endif 1265 /* low&full speed has an extra error flag */ 1266 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1267 EHCI_QH_SPEED_HIGH) 1268 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1269 else 1270 status &= EHCI_QTD_STATERRS; 1271 if (status == 0) /* no other errors means a stall */ { 1272 xfer->ux_status = USBD_STALLED; 1273 } else { 1274 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1275 } 1276 /* XXX need to reset TT on missed microframe */ 1277 if (status & EHCI_QTD_MISSEDMICRO) { 1278 printf("%s: missed microframe, TT reset not " 1279 "implemented, hub might be inoperational\n", 1280 device_xname(sc->sc_dev)); 1281 } 1282 } else { 1283 xfer->ux_status = USBD_NORMAL_COMPLETION; 1284 } 1285 1286 end: 1287 1288 ehci_del_intr_list(sc, ex); 1289 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1290 1291 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1292 } 1293 1294 Static void 1295 ehci_poll(struct usbd_bus *bus) 1296 { 1297 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1298 1299 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1300 1301 #ifdef EHCI_DEBUG 1302 static int last; 1303 int new; 1304 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1305 if (new != last) { 1306 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1307 last = new; 1308 } 1309 #endif 1310 1311 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1312 mutex_spin_enter(&sc->sc_intr_lock); 1313 ehci_intr1(sc); 1314 mutex_spin_exit(&sc->sc_intr_lock); 1315 } 1316 } 1317 1318 void 1319 ehci_childdet(device_t self, device_t child) 1320 { 1321 struct ehci_softc *sc = device_private(self); 1322 1323 KASSERT(sc->sc_child == child); 1324 sc->sc_child = NULL; 1325 } 1326 1327 int 1328 ehci_detach(struct ehci_softc *sc, int flags) 1329 { 1330 int rv = 0; 1331 1332 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1333 1334 if (sc->sc_child != NULL) 1335 rv = config_detach(sc->sc_child, flags); 1336 1337 if (rv != 0) 1338 return rv; 1339 1340 callout_halt(&sc->sc_tmo_intrlist, NULL); 1341 callout_destroy(&sc->sc_tmo_intrlist); 1342 1343 /* XXX free other data structures XXX */ 1344 if (sc->sc_softitds) 1345 kmem_free(sc->sc_softitds, 1346 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1347 cv_destroy(&sc->sc_doorbell); 1348 1349 #if 0 1350 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1351 1352 softint_disestablish(sc->sc_doorbell_si); 1353 softint_disestablish(sc->sc_pcd_si); 1354 1355 mutex_destroy(&sc->sc_lock); 1356 mutex_destroy(&sc->sc_intr_lock); 1357 #endif 1358 1359 pool_cache_destroy(sc->sc_xferpool); 1360 1361 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1362 1363 return rv; 1364 } 1365 1366 1367 int 1368 ehci_activate(device_t self, enum devact act) 1369 { 1370 struct ehci_softc *sc = device_private(self); 1371 1372 switch (act) { 1373 case DVACT_DEACTIVATE: 1374 sc->sc_dying = 1; 1375 return 0; 1376 default: 1377 return EOPNOTSUPP; 1378 } 1379 } 1380 1381 /* 1382 * Handle suspend/resume. 1383 * 1384 * We need to switch to polling mode here, because this routine is 1385 * called from an interrupt context. This is all right since we 1386 * are almost suspended anyway. 1387 * 1388 * Note that this power handler isn't to be registered directly; the 1389 * bus glue needs to call out to it. 1390 */ 1391 bool 1392 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1393 { 1394 ehci_softc_t *sc = device_private(dv); 1395 int i; 1396 uint32_t cmd, hcr; 1397 1398 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1399 1400 mutex_spin_enter(&sc->sc_intr_lock); 1401 sc->sc_bus.ub_usepolling++; 1402 mutex_spin_exit(&sc->sc_intr_lock); 1403 1404 for (i = 1; i <= sc->sc_noport; i++) { 1405 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1406 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1407 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1408 } 1409 1410 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1411 1412 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1413 EOWRITE4(sc, EHCI_USBCMD, cmd); 1414 1415 for (i = 0; i < 100; i++) { 1416 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1417 if (hcr == 0) 1418 break; 1419 1420 usb_delay_ms(&sc->sc_bus, 1); 1421 } 1422 if (hcr != 0) 1423 printf("%s: reset timeout\n", device_xname(dv)); 1424 1425 cmd &= ~EHCI_CMD_RS; 1426 EOWRITE4(sc, EHCI_USBCMD, cmd); 1427 1428 for (i = 0; i < 100; i++) { 1429 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1430 if (hcr == EHCI_STS_HCH) 1431 break; 1432 1433 usb_delay_ms(&sc->sc_bus, 1); 1434 } 1435 if (hcr != EHCI_STS_HCH) 1436 printf("%s: config timeout\n", device_xname(dv)); 1437 1438 mutex_spin_enter(&sc->sc_intr_lock); 1439 sc->sc_bus.ub_usepolling--; 1440 mutex_spin_exit(&sc->sc_intr_lock); 1441 1442 return true; 1443 } 1444 1445 bool 1446 ehci_resume(device_t dv, const pmf_qual_t *qual) 1447 { 1448 ehci_softc_t *sc = device_private(dv); 1449 int i; 1450 uint32_t cmd, hcr; 1451 1452 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1453 1454 /* restore things in case the bios sucks */ 1455 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1456 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1457 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1458 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1459 1460 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1461 1462 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1463 1464 hcr = 0; 1465 for (i = 1; i <= sc->sc_noport; i++) { 1466 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1467 if ((cmd & EHCI_PS_PO) == 0 && 1468 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1469 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1470 hcr = 1; 1471 } 1472 } 1473 1474 if (hcr) { 1475 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1476 1477 for (i = 1; i <= sc->sc_noport; i++) { 1478 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1479 if ((cmd & EHCI_PS_PO) == 0 && 1480 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1481 EOWRITE4(sc, EHCI_PORTSC(i), 1482 cmd & ~EHCI_PS_FPR); 1483 } 1484 } 1485 1486 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1487 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1488 1489 for (i = 0; i < 100; i++) { 1490 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1491 if (hcr != EHCI_STS_HCH) 1492 break; 1493 1494 usb_delay_ms(&sc->sc_bus, 1); 1495 } 1496 if (hcr == EHCI_STS_HCH) 1497 printf("%s: config timeout\n", device_xname(dv)); 1498 1499 return true; 1500 } 1501 1502 /* 1503 * Shut down the controller when the system is going down. 1504 */ 1505 bool 1506 ehci_shutdown(device_t self, int flags) 1507 { 1508 ehci_softc_t *sc = device_private(self); 1509 1510 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1511 1512 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1513 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1514 return true; 1515 } 1516 1517 Static struct usbd_xfer * 1518 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1519 { 1520 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1521 struct usbd_xfer *xfer; 1522 1523 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1524 if (xfer != NULL) { 1525 memset(xfer, 0, sizeof(struct ehci_xfer)); 1526 1527 /* Initialise this always so we can call remove on it. */ 1528 usb_init_task(&xfer->ux_aborttask, ehci_timeout_task, xfer, 1529 USB_TASKQ_MPSAFE); 1530 #ifdef DIAGNOSTIC 1531 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1532 ex->ex_isdone = true; 1533 xfer->ux_state = XFER_BUSY; 1534 #endif 1535 } 1536 return xfer; 1537 } 1538 1539 Static void 1540 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1541 { 1542 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1543 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1544 1545 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1546 xfer->ux_state); 1547 KASSERT(ex->ex_isdone); 1548 1549 #ifdef DIAGNOSTIC 1550 xfer->ux_state = XFER_FREE; 1551 #endif 1552 1553 pool_cache_put(sc->sc_xferpool, xfer); 1554 } 1555 1556 Static void 1557 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1558 { 1559 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1560 1561 *lock = &sc->sc_lock; 1562 } 1563 1564 Static void 1565 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1566 { 1567 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1568 1569 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1570 1571 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1572 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1573 #ifdef EHCI_DEBUG 1574 if (ehcidebug) 1575 usbd_dump_pipe(pipe); 1576 #endif 1577 epipe->nexttoggle = 0; 1578 } 1579 1580 Static void 1581 ehci_noop(struct usbd_pipe *pipe) 1582 { 1583 } 1584 1585 #ifdef EHCI_DEBUG 1586 /* 1587 * Unused function - this is meant to be called from a kernel 1588 * debugger. 1589 */ 1590 void 1591 ehci_dump(void) 1592 { 1593 ehci_softc_t *sc = theehci; 1594 int i; 1595 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1596 EOREAD4(sc, EHCI_USBCMD), 1597 EOREAD4(sc, EHCI_USBSTS), 1598 EOREAD4(sc, EHCI_USBINTR)); 1599 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1600 EOREAD4(sc, EHCI_FRINDEX), 1601 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1602 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1603 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1604 for (i = 1; i <= sc->sc_noport; i++) 1605 printf("port %d status=0x%08x\n", i, 1606 EOREAD4(sc, EHCI_PORTSC(i))); 1607 } 1608 1609 Static void 1610 ehci_dump_regs(ehci_softc_t *sc) 1611 { 1612 int i; 1613 1614 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1615 1616 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1617 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1618 EOREAD4(sc, EHCI_USBINTR), 0); 1619 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1620 "async = 0x%08jx", 1621 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1622 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1623 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1624 for (i = 1; i <= sc->sc_noport; i += 2) { 1625 if (i == sc->sc_noport) { 1626 DPRINTF("port %jd status = 0x%08jx", i, 1627 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1628 } else { 1629 DPRINTF("port %jd status = 0x%08jx port %jd " 1630 "status = 0x%08jx", 1631 i, EOREAD4(sc, EHCI_PORTSC(i)), 1632 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1633 } 1634 } 1635 } 1636 1637 #define ehci_dump_link(link, type) do { \ 1638 DPRINTF(" link 0x%08jx (T = %jd):", \ 1639 link, \ 1640 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1641 if (type) { \ 1642 DPRINTF( \ 1643 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1644 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1645 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1646 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1647 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1648 } \ 1649 } while(0) 1650 1651 Static void 1652 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1653 { 1654 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1655 int i; 1656 uint32_t stop = 0; 1657 1658 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1659 ehci_dump_sqtd(sqtd); 1660 usb_syncmem(&sqtd->dma, 1661 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1662 sizeof(sqtd->qtd), 1663 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1664 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1665 usb_syncmem(&sqtd->dma, 1666 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1667 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1668 } 1669 if (!stop) 1670 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1671 } 1672 1673 Static void 1674 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1675 { 1676 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1677 1678 usb_syncmem(&sqtd->dma, sqtd->offs, 1679 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1680 1681 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1682 0, 0); 1683 ehci_dump_qtd(&sqtd->qtd); 1684 1685 usb_syncmem(&sqtd->dma, sqtd->offs, 1686 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1687 } 1688 1689 Static void 1690 ehci_dump_qtd(ehci_qtd_t *qtd) 1691 { 1692 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1693 uint32_t s = le32toh(qtd->qtd_status); 1694 1695 DPRINTFN(10, 1696 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1697 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1698 DPRINTFN(10, 1699 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1700 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1701 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1702 DPRINTFN(10, 1703 " cerr = %jd pid = %jd stat = %jx", 1704 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1705 0); 1706 DPRINTFN(10, 1707 "active =%jd halted=%jd buferr=%jd babble=%jd", 1708 s & EHCI_QTD_ACTIVE ? 1 : 0, 1709 s & EHCI_QTD_HALTED ? 1 : 0, 1710 s & EHCI_QTD_BUFERR ? 1 : 0, 1711 s & EHCI_QTD_BABBLE ? 1 : 0); 1712 DPRINTFN(10, 1713 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1714 s & EHCI_QTD_XACTERR ? 1 : 0, 1715 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1716 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1717 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1718 DPRINTFN(10, 1719 "buffer[0] = %#jx buffer[1] = %#jx " 1720 "buffer[2] = %#jx buffer[3] = %#jx", 1721 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1722 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1723 DPRINTFN(10, 1724 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1725 } 1726 1727 Static void 1728 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1729 { 1730 ehci_qh_t *qh = &sqh->qh; 1731 ehci_link_t link; 1732 uint32_t endp, endphub; 1733 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1734 1735 usb_syncmem(&sqh->dma, sqh->offs, 1736 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1737 1738 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1739 link = le32toh(qh->qh_link); 1740 ehci_dump_link(link, true); 1741 1742 endp = le32toh(qh->qh_endp); 1743 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1744 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1745 "eps = %jd", 1746 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1747 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1748 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1749 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1750 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1751 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1752 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1753 1754 endphub = le32toh(qh->qh_endphub); 1755 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1756 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1757 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1758 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1759 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1760 EHCI_QH_GET_MULT(endphub), 0); 1761 1762 link = le32toh(qh->qh_curqtd); 1763 ehci_dump_link(link, false); 1764 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1765 ehci_dump_qtd(&qh->qh_qtd); 1766 1767 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1768 BUS_DMASYNC_PREREAD); 1769 } 1770 1771 Static void 1772 ehci_dump_itds(ehci_soft_itd_t *itd) 1773 { 1774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1775 int i; 1776 uint32_t stop = 0; 1777 1778 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1779 ehci_dump_itd(itd); 1780 usb_syncmem(&itd->dma, 1781 itd->offs + offsetof(ehci_itd_t, itd_next), 1782 sizeof(itd->itd), 1783 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1784 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1785 usb_syncmem(&itd->dma, 1786 itd->offs + offsetof(ehci_itd_t, itd_next), 1787 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1788 } 1789 if (!stop) 1790 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1791 } 1792 1793 Static void 1794 ehci_dump_itd(struct ehci_soft_itd *itd) 1795 { 1796 ehci_isoc_trans_t t; 1797 ehci_isoc_bufr_ptr_t b, b2, b3; 1798 int i; 1799 1800 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1801 1802 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1803 1804 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1805 t = le32toh(itd->itd.itd_ctl[i]); 1806 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1807 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1808 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1809 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1810 EHCI_ITD_GET_OFFS(t), 0); 1811 } 1812 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1813 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1814 DPRINTF(" %jx", 1815 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1816 1817 b = le32toh(itd->itd.itd_bufr[0]); 1818 b2 = le32toh(itd->itd.itd_bufr[1]); 1819 b3 = le32toh(itd->itd.itd_bufr[2]); 1820 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1821 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1822 DPRINTF(" maxpkt = %jx multi = %jx", 1823 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1824 } 1825 1826 Static void 1827 ehci_dump_sitd(struct ehci_soft_itd *itd) 1828 { 1829 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1830 1831 DPRINTF("SITD %#jx next = %p prev = %#jx", 1832 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1833 (uintptr_t)itd->frame_list.prev, 0); 1834 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1835 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1836 } 1837 1838 Static void 1839 ehci_dump_exfer(struct ehci_xfer *ex) 1840 { 1841 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1842 1843 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1844 ex->ex_isdone, 0); 1845 1846 switch (ex->ex_type) { 1847 case EX_CTRL: 1848 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1849 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1850 (uintptr_t)ex->ex_status, 0); 1851 break; 1852 case EX_BULK: 1853 case EX_INTR: 1854 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1855 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1856 0, 0); 1857 break; 1858 case EX_ISOC: 1859 DPRINTF(" itdstart = %#jx itdend = %#jx", 1860 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1861 break; 1862 case EX_FS_ISOC: 1863 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1864 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1865 0, 0); 1866 break; 1867 default: 1868 DPRINTF(" unknown type", 0, 0, 0, 0); 1869 } 1870 } 1871 #endif 1872 1873 Static usbd_status 1874 ehci_open(struct usbd_pipe *pipe) 1875 { 1876 struct usbd_device *dev = pipe->up_dev; 1877 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1878 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1879 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1880 uint8_t addr = dev->ud_addr; 1881 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1882 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1883 ehci_soft_qh_t *sqh; 1884 usbd_status err; 1885 int ival, speed, naks; 1886 int hshubaddr, hshubport; 1887 1888 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1889 1890 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1891 ed->bEndpointAddress, rhaddr); 1892 1893 if (dev->ud_myhsport) { 1894 /* 1895 * When directly attached FS/LS device while doing embedded 1896 * transaction translations and we are the hub, set the hub 1897 * address to 0 (us). 1898 */ 1899 if (!(sc->sc_flags & EHCIF_ETTF) 1900 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1901 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1902 } else { 1903 hshubaddr = 0; 1904 } 1905 hshubport = dev->ud_myhsport->up_portno; 1906 } else { 1907 hshubaddr = 0; 1908 hshubport = 0; 1909 } 1910 1911 if (sc->sc_dying) 1912 return USBD_IOERROR; 1913 1914 /* toggle state needed for bulk endpoints */ 1915 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1916 1917 if (addr == rhaddr) { 1918 switch (ed->bEndpointAddress) { 1919 case USB_CONTROL_ENDPOINT: 1920 pipe->up_methods = &roothub_ctrl_methods; 1921 break; 1922 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1923 pipe->up_methods = &ehci_root_intr_methods; 1924 break; 1925 default: 1926 DPRINTF("bad bEndpointAddress 0x%02jx", 1927 ed->bEndpointAddress, 0, 0, 0); 1928 return USBD_INVAL; 1929 } 1930 return USBD_NORMAL_COMPLETION; 1931 } 1932 1933 /* XXX All this stuff is only valid for async. */ 1934 switch (dev->ud_speed) { 1935 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1936 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1937 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1938 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1939 } 1940 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1941 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1942 0); 1943 return USBD_INVAL; 1944 } 1945 1946 /* 1947 * For interrupt transfer, nak throttling must be disabled, but for 1948 * the other transfer type, nak throttling should be enabled from the 1949 * viewpoint that avoids the memory thrashing. 1950 */ 1951 naks = (xfertype == UE_INTERRUPT) ? 0 1952 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1953 1954 /* Allocate sqh for everything, save isoc xfers */ 1955 if (xfertype != UE_ISOCHRONOUS) { 1956 sqh = ehci_alloc_sqh(sc); 1957 if (sqh == NULL) 1958 return USBD_NOMEM; 1959 /* qh_link filled when the QH is added */ 1960 sqh->qh.qh_endp = htole32( 1961 EHCI_QH_SET_ADDR(addr) | 1962 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1963 EHCI_QH_SET_EPS(speed) | 1964 EHCI_QH_DTC | 1965 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1966 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1967 EHCI_QH_CTL : 0) | 1968 EHCI_QH_SET_NRL(naks) 1969 ); 1970 sqh->qh.qh_endphub = htole32( 1971 EHCI_QH_SET_MULT(1) | 1972 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1973 ); 1974 if (speed != EHCI_QH_SPEED_HIGH) 1975 sqh->qh.qh_endphub |= htole32( 1976 EHCI_QH_SET_PORT(hshubport) | 1977 EHCI_QH_SET_HUBA(hshubaddr) | 1978 (xfertype == UE_INTERRUPT ? 1979 EHCI_QH_SET_CMASK(0x08) : 0) 1980 ); 1981 sqh->qh.qh_curqtd = EHCI_NULL; 1982 /* Fill the overlay qTD */ 1983 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1984 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1985 sqh->qh.qh_qtd.qtd_status = htole32(0); 1986 1987 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1989 epipe->sqh = sqh; 1990 } else { 1991 sqh = NULL; 1992 } /*xfertype == UE_ISOC*/ 1993 1994 switch (xfertype) { 1995 case UE_CONTROL: 1996 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1997 0, &epipe->ctrl.reqdma); 1998 #ifdef EHCI_DEBUG 1999 if (err) 2000 printf("ehci_open: usb_allocmem()=%d\n", err); 2001 #endif 2002 if (err) 2003 goto bad; 2004 pipe->up_methods = &ehci_device_ctrl_methods; 2005 mutex_enter(&sc->sc_lock); 2006 ehci_add_qh(sc, sqh, sc->sc_async_head); 2007 mutex_exit(&sc->sc_lock); 2008 break; 2009 case UE_BULK: 2010 pipe->up_methods = &ehci_device_bulk_methods; 2011 mutex_enter(&sc->sc_lock); 2012 ehci_add_qh(sc, sqh, sc->sc_async_head); 2013 mutex_exit(&sc->sc_lock); 2014 break; 2015 case UE_INTERRUPT: 2016 pipe->up_methods = &ehci_device_intr_methods; 2017 ival = pipe->up_interval; 2018 if (ival == USBD_DEFAULT_INTERVAL) { 2019 if (speed == EHCI_QH_SPEED_HIGH) { 2020 if (ed->bInterval > 16) { 2021 /* 2022 * illegal with high-speed, but there 2023 * were documentation bugs in the spec, 2024 * so be generous 2025 */ 2026 ival = 256; 2027 } else 2028 ival = (1 << (ed->bInterval - 1)) / 8; 2029 } else 2030 ival = ed->bInterval; 2031 } 2032 err = ehci_device_setintr(sc, sqh, ival); 2033 if (err) 2034 goto bad; 2035 break; 2036 case UE_ISOCHRONOUS: 2037 pipe->up_serialise = false; 2038 if (speed == EHCI_QH_SPEED_HIGH) 2039 pipe->up_methods = &ehci_device_isoc_methods; 2040 else 2041 pipe->up_methods = &ehci_device_fs_isoc_methods; 2042 if (ed->bInterval == 0 || ed->bInterval > 16) { 2043 printf("ehci: opening pipe with invalid bInterval\n"); 2044 err = USBD_INVAL; 2045 goto bad; 2046 } 2047 if (UGETW(ed->wMaxPacketSize) == 0) { 2048 printf("ehci: zero length endpoint open request\n"); 2049 err = USBD_INVAL; 2050 goto bad; 2051 } 2052 epipe->isoc.next_frame = 0; 2053 epipe->isoc.cur_xfers = 0; 2054 break; 2055 default: 2056 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2057 err = USBD_INVAL; 2058 goto bad; 2059 } 2060 return USBD_NORMAL_COMPLETION; 2061 2062 bad: 2063 if (sqh != NULL) { 2064 mutex_enter(&sc->sc_lock); 2065 ehci_free_sqh(sc, sqh); 2066 mutex_exit(&sc->sc_lock); 2067 } 2068 return err; 2069 } 2070 2071 /* 2072 * Add an ED to the schedule. Called with USB lock held. 2073 */ 2074 Static void 2075 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2076 { 2077 2078 KASSERT(mutex_owned(&sc->sc_lock)); 2079 2080 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2081 2082 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2083 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2084 2085 sqh->next = head->next; 2086 sqh->qh.qh_link = head->qh.qh_link; 2087 2088 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2089 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2090 2091 head->next = sqh; 2092 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2093 2094 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2095 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2096 2097 #ifdef EHCI_DEBUG 2098 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2099 ehci_dump_sqh(sqh); 2100 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2101 #endif 2102 } 2103 2104 /* 2105 * Remove an ED from the schedule. Called with USB lock held. 2106 */ 2107 Static void 2108 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2109 { 2110 ehci_soft_qh_t *p; 2111 2112 KASSERT(mutex_owned(&sc->sc_lock)); 2113 2114 /* XXX */ 2115 for (p = head; p != NULL && p->next != sqh; p = p->next) 2116 ; 2117 if (p == NULL) 2118 panic("ehci_rem_qh: ED not found"); 2119 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2120 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2121 p->next = sqh->next; 2122 p->qh.qh_link = sqh->qh.qh_link; 2123 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2124 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2125 2126 ehci_sync_hc(sc); 2127 } 2128 2129 Static void 2130 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2131 { 2132 int i; 2133 uint32_t status; 2134 2135 /* Save toggle bit and ping status. */ 2136 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2137 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2138 status = sqh->qh.qh_qtd.qtd_status & 2139 htole32(EHCI_QTD_TOGGLE_MASK | 2140 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2141 /* Set HALTED to make hw leave it alone. */ 2142 sqh->qh.qh_qtd.qtd_status = 2143 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2144 usb_syncmem(&sqh->dma, 2145 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2146 sizeof(sqh->qh.qh_qtd.qtd_status), 2147 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2148 sqh->qh.qh_curqtd = 0; 2149 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2150 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2151 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2152 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2153 sqh->sqtd = sqtd; 2154 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2155 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2156 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2157 sqh->qh.qh_qtd.qtd_status = status; 2158 usb_syncmem(&sqh->dma, 2159 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2160 sizeof(sqh->qh.qh_qtd.qtd_status), 2161 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2162 } 2163 2164 /* 2165 * Ensure that the HC has released all references to the QH. We do this 2166 * by asking for a Async Advance Doorbell interrupt and then we wait for 2167 * the interrupt. 2168 * To make this easier we first obtain exclusive use of the doorbell. 2169 */ 2170 Static void 2171 ehci_sync_hc(ehci_softc_t *sc) 2172 { 2173 int error __diagused; 2174 2175 KASSERT(mutex_owned(&sc->sc_lock)); 2176 2177 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2178 2179 if (sc->sc_dying) { 2180 DPRINTF("dying", 0, 0, 0, 0); 2181 return; 2182 } 2183 2184 /* ask for doorbell */ 2185 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2186 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2187 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2188 2189 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2190 2191 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2192 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2193 #ifdef DIAGNOSTIC 2194 if (error == EWOULDBLOCK) { 2195 printf("ehci_sync_hc: timed out\n"); 2196 } else if (error) { 2197 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2198 } 2199 #endif 2200 } 2201 2202 Static void 2203 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2204 { 2205 2206 KASSERT(mutex_owned(&sc->sc_lock)); 2207 2208 for (; itd != NULL; itd = itd->xfer_next) { 2209 struct ehci_soft_itd *prev = itd->frame_list.prev; 2210 2211 /* Unlink itd from hardware chain, or frame array */ 2212 if (prev == NULL) { /* We're at the table head */ 2213 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2214 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2215 usb_syncmem(&sc->sc_fldma, 2216 sizeof(ehci_link_t) * itd->slot, 2217 sizeof(ehci_link_t), 2218 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2219 2220 if (itd->frame_list.next != NULL) 2221 itd->frame_list.next->frame_list.prev = NULL; 2222 } else { 2223 /* XXX this part is untested... */ 2224 prev->itd.itd_next = itd->itd.itd_next; 2225 usb_syncmem(&itd->dma, 2226 itd->offs + offsetof(ehci_itd_t, itd_next), 2227 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2228 2229 prev->frame_list.next = itd->frame_list.next; 2230 if (itd->frame_list.next != NULL) 2231 itd->frame_list.next->frame_list.prev = prev; 2232 } 2233 } 2234 } 2235 2236 Static void 2237 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2238 { 2239 struct ehci_soft_itd *next; 2240 2241 mutex_enter(&sc->sc_lock); 2242 next = NULL; 2243 for (; itd != NULL; itd = next) { 2244 next = itd->xfer_next; 2245 ehci_free_itd_locked(sc, itd); 2246 } 2247 mutex_exit(&sc->sc_lock); 2248 } 2249 2250 Static void 2251 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2252 { 2253 2254 KASSERT(mutex_owned(&sc->sc_lock)); 2255 2256 for (; sitd != NULL; sitd = sitd->xfer_next) { 2257 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2258 2259 /* Unlink sitd from hardware chain, or frame array */ 2260 if (prev == NULL) { /* We're at the table head */ 2261 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2262 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2263 usb_syncmem(&sc->sc_fldma, 2264 sizeof(ehci_link_t) * sitd->slot, 2265 sizeof(ehci_link_t), 2266 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2267 2268 if (sitd->frame_list.next != NULL) 2269 sitd->frame_list.next->frame_list.prev = NULL; 2270 } else { 2271 /* XXX this part is untested... */ 2272 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2273 usb_syncmem(&sitd->dma, 2274 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2275 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2276 2277 prev->frame_list.next = sitd->frame_list.next; 2278 if (sitd->frame_list.next != NULL) 2279 sitd->frame_list.next->frame_list.prev = prev; 2280 } 2281 } 2282 } 2283 2284 Static void 2285 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2286 { 2287 2288 mutex_enter(&sc->sc_lock); 2289 struct ehci_soft_sitd *next = NULL; 2290 for (; sitd != NULL; sitd = next) { 2291 next = sitd->xfer_next; 2292 ehci_free_sitd_locked(sc, sitd); 2293 } 2294 mutex_exit(&sc->sc_lock); 2295 } 2296 2297 /***********/ 2298 2299 Static int 2300 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2301 void *buf, int buflen) 2302 { 2303 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2304 usb_hub_descriptor_t hubd; 2305 usb_port_status_t ps; 2306 uint16_t len, value, index; 2307 int l, totlen = 0; 2308 int port, i; 2309 uint32_t v; 2310 2311 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2312 2313 if (sc->sc_dying) 2314 return -1; 2315 2316 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2317 0, 0); 2318 2319 len = UGETW(req->wLength); 2320 value = UGETW(req->wValue); 2321 index = UGETW(req->wIndex); 2322 2323 #define C(x,y) ((x) | ((y) << 8)) 2324 switch (C(req->bRequest, req->bmRequestType)) { 2325 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2326 if (len == 0) 2327 break; 2328 switch (value) { 2329 #define sd ((usb_string_descriptor_t *)buf) 2330 case C(2, UDESC_STRING): 2331 /* Product */ 2332 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2333 break; 2334 #undef sd 2335 default: 2336 /* default from usbroothub */ 2337 return buflen; 2338 } 2339 break; 2340 2341 /* Hub requests */ 2342 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2343 break; 2344 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2345 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2346 value, 0, 0); 2347 if (index < 1 || index > sc->sc_noport) { 2348 return -1; 2349 } 2350 port = EHCI_PORTSC(index); 2351 v = EOREAD4(sc, port); 2352 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2353 v &= ~EHCI_PS_CLEAR; 2354 switch (value) { 2355 case UHF_PORT_ENABLE: 2356 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2357 break; 2358 case UHF_PORT_SUSPEND: 2359 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2360 break; 2361 v &= ~EHCI_PS_SUSP; 2362 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2363 /* see USB2 spec ch. 7.1.7.7 */ 2364 usb_delay_ms(&sc->sc_bus, 20); 2365 EOWRITE4(sc, port, v); 2366 usb_delay_ms(&sc->sc_bus, 2); 2367 #ifdef DEBUG 2368 v = EOREAD4(sc, port); 2369 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2370 printf("ehci: resume failed: %x\n", v); 2371 #endif 2372 break; 2373 case UHF_PORT_POWER: 2374 if (sc->sc_hasppc) 2375 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2376 break; 2377 case UHF_PORT_TEST: 2378 DPRINTF("clear port test %jd", index, 0, 0, 0); 2379 break; 2380 case UHF_PORT_INDICATOR: 2381 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2382 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2383 break; 2384 case UHF_C_PORT_CONNECTION: 2385 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2386 break; 2387 case UHF_C_PORT_ENABLE: 2388 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2389 break; 2390 case UHF_C_PORT_SUSPEND: 2391 /* how? */ 2392 break; 2393 case UHF_C_PORT_OVER_CURRENT: 2394 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2395 break; 2396 case UHF_C_PORT_RESET: 2397 sc->sc_isreset[index] = 0; 2398 break; 2399 default: 2400 return -1; 2401 } 2402 #if 0 2403 switch(value) { 2404 case UHF_C_PORT_CONNECTION: 2405 case UHF_C_PORT_ENABLE: 2406 case UHF_C_PORT_SUSPEND: 2407 case UHF_C_PORT_OVER_CURRENT: 2408 case UHF_C_PORT_RESET: 2409 default: 2410 break; 2411 } 2412 #endif 2413 break; 2414 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2415 if (len == 0) 2416 break; 2417 if ((value & 0xff) != 0) { 2418 return -1; 2419 } 2420 totlen = uimin(buflen, sizeof(hubd)); 2421 memcpy(&hubd, buf, totlen); 2422 hubd.bNbrPorts = sc->sc_noport; 2423 v = EOREAD4(sc, EHCI_HCSPARAMS); 2424 USETW(hubd.wHubCharacteristics, 2425 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2426 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2427 ? UHD_PORT_IND : 0); 2428 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2429 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2430 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2431 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2432 totlen = uimin(totlen, hubd.bDescLength); 2433 memcpy(buf, &hubd, totlen); 2434 break; 2435 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2436 if (len != 4) { 2437 return -1; 2438 } 2439 memset(buf, 0, len); /* ? XXX */ 2440 totlen = len; 2441 break; 2442 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2443 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2444 if (index < 1 || index > sc->sc_noport) { 2445 return -1; 2446 } 2447 if (len != 4) { 2448 return -1; 2449 } 2450 v = EOREAD4(sc, EHCI_PORTSC(index)); 2451 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2452 2453 i = UPS_HIGH_SPEED; 2454 if (sc->sc_flags & EHCIF_ETTF) { 2455 /* 2456 * If we are doing embedded transaction translation, 2457 * then directly attached LS/FS devices are reset by 2458 * the EHCI controller itself. PSPD is encoded 2459 * the same way as in USBSTATUS. 2460 */ 2461 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2462 } 2463 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2464 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2465 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2466 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2467 if (v & EHCI_PS_PR) i |= UPS_RESET; 2468 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2469 if (sc->sc_vendor_port_status) 2470 i = sc->sc_vendor_port_status(sc, v, i); 2471 USETW(ps.wPortStatus, i); 2472 i = 0; 2473 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2474 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2475 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2476 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2477 USETW(ps.wPortChange, i); 2478 totlen = uimin(len, sizeof(ps)); 2479 memcpy(buf, &ps, totlen); 2480 break; 2481 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2482 return -1; 2483 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2484 break; 2485 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2486 if (index < 1 || index > sc->sc_noport) { 2487 return -1; 2488 } 2489 port = EHCI_PORTSC(index); 2490 v = EOREAD4(sc, port); 2491 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2492 v &= ~EHCI_PS_CLEAR; 2493 switch(value) { 2494 case UHF_PORT_ENABLE: 2495 EOWRITE4(sc, port, v | EHCI_PS_PE); 2496 break; 2497 case UHF_PORT_SUSPEND: 2498 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2499 break; 2500 case UHF_PORT_RESET: 2501 DPRINTF("reset port %jd", index, 0, 0, 0); 2502 if (EHCI_PS_IS_LOWSPEED(v) 2503 && sc->sc_ncomp > 0 2504 && !(sc->sc_flags & EHCIF_ETTF)) { 2505 /* 2506 * Low speed device on non-ETTF controller or 2507 * unaccompanied controller, give up ownership. 2508 */ 2509 ehci_disown(sc, index, 1); 2510 break; 2511 } 2512 /* Start reset sequence. */ 2513 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2514 EOWRITE4(sc, port, v | EHCI_PS_PR); 2515 /* Wait for reset to complete. */ 2516 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2517 if (sc->sc_dying) { 2518 return -1; 2519 } 2520 /* 2521 * An embedded transaction translator will automatically 2522 * terminate the reset sequence so there's no need to 2523 * it. 2524 */ 2525 v = EOREAD4(sc, port); 2526 if (v & EHCI_PS_PR) { 2527 /* Terminate reset sequence. */ 2528 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2529 /* Wait for HC to complete reset. */ 2530 usb_delay_ms(&sc->sc_bus, 2531 EHCI_PORT_RESET_COMPLETE); 2532 if (sc->sc_dying) { 2533 return -1; 2534 } 2535 } 2536 2537 v = EOREAD4(sc, port); 2538 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2539 if (v & EHCI_PS_PR) { 2540 printf("%s: port reset timeout\n", 2541 device_xname(sc->sc_dev)); 2542 return USBD_TIMEOUT; 2543 } 2544 if (!(v & EHCI_PS_PE)) { 2545 /* Not a high speed device, give up ownership.*/ 2546 ehci_disown(sc, index, 0); 2547 break; 2548 } 2549 sc->sc_isreset[index] = 1; 2550 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2551 v, 0, 0); 2552 break; 2553 case UHF_PORT_POWER: 2554 DPRINTF("set port power %jd (has PPC = %jd)", index, 2555 sc->sc_hasppc, 0, 0); 2556 if (sc->sc_hasppc) 2557 EOWRITE4(sc, port, v | EHCI_PS_PP); 2558 break; 2559 case UHF_PORT_TEST: 2560 DPRINTF("set port test %jd", index, 0, 0, 0); 2561 break; 2562 case UHF_PORT_INDICATOR: 2563 DPRINTF("set port ind %jd", index, 0, 0, 0); 2564 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2565 break; 2566 default: 2567 return -1; 2568 } 2569 break; 2570 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2571 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2572 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2573 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2574 break; 2575 default: 2576 /* default from usbroothub */ 2577 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2578 2579 return buflen; 2580 } 2581 2582 DPRINTF("returning %jd", totlen, 0, 0, 0); 2583 2584 return totlen; 2585 } 2586 2587 Static void 2588 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2589 { 2590 int port; 2591 uint32_t v; 2592 2593 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2594 2595 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2596 #ifdef DIAGNOSTIC 2597 if (sc->sc_npcomp != 0) { 2598 int i = (index-1) / sc->sc_npcomp; 2599 if (i >= sc->sc_ncomp) 2600 printf("%s: strange port\n", 2601 device_xname(sc->sc_dev)); 2602 else 2603 printf("%s: handing over %s speed device on " 2604 "port %d to %s\n", 2605 device_xname(sc->sc_dev), 2606 lowspeed ? "low" : "full", 2607 index, sc->sc_comps[i] ? 2608 device_xname(sc->sc_comps[i]) : 2609 "companion controller"); 2610 } else { 2611 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2612 } 2613 #endif 2614 port = EHCI_PORTSC(index); 2615 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2616 EOWRITE4(sc, port, v | EHCI_PS_PO); 2617 } 2618 2619 Static usbd_status 2620 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2621 { 2622 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2623 usbd_status err; 2624 2625 /* Insert last in queue. */ 2626 mutex_enter(&sc->sc_lock); 2627 err = usb_insert_transfer(xfer); 2628 mutex_exit(&sc->sc_lock); 2629 if (err) 2630 return err; 2631 2632 /* Pipe isn't running, start first */ 2633 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2634 } 2635 2636 Static usbd_status 2637 ehci_root_intr_start(struct usbd_xfer *xfer) 2638 { 2639 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2640 2641 if (sc->sc_dying) 2642 return USBD_IOERROR; 2643 2644 mutex_enter(&sc->sc_lock); 2645 sc->sc_intrxfer = xfer; 2646 mutex_exit(&sc->sc_lock); 2647 2648 return USBD_IN_PROGRESS; 2649 } 2650 2651 /* Abort a root interrupt request. */ 2652 Static void 2653 ehci_root_intr_abort(struct usbd_xfer *xfer) 2654 { 2655 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2656 2657 KASSERT(mutex_owned(&sc->sc_lock)); 2658 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2659 2660 sc->sc_intrxfer = NULL; 2661 2662 xfer->ux_status = USBD_CANCELLED; 2663 usb_transfer_complete(xfer); 2664 } 2665 2666 /* Close the root pipe. */ 2667 Static void 2668 ehci_root_intr_close(struct usbd_pipe *pipe) 2669 { 2670 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2671 2672 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2673 2674 KASSERT(mutex_owned(&sc->sc_lock)); 2675 2676 sc->sc_intrxfer = NULL; 2677 } 2678 2679 Static void 2680 ehci_root_intr_done(struct usbd_xfer *xfer) 2681 { 2682 } 2683 2684 /************************/ 2685 2686 Static ehci_soft_qh_t * 2687 ehci_alloc_sqh(ehci_softc_t *sc) 2688 { 2689 ehci_soft_qh_t *sqh; 2690 usbd_status err; 2691 int i, offs; 2692 usb_dma_t dma; 2693 2694 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2695 2696 mutex_enter(&sc->sc_lock); 2697 if (sc->sc_freeqhs == NULL) { 2698 DPRINTF("allocating chunk", 0, 0, 0, 0); 2699 mutex_exit(&sc->sc_lock); 2700 2701 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2702 EHCI_PAGE_SIZE, &dma); 2703 #ifdef EHCI_DEBUG 2704 if (err) 2705 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2706 #endif 2707 if (err) 2708 return NULL; 2709 2710 mutex_enter(&sc->sc_lock); 2711 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2712 offs = i * EHCI_SQH_SIZE; 2713 sqh = KERNADDR(&dma, offs); 2714 sqh->physaddr = DMAADDR(&dma, offs); 2715 sqh->dma = dma; 2716 sqh->offs = offs; 2717 sqh->next = sc->sc_freeqhs; 2718 sc->sc_freeqhs = sqh; 2719 } 2720 } 2721 sqh = sc->sc_freeqhs; 2722 sc->sc_freeqhs = sqh->next; 2723 mutex_exit(&sc->sc_lock); 2724 2725 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2726 sqh->next = NULL; 2727 return sqh; 2728 } 2729 2730 Static void 2731 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2732 { 2733 KASSERT(mutex_owned(&sc->sc_lock)); 2734 2735 sqh->next = sc->sc_freeqhs; 2736 sc->sc_freeqhs = sqh; 2737 } 2738 2739 Static ehci_soft_qtd_t * 2740 ehci_alloc_sqtd(ehci_softc_t *sc) 2741 { 2742 ehci_soft_qtd_t *sqtd = NULL; 2743 usbd_status err; 2744 int i, offs; 2745 usb_dma_t dma; 2746 2747 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2748 2749 mutex_enter(&sc->sc_lock); 2750 if (sc->sc_freeqtds == NULL) { 2751 DPRINTF("allocating chunk", 0, 0, 0, 0); 2752 mutex_exit(&sc->sc_lock); 2753 2754 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2755 EHCI_PAGE_SIZE, &dma); 2756 #ifdef EHCI_DEBUG 2757 if (err) 2758 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2759 #endif 2760 if (err) 2761 goto done; 2762 2763 mutex_enter(&sc->sc_lock); 2764 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2765 offs = i * EHCI_SQTD_SIZE; 2766 sqtd = KERNADDR(&dma, offs); 2767 sqtd->physaddr = DMAADDR(&dma, offs); 2768 sqtd->dma = dma; 2769 sqtd->offs = offs; 2770 2771 sqtd->nextqtd = sc->sc_freeqtds; 2772 sc->sc_freeqtds = sqtd; 2773 } 2774 } 2775 2776 sqtd = sc->sc_freeqtds; 2777 sc->sc_freeqtds = sqtd->nextqtd; 2778 mutex_exit(&sc->sc_lock); 2779 2780 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2781 sqtd->nextqtd = NULL; 2782 sqtd->xfer = NULL; 2783 2784 done: 2785 return sqtd; 2786 } 2787 2788 Static void 2789 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2790 { 2791 2792 mutex_enter(&sc->sc_lock); 2793 sqtd->nextqtd = sc->sc_freeqtds; 2794 sc->sc_freeqtds = sqtd; 2795 mutex_exit(&sc->sc_lock); 2796 } 2797 2798 Static int 2799 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2800 int alen, int rd, ehci_soft_qtd_t **sp) 2801 { 2802 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2803 uint16_t flags = xfer->ux_flags; 2804 2805 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2806 2807 ASSERT_SLEEPABLE(); 2808 KASSERT(sp); 2809 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2810 2811 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2812 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2813 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2814 KM_SLEEP); 2815 exfer->ex_nsqtd = nsqtd; 2816 2817 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2818 alen, nsqtd, flags); 2819 2820 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2821 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2822 if (cur == NULL) 2823 goto nomem; 2824 exfer->ex_sqtds[j++] = cur; 2825 2826 cur->xfer = xfer; 2827 cur->len = 0; 2828 2829 } 2830 2831 *sp = exfer->ex_sqtds[0]; 2832 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2833 2834 return 0; 2835 2836 nomem: 2837 ehci_free_sqtds(sc, exfer); 2838 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2839 DPRINTF("no memory", 0, 0, 0, 0); 2840 return ENOMEM; 2841 } 2842 2843 Static void 2844 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2845 { 2846 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2847 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2848 2849 mutex_enter(&sc->sc_lock); 2850 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2851 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2852 2853 if (sqtd == NULL) 2854 break; 2855 2856 sqtd->nextqtd = sc->sc_freeqtds; 2857 sc->sc_freeqtds = sqtd; 2858 } 2859 mutex_exit(&sc->sc_lock); 2860 } 2861 2862 Static void 2863 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2864 { 2865 if (prev) { 2866 prev->nextqtd = sqtd; 2867 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2868 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2869 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2870 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2871 } 2872 } 2873 2874 Static void 2875 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2876 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2877 { 2878 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2879 usb_dma_t *dma = &xfer->ux_dmabuf; 2880 uint16_t flags = xfer->ux_flags; 2881 ehci_soft_qtd_t *sqtd, *prev; 2882 int tog = *toggle; 2883 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2884 int len = length; 2885 2886 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2887 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2888 len, isread, tog); 2889 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2890 0, 0, 0); 2891 2892 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2893 2894 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2895 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2896 EHCI_QTD_SET_CERR(3) 2897 ; 2898 2899 sqtd = prev = NULL; 2900 size_t curoffs = 0; 2901 size_t j = 0; 2902 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2903 sqtd = exfer->ex_sqtds[j++]; 2904 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 2905 (uintptr_t)prev, 0); 2906 2907 /* 2908 * The EHCI hardware can handle at most 5 pages and they do 2909 * not have to be contiguous 2910 */ 2911 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2912 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2913 size_t curlen = len; 2914 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2915 /* must use multiple TDs, fill as much as possible. */ 2916 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2917 2918 /* the length must be a multiple of the max size */ 2919 curlen -= curlen % mps; 2920 } 2921 KASSERT(curlen != 0); 2922 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 2923 curoffs, 0); 2924 2925 /* Fill the qTD */ 2926 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2927 sqtd->qtd.qtd_status = htole32( 2928 qtdstatus | 2929 EHCI_QTD_SET_BYTES(curlen) | 2930 EHCI_QTD_SET_TOGGLE(tog)); 2931 2932 /* Find number of pages we'll be using, insert dma addresses */ 2933 size_t pages = EHCI_NPAGES(curlen); 2934 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2935 size_t pageoffs = EHCI_PAGE(curoffs); 2936 for (size_t i = 0; i < pages; i++) { 2937 paddr_t a = DMAADDR(dma, 2938 pageoffs + i * EHCI_PAGE_SIZE); 2939 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2940 /* Cast up to avoid compiler warnings */ 2941 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2942 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 2943 i, pages, 2944 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2945 le32toh(sqtd->qtd.qtd_buffer[i])); 2946 } 2947 /* First buffer pointer requires a page offset to start at */ 2948 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2949 2950 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2951 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2952 2953 sqtd->len = curlen; 2954 2955 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 2956 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2957 2958 ehci_append_sqtd(sqtd, prev); 2959 2960 if (((curlen + mps - 1) / mps) & 1) { 2961 tog ^= 1; 2962 } 2963 2964 curoffs += curlen; 2965 len -= curlen; 2966 } 2967 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2968 xfer, length, len, mps, exfer->ex_nsqtd, j); 2969 2970 if (!isread && 2971 (flags & USBD_FORCE_SHORT_XFER) && 2972 length % mps == 0) { 2973 /* Force a 0 length transfer at the end. */ 2974 2975 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2976 exfer->ex_nsqtd); 2977 prev = sqtd; 2978 sqtd = exfer->ex_sqtds[j++]; 2979 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 2980 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2981 sqtd->qtd.qtd_status = htole32( 2982 qtdstatus | 2983 EHCI_QTD_SET_BYTES(0) | 2984 EHCI_QTD_SET_TOGGLE(tog)); 2985 2986 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2987 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2988 2989 ehci_append_sqtd(sqtd, prev); 2990 tog ^= 1; 2991 } 2992 2993 *lsqtd = sqtd; 2994 *toggle = tog; 2995 } 2996 2997 Static ehci_soft_itd_t * 2998 ehci_alloc_itd(ehci_softc_t *sc) 2999 { 3000 struct ehci_soft_itd *itd, *freeitd; 3001 usbd_status err; 3002 usb_dma_t dma; 3003 3004 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3005 3006 mutex_enter(&sc->sc_lock); 3007 3008 freeitd = LIST_FIRST(&sc->sc_freeitds); 3009 if (freeitd == NULL) { 3010 DPRINTF("allocating chunk", 0, 0, 0, 0); 3011 mutex_exit(&sc->sc_lock); 3012 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3013 EHCI_PAGE_SIZE, &dma); 3014 3015 if (err) { 3016 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3017 return NULL; 3018 } 3019 mutex_enter(&sc->sc_lock); 3020 3021 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3022 int offs = i * EHCI_ITD_SIZE; 3023 itd = KERNADDR(&dma, offs); 3024 itd->physaddr = DMAADDR(&dma, offs); 3025 itd->dma = dma; 3026 itd->offs = offs; 3027 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3028 } 3029 freeitd = LIST_FIRST(&sc->sc_freeitds); 3030 } 3031 3032 itd = freeitd; 3033 LIST_REMOVE(itd, free_list); 3034 mutex_exit(&sc->sc_lock); 3035 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3036 3037 itd->frame_list.next = NULL; 3038 itd->frame_list.prev = NULL; 3039 itd->xfer_next = NULL; 3040 itd->slot = 0; 3041 3042 return itd; 3043 } 3044 3045 Static ehci_soft_sitd_t * 3046 ehci_alloc_sitd(ehci_softc_t *sc) 3047 { 3048 struct ehci_soft_sitd *sitd, *freesitd; 3049 usbd_status err; 3050 int i, offs; 3051 usb_dma_t dma; 3052 3053 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3054 3055 mutex_enter(&sc->sc_lock); 3056 freesitd = LIST_FIRST(&sc->sc_freesitds); 3057 if (freesitd == NULL) { 3058 DPRINTF("allocating chunk", 0, 0, 0, 0); 3059 mutex_exit(&sc->sc_lock); 3060 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3061 EHCI_PAGE_SIZE, &dma); 3062 3063 if (err) { 3064 DPRINTF("alloc returned %jd", err, 0, 0, 3065 0); 3066 return NULL; 3067 } 3068 3069 mutex_enter(&sc->sc_lock); 3070 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3071 offs = i * EHCI_SITD_SIZE; 3072 sitd = KERNADDR(&dma, offs); 3073 sitd->physaddr = DMAADDR(&dma, offs); 3074 sitd->dma = dma; 3075 sitd->offs = offs; 3076 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3077 } 3078 freesitd = LIST_FIRST(&sc->sc_freesitds); 3079 } 3080 3081 sitd = freesitd; 3082 LIST_REMOVE(sitd, free_list); 3083 mutex_exit(&sc->sc_lock); 3084 3085 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3086 3087 sitd->frame_list.next = NULL; 3088 sitd->frame_list.prev = NULL; 3089 sitd->xfer_next = NULL; 3090 sitd->slot = 0; 3091 3092 return sitd; 3093 } 3094 3095 /****************/ 3096 3097 /* 3098 * Close a reqular pipe. 3099 * Assumes that there are no pending transactions. 3100 */ 3101 Static void 3102 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3103 { 3104 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3105 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3106 ehci_soft_qh_t *sqh = epipe->sqh; 3107 3108 KASSERT(mutex_owned(&sc->sc_lock)); 3109 3110 ehci_rem_qh(sc, sqh, head); 3111 ehci_free_sqh(sc, epipe->sqh); 3112 } 3113 3114 /* 3115 * Cancel or timeout a device request. We have two cases to deal with 3116 * 3117 * 1) A driver wants to stop scheduled or inflight transfers 3118 * 2) A transfer has timed out 3119 * 3120 * have (partially) happened since the hardware runs concurrently. 3121 * 3122 * Transfer state is protected by the bus lock and we set the transfer status 3123 * as soon as either of the above happens (with bus lock held). 3124 * 3125 * Then we arrange for the hardware to tells us that it is not still 3126 * processing the TDs by setting the QH halted bit and wait for the ehci 3127 * door bell 3128 */ 3129 Static void 3130 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3131 { 3132 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3133 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3134 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3135 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3136 ehci_soft_qh_t *sqh = epipe->sqh; 3137 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3138 ehci_physaddr_t cur; 3139 uint32_t qhstatus; 3140 int hit; 3141 3142 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 3143 "invalid status for abort: %d", (int)status); 3144 3145 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3146 3147 KASSERT(mutex_owned(&sc->sc_lock)); 3148 ASSERT_SLEEPABLE(); 3149 3150 if (status == USBD_CANCELLED) { 3151 /* 3152 * We are synchronously aborting. Try to stop the 3153 * callout and task, but if we can't, wait for them to 3154 * complete. 3155 */ 3156 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3157 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 3158 USB_TASKQ_HC, &sc->sc_lock); 3159 } else { 3160 /* Otherwise, we are timing out. */ 3161 KASSERT(status == USBD_TIMEOUT); 3162 } 3163 3164 /* 3165 * The xfer cannot have been cancelled already. It is the 3166 * responsibility of the caller of usbd_abort_pipe not to try 3167 * to abort a pipe multiple times, whether concurrently or 3168 * sequentially. 3169 */ 3170 KASSERT(xfer->ux_status != USBD_CANCELLED); 3171 3172 /* Only the timeout, which runs only once, can time it out. */ 3173 KASSERT(xfer->ux_status != USBD_TIMEOUT); 3174 3175 /* If anyone else beat us, we're done. */ 3176 if (xfer->ux_status != USBD_IN_PROGRESS) 3177 return; 3178 3179 /* We beat everyone else. Claim the status. */ 3180 xfer->ux_status = status; 3181 3182 /* 3183 * If we're dying, skip the hardware action and just notify the 3184 * software that we're done. 3185 */ 3186 if (sc->sc_dying) { 3187 goto dying; 3188 } 3189 3190 /* 3191 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3192 */ 3193 ehci_del_intr_list(sc, exfer); 3194 3195 usb_syncmem(&sqh->dma, 3196 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3197 sizeof(sqh->qh.qh_qtd.qtd_status), 3198 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3199 qhstatus = sqh->qh.qh_qtd.qtd_status; 3200 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3201 usb_syncmem(&sqh->dma, 3202 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3203 sizeof(sqh->qh.qh_qtd.qtd_status), 3204 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3205 3206 if (exfer->ex_type == EX_CTRL) { 3207 fsqtd = exfer->ex_setup; 3208 lsqtd = exfer->ex_status; 3209 } else { 3210 fsqtd = exfer->ex_sqtdstart; 3211 lsqtd = exfer->ex_sqtdend; 3212 } 3213 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3214 usb_syncmem(&sqtd->dma, 3215 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3216 sizeof(sqtd->qtd.qtd_status), 3217 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3218 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3219 usb_syncmem(&sqtd->dma, 3220 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3221 sizeof(sqtd->qtd.qtd_status), 3222 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3223 if (sqtd == lsqtd) 3224 break; 3225 } 3226 3227 /* 3228 * HC Step 2: Wait until we know hardware has finished any possible 3229 * use of the xfer. 3230 */ 3231 ehci_sync_hc(sc); 3232 3233 /* 3234 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3235 * The complication here is that the hardware may have executed 3236 * beyond the xfer we're trying to abort. So as we're scanning 3237 * the TDs of this xfer we check if the hardware points to 3238 * any of them. 3239 */ 3240 3241 usb_syncmem(&sqh->dma, 3242 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3243 sizeof(sqh->qh.qh_curqtd), 3244 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3245 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3246 hit = 0; 3247 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3248 hit |= cur == sqtd->physaddr; 3249 if (sqtd == lsqtd) 3250 break; 3251 } 3252 sqtd = sqtd->nextqtd; 3253 /* Zap curqtd register if hardware pointed inside the xfer. */ 3254 if (hit && sqtd != NULL) { 3255 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3256 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3257 usb_syncmem(&sqh->dma, 3258 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3259 sizeof(sqh->qh.qh_curqtd), 3260 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3261 sqh->qh.qh_qtd.qtd_status = qhstatus; 3262 usb_syncmem(&sqh->dma, 3263 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3264 sizeof(sqh->qh.qh_qtd.qtd_status), 3265 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3266 } else { 3267 DPRINTF("no hit", 0, 0, 0, 0); 3268 usb_syncmem(&sqh->dma, 3269 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3270 sizeof(sqh->qh.qh_curqtd), 3271 BUS_DMASYNC_PREREAD); 3272 } 3273 3274 /* 3275 * Final step: Notify completion to waiting xfers. 3276 */ 3277 dying: 3278 #ifdef DIAGNOSTIC 3279 exfer->ex_isdone = true; 3280 #endif 3281 usb_transfer_complete(xfer); 3282 DPRINTFN(14, "end", 0, 0, 0, 0); 3283 3284 KASSERT(mutex_owned(&sc->sc_lock)); 3285 } 3286 3287 Static void 3288 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3289 { 3290 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3291 ehci_isoc_trans_t trans_status; 3292 struct ehci_xfer *exfer; 3293 ehci_softc_t *sc; 3294 struct ehci_soft_itd *itd; 3295 struct ehci_soft_sitd *sitd; 3296 int i; 3297 3298 KASSERTMSG(status == USBD_CANCELLED, 3299 "invalid status for abort: %d", (int)status); 3300 3301 exfer = EHCI_XFER2EXFER(xfer); 3302 sc = EHCI_XFER2SC(xfer); 3303 3304 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3305 (uintptr_t)xfer->ux_pipe, 0, 0); 3306 3307 KASSERT(mutex_owned(&sc->sc_lock)); 3308 ASSERT_SLEEPABLE(); 3309 3310 /* No timeout or task here. */ 3311 3312 /* 3313 * The xfer cannot have been cancelled already. It is the 3314 * responsibility of the caller of usbd_abort_pipe not to try 3315 * to abort a pipe multiple times, whether concurrently or 3316 * sequentially. 3317 */ 3318 KASSERT(xfer->ux_status != USBD_CANCELLED); 3319 3320 /* If anyone else beat us, we're done. */ 3321 if (xfer->ux_status != USBD_IN_PROGRESS) 3322 return; 3323 3324 /* We beat everyone else. Claim the status. */ 3325 xfer->ux_status = status; 3326 3327 /* 3328 * If we're dying, skip the hardware action and just notify the 3329 * software that we're done. 3330 */ 3331 if (sc->sc_dying) { 3332 goto dying; 3333 } 3334 3335 /* 3336 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3337 */ 3338 ehci_del_intr_list(sc, exfer); 3339 3340 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3341 for (itd = exfer->ex_itdstart; itd != NULL; 3342 itd = itd->xfer_next) { 3343 usb_syncmem(&itd->dma, 3344 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3345 sizeof(itd->itd.itd_ctl), 3346 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3347 3348 for (i = 0; i < 8; i++) { 3349 trans_status = le32toh(itd->itd.itd_ctl[i]); 3350 trans_status &= ~EHCI_ITD_ACTIVE; 3351 itd->itd.itd_ctl[i] = htole32(trans_status); 3352 } 3353 3354 usb_syncmem(&itd->dma, 3355 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3356 sizeof(itd->itd.itd_ctl), 3357 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3358 } 3359 } else { 3360 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3361 sitd = sitd->xfer_next) { 3362 usb_syncmem(&sitd->dma, 3363 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3364 sizeof(sitd->sitd.sitd_buffer), 3365 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3366 3367 trans_status = le32toh(sitd->sitd.sitd_trans); 3368 trans_status &= ~EHCI_SITD_ACTIVE; 3369 sitd->sitd.sitd_trans = htole32(trans_status); 3370 3371 usb_syncmem(&sitd->dma, 3372 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3373 sizeof(sitd->sitd.sitd_buffer), 3374 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3375 } 3376 } 3377 3378 dying: 3379 #ifdef DIAGNOSTIC 3380 exfer->ex_isdone = true; 3381 #endif 3382 usb_transfer_complete(xfer); 3383 DPRINTFN(14, "end", 0, 0, 0, 0); 3384 3385 KASSERT(mutex_owned(&sc->sc_lock)); 3386 } 3387 3388 Static void 3389 ehci_timeout(void *addr) 3390 { 3391 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3392 struct usbd_xfer *xfer = addr; 3393 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3394 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3395 3396 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3397 #ifdef EHCI_DEBUG 3398 if (ehcidebug >= 2) { 3399 struct usbd_pipe *pipe = xfer->ux_pipe; 3400 usbd_dump_pipe(pipe); 3401 } 3402 #endif 3403 3404 mutex_enter(&sc->sc_lock); 3405 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 3406 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3407 mutex_exit(&sc->sc_lock); 3408 } 3409 3410 Static void 3411 ehci_timeout_task(void *addr) 3412 { 3413 struct usbd_xfer *xfer = addr; 3414 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3415 3416 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3417 3418 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3419 3420 mutex_enter(&sc->sc_lock); 3421 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3422 mutex_exit(&sc->sc_lock); 3423 } 3424 3425 /************************/ 3426 3427 Static int 3428 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3429 { 3430 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3431 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3432 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3433 usb_device_request_t *req = &xfer->ux_request; 3434 ehci_soft_qtd_t *setup, *status, *next; 3435 int isread = req->bmRequestType & UT_READ; 3436 int len = xfer->ux_bufsize; 3437 int err; 3438 3439 exfer->ex_type = EX_CTRL; 3440 exfer->ex_status = NULL; 3441 exfer->ex_data = NULL; 3442 exfer->ex_setup = ehci_alloc_sqtd(sc); 3443 if (exfer->ex_setup == NULL) { 3444 err = ENOMEM; 3445 goto bad1; 3446 } 3447 exfer->ex_status = ehci_alloc_sqtd(sc); 3448 if (exfer->ex_status == NULL) { 3449 err = ENOMEM; 3450 goto bad2; 3451 } 3452 setup = exfer->ex_setup; 3453 status = exfer->ex_status; 3454 exfer->ex_nsqtd = 0; 3455 next = status; 3456 /* Set up data transaction */ 3457 if (len != 0) { 3458 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3459 &exfer->ex_data); 3460 if (err) 3461 goto bad3; 3462 next = exfer->ex_data; 3463 } 3464 3465 /* Clear toggle */ 3466 setup->qtd.qtd_status = htole32( 3467 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3468 EHCI_QTD_SET_TOGGLE(0) | 3469 EHCI_QTD_SET_BYTES(sizeof(*req)) 3470 ); 3471 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3472 setup->qtd.qtd_buffer_hi[0] = 0; 3473 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3474 setup->nextqtd = next; 3475 setup->xfer = xfer; 3476 setup->len = sizeof(*req); 3477 3478 status->qtd.qtd_status = htole32( 3479 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3480 EHCI_QTD_SET_TOGGLE(1) | 3481 EHCI_QTD_IOC 3482 ); 3483 status->qtd.qtd_buffer[0] = 0; 3484 status->qtd.qtd_buffer_hi[0] = 0; 3485 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3486 status->nextqtd = NULL; 3487 status->xfer = xfer; 3488 status->len = 0; 3489 3490 return 0; 3491 bad3: 3492 ehci_free_sqtd(sc, exfer->ex_status); 3493 bad2: 3494 ehci_free_sqtd(sc, exfer->ex_setup); 3495 bad1: 3496 return err; 3497 } 3498 3499 Static void 3500 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3501 { 3502 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3503 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3504 3505 KASSERT(ex->ex_type == EX_CTRL); 3506 3507 ehci_free_sqtd(sc, ex->ex_setup); 3508 ehci_free_sqtd(sc, ex->ex_status); 3509 ehci_free_sqtds(sc, ex); 3510 if (ex->ex_nsqtd) 3511 kmem_free(ex->ex_sqtds, 3512 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3513 } 3514 3515 Static usbd_status 3516 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3517 { 3518 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3519 usbd_status err; 3520 3521 /* Insert last in queue. */ 3522 mutex_enter(&sc->sc_lock); 3523 err = usb_insert_transfer(xfer); 3524 mutex_exit(&sc->sc_lock); 3525 if (err) 3526 return err; 3527 3528 /* Pipe isn't running, start first */ 3529 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3530 } 3531 3532 Static usbd_status 3533 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3534 { 3535 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3536 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3537 usb_device_request_t *req = &xfer->ux_request; 3538 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3539 ehci_soft_qtd_t *setup, *status, *next; 3540 ehci_soft_qh_t *sqh; 3541 3542 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3543 3544 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3545 3546 if (sc->sc_dying) 3547 return USBD_IOERROR; 3548 3549 const int isread = req->bmRequestType & UT_READ; 3550 const int len = UGETW(req->wLength); 3551 3552 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3553 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3554 UGETW(req->wIndex)); 3555 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3556 len, epipe->pipe.up_dev->ud_addr, 3557 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3558 3559 sqh = epipe->sqh; 3560 3561 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3562 "address QH %" __PRIuBIT " pipe %d\n", 3563 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3564 epipe->pipe.up_dev->ud_addr); 3565 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3566 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3567 "MPS QH %" __PRIuBIT " pipe %d\n", 3568 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3569 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3570 3571 setup = exfer->ex_setup; 3572 status = exfer->ex_status; 3573 3574 DPRINTF("setup %#jx status %#jx data %#jx", 3575 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3576 KASSERTMSG(setup != NULL && status != NULL, 3577 "Failed memory allocation, setup %p status %p", 3578 setup, status); 3579 3580 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3581 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3582 3583 /* Clear toggle */ 3584 setup->qtd.qtd_status &= ~htole32( 3585 EHCI_QTD_STATUS_MASK | 3586 EHCI_QTD_BYTES_MASK | 3587 EHCI_QTD_TOGGLE_MASK | 3588 EHCI_QTD_CERR_MASK 3589 ); 3590 setup->qtd.qtd_status |= htole32( 3591 EHCI_QTD_ACTIVE | 3592 EHCI_QTD_SET_CERR(3) | 3593 EHCI_QTD_SET_TOGGLE(0) | 3594 EHCI_QTD_SET_BYTES(sizeof(*req)) 3595 ); 3596 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3597 setup->qtd.qtd_buffer_hi[0] = 0; 3598 3599 next = status; 3600 status->qtd.qtd_status &= ~htole32( 3601 EHCI_QTD_STATUS_MASK | 3602 EHCI_QTD_PID_MASK | 3603 EHCI_QTD_BYTES_MASK | 3604 EHCI_QTD_TOGGLE_MASK | 3605 EHCI_QTD_CERR_MASK 3606 ); 3607 status->qtd.qtd_status |= htole32( 3608 EHCI_QTD_ACTIVE | 3609 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3610 EHCI_QTD_SET_CERR(3) | 3611 EHCI_QTD_SET_TOGGLE(1) | 3612 EHCI_QTD_SET_BYTES(0) | 3613 EHCI_QTD_IOC 3614 ); 3615 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3616 3617 KASSERT(exfer->ex_isdone); 3618 #ifdef DIAGNOSTIC 3619 exfer->ex_isdone = false; 3620 #endif 3621 3622 /* Set up data transaction */ 3623 if (len != 0) { 3624 ehci_soft_qtd_t *end; 3625 3626 /* Start toggle at 1. */ 3627 int toggle = 1; 3628 next = exfer->ex_data; 3629 KASSERTMSG(next != NULL, "Failed memory allocation"); 3630 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3631 end->nextqtd = status; 3632 end->qtd.qtd_next = end->qtd.qtd_altnext = 3633 htole32(status->physaddr); 3634 3635 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3636 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3637 3638 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3639 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3640 } 3641 3642 setup->nextqtd = next; 3643 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3644 3645 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3646 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3647 3648 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3649 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3650 3651 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3652 3653 #ifdef EHCI_DEBUG 3654 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3655 ehci_dump_sqh(sqh); 3656 ehci_dump_sqtds(setup); 3657 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3658 #endif 3659 3660 mutex_enter(&sc->sc_lock); 3661 3662 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3663 ehci_set_qh_qtd(sqh, setup); 3664 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3665 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3666 ehci_timeout, xfer); 3667 } 3668 ehci_add_intr_list(sc, exfer); 3669 xfer->ux_status = USBD_IN_PROGRESS; 3670 mutex_exit(&sc->sc_lock); 3671 3672 #if 0 3673 #ifdef EHCI_DEBUG 3674 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3675 // delay(10000); 3676 ehci_dump_regs(sc); 3677 ehci_dump_sqh(sc->sc_async_head); 3678 ehci_dump_sqh(sqh); 3679 ehci_dump_sqtds(setup); 3680 #endif 3681 #endif 3682 3683 return USBD_IN_PROGRESS; 3684 } 3685 3686 Static void 3687 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3688 { 3689 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3690 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3691 usb_device_request_t *req = &xfer->ux_request; 3692 int len = UGETW(req->wLength); 3693 int rd = req->bmRequestType & UT_READ; 3694 3695 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3696 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3697 3698 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3699 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3700 3701 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3702 BUS_DMASYNC_POSTWRITE); 3703 if (len) 3704 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3705 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3706 3707 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3708 } 3709 3710 /* Abort a device control request. */ 3711 Static void 3712 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3713 { 3714 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3715 3716 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3717 ehci_abort_xfer(xfer, USBD_CANCELLED); 3718 } 3719 3720 /* Close a device control pipe. */ 3721 Static void 3722 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3723 { 3724 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3725 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3726 3727 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3728 3729 KASSERT(mutex_owned(&sc->sc_lock)); 3730 3731 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3732 3733 ehci_close_pipe(pipe, sc->sc_async_head); 3734 } 3735 3736 /* 3737 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3738 * qTD status, or miss signalling occasionally under heavy load. If the host 3739 * machine is too fast, we we can miss transaction completion - when we scan 3740 * the active list the transaction still seems to be active. This generally 3741 * exhibits itself as a umass stall that never recovers. 3742 * 3743 * We work around this behaviour by setting up this callback after any softintr 3744 * that completes with transactions still pending, giving us another chance to 3745 * check for completion after the writeback has taken place. 3746 */ 3747 Static void 3748 ehci_intrlist_timeout(void *arg) 3749 { 3750 ehci_softc_t *sc = arg; 3751 3752 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3753 3754 usb_schedsoftintr(&sc->sc_bus); 3755 } 3756 3757 /************************/ 3758 3759 Static int 3760 ehci_device_bulk_init(struct usbd_xfer *xfer) 3761 { 3762 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3763 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3764 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3765 int endpt = ed->bEndpointAddress; 3766 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3767 int len = xfer->ux_bufsize; 3768 int err = 0; 3769 3770 exfer->ex_type = EX_BULK; 3771 exfer->ex_nsqtd = 0; 3772 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3773 &exfer->ex_sqtdstart); 3774 3775 return err; 3776 } 3777 3778 Static void 3779 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3780 { 3781 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3782 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3783 3784 KASSERT(ex->ex_type == EX_BULK); 3785 3786 ehci_free_sqtds(sc, ex); 3787 if (ex->ex_nsqtd) 3788 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3789 } 3790 3791 Static usbd_status 3792 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3793 { 3794 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3795 usbd_status err; 3796 3797 /* Insert last in queue. */ 3798 mutex_enter(&sc->sc_lock); 3799 err = usb_insert_transfer(xfer); 3800 mutex_exit(&sc->sc_lock); 3801 if (err) 3802 return err; 3803 3804 /* Pipe isn't running, start first */ 3805 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3806 } 3807 3808 Static usbd_status 3809 ehci_device_bulk_start(struct usbd_xfer *xfer) 3810 { 3811 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3812 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3813 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3814 ehci_soft_qh_t *sqh; 3815 ehci_soft_qtd_t *end; 3816 int len, isread, endpt; 3817 3818 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3819 3820 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3821 xfer->ux_flags, 0); 3822 3823 if (sc->sc_dying) 3824 return USBD_IOERROR; 3825 3826 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3827 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3828 3829 len = xfer->ux_length; 3830 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3831 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3832 sqh = epipe->sqh; 3833 3834 KASSERT(exfer->ex_isdone); 3835 #ifdef DIAGNOSTIC 3836 exfer->ex_isdone = false; 3837 #endif 3838 3839 /* Take lock here to protect nexttoggle */ 3840 mutex_enter(&sc->sc_lock); 3841 3842 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3843 3844 exfer->ex_sqtdend = end; 3845 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3846 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3847 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3848 3849 #ifdef EHCI_DEBUG 3850 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3851 ehci_dump_sqh(sqh); 3852 ehci_dump_sqtds(exfer->ex_sqtdstart); 3853 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3854 #endif 3855 3856 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3857 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3858 3859 /* also does usb_syncmem(sqh) */ 3860 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3861 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3862 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3863 ehci_timeout, xfer); 3864 } 3865 ehci_add_intr_list(sc, exfer); 3866 xfer->ux_status = USBD_IN_PROGRESS; 3867 mutex_exit(&sc->sc_lock); 3868 3869 #if 0 3870 #ifdef EHCI_DEBUG 3871 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3872 // delay(10000); 3873 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3874 ehci_dump_regs(sc); 3875 #if 0 3876 printf("async_head:\n"); 3877 ehci_dump_sqh(sc->sc_async_head); 3878 #endif 3879 DPRINTF("sqh:", 0, 0, 0, 0); 3880 ehci_dump_sqh(sqh); 3881 ehci_dump_sqtds(exfer->ex_sqtdstart); 3882 #endif 3883 #endif 3884 3885 return USBD_IN_PROGRESS; 3886 } 3887 3888 Static void 3889 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3890 { 3891 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3892 3893 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3894 ehci_abort_xfer(xfer, USBD_CANCELLED); 3895 } 3896 3897 /* 3898 * Close a device bulk pipe. 3899 */ 3900 Static void 3901 ehci_device_bulk_close(struct usbd_pipe *pipe) 3902 { 3903 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3904 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3905 3906 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3907 3908 KASSERT(mutex_owned(&sc->sc_lock)); 3909 3910 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3911 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3912 ehci_close_pipe(pipe, sc->sc_async_head); 3913 } 3914 3915 Static void 3916 ehci_device_bulk_done(struct usbd_xfer *xfer) 3917 { 3918 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3919 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3920 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3921 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3922 3923 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3924 3925 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 3926 3927 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3928 3929 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3930 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3931 3932 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3933 } 3934 3935 /************************/ 3936 3937 Static usbd_status 3938 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3939 { 3940 struct ehci_soft_islot *isp; 3941 int islot, lev; 3942 3943 /* Find a poll rate that is large enough. */ 3944 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3945 if (EHCI_ILEV_IVAL(lev) <= ival) 3946 break; 3947 3948 /* Pick an interrupt slot at the right level. */ 3949 /* XXX could do better than picking at random */ 3950 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3951 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3952 3953 sqh->islot = islot; 3954 isp = &sc->sc_islots[islot]; 3955 mutex_enter(&sc->sc_lock); 3956 ehci_add_qh(sc, sqh, isp->sqh); 3957 mutex_exit(&sc->sc_lock); 3958 3959 return USBD_NORMAL_COMPLETION; 3960 } 3961 3962 3963 Static int 3964 ehci_device_intr_init(struct usbd_xfer *xfer) 3965 { 3966 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3967 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3968 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3969 int endpt = ed->bEndpointAddress; 3970 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3971 int len = xfer->ux_bufsize; 3972 int err; 3973 3974 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3975 3976 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3977 xfer->ux_flags, 0); 3978 3979 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3980 KASSERT(len != 0); 3981 3982 exfer->ex_type = EX_INTR; 3983 exfer->ex_nsqtd = 0; 3984 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3985 &exfer->ex_sqtdstart); 3986 3987 return err; 3988 } 3989 3990 Static void 3991 ehci_device_intr_fini(struct usbd_xfer *xfer) 3992 { 3993 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3994 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3995 3996 KASSERT(ex->ex_type == EX_INTR); 3997 3998 ehci_free_sqtds(sc, ex); 3999 if (ex->ex_nsqtd) 4000 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4001 } 4002 4003 Static usbd_status 4004 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4005 { 4006 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4007 usbd_status err; 4008 4009 /* Insert last in queue. */ 4010 mutex_enter(&sc->sc_lock); 4011 err = usb_insert_transfer(xfer); 4012 mutex_exit(&sc->sc_lock); 4013 if (err) 4014 return err; 4015 4016 /* 4017 * Pipe isn't running (otherwise err would be USBD_INPROG), 4018 * so start it first. 4019 */ 4020 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4021 } 4022 4023 Static usbd_status 4024 ehci_device_intr_start(struct usbd_xfer *xfer) 4025 { 4026 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4027 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4028 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4029 ehci_soft_qtd_t *end; 4030 ehci_soft_qh_t *sqh; 4031 int len, isread, endpt; 4032 4033 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4034 4035 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4036 xfer->ux_flags, 0); 4037 4038 if (sc->sc_dying) 4039 return USBD_IOERROR; 4040 4041 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4042 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4043 4044 len = xfer->ux_length; 4045 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4046 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4047 sqh = epipe->sqh; 4048 4049 KASSERT(exfer->ex_isdone); 4050 #ifdef DIAGNOSTIC 4051 exfer->ex_isdone = false; 4052 #endif 4053 4054 /* Take lock to protect nexttoggle */ 4055 mutex_enter(&sc->sc_lock); 4056 4057 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4058 4059 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4060 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4061 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4062 exfer->ex_sqtdend = end; 4063 4064 #ifdef EHCI_DEBUG 4065 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4066 ehci_dump_sqh(sqh); 4067 ehci_dump_sqtds(exfer->ex_sqtdstart); 4068 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4069 #endif 4070 4071 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4072 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4073 4074 /* also does usb_syncmem(sqh) */ 4075 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4076 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4077 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4078 ehci_timeout, xfer); 4079 } 4080 ehci_add_intr_list(sc, exfer); 4081 xfer->ux_status = USBD_IN_PROGRESS; 4082 mutex_exit(&sc->sc_lock); 4083 4084 #if 0 4085 #ifdef EHCI_DEBUG 4086 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4087 // delay(10000); 4088 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4089 ehci_dump_regs(sc); 4090 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4091 ehci_dump_sqh(sqh); 4092 ehci_dump_sqtds(exfer->ex_sqtdstart); 4093 #endif 4094 #endif 4095 4096 return USBD_IN_PROGRESS; 4097 } 4098 4099 Static void 4100 ehci_device_intr_abort(struct usbd_xfer *xfer) 4101 { 4102 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4103 4104 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4105 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4106 4107 /* 4108 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4109 * async doorbell. That's dependent on the async list, wheras 4110 * intr xfers are periodic, should not use this? 4111 */ 4112 ehci_abort_xfer(xfer, USBD_CANCELLED); 4113 } 4114 4115 Static void 4116 ehci_device_intr_close(struct usbd_pipe *pipe) 4117 { 4118 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4119 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4120 struct ehci_soft_islot *isp; 4121 4122 KASSERT(mutex_owned(&sc->sc_lock)); 4123 4124 isp = &sc->sc_islots[epipe->sqh->islot]; 4125 ehci_close_pipe(pipe, isp->sqh); 4126 } 4127 4128 Static void 4129 ehci_device_intr_done(struct usbd_xfer *xfer) 4130 { 4131 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4132 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4133 int isread, endpt; 4134 4135 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4136 4137 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4138 4139 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4140 4141 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4142 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4143 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4144 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4145 } 4146 4147 /************************/ 4148 Static int 4149 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4150 { 4151 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4152 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4153 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4154 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4155 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4156 int i, k, frames; 4157 u_int huba, dir; 4158 int err; 4159 4160 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4161 4162 start = NULL; 4163 sitd = NULL; 4164 4165 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4166 xfer->ux_flags, 0); 4167 4168 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4169 KASSERT(xfer->ux_nframes != 0); 4170 KASSERT(exfer->ex_isdone); 4171 4172 exfer->ex_type = EX_FS_ISOC; 4173 /* 4174 * Step 1: Allocate and initialize sitds. 4175 */ 4176 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4177 if (i > 16 || i == 0) { 4178 /* Spec page 271 says intervals > 16 are invalid */ 4179 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4180 4181 return EINVAL; 4182 } 4183 4184 frames = xfer->ux_nframes; 4185 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4186 sitd = ehci_alloc_sitd(sc); 4187 if (sitd == NULL) { 4188 err = ENOMEM; 4189 goto fail; 4190 } 4191 4192 if (prev) 4193 prev->xfer_next = sitd; 4194 else 4195 start = sitd; 4196 4197 huba = dev->ud_myhsport->up_parent->ud_addr; 4198 4199 #if 0 4200 if (sc->sc_flags & EHCIF_FREESCALE) { 4201 // Set hub address to 0 if embedded TT is used. 4202 if (huba == sc->sc_addr) 4203 huba = 0; 4204 } 4205 #endif 4206 4207 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4208 dir = UE_GET_DIR(k) ? 1 : 0; 4209 sitd->sitd.sitd_endp = 4210 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4211 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4212 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4213 EHCI_SITD_SET_HUBA(huba) | 4214 EHCI_SITD_SET_DIR(dir)); 4215 4216 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4217 } /* End of frame */ 4218 4219 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4220 4221 stop = sitd; 4222 stop->xfer_next = NULL; 4223 exfer->ex_sitdstart = start; 4224 exfer->ex_sitdend = stop; 4225 4226 return 0; 4227 4228 fail: 4229 mutex_enter(&sc->sc_lock); 4230 ehci_soft_sitd_t *next; 4231 for (sitd = start; sitd; sitd = next) { 4232 next = sitd->xfer_next; 4233 ehci_free_sitd_locked(sc, sitd); 4234 } 4235 mutex_exit(&sc->sc_lock); 4236 4237 return err; 4238 } 4239 4240 Static void 4241 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4242 { 4243 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4244 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4245 4246 KASSERT(ex->ex_type == EX_FS_ISOC); 4247 4248 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4249 } 4250 4251 Static usbd_status 4252 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4253 { 4254 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4255 usbd_status __diagused err; 4256 4257 mutex_enter(&sc->sc_lock); 4258 err = usb_insert_transfer(xfer); 4259 mutex_exit(&sc->sc_lock); 4260 4261 KASSERT(err == USBD_NORMAL_COMPLETION); 4262 4263 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4264 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4265 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4266 ehci_soft_sitd_t *sitd; 4267 usb_dma_t *dma_buf; 4268 int i, j, k, frames; 4269 int offs, total_length; 4270 int frindex; 4271 u_int dir; 4272 4273 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4274 4275 sitd = NULL; 4276 total_length = 0; 4277 4278 4279 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4280 xfer->ux_flags, 0); 4281 4282 if (sc->sc_dying) 4283 return USBD_IOERROR; 4284 4285 /* 4286 * To avoid complication, don't allow a request right now that'll span 4287 * the entire frame table. To within 4 frames, to allow some leeway 4288 * on either side of where the hc currently is. 4289 */ 4290 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4291 xfer->ux_nframes >= sc->sc_flsize - 4) { 4292 printf("ehci: isoc descriptor requested that spans the entire" 4293 "frametable, too many frames\n"); 4294 return USBD_INVAL; 4295 } 4296 4297 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4298 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4299 KASSERT(exfer->ex_isdone); 4300 #ifdef DIAGNOSTIC 4301 exfer->ex_isdone = false; 4302 #endif 4303 4304 /* 4305 * Step 1: Initialize sitds. 4306 */ 4307 4308 frames = xfer->ux_nframes; 4309 dma_buf = &xfer->ux_dmabuf; 4310 offs = 0; 4311 4312 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4313 i++, sitd = sitd->xfer_next) { 4314 KASSERT(sitd != NULL); 4315 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4316 4317 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4318 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4319 4320 /* Set page0 index and offset - TP and T-offset are set below */ 4321 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4322 4323 total_length += xfer->ux_frlengths[i]; 4324 offs += xfer->ux_frlengths[i]; 4325 4326 sitd->sitd.sitd_buffer[1] = 4327 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4328 4329 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4330 4331 #if 0 4332 if (sc->sc_flags & EHCIF_FREESCALE) { 4333 // Set hub address to 0 if embedded TT is used. 4334 if (huba == sc->sc_addr) 4335 huba = 0; 4336 } 4337 #endif 4338 4339 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4340 dir = UE_GET_DIR(k) ? 1 : 0; 4341 KASSERT(sitd->sitd.sitd_endp == htole32( 4342 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4343 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4344 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4345 EHCI_SITD_SET_HUBA(huba) | 4346 EHCI_SITD_SET_DIR(dir))); 4347 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4348 4349 uint8_t sa = 0; 4350 uint8_t sb = 0; 4351 u_int temp, tlen; 4352 4353 if (dir == 0) { /* OUT */ 4354 temp = 0; 4355 tlen = xfer->ux_frlengths[i]; 4356 if (tlen <= 188) { 4357 temp |= 1; /* T-count = 1, TP = ALL */ 4358 tlen = 1; 4359 } else { 4360 tlen += 187; 4361 tlen /= 188; 4362 temp |= tlen; /* T-count = [1..6] */ 4363 temp |= 8; /* TP = Begin */ 4364 } 4365 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4366 4367 tlen += sa; 4368 4369 if (tlen >= 8) { 4370 sb = 0; 4371 } else { 4372 sb = (1 << tlen); 4373 } 4374 4375 sa = (1 << sa); 4376 sa = (sb - sa) & 0x3F; 4377 sb = 0; 4378 } else { 4379 sb = (-(4 << sa)) & 0xFE; 4380 sa = (1 << sa) & 0x3F; 4381 sa = 0x01; 4382 sb = 0xfc; 4383 } 4384 4385 sitd->sitd.sitd_sched = htole32( 4386 EHCI_SITD_SET_SMASK(sa) | 4387 EHCI_SITD_SET_CMASK(sb) 4388 ); 4389 4390 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4391 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4392 } /* End of frame */ 4393 4394 sitd = exfer->ex_sitdend; 4395 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4396 4397 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4398 sizeof(sitd->sitd.sitd_trans), 4399 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4400 4401 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4402 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4403 4404 /* 4405 * Part 2: Transfer descriptors have now been set up, now they must 4406 * be scheduled into the periodic frame list. Erk. Not wanting to 4407 * complicate matters, transfer is denied if the transfer spans 4408 * more than the period frame list. 4409 */ 4410 4411 mutex_enter(&sc->sc_lock); 4412 4413 /* Start inserting frames */ 4414 if (epipe->isoc.cur_xfers > 0) { 4415 frindex = epipe->isoc.next_frame; 4416 } else { 4417 frindex = EOREAD4(sc, EHCI_FRINDEX); 4418 frindex = frindex >> 3; /* Erase microframe index */ 4419 frindex += 2; 4420 } 4421 4422 if (frindex >= sc->sc_flsize) 4423 frindex &= (sc->sc_flsize - 1); 4424 4425 /* Whats the frame interval? */ 4426 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4427 4428 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4429 j++, sitd = sitd->xfer_next) { 4430 KASSERT(sitd); 4431 4432 usb_syncmem(&sc->sc_fldma, 4433 sizeof(ehci_link_t) * frindex, 4434 sizeof(ehci_link_t), 4435 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4436 4437 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4438 if (sitd->sitd.sitd_next == 0) 4439 /* 4440 * FIXME: frindex table gets initialized to NULL 4441 * or EHCI_NULL? 4442 */ 4443 sitd->sitd.sitd_next = EHCI_NULL; 4444 4445 usb_syncmem(&sitd->dma, 4446 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4447 sizeof(ehci_sitd_t), 4448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4449 4450 sc->sc_flist[frindex] = 4451 htole32(EHCI_LINK_SITD | sitd->physaddr); 4452 4453 usb_syncmem(&sc->sc_fldma, 4454 sizeof(ehci_link_t) * frindex, 4455 sizeof(ehci_link_t), 4456 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4457 4458 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4459 sc->sc_softsitds[frindex] = sitd; 4460 if (sitd->frame_list.next != NULL) 4461 sitd->frame_list.next->frame_list.prev = sitd; 4462 sitd->slot = frindex; 4463 sitd->frame_list.prev = NULL; 4464 4465 frindex += i; 4466 if (frindex >= sc->sc_flsize) 4467 frindex -= sc->sc_flsize; 4468 } 4469 4470 epipe->isoc.cur_xfers++; 4471 epipe->isoc.next_frame = frindex; 4472 4473 ehci_add_intr_list(sc, exfer); 4474 xfer->ux_status = USBD_IN_PROGRESS; 4475 mutex_exit(&sc->sc_lock); 4476 4477 return USBD_IN_PROGRESS; 4478 } 4479 4480 Static void 4481 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4482 { 4483 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4484 4485 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4486 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4487 } 4488 4489 Static void 4490 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4491 { 4492 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4493 4494 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4495 } 4496 4497 Static void 4498 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4499 { 4500 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4501 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4502 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4503 4504 KASSERT(mutex_owned(&sc->sc_lock)); 4505 4506 epipe->isoc.cur_xfers--; 4507 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4508 4509 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4510 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4511 } 4512 4513 4514 /************************/ 4515 4516 4517 Static int 4518 ehci_device_isoc_init(struct usbd_xfer *xfer) 4519 { 4520 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4521 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4522 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4523 ehci_soft_itd_t *itd, *prev, *start, *stop; 4524 int i, j, k; 4525 int frames, ufrperframe; 4526 int err; 4527 4528 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4529 4530 start = NULL; 4531 prev = NULL; 4532 itd = NULL; 4533 4534 KASSERT(xfer->ux_nframes != 0); 4535 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4536 KASSERT(exfer->ex_isdone); 4537 4538 exfer->ex_type = EX_ISOC; 4539 4540 /* 4541 * Step 1: Allocate and initialize itds, how many do we need? 4542 * One per transfer if interval >= 8 microframes, less if we use 4543 * multiple microframes per frame. 4544 */ 4545 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4546 if (i > 16 || i == 0) { 4547 /* Spec page 271 says intervals > 16 are invalid */ 4548 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4549 return USBD_INVAL; 4550 } 4551 4552 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4553 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4554 4555 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4556 itd = ehci_alloc_itd(sc); 4557 if (itd == NULL) { 4558 err = ENOMEM; 4559 goto fail; 4560 } 4561 4562 if (prev != NULL) { 4563 /* Maybe not as it's updated by the scheduling? */ 4564 prev->itd.itd_next = 4565 htole32(itd->physaddr | EHCI_LINK_ITD); 4566 4567 prev->xfer_next = itd; 4568 } else { 4569 start = itd; 4570 } 4571 4572 /* 4573 * Other special values 4574 */ 4575 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4576 itd->itd.itd_bufr[0] = htole32( 4577 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4578 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4579 4580 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4581 ? 1 : 0; 4582 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4583 itd->itd.itd_bufr[1] |= htole32( 4584 EHCI_ITD_SET_DIR(k) | 4585 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4586 4587 /* FIXME: handle invalid trans - should be done in openpipe */ 4588 itd->itd.itd_bufr[2] |= 4589 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4590 } /* End of frame */ 4591 4592 stop = itd; 4593 stop->xfer_next = NULL; 4594 4595 exfer->ex_itdstart = start; 4596 exfer->ex_itdend = stop; 4597 4598 return 0; 4599 fail: 4600 mutex_enter(&sc->sc_lock); 4601 ehci_soft_itd_t *next; 4602 for (itd = start; itd; itd = next) { 4603 next = itd->xfer_next; 4604 ehci_free_itd_locked(sc, itd); 4605 } 4606 mutex_exit(&sc->sc_lock); 4607 4608 return err; 4609 4610 } 4611 4612 Static void 4613 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4614 { 4615 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4616 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4617 4618 KASSERT(ex->ex_type == EX_ISOC); 4619 4620 ehci_free_itd_chain(sc, ex->ex_itdstart); 4621 } 4622 4623 Static usbd_status 4624 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4625 { 4626 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4627 usbd_status __diagused err; 4628 4629 mutex_enter(&sc->sc_lock); 4630 err = usb_insert_transfer(xfer); 4631 mutex_exit(&sc->sc_lock); 4632 4633 KASSERT(err == USBD_NORMAL_COMPLETION); 4634 4635 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4636 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4637 ehci_soft_itd_t *itd, *prev; 4638 usb_dma_t *dma_buf; 4639 int i, j; 4640 int frames, uframes, ufrperframe; 4641 int trans_count, offs, total_length; 4642 int frindex; 4643 4644 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4645 4646 prev = NULL; 4647 itd = NULL; 4648 trans_count = 0; 4649 total_length = 0; 4650 4651 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4652 4653 if (sc->sc_dying) 4654 return USBD_IOERROR; 4655 4656 /* 4657 * To avoid complication, don't allow a request right now that'll span 4658 * the entire frame table. To within 4 frames, to allow some leeway 4659 * on either side of where the hc currently is. 4660 */ 4661 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4662 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4663 DPRINTF( 4664 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4665 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4666 return USBD_INVAL; 4667 } 4668 4669 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4670 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4671 KASSERT(exfer->ex_isdone); 4672 #ifdef DIAGNOSTIC 4673 exfer->ex_isdone = false; 4674 #endif 4675 4676 /* 4677 * Step 1: Re-Initialize itds 4678 */ 4679 4680 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4681 if (i > 16 || i == 0) { 4682 /* Spec page 271 says intervals > 16 are invalid */ 4683 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4684 return USBD_INVAL; 4685 } 4686 4687 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4688 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4689 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4690 4691 if (frames == 0) { 4692 DPRINTF("frames == 0", 0, 0, 0, 0); 4693 return USBD_INVAL; 4694 } 4695 4696 dma_buf = &xfer->ux_dmabuf; 4697 offs = 0; 4698 4699 itd = exfer->ex_itdstart; 4700 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4701 int froffs = offs; 4702 4703 if (prev != NULL) { 4704 prev->itd.itd_next = 4705 htole32(itd->physaddr | EHCI_LINK_ITD); 4706 usb_syncmem(&prev->dma, 4707 prev->offs + offsetof(ehci_itd_t, itd_next), 4708 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4709 prev->xfer_next = itd; 4710 } 4711 4712 /* 4713 * Step 1.5, initialize uframes 4714 */ 4715 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4716 /* Calculate which page in the list this starts in */ 4717 int addr = DMAADDR(dma_buf, froffs); 4718 addr = EHCI_PAGE_OFFSET(addr); 4719 addr += (offs - froffs); 4720 addr = EHCI_PAGE(addr); 4721 addr /= EHCI_PAGE_SIZE; 4722 4723 /* 4724 * This gets the initial offset into the first page, 4725 * looks how far further along the current uframe 4726 * offset is. Works out how many pages that is. 4727 */ 4728 4729 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4730 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4731 EHCI_ITD_SET_PG(addr) | 4732 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4733 4734 total_length += xfer->ux_frlengths[trans_count]; 4735 offs += xfer->ux_frlengths[trans_count]; 4736 trans_count++; 4737 4738 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4739 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4740 break; 4741 } 4742 } 4743 4744 /* 4745 * Step 1.75, set buffer pointers. To simplify matters, all 4746 * pointers are filled out for the next 7 hardware pages in 4747 * the dma block, so no need to worry what pages to cover 4748 * and what to not. 4749 */ 4750 4751 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4752 /* 4753 * Don't try to lookup a page that's past the end 4754 * of buffer 4755 */ 4756 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4757 if (page_offs >= dma_buf->udma_block->size) 4758 break; 4759 4760 uint64_t page = DMAADDR(dma_buf, page_offs); 4761 page = EHCI_PAGE(page); 4762 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4763 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4764 } 4765 /* 4766 * Other special values 4767 */ 4768 4769 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4770 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4771 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4772 4773 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4774 ? 1 : 0; 4775 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4776 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4777 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4778 4779 /* FIXME: handle invalid trans */ 4780 itd->itd.itd_bufr[2] |= 4781 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4782 4783 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4784 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4785 4786 prev = itd; 4787 } /* End of frame */ 4788 4789 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4790 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4791 4792 /* 4793 * Part 2: Transfer descriptors have now been set up, now they must 4794 * be scheduled into the period frame list. Erk. Not wanting to 4795 * complicate matters, transfer is denied if the transfer spans 4796 * more than the period frame list. 4797 */ 4798 4799 mutex_enter(&sc->sc_lock); 4800 4801 /* Start inserting frames */ 4802 if (epipe->isoc.cur_xfers > 0) { 4803 frindex = epipe->isoc.next_frame; 4804 } else { 4805 frindex = EOREAD4(sc, EHCI_FRINDEX); 4806 frindex = frindex >> 3; /* Erase microframe index */ 4807 frindex += 2; 4808 } 4809 4810 if (frindex >= sc->sc_flsize) 4811 frindex &= (sc->sc_flsize - 1); 4812 4813 /* What's the frame interval? */ 4814 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4815 if (i / USB_UFRAMES_PER_FRAME == 0) 4816 i = 1; 4817 else 4818 i /= USB_UFRAMES_PER_FRAME; 4819 4820 itd = exfer->ex_itdstart; 4821 for (j = 0; j < frames; j++) { 4822 KASSERTMSG(itd != NULL, "frame %d\n", j); 4823 4824 usb_syncmem(&sc->sc_fldma, 4825 sizeof(ehci_link_t) * frindex, 4826 sizeof(ehci_link_t), 4827 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4828 4829 itd->itd.itd_next = sc->sc_flist[frindex]; 4830 if (itd->itd.itd_next == 0) 4831 /* 4832 * FIXME: frindex table gets initialized to NULL 4833 * or EHCI_NULL? 4834 */ 4835 itd->itd.itd_next = EHCI_NULL; 4836 4837 usb_syncmem(&itd->dma, 4838 itd->offs + offsetof(ehci_itd_t, itd_next), 4839 sizeof(itd->itd.itd_next), 4840 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4841 4842 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4843 4844 usb_syncmem(&sc->sc_fldma, 4845 sizeof(ehci_link_t) * frindex, 4846 sizeof(ehci_link_t), 4847 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4848 4849 itd->frame_list.next = sc->sc_softitds[frindex]; 4850 sc->sc_softitds[frindex] = itd; 4851 if (itd->frame_list.next != NULL) 4852 itd->frame_list.next->frame_list.prev = itd; 4853 itd->slot = frindex; 4854 itd->frame_list.prev = NULL; 4855 4856 frindex += i; 4857 if (frindex >= sc->sc_flsize) 4858 frindex -= sc->sc_flsize; 4859 4860 itd = itd->xfer_next; 4861 } 4862 4863 epipe->isoc.cur_xfers++; 4864 epipe->isoc.next_frame = frindex; 4865 4866 ehci_add_intr_list(sc, exfer); 4867 xfer->ux_status = USBD_IN_PROGRESS; 4868 mutex_exit(&sc->sc_lock); 4869 4870 return USBD_IN_PROGRESS; 4871 } 4872 4873 Static void 4874 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4875 { 4876 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4877 4878 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4879 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4880 } 4881 4882 Static void 4883 ehci_device_isoc_close(struct usbd_pipe *pipe) 4884 { 4885 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4886 4887 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4888 } 4889 4890 Static void 4891 ehci_device_isoc_done(struct usbd_xfer *xfer) 4892 { 4893 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4894 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4895 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4896 4897 KASSERT(mutex_owned(&sc->sc_lock)); 4898 4899 epipe->isoc.cur_xfers--; 4900 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4901 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4902 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4903 } 4904
Indexes created Wed Oct 01 19:09:53 GMT 2025