ehci.c revision 1.257.2.4
1 /* $NetBSD: ehci.c,v 1.257.2.4 2018/09/30 01:45:51 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.257.2.4 2018/09/30 01:45:51 pgoyette Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 #include <sys/reboot.h> 79 80 #include <machine/endian.h> 81 82 #include <dev/usb/usb.h> 83 #include <dev/usb/usbdi.h> 84 #include <dev/usb/usbdivar.h> 85 #include <dev/usb/usbhist.h> 86 #include <dev/usb/usb_mem.h> 87 #include <dev/usb/usb_quirks.h> 88 89 #include <dev/usb/ehcireg.h> 90 #include <dev/usb/ehcivar.h> 91 #include <dev/usb/usbroothub.h> 92 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 static int ehcidebug = 0; 99 100 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 101 { 102 int err; 103 const struct sysctlnode *rnode; 104 const struct sysctlnode *cnode; 105 106 err = sysctl_createv(clog, 0, NULL, &rnode, 107 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 108 SYSCTL_DESCR("ehci global controls"), 109 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 110 111 if (err) 112 goto fail; 113 114 /* control debugging printfs */ 115 err = sysctl_createv(clog, 0, &rnode, &cnode, 116 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 117 "debug", SYSCTL_DESCR("Enable debugging output"), 118 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 119 if (err) 120 goto fail; 121 122 return; 123 fail: 124 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 125 } 126 127 #endif /* EHCI_DEBUG */ 128 #endif /* USB_DEBUG */ 129 130 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 131 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 132 #define EHCIHIST_FUNC() USBHIST_FUNC() 133 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 134 135 struct ehci_pipe { 136 struct usbd_pipe pipe; 137 int nexttoggle; 138 139 ehci_soft_qh_t *sqh; 140 union { 141 /* Control pipe */ 142 struct { 143 usb_dma_t reqdma; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 u_int length; 148 } intr; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 }; 155 }; 156 157 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 158 159 Static usbd_status ehci_open(struct usbd_pipe *); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_timeout(void *); 171 Static void ehci_timeout_task(void *); 172 Static void ehci_intrlist_timeout(void *); 173 Static void ehci_doorbell(void *); 174 Static void ehci_pcd(void *); 175 176 Static struct usbd_xfer * 177 ehci_allocx(struct usbd_bus *, unsigned int); 178 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 179 180 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 181 Static int ehci_roothub_ctrl(struct usbd_bus *, 182 usb_device_request_t *, void *, int); 183 184 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 185 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 186 Static void ehci_root_intr_abort(struct usbd_xfer *); 187 Static void ehci_root_intr_close(struct usbd_pipe *); 188 Static void ehci_root_intr_done(struct usbd_xfer *); 189 190 Static int ehci_device_ctrl_init(struct usbd_xfer *); 191 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 193 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 194 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 195 Static void ehci_device_ctrl_close(struct usbd_pipe *); 196 Static void ehci_device_ctrl_done(struct usbd_xfer *); 197 198 Static int ehci_device_bulk_init(struct usbd_xfer *); 199 Static void ehci_device_bulk_fini(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 201 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 202 Static void ehci_device_bulk_abort(struct usbd_xfer *); 203 Static void ehci_device_bulk_close(struct usbd_pipe *); 204 Static void ehci_device_bulk_done(struct usbd_xfer *); 205 206 Static int ehci_device_intr_init(struct usbd_xfer *); 207 Static void ehci_device_intr_fini(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 209 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 210 Static void ehci_device_intr_abort(struct usbd_xfer *); 211 Static void ehci_device_intr_close(struct usbd_pipe *); 212 Static void ehci_device_intr_done(struct usbd_xfer *); 213 214 Static int ehci_device_isoc_init(struct usbd_xfer *); 215 Static void ehci_device_isoc_fini(struct usbd_xfer *); 216 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 217 Static void ehci_device_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_isoc_done(struct usbd_xfer *); 220 221 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 223 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 225 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 226 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 227 228 Static void ehci_device_clear_toggle(struct usbd_pipe *); 229 Static void ehci_noop(struct usbd_pipe *); 230 231 Static void ehci_disown(ehci_softc_t *, int, int); 232 233 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 234 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 235 236 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 237 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 238 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 239 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 240 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 241 242 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 243 int, int, int *, ehci_soft_qtd_t **); 244 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 245 246 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 247 Static ehci_soft_sitd_t * 248 ehci_alloc_sitd(ehci_softc_t *); 249 250 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 251 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 252 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 253 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 254 255 static inline void 256 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 257 { 258 259 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 260 } 261 262 static inline void 263 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 264 { 265 266 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 267 } 268 269 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 270 271 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 272 int); 273 274 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 275 ehci_soft_qh_t *); 276 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 277 ehci_soft_qh_t *); 278 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 279 Static void ehci_sync_hc(ehci_softc_t *); 280 281 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 282 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 283 284 #ifdef EHCI_DEBUG 285 Static ehci_softc_t *theehci; 286 void ehci_dump(void); 287 #endif 288 289 #ifdef EHCI_DEBUG 290 Static void ehci_dump_regs(ehci_softc_t *); 291 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 292 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 293 Static void ehci_dump_qtd(ehci_qtd_t *); 294 Static void ehci_dump_sqh(ehci_soft_qh_t *); 295 Static void ehci_dump_sitd(struct ehci_soft_itd *); 296 Static void ehci_dump_itds(ehci_soft_itd_t *); 297 Static void ehci_dump_itd(struct ehci_soft_itd *); 298 Static void ehci_dump_exfer(struct ehci_xfer *); 299 #endif 300 301 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 302 303 static inline void 304 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 305 { 306 307 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 308 } 309 310 static inline void 311 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 312 { 313 314 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 315 } 316 317 Static const struct usbd_bus_methods ehci_bus_methods = { 318 .ubm_open = ehci_open, 319 .ubm_softint = ehci_softintr, 320 .ubm_dopoll = ehci_poll, 321 .ubm_allocx = ehci_allocx, 322 .ubm_freex = ehci_freex, 323 .ubm_getlock = ehci_get_lock, 324 .ubm_rhctrl = ehci_roothub_ctrl, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 328 .upm_transfer = ehci_root_intr_transfer, 329 .upm_start = ehci_root_intr_start, 330 .upm_abort = ehci_root_intr_abort, 331 .upm_close = ehci_root_intr_close, 332 .upm_cleartoggle = ehci_noop, 333 .upm_done = ehci_root_intr_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 337 .upm_init = ehci_device_ctrl_init, 338 .upm_fini = ehci_device_ctrl_fini, 339 .upm_transfer = ehci_device_ctrl_transfer, 340 .upm_start = ehci_device_ctrl_start, 341 .upm_abort = ehci_device_ctrl_abort, 342 .upm_close = ehci_device_ctrl_close, 343 .upm_cleartoggle = ehci_noop, 344 .upm_done = ehci_device_ctrl_done, 345 }; 346 347 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 348 .upm_init = ehci_device_intr_init, 349 .upm_fini = ehci_device_intr_fini, 350 .upm_transfer = ehci_device_intr_transfer, 351 .upm_start = ehci_device_intr_start, 352 .upm_abort = ehci_device_intr_abort, 353 .upm_close = ehci_device_intr_close, 354 .upm_cleartoggle = ehci_device_clear_toggle, 355 .upm_done = ehci_device_intr_done, 356 }; 357 358 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 359 .upm_init = ehci_device_bulk_init, 360 .upm_fini = ehci_device_bulk_fini, 361 .upm_transfer = ehci_device_bulk_transfer, 362 .upm_start = ehci_device_bulk_start, 363 .upm_abort = ehci_device_bulk_abort, 364 .upm_close = ehci_device_bulk_close, 365 .upm_cleartoggle = ehci_device_clear_toggle, 366 .upm_done = ehci_device_bulk_done, 367 }; 368 369 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 370 .upm_init = ehci_device_isoc_init, 371 .upm_fini = ehci_device_isoc_fini, 372 .upm_transfer = ehci_device_isoc_transfer, 373 .upm_abort = ehci_device_isoc_abort, 374 .upm_close = ehci_device_isoc_close, 375 .upm_cleartoggle = ehci_noop, 376 .upm_done = ehci_device_isoc_done, 377 }; 378 379 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 380 .upm_init = ehci_device_fs_isoc_init, 381 .upm_fini = ehci_device_fs_isoc_fini, 382 .upm_transfer = ehci_device_fs_isoc_transfer, 383 .upm_abort = ehci_device_fs_isoc_abort, 384 .upm_close = ehci_device_fs_isoc_close, 385 .upm_cleartoggle = ehci_noop, 386 .upm_done = ehci_device_fs_isoc_done, 387 }; 388 389 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 390 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 391 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 392 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 393 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 394 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 395 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 396 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 397 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 398 }; 399 400 int 401 ehci_init(ehci_softc_t *sc) 402 { 403 uint32_t vers, sparams, cparams, hcr; 404 u_int i; 405 usbd_status err; 406 ehci_soft_qh_t *sqh; 407 u_int ncomp; 408 409 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 410 #ifdef EHCI_DEBUG 411 theehci = sc; 412 #endif 413 414 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 415 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 416 cv_init(&sc->sc_doorbell, "ehcidb"); 417 418 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 419 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 420 421 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 422 ehci_doorbell, sc); 423 KASSERT(sc->sc_doorbell_si != NULL); 424 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 425 ehci_pcd, sc); 426 KASSERT(sc->sc_pcd_si != NULL); 427 428 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 429 430 vers = EREAD2(sc, EHCI_HCIVERSION); 431 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 432 vers >> 8, vers & 0xff); 433 434 sparams = EREAD4(sc, EHCI_HCSPARAMS); 435 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 436 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 437 ncomp = EHCI_HCS_N_CC(sparams); 438 if (ncomp != sc->sc_ncomp) { 439 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 440 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 441 #if NOHCI == 0 || NUHCI == 0 442 aprint_error("%s: ohci or uhci probably not configured\n", 443 device_xname(sc->sc_dev)); 444 #endif 445 if (ncomp < sc->sc_ncomp) 446 sc->sc_ncomp = ncomp; 447 } 448 if (sc->sc_ncomp > 0) { 449 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 450 aprint_normal_dev(sc->sc_dev, 451 "%d companion controller%s, %d port%s%s", 452 sc->sc_ncomp, 453 sc->sc_ncomp!=1 ? "s" : "", 454 EHCI_HCS_N_PCC(sparams), 455 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 456 sc->sc_ncomp!=1 ? " each" : ""); 457 if (sc->sc_comps[0]) { 458 aprint_normal(":"); 459 for (i = 0; i < sc->sc_ncomp; i++) 460 aprint_normal(" %s", 461 device_xname(sc->sc_comps[i])); 462 } 463 aprint_normal("\n"); 464 465 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 466 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 467 cv_init(&sc->sc_compcv, "ehciccv"); 468 sc->sc_comp_state = CO_EARLY; 469 } 470 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 471 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 472 473 cparams = EREAD4(sc, EHCI_HCCPARAMS); 474 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 475 476 if (EHCI_HCC_64BIT(cparams)) { 477 /* MUST clear segment register if 64 bit capable. */ 478 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 479 } 480 481 if (cparams & EHCI_HCC_IST_FULLFRAME) { 482 sc->sc_istthreshold = 0; 483 } else { 484 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 485 } 486 487 sc->sc_bus.ub_revision = USBREV_2_0; 488 sc->sc_bus.ub_usedma = true; 489 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 490 491 /* Reset the controller */ 492 DPRINTF("resetting", 0, 0, 0, 0); 493 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 494 usb_delay_ms(&sc->sc_bus, 1); 495 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 496 for (i = 0; i < 100; i++) { 497 usb_delay_ms(&sc->sc_bus, 1); 498 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 499 if (!hcr) 500 break; 501 } 502 if (hcr) { 503 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 504 return EIO; 505 } 506 if (sc->sc_vendor_init) 507 sc->sc_vendor_init(sc); 508 509 /* XXX need proper intr scheduling */ 510 sc->sc_rand = 96; 511 512 /* frame list size at default, read back what we got and use that */ 513 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 514 case 0: sc->sc_flsize = 1024; break; 515 case 1: sc->sc_flsize = 512; break; 516 case 2: sc->sc_flsize = 256; break; 517 case 3: return EIO; 518 } 519 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 520 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 521 if (err) 522 return err; 523 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 524 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 525 526 for (i = 0; i < sc->sc_flsize; i++) { 527 sc->sc_flist[i] = EHCI_NULL; 528 } 529 530 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 531 532 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 533 KM_SLEEP); 534 if (sc->sc_softitds == NULL) 535 return ENOMEM; 536 LIST_INIT(&sc->sc_freeitds); 537 LIST_INIT(&sc->sc_freesitds); 538 TAILQ_INIT(&sc->sc_intrhead); 539 540 /* Set up the bus struct. */ 541 sc->sc_bus.ub_methods = &ehci_bus_methods; 542 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 543 544 sc->sc_eintrs = EHCI_NORMAL_INTRS; 545 546 /* 547 * Allocate the interrupt dummy QHs. These are arranged to give poll 548 * intervals that are powers of 2 times 1ms. 549 */ 550 for (i = 0; i < EHCI_INTRQHS; i++) { 551 sqh = ehci_alloc_sqh(sc); 552 if (sqh == NULL) { 553 err = ENOMEM; 554 goto bad1; 555 } 556 sc->sc_islots[i].sqh = sqh; 557 } 558 for (i = 0; i < EHCI_INTRQHS; i++) { 559 sqh = sc->sc_islots[i].sqh; 560 if (i == 0) { 561 /* The last (1ms) QH terminates. */ 562 sqh->qh.qh_link = EHCI_NULL; 563 sqh->next = NULL; 564 } else { 565 /* Otherwise the next QH has half the poll interval */ 566 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 567 sqh->qh.qh_link = htole32(sqh->next->physaddr | 568 EHCI_LINK_QH); 569 } 570 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 571 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 572 sqh->qh.qh_curqtd = EHCI_NULL; 573 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 574 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 575 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 576 sqh->sqtd = NULL; 577 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 578 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 579 } 580 /* Point the frame list at the last level (128ms). */ 581 for (i = 0; i < sc->sc_flsize; i++) { 582 int j; 583 584 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 585 revbits[i & (EHCI_MAX_POLLRATE-1)]; 586 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 587 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 588 i)].sqh->physaddr); 589 } 590 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 591 BUS_DMASYNC_PREWRITE); 592 593 /* Allocate dummy QH that starts the async list. */ 594 sqh = ehci_alloc_sqh(sc); 595 if (sqh == NULL) { 596 err = ENOMEM; 597 goto bad1; 598 } 599 /* Fill the QH */ 600 sqh->qh.qh_endp = 601 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 602 sqh->qh.qh_link = 603 htole32(sqh->physaddr | EHCI_LINK_QH); 604 sqh->qh.qh_curqtd = EHCI_NULL; 605 sqh->next = NULL; 606 /* Fill the overlay qTD */ 607 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 608 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 609 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 610 sqh->sqtd = NULL; 611 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 612 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 613 #ifdef EHCI_DEBUG 614 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 615 ehci_dump_sqh(sqh); 616 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 617 #endif 618 619 /* Point to async list */ 620 sc->sc_async_head = sqh; 621 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 622 623 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 624 625 /* Turn on controller */ 626 EOWRITE4(sc, EHCI_USBCMD, 627 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 628 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 629 EHCI_CMD_ASE | 630 EHCI_CMD_PSE | 631 EHCI_CMD_RS); 632 633 /* Take over port ownership */ 634 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 635 636 for (i = 0; i < 100; i++) { 637 usb_delay_ms(&sc->sc_bus, 1); 638 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 639 if (!hcr) 640 break; 641 } 642 if (hcr) { 643 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 644 return EIO; 645 } 646 647 /* Enable interrupts */ 648 DPRINTF("enabling interrupts", 0, 0, 0, 0); 649 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 650 651 return 0; 652 653 #if 0 654 bad2: 655 ehci_free_sqh(sc, sc->sc_async_head); 656 #endif 657 bad1: 658 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 659 return err; 660 } 661 662 int 663 ehci_intr(void *v) 664 { 665 ehci_softc_t *sc = v; 666 int ret = 0; 667 668 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 669 670 if (sc == NULL) 671 return 0; 672 673 mutex_spin_enter(&sc->sc_intr_lock); 674 675 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 676 goto done; 677 678 /* If we get an interrupt while polling, then just ignore it. */ 679 if (sc->sc_bus.ub_usepolling) { 680 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 681 682 if (intrs) 683 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 684 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 685 goto done; 686 } 687 688 ret = ehci_intr1(sc); 689 690 done: 691 mutex_spin_exit(&sc->sc_intr_lock); 692 return ret; 693 } 694 695 Static int 696 ehci_intr1(ehci_softc_t *sc) 697 { 698 uint32_t intrs, eintrs; 699 700 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 701 702 /* In case the interrupt occurs before initialization has completed. */ 703 if (sc == NULL) { 704 #ifdef DIAGNOSTIC 705 printf("ehci_intr1: sc == NULL\n"); 706 #endif 707 return 0; 708 } 709 710 KASSERT(mutex_owned(&sc->sc_intr_lock)); 711 712 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 713 if (!intrs) 714 return 0; 715 716 eintrs = intrs & sc->sc_eintrs; 717 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 718 EOREAD4(sc, EHCI_USBSTS), eintrs); 719 if (!eintrs) 720 return 0; 721 722 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 723 if (eintrs & EHCI_STS_IAA) { 724 DPRINTF("door bell", 0, 0, 0, 0); 725 kpreempt_disable(); 726 KASSERT(sc->sc_doorbell_si != NULL); 727 softint_schedule(sc->sc_doorbell_si); 728 kpreempt_enable(); 729 eintrs &= ~EHCI_STS_IAA; 730 } 731 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 732 DPRINTF("INT=%jd ERRINT=%jd", 733 eintrs & EHCI_STS_INT ? 1 : 0, 734 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 735 usb_schedsoftintr(&sc->sc_bus); 736 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 737 } 738 if (eintrs & EHCI_STS_HSE) { 739 printf("%s: unrecoverable error, controller halted\n", 740 device_xname(sc->sc_dev)); 741 /* XXX what else */ 742 } 743 if (eintrs & EHCI_STS_PCD) { 744 kpreempt_disable(); 745 KASSERT(sc->sc_pcd_si != NULL); 746 softint_schedule(sc->sc_pcd_si); 747 kpreempt_enable(); 748 eintrs &= ~EHCI_STS_PCD; 749 } 750 751 if (eintrs != 0) { 752 /* Block unprocessed interrupts. */ 753 sc->sc_eintrs &= ~eintrs; 754 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 755 printf("%s: blocking intrs 0x%x\n", 756 device_xname(sc->sc_dev), eintrs); 757 } 758 759 return 1; 760 } 761 762 Static void 763 ehci_doorbell(void *addr) 764 { 765 ehci_softc_t *sc = addr; 766 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 cv_broadcast(&sc->sc_doorbell); 770 mutex_exit(&sc->sc_lock); 771 } 772 773 Static void 774 ehci_pcd(void *addr) 775 { 776 ehci_softc_t *sc = addr; 777 struct usbd_xfer *xfer; 778 u_char *p; 779 int i, m; 780 781 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 782 783 mutex_enter(&sc->sc_lock); 784 xfer = sc->sc_intrxfer; 785 786 if (xfer == NULL) { 787 /* Just ignore the change. */ 788 goto done; 789 } 790 791 p = xfer->ux_buf; 792 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 793 memset(p, 0, xfer->ux_length); 794 for (i = 1; i <= m; i++) { 795 /* Pick out CHANGE bits from the status reg. */ 796 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 797 p[i/8] |= 1 << (i%8); 798 if (i % 8 == 7) 799 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 800 } 801 xfer->ux_actlen = xfer->ux_length; 802 xfer->ux_status = USBD_NORMAL_COMPLETION; 803 804 usb_transfer_complete(xfer); 805 806 done: 807 mutex_exit(&sc->sc_lock); 808 } 809 810 Static void 811 ehci_softintr(void *v) 812 { 813 struct usbd_bus *bus = v; 814 ehci_softc_t *sc = EHCI_BUS2SC(bus); 815 struct ehci_xfer *ex, *nextex; 816 817 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 818 819 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 820 821 ex_completeq_t cq; 822 TAILQ_INIT(&cq); 823 824 /* 825 * The only explanation I can think of for why EHCI is as brain dead 826 * as UHCI interrupt-wise is that Intel was involved in both. 827 * An interrupt just tells us that something is done, we have no 828 * clue what, so we need to scan through all active transfers. :-( 829 */ 830 831 /* 832 * ehci_idone will remove transfer from sc->sc_intrhead if it's 833 * complete and add to our cq list 834 * 835 */ 836 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 837 switch (ex->ex_type) { 838 case EX_CTRL: 839 case EX_BULK: 840 case EX_INTR: 841 ehci_check_qh_intr(sc, ex, &cq); 842 break; 843 case EX_ISOC: 844 ehci_check_itd_intr(sc, ex, &cq); 845 break; 846 case EX_FS_ISOC: 847 ehci_check_sitd_intr(sc, ex, &cq); 848 break; 849 default: 850 KASSERT(false); 851 } 852 853 } 854 855 /* 856 * We abuse ex_next for the interrupt and complete lists and 857 * interrupt transfers will get re-added here so use 858 * the _SAFE version of TAILQ_FOREACH. 859 */ 860 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 861 usb_transfer_complete(&ex->ex_xfer); 862 } 863 864 /* Schedule a callout to catch any dropped transactions. */ 865 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 866 !TAILQ_EMPTY(&sc->sc_intrhead)) 867 callout_reset(&sc->sc_tmo_intrlist, 868 hz, ehci_intrlist_timeout, sc); 869 } 870 871 Static void 872 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 873 { 874 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 875 uint32_t status; 876 877 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 878 879 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 880 881 if (ex->ex_type == EX_CTRL) { 882 fsqtd = ex->ex_setup; 883 lsqtd = ex->ex_status; 884 } else { 885 fsqtd = ex->ex_sqtdstart; 886 lsqtd = ex->ex_sqtdend; 887 } 888 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 889 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 890 891 /* 892 * If the last TD is still active we need to check whether there 893 * is an error somewhere in the middle, or whether there was a 894 * short packet (SPD and not ACTIVE). 895 */ 896 usb_syncmem(&lsqtd->dma, 897 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 898 sizeof(lsqtd->qtd.qtd_status), 899 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 900 status = le32toh(lsqtd->qtd.qtd_status); 901 usb_syncmem(&lsqtd->dma, 902 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 903 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 904 if (status & EHCI_QTD_ACTIVE) { 905 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 906 907 /* last qTD has already been checked */ 908 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 909 usb_syncmem(&sqtd->dma, 910 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 911 sizeof(sqtd->qtd.qtd_status), 912 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 913 status = le32toh(sqtd->qtd.qtd_status); 914 usb_syncmem(&sqtd->dma, 915 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 916 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 917 /* If there's an active QTD the xfer isn't done. */ 918 if (status & EHCI_QTD_ACTIVE) 919 break; 920 /* Any kind of error makes the xfer done. */ 921 if (status & EHCI_QTD_HALTED) 922 goto done; 923 /* Handle short packets */ 924 if (EHCI_QTD_GET_BYTES(status) != 0) { 925 /* 926 * If we get here for a control transfer then 927 * we need to let the hardware complete the 928 * status phase. That is, we're not done 929 * quite yet. 930 * 931 * Otherwise, we're done. 932 */ 933 if (ex->ex_type == EX_CTRL) { 934 break; 935 } 936 goto done; 937 } 938 } 939 DPRINTFN(10, "ex=%#jx std=%#jx still active", 940 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 941 #ifdef EHCI_DEBUG 942 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 943 ehci_dump_sqtds(ex->ex_sqtdstart); 944 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 945 #endif 946 return; 947 } 948 done: 949 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 950 ehci_idone(ex, cq); 951 } 952 953 Static void 954 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 955 { 956 ehci_soft_itd_t *itd; 957 int i; 958 959 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 960 961 KASSERT(mutex_owned(&sc->sc_lock)); 962 963 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 964 return; 965 966 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 967 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 968 969 itd = ex->ex_itdend; 970 971 /* 972 * check no active transfers in last itd, meaning we're finished 973 */ 974 975 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 976 sizeof(itd->itd.itd_ctl), 977 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 978 979 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 980 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 981 break; 982 } 983 984 if (i == EHCI_ITD_NUFRAMES) { 985 goto done; /* All 8 descriptors inactive, it's done */ 986 } 987 988 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 989 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 990 991 DPRINTFN(10, "ex %#jx itd %#jx still active", 992 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 993 return; 994 done: 995 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 996 ehci_idone(ex, cq); 997 } 998 999 void 1000 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1001 { 1002 ehci_soft_sitd_t *sitd; 1003 1004 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1005 1006 KASSERT(mutex_owned(&sc->sc_lock)); 1007 1008 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1009 return; 1010 1011 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1012 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1013 1014 sitd = ex->ex_sitdend; 1015 1016 /* 1017 * check no active transfers in last sitd, meaning we're finished 1018 */ 1019 1020 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1021 sizeof(sitd->sitd.sitd_trans), 1022 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1023 1024 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1025 1026 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1027 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1028 1029 if (active) 1030 return; 1031 1032 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1033 ehci_idone(ex, cq); 1034 } 1035 1036 1037 Static void 1038 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1039 { 1040 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1041 struct usbd_xfer *xfer = &ex->ex_xfer; 1042 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1043 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1044 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1045 uint32_t status = 0, nstatus = 0; 1046 int actlen = 0; 1047 1048 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1049 1050 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1051 1052 /* 1053 * If software has completed it, either by cancellation 1054 * or timeout, drop it on the floor. 1055 */ 1056 if (xfer->ux_status != USBD_IN_PROGRESS) { 1057 KASSERT(xfer->ux_status == USBD_CANCELLED || 1058 xfer->ux_status == USBD_TIMEOUT); 1059 DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1060 return; 1061 } 1062 1063 /* 1064 * Cancel the timeout and the task, which have not yet 1065 * run. If they have already fired, at worst they are 1066 * waiting for the lock. They will see that the xfer 1067 * is no longer in progress and give up. 1068 */ 1069 callout_stop(&xfer->ux_callout); 1070 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 1071 1072 #ifdef DIAGNOSTIC 1073 #ifdef EHCI_DEBUG 1074 if (ex->ex_isdone) { 1075 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1076 ehci_dump_exfer(ex); 1077 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1078 } 1079 #endif 1080 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1081 ex->ex_type, xfer->ux_status); 1082 ex->ex_isdone = true; 1083 #endif 1084 1085 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1086 (uintptr_t)epipe, 0, 0); 1087 1088 /* The transfer is done, compute actual length and status. */ 1089 if (ex->ex_type == EX_ISOC) { 1090 /* HS isoc transfer */ 1091 1092 struct ehci_soft_itd *itd; 1093 int i, nframes, len, uframes; 1094 1095 nframes = 0; 1096 1097 #ifdef EHCI_DEBUG 1098 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1099 ehci_dump_itds(ex->ex_itdstart); 1100 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1101 #endif 1102 1103 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1104 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1105 1106 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1107 usb_syncmem(&itd->dma, 1108 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1109 sizeof(itd->itd.itd_ctl), 1110 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1111 1112 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1113 /* 1114 * XXX - driver didn't fill in the frame full 1115 * of uframes. This leads to scheduling 1116 * inefficiencies, but working around 1117 * this doubles complexity of tracking 1118 * an xfer. 1119 */ 1120 if (nframes >= xfer->ux_nframes) 1121 break; 1122 1123 status = le32toh(itd->itd.itd_ctl[i]); 1124 len = EHCI_ITD_GET_LEN(status); 1125 if (EHCI_ITD_GET_STATUS(status) != 0) 1126 len = 0; /*No valid data on error*/ 1127 1128 xfer->ux_frlengths[nframes++] = len; 1129 actlen += len; 1130 } 1131 usb_syncmem(&itd->dma, 1132 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1133 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1134 1135 if (nframes >= xfer->ux_nframes) 1136 break; 1137 } 1138 1139 xfer->ux_actlen = actlen; 1140 xfer->ux_status = USBD_NORMAL_COMPLETION; 1141 goto end; 1142 } else if (ex->ex_type == EX_FS_ISOC) { 1143 /* FS isoc transfer */ 1144 struct ehci_soft_sitd *sitd; 1145 int nframes, len; 1146 1147 nframes = 0; 1148 1149 for (sitd = ex->ex_sitdstart; sitd != NULL; 1150 sitd = sitd->xfer_next) { 1151 usb_syncmem(&sitd->dma, 1152 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1153 sizeof(sitd->sitd.sitd_trans), 1154 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1155 1156 /* 1157 * XXX - driver didn't fill in the frame full 1158 * of uframes. This leads to scheduling 1159 * inefficiencies, but working around 1160 * this doubles complexity of tracking 1161 * an xfer. 1162 */ 1163 if (nframes >= xfer->ux_nframes) 1164 break; 1165 1166 status = le32toh(sitd->sitd.sitd_trans); 1167 usb_syncmem(&sitd->dma, 1168 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1169 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1170 1171 len = EHCI_SITD_GET_LEN(status); 1172 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1173 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1174 /* No valid data on error */ 1175 len = xfer->ux_frlengths[nframes]; 1176 } 1177 1178 /* 1179 * frlengths[i]: # of bytes to send 1180 * len: # of bytes host didn't send 1181 */ 1182 xfer->ux_frlengths[nframes] -= len; 1183 /* frlengths[i]: # of bytes host sent */ 1184 actlen += xfer->ux_frlengths[nframes++]; 1185 1186 if (nframes >= xfer->ux_nframes) 1187 break; 1188 } 1189 1190 xfer->ux_actlen = actlen; 1191 xfer->ux_status = USBD_NORMAL_COMPLETION; 1192 goto end; 1193 } 1194 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1195 ex->ex_type == EX_BULK); 1196 1197 /* Continue processing xfers using queue heads */ 1198 if (ex->ex_type == EX_CTRL) { 1199 fsqtd = ex->ex_setup; 1200 lsqtd = ex->ex_status; 1201 } else { 1202 fsqtd = ex->ex_sqtdstart; 1203 lsqtd = ex->ex_sqtdend; 1204 } 1205 #ifdef EHCI_DEBUG 1206 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1207 ehci_dump_sqtds(fsqtd); 1208 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1209 #endif 1210 1211 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1212 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1213 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1214 nstatus = le32toh(sqtd->qtd.qtd_status); 1215 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1216 BUS_DMASYNC_PREREAD); 1217 if (nstatus & EHCI_QTD_ACTIVE) 1218 break; 1219 1220 status = nstatus; 1221 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1222 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1223 } 1224 1225 /* 1226 * If there are left over TDs we need to update the toggle. 1227 * The default pipe doesn't need it since control transfers 1228 * start the toggle at 0 every time. 1229 * For a short transfer we need to update the toggle for the missing 1230 * packets within the qTD. 1231 */ 1232 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1233 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1234 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1235 status, nstatus, 0, 0); 1236 #if 0 1237 ehci_dump_sqh(epipe->sqh); 1238 ehci_dump_sqtds(ex->ex_sqtdstart); 1239 #endif 1240 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1241 } 1242 1243 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1244 status, 0); 1245 xfer->ux_actlen = actlen; 1246 if (status & EHCI_QTD_HALTED) { 1247 #ifdef EHCI_DEBUG 1248 DPRINTF("halted addr=%jd endpt=0x%02jx", 1249 xfer->ux_pipe->up_dev->ud_addr, 1250 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1251 0, 0); 1252 DPRINTF("cerr=%jd pid=%jd", 1253 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1254 0, 0); 1255 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1256 status & EHCI_QTD_ACTIVE ? 1 : 0, 1257 status & EHCI_QTD_HALTED ? 1 : 0, 1258 status & EHCI_QTD_BUFERR ? 1 : 0, 1259 status & EHCI_QTD_BABBLE ? 1 : 0); 1260 1261 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1262 status & EHCI_QTD_XACTERR ? 1 : 0, 1263 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1264 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1265 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1266 1267 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1268 ehci_dump_sqh(epipe->sqh); 1269 ehci_dump_sqtds(ex->ex_sqtdstart); 1270 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1271 #endif 1272 /* low&full speed has an extra error flag */ 1273 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1274 EHCI_QH_SPEED_HIGH) 1275 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1276 else 1277 status &= EHCI_QTD_STATERRS; 1278 if (status == 0) /* no other errors means a stall */ { 1279 xfer->ux_status = USBD_STALLED; 1280 } else { 1281 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1282 } 1283 /* XXX need to reset TT on missed microframe */ 1284 if (status & EHCI_QTD_MISSEDMICRO) { 1285 printf("%s: missed microframe, TT reset not " 1286 "implemented, hub might be inoperational\n", 1287 device_xname(sc->sc_dev)); 1288 } 1289 } else { 1290 xfer->ux_status = USBD_NORMAL_COMPLETION; 1291 } 1292 1293 end: 1294 1295 ehci_del_intr_list(sc, ex); 1296 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1297 1298 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1299 } 1300 1301 Static void 1302 ehci_poll(struct usbd_bus *bus) 1303 { 1304 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1305 1306 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1307 1308 #ifdef EHCI_DEBUG 1309 static int last; 1310 int new; 1311 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1312 if (new != last) { 1313 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1314 last = new; 1315 } 1316 #endif 1317 1318 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1319 mutex_spin_enter(&sc->sc_intr_lock); 1320 ehci_intr1(sc); 1321 mutex_spin_exit(&sc->sc_intr_lock); 1322 } 1323 } 1324 1325 void 1326 ehci_childdet(device_t self, device_t child) 1327 { 1328 struct ehci_softc *sc = device_private(self); 1329 1330 KASSERT(sc->sc_child == child); 1331 sc->sc_child = NULL; 1332 } 1333 1334 int 1335 ehci_detach(struct ehci_softc *sc, int flags) 1336 { 1337 int rv = 0; 1338 1339 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1340 1341 if (sc->sc_child != NULL) 1342 rv = config_detach(sc->sc_child, flags); 1343 1344 if (rv != 0) 1345 return rv; 1346 1347 if (sc->sc_ncomp > 0) { 1348 mutex_enter(&sc->sc_complock); 1349 /* XXX try to halt callout instead of waiting */ 1350 while (sc->sc_comp_state == CO_SCHED) 1351 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1352 mutex_exit(&sc->sc_complock); 1353 1354 callout_halt(&sc->sc_compcallout, NULL); 1355 callout_destroy(&sc->sc_compcallout); 1356 cv_destroy(&sc->sc_compcv); 1357 mutex_destroy(&sc->sc_complock); 1358 } 1359 1360 callout_halt(&sc->sc_tmo_intrlist, NULL); 1361 callout_destroy(&sc->sc_tmo_intrlist); 1362 1363 /* XXX free other data structures XXX */ 1364 if (sc->sc_softitds) 1365 kmem_free(sc->sc_softitds, 1366 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1367 cv_destroy(&sc->sc_doorbell); 1368 1369 #if 0 1370 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1371 1372 softint_disestablish(sc->sc_doorbell_si); 1373 softint_disestablish(sc->sc_pcd_si); 1374 1375 mutex_destroy(&sc->sc_lock); 1376 mutex_destroy(&sc->sc_intr_lock); 1377 #endif 1378 1379 pool_cache_destroy(sc->sc_xferpool); 1380 1381 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1382 1383 return rv; 1384 } 1385 1386 1387 int 1388 ehci_activate(device_t self, enum devact act) 1389 { 1390 struct ehci_softc *sc = device_private(self); 1391 1392 switch (act) { 1393 case DVACT_DEACTIVATE: 1394 sc->sc_dying = 1; 1395 return 0; 1396 default: 1397 return EOPNOTSUPP; 1398 } 1399 } 1400 1401 /* 1402 * Handle suspend/resume. 1403 * 1404 * We need to switch to polling mode here, because this routine is 1405 * called from an interrupt context. This is all right since we 1406 * are almost suspended anyway. 1407 * 1408 * Note that this power handler isn't to be registered directly; the 1409 * bus glue needs to call out to it. 1410 */ 1411 bool 1412 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1413 { 1414 ehci_softc_t *sc = device_private(dv); 1415 int i; 1416 uint32_t cmd, hcr; 1417 1418 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1419 1420 mutex_spin_enter(&sc->sc_intr_lock); 1421 sc->sc_bus.ub_usepolling++; 1422 mutex_spin_exit(&sc->sc_intr_lock); 1423 1424 for (i = 1; i <= sc->sc_noport; i++) { 1425 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1426 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1427 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1428 } 1429 1430 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1431 1432 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1433 EOWRITE4(sc, EHCI_USBCMD, cmd); 1434 1435 for (i = 0; i < 100; i++) { 1436 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1437 if (hcr == 0) 1438 break; 1439 1440 usb_delay_ms(&sc->sc_bus, 1); 1441 } 1442 if (hcr != 0) 1443 printf("%s: reset timeout\n", device_xname(dv)); 1444 1445 cmd &= ~EHCI_CMD_RS; 1446 EOWRITE4(sc, EHCI_USBCMD, cmd); 1447 1448 for (i = 0; i < 100; i++) { 1449 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1450 if (hcr == EHCI_STS_HCH) 1451 break; 1452 1453 usb_delay_ms(&sc->sc_bus, 1); 1454 } 1455 if (hcr != EHCI_STS_HCH) 1456 printf("%s: config timeout\n", device_xname(dv)); 1457 1458 mutex_spin_enter(&sc->sc_intr_lock); 1459 sc->sc_bus.ub_usepolling--; 1460 mutex_spin_exit(&sc->sc_intr_lock); 1461 1462 return true; 1463 } 1464 1465 bool 1466 ehci_resume(device_t dv, const pmf_qual_t *qual) 1467 { 1468 ehci_softc_t *sc = device_private(dv); 1469 int i; 1470 uint32_t cmd, hcr; 1471 1472 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1473 1474 /* restore things in case the bios sucks */ 1475 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1476 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1477 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1478 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1479 1480 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1481 1482 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1483 1484 hcr = 0; 1485 for (i = 1; i <= sc->sc_noport; i++) { 1486 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1487 if ((cmd & EHCI_PS_PO) == 0 && 1488 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1489 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1490 hcr = 1; 1491 } 1492 } 1493 1494 if (hcr) { 1495 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1496 1497 for (i = 1; i <= sc->sc_noport; i++) { 1498 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1499 if ((cmd & EHCI_PS_PO) == 0 && 1500 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1501 EOWRITE4(sc, EHCI_PORTSC(i), 1502 cmd & ~EHCI_PS_FPR); 1503 } 1504 } 1505 1506 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1507 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1508 1509 for (i = 0; i < 100; i++) { 1510 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1511 if (hcr != EHCI_STS_HCH) 1512 break; 1513 1514 usb_delay_ms(&sc->sc_bus, 1); 1515 } 1516 if (hcr == EHCI_STS_HCH) 1517 printf("%s: config timeout\n", device_xname(dv)); 1518 1519 return true; 1520 } 1521 1522 /* 1523 * Shut down the controller when the system is going down. 1524 */ 1525 bool 1526 ehci_shutdown(device_t self, int flags) 1527 { 1528 ehci_softc_t *sc = device_private(self); 1529 1530 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1531 1532 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1533 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1534 return true; 1535 } 1536 1537 Static struct usbd_xfer * 1538 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1539 { 1540 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1541 struct usbd_xfer *xfer; 1542 1543 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1544 if (xfer != NULL) { 1545 memset(xfer, 0, sizeof(struct ehci_xfer)); 1546 1547 /* Initialise this always so we can call remove on it. */ 1548 usb_init_task(&xfer->ux_aborttask, ehci_timeout_task, xfer, 1549 USB_TASKQ_MPSAFE); 1550 #ifdef DIAGNOSTIC 1551 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1552 ex->ex_isdone = true; 1553 xfer->ux_state = XFER_BUSY; 1554 #endif 1555 } 1556 return xfer; 1557 } 1558 1559 Static void 1560 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1561 { 1562 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1563 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1564 1565 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1566 xfer->ux_state); 1567 KASSERT(ex->ex_isdone); 1568 1569 #ifdef DIAGNOSTIC 1570 xfer->ux_state = XFER_FREE; 1571 #endif 1572 1573 pool_cache_put(sc->sc_xferpool, xfer); 1574 } 1575 1576 Static void 1577 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1578 { 1579 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1580 1581 *lock = &sc->sc_lock; 1582 } 1583 1584 Static void 1585 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1586 { 1587 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1588 1589 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1590 1591 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1592 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1593 #ifdef EHCI_DEBUG 1594 if (ehcidebug) 1595 usbd_dump_pipe(pipe); 1596 #endif 1597 epipe->nexttoggle = 0; 1598 } 1599 1600 Static void 1601 ehci_noop(struct usbd_pipe *pipe) 1602 { 1603 } 1604 1605 #ifdef EHCI_DEBUG 1606 /* 1607 * Unused function - this is meant to be called from a kernel 1608 * debugger. 1609 */ 1610 void 1611 ehci_dump(void) 1612 { 1613 ehci_softc_t *sc = theehci; 1614 int i; 1615 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1616 EOREAD4(sc, EHCI_USBCMD), 1617 EOREAD4(sc, EHCI_USBSTS), 1618 EOREAD4(sc, EHCI_USBINTR)); 1619 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1620 EOREAD4(sc, EHCI_FRINDEX), 1621 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1622 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1623 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1624 for (i = 1; i <= sc->sc_noport; i++) 1625 printf("port %d status=0x%08x\n", i, 1626 EOREAD4(sc, EHCI_PORTSC(i))); 1627 } 1628 1629 Static void 1630 ehci_dump_regs(ehci_softc_t *sc) 1631 { 1632 int i; 1633 1634 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1635 1636 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1637 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1638 EOREAD4(sc, EHCI_USBINTR), 0); 1639 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1640 "async = 0x%08jx", 1641 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1642 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1643 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1644 for (i = 1; i <= sc->sc_noport; i += 2) { 1645 if (i == sc->sc_noport) { 1646 DPRINTF("port %jd status = 0x%08jx", i, 1647 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1648 } else { 1649 DPRINTF("port %jd status = 0x%08jx port %jd " 1650 "status = 0x%08jx", 1651 i, EOREAD4(sc, EHCI_PORTSC(i)), 1652 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1653 } 1654 } 1655 } 1656 1657 #define ehci_dump_link(link, type) do { \ 1658 DPRINTF(" link 0x%08jx (T = %jd):", \ 1659 link, \ 1660 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1661 if (type) { \ 1662 DPRINTF( \ 1663 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1664 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1665 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1666 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1667 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1668 } \ 1669 } while(0) 1670 1671 Static void 1672 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1673 { 1674 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1675 int i; 1676 uint32_t stop = 0; 1677 1678 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1679 ehci_dump_sqtd(sqtd); 1680 usb_syncmem(&sqtd->dma, 1681 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1682 sizeof(sqtd->qtd), 1683 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1684 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1685 usb_syncmem(&sqtd->dma, 1686 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1687 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1688 } 1689 if (!stop) 1690 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1691 } 1692 1693 Static void 1694 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1695 { 1696 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1697 1698 usb_syncmem(&sqtd->dma, sqtd->offs, 1699 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1700 1701 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1702 0, 0); 1703 ehci_dump_qtd(&sqtd->qtd); 1704 1705 usb_syncmem(&sqtd->dma, sqtd->offs, 1706 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1707 } 1708 1709 Static void 1710 ehci_dump_qtd(ehci_qtd_t *qtd) 1711 { 1712 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1713 uint32_t s = le32toh(qtd->qtd_status); 1714 1715 DPRINTFN(10, 1716 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1717 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1718 DPRINTFN(10, 1719 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1720 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1721 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1722 DPRINTFN(10, 1723 " cerr = %jd pid = %jd stat = %jx", 1724 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1725 0); 1726 DPRINTFN(10, 1727 "active =%jd halted=%jd buferr=%jd babble=%jd", 1728 s & EHCI_QTD_ACTIVE ? 1 : 0, 1729 s & EHCI_QTD_HALTED ? 1 : 0, 1730 s & EHCI_QTD_BUFERR ? 1 : 0, 1731 s & EHCI_QTD_BABBLE ? 1 : 0); 1732 DPRINTFN(10, 1733 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1734 s & EHCI_QTD_XACTERR ? 1 : 0, 1735 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1736 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1737 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1738 DPRINTFN(10, 1739 "buffer[0] = %#jx buffer[1] = %#jx " 1740 "buffer[2] = %#jx buffer[3] = %#jx", 1741 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1742 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1743 DPRINTFN(10, 1744 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1745 } 1746 1747 Static void 1748 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1749 { 1750 ehci_qh_t *qh = &sqh->qh; 1751 ehci_link_t link; 1752 uint32_t endp, endphub; 1753 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1754 1755 usb_syncmem(&sqh->dma, sqh->offs, 1756 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1757 1758 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1759 link = le32toh(qh->qh_link); 1760 ehci_dump_link(link, true); 1761 1762 endp = le32toh(qh->qh_endp); 1763 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1764 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1765 "eps = %jd", 1766 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1767 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1768 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1769 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1770 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1771 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1772 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1773 1774 endphub = le32toh(qh->qh_endphub); 1775 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1776 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1777 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1778 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1779 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1780 EHCI_QH_GET_MULT(endphub), 0); 1781 1782 link = le32toh(qh->qh_curqtd); 1783 ehci_dump_link(link, false); 1784 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1785 ehci_dump_qtd(&qh->qh_qtd); 1786 1787 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1788 BUS_DMASYNC_PREREAD); 1789 } 1790 1791 Static void 1792 ehci_dump_itds(ehci_soft_itd_t *itd) 1793 { 1794 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1795 int i; 1796 uint32_t stop = 0; 1797 1798 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1799 ehci_dump_itd(itd); 1800 usb_syncmem(&itd->dma, 1801 itd->offs + offsetof(ehci_itd_t, itd_next), 1802 sizeof(itd->itd), 1803 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1804 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1805 usb_syncmem(&itd->dma, 1806 itd->offs + offsetof(ehci_itd_t, itd_next), 1807 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1808 } 1809 if (!stop) 1810 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1811 } 1812 1813 Static void 1814 ehci_dump_itd(struct ehci_soft_itd *itd) 1815 { 1816 ehci_isoc_trans_t t; 1817 ehci_isoc_bufr_ptr_t b, b2, b3; 1818 int i; 1819 1820 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1821 1822 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1823 1824 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1825 t = le32toh(itd->itd.itd_ctl[i]); 1826 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1827 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1828 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1829 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1830 EHCI_ITD_GET_OFFS(t), 0); 1831 } 1832 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1833 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1834 DPRINTF(" %jx", 1835 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1836 1837 b = le32toh(itd->itd.itd_bufr[0]); 1838 b2 = le32toh(itd->itd.itd_bufr[1]); 1839 b3 = le32toh(itd->itd.itd_bufr[2]); 1840 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1841 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1842 DPRINTF(" maxpkt = %jx multi = %jx", 1843 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1844 } 1845 1846 Static void 1847 ehci_dump_sitd(struct ehci_soft_itd *itd) 1848 { 1849 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1850 1851 DPRINTF("SITD %#jx next = %p prev = %#jx", 1852 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1853 (uintptr_t)itd->frame_list.prev, 0); 1854 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1855 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1856 } 1857 1858 Static void 1859 ehci_dump_exfer(struct ehci_xfer *ex) 1860 { 1861 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1862 1863 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1864 ex->ex_isdone, 0); 1865 1866 switch (ex->ex_type) { 1867 case EX_CTRL: 1868 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1869 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1870 (uintptr_t)ex->ex_status, 0); 1871 break; 1872 case EX_BULK: 1873 case EX_INTR: 1874 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1875 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1876 0, 0); 1877 break; 1878 case EX_ISOC: 1879 DPRINTF(" itdstart = %#jx itdend = %#jx", 1880 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1881 break; 1882 case EX_FS_ISOC: 1883 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1884 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1885 0, 0); 1886 break; 1887 default: 1888 DPRINTF(" unknown type", 0, 0, 0, 0); 1889 } 1890 } 1891 #endif 1892 1893 Static usbd_status 1894 ehci_open(struct usbd_pipe *pipe) 1895 { 1896 struct usbd_device *dev = pipe->up_dev; 1897 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1898 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1899 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1900 uint8_t addr = dev->ud_addr; 1901 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1902 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1903 ehci_soft_qh_t *sqh; 1904 usbd_status err; 1905 int ival, speed, naks; 1906 int hshubaddr, hshubport; 1907 1908 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1909 1910 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1911 ed->bEndpointAddress, rhaddr); 1912 1913 if (dev->ud_myhsport) { 1914 /* 1915 * When directly attached FS/LS device while doing embedded 1916 * transaction translations and we are the hub, set the hub 1917 * address to 0 (us). 1918 */ 1919 if (!(sc->sc_flags & EHCIF_ETTF) 1920 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1921 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1922 } else { 1923 hshubaddr = 0; 1924 } 1925 hshubport = dev->ud_myhsport->up_portno; 1926 } else { 1927 hshubaddr = 0; 1928 hshubport = 0; 1929 } 1930 1931 if (sc->sc_dying) 1932 return USBD_IOERROR; 1933 1934 /* toggle state needed for bulk endpoints */ 1935 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1936 1937 if (addr == rhaddr) { 1938 switch (ed->bEndpointAddress) { 1939 case USB_CONTROL_ENDPOINT: 1940 pipe->up_methods = &roothub_ctrl_methods; 1941 break; 1942 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1943 pipe->up_methods = &ehci_root_intr_methods; 1944 break; 1945 default: 1946 DPRINTF("bad bEndpointAddress 0x%02jx", 1947 ed->bEndpointAddress, 0, 0, 0); 1948 return USBD_INVAL; 1949 } 1950 return USBD_NORMAL_COMPLETION; 1951 } 1952 1953 /* XXX All this stuff is only valid for async. */ 1954 switch (dev->ud_speed) { 1955 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1956 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1957 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1958 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1959 } 1960 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1961 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1962 0); 1963 return USBD_INVAL; 1964 } 1965 1966 /* 1967 * For interrupt transfer, nak throttling must be disabled, but for 1968 * the other transfer type, nak throttling should be enabled from the 1969 * viewpoint that avoids the memory thrashing. 1970 */ 1971 naks = (xfertype == UE_INTERRUPT) ? 0 1972 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1973 1974 /* Allocate sqh for everything, save isoc xfers */ 1975 if (xfertype != UE_ISOCHRONOUS) { 1976 sqh = ehci_alloc_sqh(sc); 1977 if (sqh == NULL) 1978 return USBD_NOMEM; 1979 /* qh_link filled when the QH is added */ 1980 sqh->qh.qh_endp = htole32( 1981 EHCI_QH_SET_ADDR(addr) | 1982 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1983 EHCI_QH_SET_EPS(speed) | 1984 EHCI_QH_DTC | 1985 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1986 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1987 EHCI_QH_CTL : 0) | 1988 EHCI_QH_SET_NRL(naks) 1989 ); 1990 sqh->qh.qh_endphub = htole32( 1991 EHCI_QH_SET_MULT(1) | 1992 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1993 ); 1994 if (speed != EHCI_QH_SPEED_HIGH) 1995 sqh->qh.qh_endphub |= htole32( 1996 EHCI_QH_SET_PORT(hshubport) | 1997 EHCI_QH_SET_HUBA(hshubaddr) | 1998 (xfertype == UE_INTERRUPT ? 1999 EHCI_QH_SET_CMASK(0x08) : 0) 2000 ); 2001 sqh->qh.qh_curqtd = EHCI_NULL; 2002 /* Fill the overlay qTD */ 2003 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2004 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2005 sqh->qh.qh_qtd.qtd_status = htole32(0); 2006 2007 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2008 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2009 epipe->sqh = sqh; 2010 } else { 2011 sqh = NULL; 2012 } /*xfertype == UE_ISOC*/ 2013 2014 switch (xfertype) { 2015 case UE_CONTROL: 2016 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2017 0, &epipe->ctrl.reqdma); 2018 #ifdef EHCI_DEBUG 2019 if (err) 2020 printf("ehci_open: usb_allocmem()=%d\n", err); 2021 #endif 2022 if (err) 2023 goto bad; 2024 pipe->up_methods = &ehci_device_ctrl_methods; 2025 mutex_enter(&sc->sc_lock); 2026 ehci_add_qh(sc, sqh, sc->sc_async_head); 2027 mutex_exit(&sc->sc_lock); 2028 break; 2029 case UE_BULK: 2030 pipe->up_methods = &ehci_device_bulk_methods; 2031 mutex_enter(&sc->sc_lock); 2032 ehci_add_qh(sc, sqh, sc->sc_async_head); 2033 mutex_exit(&sc->sc_lock); 2034 break; 2035 case UE_INTERRUPT: 2036 pipe->up_methods = &ehci_device_intr_methods; 2037 ival = pipe->up_interval; 2038 if (ival == USBD_DEFAULT_INTERVAL) { 2039 if (speed == EHCI_QH_SPEED_HIGH) { 2040 if (ed->bInterval > 16) { 2041 /* 2042 * illegal with high-speed, but there 2043 * were documentation bugs in the spec, 2044 * so be generous 2045 */ 2046 ival = 256; 2047 } else 2048 ival = (1 << (ed->bInterval - 1)) / 8; 2049 } else 2050 ival = ed->bInterval; 2051 } 2052 err = ehci_device_setintr(sc, sqh, ival); 2053 if (err) 2054 goto bad; 2055 break; 2056 case UE_ISOCHRONOUS: 2057 pipe->up_serialise = false; 2058 if (speed == EHCI_QH_SPEED_HIGH) 2059 pipe->up_methods = &ehci_device_isoc_methods; 2060 else 2061 pipe->up_methods = &ehci_device_fs_isoc_methods; 2062 if (ed->bInterval == 0 || ed->bInterval > 16) { 2063 printf("ehci: opening pipe with invalid bInterval\n"); 2064 err = USBD_INVAL; 2065 goto bad; 2066 } 2067 if (UGETW(ed->wMaxPacketSize) == 0) { 2068 printf("ehci: zero length endpoint open request\n"); 2069 err = USBD_INVAL; 2070 goto bad; 2071 } 2072 epipe->isoc.next_frame = 0; 2073 epipe->isoc.cur_xfers = 0; 2074 break; 2075 default: 2076 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2077 err = USBD_INVAL; 2078 goto bad; 2079 } 2080 return USBD_NORMAL_COMPLETION; 2081 2082 bad: 2083 if (sqh != NULL) { 2084 mutex_enter(&sc->sc_lock); 2085 ehci_free_sqh(sc, sqh); 2086 mutex_exit(&sc->sc_lock); 2087 } 2088 return err; 2089 } 2090 2091 /* 2092 * Add an ED to the schedule. Called with USB lock held. 2093 */ 2094 Static void 2095 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2096 { 2097 2098 KASSERT(mutex_owned(&sc->sc_lock)); 2099 2100 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2101 2102 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2103 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2104 2105 sqh->next = head->next; 2106 sqh->qh.qh_link = head->qh.qh_link; 2107 2108 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2109 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2110 2111 head->next = sqh; 2112 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2113 2114 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2115 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2116 2117 #ifdef EHCI_DEBUG 2118 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2119 ehci_dump_sqh(sqh); 2120 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2121 #endif 2122 } 2123 2124 /* 2125 * Remove an ED from the schedule. Called with USB lock held. 2126 */ 2127 Static void 2128 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2129 { 2130 ehci_soft_qh_t *p; 2131 2132 KASSERT(mutex_owned(&sc->sc_lock)); 2133 2134 /* XXX */ 2135 for (p = head; p != NULL && p->next != sqh; p = p->next) 2136 ; 2137 if (p == NULL) 2138 panic("ehci_rem_qh: ED not found"); 2139 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2140 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2141 p->next = sqh->next; 2142 p->qh.qh_link = sqh->qh.qh_link; 2143 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2144 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2145 2146 ehci_sync_hc(sc); 2147 } 2148 2149 Static void 2150 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2151 { 2152 int i; 2153 uint32_t status; 2154 2155 /* Save toggle bit and ping status. */ 2156 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2157 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2158 status = sqh->qh.qh_qtd.qtd_status & 2159 htole32(EHCI_QTD_TOGGLE_MASK | 2160 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2161 /* Set HALTED to make hw leave it alone. */ 2162 sqh->qh.qh_qtd.qtd_status = 2163 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2164 usb_syncmem(&sqh->dma, 2165 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2166 sizeof(sqh->qh.qh_qtd.qtd_status), 2167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2168 sqh->qh.qh_curqtd = 0; 2169 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2170 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2171 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2172 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2173 sqh->sqtd = sqtd; 2174 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2175 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2176 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2177 sqh->qh.qh_qtd.qtd_status = status; 2178 usb_syncmem(&sqh->dma, 2179 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2180 sizeof(sqh->qh.qh_qtd.qtd_status), 2181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2182 } 2183 2184 /* 2185 * Ensure that the HC has released all references to the QH. We do this 2186 * by asking for a Async Advance Doorbell interrupt and then we wait for 2187 * the interrupt. 2188 * To make this easier we first obtain exclusive use of the doorbell. 2189 */ 2190 Static void 2191 ehci_sync_hc(ehci_softc_t *sc) 2192 { 2193 int error __diagused; 2194 2195 KASSERT(mutex_owned(&sc->sc_lock)); 2196 2197 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2198 2199 if (sc->sc_dying) { 2200 DPRINTF("dying", 0, 0, 0, 0); 2201 return; 2202 } 2203 2204 /* ask for doorbell */ 2205 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2206 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2207 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2208 2209 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2210 2211 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2212 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2213 #ifdef DIAGNOSTIC 2214 if (error == EWOULDBLOCK) { 2215 printf("ehci_sync_hc: timed out\n"); 2216 } else if (error) { 2217 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2218 } 2219 #endif 2220 } 2221 2222 Static void 2223 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2224 { 2225 2226 KASSERT(mutex_owned(&sc->sc_lock)); 2227 2228 for (; itd != NULL; itd = itd->xfer_next) { 2229 struct ehci_soft_itd *prev = itd->frame_list.prev; 2230 2231 /* Unlink itd from hardware chain, or frame array */ 2232 if (prev == NULL) { /* We're at the table head */ 2233 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2234 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2235 usb_syncmem(&sc->sc_fldma, 2236 sizeof(ehci_link_t) * itd->slot, 2237 sizeof(ehci_link_t), 2238 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2239 2240 if (itd->frame_list.next != NULL) 2241 itd->frame_list.next->frame_list.prev = NULL; 2242 } else { 2243 /* XXX this part is untested... */ 2244 prev->itd.itd_next = itd->itd.itd_next; 2245 usb_syncmem(&itd->dma, 2246 itd->offs + offsetof(ehci_itd_t, itd_next), 2247 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2248 2249 prev->frame_list.next = itd->frame_list.next; 2250 if (itd->frame_list.next != NULL) 2251 itd->frame_list.next->frame_list.prev = prev; 2252 } 2253 } 2254 } 2255 2256 Static void 2257 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2258 { 2259 struct ehci_soft_itd *next; 2260 2261 mutex_enter(&sc->sc_lock); 2262 next = NULL; 2263 for (; itd != NULL; itd = next) { 2264 next = itd->xfer_next; 2265 ehci_free_itd_locked(sc, itd); 2266 } 2267 mutex_exit(&sc->sc_lock); 2268 } 2269 2270 Static void 2271 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2272 { 2273 2274 KASSERT(mutex_owned(&sc->sc_lock)); 2275 2276 for (; sitd != NULL; sitd = sitd->xfer_next) { 2277 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2278 2279 /* Unlink sitd from hardware chain, or frame array */ 2280 if (prev == NULL) { /* We're at the table head */ 2281 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2282 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2283 usb_syncmem(&sc->sc_fldma, 2284 sizeof(ehci_link_t) * sitd->slot, 2285 sizeof(ehci_link_t), 2286 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2287 2288 if (sitd->frame_list.next != NULL) 2289 sitd->frame_list.next->frame_list.prev = NULL; 2290 } else { 2291 /* XXX this part is untested... */ 2292 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2293 usb_syncmem(&sitd->dma, 2294 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2295 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2296 2297 prev->frame_list.next = sitd->frame_list.next; 2298 if (sitd->frame_list.next != NULL) 2299 sitd->frame_list.next->frame_list.prev = prev; 2300 } 2301 } 2302 } 2303 2304 Static void 2305 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2306 { 2307 2308 mutex_enter(&sc->sc_lock); 2309 struct ehci_soft_sitd *next = NULL; 2310 for (; sitd != NULL; sitd = next) { 2311 next = sitd->xfer_next; 2312 ehci_free_sitd_locked(sc, sitd); 2313 } 2314 mutex_exit(&sc->sc_lock); 2315 } 2316 2317 /***********/ 2318 2319 Static int 2320 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2321 void *buf, int buflen) 2322 { 2323 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2324 usb_hub_descriptor_t hubd; 2325 usb_port_status_t ps; 2326 uint16_t len, value, index; 2327 int l, totlen = 0; 2328 int port, i; 2329 uint32_t v; 2330 2331 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2332 2333 if (sc->sc_dying) 2334 return -1; 2335 2336 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2337 0, 0); 2338 2339 len = UGETW(req->wLength); 2340 value = UGETW(req->wValue); 2341 index = UGETW(req->wIndex); 2342 2343 #define C(x,y) ((x) | ((y) << 8)) 2344 switch (C(req->bRequest, req->bmRequestType)) { 2345 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2346 if (len == 0) 2347 break; 2348 switch (value) { 2349 #define sd ((usb_string_descriptor_t *)buf) 2350 case C(2, UDESC_STRING): 2351 /* Product */ 2352 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2353 break; 2354 #undef sd 2355 default: 2356 /* default from usbroothub */ 2357 return buflen; 2358 } 2359 break; 2360 2361 /* Hub requests */ 2362 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2363 break; 2364 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2365 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2366 value, 0, 0); 2367 if (index < 1 || index > sc->sc_noport) { 2368 return -1; 2369 } 2370 port = EHCI_PORTSC(index); 2371 v = EOREAD4(sc, port); 2372 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2373 v &= ~EHCI_PS_CLEAR; 2374 switch (value) { 2375 case UHF_PORT_ENABLE: 2376 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2377 break; 2378 case UHF_PORT_SUSPEND: 2379 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2380 break; 2381 v &= ~EHCI_PS_SUSP; 2382 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2383 /* see USB2 spec ch. 7.1.7.7 */ 2384 usb_delay_ms(&sc->sc_bus, 20); 2385 EOWRITE4(sc, port, v); 2386 usb_delay_ms(&sc->sc_bus, 2); 2387 #ifdef DEBUG 2388 v = EOREAD4(sc, port); 2389 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2390 printf("ehci: resume failed: %x\n", v); 2391 #endif 2392 break; 2393 case UHF_PORT_POWER: 2394 if (sc->sc_hasppc) 2395 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2396 break; 2397 case UHF_PORT_TEST: 2398 DPRINTF("clear port test %jd", index, 0, 0, 0); 2399 break; 2400 case UHF_PORT_INDICATOR: 2401 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2402 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2403 break; 2404 case UHF_C_PORT_CONNECTION: 2405 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2406 break; 2407 case UHF_C_PORT_ENABLE: 2408 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2409 break; 2410 case UHF_C_PORT_SUSPEND: 2411 /* how? */ 2412 break; 2413 case UHF_C_PORT_OVER_CURRENT: 2414 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2415 break; 2416 case UHF_C_PORT_RESET: 2417 sc->sc_isreset[index] = 0; 2418 break; 2419 default: 2420 return -1; 2421 } 2422 #if 0 2423 switch(value) { 2424 case UHF_C_PORT_CONNECTION: 2425 case UHF_C_PORT_ENABLE: 2426 case UHF_C_PORT_SUSPEND: 2427 case UHF_C_PORT_OVER_CURRENT: 2428 case UHF_C_PORT_RESET: 2429 default: 2430 break; 2431 } 2432 #endif 2433 break; 2434 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2435 if (len == 0) 2436 break; 2437 if ((value & 0xff) != 0) { 2438 return -1; 2439 } 2440 totlen = uimin(buflen, sizeof(hubd)); 2441 memcpy(&hubd, buf, totlen); 2442 hubd.bNbrPorts = sc->sc_noport; 2443 v = EOREAD4(sc, EHCI_HCSPARAMS); 2444 USETW(hubd.wHubCharacteristics, 2445 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2446 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2447 ? UHD_PORT_IND : 0); 2448 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2449 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2450 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2451 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2452 totlen = uimin(totlen, hubd.bDescLength); 2453 memcpy(buf, &hubd, totlen); 2454 break; 2455 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2456 if (len != 4) { 2457 return -1; 2458 } 2459 memset(buf, 0, len); /* ? XXX */ 2460 totlen = len; 2461 break; 2462 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2463 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2464 if (index < 1 || index > sc->sc_noport) { 2465 return -1; 2466 } 2467 if (len != 4) { 2468 return -1; 2469 } 2470 v = EOREAD4(sc, EHCI_PORTSC(index)); 2471 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2472 2473 i = UPS_HIGH_SPEED; 2474 if (sc->sc_flags & EHCIF_ETTF) { 2475 /* 2476 * If we are doing embedded transaction translation, 2477 * then directly attached LS/FS devices are reset by 2478 * the EHCI controller itself. PSPD is encoded 2479 * the same way as in USBSTATUS. 2480 */ 2481 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2482 } 2483 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2484 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2485 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2486 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2487 if (v & EHCI_PS_PR) i |= UPS_RESET; 2488 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2489 if (sc->sc_vendor_port_status) 2490 i = sc->sc_vendor_port_status(sc, v, i); 2491 USETW(ps.wPortStatus, i); 2492 i = 0; 2493 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2494 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2495 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2496 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2497 USETW(ps.wPortChange, i); 2498 totlen = uimin(len, sizeof(ps)); 2499 memcpy(buf, &ps, totlen); 2500 break; 2501 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2502 return -1; 2503 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2504 break; 2505 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2506 if (index < 1 || index > sc->sc_noport) { 2507 return -1; 2508 } 2509 port = EHCI_PORTSC(index); 2510 v = EOREAD4(sc, port); 2511 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2512 v &= ~EHCI_PS_CLEAR; 2513 switch(value) { 2514 case UHF_PORT_ENABLE: 2515 EOWRITE4(sc, port, v | EHCI_PS_PE); 2516 break; 2517 case UHF_PORT_SUSPEND: 2518 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2519 break; 2520 case UHF_PORT_RESET: 2521 DPRINTF("reset port %jd", index, 0, 0, 0); 2522 if (EHCI_PS_IS_LOWSPEED(v) 2523 && sc->sc_ncomp > 0 2524 && !(sc->sc_flags & EHCIF_ETTF)) { 2525 /* 2526 * Low speed device on non-ETTF controller or 2527 * unaccompanied controller, give up ownership. 2528 */ 2529 ehci_disown(sc, index, 1); 2530 break; 2531 } 2532 /* Start reset sequence. */ 2533 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2534 EOWRITE4(sc, port, v | EHCI_PS_PR); 2535 /* Wait for reset to complete. */ 2536 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2537 if (sc->sc_dying) { 2538 return -1; 2539 } 2540 /* 2541 * An embedded transaction translator will automatically 2542 * terminate the reset sequence so there's no need to 2543 * it. 2544 */ 2545 v = EOREAD4(sc, port); 2546 if (v & EHCI_PS_PR) { 2547 /* Terminate reset sequence. */ 2548 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2549 /* Wait for HC to complete reset. */ 2550 usb_delay_ms(&sc->sc_bus, 2551 EHCI_PORT_RESET_COMPLETE); 2552 if (sc->sc_dying) { 2553 return -1; 2554 } 2555 } 2556 2557 v = EOREAD4(sc, port); 2558 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2559 if (v & EHCI_PS_PR) { 2560 printf("%s: port reset timeout\n", 2561 device_xname(sc->sc_dev)); 2562 return USBD_TIMEOUT; 2563 } 2564 if (!(v & EHCI_PS_PE)) { 2565 /* Not a high speed device, give up ownership.*/ 2566 ehci_disown(sc, index, 0); 2567 break; 2568 } 2569 sc->sc_isreset[index] = 1; 2570 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2571 v, 0, 0); 2572 break; 2573 case UHF_PORT_POWER: 2574 DPRINTF("set port power %jd (has PPC = %jd)", index, 2575 sc->sc_hasppc, 0, 0); 2576 if (sc->sc_hasppc) 2577 EOWRITE4(sc, port, v | EHCI_PS_PP); 2578 break; 2579 case UHF_PORT_TEST: 2580 DPRINTF("set port test %jd", index, 0, 0, 0); 2581 break; 2582 case UHF_PORT_INDICATOR: 2583 DPRINTF("set port ind %jd", index, 0, 0, 0); 2584 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2585 break; 2586 default: 2587 return -1; 2588 } 2589 break; 2590 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2591 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2592 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2593 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2594 break; 2595 default: 2596 /* default from usbroothub */ 2597 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2598 2599 return buflen; 2600 } 2601 2602 DPRINTF("returning %jd", totlen, 0, 0, 0); 2603 2604 return totlen; 2605 } 2606 2607 /* 2608 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2609 * 2610 * This pile of garbage below works around the following problem without 2611 * holding boots with no hand-over devices present, while penalising 2612 * boots where the first ehci probe hands off devices with a 5 second 2613 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2614 * for RB_SINGLE, but the same basic issue exists. 2615 * 2616 * The way ehci hand-off works, the companion controller does not get the 2617 * device until after its' initial bus explore, so the reference dropped 2618 * after the first explore is not enough. 5 seconds should be enough, 2619 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2620 * 2621 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2622 * if the callback is scheduled. CO_DONE is set when the callout has 2623 * called config_pending_decr(). 2624 * 2625 * There's a mutex, a cv and a callout here, and we delay detach if the 2626 * callout has been set. 2627 */ 2628 #ifndef EHCI_DISOWN_DELAY_SECONDS 2629 #define EHCI_DISOWN_DELAY_SECONDS 5 2630 #endif 2631 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2632 2633 static void 2634 ehci_disown_callback(void *arg) 2635 { 2636 ehci_softc_t *sc = arg; 2637 2638 config_pending_decr(sc->sc_dev); 2639 2640 mutex_enter(&sc->sc_complock); 2641 KASSERT(sc->sc_comp_state == CO_SCHED); 2642 sc->sc_comp_state = CO_DONE; 2643 cv_signal(&sc->sc_compcv); 2644 mutex_exit(&sc->sc_complock); 2645 } 2646 2647 static void 2648 ehci_disown_sched_callback(ehci_softc_t *sc) 2649 { 2650 extern bool root_is_mounted; 2651 2652 mutex_enter(&sc->sc_complock); 2653 2654 if (root_is_mounted || 2655 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2656 sc->sc_comp_state != CO_EARLY) { 2657 mutex_exit(&sc->sc_complock); 2658 return; 2659 } 2660 2661 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2662 ehci_disown_callback, &sc->sc_dev); 2663 sc->sc_comp_state = CO_SCHED; 2664 2665 mutex_exit(&sc->sc_complock); 2666 2667 config_pending_incr(sc->sc_dev); 2668 aprint_normal("delaying %s by %u seconds due to USB owner change.", 2669 (boothowto & RB_ASKNAME) == 0 ? "ask root" : "single user", 2670 ehci_disown_delay_seconds); 2671 } 2672 2673 Static void 2674 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2675 { 2676 int port; 2677 uint32_t v; 2678 2679 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2680 2681 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2682 if (sc->sc_npcomp != 0) { 2683 int i = (index-1) / sc->sc_npcomp; 2684 if (i < sc->sc_ncomp) { 2685 ehci_disown_sched_callback(sc); 2686 #ifdef DIAGNOSTIC 2687 printf("%s: handing over %s speed device on " 2688 "port %d to %s\n", 2689 device_xname(sc->sc_dev), 2690 lowspeed ? "low" : "full", 2691 index, sc->sc_comps[i] ? 2692 device_xname(sc->sc_comps[i]) : 2693 "companion controller"); 2694 } else { 2695 printf("%s: strange port\n", 2696 device_xname(sc->sc_dev)); 2697 #endif 2698 } 2699 } else { 2700 #ifdef DIAGNOSTIC 2701 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2702 #endif 2703 } 2704 port = EHCI_PORTSC(index); 2705 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2706 EOWRITE4(sc, port, v | EHCI_PS_PO); 2707 } 2708 2709 Static usbd_status 2710 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2711 { 2712 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2713 usbd_status err; 2714 2715 /* Insert last in queue. */ 2716 mutex_enter(&sc->sc_lock); 2717 err = usb_insert_transfer(xfer); 2718 mutex_exit(&sc->sc_lock); 2719 if (err) 2720 return err; 2721 2722 /* Pipe isn't running, start first */ 2723 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2724 } 2725 2726 Static usbd_status 2727 ehci_root_intr_start(struct usbd_xfer *xfer) 2728 { 2729 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2730 const bool polling = sc->sc_bus.ub_usepolling; 2731 2732 if (sc->sc_dying) 2733 return USBD_IOERROR; 2734 2735 if (!polling) 2736 mutex_enter(&sc->sc_lock); 2737 sc->sc_intrxfer = xfer; 2738 if (!polling) 2739 mutex_exit(&sc->sc_lock); 2740 2741 return USBD_IN_PROGRESS; 2742 } 2743 2744 /* Abort a root interrupt request. */ 2745 Static void 2746 ehci_root_intr_abort(struct usbd_xfer *xfer) 2747 { 2748 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2749 2750 KASSERT(mutex_owned(&sc->sc_lock)); 2751 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2752 2753 sc->sc_intrxfer = NULL; 2754 2755 xfer->ux_status = USBD_CANCELLED; 2756 usb_transfer_complete(xfer); 2757 } 2758 2759 /* Close the root pipe. */ 2760 Static void 2761 ehci_root_intr_close(struct usbd_pipe *pipe) 2762 { 2763 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2764 2765 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2766 2767 KASSERT(mutex_owned(&sc->sc_lock)); 2768 2769 sc->sc_intrxfer = NULL; 2770 } 2771 2772 Static void 2773 ehci_root_intr_done(struct usbd_xfer *xfer) 2774 { 2775 } 2776 2777 /************************/ 2778 2779 Static ehci_soft_qh_t * 2780 ehci_alloc_sqh(ehci_softc_t *sc) 2781 { 2782 ehci_soft_qh_t *sqh; 2783 usbd_status err; 2784 int i, offs; 2785 usb_dma_t dma; 2786 2787 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2788 2789 mutex_enter(&sc->sc_lock); 2790 if (sc->sc_freeqhs == NULL) { 2791 DPRINTF("allocating chunk", 0, 0, 0, 0); 2792 mutex_exit(&sc->sc_lock); 2793 2794 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2795 EHCI_PAGE_SIZE, &dma); 2796 #ifdef EHCI_DEBUG 2797 if (err) 2798 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2799 #endif 2800 if (err) 2801 return NULL; 2802 2803 mutex_enter(&sc->sc_lock); 2804 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2805 offs = i * EHCI_SQH_SIZE; 2806 sqh = KERNADDR(&dma, offs); 2807 sqh->physaddr = DMAADDR(&dma, offs); 2808 sqh->dma = dma; 2809 sqh->offs = offs; 2810 sqh->next = sc->sc_freeqhs; 2811 sc->sc_freeqhs = sqh; 2812 } 2813 } 2814 sqh = sc->sc_freeqhs; 2815 sc->sc_freeqhs = sqh->next; 2816 mutex_exit(&sc->sc_lock); 2817 2818 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2819 sqh->next = NULL; 2820 return sqh; 2821 } 2822 2823 Static void 2824 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2825 { 2826 KASSERT(mutex_owned(&sc->sc_lock)); 2827 2828 sqh->next = sc->sc_freeqhs; 2829 sc->sc_freeqhs = sqh; 2830 } 2831 2832 Static ehci_soft_qtd_t * 2833 ehci_alloc_sqtd(ehci_softc_t *sc) 2834 { 2835 ehci_soft_qtd_t *sqtd = NULL; 2836 usbd_status err; 2837 int i, offs; 2838 usb_dma_t dma; 2839 2840 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2841 2842 mutex_enter(&sc->sc_lock); 2843 if (sc->sc_freeqtds == NULL) { 2844 DPRINTF("allocating chunk", 0, 0, 0, 0); 2845 mutex_exit(&sc->sc_lock); 2846 2847 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2848 EHCI_PAGE_SIZE, &dma); 2849 #ifdef EHCI_DEBUG 2850 if (err) 2851 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2852 #endif 2853 if (err) 2854 goto done; 2855 2856 mutex_enter(&sc->sc_lock); 2857 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2858 offs = i * EHCI_SQTD_SIZE; 2859 sqtd = KERNADDR(&dma, offs); 2860 sqtd->physaddr = DMAADDR(&dma, offs); 2861 sqtd->dma = dma; 2862 sqtd->offs = offs; 2863 2864 sqtd->nextqtd = sc->sc_freeqtds; 2865 sc->sc_freeqtds = sqtd; 2866 } 2867 } 2868 2869 sqtd = sc->sc_freeqtds; 2870 sc->sc_freeqtds = sqtd->nextqtd; 2871 mutex_exit(&sc->sc_lock); 2872 2873 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2874 sqtd->nextqtd = NULL; 2875 sqtd->xfer = NULL; 2876 2877 done: 2878 return sqtd; 2879 } 2880 2881 Static void 2882 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2883 { 2884 2885 mutex_enter(&sc->sc_lock); 2886 sqtd->nextqtd = sc->sc_freeqtds; 2887 sc->sc_freeqtds = sqtd; 2888 mutex_exit(&sc->sc_lock); 2889 } 2890 2891 Static int 2892 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2893 int alen, int rd, ehci_soft_qtd_t **sp) 2894 { 2895 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2896 uint16_t flags = xfer->ux_flags; 2897 2898 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2899 2900 ASSERT_SLEEPABLE(); 2901 KASSERT(sp); 2902 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2903 2904 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2905 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2906 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2907 KM_SLEEP); 2908 exfer->ex_nsqtd = nsqtd; 2909 2910 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2911 alen, nsqtd, flags); 2912 2913 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2914 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2915 if (cur == NULL) 2916 goto nomem; 2917 exfer->ex_sqtds[j++] = cur; 2918 2919 cur->xfer = xfer; 2920 cur->len = 0; 2921 2922 } 2923 2924 *sp = exfer->ex_sqtds[0]; 2925 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2926 2927 return 0; 2928 2929 nomem: 2930 ehci_free_sqtds(sc, exfer); 2931 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2932 DPRINTF("no memory", 0, 0, 0, 0); 2933 return ENOMEM; 2934 } 2935 2936 Static void 2937 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2938 { 2939 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2940 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2941 2942 mutex_enter(&sc->sc_lock); 2943 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2944 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2945 2946 if (sqtd == NULL) 2947 break; 2948 2949 sqtd->nextqtd = sc->sc_freeqtds; 2950 sc->sc_freeqtds = sqtd; 2951 } 2952 mutex_exit(&sc->sc_lock); 2953 } 2954 2955 Static void 2956 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2957 { 2958 if (prev) { 2959 prev->nextqtd = sqtd; 2960 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2961 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2962 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2963 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2964 } 2965 } 2966 2967 Static void 2968 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2969 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2970 { 2971 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2972 usb_dma_t *dma = &xfer->ux_dmabuf; 2973 uint16_t flags = xfer->ux_flags; 2974 ehci_soft_qtd_t *sqtd, *prev; 2975 int tog = *toggle; 2976 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2977 int len = length; 2978 2979 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2980 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2981 len, isread, tog); 2982 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2983 0, 0, 0); 2984 2985 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2986 2987 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2988 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2989 EHCI_QTD_SET_CERR(3) 2990 ; 2991 2992 sqtd = prev = NULL; 2993 size_t curoffs = 0; 2994 size_t j = 0; 2995 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2996 sqtd = exfer->ex_sqtds[j++]; 2997 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 2998 (uintptr_t)prev, 0); 2999 3000 /* 3001 * The EHCI hardware can handle at most 5 pages and they do 3002 * not have to be contiguous 3003 */ 3004 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3005 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3006 size_t curlen = len; 3007 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3008 /* must use multiple TDs, fill as much as possible. */ 3009 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3010 3011 /* the length must be a multiple of the max size */ 3012 curlen -= curlen % mps; 3013 } 3014 KASSERT(curlen != 0); 3015 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3016 curoffs, 0); 3017 3018 /* Fill the qTD */ 3019 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3020 sqtd->qtd.qtd_status = htole32( 3021 qtdstatus | 3022 EHCI_QTD_SET_BYTES(curlen) | 3023 EHCI_QTD_SET_TOGGLE(tog)); 3024 3025 /* Find number of pages we'll be using, insert dma addresses */ 3026 size_t pages = EHCI_NPAGES(curlen); 3027 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3028 size_t pageoffs = EHCI_PAGE(curoffs); 3029 for (size_t i = 0; i < pages; i++) { 3030 paddr_t a = DMAADDR(dma, 3031 pageoffs + i * EHCI_PAGE_SIZE); 3032 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 3033 /* Cast up to avoid compiler warnings */ 3034 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 3035 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3036 i, pages, 3037 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3038 le32toh(sqtd->qtd.qtd_buffer[i])); 3039 } 3040 /* First buffer pointer requires a page offset to start at */ 3041 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3042 3043 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3044 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3045 3046 sqtd->len = curlen; 3047 3048 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3049 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3050 3051 ehci_append_sqtd(sqtd, prev); 3052 3053 if (((curlen + mps - 1) / mps) & 1) { 3054 tog ^= 1; 3055 } 3056 3057 curoffs += curlen; 3058 len -= curlen; 3059 } 3060 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3061 xfer, length, len, mps, exfer->ex_nsqtd, j); 3062 3063 if (!isread && 3064 (flags & USBD_FORCE_SHORT_XFER) && 3065 length % mps == 0) { 3066 /* Force a 0 length transfer at the end. */ 3067 3068 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3069 exfer->ex_nsqtd); 3070 prev = sqtd; 3071 sqtd = exfer->ex_sqtds[j++]; 3072 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3073 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3074 sqtd->qtd.qtd_status = htole32( 3075 qtdstatus | 3076 EHCI_QTD_SET_BYTES(0) | 3077 EHCI_QTD_SET_TOGGLE(tog)); 3078 3079 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3080 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3081 3082 ehci_append_sqtd(sqtd, prev); 3083 tog ^= 1; 3084 } 3085 3086 *lsqtd = sqtd; 3087 *toggle = tog; 3088 } 3089 3090 Static ehci_soft_itd_t * 3091 ehci_alloc_itd(ehci_softc_t *sc) 3092 { 3093 struct ehci_soft_itd *itd, *freeitd; 3094 usbd_status err; 3095 usb_dma_t dma; 3096 3097 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3098 3099 mutex_enter(&sc->sc_lock); 3100 3101 freeitd = LIST_FIRST(&sc->sc_freeitds); 3102 if (freeitd == NULL) { 3103 DPRINTF("allocating chunk", 0, 0, 0, 0); 3104 mutex_exit(&sc->sc_lock); 3105 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3106 EHCI_PAGE_SIZE, &dma); 3107 3108 if (err) { 3109 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3110 return NULL; 3111 } 3112 mutex_enter(&sc->sc_lock); 3113 3114 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3115 int offs = i * EHCI_ITD_SIZE; 3116 itd = KERNADDR(&dma, offs); 3117 itd->physaddr = DMAADDR(&dma, offs); 3118 itd->dma = dma; 3119 itd->offs = offs; 3120 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3121 } 3122 freeitd = LIST_FIRST(&sc->sc_freeitds); 3123 } 3124 3125 itd = freeitd; 3126 LIST_REMOVE(itd, free_list); 3127 mutex_exit(&sc->sc_lock); 3128 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3129 3130 itd->frame_list.next = NULL; 3131 itd->frame_list.prev = NULL; 3132 itd->xfer_next = NULL; 3133 itd->slot = 0; 3134 3135 return itd; 3136 } 3137 3138 Static ehci_soft_sitd_t * 3139 ehci_alloc_sitd(ehci_softc_t *sc) 3140 { 3141 struct ehci_soft_sitd *sitd, *freesitd; 3142 usbd_status err; 3143 int i, offs; 3144 usb_dma_t dma; 3145 3146 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3147 3148 mutex_enter(&sc->sc_lock); 3149 freesitd = LIST_FIRST(&sc->sc_freesitds); 3150 if (freesitd == NULL) { 3151 DPRINTF("allocating chunk", 0, 0, 0, 0); 3152 mutex_exit(&sc->sc_lock); 3153 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3154 EHCI_PAGE_SIZE, &dma); 3155 3156 if (err) { 3157 DPRINTF("alloc returned %jd", err, 0, 0, 3158 0); 3159 return NULL; 3160 } 3161 3162 mutex_enter(&sc->sc_lock); 3163 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3164 offs = i * EHCI_SITD_SIZE; 3165 sitd = KERNADDR(&dma, offs); 3166 sitd->physaddr = DMAADDR(&dma, offs); 3167 sitd->dma = dma; 3168 sitd->offs = offs; 3169 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3170 } 3171 freesitd = LIST_FIRST(&sc->sc_freesitds); 3172 } 3173 3174 sitd = freesitd; 3175 LIST_REMOVE(sitd, free_list); 3176 mutex_exit(&sc->sc_lock); 3177 3178 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3179 3180 sitd->frame_list.next = NULL; 3181 sitd->frame_list.prev = NULL; 3182 sitd->xfer_next = NULL; 3183 sitd->slot = 0; 3184 3185 return sitd; 3186 } 3187 3188 /****************/ 3189 3190 /* 3191 * Close a reqular pipe. 3192 * Assumes that there are no pending transactions. 3193 */ 3194 Static void 3195 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3196 { 3197 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3198 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3199 ehci_soft_qh_t *sqh = epipe->sqh; 3200 3201 KASSERT(mutex_owned(&sc->sc_lock)); 3202 3203 ehci_rem_qh(sc, sqh, head); 3204 ehci_free_sqh(sc, epipe->sqh); 3205 } 3206 3207 /* 3208 * Cancel or timeout a device request. We have two cases to deal with 3209 * 3210 * 1) A driver wants to stop scheduled or inflight transfers 3211 * 2) A transfer has timed out 3212 * 3213 * have (partially) happened since the hardware runs concurrently. 3214 * 3215 * Transfer state is protected by the bus lock and we set the transfer status 3216 * as soon as either of the above happens (with bus lock held). 3217 * 3218 * Then we arrange for the hardware to tells us that it is not still 3219 * processing the TDs by setting the QH halted bit and wait for the ehci 3220 * door bell 3221 */ 3222 Static void 3223 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3224 { 3225 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3226 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3227 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3228 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3229 ehci_soft_qh_t *sqh = epipe->sqh; 3230 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3231 ehci_physaddr_t cur; 3232 uint32_t qhstatus; 3233 int hit; 3234 3235 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 3236 "invalid status for abort: %d", (int)status); 3237 3238 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3239 3240 KASSERT(mutex_owned(&sc->sc_lock)); 3241 ASSERT_SLEEPABLE(); 3242 3243 if (status == USBD_CANCELLED) { 3244 /* 3245 * We are synchronously aborting. Try to stop the 3246 * callout and task, but if we can't, wait for them to 3247 * complete. 3248 */ 3249 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3250 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 3251 USB_TASKQ_HC, &sc->sc_lock); 3252 } else { 3253 /* Otherwise, we are timing out. */ 3254 KASSERT(status == USBD_TIMEOUT); 3255 } 3256 3257 /* 3258 * The xfer cannot have been cancelled already. It is the 3259 * responsibility of the caller of usbd_abort_pipe not to try 3260 * to abort a pipe multiple times, whether concurrently or 3261 * sequentially. 3262 */ 3263 KASSERT(xfer->ux_status != USBD_CANCELLED); 3264 3265 /* Only the timeout, which runs only once, can time it out. */ 3266 KASSERT(xfer->ux_status != USBD_TIMEOUT); 3267 3268 /* If anyone else beat us, we're done. */ 3269 if (xfer->ux_status != USBD_IN_PROGRESS) 3270 return; 3271 3272 /* We beat everyone else. Claim the status. */ 3273 xfer->ux_status = status; 3274 3275 /* 3276 * If we're dying, skip the hardware action and just notify the 3277 * software that we're done. 3278 */ 3279 if (sc->sc_dying) { 3280 goto dying; 3281 } 3282 3283 /* 3284 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3285 */ 3286 ehci_del_intr_list(sc, exfer); 3287 3288 usb_syncmem(&sqh->dma, 3289 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3290 sizeof(sqh->qh.qh_qtd.qtd_status), 3291 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3292 qhstatus = sqh->qh.qh_qtd.qtd_status; 3293 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3294 usb_syncmem(&sqh->dma, 3295 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3296 sizeof(sqh->qh.qh_qtd.qtd_status), 3297 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3298 3299 if (exfer->ex_type == EX_CTRL) { 3300 fsqtd = exfer->ex_setup; 3301 lsqtd = exfer->ex_status; 3302 } else { 3303 fsqtd = exfer->ex_sqtdstart; 3304 lsqtd = exfer->ex_sqtdend; 3305 } 3306 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3307 usb_syncmem(&sqtd->dma, 3308 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3309 sizeof(sqtd->qtd.qtd_status), 3310 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3311 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3312 usb_syncmem(&sqtd->dma, 3313 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3314 sizeof(sqtd->qtd.qtd_status), 3315 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3316 if (sqtd == lsqtd) 3317 break; 3318 } 3319 3320 /* 3321 * HC Step 2: Wait until we know hardware has finished any possible 3322 * use of the xfer. 3323 */ 3324 ehci_sync_hc(sc); 3325 3326 /* 3327 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3328 * The complication here is that the hardware may have executed 3329 * beyond the xfer we're trying to abort. So as we're scanning 3330 * the TDs of this xfer we check if the hardware points to 3331 * any of them. 3332 */ 3333 3334 usb_syncmem(&sqh->dma, 3335 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3336 sizeof(sqh->qh.qh_curqtd), 3337 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3338 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3339 hit = 0; 3340 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3341 hit |= cur == sqtd->physaddr; 3342 if (sqtd == lsqtd) 3343 break; 3344 } 3345 sqtd = sqtd->nextqtd; 3346 /* Zap curqtd register if hardware pointed inside the xfer. */ 3347 if (hit && sqtd != NULL) { 3348 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3349 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3350 usb_syncmem(&sqh->dma, 3351 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3352 sizeof(sqh->qh.qh_curqtd), 3353 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3354 sqh->qh.qh_qtd.qtd_status = qhstatus; 3355 usb_syncmem(&sqh->dma, 3356 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3357 sizeof(sqh->qh.qh_qtd.qtd_status), 3358 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3359 } else { 3360 DPRINTF("no hit", 0, 0, 0, 0); 3361 usb_syncmem(&sqh->dma, 3362 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3363 sizeof(sqh->qh.qh_curqtd), 3364 BUS_DMASYNC_PREREAD); 3365 } 3366 3367 /* 3368 * Final step: Notify completion to waiting xfers. 3369 */ 3370 dying: 3371 #ifdef DIAGNOSTIC 3372 exfer->ex_isdone = true; 3373 #endif 3374 usb_transfer_complete(xfer); 3375 DPRINTFN(14, "end", 0, 0, 0, 0); 3376 3377 KASSERT(mutex_owned(&sc->sc_lock)); 3378 } 3379 3380 Static void 3381 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3382 { 3383 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3384 ehci_isoc_trans_t trans_status; 3385 struct ehci_xfer *exfer; 3386 ehci_softc_t *sc; 3387 struct ehci_soft_itd *itd; 3388 struct ehci_soft_sitd *sitd; 3389 int i; 3390 3391 KASSERTMSG(status == USBD_CANCELLED, 3392 "invalid status for abort: %d", (int)status); 3393 3394 exfer = EHCI_XFER2EXFER(xfer); 3395 sc = EHCI_XFER2SC(xfer); 3396 3397 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3398 (uintptr_t)xfer->ux_pipe, 0, 0); 3399 3400 KASSERT(mutex_owned(&sc->sc_lock)); 3401 ASSERT_SLEEPABLE(); 3402 3403 /* No timeout or task here. */ 3404 3405 /* 3406 * The xfer cannot have been cancelled already. It is the 3407 * responsibility of the caller of usbd_abort_pipe not to try 3408 * to abort a pipe multiple times, whether concurrently or 3409 * sequentially. 3410 */ 3411 KASSERT(xfer->ux_status != USBD_CANCELLED); 3412 3413 /* If anyone else beat us, we're done. */ 3414 if (xfer->ux_status != USBD_IN_PROGRESS) 3415 return; 3416 3417 /* We beat everyone else. Claim the status. */ 3418 xfer->ux_status = status; 3419 3420 /* 3421 * If we're dying, skip the hardware action and just notify the 3422 * software that we're done. 3423 */ 3424 if (sc->sc_dying) { 3425 goto dying; 3426 } 3427 3428 /* 3429 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3430 */ 3431 ehci_del_intr_list(sc, exfer); 3432 3433 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3434 for (itd = exfer->ex_itdstart; itd != NULL; 3435 itd = itd->xfer_next) { 3436 usb_syncmem(&itd->dma, 3437 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3438 sizeof(itd->itd.itd_ctl), 3439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3440 3441 for (i = 0; i < 8; i++) { 3442 trans_status = le32toh(itd->itd.itd_ctl[i]); 3443 trans_status &= ~EHCI_ITD_ACTIVE; 3444 itd->itd.itd_ctl[i] = htole32(trans_status); 3445 } 3446 3447 usb_syncmem(&itd->dma, 3448 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3449 sizeof(itd->itd.itd_ctl), 3450 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3451 } 3452 } else { 3453 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3454 sitd = sitd->xfer_next) { 3455 usb_syncmem(&sitd->dma, 3456 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3457 sizeof(sitd->sitd.sitd_buffer), 3458 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3459 3460 trans_status = le32toh(sitd->sitd.sitd_trans); 3461 trans_status &= ~EHCI_SITD_ACTIVE; 3462 sitd->sitd.sitd_trans = htole32(trans_status); 3463 3464 usb_syncmem(&sitd->dma, 3465 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3466 sizeof(sitd->sitd.sitd_buffer), 3467 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3468 } 3469 } 3470 3471 dying: 3472 #ifdef DIAGNOSTIC 3473 exfer->ex_isdone = true; 3474 #endif 3475 usb_transfer_complete(xfer); 3476 DPRINTFN(14, "end", 0, 0, 0, 0); 3477 3478 KASSERT(mutex_owned(&sc->sc_lock)); 3479 } 3480 3481 Static void 3482 ehci_timeout(void *addr) 3483 { 3484 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3485 struct usbd_xfer *xfer = addr; 3486 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3487 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3488 3489 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3490 #ifdef EHCI_DEBUG 3491 if (ehcidebug >= 2) { 3492 struct usbd_pipe *pipe = xfer->ux_pipe; 3493 usbd_dump_pipe(pipe); 3494 } 3495 #endif 3496 3497 mutex_enter(&sc->sc_lock); 3498 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 3499 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3500 mutex_exit(&sc->sc_lock); 3501 } 3502 3503 Static void 3504 ehci_timeout_task(void *addr) 3505 { 3506 struct usbd_xfer *xfer = addr; 3507 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3508 3509 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3510 3511 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3512 3513 mutex_enter(&sc->sc_lock); 3514 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3515 mutex_exit(&sc->sc_lock); 3516 } 3517 3518 /************************/ 3519 3520 Static int 3521 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3522 { 3523 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3524 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3525 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3526 usb_device_request_t *req = &xfer->ux_request; 3527 ehci_soft_qtd_t *setup, *status, *next; 3528 int isread = req->bmRequestType & UT_READ; 3529 int len = xfer->ux_bufsize; 3530 int err; 3531 3532 exfer->ex_type = EX_CTRL; 3533 exfer->ex_status = NULL; 3534 exfer->ex_data = NULL; 3535 exfer->ex_setup = ehci_alloc_sqtd(sc); 3536 if (exfer->ex_setup == NULL) { 3537 err = ENOMEM; 3538 goto bad1; 3539 } 3540 exfer->ex_status = ehci_alloc_sqtd(sc); 3541 if (exfer->ex_status == NULL) { 3542 err = ENOMEM; 3543 goto bad2; 3544 } 3545 setup = exfer->ex_setup; 3546 status = exfer->ex_status; 3547 exfer->ex_nsqtd = 0; 3548 next = status; 3549 /* Set up data transaction */ 3550 if (len != 0) { 3551 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3552 &exfer->ex_data); 3553 if (err) 3554 goto bad3; 3555 next = exfer->ex_data; 3556 } 3557 3558 /* Clear toggle */ 3559 setup->qtd.qtd_status = htole32( 3560 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3561 EHCI_QTD_SET_TOGGLE(0) | 3562 EHCI_QTD_SET_BYTES(sizeof(*req)) 3563 ); 3564 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3565 setup->qtd.qtd_buffer_hi[0] = 0; 3566 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3567 setup->nextqtd = next; 3568 setup->xfer = xfer; 3569 setup->len = sizeof(*req); 3570 3571 status->qtd.qtd_status = htole32( 3572 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3573 EHCI_QTD_SET_TOGGLE(1) | 3574 EHCI_QTD_IOC 3575 ); 3576 status->qtd.qtd_buffer[0] = 0; 3577 status->qtd.qtd_buffer_hi[0] = 0; 3578 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3579 status->nextqtd = NULL; 3580 status->xfer = xfer; 3581 status->len = 0; 3582 3583 return 0; 3584 bad3: 3585 ehci_free_sqtd(sc, exfer->ex_status); 3586 bad2: 3587 ehci_free_sqtd(sc, exfer->ex_setup); 3588 bad1: 3589 return err; 3590 } 3591 3592 Static void 3593 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3594 { 3595 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3596 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3597 3598 KASSERT(ex->ex_type == EX_CTRL); 3599 3600 ehci_free_sqtd(sc, ex->ex_setup); 3601 ehci_free_sqtd(sc, ex->ex_status); 3602 ehci_free_sqtds(sc, ex); 3603 if (ex->ex_nsqtd) 3604 kmem_free(ex->ex_sqtds, 3605 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3606 } 3607 3608 Static usbd_status 3609 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3610 { 3611 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3612 usbd_status err; 3613 3614 /* Insert last in queue. */ 3615 mutex_enter(&sc->sc_lock); 3616 err = usb_insert_transfer(xfer); 3617 mutex_exit(&sc->sc_lock); 3618 if (err) 3619 return err; 3620 3621 /* Pipe isn't running, start first */ 3622 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3623 } 3624 3625 Static usbd_status 3626 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3627 { 3628 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3629 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3630 usb_device_request_t *req = &xfer->ux_request; 3631 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3632 ehci_soft_qtd_t *setup, *status, *next; 3633 ehci_soft_qh_t *sqh; 3634 const bool polling = sc->sc_bus.ub_usepolling; 3635 3636 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3637 3638 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3639 3640 if (sc->sc_dying) 3641 return USBD_IOERROR; 3642 3643 const int isread = req->bmRequestType & UT_READ; 3644 const int len = UGETW(req->wLength); 3645 3646 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3647 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3648 UGETW(req->wIndex)); 3649 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3650 len, epipe->pipe.up_dev->ud_addr, 3651 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3652 3653 sqh = epipe->sqh; 3654 3655 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3656 "address QH %" __PRIuBIT " pipe %d\n", 3657 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3658 epipe->pipe.up_dev->ud_addr); 3659 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3660 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3661 "MPS QH %" __PRIuBIT " pipe %d\n", 3662 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3663 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3664 3665 setup = exfer->ex_setup; 3666 status = exfer->ex_status; 3667 3668 DPRINTF("setup %#jx status %#jx data %#jx", 3669 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3670 KASSERTMSG(setup != NULL && status != NULL, 3671 "Failed memory allocation, setup %p status %p", 3672 setup, status); 3673 3674 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3675 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3676 3677 /* Clear toggle */ 3678 setup->qtd.qtd_status &= ~htole32( 3679 EHCI_QTD_STATUS_MASK | 3680 EHCI_QTD_BYTES_MASK | 3681 EHCI_QTD_TOGGLE_MASK | 3682 EHCI_QTD_CERR_MASK 3683 ); 3684 setup->qtd.qtd_status |= htole32( 3685 EHCI_QTD_ACTIVE | 3686 EHCI_QTD_SET_CERR(3) | 3687 EHCI_QTD_SET_TOGGLE(0) | 3688 EHCI_QTD_SET_BYTES(sizeof(*req)) 3689 ); 3690 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3691 setup->qtd.qtd_buffer_hi[0] = 0; 3692 3693 next = status; 3694 status->qtd.qtd_status &= ~htole32( 3695 EHCI_QTD_STATUS_MASK | 3696 EHCI_QTD_PID_MASK | 3697 EHCI_QTD_BYTES_MASK | 3698 EHCI_QTD_TOGGLE_MASK | 3699 EHCI_QTD_CERR_MASK 3700 ); 3701 status->qtd.qtd_status |= htole32( 3702 EHCI_QTD_ACTIVE | 3703 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3704 EHCI_QTD_SET_CERR(3) | 3705 EHCI_QTD_SET_TOGGLE(1) | 3706 EHCI_QTD_SET_BYTES(0) | 3707 EHCI_QTD_IOC 3708 ); 3709 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3710 3711 KASSERT(exfer->ex_isdone); 3712 #ifdef DIAGNOSTIC 3713 exfer->ex_isdone = false; 3714 #endif 3715 3716 /* Set up data transaction */ 3717 if (len != 0) { 3718 ehci_soft_qtd_t *end; 3719 3720 /* Start toggle at 1. */ 3721 int toggle = 1; 3722 next = exfer->ex_data; 3723 KASSERTMSG(next != NULL, "Failed memory allocation"); 3724 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3725 end->nextqtd = status; 3726 end->qtd.qtd_next = end->qtd.qtd_altnext = 3727 htole32(status->physaddr); 3728 3729 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3730 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3731 3732 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3733 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3734 } 3735 3736 setup->nextqtd = next; 3737 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3738 3739 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3740 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3741 3742 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3743 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3744 3745 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3746 3747 #ifdef EHCI_DEBUG 3748 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3749 ehci_dump_sqh(sqh); 3750 ehci_dump_sqtds(setup); 3751 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3752 #endif 3753 3754 if (!polling) 3755 mutex_enter(&sc->sc_lock); 3756 3757 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3758 ehci_set_qh_qtd(sqh, setup); 3759 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3760 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3761 ehci_timeout, xfer); 3762 } 3763 ehci_add_intr_list(sc, exfer); 3764 xfer->ux_status = USBD_IN_PROGRESS; 3765 if (!polling) 3766 mutex_exit(&sc->sc_lock); 3767 3768 #if 0 3769 #ifdef EHCI_DEBUG 3770 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3771 // delay(10000); 3772 ehci_dump_regs(sc); 3773 ehci_dump_sqh(sc->sc_async_head); 3774 ehci_dump_sqh(sqh); 3775 ehci_dump_sqtds(setup); 3776 #endif 3777 #endif 3778 3779 return USBD_IN_PROGRESS; 3780 } 3781 3782 Static void 3783 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3784 { 3785 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3786 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3787 usb_device_request_t *req = &xfer->ux_request; 3788 int len = UGETW(req->wLength); 3789 int rd = req->bmRequestType & UT_READ; 3790 3791 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3792 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3793 3794 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3795 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3796 3797 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3798 BUS_DMASYNC_POSTWRITE); 3799 if (len) 3800 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3801 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3802 3803 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3804 } 3805 3806 /* Abort a device control request. */ 3807 Static void 3808 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3809 { 3810 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3811 3812 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3813 ehci_abort_xfer(xfer, USBD_CANCELLED); 3814 } 3815 3816 /* Close a device control pipe. */ 3817 Static void 3818 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3819 { 3820 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3821 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3822 3823 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3824 3825 KASSERT(mutex_owned(&sc->sc_lock)); 3826 3827 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3828 3829 ehci_close_pipe(pipe, sc->sc_async_head); 3830 } 3831 3832 /* 3833 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3834 * qTD status, or miss signalling occasionally under heavy load. If the host 3835 * machine is too fast, we we can miss transaction completion - when we scan 3836 * the active list the transaction still seems to be active. This generally 3837 * exhibits itself as a umass stall that never recovers. 3838 * 3839 * We work around this behaviour by setting up this callback after any softintr 3840 * that completes with transactions still pending, giving us another chance to 3841 * check for completion after the writeback has taken place. 3842 */ 3843 Static void 3844 ehci_intrlist_timeout(void *arg) 3845 { 3846 ehci_softc_t *sc = arg; 3847 3848 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3849 3850 usb_schedsoftintr(&sc->sc_bus); 3851 } 3852 3853 /************************/ 3854 3855 Static int 3856 ehci_device_bulk_init(struct usbd_xfer *xfer) 3857 { 3858 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3859 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3860 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3861 int endpt = ed->bEndpointAddress; 3862 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3863 int len = xfer->ux_bufsize; 3864 int err = 0; 3865 3866 exfer->ex_type = EX_BULK; 3867 exfer->ex_nsqtd = 0; 3868 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3869 &exfer->ex_sqtdstart); 3870 3871 return err; 3872 } 3873 3874 Static void 3875 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3876 { 3877 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3878 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3879 3880 KASSERT(ex->ex_type == EX_BULK); 3881 3882 ehci_free_sqtds(sc, ex); 3883 if (ex->ex_nsqtd) 3884 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3885 } 3886 3887 Static usbd_status 3888 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3889 { 3890 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3891 usbd_status err; 3892 3893 /* Insert last in queue. */ 3894 mutex_enter(&sc->sc_lock); 3895 err = usb_insert_transfer(xfer); 3896 mutex_exit(&sc->sc_lock); 3897 if (err) 3898 return err; 3899 3900 /* Pipe isn't running, start first */ 3901 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3902 } 3903 3904 Static usbd_status 3905 ehci_device_bulk_start(struct usbd_xfer *xfer) 3906 { 3907 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3908 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3909 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3910 ehci_soft_qh_t *sqh; 3911 ehci_soft_qtd_t *end; 3912 int len, isread, endpt; 3913 const bool polling = sc->sc_bus.ub_usepolling; 3914 3915 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3916 3917 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3918 xfer->ux_flags, 0); 3919 3920 if (sc->sc_dying) 3921 return USBD_IOERROR; 3922 3923 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3924 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3925 3926 len = xfer->ux_length; 3927 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3928 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3929 sqh = epipe->sqh; 3930 3931 KASSERT(exfer->ex_isdone); 3932 #ifdef DIAGNOSTIC 3933 exfer->ex_isdone = false; 3934 #endif 3935 3936 /* Take lock here to protect nexttoggle */ 3937 if (!polling) 3938 mutex_enter(&sc->sc_lock); 3939 3940 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3941 3942 exfer->ex_sqtdend = end; 3943 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3944 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3945 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3946 3947 #ifdef EHCI_DEBUG 3948 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3949 ehci_dump_sqh(sqh); 3950 ehci_dump_sqtds(exfer->ex_sqtdstart); 3951 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3952 #endif 3953 3954 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3955 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3956 3957 /* also does usb_syncmem(sqh) */ 3958 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3959 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3960 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3961 ehci_timeout, xfer); 3962 } 3963 ehci_add_intr_list(sc, exfer); 3964 xfer->ux_status = USBD_IN_PROGRESS; 3965 if (!polling) 3966 mutex_exit(&sc->sc_lock); 3967 3968 #if 0 3969 #ifdef EHCI_DEBUG 3970 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3971 // delay(10000); 3972 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3973 ehci_dump_regs(sc); 3974 #if 0 3975 printf("async_head:\n"); 3976 ehci_dump_sqh(sc->sc_async_head); 3977 #endif 3978 DPRINTF("sqh:", 0, 0, 0, 0); 3979 ehci_dump_sqh(sqh); 3980 ehci_dump_sqtds(exfer->ex_sqtdstart); 3981 #endif 3982 #endif 3983 3984 return USBD_IN_PROGRESS; 3985 } 3986 3987 Static void 3988 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3989 { 3990 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3991 3992 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3993 ehci_abort_xfer(xfer, USBD_CANCELLED); 3994 } 3995 3996 /* 3997 * Close a device bulk pipe. 3998 */ 3999 Static void 4000 ehci_device_bulk_close(struct usbd_pipe *pipe) 4001 { 4002 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4003 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4004 4005 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4006 4007 KASSERT(mutex_owned(&sc->sc_lock)); 4008 4009 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4010 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4011 ehci_close_pipe(pipe, sc->sc_async_head); 4012 } 4013 4014 Static void 4015 ehci_device_bulk_done(struct usbd_xfer *xfer) 4016 { 4017 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4018 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4019 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4020 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4021 4022 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4023 4024 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4025 4026 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4027 4028 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4029 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4030 4031 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4032 } 4033 4034 /************************/ 4035 4036 Static usbd_status 4037 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4038 { 4039 struct ehci_soft_islot *isp; 4040 int islot, lev; 4041 4042 /* Find a poll rate that is large enough. */ 4043 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4044 if (EHCI_ILEV_IVAL(lev) <= ival) 4045 break; 4046 4047 /* Pick an interrupt slot at the right level. */ 4048 /* XXX could do better than picking at random */ 4049 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4050 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4051 4052 sqh->islot = islot; 4053 isp = &sc->sc_islots[islot]; 4054 mutex_enter(&sc->sc_lock); 4055 ehci_add_qh(sc, sqh, isp->sqh); 4056 mutex_exit(&sc->sc_lock); 4057 4058 return USBD_NORMAL_COMPLETION; 4059 } 4060 4061 4062 Static int 4063 ehci_device_intr_init(struct usbd_xfer *xfer) 4064 { 4065 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4066 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4067 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4068 int endpt = ed->bEndpointAddress; 4069 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4070 int len = xfer->ux_bufsize; 4071 int err; 4072 4073 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4074 4075 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4076 xfer->ux_flags, 0); 4077 4078 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4079 KASSERT(len != 0); 4080 4081 exfer->ex_type = EX_INTR; 4082 exfer->ex_nsqtd = 0; 4083 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4084 &exfer->ex_sqtdstart); 4085 4086 return err; 4087 } 4088 4089 Static void 4090 ehci_device_intr_fini(struct usbd_xfer *xfer) 4091 { 4092 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4093 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4094 4095 KASSERT(ex->ex_type == EX_INTR); 4096 4097 ehci_free_sqtds(sc, ex); 4098 if (ex->ex_nsqtd) 4099 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4100 } 4101 4102 Static usbd_status 4103 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4104 { 4105 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4106 usbd_status err; 4107 4108 /* Insert last in queue. */ 4109 mutex_enter(&sc->sc_lock); 4110 err = usb_insert_transfer(xfer); 4111 mutex_exit(&sc->sc_lock); 4112 if (err) 4113 return err; 4114 4115 /* 4116 * Pipe isn't running (otherwise err would be USBD_INPROG), 4117 * so start it first. 4118 */ 4119 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4120 } 4121 4122 Static usbd_status 4123 ehci_device_intr_start(struct usbd_xfer *xfer) 4124 { 4125 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4126 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4127 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4128 ehci_soft_qtd_t *end; 4129 ehci_soft_qh_t *sqh; 4130 int len, isread, endpt; 4131 const bool polling = sc->sc_bus.ub_usepolling; 4132 4133 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4134 4135 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4136 xfer->ux_flags, 0); 4137 4138 if (sc->sc_dying) 4139 return USBD_IOERROR; 4140 4141 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4142 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4143 4144 len = xfer->ux_length; 4145 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4146 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4147 sqh = epipe->sqh; 4148 4149 KASSERT(exfer->ex_isdone); 4150 #ifdef DIAGNOSTIC 4151 exfer->ex_isdone = false; 4152 #endif 4153 4154 /* Take lock to protect nexttoggle */ 4155 if (!polling) 4156 mutex_enter(&sc->sc_lock); 4157 4158 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4159 4160 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4161 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4163 exfer->ex_sqtdend = end; 4164 4165 #ifdef EHCI_DEBUG 4166 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4167 ehci_dump_sqh(sqh); 4168 ehci_dump_sqtds(exfer->ex_sqtdstart); 4169 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4170 #endif 4171 4172 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4173 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4174 4175 /* also does usb_syncmem(sqh) */ 4176 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4177 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4178 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4179 ehci_timeout, xfer); 4180 } 4181 ehci_add_intr_list(sc, exfer); 4182 xfer->ux_status = USBD_IN_PROGRESS; 4183 if (!polling) 4184 mutex_exit(&sc->sc_lock); 4185 4186 #if 0 4187 #ifdef EHCI_DEBUG 4188 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4189 // delay(10000); 4190 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4191 ehci_dump_regs(sc); 4192 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4193 ehci_dump_sqh(sqh); 4194 ehci_dump_sqtds(exfer->ex_sqtdstart); 4195 #endif 4196 #endif 4197 4198 return USBD_IN_PROGRESS; 4199 } 4200 4201 Static void 4202 ehci_device_intr_abort(struct usbd_xfer *xfer) 4203 { 4204 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4205 4206 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4207 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4208 4209 /* 4210 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4211 * async doorbell. That's dependent on the async list, wheras 4212 * intr xfers are periodic, should not use this? 4213 */ 4214 ehci_abort_xfer(xfer, USBD_CANCELLED); 4215 } 4216 4217 Static void 4218 ehci_device_intr_close(struct usbd_pipe *pipe) 4219 { 4220 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4221 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4222 struct ehci_soft_islot *isp; 4223 4224 KASSERT(mutex_owned(&sc->sc_lock)); 4225 4226 isp = &sc->sc_islots[epipe->sqh->islot]; 4227 ehci_close_pipe(pipe, isp->sqh); 4228 } 4229 4230 Static void 4231 ehci_device_intr_done(struct usbd_xfer *xfer) 4232 { 4233 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4234 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4235 int isread, endpt; 4236 4237 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4238 4239 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4240 4241 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4242 4243 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4244 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4245 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4246 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4247 } 4248 4249 /************************/ 4250 Static int 4251 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4252 { 4253 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4254 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4255 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4256 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4257 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4258 int i, k, frames; 4259 u_int huba, dir; 4260 int err; 4261 4262 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4263 4264 start = NULL; 4265 sitd = NULL; 4266 4267 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4268 xfer->ux_flags, 0); 4269 4270 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4271 KASSERT(xfer->ux_nframes != 0); 4272 KASSERT(exfer->ex_isdone); 4273 4274 exfer->ex_type = EX_FS_ISOC; 4275 /* 4276 * Step 1: Allocate and initialize sitds. 4277 */ 4278 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4279 if (i > 16 || i == 0) { 4280 /* Spec page 271 says intervals > 16 are invalid */ 4281 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4282 4283 return EINVAL; 4284 } 4285 4286 frames = xfer->ux_nframes; 4287 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4288 sitd = ehci_alloc_sitd(sc); 4289 if (sitd == NULL) { 4290 err = ENOMEM; 4291 goto fail; 4292 } 4293 4294 if (prev) 4295 prev->xfer_next = sitd; 4296 else 4297 start = sitd; 4298 4299 huba = dev->ud_myhsport->up_parent->ud_addr; 4300 4301 #if 0 4302 if (sc->sc_flags & EHCIF_FREESCALE) { 4303 // Set hub address to 0 if embedded TT is used. 4304 if (huba == sc->sc_addr) 4305 huba = 0; 4306 } 4307 #endif 4308 4309 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4310 dir = UE_GET_DIR(k) ? 1 : 0; 4311 sitd->sitd.sitd_endp = 4312 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4313 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4314 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4315 EHCI_SITD_SET_HUBA(huba) | 4316 EHCI_SITD_SET_DIR(dir)); 4317 4318 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4319 } /* End of frame */ 4320 4321 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4322 4323 stop = sitd; 4324 stop->xfer_next = NULL; 4325 exfer->ex_sitdstart = start; 4326 exfer->ex_sitdend = stop; 4327 4328 return 0; 4329 4330 fail: 4331 mutex_enter(&sc->sc_lock); 4332 ehci_soft_sitd_t *next; 4333 for (sitd = start; sitd; sitd = next) { 4334 next = sitd->xfer_next; 4335 ehci_free_sitd_locked(sc, sitd); 4336 } 4337 mutex_exit(&sc->sc_lock); 4338 4339 return err; 4340 } 4341 4342 Static void 4343 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4344 { 4345 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4346 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4347 4348 KASSERT(ex->ex_type == EX_FS_ISOC); 4349 4350 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4351 } 4352 4353 Static usbd_status 4354 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4355 { 4356 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4357 usbd_status __diagused err; 4358 4359 mutex_enter(&sc->sc_lock); 4360 err = usb_insert_transfer(xfer); 4361 mutex_exit(&sc->sc_lock); 4362 4363 KASSERT(err == USBD_NORMAL_COMPLETION); 4364 4365 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4366 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4367 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4368 ehci_soft_sitd_t *sitd; 4369 usb_dma_t *dma_buf; 4370 int i, j, k, frames; 4371 int offs, total_length; 4372 int frindex; 4373 u_int dir; 4374 4375 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4376 4377 sitd = NULL; 4378 total_length = 0; 4379 4380 4381 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4382 xfer->ux_flags, 0); 4383 4384 if (sc->sc_dying) 4385 return USBD_IOERROR; 4386 4387 /* 4388 * To avoid complication, don't allow a request right now that'll span 4389 * the entire frame table. To within 4 frames, to allow some leeway 4390 * on either side of where the hc currently is. 4391 */ 4392 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4393 xfer->ux_nframes >= sc->sc_flsize - 4) { 4394 printf("ehci: isoc descriptor requested that spans the entire" 4395 "frametable, too many frames\n"); 4396 return USBD_INVAL; 4397 } 4398 4399 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4400 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4401 KASSERT(exfer->ex_isdone); 4402 #ifdef DIAGNOSTIC 4403 exfer->ex_isdone = false; 4404 #endif 4405 4406 /* 4407 * Step 1: Initialize sitds. 4408 */ 4409 4410 frames = xfer->ux_nframes; 4411 dma_buf = &xfer->ux_dmabuf; 4412 offs = 0; 4413 4414 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4415 i++, sitd = sitd->xfer_next) { 4416 KASSERT(sitd != NULL); 4417 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4418 4419 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4420 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4421 4422 /* Set page0 index and offset - TP and T-offset are set below */ 4423 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4424 4425 total_length += xfer->ux_frlengths[i]; 4426 offs += xfer->ux_frlengths[i]; 4427 4428 sitd->sitd.sitd_buffer[1] = 4429 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4430 4431 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4432 4433 #if 0 4434 if (sc->sc_flags & EHCIF_FREESCALE) { 4435 // Set hub address to 0 if embedded TT is used. 4436 if (huba == sc->sc_addr) 4437 huba = 0; 4438 } 4439 #endif 4440 4441 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4442 dir = UE_GET_DIR(k) ? 1 : 0; 4443 KASSERT(sitd->sitd.sitd_endp == htole32( 4444 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4445 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4446 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4447 EHCI_SITD_SET_HUBA(huba) | 4448 EHCI_SITD_SET_DIR(dir))); 4449 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4450 4451 uint8_t sa = 0; 4452 uint8_t sb = 0; 4453 u_int temp, tlen; 4454 4455 if (dir == 0) { /* OUT */ 4456 temp = 0; 4457 tlen = xfer->ux_frlengths[i]; 4458 if (tlen <= 188) { 4459 temp |= 1; /* T-count = 1, TP = ALL */ 4460 tlen = 1; 4461 } else { 4462 tlen += 187; 4463 tlen /= 188; 4464 temp |= tlen; /* T-count = [1..6] */ 4465 temp |= 8; /* TP = Begin */ 4466 } 4467 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4468 4469 tlen += sa; 4470 4471 if (tlen >= 8) { 4472 sb = 0; 4473 } else { 4474 sb = (1 << tlen); 4475 } 4476 4477 sa = (1 << sa); 4478 sa = (sb - sa) & 0x3F; 4479 sb = 0; 4480 } else { 4481 sb = (-(4 << sa)) & 0xFE; 4482 sa = (1 << sa) & 0x3F; 4483 sa = 0x01; 4484 sb = 0xfc; 4485 } 4486 4487 sitd->sitd.sitd_sched = htole32( 4488 EHCI_SITD_SET_SMASK(sa) | 4489 EHCI_SITD_SET_CMASK(sb) 4490 ); 4491 4492 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4493 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4494 } /* End of frame */ 4495 4496 sitd = exfer->ex_sitdend; 4497 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4498 4499 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4500 sizeof(sitd->sitd.sitd_trans), 4501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4502 4503 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4505 4506 /* 4507 * Part 2: Transfer descriptors have now been set up, now they must 4508 * be scheduled into the periodic frame list. Erk. Not wanting to 4509 * complicate matters, transfer is denied if the transfer spans 4510 * more than the period frame list. 4511 */ 4512 4513 mutex_enter(&sc->sc_lock); 4514 4515 /* Start inserting frames */ 4516 if (epipe->isoc.cur_xfers > 0) { 4517 frindex = epipe->isoc.next_frame; 4518 } else { 4519 frindex = EOREAD4(sc, EHCI_FRINDEX); 4520 frindex = frindex >> 3; /* Erase microframe index */ 4521 frindex += 2; 4522 } 4523 4524 if (frindex >= sc->sc_flsize) 4525 frindex &= (sc->sc_flsize - 1); 4526 4527 /* Whats the frame interval? */ 4528 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4529 4530 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4531 j++, sitd = sitd->xfer_next) { 4532 KASSERT(sitd); 4533 4534 usb_syncmem(&sc->sc_fldma, 4535 sizeof(ehci_link_t) * frindex, 4536 sizeof(ehci_link_t), 4537 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4538 4539 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4540 if (sitd->sitd.sitd_next == 0) 4541 /* 4542 * FIXME: frindex table gets initialized to NULL 4543 * or EHCI_NULL? 4544 */ 4545 sitd->sitd.sitd_next = EHCI_NULL; 4546 4547 usb_syncmem(&sitd->dma, 4548 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4549 sizeof(ehci_sitd_t), 4550 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4551 4552 sc->sc_flist[frindex] = 4553 htole32(EHCI_LINK_SITD | sitd->physaddr); 4554 4555 usb_syncmem(&sc->sc_fldma, 4556 sizeof(ehci_link_t) * frindex, 4557 sizeof(ehci_link_t), 4558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4559 4560 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4561 sc->sc_softsitds[frindex] = sitd; 4562 if (sitd->frame_list.next != NULL) 4563 sitd->frame_list.next->frame_list.prev = sitd; 4564 sitd->slot = frindex; 4565 sitd->frame_list.prev = NULL; 4566 4567 frindex += i; 4568 if (frindex >= sc->sc_flsize) 4569 frindex -= sc->sc_flsize; 4570 } 4571 4572 epipe->isoc.cur_xfers++; 4573 epipe->isoc.next_frame = frindex; 4574 4575 ehci_add_intr_list(sc, exfer); 4576 xfer->ux_status = USBD_IN_PROGRESS; 4577 mutex_exit(&sc->sc_lock); 4578 4579 return USBD_IN_PROGRESS; 4580 } 4581 4582 Static void 4583 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4584 { 4585 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4586 4587 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4588 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4589 } 4590 4591 Static void 4592 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4593 { 4594 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4595 4596 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4597 } 4598 4599 Static void 4600 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4601 { 4602 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4603 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4604 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4605 4606 KASSERT(mutex_owned(&sc->sc_lock)); 4607 4608 epipe->isoc.cur_xfers--; 4609 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4610 4611 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4612 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4613 } 4614 4615 4616 /************************/ 4617 4618 4619 Static int 4620 ehci_device_isoc_init(struct usbd_xfer *xfer) 4621 { 4622 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4623 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4624 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4625 ehci_soft_itd_t *itd, *prev, *start, *stop; 4626 int i, j, k; 4627 int frames, ufrperframe; 4628 int err; 4629 4630 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4631 4632 start = NULL; 4633 prev = NULL; 4634 itd = NULL; 4635 4636 KASSERT(xfer->ux_nframes != 0); 4637 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4638 KASSERT(exfer->ex_isdone); 4639 4640 exfer->ex_type = EX_ISOC; 4641 4642 /* 4643 * Step 1: Allocate and initialize itds, how many do we need? 4644 * One per transfer if interval >= 8 microframes, less if we use 4645 * multiple microframes per frame. 4646 */ 4647 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4648 if (i > 16 || i == 0) { 4649 /* Spec page 271 says intervals > 16 are invalid */ 4650 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4651 return USBD_INVAL; 4652 } 4653 4654 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4655 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4656 4657 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4658 itd = ehci_alloc_itd(sc); 4659 if (itd == NULL) { 4660 err = ENOMEM; 4661 goto fail; 4662 } 4663 4664 if (prev != NULL) { 4665 /* Maybe not as it's updated by the scheduling? */ 4666 prev->itd.itd_next = 4667 htole32(itd->physaddr | EHCI_LINK_ITD); 4668 4669 prev->xfer_next = itd; 4670 } else { 4671 start = itd; 4672 } 4673 4674 /* 4675 * Other special values 4676 */ 4677 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4678 itd->itd.itd_bufr[0] = htole32( 4679 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4680 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4681 4682 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4683 ? 1 : 0; 4684 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4685 itd->itd.itd_bufr[1] |= htole32( 4686 EHCI_ITD_SET_DIR(k) | 4687 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4688 4689 /* FIXME: handle invalid trans - should be done in openpipe */ 4690 itd->itd.itd_bufr[2] |= 4691 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4692 } /* End of frame */ 4693 4694 stop = itd; 4695 stop->xfer_next = NULL; 4696 4697 exfer->ex_itdstart = start; 4698 exfer->ex_itdend = stop; 4699 4700 return 0; 4701 fail: 4702 mutex_enter(&sc->sc_lock); 4703 ehci_soft_itd_t *next; 4704 for (itd = start; itd; itd = next) { 4705 next = itd->xfer_next; 4706 ehci_free_itd_locked(sc, itd); 4707 } 4708 mutex_exit(&sc->sc_lock); 4709 4710 return err; 4711 4712 } 4713 4714 Static void 4715 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4716 { 4717 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4718 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4719 4720 KASSERT(ex->ex_type == EX_ISOC); 4721 4722 ehci_free_itd_chain(sc, ex->ex_itdstart); 4723 } 4724 4725 Static usbd_status 4726 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4727 { 4728 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4729 usbd_status __diagused err; 4730 4731 mutex_enter(&sc->sc_lock); 4732 err = usb_insert_transfer(xfer); 4733 mutex_exit(&sc->sc_lock); 4734 4735 KASSERT(err == USBD_NORMAL_COMPLETION); 4736 4737 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4738 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4739 ehci_soft_itd_t *itd, *prev; 4740 usb_dma_t *dma_buf; 4741 int i, j; 4742 int frames, uframes, ufrperframe; 4743 int trans_count, offs, total_length; 4744 int frindex; 4745 4746 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4747 4748 prev = NULL; 4749 itd = NULL; 4750 trans_count = 0; 4751 total_length = 0; 4752 4753 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4754 4755 if (sc->sc_dying) 4756 return USBD_IOERROR; 4757 4758 /* 4759 * To avoid complication, don't allow a request right now that'll span 4760 * the entire frame table. To within 4 frames, to allow some leeway 4761 * on either side of where the hc currently is. 4762 */ 4763 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4764 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4765 DPRINTF( 4766 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4767 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4768 return USBD_INVAL; 4769 } 4770 4771 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4772 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4773 KASSERT(exfer->ex_isdone); 4774 #ifdef DIAGNOSTIC 4775 exfer->ex_isdone = false; 4776 #endif 4777 4778 /* 4779 * Step 1: Re-Initialize itds 4780 */ 4781 4782 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4783 if (i > 16 || i == 0) { 4784 /* Spec page 271 says intervals > 16 are invalid */ 4785 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4786 return USBD_INVAL; 4787 } 4788 4789 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4790 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4791 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4792 4793 if (frames == 0) { 4794 DPRINTF("frames == 0", 0, 0, 0, 0); 4795 return USBD_INVAL; 4796 } 4797 4798 dma_buf = &xfer->ux_dmabuf; 4799 offs = 0; 4800 4801 itd = exfer->ex_itdstart; 4802 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4803 int froffs = offs; 4804 4805 if (prev != NULL) { 4806 prev->itd.itd_next = 4807 htole32(itd->physaddr | EHCI_LINK_ITD); 4808 usb_syncmem(&prev->dma, 4809 prev->offs + offsetof(ehci_itd_t, itd_next), 4810 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4811 prev->xfer_next = itd; 4812 } 4813 4814 /* 4815 * Step 1.5, initialize uframes 4816 */ 4817 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4818 /* Calculate which page in the list this starts in */ 4819 int addr = DMAADDR(dma_buf, froffs); 4820 addr = EHCI_PAGE_OFFSET(addr); 4821 addr += (offs - froffs); 4822 addr = EHCI_PAGE(addr); 4823 addr /= EHCI_PAGE_SIZE; 4824 4825 /* 4826 * This gets the initial offset into the first page, 4827 * looks how far further along the current uframe 4828 * offset is. Works out how many pages that is. 4829 */ 4830 4831 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4832 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4833 EHCI_ITD_SET_PG(addr) | 4834 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4835 4836 total_length += xfer->ux_frlengths[trans_count]; 4837 offs += xfer->ux_frlengths[trans_count]; 4838 trans_count++; 4839 4840 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4841 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4842 break; 4843 } 4844 } 4845 4846 /* 4847 * Step 1.75, set buffer pointers. To simplify matters, all 4848 * pointers are filled out for the next 7 hardware pages in 4849 * the dma block, so no need to worry what pages to cover 4850 * and what to not. 4851 */ 4852 4853 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4854 /* 4855 * Don't try to lookup a page that's past the end 4856 * of buffer 4857 */ 4858 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4859 if (page_offs >= dma_buf->udma_block->size) 4860 break; 4861 4862 uint64_t page = DMAADDR(dma_buf, page_offs); 4863 page = EHCI_PAGE(page); 4864 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4865 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4866 } 4867 /* 4868 * Other special values 4869 */ 4870 4871 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4872 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4873 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4874 4875 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4876 ? 1 : 0; 4877 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4878 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4879 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4880 4881 /* FIXME: handle invalid trans */ 4882 itd->itd.itd_bufr[2] |= 4883 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4884 4885 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4886 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4887 4888 prev = itd; 4889 } /* End of frame */ 4890 4891 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4892 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4893 4894 /* 4895 * Part 2: Transfer descriptors have now been set up, now they must 4896 * be scheduled into the period frame list. Erk. Not wanting to 4897 * complicate matters, transfer is denied if the transfer spans 4898 * more than the period frame list. 4899 */ 4900 4901 mutex_enter(&sc->sc_lock); 4902 4903 /* Start inserting frames */ 4904 if (epipe->isoc.cur_xfers > 0) { 4905 frindex = epipe->isoc.next_frame; 4906 } else { 4907 frindex = EOREAD4(sc, EHCI_FRINDEX); 4908 frindex = frindex >> 3; /* Erase microframe index */ 4909 frindex += 2; 4910 } 4911 4912 if (frindex >= sc->sc_flsize) 4913 frindex &= (sc->sc_flsize - 1); 4914 4915 /* What's the frame interval? */ 4916 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4917 if (i / USB_UFRAMES_PER_FRAME == 0) 4918 i = 1; 4919 else 4920 i /= USB_UFRAMES_PER_FRAME; 4921 4922 itd = exfer->ex_itdstart; 4923 for (j = 0; j < frames; j++) { 4924 KASSERTMSG(itd != NULL, "frame %d\n", j); 4925 4926 usb_syncmem(&sc->sc_fldma, 4927 sizeof(ehci_link_t) * frindex, 4928 sizeof(ehci_link_t), 4929 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4930 4931 itd->itd.itd_next = sc->sc_flist[frindex]; 4932 if (itd->itd.itd_next == 0) 4933 /* 4934 * FIXME: frindex table gets initialized to NULL 4935 * or EHCI_NULL? 4936 */ 4937 itd->itd.itd_next = EHCI_NULL; 4938 4939 usb_syncmem(&itd->dma, 4940 itd->offs + offsetof(ehci_itd_t, itd_next), 4941 sizeof(itd->itd.itd_next), 4942 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4943 4944 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4945 4946 usb_syncmem(&sc->sc_fldma, 4947 sizeof(ehci_link_t) * frindex, 4948 sizeof(ehci_link_t), 4949 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4950 4951 itd->frame_list.next = sc->sc_softitds[frindex]; 4952 sc->sc_softitds[frindex] = itd; 4953 if (itd->frame_list.next != NULL) 4954 itd->frame_list.next->frame_list.prev = itd; 4955 itd->slot = frindex; 4956 itd->frame_list.prev = NULL; 4957 4958 frindex += i; 4959 if (frindex >= sc->sc_flsize) 4960 frindex -= sc->sc_flsize; 4961 4962 itd = itd->xfer_next; 4963 } 4964 4965 epipe->isoc.cur_xfers++; 4966 epipe->isoc.next_frame = frindex; 4967 4968 ehci_add_intr_list(sc, exfer); 4969 xfer->ux_status = USBD_IN_PROGRESS; 4970 mutex_exit(&sc->sc_lock); 4971 4972 return USBD_IN_PROGRESS; 4973 } 4974 4975 Static void 4976 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4977 { 4978 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4979 4980 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4981 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4982 } 4983 4984 Static void 4985 ehci_device_isoc_close(struct usbd_pipe *pipe) 4986 { 4987 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4988 4989 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4990 } 4991 4992 Static void 4993 ehci_device_isoc_done(struct usbd_xfer *xfer) 4994 { 4995 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4996 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4997 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4998 4999 KASSERT(mutex_owned(&sc->sc_lock)); 5000 5001 epipe->isoc.cur_xfers--; 5002 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5003 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5004 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5005 } 5006
Indexes created Wed Oct 01 19:09:53 GMT 2025