ehci.c revision 1.259.2.1
1 /* $NetBSD: ehci.c,v 1.259.2.1 2019/06/10 22:07:33 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.259.2.1 2019/06/10 22:07:33 christos Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 #include <sys/reboot.h> 79 80 #include <machine/endian.h> 81 82 #include <dev/usb/usb.h> 83 #include <dev/usb/usbdi.h> 84 #include <dev/usb/usbdivar.h> 85 #include <dev/usb/usbhist.h> 86 #include <dev/usb/usb_mem.h> 87 #include <dev/usb/usb_quirks.h> 88 89 #include <dev/usb/ehcireg.h> 90 #include <dev/usb/ehcivar.h> 91 #include <dev/usb/usbroothub.h> 92 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 static int ehcidebug = 0; 99 100 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 101 { 102 int err; 103 const struct sysctlnode *rnode; 104 const struct sysctlnode *cnode; 105 106 err = sysctl_createv(clog, 0, NULL, &rnode, 107 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 108 SYSCTL_DESCR("ehci global controls"), 109 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 110 111 if (err) 112 goto fail; 113 114 /* control debugging printfs */ 115 err = sysctl_createv(clog, 0, &rnode, &cnode, 116 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 117 "debug", SYSCTL_DESCR("Enable debugging output"), 118 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 119 if (err) 120 goto fail; 121 122 return; 123 fail: 124 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 125 } 126 127 #endif /* EHCI_DEBUG */ 128 #endif /* USB_DEBUG */ 129 130 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 131 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 132 #define EHCIHIST_FUNC() USBHIST_FUNC() 133 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 134 135 struct ehci_pipe { 136 struct usbd_pipe pipe; 137 int nexttoggle; 138 139 ehci_soft_qh_t *sqh; 140 union { 141 /* Control pipe */ 142 struct { 143 usb_dma_t reqdma; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 u_int length; 148 } intr; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 }; 155 }; 156 157 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 158 159 Static usbd_status ehci_open(struct usbd_pipe *); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_timeout(void *); 171 Static void ehci_timeout_task(void *); 172 Static void ehci_intrlist_timeout(void *); 173 Static void ehci_doorbell(void *); 174 Static void ehci_pcd(void *); 175 176 Static struct usbd_xfer * 177 ehci_allocx(struct usbd_bus *, unsigned int); 178 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 179 180 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 181 Static int ehci_roothub_ctrl(struct usbd_bus *, 182 usb_device_request_t *, void *, int); 183 184 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 185 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 186 Static void ehci_root_intr_abort(struct usbd_xfer *); 187 Static void ehci_root_intr_close(struct usbd_pipe *); 188 Static void ehci_root_intr_done(struct usbd_xfer *); 189 190 Static int ehci_device_ctrl_init(struct usbd_xfer *); 191 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 193 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 194 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 195 Static void ehci_device_ctrl_close(struct usbd_pipe *); 196 Static void ehci_device_ctrl_done(struct usbd_xfer *); 197 198 Static int ehci_device_bulk_init(struct usbd_xfer *); 199 Static void ehci_device_bulk_fini(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 201 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 202 Static void ehci_device_bulk_abort(struct usbd_xfer *); 203 Static void ehci_device_bulk_close(struct usbd_pipe *); 204 Static void ehci_device_bulk_done(struct usbd_xfer *); 205 206 Static int ehci_device_intr_init(struct usbd_xfer *); 207 Static void ehci_device_intr_fini(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 209 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 210 Static void ehci_device_intr_abort(struct usbd_xfer *); 211 Static void ehci_device_intr_close(struct usbd_pipe *); 212 Static void ehci_device_intr_done(struct usbd_xfer *); 213 214 Static int ehci_device_isoc_init(struct usbd_xfer *); 215 Static void ehci_device_isoc_fini(struct usbd_xfer *); 216 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 217 Static void ehci_device_isoc_abort(struct usbd_xfer *); 218 Static void ehci_device_isoc_close(struct usbd_pipe *); 219 Static void ehci_device_isoc_done(struct usbd_xfer *); 220 221 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 223 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 225 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 226 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 227 228 Static void ehci_device_clear_toggle(struct usbd_pipe *); 229 Static void ehci_noop(struct usbd_pipe *); 230 231 Static void ehci_disown(ehci_softc_t *, int, int); 232 233 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 234 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 235 236 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 237 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 238 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 239 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 240 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 241 242 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 243 int, int, int *, ehci_soft_qtd_t **); 244 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 245 246 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 247 Static ehci_soft_sitd_t * 248 ehci_alloc_sitd(ehci_softc_t *); 249 250 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 251 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 252 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 253 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 254 255 static inline void 256 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 257 { 258 259 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 260 } 261 262 static inline void 263 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 264 { 265 266 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 267 } 268 269 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 270 271 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 272 int); 273 274 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 275 ehci_soft_qh_t *); 276 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 277 ehci_soft_qh_t *); 278 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 279 Static void ehci_sync_hc(ehci_softc_t *); 280 281 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 282 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 283 284 #ifdef EHCI_DEBUG 285 Static ehci_softc_t *theehci; 286 void ehci_dump(void); 287 #endif 288 289 #ifdef EHCI_DEBUG 290 Static void ehci_dump_regs(ehci_softc_t *); 291 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 292 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 293 Static void ehci_dump_qtd(ehci_qtd_t *); 294 Static void ehci_dump_sqh(ehci_soft_qh_t *); 295 Static void ehci_dump_sitd(struct ehci_soft_itd *); 296 Static void ehci_dump_itds(ehci_soft_itd_t *); 297 Static void ehci_dump_itd(struct ehci_soft_itd *); 298 Static void ehci_dump_exfer(struct ehci_xfer *); 299 #endif 300 301 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 302 303 static inline void 304 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 305 { 306 307 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 308 } 309 310 static inline void 311 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 312 { 313 314 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 315 } 316 317 Static const struct usbd_bus_methods ehci_bus_methods = { 318 .ubm_open = ehci_open, 319 .ubm_softint = ehci_softintr, 320 .ubm_dopoll = ehci_poll, 321 .ubm_allocx = ehci_allocx, 322 .ubm_freex = ehci_freex, 323 .ubm_getlock = ehci_get_lock, 324 .ubm_rhctrl = ehci_roothub_ctrl, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 328 .upm_transfer = ehci_root_intr_transfer, 329 .upm_start = ehci_root_intr_start, 330 .upm_abort = ehci_root_intr_abort, 331 .upm_close = ehci_root_intr_close, 332 .upm_cleartoggle = ehci_noop, 333 .upm_done = ehci_root_intr_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 337 .upm_init = ehci_device_ctrl_init, 338 .upm_fini = ehci_device_ctrl_fini, 339 .upm_transfer = ehci_device_ctrl_transfer, 340 .upm_start = ehci_device_ctrl_start, 341 .upm_abort = ehci_device_ctrl_abort, 342 .upm_close = ehci_device_ctrl_close, 343 .upm_cleartoggle = ehci_noop, 344 .upm_done = ehci_device_ctrl_done, 345 }; 346 347 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 348 .upm_init = ehci_device_intr_init, 349 .upm_fini = ehci_device_intr_fini, 350 .upm_transfer = ehci_device_intr_transfer, 351 .upm_start = ehci_device_intr_start, 352 .upm_abort = ehci_device_intr_abort, 353 .upm_close = ehci_device_intr_close, 354 .upm_cleartoggle = ehci_device_clear_toggle, 355 .upm_done = ehci_device_intr_done, 356 }; 357 358 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 359 .upm_init = ehci_device_bulk_init, 360 .upm_fini = ehci_device_bulk_fini, 361 .upm_transfer = ehci_device_bulk_transfer, 362 .upm_start = ehci_device_bulk_start, 363 .upm_abort = ehci_device_bulk_abort, 364 .upm_close = ehci_device_bulk_close, 365 .upm_cleartoggle = ehci_device_clear_toggle, 366 .upm_done = ehci_device_bulk_done, 367 }; 368 369 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 370 .upm_init = ehci_device_isoc_init, 371 .upm_fini = ehci_device_isoc_fini, 372 .upm_transfer = ehci_device_isoc_transfer, 373 .upm_abort = ehci_device_isoc_abort, 374 .upm_close = ehci_device_isoc_close, 375 .upm_cleartoggle = ehci_noop, 376 .upm_done = ehci_device_isoc_done, 377 }; 378 379 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 380 .upm_init = ehci_device_fs_isoc_init, 381 .upm_fini = ehci_device_fs_isoc_fini, 382 .upm_transfer = ehci_device_fs_isoc_transfer, 383 .upm_abort = ehci_device_fs_isoc_abort, 384 .upm_close = ehci_device_fs_isoc_close, 385 .upm_cleartoggle = ehci_noop, 386 .upm_done = ehci_device_fs_isoc_done, 387 }; 388 389 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 390 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 391 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 392 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 393 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 394 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 395 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 396 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 397 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 398 }; 399 400 int 401 ehci_init(ehci_softc_t *sc) 402 { 403 uint32_t vers, sparams, cparams, hcr; 404 u_int i; 405 usbd_status err; 406 ehci_soft_qh_t *sqh; 407 u_int ncomp; 408 409 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 410 #ifdef EHCI_DEBUG 411 theehci = sc; 412 #endif 413 414 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 415 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 416 cv_init(&sc->sc_doorbell, "ehcidb"); 417 418 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 419 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 420 421 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 422 ehci_doorbell, sc); 423 KASSERT(sc->sc_doorbell_si != NULL); 424 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 425 ehci_pcd, sc); 426 KASSERT(sc->sc_pcd_si != NULL); 427 428 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 429 430 vers = EREAD2(sc, EHCI_HCIVERSION); 431 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 432 vers >> 8, vers & 0xff); 433 434 sparams = EREAD4(sc, EHCI_HCSPARAMS); 435 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 436 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 437 ncomp = EHCI_HCS_N_CC(sparams); 438 if (ncomp != sc->sc_ncomp) { 439 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 440 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 441 #if NOHCI == 0 || NUHCI == 0 442 aprint_error("%s: ohci or uhci probably not configured\n", 443 device_xname(sc->sc_dev)); 444 #endif 445 if (ncomp < sc->sc_ncomp) 446 sc->sc_ncomp = ncomp; 447 } 448 if (sc->sc_ncomp > 0) { 449 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 450 aprint_normal_dev(sc->sc_dev, 451 "%d companion controller%s, %d port%s%s", 452 sc->sc_ncomp, 453 sc->sc_ncomp!=1 ? "s" : "", 454 EHCI_HCS_N_PCC(sparams), 455 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 456 sc->sc_ncomp!=1 ? " each" : ""); 457 if (sc->sc_comps[0]) { 458 aprint_normal(":"); 459 for (i = 0; i < sc->sc_ncomp; i++) 460 aprint_normal(" %s", 461 device_xname(sc->sc_comps[i])); 462 } 463 aprint_normal("\n"); 464 465 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 466 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 467 cv_init(&sc->sc_compcv, "ehciccv"); 468 sc->sc_comp_state = CO_EARLY; 469 } 470 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 471 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 472 473 cparams = EREAD4(sc, EHCI_HCCPARAMS); 474 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 475 476 if (EHCI_HCC_64BIT(cparams)) { 477 /* MUST clear segment register if 64 bit capable. */ 478 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 479 } 480 481 if (cparams & EHCI_HCC_IST_FULLFRAME) { 482 sc->sc_istthreshold = 0; 483 } else { 484 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 485 } 486 487 sc->sc_bus.ub_revision = USBREV_2_0; 488 sc->sc_bus.ub_usedma = true; 489 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 490 491 /* Reset the controller */ 492 DPRINTF("resetting", 0, 0, 0, 0); 493 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 494 usb_delay_ms(&sc->sc_bus, 1); 495 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 496 for (i = 0; i < 100; i++) { 497 usb_delay_ms(&sc->sc_bus, 1); 498 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 499 if (!hcr) 500 break; 501 } 502 if (hcr) { 503 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 504 return EIO; 505 } 506 if (sc->sc_vendor_init) 507 sc->sc_vendor_init(sc); 508 509 /* XXX need proper intr scheduling */ 510 sc->sc_rand = 96; 511 512 /* frame list size at default, read back what we got and use that */ 513 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 514 case 0: sc->sc_flsize = 1024; break; 515 case 1: sc->sc_flsize = 512; break; 516 case 2: sc->sc_flsize = 256; break; 517 case 3: return EIO; 518 } 519 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 520 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 521 if (err) 522 return err; 523 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 524 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 525 526 for (i = 0; i < sc->sc_flsize; i++) { 527 sc->sc_flist[i] = EHCI_NULL; 528 } 529 530 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 531 532 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 533 KM_SLEEP); 534 if (sc->sc_softitds == NULL) 535 return ENOMEM; 536 LIST_INIT(&sc->sc_freeitds); 537 LIST_INIT(&sc->sc_freesitds); 538 TAILQ_INIT(&sc->sc_intrhead); 539 540 /* Set up the bus struct. */ 541 sc->sc_bus.ub_methods = &ehci_bus_methods; 542 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 543 544 sc->sc_eintrs = EHCI_NORMAL_INTRS; 545 546 /* 547 * Allocate the interrupt dummy QHs. These are arranged to give poll 548 * intervals that are powers of 2 times 1ms. 549 */ 550 for (i = 0; i < EHCI_INTRQHS; i++) { 551 sqh = ehci_alloc_sqh(sc); 552 if (sqh == NULL) { 553 err = ENOMEM; 554 goto bad1; 555 } 556 sc->sc_islots[i].sqh = sqh; 557 } 558 for (i = 0; i < EHCI_INTRQHS; i++) { 559 sqh = sc->sc_islots[i].sqh; 560 if (i == 0) { 561 /* The last (1ms) QH terminates. */ 562 sqh->qh.qh_link = EHCI_NULL; 563 sqh->next = NULL; 564 } else { 565 /* Otherwise the next QH has half the poll interval */ 566 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 567 sqh->qh.qh_link = htole32(sqh->next->physaddr | 568 EHCI_LINK_QH); 569 } 570 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 571 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 572 sqh->qh.qh_curqtd = EHCI_NULL; 573 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 574 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 575 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 576 sqh->sqtd = NULL; 577 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 578 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 579 } 580 /* Point the frame list at the last level (128ms). */ 581 for (i = 0; i < sc->sc_flsize; i++) { 582 int j; 583 584 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 585 revbits[i & (EHCI_MAX_POLLRATE-1)]; 586 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 587 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 588 i)].sqh->physaddr); 589 } 590 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 591 BUS_DMASYNC_PREWRITE); 592 593 /* Allocate dummy QH that starts the async list. */ 594 sqh = ehci_alloc_sqh(sc); 595 if (sqh == NULL) { 596 err = ENOMEM; 597 goto bad1; 598 } 599 /* Fill the QH */ 600 sqh->qh.qh_endp = 601 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 602 sqh->qh.qh_link = 603 htole32(sqh->physaddr | EHCI_LINK_QH); 604 sqh->qh.qh_curqtd = EHCI_NULL; 605 sqh->next = NULL; 606 /* Fill the overlay qTD */ 607 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 608 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 609 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 610 sqh->sqtd = NULL; 611 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 612 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 613 #ifdef EHCI_DEBUG 614 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 615 ehci_dump_sqh(sqh); 616 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 617 #endif 618 619 /* Point to async list */ 620 sc->sc_async_head = sqh; 621 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 622 623 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 624 625 /* Turn on controller */ 626 EOWRITE4(sc, EHCI_USBCMD, 627 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 628 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 629 EHCI_CMD_ASE | 630 EHCI_CMD_PSE | 631 EHCI_CMD_RS); 632 633 /* Take over port ownership */ 634 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 635 636 for (i = 0; i < 100; i++) { 637 usb_delay_ms(&sc->sc_bus, 1); 638 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 639 if (!hcr) 640 break; 641 } 642 if (hcr) { 643 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 644 return EIO; 645 } 646 647 /* Enable interrupts */ 648 DPRINTF("enabling interrupts", 0, 0, 0, 0); 649 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 650 651 return 0; 652 653 #if 0 654 bad2: 655 ehci_free_sqh(sc, sc->sc_async_head); 656 #endif 657 bad1: 658 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 659 return err; 660 } 661 662 int 663 ehci_intr(void *v) 664 { 665 ehci_softc_t *sc = v; 666 int ret = 0; 667 668 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 669 670 if (sc == NULL) 671 return 0; 672 673 mutex_spin_enter(&sc->sc_intr_lock); 674 675 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 676 goto done; 677 678 /* If we get an interrupt while polling, then just ignore it. */ 679 if (sc->sc_bus.ub_usepolling) { 680 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 681 682 if (intrs) 683 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 684 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 685 goto done; 686 } 687 688 ret = ehci_intr1(sc); 689 690 done: 691 mutex_spin_exit(&sc->sc_intr_lock); 692 return ret; 693 } 694 695 Static int 696 ehci_intr1(ehci_softc_t *sc) 697 { 698 uint32_t intrs, eintrs; 699 700 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 701 702 /* In case the interrupt occurs before initialization has completed. */ 703 if (sc == NULL) { 704 #ifdef DIAGNOSTIC 705 printf("ehci_intr1: sc == NULL\n"); 706 #endif 707 return 0; 708 } 709 710 KASSERT(mutex_owned(&sc->sc_intr_lock)); 711 712 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 713 if (!intrs) 714 return 0; 715 716 eintrs = intrs & sc->sc_eintrs; 717 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 718 EOREAD4(sc, EHCI_USBSTS), eintrs); 719 if (!eintrs) 720 return 0; 721 722 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 723 if (eintrs & EHCI_STS_IAA) { 724 DPRINTF("door bell", 0, 0, 0, 0); 725 kpreempt_disable(); 726 KASSERT(sc->sc_doorbell_si != NULL); 727 softint_schedule(sc->sc_doorbell_si); 728 kpreempt_enable(); 729 eintrs &= ~EHCI_STS_IAA; 730 } 731 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 732 DPRINTF("INT=%jd ERRINT=%jd", 733 eintrs & EHCI_STS_INT ? 1 : 0, 734 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 735 usb_schedsoftintr(&sc->sc_bus); 736 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 737 } 738 if (eintrs & EHCI_STS_HSE) { 739 printf("%s: unrecoverable error, controller halted\n", 740 device_xname(sc->sc_dev)); 741 /* XXX what else */ 742 } 743 if (eintrs & EHCI_STS_PCD) { 744 kpreempt_disable(); 745 KASSERT(sc->sc_pcd_si != NULL); 746 softint_schedule(sc->sc_pcd_si); 747 kpreempt_enable(); 748 eintrs &= ~EHCI_STS_PCD; 749 } 750 751 if (eintrs != 0) { 752 /* Block unprocessed interrupts. */ 753 sc->sc_eintrs &= ~eintrs; 754 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 755 printf("%s: blocking intrs 0x%x\n", 756 device_xname(sc->sc_dev), eintrs); 757 } 758 759 return 1; 760 } 761 762 Static void 763 ehci_doorbell(void *addr) 764 { 765 ehci_softc_t *sc = addr; 766 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 cv_broadcast(&sc->sc_doorbell); 770 mutex_exit(&sc->sc_lock); 771 } 772 773 Static void 774 ehci_pcd(void *addr) 775 { 776 ehci_softc_t *sc = addr; 777 struct usbd_xfer *xfer; 778 u_char *p; 779 int i, m; 780 781 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 782 783 mutex_enter(&sc->sc_lock); 784 xfer = sc->sc_intrxfer; 785 786 if (xfer == NULL) { 787 /* Just ignore the change. */ 788 goto done; 789 } 790 791 p = xfer->ux_buf; 792 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 793 memset(p, 0, xfer->ux_length); 794 for (i = 1; i <= m; i++) { 795 /* Pick out CHANGE bits from the status reg. */ 796 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 797 p[i/8] |= 1 << (i%8); 798 if (i % 8 == 7) 799 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 800 } 801 xfer->ux_actlen = xfer->ux_length; 802 xfer->ux_status = USBD_NORMAL_COMPLETION; 803 804 usb_transfer_complete(xfer); 805 806 done: 807 mutex_exit(&sc->sc_lock); 808 } 809 810 Static void 811 ehci_softintr(void *v) 812 { 813 struct usbd_bus *bus = v; 814 ehci_softc_t *sc = EHCI_BUS2SC(bus); 815 struct ehci_xfer *ex, *nextex; 816 817 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 818 819 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 820 821 ex_completeq_t cq; 822 TAILQ_INIT(&cq); 823 824 /* 825 * The only explanation I can think of for why EHCI is as brain dead 826 * as UHCI interrupt-wise is that Intel was involved in both. 827 * An interrupt just tells us that something is done, we have no 828 * clue what, so we need to scan through all active transfers. :-( 829 */ 830 831 /* 832 * ehci_idone will remove transfer from sc->sc_intrhead if it's 833 * complete and add to our cq list 834 * 835 */ 836 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 837 switch (ex->ex_type) { 838 case EX_CTRL: 839 case EX_BULK: 840 case EX_INTR: 841 ehci_check_qh_intr(sc, ex, &cq); 842 break; 843 case EX_ISOC: 844 ehci_check_itd_intr(sc, ex, &cq); 845 break; 846 case EX_FS_ISOC: 847 ehci_check_sitd_intr(sc, ex, &cq); 848 break; 849 default: 850 KASSERT(false); 851 } 852 853 } 854 855 /* 856 * We abuse ex_next for the interrupt and complete lists and 857 * interrupt transfers will get re-added here so use 858 * the _SAFE version of TAILQ_FOREACH. 859 */ 860 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 861 usb_transfer_complete(&ex->ex_xfer); 862 } 863 864 /* Schedule a callout to catch any dropped transactions. */ 865 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 866 !TAILQ_EMPTY(&sc->sc_intrhead)) 867 callout_reset(&sc->sc_tmo_intrlist, 868 hz, ehci_intrlist_timeout, sc); 869 } 870 871 Static void 872 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 873 { 874 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 875 uint32_t status; 876 877 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 878 879 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 880 881 if (ex->ex_type == EX_CTRL) { 882 fsqtd = ex->ex_setup; 883 lsqtd = ex->ex_status; 884 } else { 885 fsqtd = ex->ex_sqtdstart; 886 lsqtd = ex->ex_sqtdend; 887 } 888 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 889 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 890 891 /* 892 * If the last TD is still active we need to check whether there 893 * is an error somewhere in the middle, or whether there was a 894 * short packet (SPD and not ACTIVE). 895 */ 896 usb_syncmem(&lsqtd->dma, 897 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 898 sizeof(lsqtd->qtd.qtd_status), 899 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 900 status = le32toh(lsqtd->qtd.qtd_status); 901 usb_syncmem(&lsqtd->dma, 902 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 903 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 904 if (status & EHCI_QTD_ACTIVE) { 905 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 906 907 /* last qTD has already been checked */ 908 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 909 usb_syncmem(&sqtd->dma, 910 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 911 sizeof(sqtd->qtd.qtd_status), 912 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 913 status = le32toh(sqtd->qtd.qtd_status); 914 usb_syncmem(&sqtd->dma, 915 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 916 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 917 /* If there's an active QTD the xfer isn't done. */ 918 if (status & EHCI_QTD_ACTIVE) 919 break; 920 /* Any kind of error makes the xfer done. */ 921 if (status & EHCI_QTD_HALTED) 922 goto done; 923 /* Handle short packets */ 924 if (EHCI_QTD_GET_BYTES(status) != 0) { 925 /* 926 * If we get here for a control transfer then 927 * we need to let the hardware complete the 928 * status phase. That is, we're not done 929 * quite yet. 930 * 931 * Otherwise, we're done. 932 */ 933 if (ex->ex_type == EX_CTRL) { 934 break; 935 } 936 goto done; 937 } 938 } 939 DPRINTFN(10, "ex=%#jx std=%#jx still active", 940 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 941 #ifdef EHCI_DEBUG 942 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 943 ehci_dump_sqtds(ex->ex_sqtdstart); 944 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 945 #endif 946 return; 947 } 948 done: 949 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 950 ehci_idone(ex, cq); 951 } 952 953 Static void 954 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 955 { 956 ehci_soft_itd_t *itd; 957 int i; 958 959 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 960 961 KASSERT(mutex_owned(&sc->sc_lock)); 962 963 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 964 return; 965 966 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 967 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 968 969 itd = ex->ex_itdend; 970 971 /* 972 * check no active transfers in last itd, meaning we're finished 973 */ 974 975 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 976 sizeof(itd->itd.itd_ctl), 977 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 978 979 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 980 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 981 break; 982 } 983 984 if (i == EHCI_ITD_NUFRAMES) { 985 goto done; /* All 8 descriptors inactive, it's done */ 986 } 987 988 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 989 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 990 991 DPRINTFN(10, "ex %#jx itd %#jx still active", 992 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 993 return; 994 done: 995 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 996 ehci_idone(ex, cq); 997 } 998 999 void 1000 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1001 { 1002 ehci_soft_sitd_t *sitd; 1003 1004 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1005 1006 KASSERT(mutex_owned(&sc->sc_lock)); 1007 1008 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1009 return; 1010 1011 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1012 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1013 1014 sitd = ex->ex_sitdend; 1015 1016 /* 1017 * check no active transfers in last sitd, meaning we're finished 1018 */ 1019 1020 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1021 sizeof(sitd->sitd.sitd_trans), 1022 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1023 1024 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1025 1026 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1027 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1028 1029 if (active) 1030 return; 1031 1032 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1033 ehci_idone(ex, cq); 1034 } 1035 1036 1037 Static void 1038 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1039 { 1040 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1041 struct usbd_xfer *xfer = &ex->ex_xfer; 1042 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1043 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1044 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1045 uint32_t status = 0, nstatus = 0; 1046 int actlen = 0; 1047 1048 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1049 1050 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1051 1052 /* 1053 * If software has completed it, either by cancellation 1054 * or timeout, drop it on the floor. 1055 */ 1056 if (xfer->ux_status != USBD_IN_PROGRESS) { 1057 KASSERT(xfer->ux_status == USBD_CANCELLED || 1058 xfer->ux_status == USBD_TIMEOUT); 1059 DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1060 return; 1061 } 1062 1063 /* 1064 * Cancel the timeout and the task, which have not yet 1065 * run. If they have already fired, at worst they are 1066 * waiting for the lock. They will see that the xfer 1067 * is no longer in progress and give up. 1068 */ 1069 callout_stop(&xfer->ux_callout); 1070 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 1071 1072 #ifdef DIAGNOSTIC 1073 #ifdef EHCI_DEBUG 1074 if (ex->ex_isdone) { 1075 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1076 ehci_dump_exfer(ex); 1077 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1078 } 1079 #endif 1080 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1081 ex->ex_type, xfer->ux_status); 1082 ex->ex_isdone = true; 1083 #endif 1084 1085 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1086 (uintptr_t)epipe, 0, 0); 1087 1088 /* The transfer is done, compute actual length and status. */ 1089 if (ex->ex_type == EX_ISOC) { 1090 /* HS isoc transfer */ 1091 1092 struct ehci_soft_itd *itd; 1093 int i, nframes, len, uframes; 1094 1095 nframes = 0; 1096 1097 #ifdef EHCI_DEBUG 1098 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1099 ehci_dump_itds(ex->ex_itdstart); 1100 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1101 #endif 1102 1103 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1104 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1105 1106 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1107 usb_syncmem(&itd->dma, 1108 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1109 sizeof(itd->itd.itd_ctl), 1110 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1111 1112 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1113 /* 1114 * XXX - driver didn't fill in the frame full 1115 * of uframes. This leads to scheduling 1116 * inefficiencies, but working around 1117 * this doubles complexity of tracking 1118 * an xfer. 1119 */ 1120 if (nframes >= xfer->ux_nframes) 1121 break; 1122 1123 status = le32toh(itd->itd.itd_ctl[i]); 1124 len = EHCI_ITD_GET_LEN(status); 1125 if (EHCI_ITD_GET_STATUS(status) != 0) 1126 len = 0; /*No valid data on error*/ 1127 1128 xfer->ux_frlengths[nframes++] = len; 1129 actlen += len; 1130 } 1131 usb_syncmem(&itd->dma, 1132 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1133 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1134 1135 if (nframes >= xfer->ux_nframes) 1136 break; 1137 } 1138 1139 xfer->ux_actlen = actlen; 1140 xfer->ux_status = USBD_NORMAL_COMPLETION; 1141 goto end; 1142 } else if (ex->ex_type == EX_FS_ISOC) { 1143 /* FS isoc transfer */ 1144 struct ehci_soft_sitd *sitd; 1145 int nframes, len; 1146 1147 nframes = 0; 1148 1149 for (sitd = ex->ex_sitdstart; sitd != NULL; 1150 sitd = sitd->xfer_next) { 1151 usb_syncmem(&sitd->dma, 1152 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1153 sizeof(sitd->sitd.sitd_trans), 1154 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1155 1156 /* 1157 * XXX - driver didn't fill in the frame full 1158 * of uframes. This leads to scheduling 1159 * inefficiencies, but working around 1160 * this doubles complexity of tracking 1161 * an xfer. 1162 */ 1163 if (nframes >= xfer->ux_nframes) 1164 break; 1165 1166 status = le32toh(sitd->sitd.sitd_trans); 1167 usb_syncmem(&sitd->dma, 1168 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1169 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1170 1171 len = EHCI_SITD_GET_LEN(status); 1172 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1173 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1174 /* No valid data on error */ 1175 len = xfer->ux_frlengths[nframes]; 1176 } 1177 1178 /* 1179 * frlengths[i]: # of bytes to send 1180 * len: # of bytes host didn't send 1181 */ 1182 xfer->ux_frlengths[nframes] -= len; 1183 /* frlengths[i]: # of bytes host sent */ 1184 actlen += xfer->ux_frlengths[nframes++]; 1185 1186 if (nframes >= xfer->ux_nframes) 1187 break; 1188 } 1189 1190 xfer->ux_actlen = actlen; 1191 xfer->ux_status = USBD_NORMAL_COMPLETION; 1192 goto end; 1193 } 1194 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1195 ex->ex_type == EX_BULK); 1196 1197 /* Continue processing xfers using queue heads */ 1198 if (ex->ex_type == EX_CTRL) { 1199 fsqtd = ex->ex_setup; 1200 lsqtd = ex->ex_status; 1201 } else { 1202 fsqtd = ex->ex_sqtdstart; 1203 lsqtd = ex->ex_sqtdend; 1204 } 1205 #ifdef EHCI_DEBUG 1206 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1207 ehci_dump_sqtds(fsqtd); 1208 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1209 #endif 1210 1211 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1212 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1213 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1214 nstatus = le32toh(sqtd->qtd.qtd_status); 1215 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1216 BUS_DMASYNC_PREREAD); 1217 if (nstatus & EHCI_QTD_ACTIVE) 1218 break; 1219 1220 status = nstatus; 1221 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1222 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1223 } 1224 1225 /* 1226 * If there are left over TDs we need to update the toggle. 1227 * The default pipe doesn't need it since control transfers 1228 * start the toggle at 0 every time. 1229 * For a short transfer we need to update the toggle for the missing 1230 * packets within the qTD. 1231 */ 1232 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1233 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1234 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1235 status, nstatus, 0, 0); 1236 #if 0 1237 ehci_dump_sqh(epipe->sqh); 1238 ehci_dump_sqtds(ex->ex_sqtdstart); 1239 #endif 1240 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1241 } 1242 1243 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1244 status, 0); 1245 xfer->ux_actlen = actlen; 1246 if (status & EHCI_QTD_HALTED) { 1247 #ifdef EHCI_DEBUG 1248 DPRINTF("halted addr=%jd endpt=0x%02jx", 1249 xfer->ux_pipe->up_dev->ud_addr, 1250 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1251 0, 0); 1252 DPRINTF("cerr=%jd pid=%jd", 1253 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1254 0, 0); 1255 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1256 status & EHCI_QTD_ACTIVE ? 1 : 0, 1257 status & EHCI_QTD_HALTED ? 1 : 0, 1258 status & EHCI_QTD_BUFERR ? 1 : 0, 1259 status & EHCI_QTD_BABBLE ? 1 : 0); 1260 1261 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1262 status & EHCI_QTD_XACTERR ? 1 : 0, 1263 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1264 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1265 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1266 1267 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1268 ehci_dump_sqh(epipe->sqh); 1269 ehci_dump_sqtds(ex->ex_sqtdstart); 1270 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1271 #endif 1272 /* low&full speed has an extra error flag */ 1273 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1274 EHCI_QH_SPEED_HIGH) 1275 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1276 else 1277 status &= EHCI_QTD_STATERRS; 1278 if (status == 0) /* no other errors means a stall */ { 1279 xfer->ux_status = USBD_STALLED; 1280 } else { 1281 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1282 } 1283 /* XXX need to reset TT on missed microframe */ 1284 if (status & EHCI_QTD_MISSEDMICRO) { 1285 printf("%s: missed microframe, TT reset not " 1286 "implemented, hub might be inoperational\n", 1287 device_xname(sc->sc_dev)); 1288 } 1289 } else { 1290 xfer->ux_status = USBD_NORMAL_COMPLETION; 1291 } 1292 1293 end: 1294 1295 ehci_del_intr_list(sc, ex); 1296 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1297 1298 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1299 } 1300 1301 Static void 1302 ehci_poll(struct usbd_bus *bus) 1303 { 1304 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1305 1306 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1307 1308 #ifdef EHCI_DEBUG 1309 static int last; 1310 int new; 1311 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1312 if (new != last) { 1313 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1314 last = new; 1315 } 1316 #endif 1317 1318 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1319 mutex_spin_enter(&sc->sc_intr_lock); 1320 ehci_intr1(sc); 1321 mutex_spin_exit(&sc->sc_intr_lock); 1322 } 1323 } 1324 1325 void 1326 ehci_childdet(device_t self, device_t child) 1327 { 1328 struct ehci_softc *sc = device_private(self); 1329 1330 KASSERT(sc->sc_child == child); 1331 sc->sc_child = NULL; 1332 } 1333 1334 int 1335 ehci_detach(struct ehci_softc *sc, int flags) 1336 { 1337 int rv = 0; 1338 1339 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1340 1341 if (sc->sc_child != NULL) 1342 rv = config_detach(sc->sc_child, flags); 1343 1344 if (rv != 0) 1345 return rv; 1346 1347 if (sc->sc_ncomp > 0) { 1348 mutex_enter(&sc->sc_complock); 1349 /* XXX try to halt callout instead of waiting */ 1350 while (sc->sc_comp_state == CO_SCHED) 1351 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1352 mutex_exit(&sc->sc_complock); 1353 1354 callout_halt(&sc->sc_compcallout, NULL); 1355 callout_destroy(&sc->sc_compcallout); 1356 cv_destroy(&sc->sc_compcv); 1357 mutex_destroy(&sc->sc_complock); 1358 } 1359 1360 callout_halt(&sc->sc_tmo_intrlist, NULL); 1361 callout_destroy(&sc->sc_tmo_intrlist); 1362 1363 /* XXX free other data structures XXX */ 1364 if (sc->sc_softitds) 1365 kmem_free(sc->sc_softitds, 1366 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1367 cv_destroy(&sc->sc_doorbell); 1368 1369 #if 0 1370 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1371 1372 softint_disestablish(sc->sc_doorbell_si); 1373 softint_disestablish(sc->sc_pcd_si); 1374 1375 mutex_destroy(&sc->sc_lock); 1376 mutex_destroy(&sc->sc_intr_lock); 1377 #endif 1378 1379 pool_cache_destroy(sc->sc_xferpool); 1380 1381 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1382 1383 return rv; 1384 } 1385 1386 1387 int 1388 ehci_activate(device_t self, enum devact act) 1389 { 1390 struct ehci_softc *sc = device_private(self); 1391 1392 switch (act) { 1393 case DVACT_DEACTIVATE: 1394 sc->sc_dying = 1; 1395 return 0; 1396 default: 1397 return EOPNOTSUPP; 1398 } 1399 } 1400 1401 /* 1402 * Handle suspend/resume. 1403 * 1404 * We need to switch to polling mode here, because this routine is 1405 * called from an interrupt context. This is all right since we 1406 * are almost suspended anyway. 1407 * 1408 * Note that this power handler isn't to be registered directly; the 1409 * bus glue needs to call out to it. 1410 */ 1411 bool 1412 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1413 { 1414 ehci_softc_t *sc = device_private(dv); 1415 int i; 1416 uint32_t cmd, hcr; 1417 1418 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1419 1420 mutex_spin_enter(&sc->sc_intr_lock); 1421 sc->sc_bus.ub_usepolling++; 1422 mutex_spin_exit(&sc->sc_intr_lock); 1423 1424 for (i = 1; i <= sc->sc_noport; i++) { 1425 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1426 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1427 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1428 } 1429 1430 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1431 1432 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1433 EOWRITE4(sc, EHCI_USBCMD, cmd); 1434 1435 for (i = 0; i < 100; i++) { 1436 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1437 if (hcr == 0) 1438 break; 1439 1440 usb_delay_ms(&sc->sc_bus, 1); 1441 } 1442 if (hcr != 0) 1443 printf("%s: reset timeout\n", device_xname(dv)); 1444 1445 cmd &= ~EHCI_CMD_RS; 1446 EOWRITE4(sc, EHCI_USBCMD, cmd); 1447 1448 for (i = 0; i < 100; i++) { 1449 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1450 if (hcr == EHCI_STS_HCH) 1451 break; 1452 1453 usb_delay_ms(&sc->sc_bus, 1); 1454 } 1455 if (hcr != EHCI_STS_HCH) 1456 printf("%s: config timeout\n", device_xname(dv)); 1457 1458 mutex_spin_enter(&sc->sc_intr_lock); 1459 sc->sc_bus.ub_usepolling--; 1460 mutex_spin_exit(&sc->sc_intr_lock); 1461 1462 return true; 1463 } 1464 1465 bool 1466 ehci_resume(device_t dv, const pmf_qual_t *qual) 1467 { 1468 ehci_softc_t *sc = device_private(dv); 1469 int i; 1470 uint32_t cmd, hcr; 1471 1472 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1473 1474 /* restore things in case the bios sucks */ 1475 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1476 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1477 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1478 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1479 1480 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1481 1482 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1483 1484 hcr = 0; 1485 for (i = 1; i <= sc->sc_noport; i++) { 1486 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1487 if ((cmd & EHCI_PS_PO) == 0 && 1488 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1489 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1490 hcr = 1; 1491 } 1492 } 1493 1494 if (hcr) { 1495 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1496 1497 for (i = 1; i <= sc->sc_noport; i++) { 1498 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1499 if ((cmd & EHCI_PS_PO) == 0 && 1500 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1501 EOWRITE4(sc, EHCI_PORTSC(i), 1502 cmd & ~EHCI_PS_FPR); 1503 } 1504 } 1505 1506 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1507 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1508 1509 for (i = 0; i < 100; i++) { 1510 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1511 if (hcr != EHCI_STS_HCH) 1512 break; 1513 1514 usb_delay_ms(&sc->sc_bus, 1); 1515 } 1516 if (hcr == EHCI_STS_HCH) 1517 printf("%s: config timeout\n", device_xname(dv)); 1518 1519 return true; 1520 } 1521 1522 /* 1523 * Shut down the controller when the system is going down. 1524 */ 1525 bool 1526 ehci_shutdown(device_t self, int flags) 1527 { 1528 ehci_softc_t *sc = device_private(self); 1529 1530 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1531 1532 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1533 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1534 return true; 1535 } 1536 1537 Static struct usbd_xfer * 1538 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1539 { 1540 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1541 struct usbd_xfer *xfer; 1542 1543 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1544 if (xfer != NULL) { 1545 memset(xfer, 0, sizeof(struct ehci_xfer)); 1546 1547 /* Initialise this always so we can call remove on it. */ 1548 usb_init_task(&xfer->ux_aborttask, ehci_timeout_task, xfer, 1549 USB_TASKQ_MPSAFE); 1550 #ifdef DIAGNOSTIC 1551 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1552 ex->ex_isdone = true; 1553 xfer->ux_state = XFER_BUSY; 1554 #endif 1555 } 1556 return xfer; 1557 } 1558 1559 Static void 1560 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1561 { 1562 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1563 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1564 1565 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1566 xfer->ux_status == USBD_NOT_STARTED, 1567 "xfer %p state %d\n", xfer, xfer->ux_state); 1568 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1569 1570 #ifdef DIAGNOSTIC 1571 xfer->ux_state = XFER_FREE; 1572 #endif 1573 1574 pool_cache_put(sc->sc_xferpool, xfer); 1575 } 1576 1577 Static void 1578 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1579 { 1580 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1581 1582 *lock = &sc->sc_lock; 1583 } 1584 1585 Static void 1586 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1587 { 1588 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1589 1590 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1591 1592 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1593 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1594 #ifdef EHCI_DEBUG 1595 if (ehcidebug) 1596 usbd_dump_pipe(pipe); 1597 #endif 1598 epipe->nexttoggle = 0; 1599 } 1600 1601 Static void 1602 ehci_noop(struct usbd_pipe *pipe) 1603 { 1604 } 1605 1606 #ifdef EHCI_DEBUG 1607 /* 1608 * Unused function - this is meant to be called from a kernel 1609 * debugger. 1610 */ 1611 void 1612 ehci_dump(void) 1613 { 1614 ehci_softc_t *sc = theehci; 1615 int i; 1616 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1617 EOREAD4(sc, EHCI_USBCMD), 1618 EOREAD4(sc, EHCI_USBSTS), 1619 EOREAD4(sc, EHCI_USBINTR)); 1620 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1621 EOREAD4(sc, EHCI_FRINDEX), 1622 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1623 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1624 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1625 for (i = 1; i <= sc->sc_noport; i++) 1626 printf("port %d status=0x%08x\n", i, 1627 EOREAD4(sc, EHCI_PORTSC(i))); 1628 } 1629 1630 Static void 1631 ehci_dump_regs(ehci_softc_t *sc) 1632 { 1633 int i; 1634 1635 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1636 1637 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1638 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1639 EOREAD4(sc, EHCI_USBINTR), 0); 1640 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1641 "async = 0x%08jx", 1642 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1643 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1644 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1645 for (i = 1; i <= sc->sc_noport; i += 2) { 1646 if (i == sc->sc_noport) { 1647 DPRINTF("port %jd status = 0x%08jx", i, 1648 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1649 } else { 1650 DPRINTF("port %jd status = 0x%08jx port %jd " 1651 "status = 0x%08jx", 1652 i, EOREAD4(sc, EHCI_PORTSC(i)), 1653 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1654 } 1655 } 1656 } 1657 1658 #define ehci_dump_link(link, type) do { \ 1659 DPRINTF(" link 0x%08jx (T = %jd):", \ 1660 link, \ 1661 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1662 if (type) { \ 1663 DPRINTF( \ 1664 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1665 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1666 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1667 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1668 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1669 } \ 1670 } while(0) 1671 1672 Static void 1673 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1674 { 1675 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1676 int i; 1677 uint32_t stop = 0; 1678 1679 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1680 ehci_dump_sqtd(sqtd); 1681 usb_syncmem(&sqtd->dma, 1682 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1683 sizeof(sqtd->qtd), 1684 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1685 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1686 usb_syncmem(&sqtd->dma, 1687 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1688 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1689 } 1690 if (!stop) 1691 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1692 } 1693 1694 Static void 1695 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1696 { 1697 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1698 1699 usb_syncmem(&sqtd->dma, sqtd->offs, 1700 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1701 1702 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1703 0, 0); 1704 ehci_dump_qtd(&sqtd->qtd); 1705 1706 usb_syncmem(&sqtd->dma, sqtd->offs, 1707 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1708 } 1709 1710 Static void 1711 ehci_dump_qtd(ehci_qtd_t *qtd) 1712 { 1713 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1714 uint32_t s = le32toh(qtd->qtd_status); 1715 1716 DPRINTFN(10, 1717 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1718 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1719 DPRINTFN(10, 1720 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1721 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1722 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1723 DPRINTFN(10, 1724 " cerr = %jd pid = %jd stat = %jx", 1725 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1726 0); 1727 DPRINTFN(10, 1728 "active =%jd halted=%jd buferr=%jd babble=%jd", 1729 s & EHCI_QTD_ACTIVE ? 1 : 0, 1730 s & EHCI_QTD_HALTED ? 1 : 0, 1731 s & EHCI_QTD_BUFERR ? 1 : 0, 1732 s & EHCI_QTD_BABBLE ? 1 : 0); 1733 DPRINTFN(10, 1734 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1735 s & EHCI_QTD_XACTERR ? 1 : 0, 1736 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1737 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1738 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1739 DPRINTFN(10, 1740 "buffer[0] = %#jx buffer[1] = %#jx " 1741 "buffer[2] = %#jx buffer[3] = %#jx", 1742 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1743 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1744 DPRINTFN(10, 1745 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1746 } 1747 1748 Static void 1749 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1750 { 1751 ehci_qh_t *qh = &sqh->qh; 1752 ehci_link_t link; 1753 uint32_t endp, endphub; 1754 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1755 1756 usb_syncmem(&sqh->dma, sqh->offs, 1757 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1758 1759 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1760 link = le32toh(qh->qh_link); 1761 ehci_dump_link(link, true); 1762 1763 endp = le32toh(qh->qh_endp); 1764 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1765 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1766 "eps = %jd", 1767 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1768 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1769 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1770 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1771 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1772 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1773 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1774 1775 endphub = le32toh(qh->qh_endphub); 1776 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1777 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1778 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1779 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1780 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1781 EHCI_QH_GET_MULT(endphub), 0); 1782 1783 link = le32toh(qh->qh_curqtd); 1784 ehci_dump_link(link, false); 1785 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1786 ehci_dump_qtd(&qh->qh_qtd); 1787 1788 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1789 BUS_DMASYNC_PREREAD); 1790 } 1791 1792 Static void 1793 ehci_dump_itds(ehci_soft_itd_t *itd) 1794 { 1795 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1796 int i; 1797 uint32_t stop = 0; 1798 1799 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1800 ehci_dump_itd(itd); 1801 usb_syncmem(&itd->dma, 1802 itd->offs + offsetof(ehci_itd_t, itd_next), 1803 sizeof(itd->itd), 1804 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1805 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1806 usb_syncmem(&itd->dma, 1807 itd->offs + offsetof(ehci_itd_t, itd_next), 1808 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1809 } 1810 if (!stop) 1811 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1812 } 1813 1814 Static void 1815 ehci_dump_itd(struct ehci_soft_itd *itd) 1816 { 1817 ehci_isoc_trans_t t; 1818 ehci_isoc_bufr_ptr_t b, b2, b3; 1819 int i; 1820 1821 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1822 1823 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1824 1825 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1826 t = le32toh(itd->itd.itd_ctl[i]); 1827 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1828 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1829 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1830 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1831 EHCI_ITD_GET_OFFS(t), 0); 1832 } 1833 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1834 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1835 DPRINTF(" %jx", 1836 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1837 1838 b = le32toh(itd->itd.itd_bufr[0]); 1839 b2 = le32toh(itd->itd.itd_bufr[1]); 1840 b3 = le32toh(itd->itd.itd_bufr[2]); 1841 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1842 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1843 DPRINTF(" maxpkt = %jx multi = %jx", 1844 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1845 } 1846 1847 Static void 1848 ehci_dump_sitd(struct ehci_soft_itd *itd) 1849 { 1850 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1851 1852 DPRINTF("SITD %#jx next = %p prev = %#jx", 1853 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1854 (uintptr_t)itd->frame_list.prev, 0); 1855 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1856 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1857 } 1858 1859 Static void 1860 ehci_dump_exfer(struct ehci_xfer *ex) 1861 { 1862 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1863 1864 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1865 ex->ex_isdone, 0); 1866 1867 switch (ex->ex_type) { 1868 case EX_CTRL: 1869 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1870 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1871 (uintptr_t)ex->ex_status, 0); 1872 break; 1873 case EX_BULK: 1874 case EX_INTR: 1875 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1876 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1877 0, 0); 1878 break; 1879 case EX_ISOC: 1880 DPRINTF(" itdstart = %#jx itdend = %#jx", 1881 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1882 break; 1883 case EX_FS_ISOC: 1884 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1885 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1886 0, 0); 1887 break; 1888 default: 1889 DPRINTF(" unknown type", 0, 0, 0, 0); 1890 } 1891 } 1892 #endif 1893 1894 Static usbd_status 1895 ehci_open(struct usbd_pipe *pipe) 1896 { 1897 struct usbd_device *dev = pipe->up_dev; 1898 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1899 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1900 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1901 uint8_t addr = dev->ud_addr; 1902 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1903 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1904 ehci_soft_qh_t *sqh; 1905 usbd_status err; 1906 int ival, speed, naks; 1907 int hshubaddr, hshubport; 1908 1909 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1910 1911 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1912 ed->bEndpointAddress, rhaddr); 1913 1914 if (dev->ud_myhsport) { 1915 /* 1916 * When directly attached FS/LS device while doing embedded 1917 * transaction translations and we are the hub, set the hub 1918 * address to 0 (us). 1919 */ 1920 if (!(sc->sc_flags & EHCIF_ETTF) 1921 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1922 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1923 } else { 1924 hshubaddr = 0; 1925 } 1926 hshubport = dev->ud_myhsport->up_portno; 1927 } else { 1928 hshubaddr = 0; 1929 hshubport = 0; 1930 } 1931 1932 if (sc->sc_dying) 1933 return USBD_IOERROR; 1934 1935 /* toggle state needed for bulk endpoints */ 1936 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1937 1938 if (addr == rhaddr) { 1939 switch (ed->bEndpointAddress) { 1940 case USB_CONTROL_ENDPOINT: 1941 pipe->up_methods = &roothub_ctrl_methods; 1942 break; 1943 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1944 pipe->up_methods = &ehci_root_intr_methods; 1945 break; 1946 default: 1947 DPRINTF("bad bEndpointAddress 0x%02jx", 1948 ed->bEndpointAddress, 0, 0, 0); 1949 return USBD_INVAL; 1950 } 1951 return USBD_NORMAL_COMPLETION; 1952 } 1953 1954 /* XXX All this stuff is only valid for async. */ 1955 switch (dev->ud_speed) { 1956 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1957 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1958 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1959 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1960 } 1961 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1962 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1963 0); 1964 return USBD_INVAL; 1965 } 1966 1967 /* 1968 * For interrupt transfer, nak throttling must be disabled, but for 1969 * the other transfer type, nak throttling should be enabled from the 1970 * viewpoint that avoids the memory thrashing. 1971 */ 1972 naks = (xfertype == UE_INTERRUPT) ? 0 1973 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1974 1975 /* Allocate sqh for everything, save isoc xfers */ 1976 if (xfertype != UE_ISOCHRONOUS) { 1977 sqh = ehci_alloc_sqh(sc); 1978 if (sqh == NULL) 1979 return USBD_NOMEM; 1980 /* qh_link filled when the QH is added */ 1981 sqh->qh.qh_endp = htole32( 1982 EHCI_QH_SET_ADDR(addr) | 1983 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1984 EHCI_QH_SET_EPS(speed) | 1985 EHCI_QH_DTC | 1986 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1987 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1988 EHCI_QH_CTL : 0) | 1989 EHCI_QH_SET_NRL(naks) 1990 ); 1991 sqh->qh.qh_endphub = htole32( 1992 EHCI_QH_SET_MULT(1) | 1993 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1994 ); 1995 if (speed != EHCI_QH_SPEED_HIGH) 1996 sqh->qh.qh_endphub |= htole32( 1997 EHCI_QH_SET_PORT(hshubport) | 1998 EHCI_QH_SET_HUBA(hshubaddr) | 1999 (xfertype == UE_INTERRUPT ? 2000 EHCI_QH_SET_CMASK(0x08) : 0) 2001 ); 2002 sqh->qh.qh_curqtd = EHCI_NULL; 2003 /* Fill the overlay qTD */ 2004 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2005 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2006 sqh->qh.qh_qtd.qtd_status = htole32(0); 2007 2008 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2009 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2010 epipe->sqh = sqh; 2011 } else { 2012 sqh = NULL; 2013 } /*xfertype == UE_ISOC*/ 2014 2015 switch (xfertype) { 2016 case UE_CONTROL: 2017 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2018 0, &epipe->ctrl.reqdma); 2019 #ifdef EHCI_DEBUG 2020 if (err) 2021 printf("ehci_open: usb_allocmem()=%d\n", err); 2022 #endif 2023 if (err) 2024 goto bad; 2025 pipe->up_methods = &ehci_device_ctrl_methods; 2026 mutex_enter(&sc->sc_lock); 2027 ehci_add_qh(sc, sqh, sc->sc_async_head); 2028 mutex_exit(&sc->sc_lock); 2029 break; 2030 case UE_BULK: 2031 pipe->up_methods = &ehci_device_bulk_methods; 2032 mutex_enter(&sc->sc_lock); 2033 ehci_add_qh(sc, sqh, sc->sc_async_head); 2034 mutex_exit(&sc->sc_lock); 2035 break; 2036 case UE_INTERRUPT: 2037 pipe->up_methods = &ehci_device_intr_methods; 2038 ival = pipe->up_interval; 2039 if (ival == USBD_DEFAULT_INTERVAL) { 2040 if (speed == EHCI_QH_SPEED_HIGH) { 2041 if (ed->bInterval > 16) { 2042 /* 2043 * illegal with high-speed, but there 2044 * were documentation bugs in the spec, 2045 * so be generous 2046 */ 2047 ival = 256; 2048 } else 2049 ival = (1 << (ed->bInterval - 1)) / 8; 2050 } else 2051 ival = ed->bInterval; 2052 } 2053 err = ehci_device_setintr(sc, sqh, ival); 2054 if (err) 2055 goto bad; 2056 break; 2057 case UE_ISOCHRONOUS: 2058 pipe->up_serialise = false; 2059 if (speed == EHCI_QH_SPEED_HIGH) 2060 pipe->up_methods = &ehci_device_isoc_methods; 2061 else 2062 pipe->up_methods = &ehci_device_fs_isoc_methods; 2063 if (ed->bInterval == 0 || ed->bInterval > 16) { 2064 printf("ehci: opening pipe with invalid bInterval\n"); 2065 err = USBD_INVAL; 2066 goto bad; 2067 } 2068 if (UGETW(ed->wMaxPacketSize) == 0) { 2069 printf("ehci: zero length endpoint open request\n"); 2070 err = USBD_INVAL; 2071 goto bad; 2072 } 2073 epipe->isoc.next_frame = 0; 2074 epipe->isoc.cur_xfers = 0; 2075 break; 2076 default: 2077 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2078 err = USBD_INVAL; 2079 goto bad; 2080 } 2081 return USBD_NORMAL_COMPLETION; 2082 2083 bad: 2084 if (sqh != NULL) { 2085 mutex_enter(&sc->sc_lock); 2086 ehci_free_sqh(sc, sqh); 2087 mutex_exit(&sc->sc_lock); 2088 } 2089 return err; 2090 } 2091 2092 /* 2093 * Add an ED to the schedule. Called with USB lock held. 2094 */ 2095 Static void 2096 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2097 { 2098 2099 KASSERT(mutex_owned(&sc->sc_lock)); 2100 2101 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2102 2103 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2104 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2105 2106 sqh->next = head->next; 2107 sqh->qh.qh_link = head->qh.qh_link; 2108 2109 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2110 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2111 2112 head->next = sqh; 2113 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2114 2115 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2116 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2117 2118 #ifdef EHCI_DEBUG 2119 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2120 ehci_dump_sqh(sqh); 2121 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2122 #endif 2123 } 2124 2125 /* 2126 * Remove an ED from the schedule. Called with USB lock held. 2127 */ 2128 Static void 2129 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2130 { 2131 ehci_soft_qh_t *p; 2132 2133 KASSERT(mutex_owned(&sc->sc_lock)); 2134 2135 /* XXX */ 2136 for (p = head; p != NULL && p->next != sqh; p = p->next) 2137 ; 2138 if (p == NULL) 2139 panic("ehci_rem_qh: ED not found"); 2140 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2141 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2142 p->next = sqh->next; 2143 p->qh.qh_link = sqh->qh.qh_link; 2144 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2145 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2146 2147 ehci_sync_hc(sc); 2148 } 2149 2150 Static void 2151 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2152 { 2153 int i; 2154 uint32_t status; 2155 2156 /* Save toggle bit and ping status. */ 2157 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2158 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2159 status = sqh->qh.qh_qtd.qtd_status & 2160 htole32(EHCI_QTD_TOGGLE_MASK | 2161 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2162 /* Set HALTED to make hw leave it alone. */ 2163 sqh->qh.qh_qtd.qtd_status = 2164 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2165 usb_syncmem(&sqh->dma, 2166 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2167 sizeof(sqh->qh.qh_qtd.qtd_status), 2168 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2169 sqh->qh.qh_curqtd = 0; 2170 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2171 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2172 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2173 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2174 sqh->sqtd = sqtd; 2175 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2177 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2178 sqh->qh.qh_qtd.qtd_status = status; 2179 usb_syncmem(&sqh->dma, 2180 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2181 sizeof(sqh->qh.qh_qtd.qtd_status), 2182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2183 } 2184 2185 /* 2186 * Ensure that the HC has released all references to the QH. We do this 2187 * by asking for a Async Advance Doorbell interrupt and then we wait for 2188 * the interrupt. 2189 * To make this easier we first obtain exclusive use of the doorbell. 2190 */ 2191 Static void 2192 ehci_sync_hc(ehci_softc_t *sc) 2193 { 2194 int error __diagused; 2195 2196 KASSERT(mutex_owned(&sc->sc_lock)); 2197 2198 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2199 2200 if (sc->sc_dying) { 2201 DPRINTF("dying", 0, 0, 0, 0); 2202 return; 2203 } 2204 2205 /* ask for doorbell */ 2206 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2207 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2208 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2209 2210 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2211 2212 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2213 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2214 #ifdef DIAGNOSTIC 2215 if (error == EWOULDBLOCK) { 2216 printf("ehci_sync_hc: timed out\n"); 2217 } else if (error) { 2218 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2219 } 2220 #endif 2221 } 2222 2223 Static void 2224 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2225 { 2226 2227 KASSERT(mutex_owned(&sc->sc_lock)); 2228 2229 for (; itd != NULL; itd = itd->xfer_next) { 2230 struct ehci_soft_itd *prev = itd->frame_list.prev; 2231 2232 /* Unlink itd from hardware chain, or frame array */ 2233 if (prev == NULL) { /* We're at the table head */ 2234 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2235 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2236 usb_syncmem(&sc->sc_fldma, 2237 sizeof(ehci_link_t) * itd->slot, 2238 sizeof(ehci_link_t), 2239 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2240 2241 if (itd->frame_list.next != NULL) 2242 itd->frame_list.next->frame_list.prev = NULL; 2243 } else { 2244 /* XXX this part is untested... */ 2245 prev->itd.itd_next = itd->itd.itd_next; 2246 usb_syncmem(&itd->dma, 2247 itd->offs + offsetof(ehci_itd_t, itd_next), 2248 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2249 2250 prev->frame_list.next = itd->frame_list.next; 2251 if (itd->frame_list.next != NULL) 2252 itd->frame_list.next->frame_list.prev = prev; 2253 } 2254 } 2255 } 2256 2257 Static void 2258 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2259 { 2260 struct ehci_soft_itd *next; 2261 2262 mutex_enter(&sc->sc_lock); 2263 next = NULL; 2264 for (; itd != NULL; itd = next) { 2265 next = itd->xfer_next; 2266 ehci_free_itd_locked(sc, itd); 2267 } 2268 mutex_exit(&sc->sc_lock); 2269 } 2270 2271 Static void 2272 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2273 { 2274 2275 KASSERT(mutex_owned(&sc->sc_lock)); 2276 2277 for (; sitd != NULL; sitd = sitd->xfer_next) { 2278 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2279 2280 /* Unlink sitd from hardware chain, or frame array */ 2281 if (prev == NULL) { /* We're at the table head */ 2282 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2283 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2284 usb_syncmem(&sc->sc_fldma, 2285 sizeof(ehci_link_t) * sitd->slot, 2286 sizeof(ehci_link_t), 2287 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2288 2289 if (sitd->frame_list.next != NULL) 2290 sitd->frame_list.next->frame_list.prev = NULL; 2291 } else { 2292 /* XXX this part is untested... */ 2293 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2294 usb_syncmem(&sitd->dma, 2295 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2296 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2297 2298 prev->frame_list.next = sitd->frame_list.next; 2299 if (sitd->frame_list.next != NULL) 2300 sitd->frame_list.next->frame_list.prev = prev; 2301 } 2302 } 2303 } 2304 2305 Static void 2306 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2307 { 2308 2309 mutex_enter(&sc->sc_lock); 2310 struct ehci_soft_sitd *next = NULL; 2311 for (; sitd != NULL; sitd = next) { 2312 next = sitd->xfer_next; 2313 ehci_free_sitd_locked(sc, sitd); 2314 } 2315 mutex_exit(&sc->sc_lock); 2316 } 2317 2318 /***********/ 2319 2320 Static int 2321 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2322 void *buf, int buflen) 2323 { 2324 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2325 usb_hub_descriptor_t hubd; 2326 usb_port_status_t ps; 2327 uint16_t len, value, index; 2328 int l, totlen = 0; 2329 int port, i; 2330 uint32_t v; 2331 2332 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2333 2334 if (sc->sc_dying) 2335 return -1; 2336 2337 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2338 0, 0); 2339 2340 len = UGETW(req->wLength); 2341 value = UGETW(req->wValue); 2342 index = UGETW(req->wIndex); 2343 2344 #define C(x,y) ((x) | ((y) << 8)) 2345 switch (C(req->bRequest, req->bmRequestType)) { 2346 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2347 if (len == 0) 2348 break; 2349 switch (value) { 2350 #define sd ((usb_string_descriptor_t *)buf) 2351 case C(2, UDESC_STRING): 2352 /* Product */ 2353 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2354 break; 2355 #undef sd 2356 default: 2357 /* default from usbroothub */ 2358 return buflen; 2359 } 2360 break; 2361 2362 /* Hub requests */ 2363 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2364 break; 2365 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2366 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2367 value, 0, 0); 2368 if (index < 1 || index > sc->sc_noport) { 2369 return -1; 2370 } 2371 port = EHCI_PORTSC(index); 2372 v = EOREAD4(sc, port); 2373 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2374 v &= ~EHCI_PS_CLEAR; 2375 switch (value) { 2376 case UHF_PORT_ENABLE: 2377 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2378 break; 2379 case UHF_PORT_SUSPEND: 2380 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2381 break; 2382 v &= ~EHCI_PS_SUSP; 2383 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2384 /* see USB2 spec ch. 7.1.7.7 */ 2385 usb_delay_ms(&sc->sc_bus, 20); 2386 EOWRITE4(sc, port, v); 2387 usb_delay_ms(&sc->sc_bus, 2); 2388 #ifdef DEBUG 2389 v = EOREAD4(sc, port); 2390 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2391 printf("ehci: resume failed: %x\n", v); 2392 #endif 2393 break; 2394 case UHF_PORT_POWER: 2395 if (sc->sc_hasppc) 2396 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2397 break; 2398 case UHF_PORT_TEST: 2399 DPRINTF("clear port test %jd", index, 0, 0, 0); 2400 break; 2401 case UHF_PORT_INDICATOR: 2402 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2403 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2404 break; 2405 case UHF_C_PORT_CONNECTION: 2406 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2407 break; 2408 case UHF_C_PORT_ENABLE: 2409 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2410 break; 2411 case UHF_C_PORT_SUSPEND: 2412 /* how? */ 2413 break; 2414 case UHF_C_PORT_OVER_CURRENT: 2415 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2416 break; 2417 case UHF_C_PORT_RESET: 2418 sc->sc_isreset[index] = 0; 2419 break; 2420 default: 2421 return -1; 2422 } 2423 #if 0 2424 switch(value) { 2425 case UHF_C_PORT_CONNECTION: 2426 case UHF_C_PORT_ENABLE: 2427 case UHF_C_PORT_SUSPEND: 2428 case UHF_C_PORT_OVER_CURRENT: 2429 case UHF_C_PORT_RESET: 2430 default: 2431 break; 2432 } 2433 #endif 2434 break; 2435 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2436 if (len == 0) 2437 break; 2438 if ((value & 0xff) != 0) { 2439 return -1; 2440 } 2441 totlen = uimin(buflen, sizeof(hubd)); 2442 memcpy(&hubd, buf, totlen); 2443 hubd.bNbrPorts = sc->sc_noport; 2444 v = EOREAD4(sc, EHCI_HCSPARAMS); 2445 USETW(hubd.wHubCharacteristics, 2446 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2447 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2448 ? UHD_PORT_IND : 0); 2449 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2450 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2451 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2452 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2453 totlen = uimin(totlen, hubd.bDescLength); 2454 memcpy(buf, &hubd, totlen); 2455 break; 2456 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2457 if (len != 4) { 2458 return -1; 2459 } 2460 memset(buf, 0, len); /* ? XXX */ 2461 totlen = len; 2462 break; 2463 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2464 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2465 if (index < 1 || index > sc->sc_noport) { 2466 return -1; 2467 } 2468 if (len != 4) { 2469 return -1; 2470 } 2471 v = EOREAD4(sc, EHCI_PORTSC(index)); 2472 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2473 2474 i = UPS_HIGH_SPEED; 2475 if (sc->sc_flags & EHCIF_ETTF) { 2476 /* 2477 * If we are doing embedded transaction translation, 2478 * then directly attached LS/FS devices are reset by 2479 * the EHCI controller itself. PSPD is encoded 2480 * the same way as in USBSTATUS. 2481 */ 2482 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2483 } 2484 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2485 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2486 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2487 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2488 if (v & EHCI_PS_PR) i |= UPS_RESET; 2489 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2490 if (sc->sc_vendor_port_status) 2491 i = sc->sc_vendor_port_status(sc, v, i); 2492 USETW(ps.wPortStatus, i); 2493 i = 0; 2494 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2495 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2496 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2497 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2498 USETW(ps.wPortChange, i); 2499 totlen = uimin(len, sizeof(ps)); 2500 memcpy(buf, &ps, totlen); 2501 break; 2502 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2503 return -1; 2504 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2505 break; 2506 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2507 if (index < 1 || index > sc->sc_noport) { 2508 return -1; 2509 } 2510 port = EHCI_PORTSC(index); 2511 v = EOREAD4(sc, port); 2512 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2513 v &= ~EHCI_PS_CLEAR; 2514 switch(value) { 2515 case UHF_PORT_ENABLE: 2516 EOWRITE4(sc, port, v | EHCI_PS_PE); 2517 break; 2518 case UHF_PORT_SUSPEND: 2519 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2520 break; 2521 case UHF_PORT_RESET: 2522 DPRINTF("reset port %jd", index, 0, 0, 0); 2523 if (EHCI_PS_IS_LOWSPEED(v) 2524 && sc->sc_ncomp > 0 2525 && !(sc->sc_flags & EHCIF_ETTF)) { 2526 /* 2527 * Low speed device on non-ETTF controller or 2528 * unaccompanied controller, give up ownership. 2529 */ 2530 ehci_disown(sc, index, 1); 2531 break; 2532 } 2533 /* Start reset sequence. */ 2534 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2535 EOWRITE4(sc, port, v | EHCI_PS_PR); 2536 /* Wait for reset to complete. */ 2537 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2538 if (sc->sc_dying) { 2539 return -1; 2540 } 2541 /* 2542 * An embedded transaction translator will automatically 2543 * terminate the reset sequence so there's no need to 2544 * it. 2545 */ 2546 v = EOREAD4(sc, port); 2547 if (v & EHCI_PS_PR) { 2548 /* Terminate reset sequence. */ 2549 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2550 /* Wait for HC to complete reset. */ 2551 usb_delay_ms(&sc->sc_bus, 2552 EHCI_PORT_RESET_COMPLETE); 2553 if (sc->sc_dying) { 2554 return -1; 2555 } 2556 } 2557 2558 v = EOREAD4(sc, port); 2559 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2560 if (v & EHCI_PS_PR) { 2561 printf("%s: port reset timeout\n", 2562 device_xname(sc->sc_dev)); 2563 return USBD_TIMEOUT; 2564 } 2565 if (!(v & EHCI_PS_PE)) { 2566 /* Not a high speed device, give up ownership.*/ 2567 ehci_disown(sc, index, 0); 2568 break; 2569 } 2570 sc->sc_isreset[index] = 1; 2571 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2572 v, 0, 0); 2573 break; 2574 case UHF_PORT_POWER: 2575 DPRINTF("set port power %jd (has PPC = %jd)", index, 2576 sc->sc_hasppc, 0, 0); 2577 if (sc->sc_hasppc) 2578 EOWRITE4(sc, port, v | EHCI_PS_PP); 2579 break; 2580 case UHF_PORT_TEST: 2581 DPRINTF("set port test %jd", index, 0, 0, 0); 2582 break; 2583 case UHF_PORT_INDICATOR: 2584 DPRINTF("set port ind %jd", index, 0, 0, 0); 2585 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2586 break; 2587 default: 2588 return -1; 2589 } 2590 break; 2591 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2592 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2593 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2594 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2595 break; 2596 default: 2597 /* default from usbroothub */ 2598 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2599 2600 return buflen; 2601 } 2602 2603 DPRINTF("returning %jd", totlen, 0, 0, 0); 2604 2605 return totlen; 2606 } 2607 2608 /* 2609 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2610 * 2611 * This pile of garbage below works around the following problem without 2612 * holding boots with no hand-over devices present, while penalising 2613 * boots where the first ehci probe hands off devices with a 5 second 2614 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2615 * for RB_SINGLE, but the same basic issue exists. 2616 * 2617 * The way ehci hand-off works, the companion controller does not get the 2618 * device until after its' initial bus explore, so the reference dropped 2619 * after the first explore is not enough. 5 seconds should be enough, 2620 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2621 * 2622 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2623 * if the callback is scheduled. CO_DONE is set when the callout has 2624 * called config_pending_decr(). 2625 * 2626 * There's a mutex, a cv and a callout here, and we delay detach if the 2627 * callout has been set. 2628 */ 2629 #ifndef EHCI_DISOWN_DELAY_SECONDS 2630 #define EHCI_DISOWN_DELAY_SECONDS 5 2631 #endif 2632 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2633 2634 static void 2635 ehci_disown_callback(void *arg) 2636 { 2637 ehci_softc_t *sc = arg; 2638 2639 config_pending_decr(sc->sc_dev); 2640 2641 mutex_enter(&sc->sc_complock); 2642 KASSERT(sc->sc_comp_state == CO_SCHED); 2643 sc->sc_comp_state = CO_DONE; 2644 cv_signal(&sc->sc_compcv); 2645 mutex_exit(&sc->sc_complock); 2646 } 2647 2648 static void 2649 ehci_disown_sched_callback(ehci_softc_t *sc) 2650 { 2651 extern bool root_is_mounted; 2652 2653 mutex_enter(&sc->sc_complock); 2654 2655 if (root_is_mounted || 2656 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2657 sc->sc_comp_state != CO_EARLY) { 2658 mutex_exit(&sc->sc_complock); 2659 return; 2660 } 2661 2662 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2663 ehci_disown_callback, &sc->sc_dev); 2664 sc->sc_comp_state = CO_SCHED; 2665 2666 mutex_exit(&sc->sc_complock); 2667 2668 config_pending_incr(sc->sc_dev); 2669 aprint_normal("delaying %s by %u seconds due to USB owner change.", 2670 (boothowto & RB_ASKNAME) == 0 ? "ask root" : "single user", 2671 ehci_disown_delay_seconds); 2672 } 2673 2674 Static void 2675 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2676 { 2677 int port; 2678 uint32_t v; 2679 2680 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2681 2682 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2683 if (sc->sc_npcomp != 0) { 2684 int i = (index-1) / sc->sc_npcomp; 2685 if (i < sc->sc_ncomp) { 2686 ehci_disown_sched_callback(sc); 2687 #ifdef DIAGNOSTIC 2688 printf("%s: handing over %s speed device on " 2689 "port %d to %s\n", 2690 device_xname(sc->sc_dev), 2691 lowspeed ? "low" : "full", 2692 index, sc->sc_comps[i] ? 2693 device_xname(sc->sc_comps[i]) : 2694 "companion controller"); 2695 } else { 2696 printf("%s: strange port\n", 2697 device_xname(sc->sc_dev)); 2698 #endif 2699 } 2700 } else { 2701 #ifdef DIAGNOSTIC 2702 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2703 #endif 2704 } 2705 port = EHCI_PORTSC(index); 2706 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2707 EOWRITE4(sc, port, v | EHCI_PS_PO); 2708 } 2709 2710 Static usbd_status 2711 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2712 { 2713 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2714 usbd_status err; 2715 2716 /* Insert last in queue. */ 2717 mutex_enter(&sc->sc_lock); 2718 err = usb_insert_transfer(xfer); 2719 mutex_exit(&sc->sc_lock); 2720 if (err) 2721 return err; 2722 2723 /* Pipe isn't running, start first */ 2724 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2725 } 2726 2727 Static usbd_status 2728 ehci_root_intr_start(struct usbd_xfer *xfer) 2729 { 2730 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2731 const bool polling = sc->sc_bus.ub_usepolling; 2732 2733 if (sc->sc_dying) 2734 return USBD_IOERROR; 2735 2736 if (!polling) 2737 mutex_enter(&sc->sc_lock); 2738 sc->sc_intrxfer = xfer; 2739 if (!polling) 2740 mutex_exit(&sc->sc_lock); 2741 2742 return USBD_IN_PROGRESS; 2743 } 2744 2745 /* Abort a root interrupt request. */ 2746 Static void 2747 ehci_root_intr_abort(struct usbd_xfer *xfer) 2748 { 2749 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2750 2751 KASSERT(mutex_owned(&sc->sc_lock)); 2752 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2753 2754 sc->sc_intrxfer = NULL; 2755 2756 xfer->ux_status = USBD_CANCELLED; 2757 usb_transfer_complete(xfer); 2758 } 2759 2760 /* Close the root pipe. */ 2761 Static void 2762 ehci_root_intr_close(struct usbd_pipe *pipe) 2763 { 2764 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2765 2766 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2767 2768 KASSERT(mutex_owned(&sc->sc_lock)); 2769 2770 sc->sc_intrxfer = NULL; 2771 } 2772 2773 Static void 2774 ehci_root_intr_done(struct usbd_xfer *xfer) 2775 { 2776 } 2777 2778 /************************/ 2779 2780 Static ehci_soft_qh_t * 2781 ehci_alloc_sqh(ehci_softc_t *sc) 2782 { 2783 ehci_soft_qh_t *sqh; 2784 usbd_status err; 2785 int i, offs; 2786 usb_dma_t dma; 2787 2788 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2789 2790 mutex_enter(&sc->sc_lock); 2791 if (sc->sc_freeqhs == NULL) { 2792 DPRINTF("allocating chunk", 0, 0, 0, 0); 2793 mutex_exit(&sc->sc_lock); 2794 2795 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2796 EHCI_PAGE_SIZE, &dma); 2797 #ifdef EHCI_DEBUG 2798 if (err) 2799 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2800 #endif 2801 if (err) 2802 return NULL; 2803 2804 mutex_enter(&sc->sc_lock); 2805 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2806 offs = i * EHCI_SQH_SIZE; 2807 sqh = KERNADDR(&dma, offs); 2808 sqh->physaddr = DMAADDR(&dma, offs); 2809 sqh->dma = dma; 2810 sqh->offs = offs; 2811 sqh->next = sc->sc_freeqhs; 2812 sc->sc_freeqhs = sqh; 2813 } 2814 } 2815 sqh = sc->sc_freeqhs; 2816 sc->sc_freeqhs = sqh->next; 2817 mutex_exit(&sc->sc_lock); 2818 2819 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2820 sqh->next = NULL; 2821 return sqh; 2822 } 2823 2824 Static void 2825 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2826 { 2827 KASSERT(mutex_owned(&sc->sc_lock)); 2828 2829 sqh->next = sc->sc_freeqhs; 2830 sc->sc_freeqhs = sqh; 2831 } 2832 2833 Static ehci_soft_qtd_t * 2834 ehci_alloc_sqtd(ehci_softc_t *sc) 2835 { 2836 ehci_soft_qtd_t *sqtd = NULL; 2837 usbd_status err; 2838 int i, offs; 2839 usb_dma_t dma; 2840 2841 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2842 2843 mutex_enter(&sc->sc_lock); 2844 if (sc->sc_freeqtds == NULL) { 2845 DPRINTF("allocating chunk", 0, 0, 0, 0); 2846 mutex_exit(&sc->sc_lock); 2847 2848 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2849 EHCI_PAGE_SIZE, &dma); 2850 #ifdef EHCI_DEBUG 2851 if (err) 2852 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2853 #endif 2854 if (err) 2855 goto done; 2856 2857 mutex_enter(&sc->sc_lock); 2858 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2859 offs = i * EHCI_SQTD_SIZE; 2860 sqtd = KERNADDR(&dma, offs); 2861 sqtd->physaddr = DMAADDR(&dma, offs); 2862 sqtd->dma = dma; 2863 sqtd->offs = offs; 2864 2865 sqtd->nextqtd = sc->sc_freeqtds; 2866 sc->sc_freeqtds = sqtd; 2867 } 2868 } 2869 2870 sqtd = sc->sc_freeqtds; 2871 sc->sc_freeqtds = sqtd->nextqtd; 2872 mutex_exit(&sc->sc_lock); 2873 2874 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2875 sqtd->nextqtd = NULL; 2876 sqtd->xfer = NULL; 2877 2878 done: 2879 return sqtd; 2880 } 2881 2882 Static void 2883 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2884 { 2885 2886 mutex_enter(&sc->sc_lock); 2887 sqtd->nextqtd = sc->sc_freeqtds; 2888 sc->sc_freeqtds = sqtd; 2889 mutex_exit(&sc->sc_lock); 2890 } 2891 2892 Static int 2893 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2894 int alen, int rd, ehci_soft_qtd_t **sp) 2895 { 2896 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2897 uint16_t flags = xfer->ux_flags; 2898 2899 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2900 2901 ASSERT_SLEEPABLE(); 2902 KASSERT(sp); 2903 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2904 2905 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2906 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2907 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2908 KM_SLEEP); 2909 exfer->ex_nsqtd = nsqtd; 2910 2911 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2912 alen, nsqtd, flags); 2913 2914 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2915 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2916 if (cur == NULL) 2917 goto nomem; 2918 exfer->ex_sqtds[j++] = cur; 2919 2920 cur->xfer = xfer; 2921 cur->len = 0; 2922 2923 } 2924 2925 *sp = exfer->ex_sqtds[0]; 2926 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2927 2928 return 0; 2929 2930 nomem: 2931 ehci_free_sqtds(sc, exfer); 2932 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2933 DPRINTF("no memory", 0, 0, 0, 0); 2934 return ENOMEM; 2935 } 2936 2937 Static void 2938 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2939 { 2940 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2941 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2942 2943 mutex_enter(&sc->sc_lock); 2944 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2945 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2946 2947 if (sqtd == NULL) 2948 break; 2949 2950 sqtd->nextqtd = sc->sc_freeqtds; 2951 sc->sc_freeqtds = sqtd; 2952 } 2953 mutex_exit(&sc->sc_lock); 2954 } 2955 2956 Static void 2957 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2958 { 2959 if (prev) { 2960 prev->nextqtd = sqtd; 2961 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2962 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2963 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2964 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2965 } 2966 } 2967 2968 Static void 2969 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2970 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2971 { 2972 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2973 usb_dma_t *dma = &xfer->ux_dmabuf; 2974 uint16_t flags = xfer->ux_flags; 2975 ehci_soft_qtd_t *sqtd, *prev; 2976 int tog = *toggle; 2977 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2978 int len = length; 2979 2980 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2981 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2982 len, isread, tog); 2983 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2984 0, 0, 0); 2985 2986 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2987 2988 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2989 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2990 EHCI_QTD_SET_CERR(3) 2991 ; 2992 2993 sqtd = prev = NULL; 2994 size_t curoffs = 0; 2995 size_t j = 0; 2996 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2997 sqtd = exfer->ex_sqtds[j++]; 2998 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 2999 (uintptr_t)prev, 0); 3000 3001 /* 3002 * The EHCI hardware can handle at most 5 pages and they do 3003 * not have to be contiguous 3004 */ 3005 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3006 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3007 size_t curlen = len; 3008 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3009 /* must use multiple TDs, fill as much as possible. */ 3010 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3011 3012 /* the length must be a multiple of the max size */ 3013 curlen -= curlen % mps; 3014 } 3015 KASSERT(curlen != 0); 3016 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3017 curoffs, 0); 3018 3019 /* Fill the qTD */ 3020 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3021 sqtd->qtd.qtd_status = htole32( 3022 qtdstatus | 3023 EHCI_QTD_SET_BYTES(curlen) | 3024 EHCI_QTD_SET_TOGGLE(tog)); 3025 3026 /* Find number of pages we'll be using, insert dma addresses */ 3027 size_t pages = EHCI_NPAGES(curlen); 3028 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3029 size_t pageoffs = EHCI_PAGE(curoffs); 3030 for (size_t i = 0; i < pages; i++) { 3031 paddr_t a = DMAADDR(dma, 3032 pageoffs + i * EHCI_PAGE_SIZE); 3033 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 3034 /* Cast up to avoid compiler warnings */ 3035 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 3036 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3037 i, pages, 3038 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3039 le32toh(sqtd->qtd.qtd_buffer[i])); 3040 } 3041 /* First buffer pointer requires a page offset to start at */ 3042 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3043 3044 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3045 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3046 3047 sqtd->len = curlen; 3048 3049 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3050 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3051 3052 ehci_append_sqtd(sqtd, prev); 3053 3054 if (((curlen + mps - 1) / mps) & 1) { 3055 tog ^= 1; 3056 } 3057 3058 curoffs += curlen; 3059 len -= curlen; 3060 } 3061 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3062 xfer, length, len, mps, exfer->ex_nsqtd, j); 3063 3064 if (!isread && 3065 (flags & USBD_FORCE_SHORT_XFER) && 3066 length % mps == 0) { 3067 /* Force a 0 length transfer at the end. */ 3068 3069 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3070 exfer->ex_nsqtd); 3071 prev = sqtd; 3072 sqtd = exfer->ex_sqtds[j++]; 3073 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3074 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3075 sqtd->qtd.qtd_status = htole32( 3076 qtdstatus | 3077 EHCI_QTD_SET_BYTES(0) | 3078 EHCI_QTD_SET_TOGGLE(tog)); 3079 3080 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3081 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3082 3083 ehci_append_sqtd(sqtd, prev); 3084 tog ^= 1; 3085 } 3086 3087 *lsqtd = sqtd; 3088 *toggle = tog; 3089 } 3090 3091 Static ehci_soft_itd_t * 3092 ehci_alloc_itd(ehci_softc_t *sc) 3093 { 3094 struct ehci_soft_itd *itd, *freeitd; 3095 usbd_status err; 3096 usb_dma_t dma; 3097 3098 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3099 3100 mutex_enter(&sc->sc_lock); 3101 3102 freeitd = LIST_FIRST(&sc->sc_freeitds); 3103 if (freeitd == NULL) { 3104 DPRINTF("allocating chunk", 0, 0, 0, 0); 3105 mutex_exit(&sc->sc_lock); 3106 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3107 EHCI_PAGE_SIZE, &dma); 3108 3109 if (err) { 3110 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3111 return NULL; 3112 } 3113 mutex_enter(&sc->sc_lock); 3114 3115 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3116 int offs = i * EHCI_ITD_SIZE; 3117 itd = KERNADDR(&dma, offs); 3118 itd->physaddr = DMAADDR(&dma, offs); 3119 itd->dma = dma; 3120 itd->offs = offs; 3121 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3122 } 3123 freeitd = LIST_FIRST(&sc->sc_freeitds); 3124 } 3125 3126 itd = freeitd; 3127 LIST_REMOVE(itd, free_list); 3128 mutex_exit(&sc->sc_lock); 3129 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3130 3131 itd->frame_list.next = NULL; 3132 itd->frame_list.prev = NULL; 3133 itd->xfer_next = NULL; 3134 itd->slot = 0; 3135 3136 return itd; 3137 } 3138 3139 Static ehci_soft_sitd_t * 3140 ehci_alloc_sitd(ehci_softc_t *sc) 3141 { 3142 struct ehci_soft_sitd *sitd, *freesitd; 3143 usbd_status err; 3144 int i, offs; 3145 usb_dma_t dma; 3146 3147 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3148 3149 mutex_enter(&sc->sc_lock); 3150 freesitd = LIST_FIRST(&sc->sc_freesitds); 3151 if (freesitd == NULL) { 3152 DPRINTF("allocating chunk", 0, 0, 0, 0); 3153 mutex_exit(&sc->sc_lock); 3154 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3155 EHCI_PAGE_SIZE, &dma); 3156 3157 if (err) { 3158 DPRINTF("alloc returned %jd", err, 0, 0, 3159 0); 3160 return NULL; 3161 } 3162 3163 mutex_enter(&sc->sc_lock); 3164 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3165 offs = i * EHCI_SITD_SIZE; 3166 sitd = KERNADDR(&dma, offs); 3167 sitd->physaddr = DMAADDR(&dma, offs); 3168 sitd->dma = dma; 3169 sitd->offs = offs; 3170 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3171 } 3172 freesitd = LIST_FIRST(&sc->sc_freesitds); 3173 } 3174 3175 sitd = freesitd; 3176 LIST_REMOVE(sitd, free_list); 3177 mutex_exit(&sc->sc_lock); 3178 3179 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3180 3181 sitd->frame_list.next = NULL; 3182 sitd->frame_list.prev = NULL; 3183 sitd->xfer_next = NULL; 3184 sitd->slot = 0; 3185 3186 return sitd; 3187 } 3188 3189 /****************/ 3190 3191 /* 3192 * Close a reqular pipe. 3193 * Assumes that there are no pending transactions. 3194 */ 3195 Static void 3196 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3197 { 3198 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3199 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3200 ehci_soft_qh_t *sqh = epipe->sqh; 3201 3202 KASSERT(mutex_owned(&sc->sc_lock)); 3203 3204 ehci_rem_qh(sc, sqh, head); 3205 ehci_free_sqh(sc, epipe->sqh); 3206 } 3207 3208 /* 3209 * Cancel or timeout a device request. We have two cases to deal with 3210 * 3211 * 1) A driver wants to stop scheduled or inflight transfers 3212 * 2) A transfer has timed out 3213 * 3214 * have (partially) happened since the hardware runs concurrently. 3215 * 3216 * Transfer state is protected by the bus lock and we set the transfer status 3217 * as soon as either of the above happens (with bus lock held). 3218 * 3219 * Then we arrange for the hardware to tells us that it is not still 3220 * processing the TDs by setting the QH halted bit and wait for the ehci 3221 * door bell 3222 */ 3223 Static void 3224 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3225 { 3226 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3227 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3228 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3229 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3230 ehci_soft_qh_t *sqh = epipe->sqh; 3231 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3232 ehci_physaddr_t cur; 3233 uint32_t qhstatus; 3234 int hit; 3235 3236 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 3237 "invalid status for abort: %d", (int)status); 3238 3239 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3240 3241 KASSERT(mutex_owned(&sc->sc_lock)); 3242 ASSERT_SLEEPABLE(); 3243 3244 if (status == USBD_CANCELLED) { 3245 /* 3246 * We are synchronously aborting. Try to stop the 3247 * callout and task, but if we can't, wait for them to 3248 * complete. 3249 */ 3250 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3251 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 3252 USB_TASKQ_HC, &sc->sc_lock); 3253 } else { 3254 /* Otherwise, we are timing out. */ 3255 KASSERT(status == USBD_TIMEOUT); 3256 } 3257 3258 /* 3259 * The xfer cannot have been cancelled already. It is the 3260 * responsibility of the caller of usbd_abort_pipe not to try 3261 * to abort a pipe multiple times, whether concurrently or 3262 * sequentially. 3263 */ 3264 KASSERT(xfer->ux_status != USBD_CANCELLED); 3265 3266 /* Only the timeout, which runs only once, can time it out. */ 3267 KASSERT(xfer->ux_status != USBD_TIMEOUT); 3268 3269 /* If anyone else beat us, we're done. */ 3270 if (xfer->ux_status != USBD_IN_PROGRESS) 3271 return; 3272 3273 /* We beat everyone else. Claim the status. */ 3274 xfer->ux_status = status; 3275 3276 /* 3277 * If we're dying, skip the hardware action and just notify the 3278 * software that we're done. 3279 */ 3280 if (sc->sc_dying) { 3281 goto dying; 3282 } 3283 3284 /* 3285 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3286 */ 3287 ehci_del_intr_list(sc, exfer); 3288 3289 usb_syncmem(&sqh->dma, 3290 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3291 sizeof(sqh->qh.qh_qtd.qtd_status), 3292 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3293 qhstatus = sqh->qh.qh_qtd.qtd_status; 3294 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3295 usb_syncmem(&sqh->dma, 3296 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3297 sizeof(sqh->qh.qh_qtd.qtd_status), 3298 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3299 3300 if (exfer->ex_type == EX_CTRL) { 3301 fsqtd = exfer->ex_setup; 3302 lsqtd = exfer->ex_status; 3303 } else { 3304 fsqtd = exfer->ex_sqtdstart; 3305 lsqtd = exfer->ex_sqtdend; 3306 } 3307 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3308 usb_syncmem(&sqtd->dma, 3309 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3310 sizeof(sqtd->qtd.qtd_status), 3311 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3312 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3313 usb_syncmem(&sqtd->dma, 3314 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3315 sizeof(sqtd->qtd.qtd_status), 3316 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3317 if (sqtd == lsqtd) 3318 break; 3319 } 3320 3321 /* 3322 * HC Step 2: Wait until we know hardware has finished any possible 3323 * use of the xfer. 3324 */ 3325 ehci_sync_hc(sc); 3326 3327 /* 3328 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3329 * The complication here is that the hardware may have executed 3330 * beyond the xfer we're trying to abort. So as we're scanning 3331 * the TDs of this xfer we check if the hardware points to 3332 * any of them. 3333 */ 3334 3335 usb_syncmem(&sqh->dma, 3336 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3337 sizeof(sqh->qh.qh_curqtd), 3338 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3339 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3340 hit = 0; 3341 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3342 hit |= cur == sqtd->physaddr; 3343 if (sqtd == lsqtd) 3344 break; 3345 } 3346 sqtd = sqtd->nextqtd; 3347 /* Zap curqtd register if hardware pointed inside the xfer. */ 3348 if (hit && sqtd != NULL) { 3349 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3350 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3351 usb_syncmem(&sqh->dma, 3352 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3353 sizeof(sqh->qh.qh_curqtd), 3354 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3355 sqh->qh.qh_qtd.qtd_status = qhstatus; 3356 usb_syncmem(&sqh->dma, 3357 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3358 sizeof(sqh->qh.qh_qtd.qtd_status), 3359 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3360 } else { 3361 DPRINTF("no hit", 0, 0, 0, 0); 3362 usb_syncmem(&sqh->dma, 3363 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3364 sizeof(sqh->qh.qh_curqtd), 3365 BUS_DMASYNC_PREREAD); 3366 } 3367 3368 /* 3369 * Final step: Notify completion to waiting xfers. 3370 */ 3371 dying: 3372 #ifdef DIAGNOSTIC 3373 exfer->ex_isdone = true; 3374 #endif 3375 usb_transfer_complete(xfer); 3376 DPRINTFN(14, "end", 0, 0, 0, 0); 3377 3378 KASSERT(mutex_owned(&sc->sc_lock)); 3379 } 3380 3381 Static void 3382 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3383 { 3384 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3385 ehci_isoc_trans_t trans_status; 3386 struct ehci_xfer *exfer; 3387 ehci_softc_t *sc; 3388 struct ehci_soft_itd *itd; 3389 struct ehci_soft_sitd *sitd; 3390 int i; 3391 3392 KASSERTMSG(status == USBD_CANCELLED, 3393 "invalid status for abort: %d", (int)status); 3394 3395 exfer = EHCI_XFER2EXFER(xfer); 3396 sc = EHCI_XFER2SC(xfer); 3397 3398 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3399 (uintptr_t)xfer->ux_pipe, 0, 0); 3400 3401 KASSERT(mutex_owned(&sc->sc_lock)); 3402 ASSERT_SLEEPABLE(); 3403 3404 /* No timeout or task here. */ 3405 3406 /* 3407 * The xfer cannot have been cancelled already. It is the 3408 * responsibility of the caller of usbd_abort_pipe not to try 3409 * to abort a pipe multiple times, whether concurrently or 3410 * sequentially. 3411 */ 3412 KASSERT(xfer->ux_status != USBD_CANCELLED); 3413 3414 /* If anyone else beat us, we're done. */ 3415 if (xfer->ux_status != USBD_IN_PROGRESS) 3416 return; 3417 3418 /* We beat everyone else. Claim the status. */ 3419 xfer->ux_status = status; 3420 3421 /* 3422 * If we're dying, skip the hardware action and just notify the 3423 * software that we're done. 3424 */ 3425 if (sc->sc_dying) { 3426 goto dying; 3427 } 3428 3429 /* 3430 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3431 */ 3432 ehci_del_intr_list(sc, exfer); 3433 3434 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3435 for (itd = exfer->ex_itdstart; itd != NULL; 3436 itd = itd->xfer_next) { 3437 usb_syncmem(&itd->dma, 3438 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3439 sizeof(itd->itd.itd_ctl), 3440 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3441 3442 for (i = 0; i < 8; i++) { 3443 trans_status = le32toh(itd->itd.itd_ctl[i]); 3444 trans_status &= ~EHCI_ITD_ACTIVE; 3445 itd->itd.itd_ctl[i] = htole32(trans_status); 3446 } 3447 3448 usb_syncmem(&itd->dma, 3449 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3450 sizeof(itd->itd.itd_ctl), 3451 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3452 } 3453 } else { 3454 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3455 sitd = sitd->xfer_next) { 3456 usb_syncmem(&sitd->dma, 3457 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3458 sizeof(sitd->sitd.sitd_buffer), 3459 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3460 3461 trans_status = le32toh(sitd->sitd.sitd_trans); 3462 trans_status &= ~EHCI_SITD_ACTIVE; 3463 sitd->sitd.sitd_trans = htole32(trans_status); 3464 3465 usb_syncmem(&sitd->dma, 3466 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3467 sizeof(sitd->sitd.sitd_buffer), 3468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3469 } 3470 } 3471 3472 dying: 3473 #ifdef DIAGNOSTIC 3474 exfer->ex_isdone = true; 3475 #endif 3476 usb_transfer_complete(xfer); 3477 DPRINTFN(14, "end", 0, 0, 0, 0); 3478 3479 KASSERT(mutex_owned(&sc->sc_lock)); 3480 } 3481 3482 Static void 3483 ehci_timeout(void *addr) 3484 { 3485 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3486 struct usbd_xfer *xfer = addr; 3487 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3488 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3489 3490 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3491 #ifdef EHCI_DEBUG 3492 if (ehcidebug >= 2) { 3493 struct usbd_pipe *pipe = xfer->ux_pipe; 3494 usbd_dump_pipe(pipe); 3495 } 3496 #endif 3497 3498 mutex_enter(&sc->sc_lock); 3499 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 3500 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3501 mutex_exit(&sc->sc_lock); 3502 } 3503 3504 Static void 3505 ehci_timeout_task(void *addr) 3506 { 3507 struct usbd_xfer *xfer = addr; 3508 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3509 3510 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3511 3512 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3513 3514 mutex_enter(&sc->sc_lock); 3515 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3516 mutex_exit(&sc->sc_lock); 3517 } 3518 3519 /************************/ 3520 3521 Static int 3522 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3523 { 3524 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3525 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3526 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3527 usb_device_request_t *req = &xfer->ux_request; 3528 ehci_soft_qtd_t *setup, *status, *next; 3529 int isread = req->bmRequestType & UT_READ; 3530 int len = xfer->ux_bufsize; 3531 int err; 3532 3533 exfer->ex_type = EX_CTRL; 3534 exfer->ex_status = NULL; 3535 exfer->ex_data = NULL; 3536 exfer->ex_setup = ehci_alloc_sqtd(sc); 3537 if (exfer->ex_setup == NULL) { 3538 err = ENOMEM; 3539 goto bad1; 3540 } 3541 exfer->ex_status = ehci_alloc_sqtd(sc); 3542 if (exfer->ex_status == NULL) { 3543 err = ENOMEM; 3544 goto bad2; 3545 } 3546 setup = exfer->ex_setup; 3547 status = exfer->ex_status; 3548 exfer->ex_nsqtd = 0; 3549 next = status; 3550 /* Set up data transaction */ 3551 if (len != 0) { 3552 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3553 &exfer->ex_data); 3554 if (err) 3555 goto bad3; 3556 next = exfer->ex_data; 3557 } 3558 3559 /* Clear toggle */ 3560 setup->qtd.qtd_status = htole32( 3561 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3562 EHCI_QTD_SET_TOGGLE(0) | 3563 EHCI_QTD_SET_BYTES(sizeof(*req)) 3564 ); 3565 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3566 setup->qtd.qtd_buffer_hi[0] = 0; 3567 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3568 setup->nextqtd = next; 3569 setup->xfer = xfer; 3570 setup->len = sizeof(*req); 3571 3572 status->qtd.qtd_status = htole32( 3573 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3574 EHCI_QTD_SET_TOGGLE(1) | 3575 EHCI_QTD_IOC 3576 ); 3577 status->qtd.qtd_buffer[0] = 0; 3578 status->qtd.qtd_buffer_hi[0] = 0; 3579 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3580 status->nextqtd = NULL; 3581 status->xfer = xfer; 3582 status->len = 0; 3583 3584 return 0; 3585 bad3: 3586 ehci_free_sqtd(sc, exfer->ex_status); 3587 bad2: 3588 ehci_free_sqtd(sc, exfer->ex_setup); 3589 bad1: 3590 return err; 3591 } 3592 3593 Static void 3594 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3595 { 3596 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3597 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3598 3599 KASSERT(ex->ex_type == EX_CTRL); 3600 3601 ehci_free_sqtd(sc, ex->ex_setup); 3602 ehci_free_sqtd(sc, ex->ex_status); 3603 ehci_free_sqtds(sc, ex); 3604 if (ex->ex_nsqtd) 3605 kmem_free(ex->ex_sqtds, 3606 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3607 } 3608 3609 Static usbd_status 3610 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3611 { 3612 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3613 usbd_status err; 3614 3615 /* Insert last in queue. */ 3616 mutex_enter(&sc->sc_lock); 3617 err = usb_insert_transfer(xfer); 3618 mutex_exit(&sc->sc_lock); 3619 if (err) 3620 return err; 3621 3622 /* Pipe isn't running, start first */ 3623 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3624 } 3625 3626 Static usbd_status 3627 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3628 { 3629 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3630 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3631 usb_device_request_t *req = &xfer->ux_request; 3632 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3633 ehci_soft_qtd_t *setup, *status, *next; 3634 ehci_soft_qh_t *sqh; 3635 const bool polling = sc->sc_bus.ub_usepolling; 3636 3637 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3638 3639 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3640 3641 if (sc->sc_dying) 3642 return USBD_IOERROR; 3643 3644 const int isread = req->bmRequestType & UT_READ; 3645 const int len = UGETW(req->wLength); 3646 3647 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3648 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3649 UGETW(req->wIndex)); 3650 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3651 len, epipe->pipe.up_dev->ud_addr, 3652 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3653 3654 sqh = epipe->sqh; 3655 3656 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3657 "address QH %" __PRIuBIT " pipe %d\n", 3658 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3659 epipe->pipe.up_dev->ud_addr); 3660 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3661 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3662 "MPS QH %" __PRIuBIT " pipe %d\n", 3663 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3664 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3665 3666 setup = exfer->ex_setup; 3667 status = exfer->ex_status; 3668 3669 DPRINTF("setup %#jx status %#jx data %#jx", 3670 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3671 KASSERTMSG(setup != NULL && status != NULL, 3672 "Failed memory allocation, setup %p status %p", 3673 setup, status); 3674 3675 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3676 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3677 3678 /* Clear toggle */ 3679 setup->qtd.qtd_status &= ~htole32( 3680 EHCI_QTD_STATUS_MASK | 3681 EHCI_QTD_BYTES_MASK | 3682 EHCI_QTD_TOGGLE_MASK | 3683 EHCI_QTD_CERR_MASK 3684 ); 3685 setup->qtd.qtd_status |= htole32( 3686 EHCI_QTD_ACTIVE | 3687 EHCI_QTD_SET_CERR(3) | 3688 EHCI_QTD_SET_TOGGLE(0) | 3689 EHCI_QTD_SET_BYTES(sizeof(*req)) 3690 ); 3691 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3692 setup->qtd.qtd_buffer_hi[0] = 0; 3693 3694 next = status; 3695 status->qtd.qtd_status &= ~htole32( 3696 EHCI_QTD_STATUS_MASK | 3697 EHCI_QTD_PID_MASK | 3698 EHCI_QTD_BYTES_MASK | 3699 EHCI_QTD_TOGGLE_MASK | 3700 EHCI_QTD_CERR_MASK 3701 ); 3702 status->qtd.qtd_status |= htole32( 3703 EHCI_QTD_ACTIVE | 3704 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3705 EHCI_QTD_SET_CERR(3) | 3706 EHCI_QTD_SET_TOGGLE(1) | 3707 EHCI_QTD_SET_BYTES(0) | 3708 EHCI_QTD_IOC 3709 ); 3710 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3711 3712 KASSERT(exfer->ex_isdone); 3713 #ifdef DIAGNOSTIC 3714 exfer->ex_isdone = false; 3715 #endif 3716 3717 /* Set up data transaction */ 3718 if (len != 0) { 3719 ehci_soft_qtd_t *end; 3720 3721 /* Start toggle at 1. */ 3722 int toggle = 1; 3723 next = exfer->ex_data; 3724 KASSERTMSG(next != NULL, "Failed memory allocation"); 3725 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3726 end->nextqtd = status; 3727 end->qtd.qtd_next = end->qtd.qtd_altnext = 3728 htole32(status->physaddr); 3729 3730 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3731 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3732 3733 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3734 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3735 } 3736 3737 setup->nextqtd = next; 3738 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3739 3740 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3741 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3742 3743 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3744 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3745 3746 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3747 3748 #ifdef EHCI_DEBUG 3749 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3750 ehci_dump_sqh(sqh); 3751 ehci_dump_sqtds(setup); 3752 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3753 #endif 3754 3755 if (!polling) 3756 mutex_enter(&sc->sc_lock); 3757 3758 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3759 ehci_set_qh_qtd(sqh, setup); 3760 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3761 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3762 ehci_timeout, xfer); 3763 } 3764 ehci_add_intr_list(sc, exfer); 3765 xfer->ux_status = USBD_IN_PROGRESS; 3766 if (!polling) 3767 mutex_exit(&sc->sc_lock); 3768 3769 #if 0 3770 #ifdef EHCI_DEBUG 3771 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3772 // delay(10000); 3773 ehci_dump_regs(sc); 3774 ehci_dump_sqh(sc->sc_async_head); 3775 ehci_dump_sqh(sqh); 3776 ehci_dump_sqtds(setup); 3777 #endif 3778 #endif 3779 3780 return USBD_IN_PROGRESS; 3781 } 3782 3783 Static void 3784 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3785 { 3786 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3787 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3788 usb_device_request_t *req = &xfer->ux_request; 3789 int len = UGETW(req->wLength); 3790 int rd = req->bmRequestType & UT_READ; 3791 3792 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3793 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3794 3795 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3796 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3797 3798 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3799 BUS_DMASYNC_POSTWRITE); 3800 if (len) 3801 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3802 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3803 3804 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3805 } 3806 3807 /* Abort a device control request. */ 3808 Static void 3809 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3810 { 3811 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3812 3813 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3814 ehci_abort_xfer(xfer, USBD_CANCELLED); 3815 } 3816 3817 /* Close a device control pipe. */ 3818 Static void 3819 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3820 { 3821 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3822 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3823 3824 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3825 3826 KASSERT(mutex_owned(&sc->sc_lock)); 3827 3828 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3829 3830 ehci_close_pipe(pipe, sc->sc_async_head); 3831 } 3832 3833 /* 3834 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3835 * qTD status, or miss signalling occasionally under heavy load. If the host 3836 * machine is too fast, we we can miss transaction completion - when we scan 3837 * the active list the transaction still seems to be active. This generally 3838 * exhibits itself as a umass stall that never recovers. 3839 * 3840 * We work around this behaviour by setting up this callback after any softintr 3841 * that completes with transactions still pending, giving us another chance to 3842 * check for completion after the writeback has taken place. 3843 */ 3844 Static void 3845 ehci_intrlist_timeout(void *arg) 3846 { 3847 ehci_softc_t *sc = arg; 3848 3849 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3850 3851 usb_schedsoftintr(&sc->sc_bus); 3852 } 3853 3854 /************************/ 3855 3856 Static int 3857 ehci_device_bulk_init(struct usbd_xfer *xfer) 3858 { 3859 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3860 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3861 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3862 int endpt = ed->bEndpointAddress; 3863 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3864 int len = xfer->ux_bufsize; 3865 int err = 0; 3866 3867 exfer->ex_type = EX_BULK; 3868 exfer->ex_nsqtd = 0; 3869 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3870 &exfer->ex_sqtdstart); 3871 3872 return err; 3873 } 3874 3875 Static void 3876 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3877 { 3878 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3879 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3880 3881 KASSERT(ex->ex_type == EX_BULK); 3882 3883 ehci_free_sqtds(sc, ex); 3884 if (ex->ex_nsqtd) 3885 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3886 } 3887 3888 Static usbd_status 3889 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3890 { 3891 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3892 usbd_status err; 3893 3894 /* Insert last in queue. */ 3895 mutex_enter(&sc->sc_lock); 3896 err = usb_insert_transfer(xfer); 3897 mutex_exit(&sc->sc_lock); 3898 if (err) 3899 return err; 3900 3901 /* Pipe isn't running, start first */ 3902 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3903 } 3904 3905 Static usbd_status 3906 ehci_device_bulk_start(struct usbd_xfer *xfer) 3907 { 3908 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3909 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3910 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3911 ehci_soft_qh_t *sqh; 3912 ehci_soft_qtd_t *end; 3913 int len, isread, endpt; 3914 const bool polling = sc->sc_bus.ub_usepolling; 3915 3916 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3917 3918 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3919 xfer->ux_flags, 0); 3920 3921 if (sc->sc_dying) 3922 return USBD_IOERROR; 3923 3924 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3925 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3926 3927 len = xfer->ux_length; 3928 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3929 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3930 sqh = epipe->sqh; 3931 3932 KASSERT(exfer->ex_isdone); 3933 #ifdef DIAGNOSTIC 3934 exfer->ex_isdone = false; 3935 #endif 3936 3937 /* Take lock here to protect nexttoggle */ 3938 if (!polling) 3939 mutex_enter(&sc->sc_lock); 3940 3941 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3942 3943 exfer->ex_sqtdend = end; 3944 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3945 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3946 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3947 3948 #ifdef EHCI_DEBUG 3949 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3950 ehci_dump_sqh(sqh); 3951 ehci_dump_sqtds(exfer->ex_sqtdstart); 3952 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3953 #endif 3954 3955 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3956 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3957 3958 /* also does usb_syncmem(sqh) */ 3959 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3960 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3961 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3962 ehci_timeout, xfer); 3963 } 3964 ehci_add_intr_list(sc, exfer); 3965 xfer->ux_status = USBD_IN_PROGRESS; 3966 if (!polling) 3967 mutex_exit(&sc->sc_lock); 3968 3969 #if 0 3970 #ifdef EHCI_DEBUG 3971 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3972 // delay(10000); 3973 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3974 ehci_dump_regs(sc); 3975 #if 0 3976 printf("async_head:\n"); 3977 ehci_dump_sqh(sc->sc_async_head); 3978 #endif 3979 DPRINTF("sqh:", 0, 0, 0, 0); 3980 ehci_dump_sqh(sqh); 3981 ehci_dump_sqtds(exfer->ex_sqtdstart); 3982 #endif 3983 #endif 3984 3985 return USBD_IN_PROGRESS; 3986 } 3987 3988 Static void 3989 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3990 { 3991 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3992 3993 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3994 ehci_abort_xfer(xfer, USBD_CANCELLED); 3995 } 3996 3997 /* 3998 * Close a device bulk pipe. 3999 */ 4000 Static void 4001 ehci_device_bulk_close(struct usbd_pipe *pipe) 4002 { 4003 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4004 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4005 4006 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4007 4008 KASSERT(mutex_owned(&sc->sc_lock)); 4009 4010 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4011 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4012 ehci_close_pipe(pipe, sc->sc_async_head); 4013 } 4014 4015 Static void 4016 ehci_device_bulk_done(struct usbd_xfer *xfer) 4017 { 4018 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4019 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4020 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4021 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4022 4023 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4024 4025 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4026 4027 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4028 4029 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4030 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4031 4032 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4033 } 4034 4035 /************************/ 4036 4037 Static usbd_status 4038 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4039 { 4040 struct ehci_soft_islot *isp; 4041 int islot, lev; 4042 4043 /* Find a poll rate that is large enough. */ 4044 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4045 if (EHCI_ILEV_IVAL(lev) <= ival) 4046 break; 4047 4048 /* Pick an interrupt slot at the right level. */ 4049 /* XXX could do better than picking at random */ 4050 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4051 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4052 4053 sqh->islot = islot; 4054 isp = &sc->sc_islots[islot]; 4055 mutex_enter(&sc->sc_lock); 4056 ehci_add_qh(sc, sqh, isp->sqh); 4057 mutex_exit(&sc->sc_lock); 4058 4059 return USBD_NORMAL_COMPLETION; 4060 } 4061 4062 4063 Static int 4064 ehci_device_intr_init(struct usbd_xfer *xfer) 4065 { 4066 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4067 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4068 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4069 int endpt = ed->bEndpointAddress; 4070 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4071 int len = xfer->ux_bufsize; 4072 int err; 4073 4074 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4075 4076 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4077 xfer->ux_flags, 0); 4078 4079 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4080 KASSERT(len != 0); 4081 4082 exfer->ex_type = EX_INTR; 4083 exfer->ex_nsqtd = 0; 4084 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4085 &exfer->ex_sqtdstart); 4086 4087 return err; 4088 } 4089 4090 Static void 4091 ehci_device_intr_fini(struct usbd_xfer *xfer) 4092 { 4093 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4094 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4095 4096 KASSERT(ex->ex_type == EX_INTR); 4097 4098 ehci_free_sqtds(sc, ex); 4099 if (ex->ex_nsqtd) 4100 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4101 } 4102 4103 Static usbd_status 4104 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4105 { 4106 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4107 usbd_status err; 4108 4109 /* Insert last in queue. */ 4110 mutex_enter(&sc->sc_lock); 4111 err = usb_insert_transfer(xfer); 4112 mutex_exit(&sc->sc_lock); 4113 if (err) 4114 return err; 4115 4116 /* 4117 * Pipe isn't running (otherwise err would be USBD_INPROG), 4118 * so start it first. 4119 */ 4120 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4121 } 4122 4123 Static usbd_status 4124 ehci_device_intr_start(struct usbd_xfer *xfer) 4125 { 4126 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4127 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4128 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4129 ehci_soft_qtd_t *end; 4130 ehci_soft_qh_t *sqh; 4131 int len, isread, endpt; 4132 const bool polling = sc->sc_bus.ub_usepolling; 4133 4134 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4135 4136 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4137 xfer->ux_flags, 0); 4138 4139 if (sc->sc_dying) 4140 return USBD_IOERROR; 4141 4142 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4143 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4144 4145 len = xfer->ux_length; 4146 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4147 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4148 sqh = epipe->sqh; 4149 4150 KASSERT(exfer->ex_isdone); 4151 #ifdef DIAGNOSTIC 4152 exfer->ex_isdone = false; 4153 #endif 4154 4155 /* Take lock to protect nexttoggle */ 4156 if (!polling) 4157 mutex_enter(&sc->sc_lock); 4158 4159 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4160 4161 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4162 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4163 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4164 exfer->ex_sqtdend = end; 4165 4166 #ifdef EHCI_DEBUG 4167 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4168 ehci_dump_sqh(sqh); 4169 ehci_dump_sqtds(exfer->ex_sqtdstart); 4170 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4171 #endif 4172 4173 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4174 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4175 4176 /* also does usb_syncmem(sqh) */ 4177 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4178 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4179 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4180 ehci_timeout, xfer); 4181 } 4182 ehci_add_intr_list(sc, exfer); 4183 xfer->ux_status = USBD_IN_PROGRESS; 4184 if (!polling) 4185 mutex_exit(&sc->sc_lock); 4186 4187 #if 0 4188 #ifdef EHCI_DEBUG 4189 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4190 // delay(10000); 4191 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4192 ehci_dump_regs(sc); 4193 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4194 ehci_dump_sqh(sqh); 4195 ehci_dump_sqtds(exfer->ex_sqtdstart); 4196 #endif 4197 #endif 4198 4199 return USBD_IN_PROGRESS; 4200 } 4201 4202 Static void 4203 ehci_device_intr_abort(struct usbd_xfer *xfer) 4204 { 4205 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4206 4207 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4208 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4209 4210 /* 4211 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4212 * async doorbell. That's dependent on the async list, wheras 4213 * intr xfers are periodic, should not use this? 4214 */ 4215 ehci_abort_xfer(xfer, USBD_CANCELLED); 4216 } 4217 4218 Static void 4219 ehci_device_intr_close(struct usbd_pipe *pipe) 4220 { 4221 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4222 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4223 struct ehci_soft_islot *isp; 4224 4225 KASSERT(mutex_owned(&sc->sc_lock)); 4226 4227 isp = &sc->sc_islots[epipe->sqh->islot]; 4228 ehci_close_pipe(pipe, isp->sqh); 4229 } 4230 4231 Static void 4232 ehci_device_intr_done(struct usbd_xfer *xfer) 4233 { 4234 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4235 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4236 int isread, endpt; 4237 4238 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4239 4240 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4241 4242 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4243 4244 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4245 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4246 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4247 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4248 } 4249 4250 /************************/ 4251 Static int 4252 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4253 { 4254 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4255 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4256 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4257 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4258 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4259 int i, k, frames; 4260 u_int huba, dir; 4261 int err; 4262 4263 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4264 4265 start = NULL; 4266 sitd = NULL; 4267 4268 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4269 xfer->ux_flags, 0); 4270 4271 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4272 KASSERT(xfer->ux_nframes != 0); 4273 KASSERT(exfer->ex_isdone); 4274 4275 exfer->ex_type = EX_FS_ISOC; 4276 /* 4277 * Step 1: Allocate and initialize sitds. 4278 */ 4279 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4280 if (i > 16 || i == 0) { 4281 /* Spec page 271 says intervals > 16 are invalid */ 4282 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4283 4284 return EINVAL; 4285 } 4286 4287 frames = xfer->ux_nframes; 4288 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4289 sitd = ehci_alloc_sitd(sc); 4290 if (sitd == NULL) { 4291 err = ENOMEM; 4292 goto fail; 4293 } 4294 4295 if (prev) 4296 prev->xfer_next = sitd; 4297 else 4298 start = sitd; 4299 4300 huba = dev->ud_myhsport->up_parent->ud_addr; 4301 4302 #if 0 4303 if (sc->sc_flags & EHCIF_FREESCALE) { 4304 // Set hub address to 0 if embedded TT is used. 4305 if (huba == sc->sc_addr) 4306 huba = 0; 4307 } 4308 #endif 4309 4310 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4311 dir = UE_GET_DIR(k) ? 1 : 0; 4312 sitd->sitd.sitd_endp = 4313 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4314 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4315 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4316 EHCI_SITD_SET_HUBA(huba) | 4317 EHCI_SITD_SET_DIR(dir)); 4318 4319 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4320 } /* End of frame */ 4321 4322 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4323 4324 stop = sitd; 4325 stop->xfer_next = NULL; 4326 exfer->ex_sitdstart = start; 4327 exfer->ex_sitdend = stop; 4328 4329 return 0; 4330 4331 fail: 4332 mutex_enter(&sc->sc_lock); 4333 ehci_soft_sitd_t *next; 4334 for (sitd = start; sitd; sitd = next) { 4335 next = sitd->xfer_next; 4336 ehci_free_sitd_locked(sc, sitd); 4337 } 4338 mutex_exit(&sc->sc_lock); 4339 4340 return err; 4341 } 4342 4343 Static void 4344 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4345 { 4346 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4347 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4348 4349 KASSERT(ex->ex_type == EX_FS_ISOC); 4350 4351 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4352 } 4353 4354 Static usbd_status 4355 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4356 { 4357 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4358 usbd_status __diagused err; 4359 4360 mutex_enter(&sc->sc_lock); 4361 err = usb_insert_transfer(xfer); 4362 mutex_exit(&sc->sc_lock); 4363 4364 KASSERT(err == USBD_NORMAL_COMPLETION); 4365 4366 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4367 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4368 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4369 ehci_soft_sitd_t *sitd; 4370 usb_dma_t *dma_buf; 4371 int i, j, k, frames; 4372 int offs, total_length; 4373 int frindex; 4374 u_int dir; 4375 4376 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4377 4378 sitd = NULL; 4379 total_length = 0; 4380 4381 4382 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4383 xfer->ux_flags, 0); 4384 4385 if (sc->sc_dying) 4386 return USBD_IOERROR; 4387 4388 /* 4389 * To avoid complication, don't allow a request right now that'll span 4390 * the entire frame table. To within 4 frames, to allow some leeway 4391 * on either side of where the hc currently is. 4392 */ 4393 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4394 xfer->ux_nframes >= sc->sc_flsize - 4) { 4395 printf("ehci: isoc descriptor requested that spans the entire" 4396 "frametable, too many frames\n"); 4397 return USBD_INVAL; 4398 } 4399 4400 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4401 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4402 KASSERT(exfer->ex_isdone); 4403 #ifdef DIAGNOSTIC 4404 exfer->ex_isdone = false; 4405 #endif 4406 4407 /* 4408 * Step 1: Initialize sitds. 4409 */ 4410 4411 frames = xfer->ux_nframes; 4412 dma_buf = &xfer->ux_dmabuf; 4413 offs = 0; 4414 4415 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4416 i++, sitd = sitd->xfer_next) { 4417 KASSERT(sitd != NULL); 4418 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4419 4420 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4421 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4422 4423 /* Set page0 index and offset - TP and T-offset are set below */ 4424 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4425 4426 total_length += xfer->ux_frlengths[i]; 4427 offs += xfer->ux_frlengths[i]; 4428 4429 sitd->sitd.sitd_buffer[1] = 4430 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4431 4432 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4433 4434 #if 0 4435 if (sc->sc_flags & EHCIF_FREESCALE) { 4436 // Set hub address to 0 if embedded TT is used. 4437 if (huba == sc->sc_addr) 4438 huba = 0; 4439 } 4440 #endif 4441 4442 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4443 dir = UE_GET_DIR(k) ? 1 : 0; 4444 KASSERT(sitd->sitd.sitd_endp == htole32( 4445 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4446 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4447 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4448 EHCI_SITD_SET_HUBA(huba) | 4449 EHCI_SITD_SET_DIR(dir))); 4450 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4451 4452 uint8_t sa = 0; 4453 uint8_t sb = 0; 4454 u_int temp, tlen; 4455 4456 if (dir == 0) { /* OUT */ 4457 temp = 0; 4458 tlen = xfer->ux_frlengths[i]; 4459 if (tlen <= 188) { 4460 temp |= 1; /* T-count = 1, TP = ALL */ 4461 tlen = 1; 4462 } else { 4463 tlen += 187; 4464 tlen /= 188; 4465 temp |= tlen; /* T-count = [1..6] */ 4466 temp |= 8; /* TP = Begin */ 4467 } 4468 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4469 4470 tlen += sa; 4471 4472 if (tlen >= 8) { 4473 sb = 0; 4474 } else { 4475 sb = (1 << tlen); 4476 } 4477 4478 sa = (1 << sa); 4479 sa = (sb - sa) & 0x3F; 4480 sb = 0; 4481 } else { 4482 sb = (-(4 << sa)) & 0xFE; 4483 sa = (1 << sa) & 0x3F; 4484 sa = 0x01; 4485 sb = 0xfc; 4486 } 4487 4488 sitd->sitd.sitd_sched = htole32( 4489 EHCI_SITD_SET_SMASK(sa) | 4490 EHCI_SITD_SET_CMASK(sb) 4491 ); 4492 4493 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4494 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4495 } /* End of frame */ 4496 4497 sitd = exfer->ex_sitdend; 4498 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4499 4500 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4501 sizeof(sitd->sitd.sitd_trans), 4502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4503 4504 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4505 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4506 4507 /* 4508 * Part 2: Transfer descriptors have now been set up, now they must 4509 * be scheduled into the periodic frame list. Erk. Not wanting to 4510 * complicate matters, transfer is denied if the transfer spans 4511 * more than the period frame list. 4512 */ 4513 4514 mutex_enter(&sc->sc_lock); 4515 4516 /* Start inserting frames */ 4517 if (epipe->isoc.cur_xfers > 0) { 4518 frindex = epipe->isoc.next_frame; 4519 } else { 4520 frindex = EOREAD4(sc, EHCI_FRINDEX); 4521 frindex = frindex >> 3; /* Erase microframe index */ 4522 frindex += 2; 4523 } 4524 4525 if (frindex >= sc->sc_flsize) 4526 frindex &= (sc->sc_flsize - 1); 4527 4528 /* Whats the frame interval? */ 4529 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4530 4531 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4532 j++, sitd = sitd->xfer_next) { 4533 KASSERT(sitd); 4534 4535 usb_syncmem(&sc->sc_fldma, 4536 sizeof(ehci_link_t) * frindex, 4537 sizeof(ehci_link_t), 4538 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4539 4540 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4541 if (sitd->sitd.sitd_next == 0) 4542 /* 4543 * FIXME: frindex table gets initialized to NULL 4544 * or EHCI_NULL? 4545 */ 4546 sitd->sitd.sitd_next = EHCI_NULL; 4547 4548 usb_syncmem(&sitd->dma, 4549 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4550 sizeof(ehci_sitd_t), 4551 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4552 4553 sc->sc_flist[frindex] = 4554 htole32(EHCI_LINK_SITD | sitd->physaddr); 4555 4556 usb_syncmem(&sc->sc_fldma, 4557 sizeof(ehci_link_t) * frindex, 4558 sizeof(ehci_link_t), 4559 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4560 4561 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4562 sc->sc_softsitds[frindex] = sitd; 4563 if (sitd->frame_list.next != NULL) 4564 sitd->frame_list.next->frame_list.prev = sitd; 4565 sitd->slot = frindex; 4566 sitd->frame_list.prev = NULL; 4567 4568 frindex += i; 4569 if (frindex >= sc->sc_flsize) 4570 frindex -= sc->sc_flsize; 4571 } 4572 4573 epipe->isoc.cur_xfers++; 4574 epipe->isoc.next_frame = frindex; 4575 4576 ehci_add_intr_list(sc, exfer); 4577 xfer->ux_status = USBD_IN_PROGRESS; 4578 mutex_exit(&sc->sc_lock); 4579 4580 return USBD_IN_PROGRESS; 4581 } 4582 4583 Static void 4584 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4585 { 4586 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4587 4588 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4589 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4590 } 4591 4592 Static void 4593 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4594 { 4595 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4596 4597 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4598 } 4599 4600 Static void 4601 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4602 { 4603 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4604 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4605 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4606 4607 KASSERT(mutex_owned(&sc->sc_lock)); 4608 4609 epipe->isoc.cur_xfers--; 4610 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4611 4612 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4613 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4614 } 4615 4616 4617 /************************/ 4618 4619 4620 Static int 4621 ehci_device_isoc_init(struct usbd_xfer *xfer) 4622 { 4623 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4624 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4625 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4626 ehci_soft_itd_t *itd, *prev, *start, *stop; 4627 int i, j, k; 4628 int frames, ufrperframe; 4629 int err; 4630 4631 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4632 4633 start = NULL; 4634 prev = NULL; 4635 itd = NULL; 4636 4637 KASSERT(xfer->ux_nframes != 0); 4638 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4639 KASSERT(exfer->ex_isdone); 4640 4641 exfer->ex_type = EX_ISOC; 4642 4643 /* 4644 * Step 1: Allocate and initialize itds, how many do we need? 4645 * One per transfer if interval >= 8 microframes, less if we use 4646 * multiple microframes per frame. 4647 */ 4648 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4649 if (i > 16 || i == 0) { 4650 /* Spec page 271 says intervals > 16 are invalid */ 4651 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4652 return USBD_INVAL; 4653 } 4654 4655 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4656 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4657 4658 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4659 itd = ehci_alloc_itd(sc); 4660 if (itd == NULL) { 4661 err = ENOMEM; 4662 goto fail; 4663 } 4664 4665 if (prev != NULL) { 4666 /* Maybe not as it's updated by the scheduling? */ 4667 prev->itd.itd_next = 4668 htole32(itd->physaddr | EHCI_LINK_ITD); 4669 4670 prev->xfer_next = itd; 4671 } else { 4672 start = itd; 4673 } 4674 4675 /* 4676 * Other special values 4677 */ 4678 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4679 itd->itd.itd_bufr[0] = htole32( 4680 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4681 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4682 4683 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4684 ? 1 : 0; 4685 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4686 itd->itd.itd_bufr[1] |= htole32( 4687 EHCI_ITD_SET_DIR(k) | 4688 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4689 4690 /* FIXME: handle invalid trans - should be done in openpipe */ 4691 itd->itd.itd_bufr[2] |= 4692 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4693 } /* End of frame */ 4694 4695 stop = itd; 4696 stop->xfer_next = NULL; 4697 4698 exfer->ex_itdstart = start; 4699 exfer->ex_itdend = stop; 4700 4701 return 0; 4702 fail: 4703 mutex_enter(&sc->sc_lock); 4704 ehci_soft_itd_t *next; 4705 for (itd = start; itd; itd = next) { 4706 next = itd->xfer_next; 4707 ehci_free_itd_locked(sc, itd); 4708 } 4709 mutex_exit(&sc->sc_lock); 4710 4711 return err; 4712 4713 } 4714 4715 Static void 4716 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4717 { 4718 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4719 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4720 4721 KASSERT(ex->ex_type == EX_ISOC); 4722 4723 ehci_free_itd_chain(sc, ex->ex_itdstart); 4724 } 4725 4726 Static usbd_status 4727 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4728 { 4729 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4730 usbd_status __diagused err; 4731 4732 mutex_enter(&sc->sc_lock); 4733 err = usb_insert_transfer(xfer); 4734 mutex_exit(&sc->sc_lock); 4735 4736 KASSERT(err == USBD_NORMAL_COMPLETION); 4737 4738 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4739 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4740 ehci_soft_itd_t *itd, *prev; 4741 usb_dma_t *dma_buf; 4742 int i, j; 4743 int frames, uframes, ufrperframe; 4744 int trans_count, offs, total_length; 4745 int frindex; 4746 4747 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4748 4749 prev = NULL; 4750 itd = NULL; 4751 trans_count = 0; 4752 total_length = 0; 4753 4754 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4755 4756 if (sc->sc_dying) 4757 return USBD_IOERROR; 4758 4759 /* 4760 * To avoid complication, don't allow a request right now that'll span 4761 * the entire frame table. To within 4 frames, to allow some leeway 4762 * on either side of where the hc currently is. 4763 */ 4764 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4765 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4766 DPRINTF( 4767 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4768 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4769 return USBD_INVAL; 4770 } 4771 4772 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4773 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4774 KASSERT(exfer->ex_isdone); 4775 #ifdef DIAGNOSTIC 4776 exfer->ex_isdone = false; 4777 #endif 4778 4779 /* 4780 * Step 1: Re-Initialize itds 4781 */ 4782 4783 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4784 if (i > 16 || i == 0) { 4785 /* Spec page 271 says intervals > 16 are invalid */ 4786 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4787 return USBD_INVAL; 4788 } 4789 4790 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4791 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4792 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4793 4794 if (frames == 0) { 4795 DPRINTF("frames == 0", 0, 0, 0, 0); 4796 return USBD_INVAL; 4797 } 4798 4799 dma_buf = &xfer->ux_dmabuf; 4800 offs = 0; 4801 4802 itd = exfer->ex_itdstart; 4803 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4804 int froffs = offs; 4805 4806 if (prev != NULL) { 4807 prev->itd.itd_next = 4808 htole32(itd->physaddr | EHCI_LINK_ITD); 4809 usb_syncmem(&prev->dma, 4810 prev->offs + offsetof(ehci_itd_t, itd_next), 4811 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4812 prev->xfer_next = itd; 4813 } 4814 4815 /* 4816 * Step 1.5, initialize uframes 4817 */ 4818 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4819 /* Calculate which page in the list this starts in */ 4820 int addr = DMAADDR(dma_buf, froffs); 4821 addr = EHCI_PAGE_OFFSET(addr); 4822 addr += (offs - froffs); 4823 addr = EHCI_PAGE(addr); 4824 addr /= EHCI_PAGE_SIZE; 4825 4826 /* 4827 * This gets the initial offset into the first page, 4828 * looks how far further along the current uframe 4829 * offset is. Works out how many pages that is. 4830 */ 4831 4832 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4833 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4834 EHCI_ITD_SET_PG(addr) | 4835 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4836 4837 total_length += xfer->ux_frlengths[trans_count]; 4838 offs += xfer->ux_frlengths[trans_count]; 4839 trans_count++; 4840 4841 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4842 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4843 break; 4844 } 4845 } 4846 4847 /* 4848 * Step 1.75, set buffer pointers. To simplify matters, all 4849 * pointers are filled out for the next 7 hardware pages in 4850 * the dma block, so no need to worry what pages to cover 4851 * and what to not. 4852 */ 4853 4854 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4855 /* 4856 * Don't try to lookup a page that's past the end 4857 * of buffer 4858 */ 4859 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4860 if (page_offs >= dma_buf->udma_block->size) 4861 break; 4862 4863 uint64_t page = DMAADDR(dma_buf, page_offs); 4864 page = EHCI_PAGE(page); 4865 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4866 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4867 } 4868 /* 4869 * Other special values 4870 */ 4871 4872 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4873 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4874 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4875 4876 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4877 ? 1 : 0; 4878 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4879 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4880 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4881 4882 /* FIXME: handle invalid trans */ 4883 itd->itd.itd_bufr[2] |= 4884 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4885 4886 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4887 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4888 4889 prev = itd; 4890 } /* End of frame */ 4891 4892 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4893 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4894 4895 /* 4896 * Part 2: Transfer descriptors have now been set up, now they must 4897 * be scheduled into the period frame list. Erk. Not wanting to 4898 * complicate matters, transfer is denied if the transfer spans 4899 * more than the period frame list. 4900 */ 4901 4902 mutex_enter(&sc->sc_lock); 4903 4904 /* Start inserting frames */ 4905 if (epipe->isoc.cur_xfers > 0) { 4906 frindex = epipe->isoc.next_frame; 4907 } else { 4908 frindex = EOREAD4(sc, EHCI_FRINDEX); 4909 frindex = frindex >> 3; /* Erase microframe index */ 4910 frindex += 2; 4911 } 4912 4913 if (frindex >= sc->sc_flsize) 4914 frindex &= (sc->sc_flsize - 1); 4915 4916 /* What's the frame interval? */ 4917 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4918 if (i / USB_UFRAMES_PER_FRAME == 0) 4919 i = 1; 4920 else 4921 i /= USB_UFRAMES_PER_FRAME; 4922 4923 itd = exfer->ex_itdstart; 4924 for (j = 0; j < frames; j++) { 4925 KASSERTMSG(itd != NULL, "frame %d\n", j); 4926 4927 usb_syncmem(&sc->sc_fldma, 4928 sizeof(ehci_link_t) * frindex, 4929 sizeof(ehci_link_t), 4930 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4931 4932 itd->itd.itd_next = sc->sc_flist[frindex]; 4933 if (itd->itd.itd_next == 0) 4934 /* 4935 * FIXME: frindex table gets initialized to NULL 4936 * or EHCI_NULL? 4937 */ 4938 itd->itd.itd_next = EHCI_NULL; 4939 4940 usb_syncmem(&itd->dma, 4941 itd->offs + offsetof(ehci_itd_t, itd_next), 4942 sizeof(itd->itd.itd_next), 4943 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4944 4945 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4946 4947 usb_syncmem(&sc->sc_fldma, 4948 sizeof(ehci_link_t) * frindex, 4949 sizeof(ehci_link_t), 4950 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4951 4952 itd->frame_list.next = sc->sc_softitds[frindex]; 4953 sc->sc_softitds[frindex] = itd; 4954 if (itd->frame_list.next != NULL) 4955 itd->frame_list.next->frame_list.prev = itd; 4956 itd->slot = frindex; 4957 itd->frame_list.prev = NULL; 4958 4959 frindex += i; 4960 if (frindex >= sc->sc_flsize) 4961 frindex -= sc->sc_flsize; 4962 4963 itd = itd->xfer_next; 4964 } 4965 4966 epipe->isoc.cur_xfers++; 4967 epipe->isoc.next_frame = frindex; 4968 4969 ehci_add_intr_list(sc, exfer); 4970 xfer->ux_status = USBD_IN_PROGRESS; 4971 mutex_exit(&sc->sc_lock); 4972 4973 return USBD_IN_PROGRESS; 4974 } 4975 4976 Static void 4977 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4978 { 4979 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4980 4981 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4982 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4983 } 4984 4985 Static void 4986 ehci_device_isoc_close(struct usbd_pipe *pipe) 4987 { 4988 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4989 4990 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4991 } 4992 4993 Static void 4994 ehci_device_isoc_done(struct usbd_xfer *xfer) 4995 { 4996 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4997 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4998 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4999 5000 KASSERT(mutex_owned(&sc->sc_lock)); 5001 5002 epipe->isoc.cur_xfers--; 5003 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5004 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5005 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5006 } 5007
Indexes created Wed Oct 01 19:09:53 GMT 2025