ehci.c revision 1.259.2.2
1 /* $NetBSD: ehci.c,v 1.259.2.2 2020/04/08 14:08:13 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.259.2.2 2020/04/08 14:08:13 martin Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 #include <sys/reboot.h> 79 80 #include <machine/endian.h> 81 82 #include <dev/usb/usb.h> 83 #include <dev/usb/usbdi.h> 84 #include <dev/usb/usbdivar.h> 85 #include <dev/usb/usbhist.h> 86 #include <dev/usb/usb_mem.h> 87 #include <dev/usb/usb_quirks.h> 88 89 #include <dev/usb/ehcireg.h> 90 #include <dev/usb/ehcivar.h> 91 #include <dev/usb/usbroothub.h> 92 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 static int ehcidebug = 0; 99 100 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 101 { 102 int err; 103 const struct sysctlnode *rnode; 104 const struct sysctlnode *cnode; 105 106 err = sysctl_createv(clog, 0, NULL, &rnode, 107 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 108 SYSCTL_DESCR("ehci global controls"), 109 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 110 111 if (err) 112 goto fail; 113 114 /* control debugging printfs */ 115 err = sysctl_createv(clog, 0, &rnode, &cnode, 116 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 117 "debug", SYSCTL_DESCR("Enable debugging output"), 118 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 119 if (err) 120 goto fail; 121 122 return; 123 fail: 124 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 125 } 126 127 #endif /* EHCI_DEBUG */ 128 #endif /* USB_DEBUG */ 129 130 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 131 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 132 #define EHCIHIST_FUNC() USBHIST_FUNC() 133 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 134 135 struct ehci_pipe { 136 struct usbd_pipe pipe; 137 int nexttoggle; 138 139 ehci_soft_qh_t *sqh; 140 union { 141 /* Control pipe */ 142 struct { 143 usb_dma_t reqdma; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 u_int length; 148 } intr; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 }; 155 }; 156 157 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 158 159 Static usbd_status ehci_open(struct usbd_pipe *); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_intrlist_timeout(void *); 171 Static void ehci_doorbell(void *); 172 Static void ehci_pcd(void *); 173 174 Static struct usbd_xfer * 175 ehci_allocx(struct usbd_bus *, unsigned int); 176 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 177 178 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 179 Static bool ehci_dying(struct usbd_bus *); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abortx(struct usbd_xfer *); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_abortx = ehci_abortx, 323 .ubm_dying = ehci_dying, 324 .ubm_getlock = ehci_get_lock, 325 .ubm_rhctrl = ehci_roothub_ctrl, 326 }; 327 328 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 329 .upm_transfer = ehci_root_intr_transfer, 330 .upm_start = ehci_root_intr_start, 331 .upm_abort = ehci_root_intr_abort, 332 .upm_close = ehci_root_intr_close, 333 .upm_cleartoggle = ehci_noop, 334 .upm_done = ehci_root_intr_done, 335 }; 336 337 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 338 .upm_init = ehci_device_ctrl_init, 339 .upm_fini = ehci_device_ctrl_fini, 340 .upm_transfer = ehci_device_ctrl_transfer, 341 .upm_start = ehci_device_ctrl_start, 342 .upm_abort = ehci_device_ctrl_abort, 343 .upm_close = ehci_device_ctrl_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_ctrl_done, 346 }; 347 348 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 349 .upm_init = ehci_device_intr_init, 350 .upm_fini = ehci_device_intr_fini, 351 .upm_transfer = ehci_device_intr_transfer, 352 .upm_start = ehci_device_intr_start, 353 .upm_abort = ehci_device_intr_abort, 354 .upm_close = ehci_device_intr_close, 355 .upm_cleartoggle = ehci_device_clear_toggle, 356 .upm_done = ehci_device_intr_done, 357 }; 358 359 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 360 .upm_init = ehci_device_bulk_init, 361 .upm_fini = ehci_device_bulk_fini, 362 .upm_transfer = ehci_device_bulk_transfer, 363 .upm_start = ehci_device_bulk_start, 364 .upm_abort = ehci_device_bulk_abort, 365 .upm_close = ehci_device_bulk_close, 366 .upm_cleartoggle = ehci_device_clear_toggle, 367 .upm_done = ehci_device_bulk_done, 368 }; 369 370 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 371 .upm_init = ehci_device_isoc_init, 372 .upm_fini = ehci_device_isoc_fini, 373 .upm_transfer = ehci_device_isoc_transfer, 374 .upm_abort = ehci_device_isoc_abort, 375 .upm_close = ehci_device_isoc_close, 376 .upm_cleartoggle = ehci_noop, 377 .upm_done = ehci_device_isoc_done, 378 }; 379 380 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 381 .upm_init = ehci_device_fs_isoc_init, 382 .upm_fini = ehci_device_fs_isoc_fini, 383 .upm_transfer = ehci_device_fs_isoc_transfer, 384 .upm_abort = ehci_device_fs_isoc_abort, 385 .upm_close = ehci_device_fs_isoc_close, 386 .upm_cleartoggle = ehci_noop, 387 .upm_done = ehci_device_fs_isoc_done, 388 }; 389 390 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 391 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 392 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 393 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 394 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 395 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 396 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 397 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 398 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 399 }; 400 401 int 402 ehci_init(ehci_softc_t *sc) 403 { 404 uint32_t vers, sparams, cparams, hcr; 405 u_int i; 406 usbd_status err; 407 ehci_soft_qh_t *sqh; 408 u_int ncomp; 409 410 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 411 #ifdef EHCI_DEBUG 412 theehci = sc; 413 #endif 414 415 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 416 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 417 cv_init(&sc->sc_doorbell, "ehcidb"); 418 419 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 420 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 421 422 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 423 ehci_doorbell, sc); 424 KASSERT(sc->sc_doorbell_si != NULL); 425 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 426 ehci_pcd, sc); 427 KASSERT(sc->sc_pcd_si != NULL); 428 429 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 430 431 vers = EREAD2(sc, EHCI_HCIVERSION); 432 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 433 vers >> 8, vers & 0xff); 434 435 sparams = EREAD4(sc, EHCI_HCSPARAMS); 436 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 437 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 438 ncomp = EHCI_HCS_N_CC(sparams); 439 if (ncomp != sc->sc_ncomp) { 440 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 441 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 442 #if NOHCI == 0 || NUHCI == 0 443 aprint_error("%s: ohci or uhci probably not configured\n", 444 device_xname(sc->sc_dev)); 445 #endif 446 if (ncomp < sc->sc_ncomp) 447 sc->sc_ncomp = ncomp; 448 } 449 if (sc->sc_ncomp > 0) { 450 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 451 aprint_normal_dev(sc->sc_dev, 452 "%d companion controller%s, %d port%s%s", 453 sc->sc_ncomp, 454 sc->sc_ncomp!=1 ? "s" : "", 455 EHCI_HCS_N_PCC(sparams), 456 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 457 sc->sc_ncomp!=1 ? " each" : ""); 458 if (sc->sc_comps[0]) { 459 aprint_normal(":"); 460 for (i = 0; i < sc->sc_ncomp; i++) 461 aprint_normal(" %s", 462 device_xname(sc->sc_comps[i])); 463 } 464 aprint_normal("\n"); 465 466 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 467 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 468 cv_init(&sc->sc_compcv, "ehciccv"); 469 sc->sc_comp_state = CO_EARLY; 470 } 471 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 472 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 473 474 cparams = EREAD4(sc, EHCI_HCCPARAMS); 475 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 476 477 if (EHCI_HCC_64BIT(cparams)) { 478 /* MUST clear segment register if 64 bit capable. */ 479 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 480 } 481 482 if (cparams & EHCI_HCC_IST_FULLFRAME) { 483 sc->sc_istthreshold = 0; 484 } else { 485 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 486 } 487 488 sc->sc_bus.ub_revision = USBREV_2_0; 489 sc->sc_bus.ub_usedma = true; 490 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 491 492 /* Reset the controller */ 493 DPRINTF("resetting", 0, 0, 0, 0); 494 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 495 usb_delay_ms(&sc->sc_bus, 1); 496 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 497 for (i = 0; i < 100; i++) { 498 usb_delay_ms(&sc->sc_bus, 1); 499 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 500 if (!hcr) 501 break; 502 } 503 if (hcr) { 504 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 505 return EIO; 506 } 507 if (sc->sc_vendor_init) 508 sc->sc_vendor_init(sc); 509 510 /* XXX need proper intr scheduling */ 511 sc->sc_rand = 96; 512 513 /* frame list size at default, read back what we got and use that */ 514 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 515 case 0: sc->sc_flsize = 1024; break; 516 case 1: sc->sc_flsize = 512; break; 517 case 2: sc->sc_flsize = 256; break; 518 case 3: return EIO; 519 } 520 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 521 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 522 if (err) 523 return err; 524 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 525 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 526 527 for (i = 0; i < sc->sc_flsize; i++) { 528 sc->sc_flist[i] = EHCI_NULL; 529 } 530 531 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 532 533 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 534 KM_SLEEP); 535 if (sc->sc_softitds == NULL) 536 return ENOMEM; 537 LIST_INIT(&sc->sc_freeitds); 538 LIST_INIT(&sc->sc_freesitds); 539 TAILQ_INIT(&sc->sc_intrhead); 540 541 /* Set up the bus struct. */ 542 sc->sc_bus.ub_methods = &ehci_bus_methods; 543 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 544 545 sc->sc_eintrs = EHCI_NORMAL_INTRS; 546 547 /* 548 * Allocate the interrupt dummy QHs. These are arranged to give poll 549 * intervals that are powers of 2 times 1ms. 550 */ 551 for (i = 0; i < EHCI_INTRQHS; i++) { 552 sqh = ehci_alloc_sqh(sc); 553 if (sqh == NULL) { 554 err = ENOMEM; 555 goto bad1; 556 } 557 sc->sc_islots[i].sqh = sqh; 558 } 559 for (i = 0; i < EHCI_INTRQHS; i++) { 560 sqh = sc->sc_islots[i].sqh; 561 if (i == 0) { 562 /* The last (1ms) QH terminates. */ 563 sqh->qh.qh_link = EHCI_NULL; 564 sqh->next = NULL; 565 } else { 566 /* Otherwise the next QH has half the poll interval */ 567 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 568 sqh->qh.qh_link = htole32(sqh->next->physaddr | 569 EHCI_LINK_QH); 570 } 571 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 572 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 573 sqh->qh.qh_curqtd = EHCI_NULL; 574 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 575 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 576 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 577 sqh->sqtd = NULL; 578 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 579 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 580 } 581 /* Point the frame list at the last level (128ms). */ 582 for (i = 0; i < sc->sc_flsize; i++) { 583 int j; 584 585 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 586 revbits[i & (EHCI_MAX_POLLRATE-1)]; 587 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 588 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 589 i)].sqh->physaddr); 590 } 591 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 592 BUS_DMASYNC_PREWRITE); 593 594 /* Allocate dummy QH that starts the async list. */ 595 sqh = ehci_alloc_sqh(sc); 596 if (sqh == NULL) { 597 err = ENOMEM; 598 goto bad1; 599 } 600 /* Fill the QH */ 601 sqh->qh.qh_endp = 602 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 603 sqh->qh.qh_link = 604 htole32(sqh->physaddr | EHCI_LINK_QH); 605 sqh->qh.qh_curqtd = EHCI_NULL; 606 sqh->next = NULL; 607 /* Fill the overlay qTD */ 608 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 609 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 610 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 611 sqh->sqtd = NULL; 612 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 613 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 614 #ifdef EHCI_DEBUG 615 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 616 ehci_dump_sqh(sqh); 617 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 618 #endif 619 620 /* Point to async list */ 621 sc->sc_async_head = sqh; 622 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 623 624 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 625 626 /* Turn on controller */ 627 EOWRITE4(sc, EHCI_USBCMD, 628 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 629 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 630 EHCI_CMD_ASE | 631 EHCI_CMD_PSE | 632 EHCI_CMD_RS); 633 634 /* Take over port ownership */ 635 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 636 637 for (i = 0; i < 100; i++) { 638 usb_delay_ms(&sc->sc_bus, 1); 639 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 640 if (!hcr) 641 break; 642 } 643 if (hcr) { 644 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 645 return EIO; 646 } 647 648 /* Enable interrupts */ 649 DPRINTF("enabling interrupts", 0, 0, 0, 0); 650 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 651 652 return 0; 653 654 #if 0 655 bad2: 656 ehci_free_sqh(sc, sc->sc_async_head); 657 #endif 658 bad1: 659 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 660 return err; 661 } 662 663 int 664 ehci_intr(void *v) 665 { 666 ehci_softc_t *sc = v; 667 int ret = 0; 668 669 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 670 671 if (sc == NULL) 672 return 0; 673 674 mutex_spin_enter(&sc->sc_intr_lock); 675 676 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 677 goto done; 678 679 /* If we get an interrupt while polling, then just ignore it. */ 680 if (sc->sc_bus.ub_usepolling) { 681 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 682 683 if (intrs) 684 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 685 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 686 goto done; 687 } 688 689 ret = ehci_intr1(sc); 690 691 done: 692 mutex_spin_exit(&sc->sc_intr_lock); 693 return ret; 694 } 695 696 Static int 697 ehci_intr1(ehci_softc_t *sc) 698 { 699 uint32_t intrs, eintrs; 700 701 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 702 703 /* In case the interrupt occurs before initialization has completed. */ 704 if (sc == NULL) { 705 #ifdef DIAGNOSTIC 706 printf("ehci_intr1: sc == NULL\n"); 707 #endif 708 return 0; 709 } 710 711 KASSERT(mutex_owned(&sc->sc_intr_lock)); 712 713 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 714 if (!intrs) 715 return 0; 716 717 eintrs = intrs & sc->sc_eintrs; 718 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 719 EOREAD4(sc, EHCI_USBSTS), eintrs); 720 if (!eintrs) 721 return 0; 722 723 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 724 if (eintrs & EHCI_STS_IAA) { 725 DPRINTF("door bell", 0, 0, 0, 0); 726 kpreempt_disable(); 727 KASSERT(sc->sc_doorbell_si != NULL); 728 softint_schedule(sc->sc_doorbell_si); 729 kpreempt_enable(); 730 eintrs &= ~EHCI_STS_IAA; 731 } 732 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 733 DPRINTF("INT=%jd ERRINT=%jd", 734 eintrs & EHCI_STS_INT ? 1 : 0, 735 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 736 usb_schedsoftintr(&sc->sc_bus); 737 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 738 } 739 if (eintrs & EHCI_STS_HSE) { 740 printf("%s: unrecoverable error, controller halted\n", 741 device_xname(sc->sc_dev)); 742 /* XXX what else */ 743 } 744 if (eintrs & EHCI_STS_PCD) { 745 kpreempt_disable(); 746 KASSERT(sc->sc_pcd_si != NULL); 747 softint_schedule(sc->sc_pcd_si); 748 kpreempt_enable(); 749 eintrs &= ~EHCI_STS_PCD; 750 } 751 752 if (eintrs != 0) { 753 /* Block unprocessed interrupts. */ 754 sc->sc_eintrs &= ~eintrs; 755 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 756 printf("%s: blocking intrs %#x\n", 757 device_xname(sc->sc_dev), eintrs); 758 } 759 760 return 1; 761 } 762 763 Static void 764 ehci_doorbell(void *addr) 765 { 766 ehci_softc_t *sc = addr; 767 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 768 769 mutex_enter(&sc->sc_lock); 770 cv_broadcast(&sc->sc_doorbell); 771 mutex_exit(&sc->sc_lock); 772 } 773 774 Static void 775 ehci_pcd(void *addr) 776 { 777 ehci_softc_t *sc = addr; 778 struct usbd_xfer *xfer; 779 u_char *p; 780 int i, m; 781 782 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 783 784 mutex_enter(&sc->sc_lock); 785 xfer = sc->sc_intrxfer; 786 787 if (xfer == NULL) { 788 /* Just ignore the change. */ 789 goto done; 790 } 791 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 792 793 p = xfer->ux_buf; 794 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 795 memset(p, 0, xfer->ux_length); 796 for (i = 1; i <= m; i++) { 797 /* Pick out CHANGE bits from the status reg. */ 798 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 799 p[i/8] |= 1 << (i%8); 800 if (i % 8 == 7) 801 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 802 } 803 xfer->ux_actlen = xfer->ux_length; 804 xfer->ux_status = USBD_NORMAL_COMPLETION; 805 806 usb_transfer_complete(xfer); 807 808 done: 809 mutex_exit(&sc->sc_lock); 810 } 811 812 Static void 813 ehci_softintr(void *v) 814 { 815 struct usbd_bus *bus = v; 816 ehci_softc_t *sc = EHCI_BUS2SC(bus); 817 struct ehci_xfer *ex, *nextex; 818 819 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 820 821 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 822 823 ex_completeq_t cq; 824 TAILQ_INIT(&cq); 825 826 /* 827 * The only explanation I can think of for why EHCI is as brain dead 828 * as UHCI interrupt-wise is that Intel was involved in both. 829 * An interrupt just tells us that something is done, we have no 830 * clue what, so we need to scan through all active transfers. :-( 831 */ 832 833 /* 834 * ehci_idone will remove transfer from sc->sc_intrhead if it's 835 * complete and add to our cq list 836 * 837 */ 838 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 839 switch (ex->ex_type) { 840 case EX_CTRL: 841 case EX_BULK: 842 case EX_INTR: 843 ehci_check_qh_intr(sc, ex, &cq); 844 break; 845 case EX_ISOC: 846 ehci_check_itd_intr(sc, ex, &cq); 847 break; 848 case EX_FS_ISOC: 849 ehci_check_sitd_intr(sc, ex, &cq); 850 break; 851 default: 852 KASSERT(false); 853 } 854 855 } 856 857 /* 858 * We abuse ex_next for the interrupt and complete lists and 859 * interrupt transfers will get re-added here so use 860 * the _SAFE version of TAILQ_FOREACH. 861 */ 862 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 863 usb_transfer_complete(&ex->ex_xfer); 864 } 865 866 /* Schedule a callout to catch any dropped transactions. */ 867 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 868 !TAILQ_EMPTY(&sc->sc_intrhead)) 869 callout_reset(&sc->sc_tmo_intrlist, 870 hz, ehci_intrlist_timeout, sc); 871 } 872 873 Static void 874 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 875 { 876 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 877 uint32_t status; 878 879 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 880 881 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 882 883 if (ex->ex_type == EX_CTRL) { 884 fsqtd = ex->ex_setup; 885 lsqtd = ex->ex_status; 886 } else { 887 fsqtd = ex->ex_sqtdstart; 888 lsqtd = ex->ex_sqtdend; 889 } 890 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 891 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 892 893 /* 894 * If the last TD is still active we need to check whether there 895 * is an error somewhere in the middle, or whether there was a 896 * short packet (SPD and not ACTIVE). 897 */ 898 usb_syncmem(&lsqtd->dma, 899 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 900 sizeof(lsqtd->qtd.qtd_status), 901 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 902 status = le32toh(lsqtd->qtd.qtd_status); 903 usb_syncmem(&lsqtd->dma, 904 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 905 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 906 if (status & EHCI_QTD_ACTIVE) { 907 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 908 909 /* last qTD has already been checked */ 910 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 911 usb_syncmem(&sqtd->dma, 912 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 913 sizeof(sqtd->qtd.qtd_status), 914 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 915 status = le32toh(sqtd->qtd.qtd_status); 916 usb_syncmem(&sqtd->dma, 917 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 918 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 919 /* If there's an active QTD the xfer isn't done. */ 920 if (status & EHCI_QTD_ACTIVE) 921 break; 922 /* Any kind of error makes the xfer done. */ 923 if (status & EHCI_QTD_HALTED) 924 goto done; 925 /* Handle short packets */ 926 if (EHCI_QTD_GET_BYTES(status) != 0) { 927 /* 928 * If we get here for a control transfer then 929 * we need to let the hardware complete the 930 * status phase. That is, we're not done 931 * quite yet. 932 * 933 * Otherwise, we're done. 934 */ 935 if (ex->ex_type == EX_CTRL) { 936 break; 937 } 938 goto done; 939 } 940 } 941 DPRINTFN(10, "ex=%#jx std=%#jx still active", 942 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 943 #ifdef EHCI_DEBUG 944 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 945 ehci_dump_sqtds(ex->ex_sqtdstart); 946 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 947 #endif 948 return; 949 } 950 done: 951 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 952 ehci_idone(ex, cq); 953 } 954 955 Static void 956 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 957 { 958 ehci_soft_itd_t *itd; 959 int i; 960 961 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 962 963 KASSERT(mutex_owned(&sc->sc_lock)); 964 965 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 966 return; 967 968 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 969 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 970 971 itd = ex->ex_itdend; 972 973 /* 974 * check no active transfers in last itd, meaning we're finished 975 */ 976 977 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 978 sizeof(itd->itd.itd_ctl), 979 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 980 981 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 982 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 983 break; 984 } 985 986 if (i == EHCI_ITD_NUFRAMES) { 987 goto done; /* All 8 descriptors inactive, it's done */ 988 } 989 990 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 991 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 992 993 DPRINTFN(10, "ex %#jx itd %#jx still active", 994 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 995 return; 996 done: 997 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 998 ehci_idone(ex, cq); 999 } 1000 1001 void 1002 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1003 { 1004 ehci_soft_sitd_t *sitd; 1005 1006 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1007 1008 KASSERT(mutex_owned(&sc->sc_lock)); 1009 1010 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1011 return; 1012 1013 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1014 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1015 1016 sitd = ex->ex_sitdend; 1017 1018 /* 1019 * check no active transfers in last sitd, meaning we're finished 1020 */ 1021 1022 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1023 sizeof(sitd->sitd.sitd_trans), 1024 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1025 1026 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1027 1028 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1029 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1030 1031 if (active) 1032 return; 1033 1034 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1035 ehci_idone(ex, cq); 1036 } 1037 1038 1039 Static void 1040 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1041 { 1042 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1043 struct usbd_xfer *xfer = &ex->ex_xfer; 1044 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1045 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1046 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1047 uint32_t status = 0, nstatus = 0; 1048 int actlen = 0; 1049 1050 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1051 1052 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1053 1054 /* 1055 * Try to claim this xfer for completion. If it has already 1056 * completed or aborted, drop it on the floor. 1057 */ 1058 if (!usbd_xfer_trycomplete(xfer)) 1059 return; 1060 1061 #ifdef DIAGNOSTIC 1062 #ifdef EHCI_DEBUG 1063 if (ex->ex_isdone) { 1064 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1065 ehci_dump_exfer(ex); 1066 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1067 } 1068 #endif 1069 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1070 ex->ex_type, xfer->ux_status); 1071 ex->ex_isdone = true; 1072 #endif 1073 1074 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1075 (uintptr_t)epipe, 0, 0); 1076 1077 /* The transfer is done, compute actual length and status. */ 1078 if (ex->ex_type == EX_ISOC) { 1079 /* HS isoc transfer */ 1080 1081 struct ehci_soft_itd *itd; 1082 int i, nframes, len, uframes; 1083 1084 nframes = 0; 1085 1086 #ifdef EHCI_DEBUG 1087 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1088 ehci_dump_itds(ex->ex_itdstart); 1089 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1090 #endif 1091 1092 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1093 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1094 1095 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1096 usb_syncmem(&itd->dma, 1097 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1098 sizeof(itd->itd.itd_ctl), 1099 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1100 1101 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1102 /* 1103 * XXX - driver didn't fill in the frame full 1104 * of uframes. This leads to scheduling 1105 * inefficiencies, but working around 1106 * this doubles complexity of tracking 1107 * an xfer. 1108 */ 1109 if (nframes >= xfer->ux_nframes) 1110 break; 1111 1112 status = le32toh(itd->itd.itd_ctl[i]); 1113 len = EHCI_ITD_GET_LEN(status); 1114 if (EHCI_ITD_GET_STATUS(status) != 0) 1115 len = 0; /*No valid data on error*/ 1116 1117 xfer->ux_frlengths[nframes++] = len; 1118 actlen += len; 1119 } 1120 usb_syncmem(&itd->dma, 1121 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1122 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1123 1124 if (nframes >= xfer->ux_nframes) 1125 break; 1126 } 1127 1128 xfer->ux_actlen = actlen; 1129 xfer->ux_status = USBD_NORMAL_COMPLETION; 1130 goto end; 1131 } else if (ex->ex_type == EX_FS_ISOC) { 1132 /* FS isoc transfer */ 1133 struct ehci_soft_sitd *sitd; 1134 int nframes, len; 1135 1136 nframes = 0; 1137 1138 for (sitd = ex->ex_sitdstart; sitd != NULL; 1139 sitd = sitd->xfer_next) { 1140 usb_syncmem(&sitd->dma, 1141 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1142 sizeof(sitd->sitd.sitd_trans), 1143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1144 1145 /* 1146 * XXX - driver didn't fill in the frame full 1147 * of uframes. This leads to scheduling 1148 * inefficiencies, but working around 1149 * this doubles complexity of tracking 1150 * an xfer. 1151 */ 1152 if (nframes >= xfer->ux_nframes) 1153 break; 1154 1155 status = le32toh(sitd->sitd.sitd_trans); 1156 usb_syncmem(&sitd->dma, 1157 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1158 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1159 1160 len = EHCI_SITD_GET_LEN(status); 1161 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1162 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1163 /* No valid data on error */ 1164 len = xfer->ux_frlengths[nframes]; 1165 } 1166 1167 /* 1168 * frlengths[i]: # of bytes to send 1169 * len: # of bytes host didn't send 1170 */ 1171 xfer->ux_frlengths[nframes] -= len; 1172 /* frlengths[i]: # of bytes host sent */ 1173 actlen += xfer->ux_frlengths[nframes++]; 1174 1175 if (nframes >= xfer->ux_nframes) 1176 break; 1177 } 1178 1179 xfer->ux_actlen = actlen; 1180 xfer->ux_status = USBD_NORMAL_COMPLETION; 1181 goto end; 1182 } 1183 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1184 ex->ex_type == EX_BULK); 1185 1186 /* Continue processing xfers using queue heads */ 1187 if (ex->ex_type == EX_CTRL) { 1188 fsqtd = ex->ex_setup; 1189 lsqtd = ex->ex_status; 1190 } else { 1191 fsqtd = ex->ex_sqtdstart; 1192 lsqtd = ex->ex_sqtdend; 1193 } 1194 #ifdef EHCI_DEBUG 1195 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1196 ehci_dump_sqtds(fsqtd); 1197 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1198 #endif 1199 1200 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1201 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1202 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1203 nstatus = le32toh(sqtd->qtd.qtd_status); 1204 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1205 BUS_DMASYNC_PREREAD); 1206 if (nstatus & EHCI_QTD_ACTIVE) 1207 break; 1208 1209 status = nstatus; 1210 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1211 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1212 } 1213 1214 /* 1215 * If there are left over TDs we need to update the toggle. 1216 * The default pipe doesn't need it since control transfers 1217 * start the toggle at 0 every time. 1218 * For a short transfer we need to update the toggle for the missing 1219 * packets within the qTD. 1220 */ 1221 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1222 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1223 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1224 status, nstatus, 0, 0); 1225 #if 0 1226 ehci_dump_sqh(epipe->sqh); 1227 ehci_dump_sqtds(ex->ex_sqtdstart); 1228 #endif 1229 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1230 } 1231 1232 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1233 status, 0); 1234 xfer->ux_actlen = actlen; 1235 if (status & EHCI_QTD_HALTED) { 1236 #ifdef EHCI_DEBUG 1237 DPRINTF("halted addr=%jd endpt=0x%02jx", 1238 xfer->ux_pipe->up_dev->ud_addr, 1239 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1240 0, 0); 1241 DPRINTF("cerr=%jd pid=%jd", 1242 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1243 0, 0); 1244 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1245 status & EHCI_QTD_ACTIVE ? 1 : 0, 1246 status & EHCI_QTD_HALTED ? 1 : 0, 1247 status & EHCI_QTD_BUFERR ? 1 : 0, 1248 status & EHCI_QTD_BABBLE ? 1 : 0); 1249 1250 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1251 status & EHCI_QTD_XACTERR ? 1 : 0, 1252 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1253 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1254 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1255 1256 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1257 ehci_dump_sqh(epipe->sqh); 1258 ehci_dump_sqtds(ex->ex_sqtdstart); 1259 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1260 #endif 1261 /* low&full speed has an extra error flag */ 1262 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1263 EHCI_QH_SPEED_HIGH) 1264 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1265 else 1266 status &= EHCI_QTD_STATERRS; 1267 if (status == 0) /* no other errors means a stall */ { 1268 xfer->ux_status = USBD_STALLED; 1269 } else { 1270 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1271 } 1272 /* XXX need to reset TT on missed microframe */ 1273 if (status & EHCI_QTD_MISSEDMICRO) { 1274 printf("%s: missed microframe, TT reset not " 1275 "implemented, hub might be inoperational\n", 1276 device_xname(sc->sc_dev)); 1277 } 1278 } else { 1279 xfer->ux_status = USBD_NORMAL_COMPLETION; 1280 } 1281 1282 end: 1283 1284 ehci_del_intr_list(sc, ex); 1285 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1286 1287 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1288 } 1289 1290 Static void 1291 ehci_poll(struct usbd_bus *bus) 1292 { 1293 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1294 1295 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1296 1297 #ifdef EHCI_DEBUG 1298 static int last; 1299 int new; 1300 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1301 if (new != last) { 1302 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1303 last = new; 1304 } 1305 #endif 1306 1307 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1308 mutex_spin_enter(&sc->sc_intr_lock); 1309 ehci_intr1(sc); 1310 mutex_spin_exit(&sc->sc_intr_lock); 1311 } 1312 } 1313 1314 void 1315 ehci_childdet(device_t self, device_t child) 1316 { 1317 struct ehci_softc *sc = device_private(self); 1318 1319 KASSERT(sc->sc_child == child); 1320 sc->sc_child = NULL; 1321 } 1322 1323 int 1324 ehci_detach(struct ehci_softc *sc, int flags) 1325 { 1326 int rv = 0; 1327 1328 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1329 1330 if (sc->sc_child != NULL) 1331 rv = config_detach(sc->sc_child, flags); 1332 1333 if (rv != 0) 1334 return rv; 1335 1336 if (sc->sc_ncomp > 0) { 1337 mutex_enter(&sc->sc_complock); 1338 /* XXX try to halt callout instead of waiting */ 1339 while (sc->sc_comp_state == CO_SCHED) 1340 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1341 mutex_exit(&sc->sc_complock); 1342 1343 callout_halt(&sc->sc_compcallout, NULL); 1344 callout_destroy(&sc->sc_compcallout); 1345 cv_destroy(&sc->sc_compcv); 1346 mutex_destroy(&sc->sc_complock); 1347 } 1348 1349 callout_halt(&sc->sc_tmo_intrlist, NULL); 1350 callout_destroy(&sc->sc_tmo_intrlist); 1351 1352 /* XXX free other data structures XXX */ 1353 if (sc->sc_softitds) 1354 kmem_free(sc->sc_softitds, 1355 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1356 cv_destroy(&sc->sc_doorbell); 1357 1358 #if 0 1359 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1360 1361 softint_disestablish(sc->sc_doorbell_si); 1362 softint_disestablish(sc->sc_pcd_si); 1363 1364 mutex_destroy(&sc->sc_lock); 1365 mutex_destroy(&sc->sc_intr_lock); 1366 #endif 1367 1368 pool_cache_destroy(sc->sc_xferpool); 1369 1370 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1371 1372 return rv; 1373 } 1374 1375 1376 int 1377 ehci_activate(device_t self, enum devact act) 1378 { 1379 struct ehci_softc *sc = device_private(self); 1380 1381 switch (act) { 1382 case DVACT_DEACTIVATE: 1383 sc->sc_dying = 1; 1384 return 0; 1385 default: 1386 return EOPNOTSUPP; 1387 } 1388 } 1389 1390 /* 1391 * Handle suspend/resume. 1392 * 1393 * We need to switch to polling mode here, because this routine is 1394 * called from an interrupt context. This is all right since we 1395 * are almost suspended anyway. 1396 * 1397 * Note that this power handler isn't to be registered directly; the 1398 * bus glue needs to call out to it. 1399 */ 1400 bool 1401 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1402 { 1403 ehci_softc_t *sc = device_private(dv); 1404 int i; 1405 uint32_t cmd, hcr; 1406 1407 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1408 1409 mutex_spin_enter(&sc->sc_intr_lock); 1410 sc->sc_bus.ub_usepolling++; 1411 mutex_spin_exit(&sc->sc_intr_lock); 1412 1413 for (i = 1; i <= sc->sc_noport; i++) { 1414 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1415 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1416 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1417 } 1418 1419 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1420 1421 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1422 EOWRITE4(sc, EHCI_USBCMD, cmd); 1423 1424 for (i = 0; i < 100; i++) { 1425 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1426 if (hcr == 0) 1427 break; 1428 1429 usb_delay_ms(&sc->sc_bus, 1); 1430 } 1431 if (hcr != 0) 1432 printf("%s: reset timeout\n", device_xname(dv)); 1433 1434 cmd &= ~EHCI_CMD_RS; 1435 EOWRITE4(sc, EHCI_USBCMD, cmd); 1436 1437 for (i = 0; i < 100; i++) { 1438 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1439 if (hcr == EHCI_STS_HCH) 1440 break; 1441 1442 usb_delay_ms(&sc->sc_bus, 1); 1443 } 1444 if (hcr != EHCI_STS_HCH) 1445 printf("%s: config timeout\n", device_xname(dv)); 1446 1447 mutex_spin_enter(&sc->sc_intr_lock); 1448 sc->sc_bus.ub_usepolling--; 1449 mutex_spin_exit(&sc->sc_intr_lock); 1450 1451 return true; 1452 } 1453 1454 bool 1455 ehci_resume(device_t dv, const pmf_qual_t *qual) 1456 { 1457 ehci_softc_t *sc = device_private(dv); 1458 int i; 1459 uint32_t cmd, hcr; 1460 1461 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1462 1463 /* restore things in case the bios sucks */ 1464 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1465 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1466 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1467 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1468 1469 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1470 1471 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1472 1473 hcr = 0; 1474 for (i = 1; i <= sc->sc_noport; i++) { 1475 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1476 if ((cmd & EHCI_PS_PO) == 0 && 1477 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1478 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1479 hcr = 1; 1480 } 1481 } 1482 1483 if (hcr) { 1484 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1485 1486 for (i = 1; i <= sc->sc_noport; i++) { 1487 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1488 if ((cmd & EHCI_PS_PO) == 0 && 1489 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1490 EOWRITE4(sc, EHCI_PORTSC(i), 1491 cmd & ~EHCI_PS_FPR); 1492 } 1493 } 1494 1495 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1496 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1497 1498 for (i = 0; i < 100; i++) { 1499 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1500 if (hcr != EHCI_STS_HCH) 1501 break; 1502 1503 usb_delay_ms(&sc->sc_bus, 1); 1504 } 1505 if (hcr == EHCI_STS_HCH) 1506 printf("%s: config timeout\n", device_xname(dv)); 1507 1508 return true; 1509 } 1510 1511 /* 1512 * Shut down the controller when the system is going down. 1513 */ 1514 bool 1515 ehci_shutdown(device_t self, int flags) 1516 { 1517 ehci_softc_t *sc = device_private(self); 1518 1519 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1520 1521 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1522 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1523 return true; 1524 } 1525 1526 Static struct usbd_xfer * 1527 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1528 { 1529 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1530 struct usbd_xfer *xfer; 1531 1532 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1533 if (xfer != NULL) { 1534 memset(xfer, 0, sizeof(struct ehci_xfer)); 1535 1536 #ifdef DIAGNOSTIC 1537 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1538 ex->ex_isdone = true; 1539 xfer->ux_state = XFER_BUSY; 1540 #endif 1541 } 1542 return xfer; 1543 } 1544 1545 Static void 1546 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1547 { 1548 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1549 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1550 1551 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1552 xfer->ux_status == USBD_NOT_STARTED, 1553 "xfer %p state %d\n", xfer, xfer->ux_state); 1554 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1555 1556 #ifdef DIAGNOSTIC 1557 xfer->ux_state = XFER_FREE; 1558 #endif 1559 1560 pool_cache_put(sc->sc_xferpool, xfer); 1561 } 1562 1563 Static bool 1564 ehci_dying(struct usbd_bus *bus) 1565 { 1566 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1567 1568 return sc->sc_dying; 1569 } 1570 1571 Static void 1572 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1573 { 1574 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1575 1576 *lock = &sc->sc_lock; 1577 } 1578 1579 Static void 1580 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1581 { 1582 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1583 1584 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1585 1586 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1587 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1588 #ifdef EHCI_DEBUG 1589 if (ehcidebug) 1590 usbd_dump_pipe(pipe); 1591 #endif 1592 epipe->nexttoggle = 0; 1593 } 1594 1595 Static void 1596 ehci_noop(struct usbd_pipe *pipe) 1597 { 1598 } 1599 1600 #ifdef EHCI_DEBUG 1601 /* 1602 * Unused function - this is meant to be called from a kernel 1603 * debugger. 1604 */ 1605 void 1606 ehci_dump(void) 1607 { 1608 ehci_softc_t *sc = theehci; 1609 int i; 1610 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1611 EOREAD4(sc, EHCI_USBCMD), 1612 EOREAD4(sc, EHCI_USBSTS), 1613 EOREAD4(sc, EHCI_USBINTR)); 1614 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1615 EOREAD4(sc, EHCI_FRINDEX), 1616 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1617 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1618 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1619 for (i = 1; i <= sc->sc_noport; i++) 1620 printf("port %d status=0x%08x\n", i, 1621 EOREAD4(sc, EHCI_PORTSC(i))); 1622 } 1623 1624 Static void 1625 ehci_dump_regs(ehci_softc_t *sc) 1626 { 1627 int i; 1628 1629 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1630 1631 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1632 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1633 EOREAD4(sc, EHCI_USBINTR), 0); 1634 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1635 "async = 0x%08jx", 1636 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1637 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1638 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1639 for (i = 1; i <= sc->sc_noport; i += 2) { 1640 if (i == sc->sc_noport) { 1641 DPRINTF("port %jd status = 0x%08jx", i, 1642 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1643 } else { 1644 DPRINTF("port %jd status = 0x%08jx port %jd " 1645 "status = 0x%08jx", 1646 i, EOREAD4(sc, EHCI_PORTSC(i)), 1647 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1648 } 1649 } 1650 } 1651 1652 #define ehci_dump_link(link, type) do { \ 1653 DPRINTF(" link 0x%08jx (T = %jd):", \ 1654 link, \ 1655 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1656 if (type) { \ 1657 DPRINTF( \ 1658 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1659 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1660 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1661 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1662 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1663 } \ 1664 } while(0) 1665 1666 Static void 1667 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1668 { 1669 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1670 int i; 1671 uint32_t stop = 0; 1672 1673 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1674 ehci_dump_sqtd(sqtd); 1675 usb_syncmem(&sqtd->dma, 1676 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1677 sizeof(sqtd->qtd), 1678 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1679 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1680 usb_syncmem(&sqtd->dma, 1681 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1682 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1683 } 1684 if (!stop) 1685 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1686 } 1687 1688 Static void 1689 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1690 { 1691 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1692 1693 usb_syncmem(&sqtd->dma, sqtd->offs, 1694 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1695 1696 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1697 0, 0); 1698 ehci_dump_qtd(&sqtd->qtd); 1699 1700 usb_syncmem(&sqtd->dma, sqtd->offs, 1701 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1702 } 1703 1704 Static void 1705 ehci_dump_qtd(ehci_qtd_t *qtd) 1706 { 1707 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1708 uint32_t s = le32toh(qtd->qtd_status); 1709 1710 DPRINTFN(10, 1711 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1712 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1713 DPRINTFN(10, 1714 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1715 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1716 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1717 DPRINTFN(10, 1718 " cerr = %jd pid = %jd stat = %jx", 1719 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1720 0); 1721 DPRINTFN(10, 1722 "active =%jd halted=%jd buferr=%jd babble=%jd", 1723 s & EHCI_QTD_ACTIVE ? 1 : 0, 1724 s & EHCI_QTD_HALTED ? 1 : 0, 1725 s & EHCI_QTD_BUFERR ? 1 : 0, 1726 s & EHCI_QTD_BABBLE ? 1 : 0); 1727 DPRINTFN(10, 1728 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1729 s & EHCI_QTD_XACTERR ? 1 : 0, 1730 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1731 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1732 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1733 DPRINTFN(10, 1734 "buffer[0] = %#jx buffer[1] = %#jx " 1735 "buffer[2] = %#jx buffer[3] = %#jx", 1736 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1737 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1738 DPRINTFN(10, 1739 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1740 } 1741 1742 Static void 1743 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1744 { 1745 ehci_qh_t *qh = &sqh->qh; 1746 ehci_link_t link; 1747 uint32_t endp, endphub; 1748 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1749 1750 usb_syncmem(&sqh->dma, sqh->offs, 1751 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1752 1753 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1754 link = le32toh(qh->qh_link); 1755 ehci_dump_link(link, true); 1756 1757 endp = le32toh(qh->qh_endp); 1758 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1759 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1760 "eps = %jd", 1761 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1762 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1763 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1764 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1765 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1766 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1767 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1768 1769 endphub = le32toh(qh->qh_endphub); 1770 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1771 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1772 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1773 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1774 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1775 EHCI_QH_GET_MULT(endphub), 0); 1776 1777 link = le32toh(qh->qh_curqtd); 1778 ehci_dump_link(link, false); 1779 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1780 ehci_dump_qtd(&qh->qh_qtd); 1781 1782 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1783 BUS_DMASYNC_PREREAD); 1784 } 1785 1786 Static void 1787 ehci_dump_itds(ehci_soft_itd_t *itd) 1788 { 1789 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1790 int i; 1791 uint32_t stop = 0; 1792 1793 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1794 ehci_dump_itd(itd); 1795 usb_syncmem(&itd->dma, 1796 itd->offs + offsetof(ehci_itd_t, itd_next), 1797 sizeof(itd->itd), 1798 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1799 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1800 usb_syncmem(&itd->dma, 1801 itd->offs + offsetof(ehci_itd_t, itd_next), 1802 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1803 } 1804 if (!stop) 1805 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1806 } 1807 1808 Static void 1809 ehci_dump_itd(struct ehci_soft_itd *itd) 1810 { 1811 ehci_isoc_trans_t t; 1812 ehci_isoc_bufr_ptr_t b, b2, b3; 1813 int i; 1814 1815 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1816 1817 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1818 1819 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1820 t = le32toh(itd->itd.itd_ctl[i]); 1821 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1822 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1823 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1824 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1825 EHCI_ITD_GET_OFFS(t), 0); 1826 } 1827 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1828 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1829 DPRINTF(" %jx", 1830 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1831 1832 b = le32toh(itd->itd.itd_bufr[0]); 1833 b2 = le32toh(itd->itd.itd_bufr[1]); 1834 b3 = le32toh(itd->itd.itd_bufr[2]); 1835 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1836 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1837 DPRINTF(" maxpkt = %jx multi = %jx", 1838 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1839 } 1840 1841 Static void 1842 ehci_dump_sitd(struct ehci_soft_itd *itd) 1843 { 1844 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1845 1846 DPRINTF("SITD %#jx next = %p prev = %#jx", 1847 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1848 (uintptr_t)itd->frame_list.prev, 0); 1849 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1850 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1851 } 1852 1853 Static void 1854 ehci_dump_exfer(struct ehci_xfer *ex) 1855 { 1856 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1857 1858 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1859 ex->ex_isdone, 0); 1860 1861 switch (ex->ex_type) { 1862 case EX_CTRL: 1863 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1864 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1865 (uintptr_t)ex->ex_status, 0); 1866 break; 1867 case EX_BULK: 1868 case EX_INTR: 1869 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1870 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1871 0, 0); 1872 break; 1873 case EX_ISOC: 1874 DPRINTF(" itdstart = %#jx itdend = %#jx", 1875 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1876 break; 1877 case EX_FS_ISOC: 1878 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1879 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1880 0, 0); 1881 break; 1882 default: 1883 DPRINTF(" unknown type", 0, 0, 0, 0); 1884 } 1885 } 1886 #endif 1887 1888 Static usbd_status 1889 ehci_open(struct usbd_pipe *pipe) 1890 { 1891 struct usbd_device *dev = pipe->up_dev; 1892 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1893 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1894 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1895 uint8_t addr = dev->ud_addr; 1896 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1897 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1898 ehci_soft_qh_t *sqh; 1899 usbd_status err; 1900 int ival, speed, naks; 1901 int hshubaddr, hshubport; 1902 1903 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1904 1905 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1906 ed->bEndpointAddress, rhaddr); 1907 1908 if (dev->ud_myhsport) { 1909 /* 1910 * When directly attached FS/LS device while doing embedded 1911 * transaction translations and we are the hub, set the hub 1912 * address to 0 (us). 1913 */ 1914 if (!(sc->sc_flags & EHCIF_ETTF) 1915 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1916 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1917 } else { 1918 hshubaddr = 0; 1919 } 1920 hshubport = dev->ud_myhsport->up_portno; 1921 } else { 1922 hshubaddr = 0; 1923 hshubport = 0; 1924 } 1925 1926 if (sc->sc_dying) 1927 return USBD_IOERROR; 1928 1929 /* toggle state needed for bulk endpoints */ 1930 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1931 1932 if (addr == rhaddr) { 1933 switch (ed->bEndpointAddress) { 1934 case USB_CONTROL_ENDPOINT: 1935 pipe->up_methods = &roothub_ctrl_methods; 1936 break; 1937 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1938 pipe->up_methods = &ehci_root_intr_methods; 1939 break; 1940 default: 1941 DPRINTF("bad bEndpointAddress 0x%02jx", 1942 ed->bEndpointAddress, 0, 0, 0); 1943 return USBD_INVAL; 1944 } 1945 return USBD_NORMAL_COMPLETION; 1946 } 1947 1948 /* XXX All this stuff is only valid for async. */ 1949 switch (dev->ud_speed) { 1950 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1951 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1952 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1953 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1954 } 1955 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1956 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1957 0); 1958 return USBD_INVAL; 1959 } 1960 1961 /* 1962 * For interrupt transfer, nak throttling must be disabled, but for 1963 * the other transfer type, nak throttling should be enabled from the 1964 * viewpoint that avoids the memory thrashing. 1965 */ 1966 naks = (xfertype == UE_INTERRUPT) ? 0 1967 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1968 1969 /* Allocate sqh for everything, save isoc xfers */ 1970 if (xfertype != UE_ISOCHRONOUS) { 1971 sqh = ehci_alloc_sqh(sc); 1972 if (sqh == NULL) 1973 return USBD_NOMEM; 1974 /* qh_link filled when the QH is added */ 1975 sqh->qh.qh_endp = htole32( 1976 EHCI_QH_SET_ADDR(addr) | 1977 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1978 EHCI_QH_SET_EPS(speed) | 1979 EHCI_QH_DTC | 1980 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1981 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1982 EHCI_QH_CTL : 0) | 1983 EHCI_QH_SET_NRL(naks) 1984 ); 1985 sqh->qh.qh_endphub = htole32( 1986 EHCI_QH_SET_MULT(1) | 1987 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1988 ); 1989 if (speed != EHCI_QH_SPEED_HIGH) 1990 sqh->qh.qh_endphub |= htole32( 1991 EHCI_QH_SET_PORT(hshubport) | 1992 EHCI_QH_SET_HUBA(hshubaddr) | 1993 (xfertype == UE_INTERRUPT ? 1994 EHCI_QH_SET_CMASK(0x08) : 0) 1995 ); 1996 sqh->qh.qh_curqtd = EHCI_NULL; 1997 /* Fill the overlay qTD */ 1998 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1999 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2000 sqh->qh.qh_qtd.qtd_status = htole32(0); 2001 2002 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2003 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2004 epipe->sqh = sqh; 2005 } else { 2006 sqh = NULL; 2007 } /*xfertype == UE_ISOC*/ 2008 2009 switch (xfertype) { 2010 case UE_CONTROL: 2011 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2012 0, USBMALLOC_COHERENT, &epipe->ctrl.reqdma); 2013 #ifdef EHCI_DEBUG 2014 if (err) 2015 printf("ehci_open: usb_allocmem()=%d\n", err); 2016 #endif 2017 if (err) 2018 goto bad; 2019 pipe->up_methods = &ehci_device_ctrl_methods; 2020 mutex_enter(&sc->sc_lock); 2021 ehci_add_qh(sc, sqh, sc->sc_async_head); 2022 mutex_exit(&sc->sc_lock); 2023 break; 2024 case UE_BULK: 2025 pipe->up_methods = &ehci_device_bulk_methods; 2026 mutex_enter(&sc->sc_lock); 2027 ehci_add_qh(sc, sqh, sc->sc_async_head); 2028 mutex_exit(&sc->sc_lock); 2029 break; 2030 case UE_INTERRUPT: 2031 pipe->up_methods = &ehci_device_intr_methods; 2032 ival = pipe->up_interval; 2033 if (ival == USBD_DEFAULT_INTERVAL) { 2034 if (speed == EHCI_QH_SPEED_HIGH) { 2035 if (ed->bInterval > 16) { 2036 /* 2037 * illegal with high-speed, but there 2038 * were documentation bugs in the spec, 2039 * so be generous 2040 */ 2041 ival = 256; 2042 } else 2043 ival = (1 << (ed->bInterval - 1)) / 8; 2044 } else 2045 ival = ed->bInterval; 2046 } 2047 err = ehci_device_setintr(sc, sqh, ival); 2048 if (err) 2049 goto bad; 2050 break; 2051 case UE_ISOCHRONOUS: 2052 pipe->up_serialise = false; 2053 if (speed == EHCI_QH_SPEED_HIGH) 2054 pipe->up_methods = &ehci_device_isoc_methods; 2055 else 2056 pipe->up_methods = &ehci_device_fs_isoc_methods; 2057 if (ed->bInterval == 0 || ed->bInterval > 16) { 2058 printf("ehci: opening pipe with invalid bInterval\n"); 2059 err = USBD_INVAL; 2060 goto bad; 2061 } 2062 if (UGETW(ed->wMaxPacketSize) == 0) { 2063 printf("ehci: zero length endpoint open request\n"); 2064 err = USBD_INVAL; 2065 goto bad; 2066 } 2067 epipe->isoc.next_frame = 0; 2068 epipe->isoc.cur_xfers = 0; 2069 break; 2070 default: 2071 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2072 err = USBD_INVAL; 2073 goto bad; 2074 } 2075 return USBD_NORMAL_COMPLETION; 2076 2077 bad: 2078 if (sqh != NULL) { 2079 mutex_enter(&sc->sc_lock); 2080 ehci_free_sqh(sc, sqh); 2081 mutex_exit(&sc->sc_lock); 2082 } 2083 return err; 2084 } 2085 2086 /* 2087 * Add an ED to the schedule. Called with USB lock held. 2088 */ 2089 Static void 2090 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2091 { 2092 2093 KASSERT(mutex_owned(&sc->sc_lock)); 2094 2095 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2096 2097 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2098 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2099 2100 sqh->next = head->next; 2101 sqh->qh.qh_link = head->qh.qh_link; 2102 2103 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2104 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2105 2106 head->next = sqh; 2107 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2108 2109 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2110 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2111 2112 #ifdef EHCI_DEBUG 2113 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2114 ehci_dump_sqh(sqh); 2115 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2116 #endif 2117 } 2118 2119 /* 2120 * Remove an ED from the schedule. Called with USB lock held. 2121 */ 2122 Static void 2123 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2124 { 2125 ehci_soft_qh_t *p; 2126 2127 KASSERT(mutex_owned(&sc->sc_lock)); 2128 2129 /* XXX */ 2130 for (p = head; p != NULL && p->next != sqh; p = p->next) 2131 ; 2132 if (p == NULL) 2133 panic("ehci_rem_qh: ED not found"); 2134 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2135 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2136 p->next = sqh->next; 2137 p->qh.qh_link = sqh->qh.qh_link; 2138 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2139 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2140 2141 ehci_sync_hc(sc); 2142 } 2143 2144 Static void 2145 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2146 { 2147 int i; 2148 uint32_t status; 2149 2150 /* Save toggle bit and ping status. */ 2151 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2152 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2153 status = sqh->qh.qh_qtd.qtd_status & 2154 htole32(EHCI_QTD_TOGGLE_MASK | 2155 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2156 /* Set HALTED to make hw leave it alone. */ 2157 sqh->qh.qh_qtd.qtd_status = 2158 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2159 usb_syncmem(&sqh->dma, 2160 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2161 sizeof(sqh->qh.qh_qtd.qtd_status), 2162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2163 sqh->qh.qh_curqtd = 0; 2164 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2165 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2166 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2167 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2168 sqh->sqtd = sqtd; 2169 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2170 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2171 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2172 sqh->qh.qh_qtd.qtd_status = status; 2173 usb_syncmem(&sqh->dma, 2174 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2175 sizeof(sqh->qh.qh_qtd.qtd_status), 2176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2177 } 2178 2179 /* 2180 * Ensure that the HC has released all references to the QH. We do this 2181 * by asking for a Async Advance Doorbell interrupt and then we wait for 2182 * the interrupt. 2183 * To make this easier we first obtain exclusive use of the doorbell. 2184 */ 2185 Static void 2186 ehci_sync_hc(ehci_softc_t *sc) 2187 { 2188 int error __diagused; 2189 2190 KASSERT(mutex_owned(&sc->sc_lock)); 2191 2192 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2193 2194 if (sc->sc_dying) { 2195 DPRINTF("dying", 0, 0, 0, 0); 2196 return; 2197 } 2198 2199 /* ask for doorbell */ 2200 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2201 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2202 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2203 2204 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2205 2206 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2207 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2208 #ifdef DIAGNOSTIC 2209 if (error == EWOULDBLOCK) { 2210 printf("ehci_sync_hc: timed out\n"); 2211 } else if (error) { 2212 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2213 } 2214 #endif 2215 } 2216 2217 Static void 2218 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2219 { 2220 2221 KASSERT(mutex_owned(&sc->sc_lock)); 2222 2223 for (; itd != NULL; itd = itd->xfer_next) { 2224 struct ehci_soft_itd *prev = itd->frame_list.prev; 2225 2226 /* Unlink itd from hardware chain, or frame array */ 2227 if (prev == NULL) { /* We're at the table head */ 2228 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2229 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2230 usb_syncmem(&sc->sc_fldma, 2231 sizeof(ehci_link_t) * itd->slot, 2232 sizeof(ehci_link_t), 2233 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2234 2235 if (itd->frame_list.next != NULL) 2236 itd->frame_list.next->frame_list.prev = NULL; 2237 } else { 2238 /* XXX this part is untested... */ 2239 prev->itd.itd_next = itd->itd.itd_next; 2240 usb_syncmem(&itd->dma, 2241 itd->offs + offsetof(ehci_itd_t, itd_next), 2242 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2243 2244 prev->frame_list.next = itd->frame_list.next; 2245 if (itd->frame_list.next != NULL) 2246 itd->frame_list.next->frame_list.prev = prev; 2247 } 2248 } 2249 } 2250 2251 Static void 2252 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2253 { 2254 struct ehci_soft_itd *next; 2255 2256 mutex_enter(&sc->sc_lock); 2257 next = NULL; 2258 for (; itd != NULL; itd = next) { 2259 next = itd->xfer_next; 2260 ehci_free_itd_locked(sc, itd); 2261 } 2262 mutex_exit(&sc->sc_lock); 2263 } 2264 2265 Static void 2266 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2267 { 2268 2269 KASSERT(mutex_owned(&sc->sc_lock)); 2270 2271 for (; sitd != NULL; sitd = sitd->xfer_next) { 2272 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2273 2274 /* Unlink sitd from hardware chain, or frame array */ 2275 if (prev == NULL) { /* We're at the table head */ 2276 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2277 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2278 usb_syncmem(&sc->sc_fldma, 2279 sizeof(ehci_link_t) * sitd->slot, 2280 sizeof(ehci_link_t), 2281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2282 2283 if (sitd->frame_list.next != NULL) 2284 sitd->frame_list.next->frame_list.prev = NULL; 2285 } else { 2286 /* XXX this part is untested... */ 2287 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2288 usb_syncmem(&sitd->dma, 2289 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2290 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2291 2292 prev->frame_list.next = sitd->frame_list.next; 2293 if (sitd->frame_list.next != NULL) 2294 sitd->frame_list.next->frame_list.prev = prev; 2295 } 2296 } 2297 } 2298 2299 Static void 2300 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2301 { 2302 2303 mutex_enter(&sc->sc_lock); 2304 struct ehci_soft_sitd *next = NULL; 2305 for (; sitd != NULL; sitd = next) { 2306 next = sitd->xfer_next; 2307 ehci_free_sitd_locked(sc, sitd); 2308 } 2309 mutex_exit(&sc->sc_lock); 2310 } 2311 2312 /***********/ 2313 2314 Static int 2315 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2316 void *buf, int buflen) 2317 { 2318 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2319 usb_hub_descriptor_t hubd; 2320 usb_port_status_t ps; 2321 uint16_t len, value, index; 2322 int l, totlen = 0; 2323 int port, i; 2324 uint32_t v; 2325 2326 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2327 2328 if (sc->sc_dying) 2329 return -1; 2330 2331 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2332 0, 0); 2333 2334 len = UGETW(req->wLength); 2335 value = UGETW(req->wValue); 2336 index = UGETW(req->wIndex); 2337 2338 #define C(x,y) ((x) | ((y) << 8)) 2339 switch (C(req->bRequest, req->bmRequestType)) { 2340 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2341 if (len == 0) 2342 break; 2343 switch (value) { 2344 #define sd ((usb_string_descriptor_t *)buf) 2345 case C(2, UDESC_STRING): 2346 /* Product */ 2347 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2348 break; 2349 #undef sd 2350 default: 2351 /* default from usbroothub */ 2352 return buflen; 2353 } 2354 break; 2355 2356 /* Hub requests */ 2357 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2358 break; 2359 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2360 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2361 value, 0, 0); 2362 if (index < 1 || index > sc->sc_noport) { 2363 return -1; 2364 } 2365 port = EHCI_PORTSC(index); 2366 v = EOREAD4(sc, port); 2367 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2368 v &= ~EHCI_PS_CLEAR; 2369 switch (value) { 2370 case UHF_PORT_ENABLE: 2371 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2372 break; 2373 case UHF_PORT_SUSPEND: 2374 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2375 break; 2376 v &= ~EHCI_PS_SUSP; 2377 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2378 /* see USB2 spec ch. 7.1.7.7 */ 2379 usb_delay_ms(&sc->sc_bus, 20); 2380 EOWRITE4(sc, port, v); 2381 usb_delay_ms(&sc->sc_bus, 2); 2382 #ifdef DEBUG 2383 v = EOREAD4(sc, port); 2384 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2385 printf("ehci: resume failed: %x\n", v); 2386 #endif 2387 break; 2388 case UHF_PORT_POWER: 2389 if (sc->sc_hasppc) 2390 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2391 break; 2392 case UHF_PORT_TEST: 2393 DPRINTF("clear port test %jd", index, 0, 0, 0); 2394 break; 2395 case UHF_PORT_INDICATOR: 2396 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2397 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2398 break; 2399 case UHF_C_PORT_CONNECTION: 2400 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2401 break; 2402 case UHF_C_PORT_ENABLE: 2403 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2404 break; 2405 case UHF_C_PORT_SUSPEND: 2406 /* how? */ 2407 break; 2408 case UHF_C_PORT_OVER_CURRENT: 2409 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2410 break; 2411 case UHF_C_PORT_RESET: 2412 sc->sc_isreset[index] = 0; 2413 break; 2414 default: 2415 return -1; 2416 } 2417 #if 0 2418 switch(value) { 2419 case UHF_C_PORT_CONNECTION: 2420 case UHF_C_PORT_ENABLE: 2421 case UHF_C_PORT_SUSPEND: 2422 case UHF_C_PORT_OVER_CURRENT: 2423 case UHF_C_PORT_RESET: 2424 default: 2425 break; 2426 } 2427 #endif 2428 break; 2429 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2430 if (len == 0) 2431 break; 2432 if ((value & 0xff) != 0) { 2433 return -1; 2434 } 2435 totlen = uimin(buflen, sizeof(hubd)); 2436 memcpy(&hubd, buf, totlen); 2437 hubd.bNbrPorts = sc->sc_noport; 2438 v = EOREAD4(sc, EHCI_HCSPARAMS); 2439 USETW(hubd.wHubCharacteristics, 2440 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2441 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2442 ? UHD_PORT_IND : 0); 2443 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2444 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2445 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2446 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2447 totlen = uimin(totlen, hubd.bDescLength); 2448 memcpy(buf, &hubd, totlen); 2449 break; 2450 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2451 if (len != 4) { 2452 return -1; 2453 } 2454 memset(buf, 0, len); /* ? XXX */ 2455 totlen = len; 2456 break; 2457 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2458 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2459 if (index < 1 || index > sc->sc_noport) { 2460 return -1; 2461 } 2462 if (len != 4) { 2463 return -1; 2464 } 2465 v = EOREAD4(sc, EHCI_PORTSC(index)); 2466 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2467 2468 i = UPS_HIGH_SPEED; 2469 if (sc->sc_flags & EHCIF_ETTF) { 2470 /* 2471 * If we are doing embedded transaction translation, 2472 * then directly attached LS/FS devices are reset by 2473 * the EHCI controller itself. PSPD is encoded 2474 * the same way as in USBSTATUS. 2475 */ 2476 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2477 } 2478 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2479 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2480 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2481 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2482 if (v & EHCI_PS_PR) i |= UPS_RESET; 2483 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2484 if (sc->sc_vendor_port_status) 2485 i = sc->sc_vendor_port_status(sc, v, i); 2486 USETW(ps.wPortStatus, i); 2487 i = 0; 2488 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2489 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2490 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2491 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2492 USETW(ps.wPortChange, i); 2493 totlen = uimin(len, sizeof(ps)); 2494 memcpy(buf, &ps, totlen); 2495 break; 2496 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2497 return -1; 2498 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2499 break; 2500 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2501 if (index < 1 || index > sc->sc_noport) { 2502 return -1; 2503 } 2504 port = EHCI_PORTSC(index); 2505 v = EOREAD4(sc, port); 2506 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2507 v &= ~EHCI_PS_CLEAR; 2508 switch(value) { 2509 case UHF_PORT_ENABLE: 2510 EOWRITE4(sc, port, v | EHCI_PS_PE); 2511 break; 2512 case UHF_PORT_SUSPEND: 2513 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2514 break; 2515 case UHF_PORT_RESET: 2516 DPRINTF("reset port %jd", index, 0, 0, 0); 2517 if (EHCI_PS_IS_LOWSPEED(v) 2518 && sc->sc_ncomp > 0 2519 && !(sc->sc_flags & EHCIF_ETTF)) { 2520 /* 2521 * Low speed device on non-ETTF controller or 2522 * unaccompanied controller, give up ownership. 2523 */ 2524 ehci_disown(sc, index, 1); 2525 break; 2526 } 2527 /* Start reset sequence. */ 2528 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2529 EOWRITE4(sc, port, v | EHCI_PS_PR); 2530 /* Wait for reset to complete. */ 2531 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2532 if (sc->sc_dying) { 2533 return -1; 2534 } 2535 /* 2536 * An embedded transaction translator will automatically 2537 * terminate the reset sequence so there's no need to 2538 * it. 2539 */ 2540 v = EOREAD4(sc, port); 2541 if (v & EHCI_PS_PR) { 2542 /* Terminate reset sequence. */ 2543 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2544 /* Wait for HC to complete reset. */ 2545 usb_delay_ms(&sc->sc_bus, 2546 EHCI_PORT_RESET_COMPLETE); 2547 if (sc->sc_dying) { 2548 return -1; 2549 } 2550 } 2551 2552 v = EOREAD4(sc, port); 2553 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2554 if (v & EHCI_PS_PR) { 2555 printf("%s: port reset timeout\n", 2556 device_xname(sc->sc_dev)); 2557 return USBD_TIMEOUT; 2558 } 2559 if (!(v & EHCI_PS_PE)) { 2560 /* Not a high speed device, give up ownership.*/ 2561 ehci_disown(sc, index, 0); 2562 break; 2563 } 2564 sc->sc_isreset[index] = 1; 2565 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2566 v, 0, 0); 2567 break; 2568 case UHF_PORT_POWER: 2569 DPRINTF("set port power %jd (has PPC = %jd)", index, 2570 sc->sc_hasppc, 0, 0); 2571 if (sc->sc_hasppc) 2572 EOWRITE4(sc, port, v | EHCI_PS_PP); 2573 break; 2574 case UHF_PORT_TEST: 2575 DPRINTF("set port test %jd", index, 0, 0, 0); 2576 break; 2577 case UHF_PORT_INDICATOR: 2578 DPRINTF("set port ind %jd", index, 0, 0, 0); 2579 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2580 break; 2581 default: 2582 return -1; 2583 } 2584 break; 2585 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2586 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2587 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2588 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2589 break; 2590 default: 2591 /* default from usbroothub */ 2592 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2593 2594 return buflen; 2595 } 2596 2597 DPRINTF("returning %jd", totlen, 0, 0, 0); 2598 2599 return totlen; 2600 } 2601 2602 /* 2603 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2604 * 2605 * This pile of garbage below works around the following problem without 2606 * holding boots with no hand-over devices present, while penalising 2607 * boots where the first ehci probe hands off devices with a 5 second 2608 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2609 * for RB_SINGLE, but the same basic issue exists. 2610 * 2611 * The way ehci hand-off works, the companion controller does not get the 2612 * device until after its initial bus explore, so the reference dropped 2613 * after the first explore is not enough. 5 seconds should be enough, 2614 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2615 * 2616 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2617 * if the callback is scheduled. CO_DONE is set when the callout has 2618 * called config_pending_decr(). 2619 * 2620 * There's a mutex, a cv and a callout here, and we delay detach if the 2621 * callout has been set. 2622 */ 2623 #ifndef EHCI_DISOWN_DELAY_SECONDS 2624 #define EHCI_DISOWN_DELAY_SECONDS 5 2625 #endif 2626 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2627 2628 static void 2629 ehci_disown_callback(void *arg) 2630 { 2631 ehci_softc_t *sc = arg; 2632 2633 config_pending_decr(sc->sc_dev); 2634 2635 mutex_enter(&sc->sc_complock); 2636 KASSERT(sc->sc_comp_state == CO_SCHED); 2637 sc->sc_comp_state = CO_DONE; 2638 cv_signal(&sc->sc_compcv); 2639 mutex_exit(&sc->sc_complock); 2640 } 2641 2642 static void 2643 ehci_disown_sched_callback(ehci_softc_t *sc) 2644 { 2645 extern bool root_is_mounted; 2646 2647 mutex_enter(&sc->sc_complock); 2648 2649 if (root_is_mounted || 2650 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2651 sc->sc_comp_state != CO_EARLY) { 2652 mutex_exit(&sc->sc_complock); 2653 return; 2654 } 2655 2656 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2657 ehci_disown_callback, &sc->sc_dev); 2658 sc->sc_comp_state = CO_SCHED; 2659 2660 mutex_exit(&sc->sc_complock); 2661 2662 config_pending_incr(sc->sc_dev); 2663 aprint_normal("delaying %s by %u seconds due to USB owner change.", 2664 (boothowto & RB_ASKNAME) == 0 ? "ask root" : "single user", 2665 ehci_disown_delay_seconds); 2666 } 2667 2668 Static void 2669 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2670 { 2671 int port; 2672 uint32_t v; 2673 2674 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2675 2676 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2677 if (sc->sc_npcomp != 0) { 2678 int i = (index-1) / sc->sc_npcomp; 2679 if (i < sc->sc_ncomp) { 2680 ehci_disown_sched_callback(sc); 2681 #ifdef DIAGNOSTIC 2682 printf("%s: handing over %s speed device on " 2683 "port %d to %s\n", 2684 device_xname(sc->sc_dev), 2685 lowspeed ? "low" : "full", 2686 index, sc->sc_comps[i] ? 2687 device_xname(sc->sc_comps[i]) : 2688 "companion controller"); 2689 } else { 2690 printf("%s: strange port\n", 2691 device_xname(sc->sc_dev)); 2692 #endif 2693 } 2694 } else { 2695 #ifdef DIAGNOSTIC 2696 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2697 #endif 2698 } 2699 port = EHCI_PORTSC(index); 2700 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2701 EOWRITE4(sc, port, v | EHCI_PS_PO); 2702 } 2703 2704 Static usbd_status 2705 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2706 { 2707 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2708 usbd_status err; 2709 2710 /* Insert last in queue. */ 2711 mutex_enter(&sc->sc_lock); 2712 err = usb_insert_transfer(xfer); 2713 mutex_exit(&sc->sc_lock); 2714 if (err) 2715 return err; 2716 2717 /* Pipe isn't running, start first */ 2718 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2719 } 2720 2721 Static usbd_status 2722 ehci_root_intr_start(struct usbd_xfer *xfer) 2723 { 2724 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2725 const bool polling = sc->sc_bus.ub_usepolling; 2726 2727 if (sc->sc_dying) 2728 return USBD_IOERROR; 2729 2730 if (!polling) 2731 mutex_enter(&sc->sc_lock); 2732 KASSERT(sc->sc_intrxfer == NULL); 2733 sc->sc_intrxfer = xfer; 2734 xfer->ux_status = USBD_IN_PROGRESS; 2735 if (!polling) 2736 mutex_exit(&sc->sc_lock); 2737 2738 return USBD_IN_PROGRESS; 2739 } 2740 2741 /* Abort a root interrupt request. */ 2742 Static void 2743 ehci_root_intr_abort(struct usbd_xfer *xfer) 2744 { 2745 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2746 2747 KASSERT(mutex_owned(&sc->sc_lock)); 2748 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2749 2750 /* If xfer has already completed, nothing to do here. */ 2751 if (sc->sc_intrxfer == NULL) 2752 return; 2753 2754 /* 2755 * Otherwise, sc->sc_intrxfer had better be this transfer. 2756 * Cancel it. 2757 */ 2758 KASSERT(sc->sc_intrxfer == xfer); 2759 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2760 xfer->ux_status = USBD_CANCELLED; 2761 usb_transfer_complete(xfer); 2762 } 2763 2764 /* Close the root pipe. */ 2765 Static void 2766 ehci_root_intr_close(struct usbd_pipe *pipe) 2767 { 2768 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2769 2770 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2771 2772 KASSERT(mutex_owned(&sc->sc_lock)); 2773 2774 /* 2775 * Caller must guarantee the xfer has completed first, by 2776 * closing the pipe only after normal completion or an abort. 2777 */ 2778 KASSERT(sc->sc_intrxfer == NULL); 2779 } 2780 2781 Static void 2782 ehci_root_intr_done(struct usbd_xfer *xfer) 2783 { 2784 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2785 2786 KASSERT(mutex_owned(&sc->sc_lock)); 2787 2788 /* Claim the xfer so it doesn't get completed again. */ 2789 KASSERT(sc->sc_intrxfer == xfer); 2790 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2791 sc->sc_intrxfer = NULL; 2792 } 2793 2794 /************************/ 2795 2796 Static ehci_soft_qh_t * 2797 ehci_alloc_sqh(ehci_softc_t *sc) 2798 { 2799 ehci_soft_qh_t *sqh; 2800 usbd_status err; 2801 int i, offs; 2802 usb_dma_t dma; 2803 2804 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2805 2806 mutex_enter(&sc->sc_lock); 2807 if (sc->sc_freeqhs == NULL) { 2808 DPRINTF("allocating chunk", 0, 0, 0, 0); 2809 mutex_exit(&sc->sc_lock); 2810 2811 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2812 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2813 #ifdef EHCI_DEBUG 2814 if (err) 2815 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2816 #endif 2817 if (err) 2818 return NULL; 2819 2820 mutex_enter(&sc->sc_lock); 2821 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2822 offs = i * EHCI_SQH_SIZE; 2823 sqh = KERNADDR(&dma, offs); 2824 sqh->physaddr = DMAADDR(&dma, offs); 2825 sqh->dma = dma; 2826 sqh->offs = offs; 2827 sqh->next = sc->sc_freeqhs; 2828 sc->sc_freeqhs = sqh; 2829 } 2830 } 2831 sqh = sc->sc_freeqhs; 2832 sc->sc_freeqhs = sqh->next; 2833 mutex_exit(&sc->sc_lock); 2834 2835 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2836 sqh->next = NULL; 2837 return sqh; 2838 } 2839 2840 Static void 2841 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2842 { 2843 KASSERT(mutex_owned(&sc->sc_lock)); 2844 2845 sqh->next = sc->sc_freeqhs; 2846 sc->sc_freeqhs = sqh; 2847 } 2848 2849 Static ehci_soft_qtd_t * 2850 ehci_alloc_sqtd(ehci_softc_t *sc) 2851 { 2852 ehci_soft_qtd_t *sqtd = NULL; 2853 usbd_status err; 2854 int i, offs; 2855 usb_dma_t dma; 2856 2857 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2858 2859 mutex_enter(&sc->sc_lock); 2860 if (sc->sc_freeqtds == NULL) { 2861 DPRINTF("allocating chunk", 0, 0, 0, 0); 2862 mutex_exit(&sc->sc_lock); 2863 2864 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2865 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2866 #ifdef EHCI_DEBUG 2867 if (err) 2868 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2869 #endif 2870 if (err) 2871 goto done; 2872 2873 mutex_enter(&sc->sc_lock); 2874 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2875 offs = i * EHCI_SQTD_SIZE; 2876 sqtd = KERNADDR(&dma, offs); 2877 sqtd->physaddr = DMAADDR(&dma, offs); 2878 sqtd->dma = dma; 2879 sqtd->offs = offs; 2880 2881 sqtd->nextqtd = sc->sc_freeqtds; 2882 sc->sc_freeqtds = sqtd; 2883 } 2884 } 2885 2886 sqtd = sc->sc_freeqtds; 2887 sc->sc_freeqtds = sqtd->nextqtd; 2888 mutex_exit(&sc->sc_lock); 2889 2890 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2891 sqtd->nextqtd = NULL; 2892 sqtd->xfer = NULL; 2893 2894 done: 2895 return sqtd; 2896 } 2897 2898 Static void 2899 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2900 { 2901 2902 mutex_enter(&sc->sc_lock); 2903 sqtd->nextqtd = sc->sc_freeqtds; 2904 sc->sc_freeqtds = sqtd; 2905 mutex_exit(&sc->sc_lock); 2906 } 2907 2908 Static int 2909 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2910 int alen, int rd, ehci_soft_qtd_t **sp) 2911 { 2912 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2913 uint16_t flags = xfer->ux_flags; 2914 2915 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2916 2917 ASSERT_SLEEPABLE(); 2918 KASSERT(sp); 2919 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2920 2921 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2922 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 2923 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2924 KM_SLEEP); 2925 exfer->ex_nsqtd = nsqtd; 2926 2927 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2928 alen, nsqtd, flags); 2929 2930 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2931 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2932 if (cur == NULL) 2933 goto nomem; 2934 exfer->ex_sqtds[j++] = cur; 2935 2936 cur->xfer = xfer; 2937 cur->len = 0; 2938 2939 } 2940 2941 *sp = exfer->ex_sqtds[0]; 2942 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2943 2944 return 0; 2945 2946 nomem: 2947 ehci_free_sqtds(sc, exfer); 2948 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2949 DPRINTF("no memory", 0, 0, 0, 0); 2950 return ENOMEM; 2951 } 2952 2953 Static void 2954 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2955 { 2956 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2957 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2958 2959 mutex_enter(&sc->sc_lock); 2960 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2961 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2962 2963 if (sqtd == NULL) 2964 break; 2965 2966 sqtd->nextqtd = sc->sc_freeqtds; 2967 sc->sc_freeqtds = sqtd; 2968 } 2969 mutex_exit(&sc->sc_lock); 2970 } 2971 2972 Static void 2973 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2974 { 2975 if (prev) { 2976 prev->nextqtd = sqtd; 2977 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2978 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2979 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2980 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2981 } 2982 } 2983 2984 Static void 2985 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2986 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2987 { 2988 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2989 usb_dma_t *dma = &xfer->ux_dmabuf; 2990 uint16_t flags = xfer->ux_flags; 2991 ehci_soft_qtd_t *sqtd, *prev; 2992 int tog = *toggle; 2993 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2994 int len = length; 2995 2996 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2997 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2998 len, isread, tog); 2999 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 3000 0, 0, 0); 3001 3002 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 3003 3004 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3005 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3006 EHCI_QTD_SET_CERR(3) 3007 ; 3008 3009 sqtd = prev = NULL; 3010 size_t curoffs = 0; 3011 size_t j = 0; 3012 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3013 sqtd = exfer->ex_sqtds[j++]; 3014 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3015 (uintptr_t)prev, 0); 3016 3017 /* 3018 * The EHCI hardware can handle at most 5 pages and they do 3019 * not have to be contiguous 3020 */ 3021 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3022 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3023 size_t curlen = len; 3024 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3025 /* must use multiple TDs, fill as much as possible. */ 3026 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3027 3028 /* the length must be a multiple of the max size */ 3029 curlen -= curlen % mps; 3030 } 3031 KASSERT(curlen != 0); 3032 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3033 curoffs, 0); 3034 3035 /* Fill the qTD */ 3036 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3037 sqtd->qtd.qtd_status = htole32( 3038 qtdstatus | 3039 EHCI_QTD_SET_BYTES(curlen) | 3040 EHCI_QTD_SET_TOGGLE(tog)); 3041 3042 /* Find number of pages we'll be using, insert dma addresses */ 3043 size_t pages = EHCI_NPAGES(curlen); 3044 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3045 size_t pageoffs = EHCI_PAGE(curoffs); 3046 for (size_t i = 0; i < pages; i++) { 3047 paddr_t a = DMAADDR(dma, 3048 pageoffs + i * EHCI_PAGE_SIZE); 3049 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 3050 /* Cast up to avoid compiler warnings */ 3051 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 3052 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3053 i, pages, 3054 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3055 le32toh(sqtd->qtd.qtd_buffer[i])); 3056 } 3057 /* First buffer pointer requires a page offset to start at */ 3058 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3059 3060 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3061 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3062 3063 sqtd->len = curlen; 3064 3065 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3066 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3067 3068 ehci_append_sqtd(sqtd, prev); 3069 3070 if (howmany(curlen, mps) & 1) { 3071 tog ^= 1; 3072 } 3073 3074 curoffs += curlen; 3075 len -= curlen; 3076 } 3077 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3078 xfer, length, len, mps, exfer->ex_nsqtd, j); 3079 3080 if (!isread && 3081 (flags & USBD_FORCE_SHORT_XFER) && 3082 length % mps == 0) { 3083 /* Force a 0 length transfer at the end. */ 3084 3085 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3086 exfer->ex_nsqtd); 3087 prev = sqtd; 3088 sqtd = exfer->ex_sqtds[j++]; 3089 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3090 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3091 sqtd->qtd.qtd_status = htole32( 3092 qtdstatus | 3093 EHCI_QTD_SET_BYTES(0) | 3094 EHCI_QTD_SET_TOGGLE(tog)); 3095 3096 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3097 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3098 3099 ehci_append_sqtd(sqtd, prev); 3100 tog ^= 1; 3101 } 3102 3103 *lsqtd = sqtd; 3104 *toggle = tog; 3105 } 3106 3107 Static ehci_soft_itd_t * 3108 ehci_alloc_itd(ehci_softc_t *sc) 3109 { 3110 struct ehci_soft_itd *itd, *freeitd; 3111 usbd_status err; 3112 usb_dma_t dma; 3113 3114 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3115 3116 mutex_enter(&sc->sc_lock); 3117 3118 freeitd = LIST_FIRST(&sc->sc_freeitds); 3119 if (freeitd == NULL) { 3120 DPRINTF("allocating chunk", 0, 0, 0, 0); 3121 mutex_exit(&sc->sc_lock); 3122 3123 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3124 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3125 3126 if (err) { 3127 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3128 return NULL; 3129 } 3130 mutex_enter(&sc->sc_lock); 3131 3132 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3133 int offs = i * EHCI_ITD_SIZE; 3134 itd = KERNADDR(&dma, offs); 3135 itd->physaddr = DMAADDR(&dma, offs); 3136 itd->dma = dma; 3137 itd->offs = offs; 3138 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3139 } 3140 freeitd = LIST_FIRST(&sc->sc_freeitds); 3141 } 3142 3143 itd = freeitd; 3144 LIST_REMOVE(itd, free_list); 3145 mutex_exit(&sc->sc_lock); 3146 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3147 3148 itd->frame_list.next = NULL; 3149 itd->frame_list.prev = NULL; 3150 itd->xfer_next = NULL; 3151 itd->slot = 0; 3152 3153 return itd; 3154 } 3155 3156 Static ehci_soft_sitd_t * 3157 ehci_alloc_sitd(ehci_softc_t *sc) 3158 { 3159 struct ehci_soft_sitd *sitd, *freesitd; 3160 usbd_status err; 3161 int i, offs; 3162 usb_dma_t dma; 3163 3164 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3165 3166 mutex_enter(&sc->sc_lock); 3167 freesitd = LIST_FIRST(&sc->sc_freesitds); 3168 if (freesitd == NULL) { 3169 DPRINTF("allocating chunk", 0, 0, 0, 0); 3170 mutex_exit(&sc->sc_lock); 3171 3172 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3173 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3174 3175 if (err) { 3176 DPRINTF("alloc returned %jd", err, 0, 0, 3177 0); 3178 return NULL; 3179 } 3180 3181 mutex_enter(&sc->sc_lock); 3182 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3183 offs = i * EHCI_SITD_SIZE; 3184 sitd = KERNADDR(&dma, offs); 3185 sitd->physaddr = DMAADDR(&dma, offs); 3186 sitd->dma = dma; 3187 sitd->offs = offs; 3188 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3189 } 3190 freesitd = LIST_FIRST(&sc->sc_freesitds); 3191 } 3192 3193 sitd = freesitd; 3194 LIST_REMOVE(sitd, free_list); 3195 mutex_exit(&sc->sc_lock); 3196 3197 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3198 3199 sitd->frame_list.next = NULL; 3200 sitd->frame_list.prev = NULL; 3201 sitd->xfer_next = NULL; 3202 sitd->slot = 0; 3203 3204 return sitd; 3205 } 3206 3207 /****************/ 3208 3209 /* 3210 * Close a reqular pipe. 3211 * Assumes that there are no pending transactions. 3212 */ 3213 Static void 3214 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3215 { 3216 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3217 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3218 ehci_soft_qh_t *sqh = epipe->sqh; 3219 3220 KASSERT(mutex_owned(&sc->sc_lock)); 3221 3222 ehci_rem_qh(sc, sqh, head); 3223 ehci_free_sqh(sc, epipe->sqh); 3224 } 3225 3226 /* 3227 * Arrrange for the hardware to tells us that it is not still 3228 * processing the TDs by setting the QH halted bit and wait for the ehci 3229 * door bell 3230 */ 3231 Static void 3232 ehci_abortx(struct usbd_xfer *xfer) 3233 { 3234 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3235 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3236 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3237 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3238 ehci_soft_qh_t *sqh = epipe->sqh; 3239 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3240 ehci_physaddr_t cur; 3241 uint32_t qhstatus; 3242 int hit; 3243 3244 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3245 3246 KASSERT(mutex_owned(&sc->sc_lock)); 3247 ASSERT_SLEEPABLE(); 3248 3249 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3250 xfer->ux_status == USBD_TIMEOUT), 3251 "bad abort status: %d", xfer->ux_status); 3252 3253 /* 3254 * If we're dying, skip the hardware action and just notify the 3255 * software that we're done. 3256 */ 3257 if (sc->sc_dying) { 3258 goto dying; 3259 } 3260 3261 /* 3262 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3263 */ 3264 ehci_del_intr_list(sc, exfer); 3265 3266 usb_syncmem(&sqh->dma, 3267 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3268 sizeof(sqh->qh.qh_qtd.qtd_status), 3269 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3270 qhstatus = sqh->qh.qh_qtd.qtd_status; 3271 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3272 usb_syncmem(&sqh->dma, 3273 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3274 sizeof(sqh->qh.qh_qtd.qtd_status), 3275 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3276 3277 if (exfer->ex_type == EX_CTRL) { 3278 fsqtd = exfer->ex_setup; 3279 lsqtd = exfer->ex_status; 3280 } else { 3281 fsqtd = exfer->ex_sqtdstart; 3282 lsqtd = exfer->ex_sqtdend; 3283 } 3284 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3285 usb_syncmem(&sqtd->dma, 3286 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3287 sizeof(sqtd->qtd.qtd_status), 3288 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3289 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3290 usb_syncmem(&sqtd->dma, 3291 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3292 sizeof(sqtd->qtd.qtd_status), 3293 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3294 if (sqtd == lsqtd) 3295 break; 3296 } 3297 3298 /* 3299 * HC Step 2: Wait until we know hardware has finished any possible 3300 * use of the xfer. 3301 */ 3302 ehci_sync_hc(sc); 3303 3304 /* 3305 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3306 * The complication here is that the hardware may have executed 3307 * beyond the xfer we're trying to abort. So as we're scanning 3308 * the TDs of this xfer we check if the hardware points to 3309 * any of them. 3310 */ 3311 3312 usb_syncmem(&sqh->dma, 3313 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3314 sizeof(sqh->qh.qh_curqtd), 3315 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3316 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3317 hit = 0; 3318 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3319 hit |= cur == sqtd->physaddr; 3320 if (sqtd == lsqtd) 3321 break; 3322 } 3323 sqtd = sqtd->nextqtd; 3324 /* Zap curqtd register if hardware pointed inside the xfer. */ 3325 if (hit && sqtd != NULL) { 3326 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3327 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3328 usb_syncmem(&sqh->dma, 3329 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3330 sizeof(sqh->qh.qh_curqtd), 3331 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3332 sqh->qh.qh_qtd.qtd_status = qhstatus; 3333 usb_syncmem(&sqh->dma, 3334 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3335 sizeof(sqh->qh.qh_qtd.qtd_status), 3336 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3337 } else { 3338 DPRINTF("no hit", 0, 0, 0, 0); 3339 usb_syncmem(&sqh->dma, 3340 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3341 sizeof(sqh->qh.qh_curqtd), 3342 BUS_DMASYNC_PREREAD); 3343 } 3344 3345 /* 3346 * Final step: Notify completion to waiting xfers. 3347 */ 3348 dying: 3349 #ifdef DIAGNOSTIC 3350 exfer->ex_isdone = true; 3351 #endif 3352 usb_transfer_complete(xfer); 3353 DPRINTFN(14, "end", 0, 0, 0, 0); 3354 3355 KASSERT(mutex_owned(&sc->sc_lock)); 3356 } 3357 3358 Static void 3359 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3360 { 3361 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3362 ehci_isoc_trans_t trans_status; 3363 struct ehci_xfer *exfer; 3364 ehci_softc_t *sc; 3365 struct ehci_soft_itd *itd; 3366 struct ehci_soft_sitd *sitd; 3367 int i; 3368 3369 KASSERTMSG(status == USBD_CANCELLED, 3370 "invalid status for abort: %d", (int)status); 3371 3372 exfer = EHCI_XFER2EXFER(xfer); 3373 sc = EHCI_XFER2SC(xfer); 3374 3375 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3376 (uintptr_t)xfer->ux_pipe, 0, 0); 3377 3378 KASSERT(mutex_owned(&sc->sc_lock)); 3379 ASSERT_SLEEPABLE(); 3380 3381 /* No timeout or task here. */ 3382 3383 /* 3384 * The xfer cannot have been cancelled already. It is the 3385 * responsibility of the caller of usbd_abort_pipe not to try 3386 * to abort a pipe multiple times, whether concurrently or 3387 * sequentially. 3388 */ 3389 KASSERT(xfer->ux_status != USBD_CANCELLED); 3390 3391 /* If anyone else beat us, we're done. */ 3392 if (xfer->ux_status != USBD_IN_PROGRESS) 3393 return; 3394 3395 /* We beat everyone else. Claim the status. */ 3396 xfer->ux_status = status; 3397 3398 /* 3399 * If we're dying, skip the hardware action and just notify the 3400 * software that we're done. 3401 */ 3402 if (sc->sc_dying) { 3403 goto dying; 3404 } 3405 3406 /* 3407 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3408 */ 3409 ehci_del_intr_list(sc, exfer); 3410 3411 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3412 for (itd = exfer->ex_itdstart; itd != NULL; 3413 itd = itd->xfer_next) { 3414 usb_syncmem(&itd->dma, 3415 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3416 sizeof(itd->itd.itd_ctl), 3417 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3418 3419 for (i = 0; i < 8; i++) { 3420 trans_status = le32toh(itd->itd.itd_ctl[i]); 3421 trans_status &= ~EHCI_ITD_ACTIVE; 3422 itd->itd.itd_ctl[i] = htole32(trans_status); 3423 } 3424 3425 usb_syncmem(&itd->dma, 3426 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3427 sizeof(itd->itd.itd_ctl), 3428 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3429 } 3430 } else { 3431 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3432 sitd = sitd->xfer_next) { 3433 usb_syncmem(&sitd->dma, 3434 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3435 sizeof(sitd->sitd.sitd_buffer), 3436 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3437 3438 trans_status = le32toh(sitd->sitd.sitd_trans); 3439 trans_status &= ~EHCI_SITD_ACTIVE; 3440 sitd->sitd.sitd_trans = htole32(trans_status); 3441 3442 usb_syncmem(&sitd->dma, 3443 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3444 sizeof(sitd->sitd.sitd_buffer), 3445 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3446 } 3447 } 3448 3449 dying: 3450 #ifdef DIAGNOSTIC 3451 exfer->ex_isdone = true; 3452 #endif 3453 usb_transfer_complete(xfer); 3454 DPRINTFN(14, "end", 0, 0, 0, 0); 3455 3456 KASSERT(mutex_owned(&sc->sc_lock)); 3457 } 3458 3459 /************************/ 3460 3461 Static int 3462 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3463 { 3464 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3465 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3466 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3467 usb_device_request_t *req = &xfer->ux_request; 3468 ehci_soft_qtd_t *setup, *status, *next; 3469 int isread = req->bmRequestType & UT_READ; 3470 int len = xfer->ux_bufsize; 3471 int err; 3472 3473 exfer->ex_type = EX_CTRL; 3474 exfer->ex_status = NULL; 3475 exfer->ex_data = NULL; 3476 exfer->ex_setup = ehci_alloc_sqtd(sc); 3477 if (exfer->ex_setup == NULL) { 3478 err = ENOMEM; 3479 goto bad1; 3480 } 3481 exfer->ex_status = ehci_alloc_sqtd(sc); 3482 if (exfer->ex_status == NULL) { 3483 err = ENOMEM; 3484 goto bad2; 3485 } 3486 setup = exfer->ex_setup; 3487 status = exfer->ex_status; 3488 exfer->ex_nsqtd = 0; 3489 next = status; 3490 /* Set up data transaction */ 3491 if (len != 0) { 3492 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3493 &exfer->ex_data); 3494 if (err) 3495 goto bad3; 3496 next = exfer->ex_data; 3497 } 3498 3499 /* Clear toggle */ 3500 setup->qtd.qtd_status = htole32( 3501 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3502 EHCI_QTD_SET_TOGGLE(0) | 3503 EHCI_QTD_SET_BYTES(sizeof(*req)) 3504 ); 3505 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3506 setup->qtd.qtd_buffer_hi[0] = 0; 3507 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3508 setup->nextqtd = next; 3509 setup->xfer = xfer; 3510 setup->len = sizeof(*req); 3511 3512 status->qtd.qtd_status = htole32( 3513 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3514 EHCI_QTD_SET_TOGGLE(1) | 3515 EHCI_QTD_IOC 3516 ); 3517 status->qtd.qtd_buffer[0] = 0; 3518 status->qtd.qtd_buffer_hi[0] = 0; 3519 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3520 status->nextqtd = NULL; 3521 status->xfer = xfer; 3522 status->len = 0; 3523 3524 return 0; 3525 bad3: 3526 ehci_free_sqtd(sc, exfer->ex_status); 3527 bad2: 3528 ehci_free_sqtd(sc, exfer->ex_setup); 3529 bad1: 3530 return err; 3531 } 3532 3533 Static void 3534 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3535 { 3536 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3537 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3538 3539 KASSERT(ex->ex_type == EX_CTRL); 3540 3541 ehci_free_sqtd(sc, ex->ex_setup); 3542 ehci_free_sqtd(sc, ex->ex_status); 3543 ehci_free_sqtds(sc, ex); 3544 if (ex->ex_nsqtd) 3545 kmem_free(ex->ex_sqtds, 3546 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3547 } 3548 3549 Static usbd_status 3550 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3551 { 3552 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3553 usbd_status err; 3554 3555 /* Insert last in queue. */ 3556 mutex_enter(&sc->sc_lock); 3557 err = usb_insert_transfer(xfer); 3558 mutex_exit(&sc->sc_lock); 3559 if (err) 3560 return err; 3561 3562 /* Pipe isn't running, start first */ 3563 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3564 } 3565 3566 Static usbd_status 3567 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3568 { 3569 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3570 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3571 usb_device_request_t *req = &xfer->ux_request; 3572 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3573 ehci_soft_qtd_t *setup, *status, *next; 3574 ehci_soft_qh_t *sqh; 3575 const bool polling = sc->sc_bus.ub_usepolling; 3576 3577 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3578 3579 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3580 3581 if (sc->sc_dying) 3582 return USBD_IOERROR; 3583 3584 const int isread = req->bmRequestType & UT_READ; 3585 const int len = UGETW(req->wLength); 3586 3587 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3588 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3589 UGETW(req->wIndex)); 3590 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3591 len, epipe->pipe.up_dev->ud_addr, 3592 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3593 3594 sqh = epipe->sqh; 3595 3596 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3597 "address QH %" __PRIuBIT " pipe %d\n", 3598 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3599 epipe->pipe.up_dev->ud_addr); 3600 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3601 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3602 "MPS QH %" __PRIuBIT " pipe %d\n", 3603 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3604 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3605 3606 setup = exfer->ex_setup; 3607 status = exfer->ex_status; 3608 3609 DPRINTF("setup %#jx status %#jx data %#jx", 3610 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3611 KASSERTMSG(setup != NULL && status != NULL, 3612 "Failed memory allocation, setup %p status %p", 3613 setup, status); 3614 3615 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3616 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3617 3618 /* Clear toggle */ 3619 setup->qtd.qtd_status &= ~htole32( 3620 EHCI_QTD_STATUS_MASK | 3621 EHCI_QTD_BYTES_MASK | 3622 EHCI_QTD_TOGGLE_MASK | 3623 EHCI_QTD_CERR_MASK 3624 ); 3625 setup->qtd.qtd_status |= htole32( 3626 EHCI_QTD_ACTIVE | 3627 EHCI_QTD_SET_CERR(3) | 3628 EHCI_QTD_SET_TOGGLE(0) | 3629 EHCI_QTD_SET_BYTES(sizeof(*req)) 3630 ); 3631 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3632 setup->qtd.qtd_buffer_hi[0] = 0; 3633 3634 next = status; 3635 status->qtd.qtd_status &= ~htole32( 3636 EHCI_QTD_STATUS_MASK | 3637 EHCI_QTD_PID_MASK | 3638 EHCI_QTD_BYTES_MASK | 3639 EHCI_QTD_TOGGLE_MASK | 3640 EHCI_QTD_CERR_MASK 3641 ); 3642 status->qtd.qtd_status |= htole32( 3643 EHCI_QTD_ACTIVE | 3644 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3645 EHCI_QTD_SET_CERR(3) | 3646 EHCI_QTD_SET_TOGGLE(1) | 3647 EHCI_QTD_SET_BYTES(0) | 3648 EHCI_QTD_IOC 3649 ); 3650 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3651 3652 KASSERT(exfer->ex_isdone); 3653 #ifdef DIAGNOSTIC 3654 exfer->ex_isdone = false; 3655 #endif 3656 3657 /* Set up data transaction */ 3658 if (len != 0) { 3659 ehci_soft_qtd_t *end; 3660 3661 /* Start toggle at 1. */ 3662 int toggle = 1; 3663 next = exfer->ex_data; 3664 KASSERTMSG(next != NULL, "Failed memory allocation"); 3665 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3666 end->nextqtd = status; 3667 end->qtd.qtd_next = end->qtd.qtd_altnext = 3668 htole32(status->physaddr); 3669 3670 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3671 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3672 3673 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3674 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3675 } 3676 3677 setup->nextqtd = next; 3678 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3679 3680 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3681 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3682 3683 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3684 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3685 3686 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3687 3688 #ifdef EHCI_DEBUG 3689 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3690 ehci_dump_sqh(sqh); 3691 ehci_dump_sqtds(setup); 3692 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3693 #endif 3694 3695 if (!polling) 3696 mutex_enter(&sc->sc_lock); 3697 3698 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3699 ehci_set_qh_qtd(sqh, setup); 3700 usbd_xfer_schedule_timeout(xfer); 3701 ehci_add_intr_list(sc, exfer); 3702 xfer->ux_status = USBD_IN_PROGRESS; 3703 if (!polling) 3704 mutex_exit(&sc->sc_lock); 3705 3706 #if 0 3707 #ifdef EHCI_DEBUG 3708 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3709 // delay(10000); 3710 ehci_dump_regs(sc); 3711 ehci_dump_sqh(sc->sc_async_head); 3712 ehci_dump_sqh(sqh); 3713 ehci_dump_sqtds(setup); 3714 #endif 3715 #endif 3716 3717 return USBD_IN_PROGRESS; 3718 } 3719 3720 Static void 3721 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3722 { 3723 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3724 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3725 usb_device_request_t *req = &xfer->ux_request; 3726 int len = UGETW(req->wLength); 3727 int rd = req->bmRequestType & UT_READ; 3728 3729 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3730 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3731 3732 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3733 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3734 3735 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3736 BUS_DMASYNC_POSTWRITE); 3737 if (len) 3738 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3739 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3740 3741 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3742 } 3743 3744 /* Abort a device control request. */ 3745 Static void 3746 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3747 { 3748 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3749 3750 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3751 usbd_xfer_abort(xfer); 3752 } 3753 3754 /* Close a device control pipe. */ 3755 Static void 3756 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3757 { 3758 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3759 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3760 3761 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3762 3763 KASSERT(mutex_owned(&sc->sc_lock)); 3764 3765 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3766 3767 ehci_close_pipe(pipe, sc->sc_async_head); 3768 3769 usb_freemem(&sc->sc_bus, &epipe->ctrl.reqdma); 3770 } 3771 3772 /* 3773 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3774 * qTD status, or miss signalling occasionally under heavy load. If the host 3775 * machine is too fast, we we can miss transaction completion - when we scan 3776 * the active list the transaction still seems to be active. This generally 3777 * exhibits itself as a umass stall that never recovers. 3778 * 3779 * We work around this behaviour by setting up this callback after any softintr 3780 * that completes with transactions still pending, giving us another chance to 3781 * check for completion after the writeback has taken place. 3782 */ 3783 Static void 3784 ehci_intrlist_timeout(void *arg) 3785 { 3786 ehci_softc_t *sc = arg; 3787 3788 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3789 3790 usb_schedsoftintr(&sc->sc_bus); 3791 } 3792 3793 /************************/ 3794 3795 Static int 3796 ehci_device_bulk_init(struct usbd_xfer *xfer) 3797 { 3798 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3799 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3800 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3801 int endpt = ed->bEndpointAddress; 3802 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3803 int len = xfer->ux_bufsize; 3804 int err = 0; 3805 3806 exfer->ex_type = EX_BULK; 3807 exfer->ex_nsqtd = 0; 3808 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3809 &exfer->ex_sqtdstart); 3810 3811 return err; 3812 } 3813 3814 Static void 3815 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3816 { 3817 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3818 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3819 3820 KASSERT(ex->ex_type == EX_BULK); 3821 3822 ehci_free_sqtds(sc, ex); 3823 if (ex->ex_nsqtd) 3824 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3825 } 3826 3827 Static usbd_status 3828 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3829 { 3830 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3831 usbd_status err; 3832 3833 /* Insert last in queue. */ 3834 mutex_enter(&sc->sc_lock); 3835 err = usb_insert_transfer(xfer); 3836 mutex_exit(&sc->sc_lock); 3837 if (err) 3838 return err; 3839 3840 /* Pipe isn't running, start first */ 3841 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3842 } 3843 3844 Static usbd_status 3845 ehci_device_bulk_start(struct usbd_xfer *xfer) 3846 { 3847 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3848 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3849 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3850 ehci_soft_qh_t *sqh; 3851 ehci_soft_qtd_t *end; 3852 int len, isread, endpt; 3853 const bool polling = sc->sc_bus.ub_usepolling; 3854 3855 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3856 3857 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3858 xfer->ux_flags, 0); 3859 3860 if (sc->sc_dying) 3861 return USBD_IOERROR; 3862 3863 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3864 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3865 3866 len = xfer->ux_length; 3867 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3868 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3869 sqh = epipe->sqh; 3870 3871 KASSERT(exfer->ex_isdone); 3872 #ifdef DIAGNOSTIC 3873 exfer->ex_isdone = false; 3874 #endif 3875 3876 /* Take lock here to protect nexttoggle */ 3877 if (!polling) 3878 mutex_enter(&sc->sc_lock); 3879 3880 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3881 3882 exfer->ex_sqtdend = end; 3883 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3884 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3885 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3886 3887 #ifdef EHCI_DEBUG 3888 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3889 ehci_dump_sqh(sqh); 3890 ehci_dump_sqtds(exfer->ex_sqtdstart); 3891 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3892 #endif 3893 3894 if (xfer->ux_length) 3895 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3896 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3897 3898 /* also does usb_syncmem(sqh) */ 3899 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3900 usbd_xfer_schedule_timeout(xfer); 3901 ehci_add_intr_list(sc, exfer); 3902 xfer->ux_status = USBD_IN_PROGRESS; 3903 if (!polling) 3904 mutex_exit(&sc->sc_lock); 3905 3906 #if 0 3907 #ifdef EHCI_DEBUG 3908 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3909 // delay(10000); 3910 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3911 ehci_dump_regs(sc); 3912 #if 0 3913 printf("async_head:\n"); 3914 ehci_dump_sqh(sc->sc_async_head); 3915 #endif 3916 DPRINTF("sqh:", 0, 0, 0, 0); 3917 ehci_dump_sqh(sqh); 3918 ehci_dump_sqtds(exfer->ex_sqtdstart); 3919 #endif 3920 #endif 3921 3922 return USBD_IN_PROGRESS; 3923 } 3924 3925 Static void 3926 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3927 { 3928 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3929 3930 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3931 usbd_xfer_abort(xfer); 3932 } 3933 3934 /* 3935 * Close a device bulk pipe. 3936 */ 3937 Static void 3938 ehci_device_bulk_close(struct usbd_pipe *pipe) 3939 { 3940 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3941 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3942 3943 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3944 3945 KASSERT(mutex_owned(&sc->sc_lock)); 3946 3947 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3948 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3949 ehci_close_pipe(pipe, sc->sc_async_head); 3950 } 3951 3952 Static void 3953 ehci_device_bulk_done(struct usbd_xfer *xfer) 3954 { 3955 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3956 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3957 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3958 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3959 3960 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3961 3962 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 3963 3964 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3965 3966 if (xfer->ux_length) 3967 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3968 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3969 3970 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3971 } 3972 3973 /************************/ 3974 3975 Static usbd_status 3976 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3977 { 3978 struct ehci_soft_islot *isp; 3979 int islot, lev; 3980 3981 /* Find a poll rate that is large enough. */ 3982 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3983 if (EHCI_ILEV_IVAL(lev) <= ival) 3984 break; 3985 3986 /* Pick an interrupt slot at the right level. */ 3987 /* XXX could do better than picking at random */ 3988 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3989 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3990 3991 sqh->islot = islot; 3992 isp = &sc->sc_islots[islot]; 3993 mutex_enter(&sc->sc_lock); 3994 ehci_add_qh(sc, sqh, isp->sqh); 3995 mutex_exit(&sc->sc_lock); 3996 3997 return USBD_NORMAL_COMPLETION; 3998 } 3999 4000 4001 Static int 4002 ehci_device_intr_init(struct usbd_xfer *xfer) 4003 { 4004 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4005 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4006 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4007 int endpt = ed->bEndpointAddress; 4008 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4009 int len = xfer->ux_bufsize; 4010 int err; 4011 4012 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4013 4014 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4015 xfer->ux_flags, 0); 4016 4017 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4018 KASSERT(len != 0); 4019 4020 exfer->ex_type = EX_INTR; 4021 exfer->ex_nsqtd = 0; 4022 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4023 &exfer->ex_sqtdstart); 4024 4025 return err; 4026 } 4027 4028 Static void 4029 ehci_device_intr_fini(struct usbd_xfer *xfer) 4030 { 4031 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4032 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4033 4034 KASSERT(ex->ex_type == EX_INTR); 4035 4036 ehci_free_sqtds(sc, ex); 4037 if (ex->ex_nsqtd) 4038 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4039 } 4040 4041 Static usbd_status 4042 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4043 { 4044 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4045 usbd_status err; 4046 4047 /* Insert last in queue. */ 4048 mutex_enter(&sc->sc_lock); 4049 err = usb_insert_transfer(xfer); 4050 mutex_exit(&sc->sc_lock); 4051 if (err) 4052 return err; 4053 4054 /* 4055 * Pipe isn't running (otherwise err would be USBD_INPROG), 4056 * so start it first. 4057 */ 4058 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4059 } 4060 4061 Static usbd_status 4062 ehci_device_intr_start(struct usbd_xfer *xfer) 4063 { 4064 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4065 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4066 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4067 ehci_soft_qtd_t *end; 4068 ehci_soft_qh_t *sqh; 4069 int len, isread, endpt; 4070 const bool polling = sc->sc_bus.ub_usepolling; 4071 4072 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4073 4074 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4075 xfer->ux_flags, 0); 4076 4077 if (sc->sc_dying) 4078 return USBD_IOERROR; 4079 4080 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4081 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4082 4083 len = xfer->ux_length; 4084 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4085 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4086 sqh = epipe->sqh; 4087 4088 KASSERT(exfer->ex_isdone); 4089 #ifdef DIAGNOSTIC 4090 exfer->ex_isdone = false; 4091 #endif 4092 4093 /* Take lock to protect nexttoggle */ 4094 if (!polling) 4095 mutex_enter(&sc->sc_lock); 4096 4097 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4098 4099 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4100 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4101 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4102 exfer->ex_sqtdend = end; 4103 4104 #ifdef EHCI_DEBUG 4105 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4106 ehci_dump_sqh(sqh); 4107 ehci_dump_sqtds(exfer->ex_sqtdstart); 4108 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4109 #endif 4110 4111 if (xfer->ux_length) 4112 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4113 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4114 4115 /* also does usb_syncmem(sqh) */ 4116 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4117 usbd_xfer_schedule_timeout(xfer); 4118 ehci_add_intr_list(sc, exfer); 4119 xfer->ux_status = USBD_IN_PROGRESS; 4120 if (!polling) 4121 mutex_exit(&sc->sc_lock); 4122 4123 #if 0 4124 #ifdef EHCI_DEBUG 4125 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4126 // delay(10000); 4127 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4128 ehci_dump_regs(sc); 4129 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4130 ehci_dump_sqh(sqh); 4131 ehci_dump_sqtds(exfer->ex_sqtdstart); 4132 #endif 4133 #endif 4134 4135 return USBD_IN_PROGRESS; 4136 } 4137 4138 Static void 4139 ehci_device_intr_abort(struct usbd_xfer *xfer) 4140 { 4141 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4142 4143 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4144 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4145 4146 /* 4147 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4148 * async doorbell. That's dependent on the async list, wheras 4149 * intr xfers are periodic, should not use this? 4150 */ 4151 usbd_xfer_abort(xfer); 4152 } 4153 4154 Static void 4155 ehci_device_intr_close(struct usbd_pipe *pipe) 4156 { 4157 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4158 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4159 struct ehci_soft_islot *isp; 4160 4161 KASSERT(mutex_owned(&sc->sc_lock)); 4162 4163 isp = &sc->sc_islots[epipe->sqh->islot]; 4164 ehci_close_pipe(pipe, isp->sqh); 4165 } 4166 4167 Static void 4168 ehci_device_intr_done(struct usbd_xfer *xfer) 4169 { 4170 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4171 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4172 4173 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4174 4175 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4176 4177 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4178 4179 if (xfer->ux_length) { 4180 int isread, endpt; 4181 4182 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4183 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4184 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4185 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4186 } 4187 } 4188 4189 /************************/ 4190 Static int 4191 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4192 { 4193 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4194 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4195 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4196 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4197 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4198 int i, k, frames; 4199 u_int huba, dir; 4200 int err; 4201 4202 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4203 4204 start = NULL; 4205 sitd = NULL; 4206 4207 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4208 xfer->ux_flags, 0); 4209 4210 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4211 KASSERT(xfer->ux_nframes != 0); 4212 KASSERT(exfer->ex_isdone); 4213 4214 exfer->ex_type = EX_FS_ISOC; 4215 /* 4216 * Step 1: Allocate and initialize sitds. 4217 */ 4218 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4219 if (i > 16 || i == 0) { 4220 /* Spec page 271 says intervals > 16 are invalid */ 4221 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4222 4223 return EINVAL; 4224 } 4225 4226 frames = xfer->ux_nframes; 4227 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4228 sitd = ehci_alloc_sitd(sc); 4229 if (sitd == NULL) { 4230 err = ENOMEM; 4231 goto fail; 4232 } 4233 4234 if (prev) 4235 prev->xfer_next = sitd; 4236 else 4237 start = sitd; 4238 4239 huba = dev->ud_myhsport->up_parent->ud_addr; 4240 4241 #if 0 4242 if (sc->sc_flags & EHCIF_FREESCALE) { 4243 // Set hub address to 0 if embedded TT is used. 4244 if (huba == sc->sc_addr) 4245 huba = 0; 4246 } 4247 #endif 4248 4249 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4250 dir = UE_GET_DIR(k) ? 1 : 0; 4251 sitd->sitd.sitd_endp = 4252 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4253 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4254 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4255 EHCI_SITD_SET_HUBA(huba) | 4256 EHCI_SITD_SET_DIR(dir)); 4257 4258 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4259 } /* End of frame */ 4260 4261 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4262 4263 stop = sitd; 4264 stop->xfer_next = NULL; 4265 exfer->ex_sitdstart = start; 4266 exfer->ex_sitdend = stop; 4267 4268 return 0; 4269 4270 fail: 4271 mutex_enter(&sc->sc_lock); 4272 ehci_soft_sitd_t *next; 4273 for (sitd = start; sitd; sitd = next) { 4274 next = sitd->xfer_next; 4275 ehci_free_sitd_locked(sc, sitd); 4276 } 4277 mutex_exit(&sc->sc_lock); 4278 4279 return err; 4280 } 4281 4282 Static void 4283 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4284 { 4285 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4286 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4287 4288 KASSERT(ex->ex_type == EX_FS_ISOC); 4289 4290 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4291 } 4292 4293 Static usbd_status 4294 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4295 { 4296 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4297 usbd_status __diagused err; 4298 4299 mutex_enter(&sc->sc_lock); 4300 err = usb_insert_transfer(xfer); 4301 mutex_exit(&sc->sc_lock); 4302 4303 KASSERT(err == USBD_NORMAL_COMPLETION); 4304 4305 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4306 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4307 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4308 ehci_soft_sitd_t *sitd; 4309 usb_dma_t *dma_buf; 4310 int i, j, k, frames; 4311 int offs, total_length; 4312 int frindex; 4313 u_int dir; 4314 4315 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4316 4317 sitd = NULL; 4318 total_length = 0; 4319 4320 4321 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4322 xfer->ux_flags, 0); 4323 4324 if (sc->sc_dying) 4325 return USBD_IOERROR; 4326 4327 /* 4328 * To avoid complication, don't allow a request right now that'll span 4329 * the entire frame table. To within 4 frames, to allow some leeway 4330 * on either side of where the hc currently is. 4331 */ 4332 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4333 xfer->ux_nframes >= sc->sc_flsize - 4) { 4334 printf("ehci: isoc descriptor requested that spans the entire" 4335 "frametable, too many frames\n"); 4336 return USBD_INVAL; 4337 } 4338 4339 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4340 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4341 KASSERT(exfer->ex_isdone); 4342 #ifdef DIAGNOSTIC 4343 exfer->ex_isdone = false; 4344 #endif 4345 4346 /* 4347 * Step 1: Initialize sitds. 4348 */ 4349 4350 frames = xfer->ux_nframes; 4351 dma_buf = &xfer->ux_dmabuf; 4352 offs = 0; 4353 4354 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4355 i++, sitd = sitd->xfer_next) { 4356 KASSERT(sitd != NULL); 4357 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4358 4359 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4360 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4361 4362 /* Set page0 index and offset - TP and T-offset are set below */ 4363 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4364 4365 total_length += xfer->ux_frlengths[i]; 4366 offs += xfer->ux_frlengths[i]; 4367 4368 sitd->sitd.sitd_buffer[1] = 4369 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4370 4371 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4372 4373 #if 0 4374 if (sc->sc_flags & EHCIF_FREESCALE) { 4375 // Set hub address to 0 if embedded TT is used. 4376 if (huba == sc->sc_addr) 4377 huba = 0; 4378 } 4379 #endif 4380 4381 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4382 dir = UE_GET_DIR(k) ? 1 : 0; 4383 KASSERT(sitd->sitd.sitd_endp == htole32( 4384 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4385 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4386 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4387 EHCI_SITD_SET_HUBA(huba) | 4388 EHCI_SITD_SET_DIR(dir))); 4389 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4390 4391 uint8_t sa = 0; 4392 uint8_t sb = 0; 4393 u_int temp, tlen; 4394 4395 if (dir == 0) { /* OUT */ 4396 temp = 0; 4397 tlen = xfer->ux_frlengths[i]; 4398 if (tlen <= 188) { 4399 temp |= 1; /* T-count = 1, TP = ALL */ 4400 tlen = 1; 4401 } else { 4402 tlen += 187; 4403 tlen /= 188; 4404 temp |= tlen; /* T-count = [1..6] */ 4405 temp |= 8; /* TP = Begin */ 4406 } 4407 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4408 4409 tlen += sa; 4410 4411 if (tlen >= 8) { 4412 sb = 0; 4413 } else { 4414 sb = (1 << tlen); 4415 } 4416 4417 sa = (1 << sa); 4418 sa = (sb - sa) & 0x3F; 4419 sb = 0; 4420 } else { 4421 sb = (-(4 << sa)) & 0xFE; 4422 sa = (1 << sa) & 0x3F; 4423 sa = 0x01; 4424 sb = 0xfc; 4425 } 4426 4427 sitd->sitd.sitd_sched = htole32( 4428 EHCI_SITD_SET_SMASK(sa) | 4429 EHCI_SITD_SET_CMASK(sb) 4430 ); 4431 4432 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4433 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4434 } /* End of frame */ 4435 4436 sitd = exfer->ex_sitdend; 4437 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4438 4439 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4440 sizeof(sitd->sitd.sitd_trans), 4441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4442 4443 if (total_length) 4444 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4445 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4446 4447 /* 4448 * Part 2: Transfer descriptors have now been set up, now they must 4449 * be scheduled into the periodic frame list. Erk. Not wanting to 4450 * complicate matters, transfer is denied if the transfer spans 4451 * more than the period frame list. 4452 */ 4453 4454 mutex_enter(&sc->sc_lock); 4455 4456 /* Start inserting frames */ 4457 if (epipe->isoc.cur_xfers > 0) { 4458 frindex = epipe->isoc.next_frame; 4459 } else { 4460 frindex = EOREAD4(sc, EHCI_FRINDEX); 4461 frindex = frindex >> 3; /* Erase microframe index */ 4462 frindex += 2; 4463 } 4464 4465 if (frindex >= sc->sc_flsize) 4466 frindex &= (sc->sc_flsize - 1); 4467 4468 /* Whats the frame interval? */ 4469 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4470 4471 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4472 j++, sitd = sitd->xfer_next) { 4473 KASSERT(sitd); 4474 4475 usb_syncmem(&sc->sc_fldma, 4476 sizeof(ehci_link_t) * frindex, 4477 sizeof(ehci_link_t), 4478 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4479 4480 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4481 if (sitd->sitd.sitd_next == 0) 4482 /* 4483 * FIXME: frindex table gets initialized to NULL 4484 * or EHCI_NULL? 4485 */ 4486 sitd->sitd.sitd_next = EHCI_NULL; 4487 4488 usb_syncmem(&sitd->dma, 4489 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4490 sizeof(ehci_sitd_t), 4491 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4492 4493 sc->sc_flist[frindex] = 4494 htole32(EHCI_LINK_SITD | sitd->physaddr); 4495 4496 usb_syncmem(&sc->sc_fldma, 4497 sizeof(ehci_link_t) * frindex, 4498 sizeof(ehci_link_t), 4499 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4500 4501 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4502 sc->sc_softsitds[frindex] = sitd; 4503 if (sitd->frame_list.next != NULL) 4504 sitd->frame_list.next->frame_list.prev = sitd; 4505 sitd->slot = frindex; 4506 sitd->frame_list.prev = NULL; 4507 4508 frindex += i; 4509 if (frindex >= sc->sc_flsize) 4510 frindex -= sc->sc_flsize; 4511 } 4512 4513 epipe->isoc.cur_xfers++; 4514 epipe->isoc.next_frame = frindex; 4515 4516 ehci_add_intr_list(sc, exfer); 4517 xfer->ux_status = USBD_IN_PROGRESS; 4518 mutex_exit(&sc->sc_lock); 4519 4520 return USBD_IN_PROGRESS; 4521 } 4522 4523 Static void 4524 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4525 { 4526 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4527 4528 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4529 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4530 } 4531 4532 Static void 4533 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4534 { 4535 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4536 4537 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4538 } 4539 4540 Static void 4541 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4542 { 4543 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4544 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4545 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4546 4547 KASSERT(mutex_owned(&sc->sc_lock)); 4548 4549 epipe->isoc.cur_xfers--; 4550 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4551 4552 if (xfer->ux_length) 4553 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4554 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4555 } 4556 4557 4558 /************************/ 4559 4560 4561 Static int 4562 ehci_device_isoc_init(struct usbd_xfer *xfer) 4563 { 4564 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4565 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4566 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4567 ehci_soft_itd_t *itd, *prev, *start, *stop; 4568 int i, j, k; 4569 int frames, ufrperframe; 4570 int err; 4571 4572 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4573 4574 start = NULL; 4575 prev = NULL; 4576 itd = NULL; 4577 4578 KASSERT(xfer->ux_nframes != 0); 4579 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4580 KASSERT(exfer->ex_isdone); 4581 4582 exfer->ex_type = EX_ISOC; 4583 4584 /* 4585 * Step 1: Allocate and initialize itds, how many do we need? 4586 * One per transfer if interval >= 8 microframes, less if we use 4587 * multiple microframes per frame. 4588 */ 4589 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4590 if (i > 16 || i == 0) { 4591 /* Spec page 271 says intervals > 16 are invalid */ 4592 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4593 return USBD_INVAL; 4594 } 4595 4596 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4597 frames = howmany(xfer->ux_nframes, ufrperframe); 4598 4599 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4600 itd = ehci_alloc_itd(sc); 4601 if (itd == NULL) { 4602 err = ENOMEM; 4603 goto fail; 4604 } 4605 4606 if (prev != NULL) { 4607 /* Maybe not as it's updated by the scheduling? */ 4608 prev->itd.itd_next = 4609 htole32(itd->physaddr | EHCI_LINK_ITD); 4610 4611 prev->xfer_next = itd; 4612 } else { 4613 start = itd; 4614 } 4615 4616 /* 4617 * Other special values 4618 */ 4619 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4620 itd->itd.itd_bufr[0] = htole32( 4621 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4622 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4623 4624 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4625 ? 1 : 0; 4626 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4627 itd->itd.itd_bufr[1] |= htole32( 4628 EHCI_ITD_SET_DIR(k) | 4629 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4630 4631 /* FIXME: handle invalid trans - should be done in openpipe */ 4632 itd->itd.itd_bufr[2] |= 4633 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4634 } /* End of frame */ 4635 4636 stop = itd; 4637 stop->xfer_next = NULL; 4638 4639 exfer->ex_itdstart = start; 4640 exfer->ex_itdend = stop; 4641 4642 return 0; 4643 fail: 4644 mutex_enter(&sc->sc_lock); 4645 ehci_soft_itd_t *next; 4646 for (itd = start; itd; itd = next) { 4647 next = itd->xfer_next; 4648 ehci_free_itd_locked(sc, itd); 4649 } 4650 mutex_exit(&sc->sc_lock); 4651 4652 return err; 4653 4654 } 4655 4656 Static void 4657 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4658 { 4659 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4660 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4661 4662 KASSERT(ex->ex_type == EX_ISOC); 4663 4664 ehci_free_itd_chain(sc, ex->ex_itdstart); 4665 } 4666 4667 Static usbd_status 4668 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4669 { 4670 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4671 usbd_status __diagused err; 4672 4673 mutex_enter(&sc->sc_lock); 4674 err = usb_insert_transfer(xfer); 4675 mutex_exit(&sc->sc_lock); 4676 4677 KASSERT(err == USBD_NORMAL_COMPLETION); 4678 4679 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4680 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4681 ehci_soft_itd_t *itd, *prev; 4682 usb_dma_t *dma_buf; 4683 int i, j; 4684 int frames, uframes, ufrperframe; 4685 int trans_count, offs, total_length; 4686 int frindex; 4687 4688 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4689 4690 prev = NULL; 4691 itd = NULL; 4692 trans_count = 0; 4693 total_length = 0; 4694 4695 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4696 4697 if (sc->sc_dying) 4698 return USBD_IOERROR; 4699 4700 /* 4701 * To avoid complication, don't allow a request right now that'll span 4702 * the entire frame table. To within 4 frames, to allow some leeway 4703 * on either side of where the hc currently is. 4704 */ 4705 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4706 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4707 DPRINTF( 4708 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4709 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4710 return USBD_INVAL; 4711 } 4712 4713 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4714 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4715 KASSERT(exfer->ex_isdone); 4716 #ifdef DIAGNOSTIC 4717 exfer->ex_isdone = false; 4718 #endif 4719 4720 /* 4721 * Step 1: Re-Initialize itds 4722 */ 4723 4724 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4725 if (i > 16 || i == 0) { 4726 /* Spec page 271 says intervals > 16 are invalid */ 4727 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4728 return USBD_INVAL; 4729 } 4730 4731 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4732 frames = howmany(xfer->ux_nframes, ufrperframe); 4733 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4734 4735 if (frames == 0) { 4736 DPRINTF("frames == 0", 0, 0, 0, 0); 4737 return USBD_INVAL; 4738 } 4739 4740 dma_buf = &xfer->ux_dmabuf; 4741 offs = 0; 4742 4743 itd = exfer->ex_itdstart; 4744 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4745 int froffs = offs; 4746 4747 if (prev != NULL) { 4748 prev->itd.itd_next = 4749 htole32(itd->physaddr | EHCI_LINK_ITD); 4750 usb_syncmem(&prev->dma, 4751 prev->offs + offsetof(ehci_itd_t, itd_next), 4752 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4753 prev->xfer_next = itd; 4754 } 4755 4756 /* 4757 * Step 1.5, initialize uframes 4758 */ 4759 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4760 /* Calculate which page in the list this starts in */ 4761 int addr = DMAADDR(dma_buf, froffs); 4762 addr = EHCI_PAGE_OFFSET(addr); 4763 addr += (offs - froffs); 4764 addr = EHCI_PAGE(addr); 4765 addr /= EHCI_PAGE_SIZE; 4766 4767 /* 4768 * This gets the initial offset into the first page, 4769 * looks how far further along the current uframe 4770 * offset is. Works out how many pages that is. 4771 */ 4772 4773 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4774 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4775 EHCI_ITD_SET_PG(addr) | 4776 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4777 4778 total_length += xfer->ux_frlengths[trans_count]; 4779 offs += xfer->ux_frlengths[trans_count]; 4780 trans_count++; 4781 4782 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4783 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4784 break; 4785 } 4786 } 4787 4788 /* 4789 * Step 1.75, set buffer pointers. To simplify matters, all 4790 * pointers are filled out for the next 7 hardware pages in 4791 * the dma block, so no need to worry what pages to cover 4792 * and what to not. 4793 */ 4794 4795 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4796 /* 4797 * Don't try to lookup a page that's past the end 4798 * of buffer 4799 */ 4800 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4801 if (page_offs >= dma_buf->udma_block->size) 4802 break; 4803 4804 uint64_t page = DMAADDR(dma_buf, page_offs); 4805 page = EHCI_PAGE(page); 4806 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4807 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4808 } 4809 /* 4810 * Other special values 4811 */ 4812 4813 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4814 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4815 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4816 4817 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4818 ? 1 : 0; 4819 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4820 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4821 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4822 4823 /* FIXME: handle invalid trans */ 4824 itd->itd.itd_bufr[2] |= 4825 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4826 4827 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4828 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4829 4830 prev = itd; 4831 } /* End of frame */ 4832 4833 if (total_length) 4834 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4835 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4836 4837 /* 4838 * Part 2: Transfer descriptors have now been set up, now they must 4839 * be scheduled into the period frame list. Erk. Not wanting to 4840 * complicate matters, transfer is denied if the transfer spans 4841 * more than the period frame list. 4842 */ 4843 4844 mutex_enter(&sc->sc_lock); 4845 4846 /* Start inserting frames */ 4847 if (epipe->isoc.cur_xfers > 0) { 4848 frindex = epipe->isoc.next_frame; 4849 } else { 4850 frindex = EOREAD4(sc, EHCI_FRINDEX); 4851 frindex = frindex >> 3; /* Erase microframe index */ 4852 frindex += 2; 4853 } 4854 4855 if (frindex >= sc->sc_flsize) 4856 frindex &= (sc->sc_flsize - 1); 4857 4858 /* What's the frame interval? */ 4859 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4860 if (i / USB_UFRAMES_PER_FRAME == 0) 4861 i = 1; 4862 else 4863 i /= USB_UFRAMES_PER_FRAME; 4864 4865 itd = exfer->ex_itdstart; 4866 for (j = 0; j < frames; j++) { 4867 KASSERTMSG(itd != NULL, "frame %d\n", j); 4868 4869 usb_syncmem(&sc->sc_fldma, 4870 sizeof(ehci_link_t) * frindex, 4871 sizeof(ehci_link_t), 4872 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4873 4874 itd->itd.itd_next = sc->sc_flist[frindex]; 4875 if (itd->itd.itd_next == 0) 4876 /* 4877 * FIXME: frindex table gets initialized to NULL 4878 * or EHCI_NULL? 4879 */ 4880 itd->itd.itd_next = EHCI_NULL; 4881 4882 usb_syncmem(&itd->dma, 4883 itd->offs + offsetof(ehci_itd_t, itd_next), 4884 sizeof(itd->itd.itd_next), 4885 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4886 4887 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4888 4889 usb_syncmem(&sc->sc_fldma, 4890 sizeof(ehci_link_t) * frindex, 4891 sizeof(ehci_link_t), 4892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4893 4894 itd->frame_list.next = sc->sc_softitds[frindex]; 4895 sc->sc_softitds[frindex] = itd; 4896 if (itd->frame_list.next != NULL) 4897 itd->frame_list.next->frame_list.prev = itd; 4898 itd->slot = frindex; 4899 itd->frame_list.prev = NULL; 4900 4901 frindex += i; 4902 if (frindex >= sc->sc_flsize) 4903 frindex -= sc->sc_flsize; 4904 4905 itd = itd->xfer_next; 4906 } 4907 4908 epipe->isoc.cur_xfers++; 4909 epipe->isoc.next_frame = frindex; 4910 4911 ehci_add_intr_list(sc, exfer); 4912 xfer->ux_status = USBD_IN_PROGRESS; 4913 mutex_exit(&sc->sc_lock); 4914 4915 return USBD_IN_PROGRESS; 4916 } 4917 4918 Static void 4919 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4920 { 4921 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4922 4923 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4924 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4925 } 4926 4927 Static void 4928 ehci_device_isoc_close(struct usbd_pipe *pipe) 4929 { 4930 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4931 4932 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4933 } 4934 4935 Static void 4936 ehci_device_isoc_done(struct usbd_xfer *xfer) 4937 { 4938 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4939 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4940 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4941 4942 KASSERT(mutex_owned(&sc->sc_lock)); 4943 4944 epipe->isoc.cur_xfers--; 4945 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4946 if (xfer->ux_length) 4947 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4948 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4949 } 4950
Indexes created Wed Oct 01 19:09:53 GMT 2025