ehci.c revision 1.259.2.3
1 /* $NetBSD: ehci.c,v 1.259.2.3 2020/04/13 08:04:49 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.259.2.3 2020/04/13 08:04:49 martin Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 #include <sys/reboot.h> 79 80 #include <machine/endian.h> 81 82 #include <dev/usb/usb.h> 83 #include <dev/usb/usbdi.h> 84 #include <dev/usb/usbdivar.h> 85 #include <dev/usb/usbhist.h> 86 #include <dev/usb/usb_mem.h> 87 #include <dev/usb/usb_quirks.h> 88 89 #include <dev/usb/ehcireg.h> 90 #include <dev/usb/ehcivar.h> 91 #include <dev/usb/usbroothub.h> 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static struct usbd_xfer * 174 ehci_allocx(struct usbd_bus *, unsigned int); 175 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 176 177 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 178 Static bool ehci_dying(struct usbd_bus *); 179 Static int ehci_roothub_ctrl(struct usbd_bus *, 180 usb_device_request_t *, void *, int); 181 182 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 183 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 184 Static void ehci_root_intr_abort(struct usbd_xfer *); 185 Static void ehci_root_intr_close(struct usbd_pipe *); 186 Static void ehci_root_intr_done(struct usbd_xfer *); 187 188 Static int ehci_device_ctrl_init(struct usbd_xfer *); 189 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 190 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 192 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 193 Static void ehci_device_ctrl_close(struct usbd_pipe *); 194 Static void ehci_device_ctrl_done(struct usbd_xfer *); 195 196 Static int ehci_device_bulk_init(struct usbd_xfer *); 197 Static void ehci_device_bulk_fini(struct usbd_xfer *); 198 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 200 Static void ehci_device_bulk_abort(struct usbd_xfer *); 201 Static void ehci_device_bulk_close(struct usbd_pipe *); 202 Static void ehci_device_bulk_done(struct usbd_xfer *); 203 204 Static int ehci_device_intr_init(struct usbd_xfer *); 205 Static void ehci_device_intr_fini(struct usbd_xfer *); 206 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 208 Static void ehci_device_intr_abort(struct usbd_xfer *); 209 Static void ehci_device_intr_close(struct usbd_pipe *); 210 Static void ehci_device_intr_done(struct usbd_xfer *); 211 212 Static int ehci_device_isoc_init(struct usbd_xfer *); 213 Static void ehci_device_isoc_fini(struct usbd_xfer *); 214 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 215 Static void ehci_device_isoc_abort(struct usbd_xfer *); 216 Static void ehci_device_isoc_close(struct usbd_pipe *); 217 Static void ehci_device_isoc_done(struct usbd_xfer *); 218 219 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 220 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 221 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 222 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 224 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 225 226 Static void ehci_device_clear_toggle(struct usbd_pipe *); 227 Static void ehci_noop(struct usbd_pipe *); 228 229 Static void ehci_disown(ehci_softc_t *, int, int); 230 231 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 232 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 233 234 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 235 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 236 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 237 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 238 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 239 240 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 241 int, int, int *, ehci_soft_qtd_t **); 242 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 243 244 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 245 Static ehci_soft_sitd_t * 246 ehci_alloc_sitd(ehci_softc_t *); 247 248 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 249 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 250 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 251 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 252 253 static inline void 254 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 255 { 256 257 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 258 } 259 260 static inline void 261 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 262 { 263 264 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 265 } 266 267 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 268 269 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 270 int); 271 272 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 273 ehci_soft_qh_t *); 274 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 275 ehci_soft_qh_t *); 276 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 277 Static void ehci_sync_hc(ehci_softc_t *); 278 279 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 280 Static void ehci_abortx(struct usbd_xfer *); 281 282 #ifdef EHCI_DEBUG 283 Static ehci_softc_t *theehci; 284 void ehci_dump(void); 285 #endif 286 287 #ifdef EHCI_DEBUG 288 Static void ehci_dump_regs(ehci_softc_t *); 289 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 290 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 291 Static void ehci_dump_qtd(ehci_qtd_t *); 292 Static void ehci_dump_sqh(ehci_soft_qh_t *); 293 Static void ehci_dump_sitd(struct ehci_soft_itd *); 294 Static void ehci_dump_itds(ehci_soft_itd_t *); 295 Static void ehci_dump_itd(struct ehci_soft_itd *); 296 Static void ehci_dump_exfer(struct ehci_xfer *); 297 #endif 298 299 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 300 301 static inline void 302 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 303 { 304 305 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 306 } 307 308 static inline void 309 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 310 { 311 312 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 313 } 314 315 Static const struct usbd_bus_methods ehci_bus_methods = { 316 .ubm_open = ehci_open, 317 .ubm_softint = ehci_softintr, 318 .ubm_dopoll = ehci_poll, 319 .ubm_allocx = ehci_allocx, 320 .ubm_freex = ehci_freex, 321 .ubm_abortx = ehci_abortx, 322 .ubm_dying = ehci_dying, 323 .ubm_getlock = ehci_get_lock, 324 .ubm_rhctrl = ehci_roothub_ctrl, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 328 .upm_transfer = ehci_root_intr_transfer, 329 .upm_start = ehci_root_intr_start, 330 .upm_abort = ehci_root_intr_abort, 331 .upm_close = ehci_root_intr_close, 332 .upm_cleartoggle = ehci_noop, 333 .upm_done = ehci_root_intr_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 337 .upm_init = ehci_device_ctrl_init, 338 .upm_fini = ehci_device_ctrl_fini, 339 .upm_transfer = ehci_device_ctrl_transfer, 340 .upm_start = ehci_device_ctrl_start, 341 .upm_abort = ehci_device_ctrl_abort, 342 .upm_close = ehci_device_ctrl_close, 343 .upm_cleartoggle = ehci_noop, 344 .upm_done = ehci_device_ctrl_done, 345 }; 346 347 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 348 .upm_init = ehci_device_intr_init, 349 .upm_fini = ehci_device_intr_fini, 350 .upm_transfer = ehci_device_intr_transfer, 351 .upm_start = ehci_device_intr_start, 352 .upm_abort = ehci_device_intr_abort, 353 .upm_close = ehci_device_intr_close, 354 .upm_cleartoggle = ehci_device_clear_toggle, 355 .upm_done = ehci_device_intr_done, 356 }; 357 358 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 359 .upm_init = ehci_device_bulk_init, 360 .upm_fini = ehci_device_bulk_fini, 361 .upm_transfer = ehci_device_bulk_transfer, 362 .upm_start = ehci_device_bulk_start, 363 .upm_abort = ehci_device_bulk_abort, 364 .upm_close = ehci_device_bulk_close, 365 .upm_cleartoggle = ehci_device_clear_toggle, 366 .upm_done = ehci_device_bulk_done, 367 }; 368 369 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 370 .upm_init = ehci_device_isoc_init, 371 .upm_fini = ehci_device_isoc_fini, 372 .upm_transfer = ehci_device_isoc_transfer, 373 .upm_abort = ehci_device_isoc_abort, 374 .upm_close = ehci_device_isoc_close, 375 .upm_cleartoggle = ehci_noop, 376 .upm_done = ehci_device_isoc_done, 377 }; 378 379 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 380 .upm_init = ehci_device_fs_isoc_init, 381 .upm_fini = ehci_device_fs_isoc_fini, 382 .upm_transfer = ehci_device_fs_isoc_transfer, 383 .upm_abort = ehci_device_fs_isoc_abort, 384 .upm_close = ehci_device_fs_isoc_close, 385 .upm_cleartoggle = ehci_noop, 386 .upm_done = ehci_device_fs_isoc_done, 387 }; 388 389 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 390 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 391 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 392 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 393 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 394 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 395 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 396 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 397 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 398 }; 399 400 int 401 ehci_init(ehci_softc_t *sc) 402 { 403 uint32_t vers, sparams, cparams, hcr; 404 u_int i; 405 usbd_status err; 406 ehci_soft_qh_t *sqh; 407 u_int ncomp; 408 409 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 410 #ifdef EHCI_DEBUG 411 theehci = sc; 412 #endif 413 414 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 415 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 416 cv_init(&sc->sc_doorbell, "ehcidb"); 417 418 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 419 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 420 421 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 422 ehci_doorbell, sc); 423 KASSERT(sc->sc_doorbell_si != NULL); 424 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 425 ehci_pcd, sc); 426 KASSERT(sc->sc_pcd_si != NULL); 427 428 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 429 430 vers = EREAD2(sc, EHCI_HCIVERSION); 431 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 432 vers >> 8, vers & 0xff); 433 434 sparams = EREAD4(sc, EHCI_HCSPARAMS); 435 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 436 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 437 ncomp = EHCI_HCS_N_CC(sparams); 438 if (ncomp != sc->sc_ncomp) { 439 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 440 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 441 #if NOHCI == 0 || NUHCI == 0 442 aprint_error("%s: ohci or uhci probably not configured\n", 443 device_xname(sc->sc_dev)); 444 #endif 445 if (ncomp < sc->sc_ncomp) 446 sc->sc_ncomp = ncomp; 447 } 448 if (sc->sc_ncomp > 0) { 449 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 450 aprint_normal_dev(sc->sc_dev, 451 "%d companion controller%s, %d port%s%s", 452 sc->sc_ncomp, 453 sc->sc_ncomp!=1 ? "s" : "", 454 EHCI_HCS_N_PCC(sparams), 455 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 456 sc->sc_ncomp!=1 ? " each" : ""); 457 if (sc->sc_comps[0]) { 458 aprint_normal(":"); 459 for (i = 0; i < sc->sc_ncomp; i++) 460 aprint_normal(" %s", 461 device_xname(sc->sc_comps[i])); 462 } 463 aprint_normal("\n"); 464 465 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 466 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 467 cv_init(&sc->sc_compcv, "ehciccv"); 468 sc->sc_comp_state = CO_EARLY; 469 } 470 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 471 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 472 473 cparams = EREAD4(sc, EHCI_HCCPARAMS); 474 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 475 476 if (EHCI_HCC_64BIT(cparams)) { 477 /* MUST clear segment register if 64 bit capable. */ 478 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 479 } 480 481 if (cparams & EHCI_HCC_IST_FULLFRAME) { 482 sc->sc_istthreshold = 0; 483 } else { 484 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 485 } 486 487 sc->sc_bus.ub_revision = USBREV_2_0; 488 sc->sc_bus.ub_usedma = true; 489 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 490 491 /* Reset the controller */ 492 DPRINTF("resetting", 0, 0, 0, 0); 493 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 494 usb_delay_ms(&sc->sc_bus, 1); 495 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 496 for (i = 0; i < 100; i++) { 497 usb_delay_ms(&sc->sc_bus, 1); 498 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 499 if (!hcr) 500 break; 501 } 502 if (hcr) { 503 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 504 return EIO; 505 } 506 if (sc->sc_vendor_init) 507 sc->sc_vendor_init(sc); 508 509 /* XXX need proper intr scheduling */ 510 sc->sc_rand = 96; 511 512 /* frame list size at default, read back what we got and use that */ 513 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 514 case 0: sc->sc_flsize = 1024; break; 515 case 1: sc->sc_flsize = 512; break; 516 case 2: sc->sc_flsize = 256; break; 517 case 3: return EIO; 518 } 519 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 520 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 521 if (err) 522 return err; 523 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 524 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 525 526 for (i = 0; i < sc->sc_flsize; i++) { 527 sc->sc_flist[i] = EHCI_NULL; 528 } 529 530 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 531 532 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 533 KM_SLEEP); 534 LIST_INIT(&sc->sc_freeitds); 535 LIST_INIT(&sc->sc_freesitds); 536 TAILQ_INIT(&sc->sc_intrhead); 537 538 /* Set up the bus struct. */ 539 sc->sc_bus.ub_methods = &ehci_bus_methods; 540 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 541 542 sc->sc_eintrs = EHCI_NORMAL_INTRS; 543 544 /* 545 * Allocate the interrupt dummy QHs. These are arranged to give poll 546 * intervals that are powers of 2 times 1ms. 547 */ 548 for (i = 0; i < EHCI_INTRQHS; i++) { 549 sqh = ehci_alloc_sqh(sc); 550 if (sqh == NULL) { 551 err = ENOMEM; 552 goto bad1; 553 } 554 sc->sc_islots[i].sqh = sqh; 555 } 556 for (i = 0; i < EHCI_INTRQHS; i++) { 557 sqh = sc->sc_islots[i].sqh; 558 if (i == 0) { 559 /* The last (1ms) QH terminates. */ 560 sqh->qh.qh_link = EHCI_NULL; 561 sqh->next = NULL; 562 } else { 563 /* Otherwise the next QH has half the poll interval */ 564 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 565 sqh->qh.qh_link = htole32(sqh->next->physaddr | 566 EHCI_LINK_QH); 567 } 568 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 569 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 570 sqh->qh.qh_curqtd = EHCI_NULL; 571 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 572 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 573 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 574 sqh->sqtd = NULL; 575 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 576 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 577 } 578 /* Point the frame list at the last level (128ms). */ 579 for (i = 0; i < sc->sc_flsize; i++) { 580 int j; 581 582 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 583 revbits[i & (EHCI_MAX_POLLRATE-1)]; 584 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 585 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 586 i)].sqh->physaddr); 587 } 588 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 589 BUS_DMASYNC_PREWRITE); 590 591 /* Allocate dummy QH that starts the async list. */ 592 sqh = ehci_alloc_sqh(sc); 593 if (sqh == NULL) { 594 err = ENOMEM; 595 goto bad1; 596 } 597 /* Fill the QH */ 598 sqh->qh.qh_endp = 599 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 600 sqh->qh.qh_link = 601 htole32(sqh->physaddr | EHCI_LINK_QH); 602 sqh->qh.qh_curqtd = EHCI_NULL; 603 sqh->next = NULL; 604 /* Fill the overlay qTD */ 605 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 606 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 607 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 608 sqh->sqtd = NULL; 609 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 611 #ifdef EHCI_DEBUG 612 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 613 ehci_dump_sqh(sqh); 614 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 615 #endif 616 617 /* Point to async list */ 618 sc->sc_async_head = sqh; 619 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 620 621 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 622 623 /* Turn on controller */ 624 EOWRITE4(sc, EHCI_USBCMD, 625 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 626 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 627 EHCI_CMD_ASE | 628 EHCI_CMD_PSE | 629 EHCI_CMD_RS); 630 631 /* Take over port ownership */ 632 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 633 634 for (i = 0; i < 100; i++) { 635 usb_delay_ms(&sc->sc_bus, 1); 636 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 637 if (!hcr) 638 break; 639 } 640 if (hcr) { 641 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 642 return EIO; 643 } 644 645 /* Enable interrupts */ 646 DPRINTF("enabling interrupts", 0, 0, 0, 0); 647 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 648 649 return 0; 650 651 #if 0 652 bad2: 653 ehci_free_sqh(sc, sc->sc_async_head); 654 #endif 655 bad1: 656 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 657 return err; 658 } 659 660 int 661 ehci_intr(void *v) 662 { 663 ehci_softc_t *sc = v; 664 int ret = 0; 665 666 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 667 668 if (sc == NULL) 669 return 0; 670 671 mutex_spin_enter(&sc->sc_intr_lock); 672 673 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 674 goto done; 675 676 /* If we get an interrupt while polling, then just ignore it. */ 677 if (sc->sc_bus.ub_usepolling) { 678 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 679 680 if (intrs) 681 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 682 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 683 goto done; 684 } 685 686 ret = ehci_intr1(sc); 687 688 done: 689 mutex_spin_exit(&sc->sc_intr_lock); 690 return ret; 691 } 692 693 Static int 694 ehci_intr1(ehci_softc_t *sc) 695 { 696 uint32_t intrs, eintrs; 697 698 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 699 700 /* In case the interrupt occurs before initialization has completed. */ 701 if (sc == NULL) { 702 #ifdef DIAGNOSTIC 703 printf("ehci_intr1: sc == NULL\n"); 704 #endif 705 return 0; 706 } 707 708 KASSERT(mutex_owned(&sc->sc_intr_lock)); 709 710 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 711 if (!intrs) 712 return 0; 713 714 eintrs = intrs & sc->sc_eintrs; 715 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 716 EOREAD4(sc, EHCI_USBSTS), eintrs); 717 if (!eintrs) 718 return 0; 719 720 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 721 if (eintrs & EHCI_STS_IAA) { 722 DPRINTF("door bell", 0, 0, 0, 0); 723 kpreempt_disable(); 724 KASSERT(sc->sc_doorbell_si != NULL); 725 softint_schedule(sc->sc_doorbell_si); 726 kpreempt_enable(); 727 eintrs &= ~EHCI_STS_IAA; 728 } 729 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 730 DPRINTF("INT=%jd ERRINT=%jd", 731 eintrs & EHCI_STS_INT ? 1 : 0, 732 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 733 usb_schedsoftintr(&sc->sc_bus); 734 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 735 } 736 if (eintrs & EHCI_STS_HSE) { 737 printf("%s: unrecoverable error, controller halted\n", 738 device_xname(sc->sc_dev)); 739 /* XXX what else */ 740 } 741 if (eintrs & EHCI_STS_PCD) { 742 kpreempt_disable(); 743 KASSERT(sc->sc_pcd_si != NULL); 744 softint_schedule(sc->sc_pcd_si); 745 kpreempt_enable(); 746 eintrs &= ~EHCI_STS_PCD; 747 } 748 749 if (eintrs != 0) { 750 /* Block unprocessed interrupts. */ 751 sc->sc_eintrs &= ~eintrs; 752 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 753 printf("%s: blocking intrs %#x\n", 754 device_xname(sc->sc_dev), eintrs); 755 } 756 757 return 1; 758 } 759 760 Static void 761 ehci_doorbell(void *addr) 762 { 763 ehci_softc_t *sc = addr; 764 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 765 766 mutex_enter(&sc->sc_lock); 767 cv_broadcast(&sc->sc_doorbell); 768 mutex_exit(&sc->sc_lock); 769 } 770 771 Static void 772 ehci_pcd(void *addr) 773 { 774 ehci_softc_t *sc = addr; 775 struct usbd_xfer *xfer; 776 u_char *p; 777 int i, m; 778 779 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 780 781 mutex_enter(&sc->sc_lock); 782 xfer = sc->sc_intrxfer; 783 784 if (xfer == NULL) { 785 /* Just ignore the change. */ 786 goto done; 787 } 788 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 789 790 p = xfer->ux_buf; 791 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 792 memset(p, 0, xfer->ux_length); 793 for (i = 1; i <= m; i++) { 794 /* Pick out CHANGE bits from the status reg. */ 795 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 796 p[i/8] |= 1 << (i%8); 797 if (i % 8 == 7) 798 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 799 } 800 xfer->ux_actlen = xfer->ux_length; 801 xfer->ux_status = USBD_NORMAL_COMPLETION; 802 803 usb_transfer_complete(xfer); 804 805 done: 806 mutex_exit(&sc->sc_lock); 807 } 808 809 Static void 810 ehci_softintr(void *v) 811 { 812 struct usbd_bus *bus = v; 813 ehci_softc_t *sc = EHCI_BUS2SC(bus); 814 struct ehci_xfer *ex, *nextex; 815 816 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 817 818 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 819 820 ex_completeq_t cq; 821 TAILQ_INIT(&cq); 822 823 /* 824 * The only explanation I can think of for why EHCI is as brain dead 825 * as UHCI interrupt-wise is that Intel was involved in both. 826 * An interrupt just tells us that something is done, we have no 827 * clue what, so we need to scan through all active transfers. :-( 828 */ 829 830 /* 831 * ehci_idone will remove transfer from sc->sc_intrhead if it's 832 * complete and add to our cq list 833 * 834 */ 835 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 836 switch (ex->ex_type) { 837 case EX_CTRL: 838 case EX_BULK: 839 case EX_INTR: 840 ehci_check_qh_intr(sc, ex, &cq); 841 break; 842 case EX_ISOC: 843 ehci_check_itd_intr(sc, ex, &cq); 844 break; 845 case EX_FS_ISOC: 846 ehci_check_sitd_intr(sc, ex, &cq); 847 break; 848 default: 849 KASSERT(false); 850 } 851 852 } 853 854 /* 855 * We abuse ex_next for the interrupt and complete lists and 856 * interrupt transfers will get re-added here so use 857 * the _SAFE version of TAILQ_FOREACH. 858 */ 859 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 860 usb_transfer_complete(&ex->ex_xfer); 861 } 862 863 /* Schedule a callout to catch any dropped transactions. */ 864 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 865 !TAILQ_EMPTY(&sc->sc_intrhead)) 866 callout_reset(&sc->sc_tmo_intrlist, 867 hz, ehci_intrlist_timeout, sc); 868 } 869 870 Static void 871 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 872 { 873 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 874 uint32_t status; 875 876 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 877 878 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 879 880 if (ex->ex_type == EX_CTRL) { 881 fsqtd = ex->ex_setup; 882 lsqtd = ex->ex_status; 883 } else { 884 fsqtd = ex->ex_sqtdstart; 885 lsqtd = ex->ex_sqtdend; 886 } 887 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 888 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 889 890 /* 891 * If the last TD is still active we need to check whether there 892 * is an error somewhere in the middle, or whether there was a 893 * short packet (SPD and not ACTIVE). 894 */ 895 usb_syncmem(&lsqtd->dma, 896 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 897 sizeof(lsqtd->qtd.qtd_status), 898 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 899 status = le32toh(lsqtd->qtd.qtd_status); 900 usb_syncmem(&lsqtd->dma, 901 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 902 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 903 if (status & EHCI_QTD_ACTIVE) { 904 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 905 906 /* last qTD has already been checked */ 907 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 908 usb_syncmem(&sqtd->dma, 909 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 910 sizeof(sqtd->qtd.qtd_status), 911 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 912 status = le32toh(sqtd->qtd.qtd_status); 913 usb_syncmem(&sqtd->dma, 914 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 915 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 916 /* If there's an active QTD the xfer isn't done. */ 917 if (status & EHCI_QTD_ACTIVE) 918 break; 919 /* Any kind of error makes the xfer done. */ 920 if (status & EHCI_QTD_HALTED) 921 goto done; 922 /* Handle short packets */ 923 if (EHCI_QTD_GET_BYTES(status) != 0) { 924 /* 925 * If we get here for a control transfer then 926 * we need to let the hardware complete the 927 * status phase. That is, we're not done 928 * quite yet. 929 * 930 * Otherwise, we're done. 931 */ 932 if (ex->ex_type == EX_CTRL) { 933 break; 934 } 935 goto done; 936 } 937 } 938 DPRINTFN(10, "ex=%#jx std=%#jx still active", 939 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 940 #ifdef EHCI_DEBUG 941 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 942 ehci_dump_sqtds(ex->ex_sqtdstart); 943 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 944 #endif 945 return; 946 } 947 done: 948 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 949 ehci_idone(ex, cq); 950 } 951 952 Static void 953 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 954 { 955 ehci_soft_itd_t *itd; 956 int i; 957 958 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 959 960 KASSERT(mutex_owned(&sc->sc_lock)); 961 962 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 963 return; 964 965 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 966 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 967 968 itd = ex->ex_itdend; 969 970 /* 971 * check no active transfers in last itd, meaning we're finished 972 */ 973 974 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 975 sizeof(itd->itd.itd_ctl), 976 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 977 978 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 979 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 980 break; 981 } 982 983 if (i == EHCI_ITD_NUFRAMES) { 984 goto done; /* All 8 descriptors inactive, it's done */ 985 } 986 987 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 988 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 989 990 DPRINTFN(10, "ex %#jx itd %#jx still active", 991 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 992 return; 993 done: 994 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 995 ehci_idone(ex, cq); 996 } 997 998 void 999 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1000 { 1001 ehci_soft_sitd_t *sitd; 1002 1003 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1004 1005 KASSERT(mutex_owned(&sc->sc_lock)); 1006 1007 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1008 return; 1009 1010 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1011 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1012 1013 sitd = ex->ex_sitdend; 1014 1015 /* 1016 * check no active transfers in last sitd, meaning we're finished 1017 */ 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), 1021 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1022 1023 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1024 1025 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1026 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1027 1028 if (active) 1029 return; 1030 1031 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1032 ehci_idone(ex, cq); 1033 } 1034 1035 Static void 1036 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1037 { 1038 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1039 struct usbd_xfer *xfer = &ex->ex_xfer; 1040 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1041 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1042 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1043 uint32_t status = 0, nstatus = 0; 1044 int actlen = 0; 1045 1046 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1047 1048 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1049 1050 /* 1051 * Try to claim this xfer for completion. If it has already 1052 * completed or aborted, drop it on the floor. 1053 */ 1054 if (!usbd_xfer_trycomplete(xfer)) 1055 return; 1056 1057 #ifdef DIAGNOSTIC 1058 #ifdef EHCI_DEBUG 1059 if (ex->ex_isdone) { 1060 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1061 ehci_dump_exfer(ex); 1062 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1063 } 1064 #endif 1065 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1066 ex->ex_type, xfer->ux_status); 1067 ex->ex_isdone = true; 1068 #endif 1069 1070 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1071 (uintptr_t)epipe, 0, 0); 1072 1073 /* The transfer is done, compute actual length and status. */ 1074 if (ex->ex_type == EX_ISOC) { 1075 /* HS isoc transfer */ 1076 1077 struct ehci_soft_itd *itd; 1078 int i, nframes, len, uframes; 1079 1080 nframes = 0; 1081 1082 #ifdef EHCI_DEBUG 1083 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1084 ehci_dump_itds(ex->ex_itdstart); 1085 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1086 #endif 1087 1088 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1089 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1090 1091 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1092 usb_syncmem(&itd->dma, 1093 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1094 sizeof(itd->itd.itd_ctl), 1095 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1096 1097 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1098 /* 1099 * XXX - driver didn't fill in the frame full 1100 * of uframes. This leads to scheduling 1101 * inefficiencies, but working around 1102 * this doubles complexity of tracking 1103 * an xfer. 1104 */ 1105 if (nframes >= xfer->ux_nframes) 1106 break; 1107 1108 status = le32toh(itd->itd.itd_ctl[i]); 1109 len = EHCI_ITD_GET_LEN(status); 1110 if (EHCI_ITD_GET_STATUS(status) != 0) 1111 len = 0; /*No valid data on error*/ 1112 1113 xfer->ux_frlengths[nframes++] = len; 1114 actlen += len; 1115 } 1116 usb_syncmem(&itd->dma, 1117 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1118 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1119 1120 if (nframes >= xfer->ux_nframes) 1121 break; 1122 } 1123 1124 xfer->ux_actlen = actlen; 1125 xfer->ux_status = USBD_NORMAL_COMPLETION; 1126 goto end; 1127 } else if (ex->ex_type == EX_FS_ISOC) { 1128 /* FS isoc transfer */ 1129 struct ehci_soft_sitd *sitd; 1130 int nframes, len; 1131 1132 nframes = 0; 1133 1134 for (sitd = ex->ex_sitdstart; sitd != NULL; 1135 sitd = sitd->xfer_next) { 1136 usb_syncmem(&sitd->dma, 1137 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1138 sizeof(sitd->sitd.sitd_trans), 1139 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1140 1141 /* 1142 * XXX - driver didn't fill in the frame full 1143 * of uframes. This leads to scheduling 1144 * inefficiencies, but working around 1145 * this doubles complexity of tracking 1146 * an xfer. 1147 */ 1148 if (nframes >= xfer->ux_nframes) 1149 break; 1150 1151 status = le32toh(sitd->sitd.sitd_trans); 1152 usb_syncmem(&sitd->dma, 1153 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1154 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1155 1156 len = EHCI_SITD_GET_LEN(status); 1157 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1158 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1159 /* No valid data on error */ 1160 len = xfer->ux_frlengths[nframes]; 1161 } 1162 1163 /* 1164 * frlengths[i]: # of bytes to send 1165 * len: # of bytes host didn't send 1166 */ 1167 xfer->ux_frlengths[nframes] -= len; 1168 /* frlengths[i]: # of bytes host sent */ 1169 actlen += xfer->ux_frlengths[nframes++]; 1170 1171 if (nframes >= xfer->ux_nframes) 1172 break; 1173 } 1174 1175 xfer->ux_actlen = actlen; 1176 xfer->ux_status = USBD_NORMAL_COMPLETION; 1177 goto end; 1178 } 1179 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1180 ex->ex_type == EX_BULK); 1181 1182 /* Continue processing xfers using queue heads */ 1183 if (ex->ex_type == EX_CTRL) { 1184 fsqtd = ex->ex_setup; 1185 lsqtd = ex->ex_status; 1186 } else { 1187 fsqtd = ex->ex_sqtdstart; 1188 lsqtd = ex->ex_sqtdend; 1189 } 1190 #ifdef EHCI_DEBUG 1191 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1192 ehci_dump_sqtds(fsqtd); 1193 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1194 #endif 1195 1196 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1197 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1198 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1199 nstatus = le32toh(sqtd->qtd.qtd_status); 1200 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1201 BUS_DMASYNC_PREREAD); 1202 if (nstatus & EHCI_QTD_ACTIVE) 1203 break; 1204 1205 status = nstatus; 1206 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1207 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1208 } 1209 1210 /* 1211 * If there are left over TDs we need to update the toggle. 1212 * The default pipe doesn't need it since control transfers 1213 * start the toggle at 0 every time. 1214 * For a short transfer we need to update the toggle for the missing 1215 * packets within the qTD. 1216 */ 1217 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1218 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1219 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1220 status, nstatus, 0, 0); 1221 #if 0 1222 ehci_dump_sqh(epipe->sqh); 1223 ehci_dump_sqtds(ex->ex_sqtdstart); 1224 #endif 1225 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1226 } 1227 1228 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1229 status, 0); 1230 xfer->ux_actlen = actlen; 1231 if (status & EHCI_QTD_HALTED) { 1232 #ifdef EHCI_DEBUG 1233 DPRINTF("halted addr=%jd endpt=0x%02jx", 1234 xfer->ux_pipe->up_dev->ud_addr, 1235 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1236 0, 0); 1237 DPRINTF("cerr=%jd pid=%jd", 1238 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1239 0, 0); 1240 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1241 status & EHCI_QTD_ACTIVE ? 1 : 0, 1242 status & EHCI_QTD_HALTED ? 1 : 0, 1243 status & EHCI_QTD_BUFERR ? 1 : 0, 1244 status & EHCI_QTD_BABBLE ? 1 : 0); 1245 1246 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1247 status & EHCI_QTD_XACTERR ? 1 : 0, 1248 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1249 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1250 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1251 1252 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1253 ehci_dump_sqh(epipe->sqh); 1254 ehci_dump_sqtds(ex->ex_sqtdstart); 1255 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1256 #endif 1257 /* low&full speed has an extra error flag */ 1258 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1259 EHCI_QH_SPEED_HIGH) 1260 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1261 else 1262 status &= EHCI_QTD_STATERRS; 1263 if (status == 0) /* no other errors means a stall */ { 1264 xfer->ux_status = USBD_STALLED; 1265 } else { 1266 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1267 } 1268 /* XXX need to reset TT on missed microframe */ 1269 if (status & EHCI_QTD_MISSEDMICRO) { 1270 printf("%s: missed microframe, TT reset not " 1271 "implemented, hub might be inoperational\n", 1272 device_xname(sc->sc_dev)); 1273 } 1274 } else { 1275 xfer->ux_status = USBD_NORMAL_COMPLETION; 1276 } 1277 1278 end: 1279 1280 ehci_del_intr_list(sc, ex); 1281 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1282 1283 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1284 } 1285 1286 Static void 1287 ehci_poll(struct usbd_bus *bus) 1288 { 1289 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1290 1291 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1292 1293 #ifdef EHCI_DEBUG 1294 static int last; 1295 int new; 1296 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1297 if (new != last) { 1298 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1299 last = new; 1300 } 1301 #endif 1302 1303 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1304 mutex_spin_enter(&sc->sc_intr_lock); 1305 ehci_intr1(sc); 1306 mutex_spin_exit(&sc->sc_intr_lock); 1307 } 1308 } 1309 1310 void 1311 ehci_childdet(device_t self, device_t child) 1312 { 1313 struct ehci_softc *sc = device_private(self); 1314 1315 KASSERT(sc->sc_child == child); 1316 sc->sc_child = NULL; 1317 } 1318 1319 int 1320 ehci_detach(struct ehci_softc *sc, int flags) 1321 { 1322 int rv = 0; 1323 1324 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1325 1326 if (sc->sc_child != NULL) { 1327 rv = config_detach(sc->sc_child, flags); 1328 if (rv != 0) 1329 return rv; 1330 } 1331 1332 if (sc->sc_ncomp > 0) { 1333 mutex_enter(&sc->sc_complock); 1334 /* XXX try to halt callout instead of waiting */ 1335 while (sc->sc_comp_state == CO_SCHED) 1336 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1337 mutex_exit(&sc->sc_complock); 1338 1339 callout_halt(&sc->sc_compcallout, NULL); 1340 callout_destroy(&sc->sc_compcallout); 1341 cv_destroy(&sc->sc_compcv); 1342 mutex_destroy(&sc->sc_complock); 1343 } 1344 1345 callout_halt(&sc->sc_tmo_intrlist, NULL); 1346 callout_destroy(&sc->sc_tmo_intrlist); 1347 1348 /* XXX free other data structures */ 1349 if (sc->sc_softitds) { 1350 kmem_free(sc->sc_softitds, 1351 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1352 } 1353 cv_destroy(&sc->sc_doorbell); 1354 1355 #if 0 1356 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1357 softint_disestablish(sc->sc_doorbell_si); 1358 softint_disestablish(sc->sc_pcd_si); 1359 mutex_destroy(&sc->sc_lock); 1360 mutex_destroy(&sc->sc_intr_lock); 1361 #endif 1362 1363 pool_cache_destroy(sc->sc_xferpool); 1364 1365 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1366 1367 return rv; 1368 } 1369 1370 int 1371 ehci_activate(device_t self, enum devact act) 1372 { 1373 struct ehci_softc *sc = device_private(self); 1374 1375 switch (act) { 1376 case DVACT_DEACTIVATE: 1377 sc->sc_dying = 1; 1378 return 0; 1379 default: 1380 return EOPNOTSUPP; 1381 } 1382 } 1383 1384 /* 1385 * Handle suspend/resume. 1386 * 1387 * We need to switch to polling mode here, because this routine is 1388 * called from an interrupt context. This is all right since we 1389 * are almost suspended anyway. 1390 * 1391 * Note that this power handler isn't to be registered directly; the 1392 * bus glue needs to call out to it. 1393 */ 1394 bool 1395 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1396 { 1397 ehci_softc_t *sc = device_private(dv); 1398 int i; 1399 uint32_t cmd, hcr; 1400 1401 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1402 1403 mutex_spin_enter(&sc->sc_intr_lock); 1404 sc->sc_bus.ub_usepolling++; 1405 mutex_spin_exit(&sc->sc_intr_lock); 1406 1407 for (i = 1; i <= sc->sc_noport; i++) { 1408 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1409 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1410 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1411 } 1412 1413 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1414 1415 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1416 EOWRITE4(sc, EHCI_USBCMD, cmd); 1417 1418 for (i = 0; i < 100; i++) { 1419 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1420 if (hcr == 0) 1421 break; 1422 1423 usb_delay_ms(&sc->sc_bus, 1); 1424 } 1425 if (hcr != 0) 1426 printf("%s: reset timeout\n", device_xname(dv)); 1427 1428 cmd &= ~EHCI_CMD_RS; 1429 EOWRITE4(sc, EHCI_USBCMD, cmd); 1430 1431 for (i = 0; i < 100; i++) { 1432 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1433 if (hcr == EHCI_STS_HCH) 1434 break; 1435 1436 usb_delay_ms(&sc->sc_bus, 1); 1437 } 1438 if (hcr != EHCI_STS_HCH) 1439 printf("%s: config timeout\n", device_xname(dv)); 1440 1441 mutex_spin_enter(&sc->sc_intr_lock); 1442 sc->sc_bus.ub_usepolling--; 1443 mutex_spin_exit(&sc->sc_intr_lock); 1444 1445 return true; 1446 } 1447 1448 bool 1449 ehci_resume(device_t dv, const pmf_qual_t *qual) 1450 { 1451 ehci_softc_t *sc = device_private(dv); 1452 int i; 1453 uint32_t cmd, hcr; 1454 1455 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1456 1457 /* restore things in case the bios sucks */ 1458 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1459 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1460 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1461 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1462 1463 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1464 1465 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1466 1467 hcr = 0; 1468 for (i = 1; i <= sc->sc_noport; i++) { 1469 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1470 if ((cmd & EHCI_PS_PO) == 0 && 1471 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1472 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1473 hcr = 1; 1474 } 1475 } 1476 1477 if (hcr) { 1478 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1479 1480 for (i = 1; i <= sc->sc_noport; i++) { 1481 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1482 if ((cmd & EHCI_PS_PO) == 0 && 1483 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1484 EOWRITE4(sc, EHCI_PORTSC(i), 1485 cmd & ~EHCI_PS_FPR); 1486 } 1487 } 1488 1489 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1490 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1491 1492 for (i = 0; i < 100; i++) { 1493 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1494 if (hcr != EHCI_STS_HCH) 1495 break; 1496 1497 usb_delay_ms(&sc->sc_bus, 1); 1498 } 1499 if (hcr == EHCI_STS_HCH) 1500 printf("%s: config timeout\n", device_xname(dv)); 1501 1502 return true; 1503 } 1504 1505 /* 1506 * Shut down the controller when the system is going down. 1507 */ 1508 bool 1509 ehci_shutdown(device_t self, int flags) 1510 { 1511 ehci_softc_t *sc = device_private(self); 1512 1513 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1514 1515 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1516 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1517 return true; 1518 } 1519 1520 Static struct usbd_xfer * 1521 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1522 { 1523 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1524 struct usbd_xfer *xfer; 1525 1526 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1527 if (xfer != NULL) { 1528 memset(xfer, 0, sizeof(struct ehci_xfer)); 1529 1530 #ifdef DIAGNOSTIC 1531 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1532 ex->ex_isdone = true; 1533 xfer->ux_state = XFER_BUSY; 1534 #endif 1535 } 1536 return xfer; 1537 } 1538 1539 Static void 1540 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1541 { 1542 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1543 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1544 1545 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1546 xfer->ux_status == USBD_NOT_STARTED, 1547 "xfer %p state %d\n", xfer, xfer->ux_state); 1548 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1549 1550 #ifdef DIAGNOSTIC 1551 xfer->ux_state = XFER_FREE; 1552 #endif 1553 1554 pool_cache_put(sc->sc_xferpool, xfer); 1555 } 1556 1557 Static bool 1558 ehci_dying(struct usbd_bus *bus) 1559 { 1560 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1561 1562 return sc->sc_dying; 1563 } 1564 1565 Static void 1566 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1567 { 1568 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1569 1570 *lock = &sc->sc_lock; 1571 } 1572 1573 Static void 1574 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1575 { 1576 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1577 1578 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1579 1580 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1581 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1582 #ifdef EHCI_DEBUG 1583 if (ehcidebug) 1584 usbd_dump_pipe(pipe); 1585 #endif 1586 epipe->nexttoggle = 0; 1587 } 1588 1589 Static void 1590 ehci_noop(struct usbd_pipe *pipe) 1591 { 1592 } 1593 1594 #ifdef EHCI_DEBUG 1595 /* 1596 * Unused function - this is meant to be called from a kernel 1597 * debugger. 1598 */ 1599 void 1600 ehci_dump(void) 1601 { 1602 ehci_softc_t *sc = theehci; 1603 int i; 1604 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1605 EOREAD4(sc, EHCI_USBCMD), 1606 EOREAD4(sc, EHCI_USBSTS), 1607 EOREAD4(sc, EHCI_USBINTR)); 1608 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1609 EOREAD4(sc, EHCI_FRINDEX), 1610 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1611 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1612 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1613 for (i = 1; i <= sc->sc_noport; i++) 1614 printf("port %d status=0x%08x\n", i, 1615 EOREAD4(sc, EHCI_PORTSC(i))); 1616 } 1617 1618 Static void 1619 ehci_dump_regs(ehci_softc_t *sc) 1620 { 1621 int i; 1622 1623 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1624 1625 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1626 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1627 EOREAD4(sc, EHCI_USBINTR), 0); 1628 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1629 "async = 0x%08jx", 1630 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1631 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1632 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1633 for (i = 1; i <= sc->sc_noport; i += 2) { 1634 if (i == sc->sc_noport) { 1635 DPRINTF("port %jd status = 0x%08jx", i, 1636 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1637 } else { 1638 DPRINTF("port %jd status = 0x%08jx port %jd " 1639 "status = 0x%08jx", 1640 i, EOREAD4(sc, EHCI_PORTSC(i)), 1641 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1642 } 1643 } 1644 } 1645 1646 #define ehci_dump_link(link, type) do { \ 1647 DPRINTF(" link 0x%08jx (T = %jd):", \ 1648 link, \ 1649 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1650 if (type) { \ 1651 DPRINTF( \ 1652 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1653 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1654 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1655 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1656 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1657 } \ 1658 } while(0) 1659 1660 Static void 1661 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1662 { 1663 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1664 int i; 1665 uint32_t stop = 0; 1666 1667 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1668 ehci_dump_sqtd(sqtd); 1669 usb_syncmem(&sqtd->dma, 1670 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1671 sizeof(sqtd->qtd), 1672 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1673 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1674 usb_syncmem(&sqtd->dma, 1675 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1676 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1677 } 1678 if (!stop) 1679 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1680 } 1681 1682 Static void 1683 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1684 { 1685 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1686 1687 usb_syncmem(&sqtd->dma, sqtd->offs, 1688 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1689 1690 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1691 0, 0); 1692 ehci_dump_qtd(&sqtd->qtd); 1693 1694 usb_syncmem(&sqtd->dma, sqtd->offs, 1695 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1696 } 1697 1698 Static void 1699 ehci_dump_qtd(ehci_qtd_t *qtd) 1700 { 1701 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1702 uint32_t s = le32toh(qtd->qtd_status); 1703 1704 DPRINTFN(10, 1705 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1706 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1707 DPRINTFN(10, 1708 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1709 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1710 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1711 DPRINTFN(10, 1712 " cerr = %jd pid = %jd stat = %jx", 1713 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1714 0); 1715 DPRINTFN(10, 1716 "active =%jd halted=%jd buferr=%jd babble=%jd", 1717 s & EHCI_QTD_ACTIVE ? 1 : 0, 1718 s & EHCI_QTD_HALTED ? 1 : 0, 1719 s & EHCI_QTD_BUFERR ? 1 : 0, 1720 s & EHCI_QTD_BABBLE ? 1 : 0); 1721 DPRINTFN(10, 1722 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1723 s & EHCI_QTD_XACTERR ? 1 : 0, 1724 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1725 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1726 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1727 DPRINTFN(10, 1728 "buffer[0] = %#jx buffer[1] = %#jx " 1729 "buffer[2] = %#jx buffer[3] = %#jx", 1730 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1731 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1732 DPRINTFN(10, 1733 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1734 } 1735 1736 Static void 1737 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1738 { 1739 ehci_qh_t *qh = &sqh->qh; 1740 ehci_link_t link; 1741 uint32_t endp, endphub; 1742 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1743 1744 usb_syncmem(&sqh->dma, sqh->offs, 1745 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1746 1747 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1748 link = le32toh(qh->qh_link); 1749 ehci_dump_link(link, true); 1750 1751 endp = le32toh(qh->qh_endp); 1752 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1753 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1754 "eps = %jd", 1755 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1756 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1757 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1758 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1759 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1760 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1761 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1762 1763 endphub = le32toh(qh->qh_endphub); 1764 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1765 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1766 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1767 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1768 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1769 EHCI_QH_GET_MULT(endphub), 0); 1770 1771 link = le32toh(qh->qh_curqtd); 1772 ehci_dump_link(link, false); 1773 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1774 ehci_dump_qtd(&qh->qh_qtd); 1775 1776 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1777 BUS_DMASYNC_PREREAD); 1778 } 1779 1780 Static void 1781 ehci_dump_itds(ehci_soft_itd_t *itd) 1782 { 1783 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1784 int i; 1785 uint32_t stop = 0; 1786 1787 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1788 ehci_dump_itd(itd); 1789 usb_syncmem(&itd->dma, 1790 itd->offs + offsetof(ehci_itd_t, itd_next), 1791 sizeof(itd->itd), 1792 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1793 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1794 usb_syncmem(&itd->dma, 1795 itd->offs + offsetof(ehci_itd_t, itd_next), 1796 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1797 } 1798 if (!stop) 1799 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1800 } 1801 1802 Static void 1803 ehci_dump_itd(struct ehci_soft_itd *itd) 1804 { 1805 ehci_isoc_trans_t t; 1806 ehci_isoc_bufr_ptr_t b, b2, b3; 1807 int i; 1808 1809 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1810 1811 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1812 1813 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1814 t = le32toh(itd->itd.itd_ctl[i]); 1815 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1816 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1817 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1818 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1819 EHCI_ITD_GET_OFFS(t), 0); 1820 } 1821 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1822 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1823 DPRINTF(" %jx", 1824 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1825 1826 b = le32toh(itd->itd.itd_bufr[0]); 1827 b2 = le32toh(itd->itd.itd_bufr[1]); 1828 b3 = le32toh(itd->itd.itd_bufr[2]); 1829 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1830 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1831 DPRINTF(" maxpkt = %jx multi = %jx", 1832 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1833 } 1834 1835 Static void 1836 ehci_dump_sitd(struct ehci_soft_itd *itd) 1837 { 1838 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1839 1840 DPRINTF("SITD %#jx next = %p prev = %#jx", 1841 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1842 (uintptr_t)itd->frame_list.prev, 0); 1843 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1844 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1845 } 1846 1847 Static void 1848 ehci_dump_exfer(struct ehci_xfer *ex) 1849 { 1850 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1851 1852 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1853 ex->ex_isdone, 0); 1854 1855 switch (ex->ex_type) { 1856 case EX_CTRL: 1857 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1858 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1859 (uintptr_t)ex->ex_status, 0); 1860 break; 1861 case EX_BULK: 1862 case EX_INTR: 1863 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1864 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1865 0, 0); 1866 break; 1867 case EX_ISOC: 1868 DPRINTF(" itdstart = %#jx itdend = %#jx", 1869 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1870 break; 1871 case EX_FS_ISOC: 1872 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1873 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1874 0, 0); 1875 break; 1876 default: 1877 DPRINTF(" unknown type", 0, 0, 0, 0); 1878 } 1879 } 1880 #endif 1881 1882 Static usbd_status 1883 ehci_open(struct usbd_pipe *pipe) 1884 { 1885 struct usbd_device *dev = pipe->up_dev; 1886 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1887 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1888 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1889 uint8_t addr = dev->ud_addr; 1890 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1891 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1892 ehci_soft_qh_t *sqh; 1893 usbd_status err; 1894 int ival, speed, naks; 1895 int hshubaddr, hshubport; 1896 1897 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1898 1899 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1900 ed->bEndpointAddress, rhaddr); 1901 1902 if (dev->ud_myhsport) { 1903 /* 1904 * When directly attached FS/LS device while doing embedded 1905 * transaction translations and we are the hub, set the hub 1906 * address to 0 (us). 1907 */ 1908 if (!(sc->sc_flags & EHCIF_ETTF) 1909 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1910 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1911 } else { 1912 hshubaddr = 0; 1913 } 1914 hshubport = dev->ud_myhsport->up_portno; 1915 } else { 1916 hshubaddr = 0; 1917 hshubport = 0; 1918 } 1919 1920 if (sc->sc_dying) 1921 return USBD_IOERROR; 1922 1923 /* toggle state needed for bulk endpoints */ 1924 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1925 1926 if (addr == rhaddr) { 1927 switch (ed->bEndpointAddress) { 1928 case USB_CONTROL_ENDPOINT: 1929 pipe->up_methods = &roothub_ctrl_methods; 1930 break; 1931 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1932 pipe->up_methods = &ehci_root_intr_methods; 1933 break; 1934 default: 1935 DPRINTF("bad bEndpointAddress 0x%02jx", 1936 ed->bEndpointAddress, 0, 0, 0); 1937 return USBD_INVAL; 1938 } 1939 return USBD_NORMAL_COMPLETION; 1940 } 1941 1942 /* XXX All this stuff is only valid for async. */ 1943 switch (dev->ud_speed) { 1944 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1945 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1946 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1947 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1948 } 1949 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1950 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1951 0); 1952 return USBD_INVAL; 1953 } 1954 1955 /* 1956 * For interrupt transfer, nak throttling must be disabled, but for 1957 * the other transfer type, nak throttling should be enabled from the 1958 * viewpoint that avoids the memory thrashing. 1959 */ 1960 naks = (xfertype == UE_INTERRUPT) ? 0 1961 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1962 1963 /* Allocate sqh for everything, save isoc xfers */ 1964 if (xfertype != UE_ISOCHRONOUS) { 1965 sqh = ehci_alloc_sqh(sc); 1966 if (sqh == NULL) 1967 return USBD_NOMEM; 1968 /* qh_link filled when the QH is added */ 1969 sqh->qh.qh_endp = htole32( 1970 EHCI_QH_SET_ADDR(addr) | 1971 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1972 EHCI_QH_SET_EPS(speed) | 1973 EHCI_QH_DTC | 1974 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1975 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1976 EHCI_QH_CTL : 0) | 1977 EHCI_QH_SET_NRL(naks) 1978 ); 1979 sqh->qh.qh_endphub = htole32( 1980 EHCI_QH_SET_MULT(1) | 1981 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1982 ); 1983 if (speed != EHCI_QH_SPEED_HIGH) 1984 sqh->qh.qh_endphub |= htole32( 1985 EHCI_QH_SET_PORT(hshubport) | 1986 EHCI_QH_SET_HUBA(hshubaddr) | 1987 (xfertype == UE_INTERRUPT ? 1988 EHCI_QH_SET_CMASK(0x08) : 0) 1989 ); 1990 sqh->qh.qh_curqtd = EHCI_NULL; 1991 /* Fill the overlay qTD */ 1992 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1993 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1994 sqh->qh.qh_qtd.qtd_status = htole32(0); 1995 1996 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1997 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1998 epipe->sqh = sqh; 1999 } else { 2000 sqh = NULL; 2001 } /*xfertype == UE_ISOC*/ 2002 2003 switch (xfertype) { 2004 case UE_CONTROL: 2005 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2006 0, USBMALLOC_COHERENT, &epipe->ctrl.reqdma); 2007 #ifdef EHCI_DEBUG 2008 if (err) 2009 printf("ehci_open: usb_allocmem()=%d\n", err); 2010 #endif 2011 if (err) 2012 goto bad; 2013 pipe->up_methods = &ehci_device_ctrl_methods; 2014 mutex_enter(&sc->sc_lock); 2015 ehci_add_qh(sc, sqh, sc->sc_async_head); 2016 mutex_exit(&sc->sc_lock); 2017 break; 2018 case UE_BULK: 2019 pipe->up_methods = &ehci_device_bulk_methods; 2020 mutex_enter(&sc->sc_lock); 2021 ehci_add_qh(sc, sqh, sc->sc_async_head); 2022 mutex_exit(&sc->sc_lock); 2023 break; 2024 case UE_INTERRUPT: 2025 pipe->up_methods = &ehci_device_intr_methods; 2026 ival = pipe->up_interval; 2027 if (ival == USBD_DEFAULT_INTERVAL) { 2028 if (speed == EHCI_QH_SPEED_HIGH) { 2029 if (ed->bInterval > 16) { 2030 /* 2031 * illegal with high-speed, but there 2032 * were documentation bugs in the spec, 2033 * so be generous 2034 */ 2035 ival = 256; 2036 } else 2037 ival = (1 << (ed->bInterval - 1)) / 8; 2038 } else 2039 ival = ed->bInterval; 2040 } 2041 err = ehci_device_setintr(sc, sqh, ival); 2042 if (err) 2043 goto bad; 2044 break; 2045 case UE_ISOCHRONOUS: 2046 pipe->up_serialise = false; 2047 if (speed == EHCI_QH_SPEED_HIGH) 2048 pipe->up_methods = &ehci_device_isoc_methods; 2049 else 2050 pipe->up_methods = &ehci_device_fs_isoc_methods; 2051 if (ed->bInterval == 0 || ed->bInterval > 16) { 2052 printf("ehci: opening pipe with invalid bInterval\n"); 2053 err = USBD_INVAL; 2054 goto bad; 2055 } 2056 if (UGETW(ed->wMaxPacketSize) == 0) { 2057 printf("ehci: zero length endpoint open request\n"); 2058 err = USBD_INVAL; 2059 goto bad; 2060 } 2061 epipe->isoc.next_frame = 0; 2062 epipe->isoc.cur_xfers = 0; 2063 break; 2064 default: 2065 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2066 err = USBD_INVAL; 2067 goto bad; 2068 } 2069 return USBD_NORMAL_COMPLETION; 2070 2071 bad: 2072 if (sqh != NULL) { 2073 mutex_enter(&sc->sc_lock); 2074 ehci_free_sqh(sc, sqh); 2075 mutex_exit(&sc->sc_lock); 2076 } 2077 return err; 2078 } 2079 2080 /* 2081 * Add an ED to the schedule. Called with USB lock held. 2082 */ 2083 Static void 2084 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2085 { 2086 2087 KASSERT(mutex_owned(&sc->sc_lock)); 2088 2089 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2090 2091 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2092 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2093 2094 sqh->next = head->next; 2095 sqh->qh.qh_link = head->qh.qh_link; 2096 2097 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2098 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2099 2100 head->next = sqh; 2101 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2102 2103 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2104 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2105 2106 #ifdef EHCI_DEBUG 2107 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2108 ehci_dump_sqh(sqh); 2109 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2110 #endif 2111 } 2112 2113 /* 2114 * Remove an ED from the schedule. Called with USB lock held. 2115 */ 2116 Static void 2117 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2118 { 2119 ehci_soft_qh_t *p; 2120 2121 KASSERT(mutex_owned(&sc->sc_lock)); 2122 2123 /* XXX */ 2124 for (p = head; p != NULL && p->next != sqh; p = p->next) 2125 ; 2126 if (p == NULL) 2127 panic("ehci_rem_qh: ED not found"); 2128 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2129 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2130 p->next = sqh->next; 2131 p->qh.qh_link = sqh->qh.qh_link; 2132 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2133 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2134 2135 ehci_sync_hc(sc); 2136 } 2137 2138 Static void 2139 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2140 { 2141 int i; 2142 uint32_t status; 2143 2144 /* Save toggle bit and ping status. */ 2145 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2146 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2147 status = sqh->qh.qh_qtd.qtd_status & 2148 htole32(EHCI_QTD_TOGGLE_MASK | 2149 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2150 /* Set HALTED to make hw leave it alone. */ 2151 sqh->qh.qh_qtd.qtd_status = 2152 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2153 usb_syncmem(&sqh->dma, 2154 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2155 sizeof(sqh->qh.qh_qtd.qtd_status), 2156 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2157 sqh->qh.qh_curqtd = 0; 2158 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2159 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2160 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2161 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2162 sqh->sqtd = sqtd; 2163 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2164 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2165 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2166 sqh->qh.qh_qtd.qtd_status = status; 2167 usb_syncmem(&sqh->dma, 2168 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2169 sizeof(sqh->qh.qh_qtd.qtd_status), 2170 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2171 } 2172 2173 /* 2174 * Ensure that the HC has released all references to the QH. We do this 2175 * by asking for a Async Advance Doorbell interrupt and then we wait for 2176 * the interrupt. 2177 * To make this easier we first obtain exclusive use of the doorbell. 2178 */ 2179 Static void 2180 ehci_sync_hc(ehci_softc_t *sc) 2181 { 2182 int error __diagused; 2183 2184 KASSERT(mutex_owned(&sc->sc_lock)); 2185 2186 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2187 2188 if (sc->sc_dying) { 2189 DPRINTF("dying", 0, 0, 0, 0); 2190 return; 2191 } 2192 2193 /* ask for doorbell */ 2194 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2195 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2196 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2197 2198 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2199 2200 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2201 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2202 #ifdef DIAGNOSTIC 2203 if (error == EWOULDBLOCK) { 2204 printf("ehci_sync_hc: timed out\n"); 2205 } else if (error) { 2206 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2207 } 2208 #endif 2209 } 2210 2211 Static void 2212 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2213 { 2214 2215 KASSERT(mutex_owned(&sc->sc_lock)); 2216 2217 for (; itd != NULL; itd = itd->xfer_next) { 2218 struct ehci_soft_itd *prev = itd->frame_list.prev; 2219 2220 /* Unlink itd from hardware chain, or frame array */ 2221 if (prev == NULL) { /* We're at the table head */ 2222 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2223 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2224 usb_syncmem(&sc->sc_fldma, 2225 sizeof(ehci_link_t) * itd->slot, 2226 sizeof(ehci_link_t), 2227 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2228 2229 if (itd->frame_list.next != NULL) 2230 itd->frame_list.next->frame_list.prev = NULL; 2231 } else { 2232 /* XXX this part is untested... */ 2233 prev->itd.itd_next = itd->itd.itd_next; 2234 usb_syncmem(&itd->dma, 2235 itd->offs + offsetof(ehci_itd_t, itd_next), 2236 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2237 2238 prev->frame_list.next = itd->frame_list.next; 2239 if (itd->frame_list.next != NULL) 2240 itd->frame_list.next->frame_list.prev = prev; 2241 } 2242 } 2243 } 2244 2245 Static void 2246 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2247 { 2248 struct ehci_soft_itd *next; 2249 2250 mutex_enter(&sc->sc_lock); 2251 next = NULL; 2252 for (; itd != NULL; itd = next) { 2253 next = itd->xfer_next; 2254 ehci_free_itd_locked(sc, itd); 2255 } 2256 mutex_exit(&sc->sc_lock); 2257 } 2258 2259 Static void 2260 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2261 { 2262 2263 KASSERT(mutex_owned(&sc->sc_lock)); 2264 2265 for (; sitd != NULL; sitd = sitd->xfer_next) { 2266 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2267 2268 /* Unlink sitd from hardware chain, or frame array */ 2269 if (prev == NULL) { /* We're at the table head */ 2270 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2271 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2272 usb_syncmem(&sc->sc_fldma, 2273 sizeof(ehci_link_t) * sitd->slot, 2274 sizeof(ehci_link_t), 2275 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2276 2277 if (sitd->frame_list.next != NULL) 2278 sitd->frame_list.next->frame_list.prev = NULL; 2279 } else { 2280 /* XXX this part is untested... */ 2281 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2282 usb_syncmem(&sitd->dma, 2283 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2284 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2285 2286 prev->frame_list.next = sitd->frame_list.next; 2287 if (sitd->frame_list.next != NULL) 2288 sitd->frame_list.next->frame_list.prev = prev; 2289 } 2290 } 2291 } 2292 2293 Static void 2294 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2295 { 2296 2297 mutex_enter(&sc->sc_lock); 2298 struct ehci_soft_sitd *next = NULL; 2299 for (; sitd != NULL; sitd = next) { 2300 next = sitd->xfer_next; 2301 ehci_free_sitd_locked(sc, sitd); 2302 } 2303 mutex_exit(&sc->sc_lock); 2304 } 2305 2306 /***********/ 2307 2308 Static int 2309 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2310 void *buf, int buflen) 2311 { 2312 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2313 usb_hub_descriptor_t hubd; 2314 usb_port_status_t ps; 2315 uint16_t len, value, index; 2316 int l, totlen = 0; 2317 int port, i; 2318 uint32_t v; 2319 2320 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2321 2322 if (sc->sc_dying) 2323 return -1; 2324 2325 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2326 0, 0); 2327 2328 len = UGETW(req->wLength); 2329 value = UGETW(req->wValue); 2330 index = UGETW(req->wIndex); 2331 2332 #define C(x,y) ((x) | ((y) << 8)) 2333 switch (C(req->bRequest, req->bmRequestType)) { 2334 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2335 if (len == 0) 2336 break; 2337 switch (value) { 2338 #define sd ((usb_string_descriptor_t *)buf) 2339 case C(2, UDESC_STRING): 2340 /* Product */ 2341 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2342 break; 2343 #undef sd 2344 default: 2345 /* default from usbroothub */ 2346 return buflen; 2347 } 2348 break; 2349 2350 /* Hub requests */ 2351 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2352 break; 2353 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2354 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2355 value, 0, 0); 2356 if (index < 1 || index > sc->sc_noport) { 2357 return -1; 2358 } 2359 port = EHCI_PORTSC(index); 2360 v = EOREAD4(sc, port); 2361 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2362 v &= ~EHCI_PS_CLEAR; 2363 switch (value) { 2364 case UHF_PORT_ENABLE: 2365 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2366 break; 2367 case UHF_PORT_SUSPEND: 2368 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2369 break; 2370 v &= ~EHCI_PS_SUSP; 2371 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2372 /* see USB2 spec ch. 7.1.7.7 */ 2373 usb_delay_ms(&sc->sc_bus, 20); 2374 EOWRITE4(sc, port, v); 2375 usb_delay_ms(&sc->sc_bus, 2); 2376 #ifdef DEBUG 2377 v = EOREAD4(sc, port); 2378 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2379 printf("ehci: resume failed: %x\n", v); 2380 #endif 2381 break; 2382 case UHF_PORT_POWER: 2383 if (sc->sc_hasppc) 2384 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2385 break; 2386 case UHF_PORT_TEST: 2387 DPRINTF("clear port test %jd", index, 0, 0, 0); 2388 break; 2389 case UHF_PORT_INDICATOR: 2390 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2391 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2392 break; 2393 case UHF_C_PORT_CONNECTION: 2394 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2395 break; 2396 case UHF_C_PORT_ENABLE: 2397 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2398 break; 2399 case UHF_C_PORT_SUSPEND: 2400 /* how? */ 2401 break; 2402 case UHF_C_PORT_OVER_CURRENT: 2403 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2404 break; 2405 case UHF_C_PORT_RESET: 2406 sc->sc_isreset[index] = 0; 2407 break; 2408 default: 2409 return -1; 2410 } 2411 #if 0 2412 switch(value) { 2413 case UHF_C_PORT_CONNECTION: 2414 case UHF_C_PORT_ENABLE: 2415 case UHF_C_PORT_SUSPEND: 2416 case UHF_C_PORT_OVER_CURRENT: 2417 case UHF_C_PORT_RESET: 2418 default: 2419 break; 2420 } 2421 #endif 2422 break; 2423 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2424 if (len == 0) 2425 break; 2426 if ((value & 0xff) != 0) { 2427 return -1; 2428 } 2429 totlen = uimin(buflen, sizeof(hubd)); 2430 memcpy(&hubd, buf, totlen); 2431 hubd.bNbrPorts = sc->sc_noport; 2432 v = EOREAD4(sc, EHCI_HCSPARAMS); 2433 USETW(hubd.wHubCharacteristics, 2434 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2435 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2436 ? UHD_PORT_IND : 0); 2437 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2438 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2439 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2440 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2441 totlen = uimin(totlen, hubd.bDescLength); 2442 memcpy(buf, &hubd, totlen); 2443 break; 2444 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2445 if (len != 4) { 2446 return -1; 2447 } 2448 memset(buf, 0, len); /* ? XXX */ 2449 totlen = len; 2450 break; 2451 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2452 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2453 if (index < 1 || index > sc->sc_noport) { 2454 return -1; 2455 } 2456 if (len != 4) { 2457 return -1; 2458 } 2459 v = EOREAD4(sc, EHCI_PORTSC(index)); 2460 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2461 2462 i = UPS_HIGH_SPEED; 2463 if (sc->sc_flags & EHCIF_ETTF) { 2464 /* 2465 * If we are doing embedded transaction translation, 2466 * then directly attached LS/FS devices are reset by 2467 * the EHCI controller itself. PSPD is encoded 2468 * the same way as in USBSTATUS. 2469 */ 2470 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2471 } 2472 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2473 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2474 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2475 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2476 if (v & EHCI_PS_PR) i |= UPS_RESET; 2477 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2478 if (sc->sc_vendor_port_status) 2479 i = sc->sc_vendor_port_status(sc, v, i); 2480 USETW(ps.wPortStatus, i); 2481 i = 0; 2482 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2483 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2484 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2485 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2486 USETW(ps.wPortChange, i); 2487 totlen = uimin(len, sizeof(ps)); 2488 memcpy(buf, &ps, totlen); 2489 break; 2490 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2491 return -1; 2492 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2493 break; 2494 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2495 if (index < 1 || index > sc->sc_noport) { 2496 return -1; 2497 } 2498 port = EHCI_PORTSC(index); 2499 v = EOREAD4(sc, port); 2500 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2501 v &= ~EHCI_PS_CLEAR; 2502 switch(value) { 2503 case UHF_PORT_ENABLE: 2504 EOWRITE4(sc, port, v | EHCI_PS_PE); 2505 break; 2506 case UHF_PORT_SUSPEND: 2507 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2508 break; 2509 case UHF_PORT_RESET: 2510 DPRINTF("reset port %jd", index, 0, 0, 0); 2511 if (EHCI_PS_IS_LOWSPEED(v) 2512 && sc->sc_ncomp > 0 2513 && !(sc->sc_flags & EHCIF_ETTF)) { 2514 /* 2515 * Low speed device on non-ETTF controller or 2516 * unaccompanied controller, give up ownership. 2517 */ 2518 ehci_disown(sc, index, 1); 2519 break; 2520 } 2521 /* Start reset sequence. */ 2522 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2523 EOWRITE4(sc, port, v | EHCI_PS_PR); 2524 /* Wait for reset to complete. */ 2525 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2526 if (sc->sc_dying) { 2527 return -1; 2528 } 2529 /* 2530 * An embedded transaction translator will automatically 2531 * terminate the reset sequence so there's no need to 2532 * it. 2533 */ 2534 v = EOREAD4(sc, port); 2535 if (v & EHCI_PS_PR) { 2536 /* Terminate reset sequence. */ 2537 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2538 /* Wait for HC to complete reset. */ 2539 usb_delay_ms(&sc->sc_bus, 2540 EHCI_PORT_RESET_COMPLETE); 2541 if (sc->sc_dying) { 2542 return -1; 2543 } 2544 } 2545 2546 v = EOREAD4(sc, port); 2547 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2548 if (v & EHCI_PS_PR) { 2549 printf("%s: port reset timeout\n", 2550 device_xname(sc->sc_dev)); 2551 return USBD_TIMEOUT; 2552 } 2553 if (!(v & EHCI_PS_PE)) { 2554 /* Not a high speed device, give up ownership.*/ 2555 ehci_disown(sc, index, 0); 2556 break; 2557 } 2558 sc->sc_isreset[index] = 1; 2559 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2560 v, 0, 0); 2561 break; 2562 case UHF_PORT_POWER: 2563 DPRINTF("set port power %jd (has PPC = %jd)", index, 2564 sc->sc_hasppc, 0, 0); 2565 if (sc->sc_hasppc) 2566 EOWRITE4(sc, port, v | EHCI_PS_PP); 2567 break; 2568 case UHF_PORT_TEST: 2569 DPRINTF("set port test %jd", index, 0, 0, 0); 2570 break; 2571 case UHF_PORT_INDICATOR: 2572 DPRINTF("set port ind %jd", index, 0, 0, 0); 2573 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2574 break; 2575 default: 2576 return -1; 2577 } 2578 break; 2579 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2580 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2581 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2582 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2583 break; 2584 default: 2585 /* default from usbroothub */ 2586 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2587 2588 return buflen; 2589 } 2590 2591 DPRINTF("returning %jd", totlen, 0, 0, 0); 2592 2593 return totlen; 2594 } 2595 2596 /* 2597 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2598 * 2599 * This pile of garbage below works around the following problem without 2600 * holding boots with no hand-over devices present, while penalising 2601 * boots where the first ehci probe hands off devices with a 5 second 2602 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2603 * for RB_SINGLE, but the same basic issue exists. 2604 * 2605 * The way ehci hand-off works, the companion controller does not get the 2606 * device until after its initial bus explore, so the reference dropped 2607 * after the first explore is not enough. 5 seconds should be enough, 2608 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2609 * 2610 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2611 * if the callback is scheduled. CO_DONE is set when the callout has 2612 * called config_pending_decr(). 2613 * 2614 * There's a mutex, a cv and a callout here, and we delay detach if the 2615 * callout has been set. 2616 */ 2617 #ifndef EHCI_DISOWN_DELAY_SECONDS 2618 #define EHCI_DISOWN_DELAY_SECONDS 5 2619 #endif 2620 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2621 2622 static void 2623 ehci_disown_callback(void *arg) 2624 { 2625 ehci_softc_t *sc = arg; 2626 2627 config_pending_decr(sc->sc_dev); 2628 2629 mutex_enter(&sc->sc_complock); 2630 KASSERT(sc->sc_comp_state == CO_SCHED); 2631 sc->sc_comp_state = CO_DONE; 2632 cv_signal(&sc->sc_compcv); 2633 mutex_exit(&sc->sc_complock); 2634 } 2635 2636 static void 2637 ehci_disown_sched_callback(ehci_softc_t *sc) 2638 { 2639 extern bool root_is_mounted; 2640 2641 mutex_enter(&sc->sc_complock); 2642 2643 if (root_is_mounted || 2644 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2645 sc->sc_comp_state != CO_EARLY) { 2646 mutex_exit(&sc->sc_complock); 2647 return; 2648 } 2649 2650 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2651 ehci_disown_callback, &sc->sc_dev); 2652 sc->sc_comp_state = CO_SCHED; 2653 2654 mutex_exit(&sc->sc_complock); 2655 2656 config_pending_incr(sc->sc_dev); 2657 aprint_normal("delaying %s by %u seconds due to USB owner change.", 2658 (boothowto & RB_ASKNAME) == 0 ? "ask root" : "single user", 2659 ehci_disown_delay_seconds); 2660 } 2661 2662 Static void 2663 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2664 { 2665 int port; 2666 uint32_t v; 2667 2668 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2669 2670 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2671 if (sc->sc_npcomp != 0) { 2672 int i = (index-1) / sc->sc_npcomp; 2673 if (i < sc->sc_ncomp) { 2674 ehci_disown_sched_callback(sc); 2675 #ifdef DIAGNOSTIC 2676 printf("%s: handing over %s speed device on " 2677 "port %d to %s\n", 2678 device_xname(sc->sc_dev), 2679 lowspeed ? "low" : "full", 2680 index, sc->sc_comps[i] ? 2681 device_xname(sc->sc_comps[i]) : 2682 "companion controller"); 2683 } else { 2684 printf("%s: strange port\n", 2685 device_xname(sc->sc_dev)); 2686 #endif 2687 } 2688 } else { 2689 #ifdef DIAGNOSTIC 2690 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2691 #endif 2692 } 2693 port = EHCI_PORTSC(index); 2694 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2695 EOWRITE4(sc, port, v | EHCI_PS_PO); 2696 } 2697 2698 Static usbd_status 2699 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2700 { 2701 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2702 usbd_status err; 2703 2704 /* Insert last in queue. */ 2705 mutex_enter(&sc->sc_lock); 2706 err = usb_insert_transfer(xfer); 2707 mutex_exit(&sc->sc_lock); 2708 if (err) 2709 return err; 2710 2711 /* Pipe isn't running, start first */ 2712 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2713 } 2714 2715 Static usbd_status 2716 ehci_root_intr_start(struct usbd_xfer *xfer) 2717 { 2718 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2719 const bool polling = sc->sc_bus.ub_usepolling; 2720 2721 if (sc->sc_dying) 2722 return USBD_IOERROR; 2723 2724 if (!polling) 2725 mutex_enter(&sc->sc_lock); 2726 KASSERT(sc->sc_intrxfer == NULL); 2727 sc->sc_intrxfer = xfer; 2728 xfer->ux_status = USBD_IN_PROGRESS; 2729 if (!polling) 2730 mutex_exit(&sc->sc_lock); 2731 2732 return USBD_IN_PROGRESS; 2733 } 2734 2735 /* Abort a root interrupt request. */ 2736 Static void 2737 ehci_root_intr_abort(struct usbd_xfer *xfer) 2738 { 2739 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2740 2741 KASSERT(mutex_owned(&sc->sc_lock)); 2742 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2743 2744 /* If xfer has already completed, nothing to do here. */ 2745 if (sc->sc_intrxfer == NULL) 2746 return; 2747 2748 /* 2749 * Otherwise, sc->sc_intrxfer had better be this transfer. 2750 * Cancel it. 2751 */ 2752 KASSERT(sc->sc_intrxfer == xfer); 2753 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2754 xfer->ux_status = USBD_CANCELLED; 2755 usb_transfer_complete(xfer); 2756 } 2757 2758 /* Close the root pipe. */ 2759 Static void 2760 ehci_root_intr_close(struct usbd_pipe *pipe) 2761 { 2762 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2763 2764 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2765 2766 KASSERT(mutex_owned(&sc->sc_lock)); 2767 2768 /* 2769 * Caller must guarantee the xfer has completed first, by 2770 * closing the pipe only after normal completion or an abort. 2771 */ 2772 KASSERT(sc->sc_intrxfer == NULL); 2773 } 2774 2775 Static void 2776 ehci_root_intr_done(struct usbd_xfer *xfer) 2777 { 2778 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2779 2780 KASSERT(mutex_owned(&sc->sc_lock)); 2781 2782 /* Claim the xfer so it doesn't get completed again. */ 2783 KASSERT(sc->sc_intrxfer == xfer); 2784 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2785 sc->sc_intrxfer = NULL; 2786 } 2787 2788 /************************/ 2789 2790 Static ehci_soft_qh_t * 2791 ehci_alloc_sqh(ehci_softc_t *sc) 2792 { 2793 ehci_soft_qh_t *sqh; 2794 usbd_status err; 2795 int i, offs; 2796 usb_dma_t dma; 2797 2798 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2799 2800 mutex_enter(&sc->sc_lock); 2801 if (sc->sc_freeqhs == NULL) { 2802 DPRINTF("allocating chunk", 0, 0, 0, 0); 2803 mutex_exit(&sc->sc_lock); 2804 2805 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2806 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2807 #ifdef EHCI_DEBUG 2808 if (err) 2809 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2810 #endif 2811 if (err) 2812 return NULL; 2813 2814 mutex_enter(&sc->sc_lock); 2815 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2816 offs = i * EHCI_SQH_SIZE; 2817 sqh = KERNADDR(&dma, offs); 2818 sqh->physaddr = DMAADDR(&dma, offs); 2819 sqh->dma = dma; 2820 sqh->offs = offs; 2821 sqh->next = sc->sc_freeqhs; 2822 sc->sc_freeqhs = sqh; 2823 } 2824 } 2825 sqh = sc->sc_freeqhs; 2826 sc->sc_freeqhs = sqh->next; 2827 mutex_exit(&sc->sc_lock); 2828 2829 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2830 sqh->next = NULL; 2831 return sqh; 2832 } 2833 2834 Static void 2835 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2836 { 2837 KASSERT(mutex_owned(&sc->sc_lock)); 2838 2839 sqh->next = sc->sc_freeqhs; 2840 sc->sc_freeqhs = sqh; 2841 } 2842 2843 Static ehci_soft_qtd_t * 2844 ehci_alloc_sqtd(ehci_softc_t *sc) 2845 { 2846 ehci_soft_qtd_t *sqtd = NULL; 2847 usbd_status err; 2848 int i, offs; 2849 usb_dma_t dma; 2850 2851 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2852 2853 mutex_enter(&sc->sc_lock); 2854 if (sc->sc_freeqtds == NULL) { 2855 DPRINTF("allocating chunk", 0, 0, 0, 0); 2856 mutex_exit(&sc->sc_lock); 2857 2858 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2859 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2860 #ifdef EHCI_DEBUG 2861 if (err) 2862 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2863 #endif 2864 if (err) 2865 goto done; 2866 2867 mutex_enter(&sc->sc_lock); 2868 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2869 offs = i * EHCI_SQTD_SIZE; 2870 sqtd = KERNADDR(&dma, offs); 2871 sqtd->physaddr = DMAADDR(&dma, offs); 2872 sqtd->dma = dma; 2873 sqtd->offs = offs; 2874 2875 sqtd->nextqtd = sc->sc_freeqtds; 2876 sc->sc_freeqtds = sqtd; 2877 } 2878 } 2879 2880 sqtd = sc->sc_freeqtds; 2881 sc->sc_freeqtds = sqtd->nextqtd; 2882 mutex_exit(&sc->sc_lock); 2883 2884 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2885 sqtd->nextqtd = NULL; 2886 sqtd->xfer = NULL; 2887 2888 done: 2889 return sqtd; 2890 } 2891 2892 Static void 2893 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2894 { 2895 2896 mutex_enter(&sc->sc_lock); 2897 sqtd->nextqtd = sc->sc_freeqtds; 2898 sc->sc_freeqtds = sqtd; 2899 mutex_exit(&sc->sc_lock); 2900 } 2901 2902 Static int 2903 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2904 int alen, int rd, ehci_soft_qtd_t **sp) 2905 { 2906 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2907 uint16_t flags = xfer->ux_flags; 2908 2909 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2910 2911 ASSERT_SLEEPABLE(); 2912 KASSERT(sp); 2913 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2914 2915 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2916 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 2917 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2918 KM_SLEEP); 2919 exfer->ex_nsqtd = nsqtd; 2920 2921 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2922 alen, nsqtd, flags); 2923 2924 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2925 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2926 if (cur == NULL) 2927 goto nomem; 2928 exfer->ex_sqtds[j++] = cur; 2929 2930 cur->xfer = xfer; 2931 cur->len = 0; 2932 2933 } 2934 2935 *sp = exfer->ex_sqtds[0]; 2936 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2937 2938 return 0; 2939 2940 nomem: 2941 ehci_free_sqtds(sc, exfer); 2942 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2943 DPRINTF("no memory", 0, 0, 0, 0); 2944 return ENOMEM; 2945 } 2946 2947 Static void 2948 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2949 { 2950 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2951 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2952 2953 mutex_enter(&sc->sc_lock); 2954 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2955 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2956 2957 if (sqtd == NULL) 2958 break; 2959 2960 sqtd->nextqtd = sc->sc_freeqtds; 2961 sc->sc_freeqtds = sqtd; 2962 } 2963 mutex_exit(&sc->sc_lock); 2964 } 2965 2966 Static void 2967 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2968 { 2969 if (prev) { 2970 prev->nextqtd = sqtd; 2971 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2972 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2973 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2974 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2975 } 2976 } 2977 2978 Static void 2979 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2980 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2981 { 2982 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2983 usb_dma_t *dma = &xfer->ux_dmabuf; 2984 uint16_t flags = xfer->ux_flags; 2985 ehci_soft_qtd_t *sqtd, *prev; 2986 int tog = *toggle; 2987 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2988 int len = length; 2989 2990 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2991 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2992 len, isread, tog); 2993 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2994 0, 0, 0); 2995 2996 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2997 2998 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2999 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3000 EHCI_QTD_SET_CERR(3) 3001 ; 3002 3003 sqtd = prev = NULL; 3004 size_t curoffs = 0; 3005 size_t j = 0; 3006 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3007 sqtd = exfer->ex_sqtds[j++]; 3008 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3009 (uintptr_t)prev, 0); 3010 3011 /* 3012 * The EHCI hardware can handle at most 5 pages and they do 3013 * not have to be contiguous 3014 */ 3015 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3016 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3017 size_t curlen = len; 3018 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3019 /* must use multiple TDs, fill as much as possible. */ 3020 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3021 3022 /* the length must be a multiple of the max size */ 3023 curlen -= curlen % mps; 3024 } 3025 KASSERT(curlen != 0); 3026 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3027 curoffs, 0); 3028 3029 /* Fill the qTD */ 3030 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3031 sqtd->qtd.qtd_status = htole32( 3032 qtdstatus | 3033 EHCI_QTD_SET_BYTES(curlen) | 3034 EHCI_QTD_SET_TOGGLE(tog)); 3035 3036 /* Find number of pages we'll be using, insert dma addresses */ 3037 size_t pages = EHCI_NPAGES(curlen); 3038 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3039 size_t pageoffs = EHCI_PAGE(curoffs); 3040 for (size_t i = 0; i < pages; i++) { 3041 paddr_t a = DMAADDR(dma, 3042 pageoffs + i * EHCI_PAGE_SIZE); 3043 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 3044 /* Cast up to avoid compiler warnings */ 3045 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 3046 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3047 i, pages, 3048 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3049 le32toh(sqtd->qtd.qtd_buffer[i])); 3050 } 3051 /* First buffer pointer requires a page offset to start at */ 3052 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3053 3054 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3055 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3056 3057 sqtd->len = curlen; 3058 3059 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3060 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3061 3062 ehci_append_sqtd(sqtd, prev); 3063 3064 if (howmany(curlen, mps) & 1) { 3065 tog ^= 1; 3066 } 3067 3068 curoffs += curlen; 3069 len -= curlen; 3070 } 3071 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3072 xfer, length, len, mps, exfer->ex_nsqtd, j); 3073 3074 if (!isread && 3075 (flags & USBD_FORCE_SHORT_XFER) && 3076 length % mps == 0) { 3077 /* Force a 0 length transfer at the end. */ 3078 3079 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3080 exfer->ex_nsqtd); 3081 prev = sqtd; 3082 sqtd = exfer->ex_sqtds[j++]; 3083 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3084 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3085 sqtd->qtd.qtd_status = htole32( 3086 qtdstatus | 3087 EHCI_QTD_SET_BYTES(0) | 3088 EHCI_QTD_SET_TOGGLE(tog)); 3089 3090 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3091 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3092 3093 ehci_append_sqtd(sqtd, prev); 3094 tog ^= 1; 3095 } 3096 3097 *lsqtd = sqtd; 3098 *toggle = tog; 3099 } 3100 3101 Static ehci_soft_itd_t * 3102 ehci_alloc_itd(ehci_softc_t *sc) 3103 { 3104 struct ehci_soft_itd *itd, *freeitd; 3105 usbd_status err; 3106 usb_dma_t dma; 3107 3108 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3109 3110 mutex_enter(&sc->sc_lock); 3111 3112 freeitd = LIST_FIRST(&sc->sc_freeitds); 3113 if (freeitd == NULL) { 3114 DPRINTF("allocating chunk", 0, 0, 0, 0); 3115 mutex_exit(&sc->sc_lock); 3116 3117 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3118 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3119 3120 if (err) { 3121 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3122 return NULL; 3123 } 3124 mutex_enter(&sc->sc_lock); 3125 3126 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3127 int offs = i * EHCI_ITD_SIZE; 3128 itd = KERNADDR(&dma, offs); 3129 itd->physaddr = DMAADDR(&dma, offs); 3130 itd->dma = dma; 3131 itd->offs = offs; 3132 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3133 } 3134 freeitd = LIST_FIRST(&sc->sc_freeitds); 3135 } 3136 3137 itd = freeitd; 3138 LIST_REMOVE(itd, free_list); 3139 mutex_exit(&sc->sc_lock); 3140 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3141 3142 itd->frame_list.next = NULL; 3143 itd->frame_list.prev = NULL; 3144 itd->xfer_next = NULL; 3145 itd->slot = 0; 3146 3147 return itd; 3148 } 3149 3150 Static ehci_soft_sitd_t * 3151 ehci_alloc_sitd(ehci_softc_t *sc) 3152 { 3153 struct ehci_soft_sitd *sitd, *freesitd; 3154 usbd_status err; 3155 int i, offs; 3156 usb_dma_t dma; 3157 3158 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3159 3160 mutex_enter(&sc->sc_lock); 3161 freesitd = LIST_FIRST(&sc->sc_freesitds); 3162 if (freesitd == NULL) { 3163 DPRINTF("allocating chunk", 0, 0, 0, 0); 3164 mutex_exit(&sc->sc_lock); 3165 3166 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3167 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3168 3169 if (err) { 3170 DPRINTF("alloc returned %jd", err, 0, 0, 3171 0); 3172 return NULL; 3173 } 3174 3175 mutex_enter(&sc->sc_lock); 3176 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3177 offs = i * EHCI_SITD_SIZE; 3178 sitd = KERNADDR(&dma, offs); 3179 sitd->physaddr = DMAADDR(&dma, offs); 3180 sitd->dma = dma; 3181 sitd->offs = offs; 3182 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3183 } 3184 freesitd = LIST_FIRST(&sc->sc_freesitds); 3185 } 3186 3187 sitd = freesitd; 3188 LIST_REMOVE(sitd, free_list); 3189 mutex_exit(&sc->sc_lock); 3190 3191 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3192 3193 sitd->frame_list.next = NULL; 3194 sitd->frame_list.prev = NULL; 3195 sitd->xfer_next = NULL; 3196 sitd->slot = 0; 3197 3198 return sitd; 3199 } 3200 3201 /****************/ 3202 3203 /* 3204 * Close a reqular pipe. 3205 * Assumes that there are no pending transactions. 3206 */ 3207 Static void 3208 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3209 { 3210 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3211 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3212 ehci_soft_qh_t *sqh = epipe->sqh; 3213 3214 KASSERT(mutex_owned(&sc->sc_lock)); 3215 3216 ehci_rem_qh(sc, sqh, head); 3217 ehci_free_sqh(sc, epipe->sqh); 3218 } 3219 3220 /* 3221 * Arrrange for the hardware to tells us that it is not still 3222 * processing the TDs by setting the QH halted bit and wait for the ehci 3223 * door bell 3224 */ 3225 Static void 3226 ehci_abortx(struct usbd_xfer *xfer) 3227 { 3228 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3229 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3230 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3231 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3232 ehci_soft_qh_t *sqh = epipe->sqh; 3233 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3234 ehci_physaddr_t cur; 3235 uint32_t qhstatus; 3236 int hit; 3237 3238 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3239 3240 KASSERT(mutex_owned(&sc->sc_lock)); 3241 ASSERT_SLEEPABLE(); 3242 3243 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3244 xfer->ux_status == USBD_TIMEOUT), 3245 "bad abort status: %d", xfer->ux_status); 3246 3247 /* 3248 * If we're dying, skip the hardware action and just notify the 3249 * software that we're done. 3250 */ 3251 if (sc->sc_dying) { 3252 goto dying; 3253 } 3254 3255 /* 3256 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3257 */ 3258 ehci_del_intr_list(sc, exfer); 3259 3260 usb_syncmem(&sqh->dma, 3261 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3262 sizeof(sqh->qh.qh_qtd.qtd_status), 3263 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3264 qhstatus = sqh->qh.qh_qtd.qtd_status; 3265 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3266 usb_syncmem(&sqh->dma, 3267 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3268 sizeof(sqh->qh.qh_qtd.qtd_status), 3269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3270 3271 if (exfer->ex_type == EX_CTRL) { 3272 fsqtd = exfer->ex_setup; 3273 lsqtd = exfer->ex_status; 3274 } else { 3275 fsqtd = exfer->ex_sqtdstart; 3276 lsqtd = exfer->ex_sqtdend; 3277 } 3278 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3279 usb_syncmem(&sqtd->dma, 3280 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3281 sizeof(sqtd->qtd.qtd_status), 3282 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3283 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3284 usb_syncmem(&sqtd->dma, 3285 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3286 sizeof(sqtd->qtd.qtd_status), 3287 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3288 if (sqtd == lsqtd) 3289 break; 3290 } 3291 3292 /* 3293 * HC Step 2: Wait until we know hardware has finished any possible 3294 * use of the xfer. 3295 */ 3296 ehci_sync_hc(sc); 3297 3298 /* 3299 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3300 * The complication here is that the hardware may have executed 3301 * beyond the xfer we're trying to abort. So as we're scanning 3302 * the TDs of this xfer we check if the hardware points to 3303 * any of them. 3304 */ 3305 3306 usb_syncmem(&sqh->dma, 3307 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3308 sizeof(sqh->qh.qh_curqtd), 3309 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3310 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3311 hit = 0; 3312 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3313 hit |= cur == sqtd->physaddr; 3314 if (sqtd == lsqtd) 3315 break; 3316 } 3317 sqtd = sqtd->nextqtd; 3318 /* Zap curqtd register if hardware pointed inside the xfer. */ 3319 if (hit && sqtd != NULL) { 3320 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3321 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3322 usb_syncmem(&sqh->dma, 3323 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3324 sizeof(sqh->qh.qh_curqtd), 3325 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3326 sqh->qh.qh_qtd.qtd_status = qhstatus; 3327 usb_syncmem(&sqh->dma, 3328 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3329 sizeof(sqh->qh.qh_qtd.qtd_status), 3330 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3331 } else { 3332 DPRINTF("no hit", 0, 0, 0, 0); 3333 usb_syncmem(&sqh->dma, 3334 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3335 sizeof(sqh->qh.qh_curqtd), 3336 BUS_DMASYNC_PREREAD); 3337 } 3338 3339 /* 3340 * Final step: Notify completion to waiting xfers. 3341 */ 3342 dying: 3343 #ifdef DIAGNOSTIC 3344 exfer->ex_isdone = true; 3345 #endif 3346 usb_transfer_complete(xfer); 3347 DPRINTFN(14, "end", 0, 0, 0, 0); 3348 3349 KASSERT(mutex_owned(&sc->sc_lock)); 3350 } 3351 3352 Static void 3353 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3354 { 3355 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3356 ehci_isoc_trans_t trans_status; 3357 struct ehci_xfer *exfer; 3358 ehci_softc_t *sc; 3359 struct ehci_soft_itd *itd; 3360 struct ehci_soft_sitd *sitd; 3361 int i; 3362 3363 KASSERTMSG(status == USBD_CANCELLED, 3364 "invalid status for abort: %d", (int)status); 3365 3366 exfer = EHCI_XFER2EXFER(xfer); 3367 sc = EHCI_XFER2SC(xfer); 3368 3369 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3370 (uintptr_t)xfer->ux_pipe, 0, 0); 3371 3372 KASSERT(mutex_owned(&sc->sc_lock)); 3373 ASSERT_SLEEPABLE(); 3374 3375 /* No timeout or task here. */ 3376 3377 /* 3378 * The xfer cannot have been cancelled already. It is the 3379 * responsibility of the caller of usbd_abort_pipe not to try 3380 * to abort a pipe multiple times, whether concurrently or 3381 * sequentially. 3382 */ 3383 KASSERT(xfer->ux_status != USBD_CANCELLED); 3384 3385 /* If anyone else beat us, we're done. */ 3386 if (xfer->ux_status != USBD_IN_PROGRESS) 3387 return; 3388 3389 /* We beat everyone else. Claim the status. */ 3390 xfer->ux_status = status; 3391 3392 /* 3393 * If we're dying, skip the hardware action and just notify the 3394 * software that we're done. 3395 */ 3396 if (sc->sc_dying) { 3397 goto dying; 3398 } 3399 3400 /* 3401 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3402 */ 3403 ehci_del_intr_list(sc, exfer); 3404 3405 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3406 for (itd = exfer->ex_itdstart; itd != NULL; 3407 itd = itd->xfer_next) { 3408 usb_syncmem(&itd->dma, 3409 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3410 sizeof(itd->itd.itd_ctl), 3411 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3412 3413 for (i = 0; i < 8; i++) { 3414 trans_status = le32toh(itd->itd.itd_ctl[i]); 3415 trans_status &= ~EHCI_ITD_ACTIVE; 3416 itd->itd.itd_ctl[i] = htole32(trans_status); 3417 } 3418 3419 usb_syncmem(&itd->dma, 3420 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3421 sizeof(itd->itd.itd_ctl), 3422 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3423 } 3424 } else { 3425 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3426 sitd = sitd->xfer_next) { 3427 usb_syncmem(&sitd->dma, 3428 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3429 sizeof(sitd->sitd.sitd_buffer), 3430 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3431 3432 trans_status = le32toh(sitd->sitd.sitd_trans); 3433 trans_status &= ~EHCI_SITD_ACTIVE; 3434 sitd->sitd.sitd_trans = htole32(trans_status); 3435 3436 usb_syncmem(&sitd->dma, 3437 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3438 sizeof(sitd->sitd.sitd_buffer), 3439 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3440 } 3441 } 3442 3443 dying: 3444 #ifdef DIAGNOSTIC 3445 exfer->ex_isdone = true; 3446 #endif 3447 usb_transfer_complete(xfer); 3448 DPRINTFN(14, "end", 0, 0, 0, 0); 3449 3450 KASSERT(mutex_owned(&sc->sc_lock)); 3451 } 3452 3453 /************************/ 3454 3455 Static int 3456 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3457 { 3458 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3459 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3460 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3461 usb_device_request_t *req = &xfer->ux_request; 3462 ehci_soft_qtd_t *setup, *status, *next; 3463 int isread = req->bmRequestType & UT_READ; 3464 int len = xfer->ux_bufsize; 3465 int err; 3466 3467 exfer->ex_type = EX_CTRL; 3468 exfer->ex_status = NULL; 3469 exfer->ex_data = NULL; 3470 exfer->ex_setup = ehci_alloc_sqtd(sc); 3471 if (exfer->ex_setup == NULL) { 3472 err = ENOMEM; 3473 goto bad1; 3474 } 3475 exfer->ex_status = ehci_alloc_sqtd(sc); 3476 if (exfer->ex_status == NULL) { 3477 err = ENOMEM; 3478 goto bad2; 3479 } 3480 setup = exfer->ex_setup; 3481 status = exfer->ex_status; 3482 exfer->ex_nsqtd = 0; 3483 next = status; 3484 /* Set up data transaction */ 3485 if (len != 0) { 3486 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3487 &exfer->ex_data); 3488 if (err) 3489 goto bad3; 3490 next = exfer->ex_data; 3491 } 3492 3493 /* Clear toggle */ 3494 setup->qtd.qtd_status = htole32( 3495 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3496 EHCI_QTD_SET_TOGGLE(0) | 3497 EHCI_QTD_SET_BYTES(sizeof(*req)) 3498 ); 3499 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3500 setup->qtd.qtd_buffer_hi[0] = 0; 3501 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3502 setup->nextqtd = next; 3503 setup->xfer = xfer; 3504 setup->len = sizeof(*req); 3505 3506 status->qtd.qtd_status = htole32( 3507 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3508 EHCI_QTD_SET_TOGGLE(1) | 3509 EHCI_QTD_IOC 3510 ); 3511 status->qtd.qtd_buffer[0] = 0; 3512 status->qtd.qtd_buffer_hi[0] = 0; 3513 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3514 status->nextqtd = NULL; 3515 status->xfer = xfer; 3516 status->len = 0; 3517 3518 return 0; 3519 bad3: 3520 ehci_free_sqtd(sc, exfer->ex_status); 3521 bad2: 3522 ehci_free_sqtd(sc, exfer->ex_setup); 3523 bad1: 3524 return err; 3525 } 3526 3527 Static void 3528 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3529 { 3530 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3531 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3532 3533 KASSERT(ex->ex_type == EX_CTRL); 3534 3535 ehci_free_sqtd(sc, ex->ex_setup); 3536 ehci_free_sqtd(sc, ex->ex_status); 3537 ehci_free_sqtds(sc, ex); 3538 if (ex->ex_nsqtd) 3539 kmem_free(ex->ex_sqtds, 3540 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3541 } 3542 3543 Static usbd_status 3544 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3545 { 3546 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3547 usbd_status err; 3548 3549 /* Insert last in queue. */ 3550 mutex_enter(&sc->sc_lock); 3551 err = usb_insert_transfer(xfer); 3552 mutex_exit(&sc->sc_lock); 3553 if (err) 3554 return err; 3555 3556 /* Pipe isn't running, start first */ 3557 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3558 } 3559 3560 Static usbd_status 3561 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3562 { 3563 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3564 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3565 usb_device_request_t *req = &xfer->ux_request; 3566 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3567 ehci_soft_qtd_t *setup, *status, *next; 3568 ehci_soft_qh_t *sqh; 3569 const bool polling = sc->sc_bus.ub_usepolling; 3570 3571 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3572 3573 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3574 3575 if (sc->sc_dying) 3576 return USBD_IOERROR; 3577 3578 const int isread = req->bmRequestType & UT_READ; 3579 const int len = UGETW(req->wLength); 3580 3581 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3582 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3583 UGETW(req->wIndex)); 3584 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3585 len, epipe->pipe.up_dev->ud_addr, 3586 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3587 3588 sqh = epipe->sqh; 3589 3590 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3591 "address QH %" __PRIuBIT " pipe %d\n", 3592 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3593 epipe->pipe.up_dev->ud_addr); 3594 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3595 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3596 "MPS QH %" __PRIuBIT " pipe %d\n", 3597 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3598 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3599 3600 setup = exfer->ex_setup; 3601 status = exfer->ex_status; 3602 3603 DPRINTF("setup %#jx status %#jx data %#jx", 3604 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3605 KASSERTMSG(setup != NULL && status != NULL, 3606 "Failed memory allocation, setup %p status %p", 3607 setup, status); 3608 3609 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3610 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3611 3612 /* Clear toggle */ 3613 setup->qtd.qtd_status &= ~htole32( 3614 EHCI_QTD_STATUS_MASK | 3615 EHCI_QTD_BYTES_MASK | 3616 EHCI_QTD_TOGGLE_MASK | 3617 EHCI_QTD_CERR_MASK 3618 ); 3619 setup->qtd.qtd_status |= htole32( 3620 EHCI_QTD_ACTIVE | 3621 EHCI_QTD_SET_CERR(3) | 3622 EHCI_QTD_SET_TOGGLE(0) | 3623 EHCI_QTD_SET_BYTES(sizeof(*req)) 3624 ); 3625 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3626 setup->qtd.qtd_buffer_hi[0] = 0; 3627 3628 next = status; 3629 status->qtd.qtd_status &= ~htole32( 3630 EHCI_QTD_STATUS_MASK | 3631 EHCI_QTD_PID_MASK | 3632 EHCI_QTD_BYTES_MASK | 3633 EHCI_QTD_TOGGLE_MASK | 3634 EHCI_QTD_CERR_MASK 3635 ); 3636 status->qtd.qtd_status |= htole32( 3637 EHCI_QTD_ACTIVE | 3638 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3639 EHCI_QTD_SET_CERR(3) | 3640 EHCI_QTD_SET_TOGGLE(1) | 3641 EHCI_QTD_SET_BYTES(0) | 3642 EHCI_QTD_IOC 3643 ); 3644 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3645 3646 KASSERT(exfer->ex_isdone); 3647 #ifdef DIAGNOSTIC 3648 exfer->ex_isdone = false; 3649 #endif 3650 3651 /* Set up data transaction */ 3652 if (len != 0) { 3653 ehci_soft_qtd_t *end; 3654 3655 /* Start toggle at 1. */ 3656 int toggle = 1; 3657 next = exfer->ex_data; 3658 KASSERTMSG(next != NULL, "Failed memory allocation"); 3659 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3660 end->nextqtd = status; 3661 end->qtd.qtd_next = end->qtd.qtd_altnext = 3662 htole32(status->physaddr); 3663 3664 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3665 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3666 3667 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3668 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3669 } 3670 3671 setup->nextqtd = next; 3672 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3673 3674 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3675 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3676 3677 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3678 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3679 3680 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3681 3682 #ifdef EHCI_DEBUG 3683 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3684 ehci_dump_sqh(sqh); 3685 ehci_dump_sqtds(setup); 3686 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3687 #endif 3688 3689 if (!polling) 3690 mutex_enter(&sc->sc_lock); 3691 3692 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3693 ehci_set_qh_qtd(sqh, setup); 3694 usbd_xfer_schedule_timeout(xfer); 3695 ehci_add_intr_list(sc, exfer); 3696 xfer->ux_status = USBD_IN_PROGRESS; 3697 if (!polling) 3698 mutex_exit(&sc->sc_lock); 3699 3700 #if 0 3701 #ifdef EHCI_DEBUG 3702 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3703 // delay(10000); 3704 ehci_dump_regs(sc); 3705 ehci_dump_sqh(sc->sc_async_head); 3706 ehci_dump_sqh(sqh); 3707 ehci_dump_sqtds(setup); 3708 #endif 3709 #endif 3710 3711 return USBD_IN_PROGRESS; 3712 } 3713 3714 Static void 3715 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3716 { 3717 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3718 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3719 usb_device_request_t *req = &xfer->ux_request; 3720 int len = UGETW(req->wLength); 3721 int rd = req->bmRequestType & UT_READ; 3722 3723 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3724 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3725 3726 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3727 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3728 3729 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3730 BUS_DMASYNC_POSTWRITE); 3731 if (len) 3732 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3733 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3734 3735 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3736 } 3737 3738 /* Abort a device control request. */ 3739 Static void 3740 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3741 { 3742 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3743 3744 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3745 usbd_xfer_abort(xfer); 3746 } 3747 3748 /* Close a device control pipe. */ 3749 Static void 3750 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3751 { 3752 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3753 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3754 3755 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3756 3757 KASSERT(mutex_owned(&sc->sc_lock)); 3758 3759 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3760 3761 ehci_close_pipe(pipe, sc->sc_async_head); 3762 3763 usb_freemem(&sc->sc_bus, &epipe->ctrl.reqdma); 3764 } 3765 3766 /* 3767 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3768 * qTD status, or miss signalling occasionally under heavy load. If the host 3769 * machine is too fast, we we can miss transaction completion - when we scan 3770 * the active list the transaction still seems to be active. This generally 3771 * exhibits itself as a umass stall that never recovers. 3772 * 3773 * We work around this behaviour by setting up this callback after any softintr 3774 * that completes with transactions still pending, giving us another chance to 3775 * check for completion after the writeback has taken place. 3776 */ 3777 Static void 3778 ehci_intrlist_timeout(void *arg) 3779 { 3780 ehci_softc_t *sc = arg; 3781 3782 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3783 3784 usb_schedsoftintr(&sc->sc_bus); 3785 } 3786 3787 /************************/ 3788 3789 Static int 3790 ehci_device_bulk_init(struct usbd_xfer *xfer) 3791 { 3792 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3793 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3794 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3795 int endpt = ed->bEndpointAddress; 3796 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3797 int len = xfer->ux_bufsize; 3798 int err = 0; 3799 3800 exfer->ex_type = EX_BULK; 3801 exfer->ex_nsqtd = 0; 3802 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3803 &exfer->ex_sqtdstart); 3804 3805 return err; 3806 } 3807 3808 Static void 3809 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3810 { 3811 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3812 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3813 3814 KASSERT(ex->ex_type == EX_BULK); 3815 3816 ehci_free_sqtds(sc, ex); 3817 if (ex->ex_nsqtd) 3818 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3819 } 3820 3821 Static usbd_status 3822 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3823 { 3824 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3825 usbd_status err; 3826 3827 /* Insert last in queue. */ 3828 mutex_enter(&sc->sc_lock); 3829 err = usb_insert_transfer(xfer); 3830 mutex_exit(&sc->sc_lock); 3831 if (err) 3832 return err; 3833 3834 /* Pipe isn't running, start first */ 3835 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3836 } 3837 3838 Static usbd_status 3839 ehci_device_bulk_start(struct usbd_xfer *xfer) 3840 { 3841 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3842 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3843 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3844 ehci_soft_qh_t *sqh; 3845 ehci_soft_qtd_t *end; 3846 int len, isread, endpt; 3847 const bool polling = sc->sc_bus.ub_usepolling; 3848 3849 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3850 3851 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3852 xfer->ux_flags, 0); 3853 3854 if (sc->sc_dying) 3855 return USBD_IOERROR; 3856 3857 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3858 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3859 3860 len = xfer->ux_length; 3861 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3862 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3863 sqh = epipe->sqh; 3864 3865 KASSERT(exfer->ex_isdone); 3866 #ifdef DIAGNOSTIC 3867 exfer->ex_isdone = false; 3868 #endif 3869 3870 /* Take lock here to protect nexttoggle */ 3871 if (!polling) 3872 mutex_enter(&sc->sc_lock); 3873 3874 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3875 3876 exfer->ex_sqtdend = end; 3877 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3878 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3879 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3880 3881 #ifdef EHCI_DEBUG 3882 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3883 ehci_dump_sqh(sqh); 3884 ehci_dump_sqtds(exfer->ex_sqtdstart); 3885 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3886 #endif 3887 3888 if (xfer->ux_length) 3889 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3890 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3891 3892 /* also does usb_syncmem(sqh) */ 3893 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3894 usbd_xfer_schedule_timeout(xfer); 3895 ehci_add_intr_list(sc, exfer); 3896 xfer->ux_status = USBD_IN_PROGRESS; 3897 if (!polling) 3898 mutex_exit(&sc->sc_lock); 3899 3900 #if 0 3901 #ifdef EHCI_DEBUG 3902 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3903 // delay(10000); 3904 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3905 ehci_dump_regs(sc); 3906 #if 0 3907 printf("async_head:\n"); 3908 ehci_dump_sqh(sc->sc_async_head); 3909 #endif 3910 DPRINTF("sqh:", 0, 0, 0, 0); 3911 ehci_dump_sqh(sqh); 3912 ehci_dump_sqtds(exfer->ex_sqtdstart); 3913 #endif 3914 #endif 3915 3916 return USBD_IN_PROGRESS; 3917 } 3918 3919 Static void 3920 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3921 { 3922 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3923 3924 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3925 usbd_xfer_abort(xfer); 3926 } 3927 3928 /* 3929 * Close a device bulk pipe. 3930 */ 3931 Static void 3932 ehci_device_bulk_close(struct usbd_pipe *pipe) 3933 { 3934 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3935 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3936 3937 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3938 3939 KASSERT(mutex_owned(&sc->sc_lock)); 3940 3941 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3942 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3943 ehci_close_pipe(pipe, sc->sc_async_head); 3944 } 3945 3946 Static void 3947 ehci_device_bulk_done(struct usbd_xfer *xfer) 3948 { 3949 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3950 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3951 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3952 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3953 3954 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3955 3956 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 3957 3958 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3959 3960 if (xfer->ux_length) 3961 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3962 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3963 3964 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3965 } 3966 3967 /************************/ 3968 3969 Static usbd_status 3970 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3971 { 3972 struct ehci_soft_islot *isp; 3973 int islot, lev; 3974 3975 /* Find a poll rate that is large enough. */ 3976 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3977 if (EHCI_ILEV_IVAL(lev) <= ival) 3978 break; 3979 3980 /* Pick an interrupt slot at the right level. */ 3981 /* XXX could do better than picking at random */ 3982 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3983 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3984 3985 sqh->islot = islot; 3986 isp = &sc->sc_islots[islot]; 3987 mutex_enter(&sc->sc_lock); 3988 ehci_add_qh(sc, sqh, isp->sqh); 3989 mutex_exit(&sc->sc_lock); 3990 3991 return USBD_NORMAL_COMPLETION; 3992 } 3993 3994 Static int 3995 ehci_device_intr_init(struct usbd_xfer *xfer) 3996 { 3997 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3998 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3999 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4000 int endpt = ed->bEndpointAddress; 4001 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4002 int len = xfer->ux_bufsize; 4003 int err; 4004 4005 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4006 4007 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4008 xfer->ux_flags, 0); 4009 4010 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4011 KASSERT(len != 0); 4012 4013 exfer->ex_type = EX_INTR; 4014 exfer->ex_nsqtd = 0; 4015 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4016 &exfer->ex_sqtdstart); 4017 4018 return err; 4019 } 4020 4021 Static void 4022 ehci_device_intr_fini(struct usbd_xfer *xfer) 4023 { 4024 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4025 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4026 4027 KASSERT(ex->ex_type == EX_INTR); 4028 4029 ehci_free_sqtds(sc, ex); 4030 if (ex->ex_nsqtd) 4031 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4032 } 4033 4034 Static usbd_status 4035 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4036 { 4037 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4038 usbd_status err; 4039 4040 /* Insert last in queue. */ 4041 mutex_enter(&sc->sc_lock); 4042 err = usb_insert_transfer(xfer); 4043 mutex_exit(&sc->sc_lock); 4044 if (err) 4045 return err; 4046 4047 /* 4048 * Pipe isn't running (otherwise err would be USBD_INPROG), 4049 * so start it first. 4050 */ 4051 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4052 } 4053 4054 Static usbd_status 4055 ehci_device_intr_start(struct usbd_xfer *xfer) 4056 { 4057 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4058 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4059 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4060 ehci_soft_qtd_t *end; 4061 ehci_soft_qh_t *sqh; 4062 int len, isread, endpt; 4063 const bool polling = sc->sc_bus.ub_usepolling; 4064 4065 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4066 4067 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4068 xfer->ux_flags, 0); 4069 4070 if (sc->sc_dying) 4071 return USBD_IOERROR; 4072 4073 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4074 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4075 4076 len = xfer->ux_length; 4077 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4078 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4079 sqh = epipe->sqh; 4080 4081 KASSERT(exfer->ex_isdone); 4082 #ifdef DIAGNOSTIC 4083 exfer->ex_isdone = false; 4084 #endif 4085 4086 /* Take lock to protect nexttoggle */ 4087 if (!polling) 4088 mutex_enter(&sc->sc_lock); 4089 4090 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4091 4092 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4093 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4094 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4095 exfer->ex_sqtdend = end; 4096 4097 #ifdef EHCI_DEBUG 4098 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4099 ehci_dump_sqh(sqh); 4100 ehci_dump_sqtds(exfer->ex_sqtdstart); 4101 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4102 #endif 4103 4104 if (xfer->ux_length) 4105 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4106 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4107 4108 /* also does usb_syncmem(sqh) */ 4109 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4110 usbd_xfer_schedule_timeout(xfer); 4111 ehci_add_intr_list(sc, exfer); 4112 xfer->ux_status = USBD_IN_PROGRESS; 4113 if (!polling) 4114 mutex_exit(&sc->sc_lock); 4115 4116 #if 0 4117 #ifdef EHCI_DEBUG 4118 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4119 // delay(10000); 4120 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4121 ehci_dump_regs(sc); 4122 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4123 ehci_dump_sqh(sqh); 4124 ehci_dump_sqtds(exfer->ex_sqtdstart); 4125 #endif 4126 #endif 4127 4128 return USBD_IN_PROGRESS; 4129 } 4130 4131 Static void 4132 ehci_device_intr_abort(struct usbd_xfer *xfer) 4133 { 4134 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4135 4136 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4137 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4138 4139 /* 4140 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4141 * async doorbell. That's dependent on the async list, wheras 4142 * intr xfers are periodic, should not use this? 4143 */ 4144 usbd_xfer_abort(xfer); 4145 } 4146 4147 Static void 4148 ehci_device_intr_close(struct usbd_pipe *pipe) 4149 { 4150 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4151 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4152 struct ehci_soft_islot *isp; 4153 4154 KASSERT(mutex_owned(&sc->sc_lock)); 4155 4156 isp = &sc->sc_islots[epipe->sqh->islot]; 4157 ehci_close_pipe(pipe, isp->sqh); 4158 } 4159 4160 Static void 4161 ehci_device_intr_done(struct usbd_xfer *xfer) 4162 { 4163 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4164 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4165 4166 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4167 4168 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4169 4170 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4171 4172 if (xfer->ux_length) { 4173 int isread, endpt; 4174 4175 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4176 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4177 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4178 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4179 } 4180 } 4181 4182 /************************/ 4183 Static int 4184 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4185 { 4186 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4187 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4188 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4189 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4190 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4191 int i, k, frames; 4192 u_int huba, dir; 4193 int err; 4194 4195 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4196 4197 start = NULL; 4198 sitd = NULL; 4199 4200 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4201 xfer->ux_flags, 0); 4202 4203 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4204 KASSERT(xfer->ux_nframes != 0); 4205 KASSERT(exfer->ex_isdone); 4206 4207 exfer->ex_type = EX_FS_ISOC; 4208 /* 4209 * Step 1: Allocate and initialize sitds. 4210 */ 4211 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4212 if (i > 16 || i == 0) { 4213 /* Spec page 271 says intervals > 16 are invalid */ 4214 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4215 4216 return EINVAL; 4217 } 4218 4219 frames = xfer->ux_nframes; 4220 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4221 sitd = ehci_alloc_sitd(sc); 4222 if (sitd == NULL) { 4223 err = ENOMEM; 4224 goto fail; 4225 } 4226 4227 if (prev) 4228 prev->xfer_next = sitd; 4229 else 4230 start = sitd; 4231 4232 huba = dev->ud_myhsport->up_parent->ud_addr; 4233 4234 #if 0 4235 if (sc->sc_flags & EHCIF_FREESCALE) { 4236 // Set hub address to 0 if embedded TT is used. 4237 if (huba == sc->sc_addr) 4238 huba = 0; 4239 } 4240 #endif 4241 4242 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4243 dir = UE_GET_DIR(k) ? 1 : 0; 4244 sitd->sitd.sitd_endp = 4245 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4246 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4247 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4248 EHCI_SITD_SET_HUBA(huba) | 4249 EHCI_SITD_SET_DIR(dir)); 4250 4251 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4252 } /* End of frame */ 4253 4254 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4255 4256 stop = sitd; 4257 stop->xfer_next = NULL; 4258 exfer->ex_sitdstart = start; 4259 exfer->ex_sitdend = stop; 4260 4261 return 0; 4262 4263 fail: 4264 mutex_enter(&sc->sc_lock); 4265 ehci_soft_sitd_t *next; 4266 for (sitd = start; sitd; sitd = next) { 4267 next = sitd->xfer_next; 4268 ehci_free_sitd_locked(sc, sitd); 4269 } 4270 mutex_exit(&sc->sc_lock); 4271 4272 return err; 4273 } 4274 4275 Static void 4276 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4277 { 4278 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4279 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4280 4281 KASSERT(ex->ex_type == EX_FS_ISOC); 4282 4283 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4284 } 4285 4286 Static usbd_status 4287 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4288 { 4289 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4290 usbd_status __diagused err; 4291 4292 mutex_enter(&sc->sc_lock); 4293 err = usb_insert_transfer(xfer); 4294 mutex_exit(&sc->sc_lock); 4295 4296 KASSERT(err == USBD_NORMAL_COMPLETION); 4297 4298 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4299 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4300 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4301 ehci_soft_sitd_t *sitd; 4302 usb_dma_t *dma_buf; 4303 int i, j, k, frames; 4304 int offs, total_length; 4305 int frindex; 4306 u_int dir; 4307 4308 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4309 4310 sitd = NULL; 4311 total_length = 0; 4312 4313 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4314 xfer->ux_flags, 0); 4315 4316 if (sc->sc_dying) 4317 return USBD_IOERROR; 4318 4319 /* 4320 * To avoid complication, don't allow a request right now that'll span 4321 * the entire frame table. To within 4 frames, to allow some leeway 4322 * on either side of where the hc currently is. 4323 */ 4324 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4325 xfer->ux_nframes >= sc->sc_flsize - 4) { 4326 printf("ehci: isoc descriptor requested that spans the entire" 4327 "frametable, too many frames\n"); 4328 return USBD_INVAL; 4329 } 4330 4331 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4332 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4333 KASSERT(exfer->ex_isdone); 4334 #ifdef DIAGNOSTIC 4335 exfer->ex_isdone = false; 4336 #endif 4337 4338 /* 4339 * Step 1: Initialize sitds. 4340 */ 4341 4342 frames = xfer->ux_nframes; 4343 dma_buf = &xfer->ux_dmabuf; 4344 offs = 0; 4345 4346 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4347 i++, sitd = sitd->xfer_next) { 4348 KASSERT(sitd != NULL); 4349 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4350 4351 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4352 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4353 4354 /* Set page0 index and offset - TP and T-offset are set below */ 4355 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4356 4357 total_length += xfer->ux_frlengths[i]; 4358 offs += xfer->ux_frlengths[i]; 4359 4360 sitd->sitd.sitd_buffer[1] = 4361 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4362 4363 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4364 4365 #if 0 4366 if (sc->sc_flags & EHCIF_FREESCALE) { 4367 // Set hub address to 0 if embedded TT is used. 4368 if (huba == sc->sc_addr) 4369 huba = 0; 4370 } 4371 #endif 4372 4373 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4374 dir = UE_GET_DIR(k) ? 1 : 0; 4375 KASSERT(sitd->sitd.sitd_endp == htole32( 4376 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4377 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4378 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4379 EHCI_SITD_SET_HUBA(huba) | 4380 EHCI_SITD_SET_DIR(dir))); 4381 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4382 4383 uint8_t sa = 0; 4384 uint8_t sb = 0; 4385 u_int temp, tlen; 4386 4387 if (dir == 0) { /* OUT */ 4388 temp = 0; 4389 tlen = xfer->ux_frlengths[i]; 4390 if (tlen <= 188) { 4391 temp |= 1; /* T-count = 1, TP = ALL */ 4392 tlen = 1; 4393 } else { 4394 tlen += 187; 4395 tlen /= 188; 4396 temp |= tlen; /* T-count = [1..6] */ 4397 temp |= 8; /* TP = Begin */ 4398 } 4399 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4400 4401 tlen += sa; 4402 4403 if (tlen >= 8) { 4404 sb = 0; 4405 } else { 4406 sb = (1 << tlen); 4407 } 4408 4409 sa = (1 << sa); 4410 sa = (sb - sa) & 0x3F; 4411 sb = 0; 4412 } else { 4413 sb = (-(4 << sa)) & 0xFE; 4414 sa = (1 << sa) & 0x3F; 4415 sa = 0x01; 4416 sb = 0xfc; 4417 } 4418 4419 sitd->sitd.sitd_sched = htole32( 4420 EHCI_SITD_SET_SMASK(sa) | 4421 EHCI_SITD_SET_CMASK(sb) 4422 ); 4423 4424 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4425 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4426 } /* End of frame */ 4427 4428 sitd = exfer->ex_sitdend; 4429 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4430 4431 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4432 sizeof(sitd->sitd.sitd_trans), 4433 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4434 4435 if (total_length) 4436 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4437 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4438 4439 /* 4440 * Part 2: Transfer descriptors have now been set up, now they must 4441 * be scheduled into the periodic frame list. Erk. Not wanting to 4442 * complicate matters, transfer is denied if the transfer spans 4443 * more than the period frame list. 4444 */ 4445 4446 mutex_enter(&sc->sc_lock); 4447 4448 /* Start inserting frames */ 4449 if (epipe->isoc.cur_xfers > 0) { 4450 frindex = epipe->isoc.next_frame; 4451 } else { 4452 frindex = EOREAD4(sc, EHCI_FRINDEX); 4453 frindex = frindex >> 3; /* Erase microframe index */ 4454 frindex += 2; 4455 } 4456 4457 if (frindex >= sc->sc_flsize) 4458 frindex &= (sc->sc_flsize - 1); 4459 4460 /* Whats the frame interval? */ 4461 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4462 4463 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4464 j++, sitd = sitd->xfer_next) { 4465 KASSERT(sitd); 4466 4467 usb_syncmem(&sc->sc_fldma, 4468 sizeof(ehci_link_t) * frindex, 4469 sizeof(ehci_link_t), 4470 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4471 4472 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4473 if (sitd->sitd.sitd_next == 0) 4474 /* 4475 * FIXME: frindex table gets initialized to NULL 4476 * or EHCI_NULL? 4477 */ 4478 sitd->sitd.sitd_next = EHCI_NULL; 4479 4480 usb_syncmem(&sitd->dma, 4481 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4482 sizeof(ehci_sitd_t), 4483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4484 4485 sc->sc_flist[frindex] = 4486 htole32(EHCI_LINK_SITD | sitd->physaddr); 4487 4488 usb_syncmem(&sc->sc_fldma, 4489 sizeof(ehci_link_t) * frindex, 4490 sizeof(ehci_link_t), 4491 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4492 4493 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4494 sc->sc_softsitds[frindex] = sitd; 4495 if (sitd->frame_list.next != NULL) 4496 sitd->frame_list.next->frame_list.prev = sitd; 4497 sitd->slot = frindex; 4498 sitd->frame_list.prev = NULL; 4499 4500 frindex += i; 4501 if (frindex >= sc->sc_flsize) 4502 frindex -= sc->sc_flsize; 4503 } 4504 4505 epipe->isoc.cur_xfers++; 4506 epipe->isoc.next_frame = frindex; 4507 4508 ehci_add_intr_list(sc, exfer); 4509 xfer->ux_status = USBD_IN_PROGRESS; 4510 mutex_exit(&sc->sc_lock); 4511 4512 return USBD_IN_PROGRESS; 4513 } 4514 4515 Static void 4516 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4517 { 4518 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4519 4520 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4521 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4522 } 4523 4524 Static void 4525 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4526 { 4527 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4528 4529 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4530 } 4531 4532 Static void 4533 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4534 { 4535 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4536 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4537 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4538 4539 KASSERT(mutex_owned(&sc->sc_lock)); 4540 4541 epipe->isoc.cur_xfers--; 4542 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4543 4544 if (xfer->ux_length) 4545 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4546 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4547 } 4548 4549 /* -------------------------------------------------------------------------- */ 4550 4551 Static int 4552 ehci_device_isoc_init(struct usbd_xfer *xfer) 4553 { 4554 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4555 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4556 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4557 ehci_soft_itd_t *itd, *prev, *start, *stop; 4558 int i, j, k; 4559 int frames, ufrperframe; 4560 int err; 4561 4562 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4563 4564 start = NULL; 4565 prev = NULL; 4566 itd = NULL; 4567 4568 KASSERT(xfer->ux_nframes != 0); 4569 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4570 KASSERT(exfer->ex_isdone); 4571 4572 exfer->ex_type = EX_ISOC; 4573 4574 /* 4575 * Step 1: Allocate and initialize itds, how many do we need? 4576 * One per transfer if interval >= 8 microframes, less if we use 4577 * multiple microframes per frame. 4578 */ 4579 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4580 if (i > 16 || i == 0) { 4581 /* Spec page 271 says intervals > 16 are invalid */ 4582 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4583 return USBD_INVAL; 4584 } 4585 4586 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4587 frames = howmany(xfer->ux_nframes, ufrperframe); 4588 4589 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4590 itd = ehci_alloc_itd(sc); 4591 if (itd == NULL) { 4592 err = ENOMEM; 4593 goto fail; 4594 } 4595 4596 if (prev != NULL) { 4597 /* Maybe not as it's updated by the scheduling? */ 4598 prev->itd.itd_next = 4599 htole32(itd->physaddr | EHCI_LINK_ITD); 4600 4601 prev->xfer_next = itd; 4602 } else { 4603 start = itd; 4604 } 4605 4606 /* 4607 * Other special values 4608 */ 4609 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4610 itd->itd.itd_bufr[0] = htole32( 4611 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4612 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4613 4614 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4615 ? 1 : 0; 4616 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4617 itd->itd.itd_bufr[1] |= htole32( 4618 EHCI_ITD_SET_DIR(k) | 4619 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4620 4621 /* FIXME: handle invalid trans - should be done in openpipe */ 4622 itd->itd.itd_bufr[2] |= 4623 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4624 } /* End of frame */ 4625 4626 stop = itd; 4627 stop->xfer_next = NULL; 4628 4629 exfer->ex_itdstart = start; 4630 exfer->ex_itdend = stop; 4631 4632 return 0; 4633 fail: 4634 mutex_enter(&sc->sc_lock); 4635 ehci_soft_itd_t *next; 4636 for (itd = start; itd; itd = next) { 4637 next = itd->xfer_next; 4638 ehci_free_itd_locked(sc, itd); 4639 } 4640 mutex_exit(&sc->sc_lock); 4641 4642 return err; 4643 4644 } 4645 4646 Static void 4647 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4648 { 4649 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4650 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4651 4652 KASSERT(ex->ex_type == EX_ISOC); 4653 4654 ehci_free_itd_chain(sc, ex->ex_itdstart); 4655 } 4656 4657 Static usbd_status 4658 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4659 { 4660 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4661 usbd_status __diagused err; 4662 4663 mutex_enter(&sc->sc_lock); 4664 err = usb_insert_transfer(xfer); 4665 mutex_exit(&sc->sc_lock); 4666 4667 KASSERT(err == USBD_NORMAL_COMPLETION); 4668 4669 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4670 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4671 ehci_soft_itd_t *itd, *prev; 4672 usb_dma_t *dma_buf; 4673 int i, j; 4674 int frames, uframes, ufrperframe; 4675 int trans_count, offs, total_length; 4676 int frindex; 4677 4678 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4679 4680 prev = NULL; 4681 itd = NULL; 4682 trans_count = 0; 4683 total_length = 0; 4684 4685 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4686 4687 if (sc->sc_dying) 4688 return USBD_IOERROR; 4689 4690 /* 4691 * To avoid complication, don't allow a request right now that'll span 4692 * the entire frame table. To within 4 frames, to allow some leeway 4693 * on either side of where the hc currently is. 4694 */ 4695 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4696 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4697 DPRINTF( 4698 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4699 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4700 return USBD_INVAL; 4701 } 4702 4703 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4704 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4705 KASSERT(exfer->ex_isdone); 4706 #ifdef DIAGNOSTIC 4707 exfer->ex_isdone = false; 4708 #endif 4709 4710 /* 4711 * Step 1: Re-Initialize itds 4712 */ 4713 4714 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4715 if (i > 16 || i == 0) { 4716 /* Spec page 271 says intervals > 16 are invalid */ 4717 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4718 return USBD_INVAL; 4719 } 4720 4721 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4722 frames = howmany(xfer->ux_nframes, ufrperframe); 4723 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4724 4725 if (frames == 0) { 4726 DPRINTF("frames == 0", 0, 0, 0, 0); 4727 return USBD_INVAL; 4728 } 4729 4730 dma_buf = &xfer->ux_dmabuf; 4731 offs = 0; 4732 4733 itd = exfer->ex_itdstart; 4734 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4735 int froffs = offs; 4736 4737 if (prev != NULL) { 4738 prev->itd.itd_next = 4739 htole32(itd->physaddr | EHCI_LINK_ITD); 4740 usb_syncmem(&prev->dma, 4741 prev->offs + offsetof(ehci_itd_t, itd_next), 4742 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4743 prev->xfer_next = itd; 4744 } 4745 4746 /* 4747 * Step 1.5, initialize uframes 4748 */ 4749 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4750 /* Calculate which page in the list this starts in */ 4751 int addr = DMAADDR(dma_buf, froffs); 4752 addr = EHCI_PAGE_OFFSET(addr); 4753 addr += (offs - froffs); 4754 addr = EHCI_PAGE(addr); 4755 addr /= EHCI_PAGE_SIZE; 4756 4757 /* 4758 * This gets the initial offset into the first page, 4759 * looks how far further along the current uframe 4760 * offset is. Works out how many pages that is. 4761 */ 4762 4763 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4764 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4765 EHCI_ITD_SET_PG(addr) | 4766 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4767 4768 total_length += xfer->ux_frlengths[trans_count]; 4769 offs += xfer->ux_frlengths[trans_count]; 4770 trans_count++; 4771 4772 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4773 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4774 break; 4775 } 4776 } 4777 4778 /* 4779 * Step 1.75, set buffer pointers. To simplify matters, all 4780 * pointers are filled out for the next 7 hardware pages in 4781 * the dma block, so no need to worry what pages to cover 4782 * and what to not. 4783 */ 4784 4785 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4786 /* 4787 * Don't try to lookup a page that's past the end 4788 * of buffer 4789 */ 4790 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4791 if (page_offs >= dma_buf->udma_block->size) 4792 break; 4793 4794 uint64_t page = DMAADDR(dma_buf, page_offs); 4795 page = EHCI_PAGE(page); 4796 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4797 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4798 } 4799 /* 4800 * Other special values 4801 */ 4802 4803 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4804 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4805 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4806 4807 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4808 ? 1 : 0; 4809 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4810 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4811 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4812 4813 /* FIXME: handle invalid trans */ 4814 itd->itd.itd_bufr[2] |= 4815 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4816 4817 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4818 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4819 4820 prev = itd; 4821 } /* End of frame */ 4822 4823 if (total_length) 4824 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4825 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4826 4827 /* 4828 * Part 2: Transfer descriptors have now been set up, now they must 4829 * be scheduled into the period frame list. Erk. Not wanting to 4830 * complicate matters, transfer is denied if the transfer spans 4831 * more than the period frame list. 4832 */ 4833 4834 mutex_enter(&sc->sc_lock); 4835 4836 /* Start inserting frames */ 4837 if (epipe->isoc.cur_xfers > 0) { 4838 frindex = epipe->isoc.next_frame; 4839 } else { 4840 frindex = EOREAD4(sc, EHCI_FRINDEX); 4841 frindex = frindex >> 3; /* Erase microframe index */ 4842 frindex += 2; 4843 } 4844 4845 if (frindex >= sc->sc_flsize) 4846 frindex &= (sc->sc_flsize - 1); 4847 4848 /* What's the frame interval? */ 4849 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4850 if (i / USB_UFRAMES_PER_FRAME == 0) 4851 i = 1; 4852 else 4853 i /= USB_UFRAMES_PER_FRAME; 4854 4855 itd = exfer->ex_itdstart; 4856 for (j = 0; j < frames; j++) { 4857 KASSERTMSG(itd != NULL, "frame %d\n", j); 4858 4859 usb_syncmem(&sc->sc_fldma, 4860 sizeof(ehci_link_t) * frindex, 4861 sizeof(ehci_link_t), 4862 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4863 4864 itd->itd.itd_next = sc->sc_flist[frindex]; 4865 if (itd->itd.itd_next == 0) 4866 /* 4867 * FIXME: frindex table gets initialized to NULL 4868 * or EHCI_NULL? 4869 */ 4870 itd->itd.itd_next = EHCI_NULL; 4871 4872 usb_syncmem(&itd->dma, 4873 itd->offs + offsetof(ehci_itd_t, itd_next), 4874 sizeof(itd->itd.itd_next), 4875 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4876 4877 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4878 4879 usb_syncmem(&sc->sc_fldma, 4880 sizeof(ehci_link_t) * frindex, 4881 sizeof(ehci_link_t), 4882 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4883 4884 itd->frame_list.next = sc->sc_softitds[frindex]; 4885 sc->sc_softitds[frindex] = itd; 4886 if (itd->frame_list.next != NULL) 4887 itd->frame_list.next->frame_list.prev = itd; 4888 itd->slot = frindex; 4889 itd->frame_list.prev = NULL; 4890 4891 frindex += i; 4892 if (frindex >= sc->sc_flsize) 4893 frindex -= sc->sc_flsize; 4894 4895 itd = itd->xfer_next; 4896 } 4897 4898 epipe->isoc.cur_xfers++; 4899 epipe->isoc.next_frame = frindex; 4900 4901 ehci_add_intr_list(sc, exfer); 4902 xfer->ux_status = USBD_IN_PROGRESS; 4903 mutex_exit(&sc->sc_lock); 4904 4905 return USBD_IN_PROGRESS; 4906 } 4907 4908 Static void 4909 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4910 { 4911 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4912 4913 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4914 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4915 } 4916 4917 Static void 4918 ehci_device_isoc_close(struct usbd_pipe *pipe) 4919 { 4920 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4921 4922 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4923 } 4924 4925 Static void 4926 ehci_device_isoc_done(struct usbd_xfer *xfer) 4927 { 4928 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4929 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4930 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4931 4932 KASSERT(mutex_owned(&sc->sc_lock)); 4933 4934 epipe->isoc.cur_xfers--; 4935 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4936 if (xfer->ux_length) 4937 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4938 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4939 } 4940
Indexes created Wed Oct 01 19:09:53 GMT 2025