ehci.c revision 1.260
1 /* $NetBSD: ehci.c,v 1.260 2018/08/09 06:26:47 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.260 2018/08/09 06:26:47 mrg Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static void ehci_intrlist_timeout(void *); 172 Static void ehci_doorbell(void *); 173 Static void ehci_pcd(void *); 174 175 Static struct usbd_xfer * 176 ehci_allocx(struct usbd_bus *, unsigned int); 177 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 178 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_doorbell, "ehcidb"); 416 417 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 418 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 419 420 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 421 ehci_doorbell, sc); 422 KASSERT(sc->sc_doorbell_si != NULL); 423 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 424 ehci_pcd, sc); 425 KASSERT(sc->sc_pcd_si != NULL); 426 427 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 428 429 vers = EREAD2(sc, EHCI_HCIVERSION); 430 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 431 vers >> 8, vers & 0xff); 432 433 sparams = EREAD4(sc, EHCI_HCSPARAMS); 434 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 435 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 436 ncomp = EHCI_HCS_N_CC(sparams); 437 if (ncomp != sc->sc_ncomp) { 438 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 439 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 440 #if NOHCI == 0 || NUHCI == 0 441 aprint_error("%s: ohci or uhci probably not configured\n", 442 device_xname(sc->sc_dev)); 443 #endif 444 if (ncomp < sc->sc_ncomp) 445 sc->sc_ncomp = ncomp; 446 } 447 if (sc->sc_ncomp > 0) { 448 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 449 aprint_normal("%s: %d companion controller%s, %d port%s%s", 450 device_xname(sc->sc_dev), sc->sc_ncomp, 451 sc->sc_ncomp!=1 ? "s" : "", 452 EHCI_HCS_N_PCC(sparams), 453 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 454 sc->sc_ncomp!=1 ? " each" : ""); 455 if (sc->sc_comps[0]) { 456 aprint_normal(":"); 457 for (i = 0; i < sc->sc_ncomp; i++) 458 aprint_normal(" %s", 459 device_xname(sc->sc_comps[i])); 460 } 461 aprint_normal("\n"); 462 } 463 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 464 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 465 466 cparams = EREAD4(sc, EHCI_HCCPARAMS); 467 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 468 469 if (EHCI_HCC_64BIT(cparams)) { 470 /* MUST clear segment register if 64 bit capable. */ 471 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 472 } 473 474 if (cparams & EHCI_HCC_IST_FULLFRAME) { 475 sc->sc_istthreshold = 0; 476 } else { 477 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 478 } 479 480 sc->sc_bus.ub_revision = USBREV_2_0; 481 sc->sc_bus.ub_usedma = true; 482 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 483 484 /* Reset the controller */ 485 DPRINTF("resetting", 0, 0, 0, 0); 486 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 487 usb_delay_ms(&sc->sc_bus, 1); 488 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 489 for (i = 0; i < 100; i++) { 490 usb_delay_ms(&sc->sc_bus, 1); 491 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 492 if (!hcr) 493 break; 494 } 495 if (hcr) { 496 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 497 return EIO; 498 } 499 if (sc->sc_vendor_init) 500 sc->sc_vendor_init(sc); 501 502 /* XXX need proper intr scheduling */ 503 sc->sc_rand = 96; 504 505 /* frame list size at default, read back what we got and use that */ 506 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 507 case 0: sc->sc_flsize = 1024; break; 508 case 1: sc->sc_flsize = 512; break; 509 case 2: sc->sc_flsize = 256; break; 510 case 3: return EIO; 511 } 512 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 513 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 514 if (err) 515 return err; 516 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 517 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 518 519 for (i = 0; i < sc->sc_flsize; i++) { 520 sc->sc_flist[i] = EHCI_NULL; 521 } 522 523 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 524 525 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 526 KM_SLEEP); 527 if (sc->sc_softitds == NULL) 528 return ENOMEM; 529 LIST_INIT(&sc->sc_freeitds); 530 LIST_INIT(&sc->sc_freesitds); 531 TAILQ_INIT(&sc->sc_intrhead); 532 533 /* Set up the bus struct. */ 534 sc->sc_bus.ub_methods = &ehci_bus_methods; 535 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 536 537 sc->sc_eintrs = EHCI_NORMAL_INTRS; 538 539 /* 540 * Allocate the interrupt dummy QHs. These are arranged to give poll 541 * intervals that are powers of 2 times 1ms. 542 */ 543 for (i = 0; i < EHCI_INTRQHS; i++) { 544 sqh = ehci_alloc_sqh(sc); 545 if (sqh == NULL) { 546 err = ENOMEM; 547 goto bad1; 548 } 549 sc->sc_islots[i].sqh = sqh; 550 } 551 for (i = 0; i < EHCI_INTRQHS; i++) { 552 sqh = sc->sc_islots[i].sqh; 553 if (i == 0) { 554 /* The last (1ms) QH terminates. */ 555 sqh->qh.qh_link = EHCI_NULL; 556 sqh->next = NULL; 557 } else { 558 /* Otherwise the next QH has half the poll interval */ 559 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 560 sqh->qh.qh_link = htole32(sqh->next->physaddr | 561 EHCI_LINK_QH); 562 } 563 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 564 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 565 sqh->qh.qh_curqtd = EHCI_NULL; 566 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 567 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 568 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 569 sqh->sqtd = NULL; 570 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 572 } 573 /* Point the frame list at the last level (128ms). */ 574 for (i = 0; i < sc->sc_flsize; i++) { 575 int j; 576 577 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 578 revbits[i & (EHCI_MAX_POLLRATE-1)]; 579 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 580 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 581 i)].sqh->physaddr); 582 } 583 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 584 BUS_DMASYNC_PREWRITE); 585 586 /* Allocate dummy QH that starts the async list. */ 587 sqh = ehci_alloc_sqh(sc); 588 if (sqh == NULL) { 589 err = ENOMEM; 590 goto bad1; 591 } 592 /* Fill the QH */ 593 sqh->qh.qh_endp = 594 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 595 sqh->qh.qh_link = 596 htole32(sqh->physaddr | EHCI_LINK_QH); 597 sqh->qh.qh_curqtd = EHCI_NULL; 598 sqh->next = NULL; 599 /* Fill the overlay qTD */ 600 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 601 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 602 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 603 sqh->sqtd = NULL; 604 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 605 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 606 #ifdef EHCI_DEBUG 607 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 608 ehci_dump_sqh(sqh); 609 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 610 #endif 611 612 /* Point to async list */ 613 sc->sc_async_head = sqh; 614 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 615 616 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 617 618 /* Turn on controller */ 619 EOWRITE4(sc, EHCI_USBCMD, 620 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 621 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 622 EHCI_CMD_ASE | 623 EHCI_CMD_PSE | 624 EHCI_CMD_RS); 625 626 /* Take over port ownership */ 627 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 628 629 for (i = 0; i < 100; i++) { 630 usb_delay_ms(&sc->sc_bus, 1); 631 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 632 if (!hcr) 633 break; 634 } 635 if (hcr) { 636 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 637 return EIO; 638 } 639 640 /* Enable interrupts */ 641 DPRINTF("enabling interupts", 0, 0, 0, 0); 642 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 643 644 return 0; 645 646 #if 0 647 bad2: 648 ehci_free_sqh(sc, sc->sc_async_head); 649 #endif 650 bad1: 651 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 652 return err; 653 } 654 655 int 656 ehci_intr(void *v) 657 { 658 ehci_softc_t *sc = v; 659 int ret = 0; 660 661 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 662 663 if (sc == NULL) 664 return 0; 665 666 mutex_spin_enter(&sc->sc_intr_lock); 667 668 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 669 goto done; 670 671 /* If we get an interrupt while polling, then just ignore it. */ 672 if (sc->sc_bus.ub_usepolling) { 673 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 674 675 if (intrs) 676 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 677 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 678 goto done; 679 } 680 681 ret = ehci_intr1(sc); 682 683 done: 684 mutex_spin_exit(&sc->sc_intr_lock); 685 return ret; 686 } 687 688 Static int 689 ehci_intr1(ehci_softc_t *sc) 690 { 691 uint32_t intrs, eintrs; 692 693 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 694 695 /* In case the interrupt occurs before initialization has completed. */ 696 if (sc == NULL) { 697 #ifdef DIAGNOSTIC 698 printf("ehci_intr1: sc == NULL\n"); 699 #endif 700 return 0; 701 } 702 703 KASSERT(mutex_owned(&sc->sc_intr_lock)); 704 705 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 706 if (!intrs) 707 return 0; 708 709 eintrs = intrs & sc->sc_eintrs; 710 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 711 EOREAD4(sc, EHCI_USBSTS), eintrs); 712 if (!eintrs) 713 return 0; 714 715 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 716 if (eintrs & EHCI_STS_IAA) { 717 DPRINTF("door bell", 0, 0, 0, 0); 718 kpreempt_disable(); 719 KASSERT(sc->sc_doorbell_si != NULL); 720 softint_schedule(sc->sc_doorbell_si); 721 kpreempt_enable(); 722 eintrs &= ~EHCI_STS_IAA; 723 } 724 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 725 DPRINTF("INT=%jd ERRINT=%jd", 726 eintrs & EHCI_STS_INT ? 1 : 0, 727 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 728 usb_schedsoftintr(&sc->sc_bus); 729 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 730 } 731 if (eintrs & EHCI_STS_HSE) { 732 printf("%s: unrecoverable error, controller halted\n", 733 device_xname(sc->sc_dev)); 734 /* XXX what else */ 735 } 736 if (eintrs & EHCI_STS_PCD) { 737 kpreempt_disable(); 738 KASSERT(sc->sc_pcd_si != NULL); 739 softint_schedule(sc->sc_pcd_si); 740 kpreempt_enable(); 741 eintrs &= ~EHCI_STS_PCD; 742 } 743 744 if (eintrs != 0) { 745 /* Block unprocessed interrupts. */ 746 sc->sc_eintrs &= ~eintrs; 747 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 748 printf("%s: blocking intrs 0x%x\n", 749 device_xname(sc->sc_dev), eintrs); 750 } 751 752 return 1; 753 } 754 755 Static void 756 ehci_doorbell(void *addr) 757 { 758 ehci_softc_t *sc = addr; 759 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 760 761 mutex_enter(&sc->sc_lock); 762 cv_broadcast(&sc->sc_doorbell); 763 mutex_exit(&sc->sc_lock); 764 } 765 766 Static void 767 ehci_pcd(void *addr) 768 { 769 ehci_softc_t *sc = addr; 770 struct usbd_xfer *xfer; 771 u_char *p; 772 int i, m; 773 774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 775 776 mutex_enter(&sc->sc_lock); 777 xfer = sc->sc_intrxfer; 778 779 if (xfer == NULL) { 780 /* Just ignore the change. */ 781 goto done; 782 } 783 784 p = xfer->ux_buf; 785 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 786 memset(p, 0, xfer->ux_length); 787 for (i = 1; i <= m; i++) { 788 /* Pick out CHANGE bits from the status reg. */ 789 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 790 p[i/8] |= 1 << (i%8); 791 if (i % 8 == 7) 792 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 793 } 794 xfer->ux_actlen = xfer->ux_length; 795 xfer->ux_status = USBD_NORMAL_COMPLETION; 796 797 usb_transfer_complete(xfer); 798 799 done: 800 mutex_exit(&sc->sc_lock); 801 } 802 803 Static void 804 ehci_softintr(void *v) 805 { 806 struct usbd_bus *bus = v; 807 ehci_softc_t *sc = EHCI_BUS2SC(bus); 808 struct ehci_xfer *ex, *nextex; 809 810 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 811 812 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 813 814 ex_completeq_t cq; 815 TAILQ_INIT(&cq); 816 817 /* 818 * The only explanation I can think of for why EHCI is as brain dead 819 * as UHCI interrupt-wise is that Intel was involved in both. 820 * An interrupt just tells us that something is done, we have no 821 * clue what, so we need to scan through all active transfers. :-( 822 */ 823 824 /* 825 * ehci_idone will remove transfer from sc->sc_intrhead if it's 826 * complete and add to our cq list 827 * 828 */ 829 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 830 switch (ex->ex_type) { 831 case EX_CTRL: 832 case EX_BULK: 833 case EX_INTR: 834 ehci_check_qh_intr(sc, ex, &cq); 835 break; 836 case EX_ISOC: 837 ehci_check_itd_intr(sc, ex, &cq); 838 break; 839 case EX_FS_ISOC: 840 ehci_check_sitd_intr(sc, ex, &cq); 841 break; 842 default: 843 KASSERT(false); 844 } 845 846 } 847 848 /* 849 * We abuse ex_next for the interrupt and complete lists and 850 * interrupt transfers will get re-added here so use 851 * the _SAFE version of TAILQ_FOREACH. 852 */ 853 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 854 usb_transfer_complete(&ex->ex_xfer); 855 } 856 857 /* Schedule a callout to catch any dropped transactions. */ 858 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 859 !TAILQ_EMPTY(&sc->sc_intrhead)) 860 callout_reset(&sc->sc_tmo_intrlist, 861 hz, ehci_intrlist_timeout, sc); 862 } 863 864 Static void 865 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 866 { 867 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 868 uint32_t status; 869 870 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 871 872 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 873 874 if (ex->ex_type == EX_CTRL) { 875 fsqtd = ex->ex_setup; 876 lsqtd = ex->ex_status; 877 } else { 878 fsqtd = ex->ex_sqtdstart; 879 lsqtd = ex->ex_sqtdend; 880 } 881 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 882 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 883 884 /* 885 * If the last TD is still active we need to check whether there 886 * is an error somewhere in the middle, or whether there was a 887 * short packet (SPD and not ACTIVE). 888 */ 889 usb_syncmem(&lsqtd->dma, 890 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 891 sizeof(lsqtd->qtd.qtd_status), 892 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 893 status = le32toh(lsqtd->qtd.qtd_status); 894 usb_syncmem(&lsqtd->dma, 895 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 896 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 897 if (status & EHCI_QTD_ACTIVE) { 898 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 899 900 /* last qTD has already been checked */ 901 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 902 usb_syncmem(&sqtd->dma, 903 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 904 sizeof(sqtd->qtd.qtd_status), 905 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 906 status = le32toh(sqtd->qtd.qtd_status); 907 usb_syncmem(&sqtd->dma, 908 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 909 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 910 /* If there's an active QTD the xfer isn't done. */ 911 if (status & EHCI_QTD_ACTIVE) 912 break; 913 /* Any kind of error makes the xfer done. */ 914 if (status & EHCI_QTD_HALTED) 915 goto done; 916 /* Handle short packets */ 917 if (EHCI_QTD_GET_BYTES(status) != 0) { 918 /* 919 * If we get here for a control transfer then 920 * we need to let the hardware complete the 921 * status phase. That is, we're not done 922 * quite yet. 923 * 924 * Otherwise, we're done. 925 */ 926 if (ex->ex_type == EX_CTRL) { 927 break; 928 } 929 goto done; 930 } 931 } 932 DPRINTFN(10, "ex=%#jx std=%#jx still active", 933 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 934 #ifdef EHCI_DEBUG 935 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 936 ehci_dump_sqtds(ex->ex_sqtdstart); 937 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 938 #endif 939 return; 940 } 941 done: 942 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 943 ehci_idone(ex, cq); 944 } 945 946 Static void 947 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 948 { 949 ehci_soft_itd_t *itd; 950 int i; 951 952 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 953 954 KASSERT(mutex_owned(&sc->sc_lock)); 955 956 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 957 return; 958 959 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 960 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 961 962 itd = ex->ex_itdend; 963 964 /* 965 * check no active transfers in last itd, meaning we're finished 966 */ 967 968 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 969 sizeof(itd->itd.itd_ctl), 970 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 971 972 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 973 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 974 break; 975 } 976 977 if (i == EHCI_ITD_NUFRAMES) { 978 goto done; /* All 8 descriptors inactive, it's done */ 979 } 980 981 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 982 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 983 984 DPRINTFN(10, "ex %#jx itd %#jx still active", 985 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 986 return; 987 done: 988 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 989 ehci_idone(ex, cq); 990 } 991 992 void 993 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 994 { 995 ehci_soft_sitd_t *sitd; 996 997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 998 999 KASSERT(mutex_owned(&sc->sc_lock)); 1000 1001 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1002 return; 1003 1004 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1005 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1006 1007 sitd = ex->ex_sitdend; 1008 1009 /* 1010 * check no active transfers in last sitd, meaning we're finished 1011 */ 1012 1013 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1014 sizeof(sitd->sitd.sitd_trans), 1015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1016 1017 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1021 1022 if (active) 1023 return; 1024 1025 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1026 ehci_idone(ex, cq); 1027 } 1028 1029 1030 Static void 1031 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1032 { 1033 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1034 struct usbd_xfer *xfer = &ex->ex_xfer; 1035 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1036 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1037 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1038 uint32_t status = 0, nstatus = 0; 1039 int actlen = 0; 1040 bool polling = sc->sc_bus.ub_usepolling; 1041 1042 KASSERT(polling || mutex_owned(&sc->sc_lock)); 1043 1044 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1045 1046 /* 1047 * If software has completed it, either by cancellation 1048 * or timeout, drop it on the floor. 1049 */ 1050 if (xfer->ux_status != USBD_IN_PROGRESS) { 1051 KASSERT(xfer->ux_status == USBD_CANCELLED || 1052 xfer->ux_status == USBD_TIMEOUT); 1053 DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1054 return; 1055 } 1056 1057 /* 1058 * Cancel the timeout and the task, which have not yet 1059 * run. If they have already fired, at worst they are 1060 * waiting for the lock. They will see that the xfer 1061 * is no longer in progress and give up. 1062 */ 1063 callout_stop(&xfer->ux_callout); 1064 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 1065 1066 #ifdef DIAGNOSTIC 1067 #ifdef EHCI_DEBUG 1068 if (ex->ex_isdone) { 1069 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1070 ehci_dump_exfer(ex); 1071 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1072 } 1073 #endif 1074 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1075 ex->ex_type, xfer->ux_status); 1076 ex->ex_isdone = true; 1077 #endif 1078 1079 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1080 (uintptr_t)epipe, 0, 0); 1081 1082 /* The transfer is done, compute actual length and status. */ 1083 if (ex->ex_type == EX_ISOC) { 1084 /* HS isoc transfer */ 1085 1086 struct ehci_soft_itd *itd; 1087 int i, nframes, len, uframes; 1088 1089 nframes = 0; 1090 1091 #ifdef EHCI_DEBUG 1092 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1093 ehci_dump_itds(ex->ex_itdstart); 1094 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1095 #endif 1096 1097 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1098 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1099 1100 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1101 usb_syncmem(&itd->dma, 1102 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1103 sizeof(itd->itd.itd_ctl), 1104 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1105 1106 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1107 /* 1108 * XXX - driver didn't fill in the frame full 1109 * of uframes. This leads to scheduling 1110 * inefficiencies, but working around 1111 * this doubles complexity of tracking 1112 * an xfer. 1113 */ 1114 if (nframes >= xfer->ux_nframes) 1115 break; 1116 1117 status = le32toh(itd->itd.itd_ctl[i]); 1118 len = EHCI_ITD_GET_LEN(status); 1119 if (EHCI_ITD_GET_STATUS(status) != 0) 1120 len = 0; /*No valid data on error*/ 1121 1122 xfer->ux_frlengths[nframes++] = len; 1123 actlen += len; 1124 } 1125 usb_syncmem(&itd->dma, 1126 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1127 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1128 1129 if (nframes >= xfer->ux_nframes) 1130 break; 1131 } 1132 1133 xfer->ux_actlen = actlen; 1134 xfer->ux_status = USBD_NORMAL_COMPLETION; 1135 goto end; 1136 } else if (ex->ex_type == EX_FS_ISOC) { 1137 /* FS isoc transfer */ 1138 struct ehci_soft_sitd *sitd; 1139 int nframes, len; 1140 1141 nframes = 0; 1142 1143 for (sitd = ex->ex_sitdstart; sitd != NULL; 1144 sitd = sitd->xfer_next) { 1145 usb_syncmem(&sitd->dma, 1146 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1147 sizeof(sitd->sitd.sitd_trans), 1148 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1149 1150 /* 1151 * XXX - driver didn't fill in the frame full 1152 * of uframes. This leads to scheduling 1153 * inefficiencies, but working around 1154 * this doubles complexity of tracking 1155 * an xfer. 1156 */ 1157 if (nframes >= xfer->ux_nframes) 1158 break; 1159 1160 status = le32toh(sitd->sitd.sitd_trans); 1161 usb_syncmem(&sitd->dma, 1162 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1163 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1164 1165 len = EHCI_SITD_GET_LEN(status); 1166 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1167 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1168 /* No valid data on error */ 1169 len = xfer->ux_frlengths[nframes]; 1170 } 1171 1172 /* 1173 * frlengths[i]: # of bytes to send 1174 * len: # of bytes host didn't send 1175 */ 1176 xfer->ux_frlengths[nframes] -= len; 1177 /* frlengths[i]: # of bytes host sent */ 1178 actlen += xfer->ux_frlengths[nframes++]; 1179 1180 if (nframes >= xfer->ux_nframes) 1181 break; 1182 } 1183 1184 xfer->ux_actlen = actlen; 1185 xfer->ux_status = USBD_NORMAL_COMPLETION; 1186 goto end; 1187 } 1188 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1189 ex->ex_type == EX_BULK); 1190 1191 /* Continue processing xfers using queue heads */ 1192 if (ex->ex_type == EX_CTRL) { 1193 fsqtd = ex->ex_setup; 1194 lsqtd = ex->ex_status; 1195 } else { 1196 fsqtd = ex->ex_sqtdstart; 1197 lsqtd = ex->ex_sqtdend; 1198 } 1199 #ifdef EHCI_DEBUG 1200 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1201 ehci_dump_sqtds(fsqtd); 1202 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1203 #endif 1204 1205 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1206 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1207 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1208 nstatus = le32toh(sqtd->qtd.qtd_status); 1209 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1210 BUS_DMASYNC_PREREAD); 1211 if (nstatus & EHCI_QTD_ACTIVE) 1212 break; 1213 1214 status = nstatus; 1215 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1216 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1217 } 1218 1219 /* 1220 * If there are left over TDs we need to update the toggle. 1221 * The default pipe doesn't need it since control transfers 1222 * start the toggle at 0 every time. 1223 * For a short transfer we need to update the toggle for the missing 1224 * packets within the qTD. 1225 */ 1226 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1227 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1228 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1229 status, nstatus, 0, 0); 1230 #if 0 1231 ehci_dump_sqh(epipe->sqh); 1232 ehci_dump_sqtds(ex->ex_sqtdstart); 1233 #endif 1234 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1235 } 1236 1237 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1238 status, 0); 1239 xfer->ux_actlen = actlen; 1240 if (status & EHCI_QTD_HALTED) { 1241 #ifdef EHCI_DEBUG 1242 DPRINTF("halted addr=%jd endpt=0x%02jx", 1243 xfer->ux_pipe->up_dev->ud_addr, 1244 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1245 0, 0); 1246 DPRINTF("cerr=%jd pid=%jd", 1247 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1248 0, 0); 1249 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1250 status & EHCI_QTD_ACTIVE ? 1 : 0, 1251 status & EHCI_QTD_HALTED ? 1 : 0, 1252 status & EHCI_QTD_BUFERR ? 1 : 0, 1253 status & EHCI_QTD_BABBLE ? 1 : 0); 1254 1255 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1256 status & EHCI_QTD_XACTERR ? 1 : 0, 1257 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1258 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1259 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1260 1261 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1262 ehci_dump_sqh(epipe->sqh); 1263 ehci_dump_sqtds(ex->ex_sqtdstart); 1264 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1265 #endif 1266 /* low&full speed has an extra error flag */ 1267 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1268 EHCI_QH_SPEED_HIGH) 1269 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1270 else 1271 status &= EHCI_QTD_STATERRS; 1272 if (status == 0) /* no other errors means a stall */ { 1273 xfer->ux_status = USBD_STALLED; 1274 } else { 1275 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1276 } 1277 /* XXX need to reset TT on missed microframe */ 1278 if (status & EHCI_QTD_MISSEDMICRO) { 1279 printf("%s: missed microframe, TT reset not " 1280 "implemented, hub might be inoperational\n", 1281 device_xname(sc->sc_dev)); 1282 } 1283 } else { 1284 xfer->ux_status = USBD_NORMAL_COMPLETION; 1285 } 1286 1287 end: 1288 1289 ehci_del_intr_list(sc, ex); 1290 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1291 1292 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1293 } 1294 1295 Static void 1296 ehci_poll(struct usbd_bus *bus) 1297 { 1298 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1299 1300 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1301 1302 #ifdef EHCI_DEBUG 1303 static int last; 1304 int new; 1305 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1306 if (new != last) { 1307 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1308 last = new; 1309 } 1310 #endif 1311 1312 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1313 mutex_spin_enter(&sc->sc_intr_lock); 1314 ehci_intr1(sc); 1315 mutex_spin_exit(&sc->sc_intr_lock); 1316 } 1317 } 1318 1319 void 1320 ehci_childdet(device_t self, device_t child) 1321 { 1322 struct ehci_softc *sc = device_private(self); 1323 1324 KASSERT(sc->sc_child == child); 1325 sc->sc_child = NULL; 1326 } 1327 1328 int 1329 ehci_detach(struct ehci_softc *sc, int flags) 1330 { 1331 int rv = 0; 1332 1333 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1334 1335 if (sc->sc_child != NULL) 1336 rv = config_detach(sc->sc_child, flags); 1337 1338 if (rv != 0) 1339 return rv; 1340 1341 callout_halt(&sc->sc_tmo_intrlist, NULL); 1342 callout_destroy(&sc->sc_tmo_intrlist); 1343 1344 /* XXX free other data structures XXX */ 1345 if (sc->sc_softitds) 1346 kmem_free(sc->sc_softitds, 1347 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1348 cv_destroy(&sc->sc_doorbell); 1349 1350 #if 0 1351 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1352 1353 softint_disestablish(sc->sc_doorbell_si); 1354 softint_disestablish(sc->sc_pcd_si); 1355 1356 mutex_destroy(&sc->sc_lock); 1357 mutex_destroy(&sc->sc_intr_lock); 1358 #endif 1359 1360 pool_cache_destroy(sc->sc_xferpool); 1361 1362 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1363 1364 return rv; 1365 } 1366 1367 1368 int 1369 ehci_activate(device_t self, enum devact act) 1370 { 1371 struct ehci_softc *sc = device_private(self); 1372 1373 switch (act) { 1374 case DVACT_DEACTIVATE: 1375 sc->sc_dying = 1; 1376 return 0; 1377 default: 1378 return EOPNOTSUPP; 1379 } 1380 } 1381 1382 /* 1383 * Handle suspend/resume. 1384 * 1385 * We need to switch to polling mode here, because this routine is 1386 * called from an interrupt context. This is all right since we 1387 * are almost suspended anyway. 1388 * 1389 * Note that this power handler isn't to be registered directly; the 1390 * bus glue needs to call out to it. 1391 */ 1392 bool 1393 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1394 { 1395 ehci_softc_t *sc = device_private(dv); 1396 int i; 1397 uint32_t cmd, hcr; 1398 1399 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1400 1401 mutex_spin_enter(&sc->sc_intr_lock); 1402 sc->sc_bus.ub_usepolling++; 1403 mutex_spin_exit(&sc->sc_intr_lock); 1404 1405 for (i = 1; i <= sc->sc_noport; i++) { 1406 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1407 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1408 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1409 } 1410 1411 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1412 1413 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1414 EOWRITE4(sc, EHCI_USBCMD, cmd); 1415 1416 for (i = 0; i < 100; i++) { 1417 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1418 if (hcr == 0) 1419 break; 1420 1421 usb_delay_ms(&sc->sc_bus, 1); 1422 } 1423 if (hcr != 0) 1424 printf("%s: reset timeout\n", device_xname(dv)); 1425 1426 cmd &= ~EHCI_CMD_RS; 1427 EOWRITE4(sc, EHCI_USBCMD, cmd); 1428 1429 for (i = 0; i < 100; i++) { 1430 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1431 if (hcr == EHCI_STS_HCH) 1432 break; 1433 1434 usb_delay_ms(&sc->sc_bus, 1); 1435 } 1436 if (hcr != EHCI_STS_HCH) 1437 printf("%s: config timeout\n", device_xname(dv)); 1438 1439 mutex_spin_enter(&sc->sc_intr_lock); 1440 sc->sc_bus.ub_usepolling--; 1441 mutex_spin_exit(&sc->sc_intr_lock); 1442 1443 return true; 1444 } 1445 1446 bool 1447 ehci_resume(device_t dv, const pmf_qual_t *qual) 1448 { 1449 ehci_softc_t *sc = device_private(dv); 1450 int i; 1451 uint32_t cmd, hcr; 1452 1453 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1454 1455 /* restore things in case the bios sucks */ 1456 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1457 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1458 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1459 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1460 1461 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1462 1463 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1464 1465 hcr = 0; 1466 for (i = 1; i <= sc->sc_noport; i++) { 1467 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1468 if ((cmd & EHCI_PS_PO) == 0 && 1469 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1470 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1471 hcr = 1; 1472 } 1473 } 1474 1475 if (hcr) { 1476 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1477 1478 for (i = 1; i <= sc->sc_noport; i++) { 1479 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1480 if ((cmd & EHCI_PS_PO) == 0 && 1481 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1482 EOWRITE4(sc, EHCI_PORTSC(i), 1483 cmd & ~EHCI_PS_FPR); 1484 } 1485 } 1486 1487 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1488 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1489 1490 for (i = 0; i < 100; i++) { 1491 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1492 if (hcr != EHCI_STS_HCH) 1493 break; 1494 1495 usb_delay_ms(&sc->sc_bus, 1); 1496 } 1497 if (hcr == EHCI_STS_HCH) 1498 printf("%s: config timeout\n", device_xname(dv)); 1499 1500 return true; 1501 } 1502 1503 /* 1504 * Shut down the controller when the system is going down. 1505 */ 1506 bool 1507 ehci_shutdown(device_t self, int flags) 1508 { 1509 ehci_softc_t *sc = device_private(self); 1510 1511 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1512 1513 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1514 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1515 return true; 1516 } 1517 1518 Static struct usbd_xfer * 1519 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1520 { 1521 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1522 struct usbd_xfer *xfer; 1523 1524 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1525 if (xfer != NULL) { 1526 memset(xfer, 0, sizeof(struct ehci_xfer)); 1527 1528 /* Initialise this always so we can call remove on it. */ 1529 usb_init_task(&xfer->ux_aborttask, ehci_timeout_task, xfer, 1530 USB_TASKQ_MPSAFE); 1531 #ifdef DIAGNOSTIC 1532 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1533 ex->ex_isdone = true; 1534 xfer->ux_state = XFER_BUSY; 1535 #endif 1536 } 1537 return xfer; 1538 } 1539 1540 Static void 1541 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1542 { 1543 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1544 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1545 1546 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1547 xfer->ux_state); 1548 KASSERT(ex->ex_isdone); 1549 1550 #ifdef DIAGNOSTIC 1551 xfer->ux_state = XFER_FREE; 1552 #endif 1553 1554 pool_cache_put(sc->sc_xferpool, xfer); 1555 } 1556 1557 Static void 1558 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1559 { 1560 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1561 1562 *lock = &sc->sc_lock; 1563 } 1564 1565 Static void 1566 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1567 { 1568 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1569 1570 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1571 1572 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1573 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1574 #ifdef EHCI_DEBUG 1575 if (ehcidebug) 1576 usbd_dump_pipe(pipe); 1577 #endif 1578 epipe->nexttoggle = 0; 1579 } 1580 1581 Static void 1582 ehci_noop(struct usbd_pipe *pipe) 1583 { 1584 } 1585 1586 #ifdef EHCI_DEBUG 1587 /* 1588 * Unused function - this is meant to be called from a kernel 1589 * debugger. 1590 */ 1591 void 1592 ehci_dump(void) 1593 { 1594 ehci_softc_t *sc = theehci; 1595 int i; 1596 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1597 EOREAD4(sc, EHCI_USBCMD), 1598 EOREAD4(sc, EHCI_USBSTS), 1599 EOREAD4(sc, EHCI_USBINTR)); 1600 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1601 EOREAD4(sc, EHCI_FRINDEX), 1602 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1603 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1604 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1605 for (i = 1; i <= sc->sc_noport; i++) 1606 printf("port %d status=0x%08x\n", i, 1607 EOREAD4(sc, EHCI_PORTSC(i))); 1608 } 1609 1610 Static void 1611 ehci_dump_regs(ehci_softc_t *sc) 1612 { 1613 int i; 1614 1615 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1616 1617 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1618 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1619 EOREAD4(sc, EHCI_USBINTR), 0); 1620 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1621 "async = 0x%08jx", 1622 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1623 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1624 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1625 for (i = 1; i <= sc->sc_noport; i += 2) { 1626 if (i == sc->sc_noport) { 1627 DPRINTF("port %jd status = 0x%08jx", i, 1628 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1629 } else { 1630 DPRINTF("port %jd status = 0x%08jx port %jd " 1631 "status = 0x%08jx", 1632 i, EOREAD4(sc, EHCI_PORTSC(i)), 1633 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1634 } 1635 } 1636 } 1637 1638 #define ehci_dump_link(link, type) do { \ 1639 DPRINTF(" link 0x%08jx (T = %jd):", \ 1640 link, \ 1641 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1642 if (type) { \ 1643 DPRINTF( \ 1644 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1645 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1646 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1647 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1648 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1649 } \ 1650 } while(0) 1651 1652 Static void 1653 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1654 { 1655 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1656 int i; 1657 uint32_t stop = 0; 1658 1659 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1660 ehci_dump_sqtd(sqtd); 1661 usb_syncmem(&sqtd->dma, 1662 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1663 sizeof(sqtd->qtd), 1664 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1665 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1666 usb_syncmem(&sqtd->dma, 1667 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1668 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1669 } 1670 if (!stop) 1671 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1672 } 1673 1674 Static void 1675 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1676 { 1677 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1678 1679 usb_syncmem(&sqtd->dma, sqtd->offs, 1680 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1681 1682 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1683 0, 0); 1684 ehci_dump_qtd(&sqtd->qtd); 1685 1686 usb_syncmem(&sqtd->dma, sqtd->offs, 1687 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1688 } 1689 1690 Static void 1691 ehci_dump_qtd(ehci_qtd_t *qtd) 1692 { 1693 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1694 uint32_t s = le32toh(qtd->qtd_status); 1695 1696 DPRINTFN(10, 1697 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1698 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1699 DPRINTFN(10, 1700 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1701 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1702 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1703 DPRINTFN(10, 1704 " cerr = %jd pid = %jd stat = %jx", 1705 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1706 0); 1707 DPRINTFN(10, 1708 "active =%jd halted=%jd buferr=%jd babble=%jd", 1709 s & EHCI_QTD_ACTIVE ? 1 : 0, 1710 s & EHCI_QTD_HALTED ? 1 : 0, 1711 s & EHCI_QTD_BUFERR ? 1 : 0, 1712 s & EHCI_QTD_BABBLE ? 1 : 0); 1713 DPRINTFN(10, 1714 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1715 s & EHCI_QTD_XACTERR ? 1 : 0, 1716 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1717 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1718 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1719 DPRINTFN(10, 1720 "buffer[0] = %#jx buffer[1] = %#jx " 1721 "buffer[2] = %#jx buffer[3] = %#jx", 1722 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1723 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1724 DPRINTFN(10, 1725 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1726 } 1727 1728 Static void 1729 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1730 { 1731 ehci_qh_t *qh = &sqh->qh; 1732 ehci_link_t link; 1733 uint32_t endp, endphub; 1734 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1735 1736 usb_syncmem(&sqh->dma, sqh->offs, 1737 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1738 1739 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1740 link = le32toh(qh->qh_link); 1741 ehci_dump_link(link, true); 1742 1743 endp = le32toh(qh->qh_endp); 1744 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1745 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1746 "eps = %jd", 1747 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1748 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1749 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1750 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1751 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1752 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1753 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1754 1755 endphub = le32toh(qh->qh_endphub); 1756 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1757 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1758 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1759 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1760 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1761 EHCI_QH_GET_MULT(endphub), 0); 1762 1763 link = le32toh(qh->qh_curqtd); 1764 ehci_dump_link(link, false); 1765 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1766 ehci_dump_qtd(&qh->qh_qtd); 1767 1768 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1769 BUS_DMASYNC_PREREAD); 1770 } 1771 1772 Static void 1773 ehci_dump_itds(ehci_soft_itd_t *itd) 1774 { 1775 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1776 int i; 1777 uint32_t stop = 0; 1778 1779 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1780 ehci_dump_itd(itd); 1781 usb_syncmem(&itd->dma, 1782 itd->offs + offsetof(ehci_itd_t, itd_next), 1783 sizeof(itd->itd), 1784 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1785 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1786 usb_syncmem(&itd->dma, 1787 itd->offs + offsetof(ehci_itd_t, itd_next), 1788 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1789 } 1790 if (!stop) 1791 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1792 } 1793 1794 Static void 1795 ehci_dump_itd(struct ehci_soft_itd *itd) 1796 { 1797 ehci_isoc_trans_t t; 1798 ehci_isoc_bufr_ptr_t b, b2, b3; 1799 int i; 1800 1801 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1802 1803 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1804 1805 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1806 t = le32toh(itd->itd.itd_ctl[i]); 1807 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1808 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1809 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1810 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1811 EHCI_ITD_GET_OFFS(t), 0); 1812 } 1813 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1814 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1815 DPRINTF(" %jx", 1816 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1817 1818 b = le32toh(itd->itd.itd_bufr[0]); 1819 b2 = le32toh(itd->itd.itd_bufr[1]); 1820 b3 = le32toh(itd->itd.itd_bufr[2]); 1821 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1822 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1823 DPRINTF(" maxpkt = %jx multi = %jx", 1824 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1825 } 1826 1827 Static void 1828 ehci_dump_sitd(struct ehci_soft_itd *itd) 1829 { 1830 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1831 1832 DPRINTF("SITD %#jx next = %p prev = %#jx", 1833 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1834 (uintptr_t)itd->frame_list.prev, 0); 1835 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1836 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1837 } 1838 1839 Static void 1840 ehci_dump_exfer(struct ehci_xfer *ex) 1841 { 1842 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1843 1844 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1845 ex->ex_isdone, 0); 1846 1847 switch (ex->ex_type) { 1848 case EX_CTRL: 1849 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1850 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1851 (uintptr_t)ex->ex_status, 0); 1852 break; 1853 case EX_BULK: 1854 case EX_INTR: 1855 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1856 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1857 0, 0); 1858 break; 1859 case EX_ISOC: 1860 DPRINTF(" itdstart = %#jx itdend = %#jx", 1861 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1862 break; 1863 case EX_FS_ISOC: 1864 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1865 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1866 0, 0); 1867 break; 1868 default: 1869 DPRINTF(" unknown type", 0, 0, 0, 0); 1870 } 1871 } 1872 #endif 1873 1874 Static usbd_status 1875 ehci_open(struct usbd_pipe *pipe) 1876 { 1877 struct usbd_device *dev = pipe->up_dev; 1878 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1879 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1880 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1881 uint8_t addr = dev->ud_addr; 1882 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1883 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1884 ehci_soft_qh_t *sqh; 1885 usbd_status err; 1886 int ival, speed, naks; 1887 int hshubaddr, hshubport; 1888 1889 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1890 1891 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1892 ed->bEndpointAddress, rhaddr); 1893 1894 if (dev->ud_myhsport) { 1895 /* 1896 * When directly attached FS/LS device while doing embedded 1897 * transaction translations and we are the hub, set the hub 1898 * address to 0 (us). 1899 */ 1900 if (!(sc->sc_flags & EHCIF_ETTF) 1901 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1902 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1903 } else { 1904 hshubaddr = 0; 1905 } 1906 hshubport = dev->ud_myhsport->up_portno; 1907 } else { 1908 hshubaddr = 0; 1909 hshubport = 0; 1910 } 1911 1912 if (sc->sc_dying) 1913 return USBD_IOERROR; 1914 1915 /* toggle state needed for bulk endpoints */ 1916 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1917 1918 if (addr == rhaddr) { 1919 switch (ed->bEndpointAddress) { 1920 case USB_CONTROL_ENDPOINT: 1921 pipe->up_methods = &roothub_ctrl_methods; 1922 break; 1923 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1924 pipe->up_methods = &ehci_root_intr_methods; 1925 break; 1926 default: 1927 DPRINTF("bad bEndpointAddress 0x%02jx", 1928 ed->bEndpointAddress, 0, 0, 0); 1929 return USBD_INVAL; 1930 } 1931 return USBD_NORMAL_COMPLETION; 1932 } 1933 1934 /* XXX All this stuff is only valid for async. */ 1935 switch (dev->ud_speed) { 1936 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1937 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1938 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1939 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1940 } 1941 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1942 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1943 0); 1944 return USBD_INVAL; 1945 } 1946 1947 /* 1948 * For interrupt transfer, nak throttling must be disabled, but for 1949 * the other transfer type, nak throttling should be enabled from the 1950 * viewpoint that avoids the memory thrashing. 1951 */ 1952 naks = (xfertype == UE_INTERRUPT) ? 0 1953 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1954 1955 /* Allocate sqh for everything, save isoc xfers */ 1956 if (xfertype != UE_ISOCHRONOUS) { 1957 sqh = ehci_alloc_sqh(sc); 1958 if (sqh == NULL) 1959 return USBD_NOMEM; 1960 /* qh_link filled when the QH is added */ 1961 sqh->qh.qh_endp = htole32( 1962 EHCI_QH_SET_ADDR(addr) | 1963 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1964 EHCI_QH_SET_EPS(speed) | 1965 EHCI_QH_DTC | 1966 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1967 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1968 EHCI_QH_CTL : 0) | 1969 EHCI_QH_SET_NRL(naks) 1970 ); 1971 sqh->qh.qh_endphub = htole32( 1972 EHCI_QH_SET_MULT(1) | 1973 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1974 ); 1975 if (speed != EHCI_QH_SPEED_HIGH) 1976 sqh->qh.qh_endphub |= htole32( 1977 EHCI_QH_SET_PORT(hshubport) | 1978 EHCI_QH_SET_HUBA(hshubaddr) | 1979 (xfertype == UE_INTERRUPT ? 1980 EHCI_QH_SET_CMASK(0x08) : 0) 1981 ); 1982 sqh->qh.qh_curqtd = EHCI_NULL; 1983 /* Fill the overlay qTD */ 1984 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1985 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1986 sqh->qh.qh_qtd.qtd_status = htole32(0); 1987 1988 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1989 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1990 epipe->sqh = sqh; 1991 } else { 1992 sqh = NULL; 1993 } /*xfertype == UE_ISOC*/ 1994 1995 switch (xfertype) { 1996 case UE_CONTROL: 1997 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1998 0, &epipe->ctrl.reqdma); 1999 #ifdef EHCI_DEBUG 2000 if (err) 2001 printf("ehci_open: usb_allocmem()=%d\n", err); 2002 #endif 2003 if (err) 2004 goto bad; 2005 pipe->up_methods = &ehci_device_ctrl_methods; 2006 mutex_enter(&sc->sc_lock); 2007 ehci_add_qh(sc, sqh, sc->sc_async_head); 2008 mutex_exit(&sc->sc_lock); 2009 break; 2010 case UE_BULK: 2011 pipe->up_methods = &ehci_device_bulk_methods; 2012 mutex_enter(&sc->sc_lock); 2013 ehci_add_qh(sc, sqh, sc->sc_async_head); 2014 mutex_exit(&sc->sc_lock); 2015 break; 2016 case UE_INTERRUPT: 2017 pipe->up_methods = &ehci_device_intr_methods; 2018 ival = pipe->up_interval; 2019 if (ival == USBD_DEFAULT_INTERVAL) { 2020 if (speed == EHCI_QH_SPEED_HIGH) { 2021 if (ed->bInterval > 16) { 2022 /* 2023 * illegal with high-speed, but there 2024 * were documentation bugs in the spec, 2025 * so be generous 2026 */ 2027 ival = 256; 2028 } else 2029 ival = (1 << (ed->bInterval - 1)) / 8; 2030 } else 2031 ival = ed->bInterval; 2032 } 2033 err = ehci_device_setintr(sc, sqh, ival); 2034 if (err) 2035 goto bad; 2036 break; 2037 case UE_ISOCHRONOUS: 2038 pipe->up_serialise = false; 2039 if (speed == EHCI_QH_SPEED_HIGH) 2040 pipe->up_methods = &ehci_device_isoc_methods; 2041 else 2042 pipe->up_methods = &ehci_device_fs_isoc_methods; 2043 if (ed->bInterval == 0 || ed->bInterval > 16) { 2044 printf("ehci: opening pipe with invalid bInterval\n"); 2045 err = USBD_INVAL; 2046 goto bad; 2047 } 2048 if (UGETW(ed->wMaxPacketSize) == 0) { 2049 printf("ehci: zero length endpoint open request\n"); 2050 err = USBD_INVAL; 2051 goto bad; 2052 } 2053 epipe->isoc.next_frame = 0; 2054 epipe->isoc.cur_xfers = 0; 2055 break; 2056 default: 2057 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2058 err = USBD_INVAL; 2059 goto bad; 2060 } 2061 return USBD_NORMAL_COMPLETION; 2062 2063 bad: 2064 if (sqh != NULL) { 2065 mutex_enter(&sc->sc_lock); 2066 ehci_free_sqh(sc, sqh); 2067 mutex_exit(&sc->sc_lock); 2068 } 2069 return err; 2070 } 2071 2072 /* 2073 * Add an ED to the schedule. Called with USB lock held. 2074 */ 2075 Static void 2076 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2077 { 2078 2079 KASSERT(mutex_owned(&sc->sc_lock)); 2080 2081 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2082 2083 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2084 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2085 2086 sqh->next = head->next; 2087 sqh->qh.qh_link = head->qh.qh_link; 2088 2089 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2090 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2091 2092 head->next = sqh; 2093 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2094 2095 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2096 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2097 2098 #ifdef EHCI_DEBUG 2099 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2100 ehci_dump_sqh(sqh); 2101 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2102 #endif 2103 } 2104 2105 /* 2106 * Remove an ED from the schedule. Called with USB lock held. 2107 */ 2108 Static void 2109 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2110 { 2111 ehci_soft_qh_t *p; 2112 2113 KASSERT(mutex_owned(&sc->sc_lock)); 2114 2115 /* XXX */ 2116 for (p = head; p != NULL && p->next != sqh; p = p->next) 2117 ; 2118 if (p == NULL) 2119 panic("ehci_rem_qh: ED not found"); 2120 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2121 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2122 p->next = sqh->next; 2123 p->qh.qh_link = sqh->qh.qh_link; 2124 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2125 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2126 2127 ehci_sync_hc(sc); 2128 } 2129 2130 Static void 2131 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2132 { 2133 int i; 2134 uint32_t status; 2135 2136 /* Save toggle bit and ping status. */ 2137 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2138 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2139 status = sqh->qh.qh_qtd.qtd_status & 2140 htole32(EHCI_QTD_TOGGLE_MASK | 2141 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2142 /* Set HALTED to make hw leave it alone. */ 2143 sqh->qh.qh_qtd.qtd_status = 2144 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2145 usb_syncmem(&sqh->dma, 2146 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2147 sizeof(sqh->qh.qh_qtd.qtd_status), 2148 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2149 sqh->qh.qh_curqtd = 0; 2150 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2151 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2152 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2153 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2154 sqh->sqtd = sqtd; 2155 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2156 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2157 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2158 sqh->qh.qh_qtd.qtd_status = status; 2159 usb_syncmem(&sqh->dma, 2160 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2161 sizeof(sqh->qh.qh_qtd.qtd_status), 2162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2163 } 2164 2165 /* 2166 * Ensure that the HC has released all references to the QH. We do this 2167 * by asking for a Async Advance Doorbell interrupt and then we wait for 2168 * the interrupt. 2169 * To make this easier we first obtain exclusive use of the doorbell. 2170 */ 2171 Static void 2172 ehci_sync_hc(ehci_softc_t *sc) 2173 { 2174 int error __diagused; 2175 2176 KASSERT(mutex_owned(&sc->sc_lock)); 2177 2178 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2179 2180 if (sc->sc_dying) { 2181 DPRINTF("dying", 0, 0, 0, 0); 2182 return; 2183 } 2184 2185 /* ask for doorbell */ 2186 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2187 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2188 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2189 2190 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2191 2192 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2193 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2194 #ifdef DIAGNOSTIC 2195 if (error == EWOULDBLOCK) { 2196 printf("ehci_sync_hc: timed out\n"); 2197 } else if (error) { 2198 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2199 } 2200 #endif 2201 } 2202 2203 Static void 2204 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2205 { 2206 2207 KASSERT(mutex_owned(&sc->sc_lock)); 2208 2209 for (; itd != NULL; itd = itd->xfer_next) { 2210 struct ehci_soft_itd *prev = itd->frame_list.prev; 2211 2212 /* Unlink itd from hardware chain, or frame array */ 2213 if (prev == NULL) { /* We're at the table head */ 2214 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2215 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2216 usb_syncmem(&sc->sc_fldma, 2217 sizeof(ehci_link_t) * itd->slot, 2218 sizeof(ehci_link_t), 2219 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2220 2221 if (itd->frame_list.next != NULL) 2222 itd->frame_list.next->frame_list.prev = NULL; 2223 } else { 2224 /* XXX this part is untested... */ 2225 prev->itd.itd_next = itd->itd.itd_next; 2226 usb_syncmem(&itd->dma, 2227 itd->offs + offsetof(ehci_itd_t, itd_next), 2228 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2229 2230 prev->frame_list.next = itd->frame_list.next; 2231 if (itd->frame_list.next != NULL) 2232 itd->frame_list.next->frame_list.prev = prev; 2233 } 2234 } 2235 } 2236 2237 Static void 2238 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2239 { 2240 struct ehci_soft_itd *next; 2241 2242 mutex_enter(&sc->sc_lock); 2243 next = NULL; 2244 for (; itd != NULL; itd = next) { 2245 next = itd->xfer_next; 2246 ehci_free_itd_locked(sc, itd); 2247 } 2248 mutex_exit(&sc->sc_lock); 2249 } 2250 2251 Static void 2252 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2253 { 2254 2255 KASSERT(mutex_owned(&sc->sc_lock)); 2256 2257 for (; sitd != NULL; sitd = sitd->xfer_next) { 2258 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2259 2260 /* Unlink sitd from hardware chain, or frame array */ 2261 if (prev == NULL) { /* We're at the table head */ 2262 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2263 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2264 usb_syncmem(&sc->sc_fldma, 2265 sizeof(ehci_link_t) * sitd->slot, 2266 sizeof(ehci_link_t), 2267 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2268 2269 if (sitd->frame_list.next != NULL) 2270 sitd->frame_list.next->frame_list.prev = NULL; 2271 } else { 2272 /* XXX this part is untested... */ 2273 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2274 usb_syncmem(&sitd->dma, 2275 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2276 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2277 2278 prev->frame_list.next = sitd->frame_list.next; 2279 if (sitd->frame_list.next != NULL) 2280 sitd->frame_list.next->frame_list.prev = prev; 2281 } 2282 } 2283 } 2284 2285 Static void 2286 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2287 { 2288 2289 mutex_enter(&sc->sc_lock); 2290 struct ehci_soft_sitd *next = NULL; 2291 for (; sitd != NULL; sitd = next) { 2292 next = sitd->xfer_next; 2293 ehci_free_sitd_locked(sc, sitd); 2294 } 2295 mutex_exit(&sc->sc_lock); 2296 } 2297 2298 /***********/ 2299 2300 Static int 2301 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2302 void *buf, int buflen) 2303 { 2304 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2305 usb_hub_descriptor_t hubd; 2306 usb_port_status_t ps; 2307 uint16_t len, value, index; 2308 int l, totlen = 0; 2309 int port, i; 2310 uint32_t v; 2311 2312 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2313 2314 if (sc->sc_dying) 2315 return -1; 2316 2317 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2318 0, 0); 2319 2320 len = UGETW(req->wLength); 2321 value = UGETW(req->wValue); 2322 index = UGETW(req->wIndex); 2323 2324 #define C(x,y) ((x) | ((y) << 8)) 2325 switch (C(req->bRequest, req->bmRequestType)) { 2326 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2327 if (len == 0) 2328 break; 2329 switch (value) { 2330 #define sd ((usb_string_descriptor_t *)buf) 2331 case C(2, UDESC_STRING): 2332 /* Product */ 2333 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2334 break; 2335 #undef sd 2336 default: 2337 /* default from usbroothub */ 2338 return buflen; 2339 } 2340 break; 2341 2342 /* Hub requests */ 2343 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2344 break; 2345 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2346 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2347 value, 0, 0); 2348 if (index < 1 || index > sc->sc_noport) { 2349 return -1; 2350 } 2351 port = EHCI_PORTSC(index); 2352 v = EOREAD4(sc, port); 2353 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2354 v &= ~EHCI_PS_CLEAR; 2355 switch (value) { 2356 case UHF_PORT_ENABLE: 2357 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2358 break; 2359 case UHF_PORT_SUSPEND: 2360 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2361 break; 2362 v &= ~EHCI_PS_SUSP; 2363 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2364 /* see USB2 spec ch. 7.1.7.7 */ 2365 usb_delay_ms(&sc->sc_bus, 20); 2366 EOWRITE4(sc, port, v); 2367 usb_delay_ms(&sc->sc_bus, 2); 2368 #ifdef DEBUG 2369 v = EOREAD4(sc, port); 2370 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2371 printf("ehci: resume failed: %x\n", v); 2372 #endif 2373 break; 2374 case UHF_PORT_POWER: 2375 if (sc->sc_hasppc) 2376 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2377 break; 2378 case UHF_PORT_TEST: 2379 DPRINTF("clear port test %jd", index, 0, 0, 0); 2380 break; 2381 case UHF_PORT_INDICATOR: 2382 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2383 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2384 break; 2385 case UHF_C_PORT_CONNECTION: 2386 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2387 break; 2388 case UHF_C_PORT_ENABLE: 2389 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2390 break; 2391 case UHF_C_PORT_SUSPEND: 2392 /* how? */ 2393 break; 2394 case UHF_C_PORT_OVER_CURRENT: 2395 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2396 break; 2397 case UHF_C_PORT_RESET: 2398 sc->sc_isreset[index] = 0; 2399 break; 2400 default: 2401 return -1; 2402 } 2403 #if 0 2404 switch(value) { 2405 case UHF_C_PORT_CONNECTION: 2406 case UHF_C_PORT_ENABLE: 2407 case UHF_C_PORT_SUSPEND: 2408 case UHF_C_PORT_OVER_CURRENT: 2409 case UHF_C_PORT_RESET: 2410 default: 2411 break; 2412 } 2413 #endif 2414 break; 2415 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2416 if (len == 0) 2417 break; 2418 if ((value & 0xff) != 0) { 2419 return -1; 2420 } 2421 totlen = min(buflen, sizeof(hubd)); 2422 memcpy(&hubd, buf, totlen); 2423 hubd.bNbrPorts = sc->sc_noport; 2424 v = EOREAD4(sc, EHCI_HCSPARAMS); 2425 USETW(hubd.wHubCharacteristics, 2426 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2427 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2428 ? UHD_PORT_IND : 0); 2429 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2430 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2431 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2432 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2433 totlen = min(totlen, hubd.bDescLength); 2434 memcpy(buf, &hubd, totlen); 2435 break; 2436 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2437 if (len != 4) { 2438 return -1; 2439 } 2440 memset(buf, 0, len); /* ? XXX */ 2441 totlen = len; 2442 break; 2443 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2444 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2445 if (index < 1 || index > sc->sc_noport) { 2446 return -1; 2447 } 2448 if (len != 4) { 2449 return -1; 2450 } 2451 v = EOREAD4(sc, EHCI_PORTSC(index)); 2452 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2453 2454 i = UPS_HIGH_SPEED; 2455 if (sc->sc_flags & EHCIF_ETTF) { 2456 /* 2457 * If we are doing embedded transaction translation, 2458 * then directly attached LS/FS devices are reset by 2459 * the EHCI controller itself. PSPD is encoded 2460 * the same way as in USBSTATUS. 2461 */ 2462 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2463 } 2464 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2465 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2466 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2467 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2468 if (v & EHCI_PS_PR) i |= UPS_RESET; 2469 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2470 if (sc->sc_vendor_port_status) 2471 i = sc->sc_vendor_port_status(sc, v, i); 2472 USETW(ps.wPortStatus, i); 2473 i = 0; 2474 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2475 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2476 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2477 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2478 USETW(ps.wPortChange, i); 2479 totlen = min(len, sizeof(ps)); 2480 memcpy(buf, &ps, totlen); 2481 break; 2482 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2483 return -1; 2484 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2485 break; 2486 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2487 if (index < 1 || index > sc->sc_noport) { 2488 return -1; 2489 } 2490 port = EHCI_PORTSC(index); 2491 v = EOREAD4(sc, port); 2492 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2493 v &= ~EHCI_PS_CLEAR; 2494 switch(value) { 2495 case UHF_PORT_ENABLE: 2496 EOWRITE4(sc, port, v | EHCI_PS_PE); 2497 break; 2498 case UHF_PORT_SUSPEND: 2499 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2500 break; 2501 case UHF_PORT_RESET: 2502 DPRINTF("reset port %jd", index, 0, 0, 0); 2503 if (EHCI_PS_IS_LOWSPEED(v) 2504 && sc->sc_ncomp > 0 2505 && !(sc->sc_flags & EHCIF_ETTF)) { 2506 /* 2507 * Low speed device on non-ETTF controller or 2508 * unaccompanied controller, give up ownership. 2509 */ 2510 ehci_disown(sc, index, 1); 2511 break; 2512 } 2513 /* Start reset sequence. */ 2514 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2515 EOWRITE4(sc, port, v | EHCI_PS_PR); 2516 /* Wait for reset to complete. */ 2517 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2518 if (sc->sc_dying) { 2519 return -1; 2520 } 2521 /* 2522 * An embedded transaction translator will automatically 2523 * terminate the reset sequence so there's no need to 2524 * it. 2525 */ 2526 v = EOREAD4(sc, port); 2527 if (v & EHCI_PS_PR) { 2528 /* Terminate reset sequence. */ 2529 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2530 /* Wait for HC to complete reset. */ 2531 usb_delay_ms(&sc->sc_bus, 2532 EHCI_PORT_RESET_COMPLETE); 2533 if (sc->sc_dying) { 2534 return -1; 2535 } 2536 } 2537 2538 v = EOREAD4(sc, port); 2539 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2540 if (v & EHCI_PS_PR) { 2541 printf("%s: port reset timeout\n", 2542 device_xname(sc->sc_dev)); 2543 return USBD_TIMEOUT; 2544 } 2545 if (!(v & EHCI_PS_PE)) { 2546 /* Not a high speed device, give up ownership.*/ 2547 ehci_disown(sc, index, 0); 2548 break; 2549 } 2550 sc->sc_isreset[index] = 1; 2551 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2552 v, 0, 0); 2553 break; 2554 case UHF_PORT_POWER: 2555 DPRINTF("set port power %jd (has PPC = %jd)", index, 2556 sc->sc_hasppc, 0, 0); 2557 if (sc->sc_hasppc) 2558 EOWRITE4(sc, port, v | EHCI_PS_PP); 2559 break; 2560 case UHF_PORT_TEST: 2561 DPRINTF("set port test %jd", index, 0, 0, 0); 2562 break; 2563 case UHF_PORT_INDICATOR: 2564 DPRINTF("set port ind %jd", index, 0, 0, 0); 2565 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2566 break; 2567 default: 2568 return -1; 2569 } 2570 break; 2571 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2572 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2573 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2574 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2575 break; 2576 default: 2577 /* default from usbroothub */ 2578 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2579 2580 return buflen; 2581 } 2582 2583 DPRINTF("returning %jd", totlen, 0, 0, 0); 2584 2585 return totlen; 2586 } 2587 2588 Static void 2589 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2590 { 2591 int port; 2592 uint32_t v; 2593 2594 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2595 2596 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2597 #ifdef DIAGNOSTIC 2598 if (sc->sc_npcomp != 0) { 2599 int i = (index-1) / sc->sc_npcomp; 2600 if (i >= sc->sc_ncomp) 2601 printf("%s: strange port\n", 2602 device_xname(sc->sc_dev)); 2603 else 2604 printf("%s: handing over %s speed device on " 2605 "port %d to %s\n", 2606 device_xname(sc->sc_dev), 2607 lowspeed ? "low" : "full", 2608 index, sc->sc_comps[i] ? 2609 device_xname(sc->sc_comps[i]) : 2610 "companion controller"); 2611 } else { 2612 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2613 } 2614 #endif 2615 port = EHCI_PORTSC(index); 2616 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2617 EOWRITE4(sc, port, v | EHCI_PS_PO); 2618 } 2619 2620 Static usbd_status 2621 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2622 { 2623 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2624 usbd_status err; 2625 2626 /* Insert last in queue. */ 2627 mutex_enter(&sc->sc_lock); 2628 err = usb_insert_transfer(xfer); 2629 mutex_exit(&sc->sc_lock); 2630 if (err) 2631 return err; 2632 2633 /* Pipe isn't running, start first */ 2634 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2635 } 2636 2637 Static usbd_status 2638 ehci_root_intr_start(struct usbd_xfer *xfer) 2639 { 2640 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2641 2642 if (sc->sc_dying) 2643 return USBD_IOERROR; 2644 2645 mutex_enter(&sc->sc_lock); 2646 sc->sc_intrxfer = xfer; 2647 mutex_exit(&sc->sc_lock); 2648 2649 return USBD_IN_PROGRESS; 2650 } 2651 2652 /* Abort a root interrupt request. */ 2653 Static void 2654 ehci_root_intr_abort(struct usbd_xfer *xfer) 2655 { 2656 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2657 2658 KASSERT(mutex_owned(&sc->sc_lock)); 2659 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2660 2661 sc->sc_intrxfer = NULL; 2662 2663 xfer->ux_status = USBD_CANCELLED; 2664 usb_transfer_complete(xfer); 2665 } 2666 2667 /* Close the root pipe. */ 2668 Static void 2669 ehci_root_intr_close(struct usbd_pipe *pipe) 2670 { 2671 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2672 2673 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2674 2675 KASSERT(mutex_owned(&sc->sc_lock)); 2676 2677 sc->sc_intrxfer = NULL; 2678 } 2679 2680 Static void 2681 ehci_root_intr_done(struct usbd_xfer *xfer) 2682 { 2683 } 2684 2685 /************************/ 2686 2687 Static ehci_soft_qh_t * 2688 ehci_alloc_sqh(ehci_softc_t *sc) 2689 { 2690 ehci_soft_qh_t *sqh; 2691 usbd_status err; 2692 int i, offs; 2693 usb_dma_t dma; 2694 2695 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2696 2697 mutex_enter(&sc->sc_lock); 2698 if (sc->sc_freeqhs == NULL) { 2699 DPRINTF("allocating chunk", 0, 0, 0, 0); 2700 mutex_exit(&sc->sc_lock); 2701 2702 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2703 EHCI_PAGE_SIZE, &dma); 2704 #ifdef EHCI_DEBUG 2705 if (err) 2706 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2707 #endif 2708 if (err) 2709 return NULL; 2710 2711 mutex_enter(&sc->sc_lock); 2712 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2713 offs = i * EHCI_SQH_SIZE; 2714 sqh = KERNADDR(&dma, offs); 2715 sqh->physaddr = DMAADDR(&dma, offs); 2716 sqh->dma = dma; 2717 sqh->offs = offs; 2718 sqh->next = sc->sc_freeqhs; 2719 sc->sc_freeqhs = sqh; 2720 } 2721 } 2722 sqh = sc->sc_freeqhs; 2723 sc->sc_freeqhs = sqh->next; 2724 mutex_exit(&sc->sc_lock); 2725 2726 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2727 sqh->next = NULL; 2728 return sqh; 2729 } 2730 2731 Static void 2732 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2733 { 2734 KASSERT(mutex_owned(&sc->sc_lock)); 2735 2736 sqh->next = sc->sc_freeqhs; 2737 sc->sc_freeqhs = sqh; 2738 } 2739 2740 Static ehci_soft_qtd_t * 2741 ehci_alloc_sqtd(ehci_softc_t *sc) 2742 { 2743 ehci_soft_qtd_t *sqtd = NULL; 2744 usbd_status err; 2745 int i, offs; 2746 usb_dma_t dma; 2747 2748 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2749 2750 mutex_enter(&sc->sc_lock); 2751 if (sc->sc_freeqtds == NULL) { 2752 DPRINTF("allocating chunk", 0, 0, 0, 0); 2753 mutex_exit(&sc->sc_lock); 2754 2755 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2756 EHCI_PAGE_SIZE, &dma); 2757 #ifdef EHCI_DEBUG 2758 if (err) 2759 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2760 #endif 2761 if (err) 2762 goto done; 2763 2764 mutex_enter(&sc->sc_lock); 2765 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2766 offs = i * EHCI_SQTD_SIZE; 2767 sqtd = KERNADDR(&dma, offs); 2768 sqtd->physaddr = DMAADDR(&dma, offs); 2769 sqtd->dma = dma; 2770 sqtd->offs = offs; 2771 2772 sqtd->nextqtd = sc->sc_freeqtds; 2773 sc->sc_freeqtds = sqtd; 2774 } 2775 } 2776 2777 sqtd = sc->sc_freeqtds; 2778 sc->sc_freeqtds = sqtd->nextqtd; 2779 mutex_exit(&sc->sc_lock); 2780 2781 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2782 sqtd->nextqtd = NULL; 2783 sqtd->xfer = NULL; 2784 2785 done: 2786 return sqtd; 2787 } 2788 2789 Static void 2790 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2791 { 2792 2793 mutex_enter(&sc->sc_lock); 2794 sqtd->nextqtd = sc->sc_freeqtds; 2795 sc->sc_freeqtds = sqtd; 2796 mutex_exit(&sc->sc_lock); 2797 } 2798 2799 Static int 2800 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2801 int alen, int rd, ehci_soft_qtd_t **sp) 2802 { 2803 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2804 uint16_t flags = xfer->ux_flags; 2805 2806 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2807 2808 ASSERT_SLEEPABLE(); 2809 KASSERT(sp); 2810 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2811 2812 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2813 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2814 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2815 KM_SLEEP); 2816 exfer->ex_nsqtd = nsqtd; 2817 2818 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2819 alen, nsqtd, flags); 2820 2821 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2822 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2823 if (cur == NULL) 2824 goto nomem; 2825 exfer->ex_sqtds[j++] = cur; 2826 2827 cur->xfer = xfer; 2828 cur->len = 0; 2829 2830 } 2831 2832 *sp = exfer->ex_sqtds[0]; 2833 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2834 2835 return 0; 2836 2837 nomem: 2838 ehci_free_sqtds(sc, exfer); 2839 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2840 DPRINTF("no memory", 0, 0, 0, 0); 2841 return ENOMEM; 2842 } 2843 2844 Static void 2845 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2846 { 2847 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2848 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2849 2850 mutex_enter(&sc->sc_lock); 2851 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2852 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2853 2854 if (sqtd == NULL) 2855 break; 2856 2857 sqtd->nextqtd = sc->sc_freeqtds; 2858 sc->sc_freeqtds = sqtd; 2859 } 2860 mutex_exit(&sc->sc_lock); 2861 } 2862 2863 Static void 2864 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2865 { 2866 if (prev) { 2867 prev->nextqtd = sqtd; 2868 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2869 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2870 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2871 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2872 } 2873 } 2874 2875 Static void 2876 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2877 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2878 { 2879 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2880 usb_dma_t *dma = &xfer->ux_dmabuf; 2881 uint16_t flags = xfer->ux_flags; 2882 ehci_soft_qtd_t *sqtd, *prev; 2883 int tog = *toggle; 2884 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2885 int len = length; 2886 2887 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2888 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2889 len, isread, tog); 2890 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2891 0, 0, 0); 2892 2893 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2894 2895 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2896 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2897 EHCI_QTD_SET_CERR(3) 2898 ; 2899 2900 sqtd = prev = NULL; 2901 size_t curoffs = 0; 2902 size_t j = 0; 2903 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2904 sqtd = exfer->ex_sqtds[j++]; 2905 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 2906 (uintptr_t)prev, 0); 2907 2908 /* 2909 * The EHCI hardware can handle at most 5 pages and they do 2910 * not have to be contiguous 2911 */ 2912 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2913 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2914 size_t curlen = len; 2915 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2916 /* must use multiple TDs, fill as much as possible. */ 2917 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2918 2919 /* the length must be a multiple of the max size */ 2920 curlen -= curlen % mps; 2921 } 2922 KASSERT(curlen != 0); 2923 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 2924 curoffs, 0); 2925 2926 /* Fill the qTD */ 2927 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2928 sqtd->qtd.qtd_status = htole32( 2929 qtdstatus | 2930 EHCI_QTD_SET_BYTES(curlen) | 2931 EHCI_QTD_SET_TOGGLE(tog)); 2932 2933 /* Find number of pages we'll be using, insert dma addresses */ 2934 size_t pages = EHCI_NPAGES(curlen); 2935 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2936 size_t pageoffs = EHCI_PAGE(curoffs); 2937 for (size_t i = 0; i < pages; i++) { 2938 paddr_t a = DMAADDR(dma, 2939 pageoffs + i * EHCI_PAGE_SIZE); 2940 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2941 /* Cast up to avoid compiler warnings */ 2942 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2943 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 2944 i, pages, 2945 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2946 le32toh(sqtd->qtd.qtd_buffer[i])); 2947 } 2948 /* First buffer pointer requires a page offset to start at */ 2949 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2950 2951 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2952 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2953 2954 sqtd->len = curlen; 2955 2956 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 2957 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2958 2959 ehci_append_sqtd(sqtd, prev); 2960 2961 if (((curlen + mps - 1) / mps) & 1) { 2962 tog ^= 1; 2963 } 2964 2965 curoffs += curlen; 2966 len -= curlen; 2967 } 2968 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2969 xfer, length, len, mps, exfer->ex_nsqtd, j); 2970 2971 if (!isread && 2972 (flags & USBD_FORCE_SHORT_XFER) && 2973 length % mps == 0) { 2974 /* Force a 0 length transfer at the end. */ 2975 2976 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2977 exfer->ex_nsqtd); 2978 prev = sqtd; 2979 sqtd = exfer->ex_sqtds[j++]; 2980 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 2981 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2982 sqtd->qtd.qtd_status = htole32( 2983 qtdstatus | 2984 EHCI_QTD_SET_BYTES(0) | 2985 EHCI_QTD_SET_TOGGLE(tog)); 2986 2987 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2989 2990 ehci_append_sqtd(sqtd, prev); 2991 tog ^= 1; 2992 } 2993 2994 *lsqtd = sqtd; 2995 *toggle = tog; 2996 } 2997 2998 Static ehci_soft_itd_t * 2999 ehci_alloc_itd(ehci_softc_t *sc) 3000 { 3001 struct ehci_soft_itd *itd, *freeitd; 3002 usbd_status err; 3003 usb_dma_t dma; 3004 3005 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3006 3007 mutex_enter(&sc->sc_lock); 3008 3009 freeitd = LIST_FIRST(&sc->sc_freeitds); 3010 if (freeitd == NULL) { 3011 DPRINTF("allocating chunk", 0, 0, 0, 0); 3012 mutex_exit(&sc->sc_lock); 3013 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3014 EHCI_PAGE_SIZE, &dma); 3015 3016 if (err) { 3017 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3018 return NULL; 3019 } 3020 mutex_enter(&sc->sc_lock); 3021 3022 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3023 int offs = i * EHCI_ITD_SIZE; 3024 itd = KERNADDR(&dma, offs); 3025 itd->physaddr = DMAADDR(&dma, offs); 3026 itd->dma = dma; 3027 itd->offs = offs; 3028 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3029 } 3030 freeitd = LIST_FIRST(&sc->sc_freeitds); 3031 } 3032 3033 itd = freeitd; 3034 LIST_REMOVE(itd, free_list); 3035 mutex_exit(&sc->sc_lock); 3036 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3037 3038 itd->frame_list.next = NULL; 3039 itd->frame_list.prev = NULL; 3040 itd->xfer_next = NULL; 3041 itd->slot = 0; 3042 3043 return itd; 3044 } 3045 3046 Static ehci_soft_sitd_t * 3047 ehci_alloc_sitd(ehci_softc_t *sc) 3048 { 3049 struct ehci_soft_sitd *sitd, *freesitd; 3050 usbd_status err; 3051 int i, offs; 3052 usb_dma_t dma; 3053 3054 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3055 3056 mutex_enter(&sc->sc_lock); 3057 freesitd = LIST_FIRST(&sc->sc_freesitds); 3058 if (freesitd == NULL) { 3059 DPRINTF("allocating chunk", 0, 0, 0, 0); 3060 mutex_exit(&sc->sc_lock); 3061 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3062 EHCI_PAGE_SIZE, &dma); 3063 3064 if (err) { 3065 DPRINTF("alloc returned %jd", err, 0, 0, 3066 0); 3067 return NULL; 3068 } 3069 3070 mutex_enter(&sc->sc_lock); 3071 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3072 offs = i * EHCI_SITD_SIZE; 3073 sitd = KERNADDR(&dma, offs); 3074 sitd->physaddr = DMAADDR(&dma, offs); 3075 sitd->dma = dma; 3076 sitd->offs = offs; 3077 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3078 } 3079 freesitd = LIST_FIRST(&sc->sc_freesitds); 3080 } 3081 3082 sitd = freesitd; 3083 LIST_REMOVE(sitd, free_list); 3084 mutex_exit(&sc->sc_lock); 3085 3086 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3087 3088 sitd->frame_list.next = NULL; 3089 sitd->frame_list.prev = NULL; 3090 sitd->xfer_next = NULL; 3091 sitd->slot = 0; 3092 3093 return sitd; 3094 } 3095 3096 /****************/ 3097 3098 /* 3099 * Close a reqular pipe. 3100 * Assumes that there are no pending transactions. 3101 */ 3102 Static void 3103 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3104 { 3105 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3106 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3107 ehci_soft_qh_t *sqh = epipe->sqh; 3108 3109 KASSERT(mutex_owned(&sc->sc_lock)); 3110 3111 ehci_rem_qh(sc, sqh, head); 3112 ehci_free_sqh(sc, epipe->sqh); 3113 } 3114 3115 /* 3116 * Cancel or timeout a device request. We have two cases to deal with 3117 * 3118 * 1) A driver wants to stop scheduled or inflight transfers 3119 * 2) A transfer has timed out 3120 * 3121 * have (partially) happened since the hardware runs concurrently. 3122 * 3123 * Transfer state is protected by the bus lock and we set the transfer status 3124 * as soon as either of the above happens (with bus lock held). 3125 * 3126 * Then we arrange for the hardware to tells us that it is not still 3127 * processing the TDs by setting the QH halted bit and wait for the ehci 3128 * door bell 3129 */ 3130 Static void 3131 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3132 { 3133 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3134 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3135 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3136 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3137 ehci_soft_qh_t *sqh = epipe->sqh; 3138 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3139 ehci_physaddr_t cur; 3140 uint32_t qhstatus; 3141 int hit; 3142 3143 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 3144 "invalid status for abort: %d", (int)status); 3145 3146 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3147 3148 KASSERT(mutex_owned(&sc->sc_lock)); 3149 ASSERT_SLEEPABLE(); 3150 3151 if (status == USBD_CANCELLED) { 3152 /* 3153 * We are synchronously aborting. Try to stop the 3154 * callout and task, but if we can't, wait for them to 3155 * complete. 3156 */ 3157 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3158 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 3159 USB_TASKQ_HC, &sc->sc_lock); 3160 } else { 3161 /* Otherwise, we are timing out. */ 3162 KASSERT(status == USBD_TIMEOUT); 3163 } 3164 3165 /* 3166 * The xfer cannot have been cancelled already. It is the 3167 * responsibility of the caller of usbd_abort_pipe not to try 3168 * to abort a pipe multiple times, whether concurrently or 3169 * sequentially. 3170 */ 3171 KASSERT(xfer->ux_status != USBD_CANCELLED); 3172 3173 /* Only the timeout, which runs only once, can time it out. */ 3174 KASSERT(xfer->ux_status != USBD_TIMEOUT); 3175 3176 /* If anyone else beat us, we're done. */ 3177 if (xfer->ux_status != USBD_IN_PROGRESS) 3178 return; 3179 3180 /* We beat everyone else. Claim the status. */ 3181 xfer->ux_status = status; 3182 3183 /* 3184 * If we're dying, skip the hardware action and just notify the 3185 * software that we're done. 3186 */ 3187 if (sc->sc_dying) { 3188 goto dying; 3189 } 3190 3191 /* 3192 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3193 */ 3194 ehci_del_intr_list(sc, exfer); 3195 3196 usb_syncmem(&sqh->dma, 3197 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3198 sizeof(sqh->qh.qh_qtd.qtd_status), 3199 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3200 qhstatus = sqh->qh.qh_qtd.qtd_status; 3201 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3202 usb_syncmem(&sqh->dma, 3203 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3204 sizeof(sqh->qh.qh_qtd.qtd_status), 3205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3206 3207 if (exfer->ex_type == EX_CTRL) { 3208 fsqtd = exfer->ex_setup; 3209 lsqtd = exfer->ex_status; 3210 } else { 3211 fsqtd = exfer->ex_sqtdstart; 3212 lsqtd = exfer->ex_sqtdend; 3213 } 3214 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3215 usb_syncmem(&sqtd->dma, 3216 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3217 sizeof(sqtd->qtd.qtd_status), 3218 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3219 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3220 usb_syncmem(&sqtd->dma, 3221 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3222 sizeof(sqtd->qtd.qtd_status), 3223 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3224 if (sqtd == lsqtd) 3225 break; 3226 } 3227 3228 /* 3229 * HC Step 2: Wait until we know hardware has finished any possible 3230 * use of the xfer. 3231 */ 3232 ehci_sync_hc(sc); 3233 3234 /* 3235 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3236 * The complication here is that the hardware may have executed 3237 * beyond the xfer we're trying to abort. So as we're scanning 3238 * the TDs of this xfer we check if the hardware points to 3239 * any of them. 3240 */ 3241 3242 usb_syncmem(&sqh->dma, 3243 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3244 sizeof(sqh->qh.qh_curqtd), 3245 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3246 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3247 hit = 0; 3248 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3249 hit |= cur == sqtd->physaddr; 3250 if (sqtd == lsqtd) 3251 break; 3252 } 3253 sqtd = sqtd->nextqtd; 3254 /* Zap curqtd register if hardware pointed inside the xfer. */ 3255 if (hit && sqtd != NULL) { 3256 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3257 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3258 usb_syncmem(&sqh->dma, 3259 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3260 sizeof(sqh->qh.qh_curqtd), 3261 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3262 sqh->qh.qh_qtd.qtd_status = qhstatus; 3263 usb_syncmem(&sqh->dma, 3264 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3265 sizeof(sqh->qh.qh_qtd.qtd_status), 3266 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3267 } else { 3268 DPRINTF("no hit", 0, 0, 0, 0); 3269 usb_syncmem(&sqh->dma, 3270 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3271 sizeof(sqh->qh.qh_curqtd), 3272 BUS_DMASYNC_PREREAD); 3273 } 3274 3275 /* 3276 * Final step: Notify completion to waiting xfers. 3277 */ 3278 dying: 3279 #ifdef DIAGNOSTIC 3280 exfer->ex_isdone = true; 3281 #endif 3282 usb_transfer_complete(xfer); 3283 DPRINTFN(14, "end", 0, 0, 0, 0); 3284 3285 KASSERT(mutex_owned(&sc->sc_lock)); 3286 } 3287 3288 Static void 3289 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3290 { 3291 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3292 ehci_isoc_trans_t trans_status; 3293 struct ehci_xfer *exfer; 3294 ehci_softc_t *sc; 3295 struct ehci_soft_itd *itd; 3296 struct ehci_soft_sitd *sitd; 3297 int i; 3298 3299 KASSERTMSG(status == USBD_CANCELLED, 3300 "invalid status for abort: %d", (int)status); 3301 3302 exfer = EHCI_XFER2EXFER(xfer); 3303 sc = EHCI_XFER2SC(xfer); 3304 3305 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3306 (uintptr_t)xfer->ux_pipe, 0, 0); 3307 3308 KASSERT(mutex_owned(&sc->sc_lock)); 3309 ASSERT_SLEEPABLE(); 3310 3311 /* No timeout or task here. */ 3312 3313 /* 3314 * The xfer cannot have been cancelled already. It is the 3315 * responsibility of the caller of usbd_abort_pipe not to try 3316 * to abort a pipe multiple times, whether concurrently or 3317 * sequentially. 3318 */ 3319 KASSERT(xfer->ux_status != USBD_CANCELLED); 3320 3321 /* If anyone else beat us, we're done. */ 3322 if (xfer->ux_status != USBD_IN_PROGRESS) 3323 return; 3324 3325 /* We beat everyone else. Claim the status. */ 3326 xfer->ux_status = status; 3327 3328 /* 3329 * If we're dying, skip the hardware action and just notify the 3330 * software that we're done. 3331 */ 3332 if (sc->sc_dying) { 3333 goto dying; 3334 } 3335 3336 /* 3337 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3338 */ 3339 ehci_del_intr_list(sc, exfer); 3340 3341 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3342 for (itd = exfer->ex_itdstart; itd != NULL; 3343 itd = itd->xfer_next) { 3344 usb_syncmem(&itd->dma, 3345 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3346 sizeof(itd->itd.itd_ctl), 3347 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3348 3349 for (i = 0; i < 8; i++) { 3350 trans_status = le32toh(itd->itd.itd_ctl[i]); 3351 trans_status &= ~EHCI_ITD_ACTIVE; 3352 itd->itd.itd_ctl[i] = htole32(trans_status); 3353 } 3354 3355 usb_syncmem(&itd->dma, 3356 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3357 sizeof(itd->itd.itd_ctl), 3358 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3359 } 3360 } else { 3361 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3362 sitd = sitd->xfer_next) { 3363 usb_syncmem(&sitd->dma, 3364 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3365 sizeof(sitd->sitd.sitd_buffer), 3366 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3367 3368 trans_status = le32toh(sitd->sitd.sitd_trans); 3369 trans_status &= ~EHCI_SITD_ACTIVE; 3370 sitd->sitd.sitd_trans = htole32(trans_status); 3371 3372 usb_syncmem(&sitd->dma, 3373 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3374 sizeof(sitd->sitd.sitd_buffer), 3375 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3376 } 3377 } 3378 3379 dying: 3380 #ifdef DIAGNOSTIC 3381 exfer->ex_isdone = true; 3382 #endif 3383 usb_transfer_complete(xfer); 3384 DPRINTFN(14, "end", 0, 0, 0, 0); 3385 3386 KASSERT(mutex_owned(&sc->sc_lock)); 3387 } 3388 3389 Static void 3390 ehci_timeout(void *addr) 3391 { 3392 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3393 struct usbd_xfer *xfer = addr; 3394 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3395 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3396 3397 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3398 #ifdef EHCI_DEBUG 3399 if (ehcidebug >= 2) { 3400 struct usbd_pipe *pipe = xfer->ux_pipe; 3401 usbd_dump_pipe(pipe); 3402 } 3403 #endif 3404 3405 mutex_enter(&sc->sc_lock); 3406 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 3407 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3408 mutex_exit(&sc->sc_lock); 3409 } 3410 3411 Static void 3412 ehci_timeout_task(void *addr) 3413 { 3414 struct usbd_xfer *xfer = addr; 3415 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3416 3417 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3418 3419 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3420 3421 mutex_enter(&sc->sc_lock); 3422 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3423 mutex_exit(&sc->sc_lock); 3424 } 3425 3426 /************************/ 3427 3428 Static int 3429 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3430 { 3431 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3432 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3433 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3434 usb_device_request_t *req = &xfer->ux_request; 3435 ehci_soft_qtd_t *setup, *status, *next; 3436 int isread = req->bmRequestType & UT_READ; 3437 int len = xfer->ux_bufsize; 3438 int err; 3439 3440 exfer->ex_type = EX_CTRL; 3441 exfer->ex_status = NULL; 3442 exfer->ex_data = NULL; 3443 exfer->ex_setup = ehci_alloc_sqtd(sc); 3444 if (exfer->ex_setup == NULL) { 3445 err = ENOMEM; 3446 goto bad1; 3447 } 3448 exfer->ex_status = ehci_alloc_sqtd(sc); 3449 if (exfer->ex_status == NULL) { 3450 err = ENOMEM; 3451 goto bad2; 3452 } 3453 setup = exfer->ex_setup; 3454 status = exfer->ex_status; 3455 exfer->ex_nsqtd = 0; 3456 next = status; 3457 /* Set up data transaction */ 3458 if (len != 0) { 3459 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3460 &exfer->ex_data); 3461 if (err) 3462 goto bad3; 3463 next = exfer->ex_data; 3464 } 3465 3466 /* Clear toggle */ 3467 setup->qtd.qtd_status = htole32( 3468 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3469 EHCI_QTD_SET_TOGGLE(0) | 3470 EHCI_QTD_SET_BYTES(sizeof(*req)) 3471 ); 3472 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3473 setup->qtd.qtd_buffer_hi[0] = 0; 3474 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3475 setup->nextqtd = next; 3476 setup->xfer = xfer; 3477 setup->len = sizeof(*req); 3478 3479 status->qtd.qtd_status = htole32( 3480 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3481 EHCI_QTD_SET_TOGGLE(1) | 3482 EHCI_QTD_IOC 3483 ); 3484 status->qtd.qtd_buffer[0] = 0; 3485 status->qtd.qtd_buffer_hi[0] = 0; 3486 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3487 status->nextqtd = NULL; 3488 status->xfer = xfer; 3489 status->len = 0; 3490 3491 return 0; 3492 bad3: 3493 ehci_free_sqtd(sc, exfer->ex_status); 3494 bad2: 3495 ehci_free_sqtd(sc, exfer->ex_setup); 3496 bad1: 3497 return err; 3498 } 3499 3500 Static void 3501 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3502 { 3503 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3504 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3505 3506 KASSERT(ex->ex_type == EX_CTRL); 3507 3508 ehci_free_sqtd(sc, ex->ex_setup); 3509 ehci_free_sqtd(sc, ex->ex_status); 3510 ehci_free_sqtds(sc, ex); 3511 if (ex->ex_nsqtd) 3512 kmem_free(ex->ex_sqtds, 3513 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3514 } 3515 3516 Static usbd_status 3517 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3518 { 3519 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3520 usbd_status err; 3521 3522 /* Insert last in queue. */ 3523 mutex_enter(&sc->sc_lock); 3524 err = usb_insert_transfer(xfer); 3525 mutex_exit(&sc->sc_lock); 3526 if (err) 3527 return err; 3528 3529 /* Pipe isn't running, start first */ 3530 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3531 } 3532 3533 Static usbd_status 3534 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3535 { 3536 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3537 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3538 usb_device_request_t *req = &xfer->ux_request; 3539 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3540 ehci_soft_qtd_t *setup, *status, *next; 3541 ehci_soft_qh_t *sqh; 3542 3543 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3544 3545 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3546 3547 if (sc->sc_dying) 3548 return USBD_IOERROR; 3549 3550 const int isread = req->bmRequestType & UT_READ; 3551 const int len = UGETW(req->wLength); 3552 3553 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3554 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3555 UGETW(req->wIndex)); 3556 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3557 len, epipe->pipe.up_dev->ud_addr, 3558 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3559 3560 sqh = epipe->sqh; 3561 3562 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3563 "address QH %" __PRIuBIT " pipe %d\n", 3564 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3565 epipe->pipe.up_dev->ud_addr); 3566 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3567 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3568 "MPS QH %" __PRIuBIT " pipe %d\n", 3569 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3570 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3571 3572 setup = exfer->ex_setup; 3573 status = exfer->ex_status; 3574 3575 DPRINTF("setup %#jx status %#jx data %#jx", 3576 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3577 KASSERTMSG(setup != NULL && status != NULL, 3578 "Failed memory allocation, setup %p status %p", 3579 setup, status); 3580 3581 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3582 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3583 3584 /* Clear toggle */ 3585 setup->qtd.qtd_status &= ~htole32( 3586 EHCI_QTD_STATUS_MASK | 3587 EHCI_QTD_BYTES_MASK | 3588 EHCI_QTD_TOGGLE_MASK | 3589 EHCI_QTD_CERR_MASK 3590 ); 3591 setup->qtd.qtd_status |= htole32( 3592 EHCI_QTD_ACTIVE | 3593 EHCI_QTD_SET_CERR(3) | 3594 EHCI_QTD_SET_TOGGLE(0) | 3595 EHCI_QTD_SET_BYTES(sizeof(*req)) 3596 ); 3597 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3598 setup->qtd.qtd_buffer_hi[0] = 0; 3599 3600 next = status; 3601 status->qtd.qtd_status &= ~htole32( 3602 EHCI_QTD_STATUS_MASK | 3603 EHCI_QTD_PID_MASK | 3604 EHCI_QTD_BYTES_MASK | 3605 EHCI_QTD_TOGGLE_MASK | 3606 EHCI_QTD_CERR_MASK 3607 ); 3608 status->qtd.qtd_status |= htole32( 3609 EHCI_QTD_ACTIVE | 3610 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3611 EHCI_QTD_SET_CERR(3) | 3612 EHCI_QTD_SET_TOGGLE(1) | 3613 EHCI_QTD_SET_BYTES(0) | 3614 EHCI_QTD_IOC 3615 ); 3616 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3617 3618 KASSERT(exfer->ex_isdone); 3619 #ifdef DIAGNOSTIC 3620 exfer->ex_isdone = false; 3621 #endif 3622 3623 /* Set up data transaction */ 3624 if (len != 0) { 3625 ehci_soft_qtd_t *end; 3626 3627 /* Start toggle at 1. */ 3628 int toggle = 1; 3629 next = exfer->ex_data; 3630 KASSERTMSG(next != NULL, "Failed memory allocation"); 3631 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3632 end->nextqtd = status; 3633 end->qtd.qtd_next = end->qtd.qtd_altnext = 3634 htole32(status->physaddr); 3635 3636 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3637 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3638 3639 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3640 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3641 } 3642 3643 setup->nextqtd = next; 3644 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3645 3646 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3647 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3648 3649 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3650 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3651 3652 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3653 3654 #ifdef EHCI_DEBUG 3655 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3656 ehci_dump_sqh(sqh); 3657 ehci_dump_sqtds(setup); 3658 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3659 #endif 3660 3661 mutex_enter(&sc->sc_lock); 3662 3663 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3664 ehci_set_qh_qtd(sqh, setup); 3665 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3666 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3667 ehci_timeout, xfer); 3668 } 3669 ehci_add_intr_list(sc, exfer); 3670 xfer->ux_status = USBD_IN_PROGRESS; 3671 mutex_exit(&sc->sc_lock); 3672 3673 #if 0 3674 #ifdef EHCI_DEBUG 3675 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3676 // delay(10000); 3677 ehci_dump_regs(sc); 3678 ehci_dump_sqh(sc->sc_async_head); 3679 ehci_dump_sqh(sqh); 3680 ehci_dump_sqtds(setup); 3681 #endif 3682 #endif 3683 3684 return USBD_IN_PROGRESS; 3685 } 3686 3687 Static void 3688 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3689 { 3690 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3691 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3692 usb_device_request_t *req = &xfer->ux_request; 3693 int len = UGETW(req->wLength); 3694 int rd = req->bmRequestType & UT_READ; 3695 3696 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3697 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3698 3699 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3700 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3701 3702 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3703 BUS_DMASYNC_POSTWRITE); 3704 if (len) 3705 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3706 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3707 3708 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3709 } 3710 3711 /* Abort a device control request. */ 3712 Static void 3713 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3714 { 3715 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3716 3717 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3718 ehci_abort_xfer(xfer, USBD_CANCELLED); 3719 } 3720 3721 /* Close a device control pipe. */ 3722 Static void 3723 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3724 { 3725 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3726 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3727 3728 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3729 3730 KASSERT(mutex_owned(&sc->sc_lock)); 3731 3732 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3733 3734 ehci_close_pipe(pipe, sc->sc_async_head); 3735 } 3736 3737 /* 3738 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3739 * qTD status, or miss signalling occasionally under heavy load. If the host 3740 * machine is too fast, we we can miss transaction completion - when we scan 3741 * the active list the transaction still seems to be active. This generally 3742 * exhibits itself as a umass stall that never recovers. 3743 * 3744 * We work around this behaviour by setting up this callback after any softintr 3745 * that completes with transactions still pending, giving us another chance to 3746 * check for completion after the writeback has taken place. 3747 */ 3748 Static void 3749 ehci_intrlist_timeout(void *arg) 3750 { 3751 ehci_softc_t *sc = arg; 3752 3753 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3754 3755 usb_schedsoftintr(&sc->sc_bus); 3756 } 3757 3758 /************************/ 3759 3760 Static int 3761 ehci_device_bulk_init(struct usbd_xfer *xfer) 3762 { 3763 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3764 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3765 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3766 int endpt = ed->bEndpointAddress; 3767 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3768 int len = xfer->ux_bufsize; 3769 int err = 0; 3770 3771 exfer->ex_type = EX_BULK; 3772 exfer->ex_nsqtd = 0; 3773 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3774 &exfer->ex_sqtdstart); 3775 3776 return err; 3777 } 3778 3779 Static void 3780 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3781 { 3782 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3783 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3784 3785 KASSERT(ex->ex_type == EX_BULK); 3786 3787 ehci_free_sqtds(sc, ex); 3788 if (ex->ex_nsqtd) 3789 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3790 } 3791 3792 Static usbd_status 3793 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3794 { 3795 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3796 usbd_status err; 3797 3798 /* Insert last in queue. */ 3799 mutex_enter(&sc->sc_lock); 3800 err = usb_insert_transfer(xfer); 3801 mutex_exit(&sc->sc_lock); 3802 if (err) 3803 return err; 3804 3805 /* Pipe isn't running, start first */ 3806 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3807 } 3808 3809 Static usbd_status 3810 ehci_device_bulk_start(struct usbd_xfer *xfer) 3811 { 3812 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3813 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3814 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3815 ehci_soft_qh_t *sqh; 3816 ehci_soft_qtd_t *end; 3817 int len, isread, endpt; 3818 3819 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3820 3821 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3822 xfer->ux_flags, 0); 3823 3824 if (sc->sc_dying) 3825 return USBD_IOERROR; 3826 3827 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3828 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3829 3830 len = xfer->ux_length; 3831 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3832 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3833 sqh = epipe->sqh; 3834 3835 KASSERT(exfer->ex_isdone); 3836 #ifdef DIAGNOSTIC 3837 exfer->ex_isdone = false; 3838 #endif 3839 3840 /* Take lock here to protect nexttoggle */ 3841 mutex_enter(&sc->sc_lock); 3842 3843 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3844 3845 exfer->ex_sqtdend = end; 3846 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3847 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3848 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3849 3850 #ifdef EHCI_DEBUG 3851 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3852 ehci_dump_sqh(sqh); 3853 ehci_dump_sqtds(exfer->ex_sqtdstart); 3854 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3855 #endif 3856 3857 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3858 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3859 3860 /* also does usb_syncmem(sqh) */ 3861 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3862 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3863 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3864 ehci_timeout, xfer); 3865 } 3866 ehci_add_intr_list(sc, exfer); 3867 xfer->ux_status = USBD_IN_PROGRESS; 3868 mutex_exit(&sc->sc_lock); 3869 3870 #if 0 3871 #ifdef EHCI_DEBUG 3872 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3873 // delay(10000); 3874 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3875 ehci_dump_regs(sc); 3876 #if 0 3877 printf("async_head:\n"); 3878 ehci_dump_sqh(sc->sc_async_head); 3879 #endif 3880 DPRINTF("sqh:", 0, 0, 0, 0); 3881 ehci_dump_sqh(sqh); 3882 ehci_dump_sqtds(exfer->ex_sqtdstart); 3883 #endif 3884 #endif 3885 3886 return USBD_IN_PROGRESS; 3887 } 3888 3889 Static void 3890 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3891 { 3892 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3893 3894 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3895 ehci_abort_xfer(xfer, USBD_CANCELLED); 3896 } 3897 3898 /* 3899 * Close a device bulk pipe. 3900 */ 3901 Static void 3902 ehci_device_bulk_close(struct usbd_pipe *pipe) 3903 { 3904 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3905 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3906 3907 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3908 3909 KASSERT(mutex_owned(&sc->sc_lock)); 3910 3911 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3912 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3913 ehci_close_pipe(pipe, sc->sc_async_head); 3914 } 3915 3916 Static void 3917 ehci_device_bulk_done(struct usbd_xfer *xfer) 3918 { 3919 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3920 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3921 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3922 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3923 3924 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3925 3926 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 3927 3928 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3929 3930 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3931 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3932 3933 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3934 } 3935 3936 /************************/ 3937 3938 Static usbd_status 3939 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3940 { 3941 struct ehci_soft_islot *isp; 3942 int islot, lev; 3943 3944 /* Find a poll rate that is large enough. */ 3945 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3946 if (EHCI_ILEV_IVAL(lev) <= ival) 3947 break; 3948 3949 /* Pick an interrupt slot at the right level. */ 3950 /* XXX could do better than picking at random */ 3951 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3952 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3953 3954 sqh->islot = islot; 3955 isp = &sc->sc_islots[islot]; 3956 mutex_enter(&sc->sc_lock); 3957 ehci_add_qh(sc, sqh, isp->sqh); 3958 mutex_exit(&sc->sc_lock); 3959 3960 return USBD_NORMAL_COMPLETION; 3961 } 3962 3963 3964 Static int 3965 ehci_device_intr_init(struct usbd_xfer *xfer) 3966 { 3967 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3968 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3969 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3970 int endpt = ed->bEndpointAddress; 3971 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3972 int len = xfer->ux_bufsize; 3973 int err; 3974 3975 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3976 3977 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3978 xfer->ux_flags, 0); 3979 3980 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3981 KASSERT(len != 0); 3982 3983 exfer->ex_type = EX_INTR; 3984 exfer->ex_nsqtd = 0; 3985 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3986 &exfer->ex_sqtdstart); 3987 3988 return err; 3989 } 3990 3991 Static void 3992 ehci_device_intr_fini(struct usbd_xfer *xfer) 3993 { 3994 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3995 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3996 3997 KASSERT(ex->ex_type == EX_INTR); 3998 3999 ehci_free_sqtds(sc, ex); 4000 if (ex->ex_nsqtd) 4001 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4002 } 4003 4004 Static usbd_status 4005 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4006 { 4007 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4008 usbd_status err; 4009 4010 /* Insert last in queue. */ 4011 mutex_enter(&sc->sc_lock); 4012 err = usb_insert_transfer(xfer); 4013 mutex_exit(&sc->sc_lock); 4014 if (err) 4015 return err; 4016 4017 /* 4018 * Pipe isn't running (otherwise err would be USBD_INPROG), 4019 * so start it first. 4020 */ 4021 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4022 } 4023 4024 Static usbd_status 4025 ehci_device_intr_start(struct usbd_xfer *xfer) 4026 { 4027 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4028 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4029 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4030 ehci_soft_qtd_t *end; 4031 ehci_soft_qh_t *sqh; 4032 int len, isread, endpt; 4033 4034 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4035 4036 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4037 xfer->ux_flags, 0); 4038 4039 if (sc->sc_dying) 4040 return USBD_IOERROR; 4041 4042 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4043 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4044 4045 len = xfer->ux_length; 4046 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4047 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4048 sqh = epipe->sqh; 4049 4050 KASSERT(exfer->ex_isdone); 4051 #ifdef DIAGNOSTIC 4052 exfer->ex_isdone = false; 4053 #endif 4054 4055 /* Take lock to protect nexttoggle */ 4056 mutex_enter(&sc->sc_lock); 4057 4058 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4059 4060 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4061 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4062 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4063 exfer->ex_sqtdend = end; 4064 4065 #ifdef EHCI_DEBUG 4066 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4067 ehci_dump_sqh(sqh); 4068 ehci_dump_sqtds(exfer->ex_sqtdstart); 4069 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4070 #endif 4071 4072 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4073 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4074 4075 /* also does usb_syncmem(sqh) */ 4076 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4077 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4078 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4079 ehci_timeout, xfer); 4080 } 4081 ehci_add_intr_list(sc, exfer); 4082 xfer->ux_status = USBD_IN_PROGRESS; 4083 mutex_exit(&sc->sc_lock); 4084 4085 #if 0 4086 #ifdef EHCI_DEBUG 4087 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4088 // delay(10000); 4089 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4090 ehci_dump_regs(sc); 4091 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4092 ehci_dump_sqh(sqh); 4093 ehci_dump_sqtds(exfer->ex_sqtdstart); 4094 #endif 4095 #endif 4096 4097 return USBD_IN_PROGRESS; 4098 } 4099 4100 Static void 4101 ehci_device_intr_abort(struct usbd_xfer *xfer) 4102 { 4103 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4104 4105 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4106 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4107 4108 /* 4109 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4110 * async doorbell. That's dependent on the async list, wheras 4111 * intr xfers are periodic, should not use this? 4112 */ 4113 ehci_abort_xfer(xfer, USBD_CANCELLED); 4114 } 4115 4116 Static void 4117 ehci_device_intr_close(struct usbd_pipe *pipe) 4118 { 4119 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4120 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4121 struct ehci_soft_islot *isp; 4122 4123 KASSERT(mutex_owned(&sc->sc_lock)); 4124 4125 isp = &sc->sc_islots[epipe->sqh->islot]; 4126 ehci_close_pipe(pipe, isp->sqh); 4127 } 4128 4129 Static void 4130 ehci_device_intr_done(struct usbd_xfer *xfer) 4131 { 4132 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4133 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4134 int isread, endpt; 4135 4136 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4137 4138 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4139 4140 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4141 4142 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4143 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4144 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4145 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4146 } 4147 4148 /************************/ 4149 Static int 4150 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4151 { 4152 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4153 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4154 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4155 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4156 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4157 int i, k, frames; 4158 u_int huba, dir; 4159 int err; 4160 4161 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4162 4163 start = NULL; 4164 sitd = NULL; 4165 4166 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4167 xfer->ux_flags, 0); 4168 4169 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4170 KASSERT(xfer->ux_nframes != 0); 4171 KASSERT(exfer->ex_isdone); 4172 4173 exfer->ex_type = EX_FS_ISOC; 4174 /* 4175 * Step 1: Allocate and initialize sitds. 4176 */ 4177 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4178 if (i > 16 || i == 0) { 4179 /* Spec page 271 says intervals > 16 are invalid */ 4180 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4181 4182 return EINVAL; 4183 } 4184 4185 frames = xfer->ux_nframes; 4186 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4187 sitd = ehci_alloc_sitd(sc); 4188 if (sitd == NULL) { 4189 err = ENOMEM; 4190 goto fail; 4191 } 4192 4193 if (prev) 4194 prev->xfer_next = sitd; 4195 else 4196 start = sitd; 4197 4198 huba = dev->ud_myhsport->up_parent->ud_addr; 4199 4200 #if 0 4201 if (sc->sc_flags & EHCIF_FREESCALE) { 4202 // Set hub address to 0 if embedded TT is used. 4203 if (huba == sc->sc_addr) 4204 huba = 0; 4205 } 4206 #endif 4207 4208 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4209 dir = UE_GET_DIR(k) ? 1 : 0; 4210 sitd->sitd.sitd_endp = 4211 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4212 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4213 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4214 EHCI_SITD_SET_HUBA(huba) | 4215 EHCI_SITD_SET_DIR(dir)); 4216 4217 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4218 } /* End of frame */ 4219 4220 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4221 4222 stop = sitd; 4223 stop->xfer_next = NULL; 4224 exfer->ex_sitdstart = start; 4225 exfer->ex_sitdend = stop; 4226 4227 return 0; 4228 4229 fail: 4230 mutex_enter(&sc->sc_lock); 4231 ehci_soft_sitd_t *next; 4232 for (sitd = start; sitd; sitd = next) { 4233 next = sitd->xfer_next; 4234 ehci_free_sitd_locked(sc, sitd); 4235 } 4236 mutex_exit(&sc->sc_lock); 4237 4238 return err; 4239 } 4240 4241 Static void 4242 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4243 { 4244 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4245 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4246 4247 KASSERT(ex->ex_type == EX_FS_ISOC); 4248 4249 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4250 } 4251 4252 Static usbd_status 4253 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4254 { 4255 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4256 usbd_status __diagused err; 4257 4258 mutex_enter(&sc->sc_lock); 4259 err = usb_insert_transfer(xfer); 4260 mutex_exit(&sc->sc_lock); 4261 4262 KASSERT(err == USBD_NORMAL_COMPLETION); 4263 4264 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4265 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4266 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4267 ehci_soft_sitd_t *sitd; 4268 usb_dma_t *dma_buf; 4269 int i, j, k, frames; 4270 int offs, total_length; 4271 int frindex; 4272 u_int dir; 4273 4274 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4275 4276 sitd = NULL; 4277 total_length = 0; 4278 4279 4280 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4281 xfer->ux_flags, 0); 4282 4283 if (sc->sc_dying) 4284 return USBD_IOERROR; 4285 4286 /* 4287 * To avoid complication, don't allow a request right now that'll span 4288 * the entire frame table. To within 4 frames, to allow some leeway 4289 * on either side of where the hc currently is. 4290 */ 4291 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4292 xfer->ux_nframes >= sc->sc_flsize - 4) { 4293 printf("ehci: isoc descriptor requested that spans the entire" 4294 "frametable, too many frames\n"); 4295 return USBD_INVAL; 4296 } 4297 4298 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4299 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4300 KASSERT(exfer->ex_isdone); 4301 #ifdef DIAGNOSTIC 4302 exfer->ex_isdone = false; 4303 #endif 4304 4305 /* 4306 * Step 1: Initialize sitds. 4307 */ 4308 4309 frames = xfer->ux_nframes; 4310 dma_buf = &xfer->ux_dmabuf; 4311 offs = 0; 4312 4313 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4314 i++, sitd = sitd->xfer_next) { 4315 KASSERT(sitd != NULL); 4316 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4317 4318 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4319 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4320 4321 /* Set page0 index and offset - TP and T-offset are set below */ 4322 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4323 4324 total_length += xfer->ux_frlengths[i]; 4325 offs += xfer->ux_frlengths[i]; 4326 4327 sitd->sitd.sitd_buffer[1] = 4328 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4329 4330 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4331 4332 #if 0 4333 if (sc->sc_flags & EHCIF_FREESCALE) { 4334 // Set hub address to 0 if embedded TT is used. 4335 if (huba == sc->sc_addr) 4336 huba = 0; 4337 } 4338 #endif 4339 4340 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4341 dir = UE_GET_DIR(k) ? 1 : 0; 4342 KASSERT(sitd->sitd.sitd_endp == htole32( 4343 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4344 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4345 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4346 EHCI_SITD_SET_HUBA(huba) | 4347 EHCI_SITD_SET_DIR(dir))); 4348 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4349 4350 uint8_t sa = 0; 4351 uint8_t sb = 0; 4352 u_int temp, tlen; 4353 4354 if (dir == 0) { /* OUT */ 4355 temp = 0; 4356 tlen = xfer->ux_frlengths[i]; 4357 if (tlen <= 188) { 4358 temp |= 1; /* T-count = 1, TP = ALL */ 4359 tlen = 1; 4360 } else { 4361 tlen += 187; 4362 tlen /= 188; 4363 temp |= tlen; /* T-count = [1..6] */ 4364 temp |= 8; /* TP = Begin */ 4365 } 4366 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4367 4368 tlen += sa; 4369 4370 if (tlen >= 8) { 4371 sb = 0; 4372 } else { 4373 sb = (1 << tlen); 4374 } 4375 4376 sa = (1 << sa); 4377 sa = (sb - sa) & 0x3F; 4378 sb = 0; 4379 } else { 4380 sb = (-(4 << sa)) & 0xFE; 4381 sa = (1 << sa) & 0x3F; 4382 sa = 0x01; 4383 sb = 0xfc; 4384 } 4385 4386 sitd->sitd.sitd_sched = htole32( 4387 EHCI_SITD_SET_SMASK(sa) | 4388 EHCI_SITD_SET_CMASK(sb) 4389 ); 4390 4391 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4392 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4393 } /* End of frame */ 4394 4395 sitd = exfer->ex_sitdend; 4396 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4397 4398 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4399 sizeof(sitd->sitd.sitd_trans), 4400 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4401 4402 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4403 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4404 4405 /* 4406 * Part 2: Transfer descriptors have now been set up, now they must 4407 * be scheduled into the periodic frame list. Erk. Not wanting to 4408 * complicate matters, transfer is denied if the transfer spans 4409 * more than the period frame list. 4410 */ 4411 4412 mutex_enter(&sc->sc_lock); 4413 4414 /* Start inserting frames */ 4415 if (epipe->isoc.cur_xfers > 0) { 4416 frindex = epipe->isoc.next_frame; 4417 } else { 4418 frindex = EOREAD4(sc, EHCI_FRINDEX); 4419 frindex = frindex >> 3; /* Erase microframe index */ 4420 frindex += 2; 4421 } 4422 4423 if (frindex >= sc->sc_flsize) 4424 frindex &= (sc->sc_flsize - 1); 4425 4426 /* Whats the frame interval? */ 4427 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4428 4429 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4430 j++, sitd = sitd->xfer_next) { 4431 KASSERT(sitd); 4432 4433 usb_syncmem(&sc->sc_fldma, 4434 sizeof(ehci_link_t) * frindex, 4435 sizeof(ehci_link_t), 4436 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4437 4438 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4439 if (sitd->sitd.sitd_next == 0) 4440 /* 4441 * FIXME: frindex table gets initialized to NULL 4442 * or EHCI_NULL? 4443 */ 4444 sitd->sitd.sitd_next = EHCI_NULL; 4445 4446 usb_syncmem(&sitd->dma, 4447 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4448 sizeof(ehci_sitd_t), 4449 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4450 4451 sc->sc_flist[frindex] = 4452 htole32(EHCI_LINK_SITD | sitd->physaddr); 4453 4454 usb_syncmem(&sc->sc_fldma, 4455 sizeof(ehci_link_t) * frindex, 4456 sizeof(ehci_link_t), 4457 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4458 4459 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4460 sc->sc_softsitds[frindex] = sitd; 4461 if (sitd->frame_list.next != NULL) 4462 sitd->frame_list.next->frame_list.prev = sitd; 4463 sitd->slot = frindex; 4464 sitd->frame_list.prev = NULL; 4465 4466 frindex += i; 4467 if (frindex >= sc->sc_flsize) 4468 frindex -= sc->sc_flsize; 4469 } 4470 4471 epipe->isoc.cur_xfers++; 4472 epipe->isoc.next_frame = frindex; 4473 4474 ehci_add_intr_list(sc, exfer); 4475 xfer->ux_status = USBD_IN_PROGRESS; 4476 mutex_exit(&sc->sc_lock); 4477 4478 return USBD_IN_PROGRESS; 4479 } 4480 4481 Static void 4482 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4483 { 4484 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4485 4486 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4487 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4488 } 4489 4490 Static void 4491 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4492 { 4493 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4494 4495 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4496 } 4497 4498 Static void 4499 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4500 { 4501 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4502 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4503 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4504 4505 KASSERT(mutex_owned(&sc->sc_lock)); 4506 4507 epipe->isoc.cur_xfers--; 4508 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4509 4510 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4511 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4512 } 4513 4514 4515 /************************/ 4516 4517 4518 Static int 4519 ehci_device_isoc_init(struct usbd_xfer *xfer) 4520 { 4521 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4522 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4523 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4524 ehci_soft_itd_t *itd, *prev, *start, *stop; 4525 int i, j, k; 4526 int frames, ufrperframe; 4527 int err; 4528 4529 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4530 4531 start = NULL; 4532 prev = NULL; 4533 itd = NULL; 4534 4535 KASSERT(xfer->ux_nframes != 0); 4536 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4537 KASSERT(exfer->ex_isdone); 4538 4539 exfer->ex_type = EX_ISOC; 4540 4541 /* 4542 * Step 1: Allocate and initialize itds, how many do we need? 4543 * One per transfer if interval >= 8 microframes, less if we use 4544 * multiple microframes per frame. 4545 */ 4546 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4547 if (i > 16 || i == 0) { 4548 /* Spec page 271 says intervals > 16 are invalid */ 4549 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4550 return USBD_INVAL; 4551 } 4552 4553 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4554 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4555 4556 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4557 itd = ehci_alloc_itd(sc); 4558 if (itd == NULL) { 4559 err = ENOMEM; 4560 goto fail; 4561 } 4562 4563 if (prev != NULL) { 4564 /* Maybe not as it's updated by the scheduling? */ 4565 prev->itd.itd_next = 4566 htole32(itd->physaddr | EHCI_LINK_ITD); 4567 4568 prev->xfer_next = itd; 4569 } else { 4570 start = itd; 4571 } 4572 4573 /* 4574 * Other special values 4575 */ 4576 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4577 itd->itd.itd_bufr[0] = htole32( 4578 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4579 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4580 4581 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4582 ? 1 : 0; 4583 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4584 itd->itd.itd_bufr[1] |= htole32( 4585 EHCI_ITD_SET_DIR(k) | 4586 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4587 4588 /* FIXME: handle invalid trans - should be done in openpipe */ 4589 itd->itd.itd_bufr[2] |= 4590 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4591 } /* End of frame */ 4592 4593 stop = itd; 4594 stop->xfer_next = NULL; 4595 4596 exfer->ex_itdstart = start; 4597 exfer->ex_itdend = stop; 4598 4599 return 0; 4600 fail: 4601 mutex_enter(&sc->sc_lock); 4602 ehci_soft_itd_t *next; 4603 for (itd = start; itd; itd = next) { 4604 next = itd->xfer_next; 4605 ehci_free_itd_locked(sc, itd); 4606 } 4607 mutex_exit(&sc->sc_lock); 4608 4609 return err; 4610 4611 } 4612 4613 Static void 4614 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4615 { 4616 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4617 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4618 4619 KASSERT(ex->ex_type == EX_ISOC); 4620 4621 ehci_free_itd_chain(sc, ex->ex_itdstart); 4622 } 4623 4624 Static usbd_status 4625 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4626 { 4627 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4628 usbd_status __diagused err; 4629 4630 mutex_enter(&sc->sc_lock); 4631 err = usb_insert_transfer(xfer); 4632 mutex_exit(&sc->sc_lock); 4633 4634 KASSERT(err == USBD_NORMAL_COMPLETION); 4635 4636 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4637 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4638 ehci_soft_itd_t *itd, *prev; 4639 usb_dma_t *dma_buf; 4640 int i, j; 4641 int frames, uframes, ufrperframe; 4642 int trans_count, offs, total_length; 4643 int frindex; 4644 4645 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4646 4647 prev = NULL; 4648 itd = NULL; 4649 trans_count = 0; 4650 total_length = 0; 4651 4652 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4653 4654 if (sc->sc_dying) 4655 return USBD_IOERROR; 4656 4657 /* 4658 * To avoid complication, don't allow a request right now that'll span 4659 * the entire frame table. To within 4 frames, to allow some leeway 4660 * on either side of where the hc currently is. 4661 */ 4662 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4663 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4664 DPRINTF( 4665 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4666 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4667 return USBD_INVAL; 4668 } 4669 4670 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4671 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4672 KASSERT(exfer->ex_isdone); 4673 #ifdef DIAGNOSTIC 4674 exfer->ex_isdone = false; 4675 #endif 4676 4677 /* 4678 * Step 1: Re-Initialize itds 4679 */ 4680 4681 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4682 if (i > 16 || i == 0) { 4683 /* Spec page 271 says intervals > 16 are invalid */ 4684 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4685 return USBD_INVAL; 4686 } 4687 4688 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4689 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4690 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4691 4692 if (frames == 0) { 4693 DPRINTF("frames == 0", 0, 0, 0, 0); 4694 return USBD_INVAL; 4695 } 4696 4697 dma_buf = &xfer->ux_dmabuf; 4698 offs = 0; 4699 4700 itd = exfer->ex_itdstart; 4701 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4702 int froffs = offs; 4703 4704 if (prev != NULL) { 4705 prev->itd.itd_next = 4706 htole32(itd->physaddr | EHCI_LINK_ITD); 4707 usb_syncmem(&prev->dma, 4708 prev->offs + offsetof(ehci_itd_t, itd_next), 4709 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4710 prev->xfer_next = itd; 4711 } 4712 4713 /* 4714 * Step 1.5, initialize uframes 4715 */ 4716 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4717 /* Calculate which page in the list this starts in */ 4718 int addr = DMAADDR(dma_buf, froffs); 4719 addr = EHCI_PAGE_OFFSET(addr); 4720 addr += (offs - froffs); 4721 addr = EHCI_PAGE(addr); 4722 addr /= EHCI_PAGE_SIZE; 4723 4724 /* 4725 * This gets the initial offset into the first page, 4726 * looks how far further along the current uframe 4727 * offset is. Works out how many pages that is. 4728 */ 4729 4730 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4731 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4732 EHCI_ITD_SET_PG(addr) | 4733 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4734 4735 total_length += xfer->ux_frlengths[trans_count]; 4736 offs += xfer->ux_frlengths[trans_count]; 4737 trans_count++; 4738 4739 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4740 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4741 break; 4742 } 4743 } 4744 4745 /* 4746 * Step 1.75, set buffer pointers. To simplify matters, all 4747 * pointers are filled out for the next 7 hardware pages in 4748 * the dma block, so no need to worry what pages to cover 4749 * and what to not. 4750 */ 4751 4752 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4753 /* 4754 * Don't try to lookup a page that's past the end 4755 * of buffer 4756 */ 4757 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4758 if (page_offs >= dma_buf->udma_block->size) 4759 break; 4760 4761 uint64_t page = DMAADDR(dma_buf, page_offs); 4762 page = EHCI_PAGE(page); 4763 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4764 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4765 } 4766 /* 4767 * Other special values 4768 */ 4769 4770 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4771 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4772 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4773 4774 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4775 ? 1 : 0; 4776 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4777 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4778 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4779 4780 /* FIXME: handle invalid trans */ 4781 itd->itd.itd_bufr[2] |= 4782 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4783 4784 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4785 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4786 4787 prev = itd; 4788 } /* End of frame */ 4789 4790 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4791 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4792 4793 /* 4794 * Part 2: Transfer descriptors have now been set up, now they must 4795 * be scheduled into the period frame list. Erk. Not wanting to 4796 * complicate matters, transfer is denied if the transfer spans 4797 * more than the period frame list. 4798 */ 4799 4800 mutex_enter(&sc->sc_lock); 4801 4802 /* Start inserting frames */ 4803 if (epipe->isoc.cur_xfers > 0) { 4804 frindex = epipe->isoc.next_frame; 4805 } else { 4806 frindex = EOREAD4(sc, EHCI_FRINDEX); 4807 frindex = frindex >> 3; /* Erase microframe index */ 4808 frindex += 2; 4809 } 4810 4811 if (frindex >= sc->sc_flsize) 4812 frindex &= (sc->sc_flsize - 1); 4813 4814 /* What's the frame interval? */ 4815 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4816 if (i / USB_UFRAMES_PER_FRAME == 0) 4817 i = 1; 4818 else 4819 i /= USB_UFRAMES_PER_FRAME; 4820 4821 itd = exfer->ex_itdstart; 4822 for (j = 0; j < frames; j++) { 4823 KASSERTMSG(itd != NULL, "frame %d\n", j); 4824 4825 usb_syncmem(&sc->sc_fldma, 4826 sizeof(ehci_link_t) * frindex, 4827 sizeof(ehci_link_t), 4828 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4829 4830 itd->itd.itd_next = sc->sc_flist[frindex]; 4831 if (itd->itd.itd_next == 0) 4832 /* 4833 * FIXME: frindex table gets initialized to NULL 4834 * or EHCI_NULL? 4835 */ 4836 itd->itd.itd_next = EHCI_NULL; 4837 4838 usb_syncmem(&itd->dma, 4839 itd->offs + offsetof(ehci_itd_t, itd_next), 4840 sizeof(itd->itd.itd_next), 4841 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4842 4843 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4844 4845 usb_syncmem(&sc->sc_fldma, 4846 sizeof(ehci_link_t) * frindex, 4847 sizeof(ehci_link_t), 4848 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4849 4850 itd->frame_list.next = sc->sc_softitds[frindex]; 4851 sc->sc_softitds[frindex] = itd; 4852 if (itd->frame_list.next != NULL) 4853 itd->frame_list.next->frame_list.prev = itd; 4854 itd->slot = frindex; 4855 itd->frame_list.prev = NULL; 4856 4857 frindex += i; 4858 if (frindex >= sc->sc_flsize) 4859 frindex -= sc->sc_flsize; 4860 4861 itd = itd->xfer_next; 4862 } 4863 4864 epipe->isoc.cur_xfers++; 4865 epipe->isoc.next_frame = frindex; 4866 4867 ehci_add_intr_list(sc, exfer); 4868 xfer->ux_status = USBD_IN_PROGRESS; 4869 mutex_exit(&sc->sc_lock); 4870 4871 return USBD_IN_PROGRESS; 4872 } 4873 4874 Static void 4875 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4876 { 4877 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4878 4879 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4880 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4881 } 4882 4883 Static void 4884 ehci_device_isoc_close(struct usbd_pipe *pipe) 4885 { 4886 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4887 4888 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4889 } 4890 4891 Static void 4892 ehci_device_isoc_done(struct usbd_xfer *xfer) 4893 { 4894 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4895 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4896 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4897 4898 KASSERT(mutex_owned(&sc->sc_lock)); 4899 4900 epipe->isoc.cur_xfers--; 4901 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4902 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4903 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4904 } 4905
Indexes created Tue Sep 23 23:09:58 GMT 2025