ehci.c revision 1.270
1 /* $NetBSD: ehci.c,v 1.270 2020/02/12 16:00:34 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.270 2020/02/12 16:00:34 riastradh Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 #include <sys/reboot.h> 79 80 #include <machine/endian.h> 81 82 #include <dev/usb/usb.h> 83 #include <dev/usb/usbdi.h> 84 #include <dev/usb/usbdivar.h> 85 #include <dev/usb/usbhist.h> 86 #include <dev/usb/usb_mem.h> 87 #include <dev/usb/usb_quirks.h> 88 89 #include <dev/usb/ehcireg.h> 90 #include <dev/usb/ehcivar.h> 91 #include <dev/usb/usbroothub.h> 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static bool ehci_probe_timeout(struct usbd_xfer *); 172 Static void ehci_schedule_timeout(struct usbd_xfer *); 173 Static void ehci_cancel_timeout_async(struct usbd_xfer *); 174 Static void ehci_intrlist_timeout(void *); 175 Static void ehci_doorbell(void *); 176 Static void ehci_pcd(void *); 177 178 Static struct usbd_xfer * 179 ehci_allocx(struct usbd_bus *, unsigned int); 180 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 181 182 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 183 Static int ehci_roothub_ctrl(struct usbd_bus *, 184 usb_device_request_t *, void *, int); 185 186 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 187 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 188 Static void ehci_root_intr_abort(struct usbd_xfer *); 189 Static void ehci_root_intr_close(struct usbd_pipe *); 190 Static void ehci_root_intr_done(struct usbd_xfer *); 191 192 Static int ehci_device_ctrl_init(struct usbd_xfer *); 193 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 194 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 195 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 196 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 197 Static void ehci_device_ctrl_close(struct usbd_pipe *); 198 Static void ehci_device_ctrl_done(struct usbd_xfer *); 199 200 Static int ehci_device_bulk_init(struct usbd_xfer *); 201 Static void ehci_device_bulk_fini(struct usbd_xfer *); 202 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 203 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 204 Static void ehci_device_bulk_abort(struct usbd_xfer *); 205 Static void ehci_device_bulk_close(struct usbd_pipe *); 206 Static void ehci_device_bulk_done(struct usbd_xfer *); 207 208 Static int ehci_device_intr_init(struct usbd_xfer *); 209 Static void ehci_device_intr_fini(struct usbd_xfer *); 210 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 211 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 212 Static void ehci_device_intr_abort(struct usbd_xfer *); 213 Static void ehci_device_intr_close(struct usbd_pipe *); 214 Static void ehci_device_intr_done(struct usbd_xfer *); 215 216 Static int ehci_device_isoc_init(struct usbd_xfer *); 217 Static void ehci_device_isoc_fini(struct usbd_xfer *); 218 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 219 Static void ehci_device_isoc_abort(struct usbd_xfer *); 220 Static void ehci_device_isoc_close(struct usbd_pipe *); 221 Static void ehci_device_isoc_done(struct usbd_xfer *); 222 223 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 225 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 226 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 227 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 228 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 229 230 Static void ehci_device_clear_toggle(struct usbd_pipe *); 231 Static void ehci_noop(struct usbd_pipe *); 232 233 Static void ehci_disown(ehci_softc_t *, int, int); 234 235 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 236 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 237 238 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 239 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 240 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 241 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 242 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 243 244 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 245 int, int, int *, ehci_soft_qtd_t **); 246 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 247 248 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 249 Static ehci_soft_sitd_t * 250 ehci_alloc_sitd(ehci_softc_t *); 251 252 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 253 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 254 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 255 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 256 257 static inline void 258 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 259 { 260 261 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 262 } 263 264 static inline void 265 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 266 { 267 268 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 269 } 270 271 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 272 273 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 274 int); 275 276 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 277 ehci_soft_qh_t *); 278 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 279 ehci_soft_qh_t *); 280 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 281 Static void ehci_sync_hc(ehci_softc_t *); 282 283 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 284 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 285 286 #ifdef EHCI_DEBUG 287 Static ehci_softc_t *theehci; 288 void ehci_dump(void); 289 #endif 290 291 #ifdef EHCI_DEBUG 292 Static void ehci_dump_regs(ehci_softc_t *); 293 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 294 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 295 Static void ehci_dump_qtd(ehci_qtd_t *); 296 Static void ehci_dump_sqh(ehci_soft_qh_t *); 297 Static void ehci_dump_sitd(struct ehci_soft_itd *); 298 Static void ehci_dump_itds(ehci_soft_itd_t *); 299 Static void ehci_dump_itd(struct ehci_soft_itd *); 300 Static void ehci_dump_exfer(struct ehci_xfer *); 301 #endif 302 303 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 304 305 static inline void 306 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 307 { 308 309 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 310 } 311 312 static inline void 313 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 314 { 315 316 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 317 } 318 319 Static const struct usbd_bus_methods ehci_bus_methods = { 320 .ubm_open = ehci_open, 321 .ubm_softint = ehci_softintr, 322 .ubm_dopoll = ehci_poll, 323 .ubm_allocx = ehci_allocx, 324 .ubm_freex = ehci_freex, 325 .ubm_getlock = ehci_get_lock, 326 .ubm_rhctrl = ehci_roothub_ctrl, 327 }; 328 329 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 330 .upm_transfer = ehci_root_intr_transfer, 331 .upm_start = ehci_root_intr_start, 332 .upm_abort = ehci_root_intr_abort, 333 .upm_close = ehci_root_intr_close, 334 .upm_cleartoggle = ehci_noop, 335 .upm_done = ehci_root_intr_done, 336 }; 337 338 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 339 .upm_init = ehci_device_ctrl_init, 340 .upm_fini = ehci_device_ctrl_fini, 341 .upm_transfer = ehci_device_ctrl_transfer, 342 .upm_start = ehci_device_ctrl_start, 343 .upm_abort = ehci_device_ctrl_abort, 344 .upm_close = ehci_device_ctrl_close, 345 .upm_cleartoggle = ehci_noop, 346 .upm_done = ehci_device_ctrl_done, 347 }; 348 349 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 350 .upm_init = ehci_device_intr_init, 351 .upm_fini = ehci_device_intr_fini, 352 .upm_transfer = ehci_device_intr_transfer, 353 .upm_start = ehci_device_intr_start, 354 .upm_abort = ehci_device_intr_abort, 355 .upm_close = ehci_device_intr_close, 356 .upm_cleartoggle = ehci_device_clear_toggle, 357 .upm_done = ehci_device_intr_done, 358 }; 359 360 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 361 .upm_init = ehci_device_bulk_init, 362 .upm_fini = ehci_device_bulk_fini, 363 .upm_transfer = ehci_device_bulk_transfer, 364 .upm_start = ehci_device_bulk_start, 365 .upm_abort = ehci_device_bulk_abort, 366 .upm_close = ehci_device_bulk_close, 367 .upm_cleartoggle = ehci_device_clear_toggle, 368 .upm_done = ehci_device_bulk_done, 369 }; 370 371 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 372 .upm_init = ehci_device_isoc_init, 373 .upm_fini = ehci_device_isoc_fini, 374 .upm_transfer = ehci_device_isoc_transfer, 375 .upm_abort = ehci_device_isoc_abort, 376 .upm_close = ehci_device_isoc_close, 377 .upm_cleartoggle = ehci_noop, 378 .upm_done = ehci_device_isoc_done, 379 }; 380 381 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 382 .upm_init = ehci_device_fs_isoc_init, 383 .upm_fini = ehci_device_fs_isoc_fini, 384 .upm_transfer = ehci_device_fs_isoc_transfer, 385 .upm_abort = ehci_device_fs_isoc_abort, 386 .upm_close = ehci_device_fs_isoc_close, 387 .upm_cleartoggle = ehci_noop, 388 .upm_done = ehci_device_fs_isoc_done, 389 }; 390 391 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 392 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 393 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 394 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 395 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 396 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 397 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 398 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 399 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 400 }; 401 402 int 403 ehci_init(ehci_softc_t *sc) 404 { 405 uint32_t vers, sparams, cparams, hcr; 406 u_int i; 407 usbd_status err; 408 ehci_soft_qh_t *sqh; 409 u_int ncomp; 410 411 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 412 #ifdef EHCI_DEBUG 413 theehci = sc; 414 #endif 415 416 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 417 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 418 cv_init(&sc->sc_doorbell, "ehcidb"); 419 420 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 421 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 422 423 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 424 ehci_doorbell, sc); 425 KASSERT(sc->sc_doorbell_si != NULL); 426 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 427 ehci_pcd, sc); 428 KASSERT(sc->sc_pcd_si != NULL); 429 430 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 431 432 vers = EREAD2(sc, EHCI_HCIVERSION); 433 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 434 vers >> 8, vers & 0xff); 435 436 sparams = EREAD4(sc, EHCI_HCSPARAMS); 437 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 438 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 439 ncomp = EHCI_HCS_N_CC(sparams); 440 if (ncomp != sc->sc_ncomp) { 441 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 442 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 443 #if NOHCI == 0 || NUHCI == 0 444 aprint_error("%s: ohci or uhci probably not configured\n", 445 device_xname(sc->sc_dev)); 446 #endif 447 if (ncomp < sc->sc_ncomp) 448 sc->sc_ncomp = ncomp; 449 } 450 if (sc->sc_ncomp > 0) { 451 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 452 aprint_normal_dev(sc->sc_dev, 453 "%d companion controller%s, %d port%s%s", 454 sc->sc_ncomp, 455 sc->sc_ncomp!=1 ? "s" : "", 456 EHCI_HCS_N_PCC(sparams), 457 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 458 sc->sc_ncomp!=1 ? " each" : ""); 459 if (sc->sc_comps[0]) { 460 aprint_normal(":"); 461 for (i = 0; i < sc->sc_ncomp; i++) 462 aprint_normal(" %s", 463 device_xname(sc->sc_comps[i])); 464 } 465 aprint_normal("\n"); 466 467 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 468 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 469 cv_init(&sc->sc_compcv, "ehciccv"); 470 sc->sc_comp_state = CO_EARLY; 471 } 472 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 473 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 474 475 cparams = EREAD4(sc, EHCI_HCCPARAMS); 476 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 477 478 if (EHCI_HCC_64BIT(cparams)) { 479 /* MUST clear segment register if 64 bit capable. */ 480 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 481 } 482 483 if (cparams & EHCI_HCC_IST_FULLFRAME) { 484 sc->sc_istthreshold = 0; 485 } else { 486 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 487 } 488 489 sc->sc_bus.ub_revision = USBREV_2_0; 490 sc->sc_bus.ub_usedma = true; 491 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 492 493 /* Reset the controller */ 494 DPRINTF("resetting", 0, 0, 0, 0); 495 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 496 usb_delay_ms(&sc->sc_bus, 1); 497 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 498 for (i = 0; i < 100; i++) { 499 usb_delay_ms(&sc->sc_bus, 1); 500 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 501 if (!hcr) 502 break; 503 } 504 if (hcr) { 505 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 506 return EIO; 507 } 508 if (sc->sc_vendor_init) 509 sc->sc_vendor_init(sc); 510 511 /* XXX need proper intr scheduling */ 512 sc->sc_rand = 96; 513 514 /* frame list size at default, read back what we got and use that */ 515 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 516 case 0: sc->sc_flsize = 1024; break; 517 case 1: sc->sc_flsize = 512; break; 518 case 2: sc->sc_flsize = 256; break; 519 case 3: return EIO; 520 } 521 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 522 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 523 if (err) 524 return err; 525 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 526 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 527 528 for (i = 0; i < sc->sc_flsize; i++) { 529 sc->sc_flist[i] = EHCI_NULL; 530 } 531 532 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 533 534 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 535 KM_SLEEP); 536 LIST_INIT(&sc->sc_freeitds); 537 LIST_INIT(&sc->sc_freesitds); 538 TAILQ_INIT(&sc->sc_intrhead); 539 540 /* Set up the bus struct. */ 541 sc->sc_bus.ub_methods = &ehci_bus_methods; 542 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 543 544 sc->sc_eintrs = EHCI_NORMAL_INTRS; 545 546 /* 547 * Allocate the interrupt dummy QHs. These are arranged to give poll 548 * intervals that are powers of 2 times 1ms. 549 */ 550 for (i = 0; i < EHCI_INTRQHS; i++) { 551 sqh = ehci_alloc_sqh(sc); 552 if (sqh == NULL) { 553 err = ENOMEM; 554 goto bad1; 555 } 556 sc->sc_islots[i].sqh = sqh; 557 } 558 for (i = 0; i < EHCI_INTRQHS; i++) { 559 sqh = sc->sc_islots[i].sqh; 560 if (i == 0) { 561 /* The last (1ms) QH terminates. */ 562 sqh->qh.qh_link = EHCI_NULL; 563 sqh->next = NULL; 564 } else { 565 /* Otherwise the next QH has half the poll interval */ 566 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 567 sqh->qh.qh_link = htole32(sqh->next->physaddr | 568 EHCI_LINK_QH); 569 } 570 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 571 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 572 sqh->qh.qh_curqtd = EHCI_NULL; 573 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 574 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 575 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 576 sqh->sqtd = NULL; 577 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 578 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 579 } 580 /* Point the frame list at the last level (128ms). */ 581 for (i = 0; i < sc->sc_flsize; i++) { 582 int j; 583 584 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 585 revbits[i & (EHCI_MAX_POLLRATE-1)]; 586 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 587 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 588 i)].sqh->physaddr); 589 } 590 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 591 BUS_DMASYNC_PREWRITE); 592 593 /* Allocate dummy QH that starts the async list. */ 594 sqh = ehci_alloc_sqh(sc); 595 if (sqh == NULL) { 596 err = ENOMEM; 597 goto bad1; 598 } 599 /* Fill the QH */ 600 sqh->qh.qh_endp = 601 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 602 sqh->qh.qh_link = 603 htole32(sqh->physaddr | EHCI_LINK_QH); 604 sqh->qh.qh_curqtd = EHCI_NULL; 605 sqh->next = NULL; 606 /* Fill the overlay qTD */ 607 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 608 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 609 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 610 sqh->sqtd = NULL; 611 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 612 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 613 #ifdef EHCI_DEBUG 614 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 615 ehci_dump_sqh(sqh); 616 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 617 #endif 618 619 /* Point to async list */ 620 sc->sc_async_head = sqh; 621 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 622 623 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 624 625 /* Turn on controller */ 626 EOWRITE4(sc, EHCI_USBCMD, 627 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 628 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 629 EHCI_CMD_ASE | 630 EHCI_CMD_PSE | 631 EHCI_CMD_RS); 632 633 /* Take over port ownership */ 634 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 635 636 for (i = 0; i < 100; i++) { 637 usb_delay_ms(&sc->sc_bus, 1); 638 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 639 if (!hcr) 640 break; 641 } 642 if (hcr) { 643 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 644 return EIO; 645 } 646 647 /* Enable interrupts */ 648 DPRINTF("enabling interrupts", 0, 0, 0, 0); 649 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 650 651 return 0; 652 653 #if 0 654 bad2: 655 ehci_free_sqh(sc, sc->sc_async_head); 656 #endif 657 bad1: 658 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 659 return err; 660 } 661 662 int 663 ehci_intr(void *v) 664 { 665 ehci_softc_t *sc = v; 666 int ret = 0; 667 668 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 669 670 if (sc == NULL) 671 return 0; 672 673 mutex_spin_enter(&sc->sc_intr_lock); 674 675 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 676 goto done; 677 678 /* If we get an interrupt while polling, then just ignore it. */ 679 if (sc->sc_bus.ub_usepolling) { 680 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 681 682 if (intrs) 683 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 684 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 685 goto done; 686 } 687 688 ret = ehci_intr1(sc); 689 690 done: 691 mutex_spin_exit(&sc->sc_intr_lock); 692 return ret; 693 } 694 695 Static int 696 ehci_intr1(ehci_softc_t *sc) 697 { 698 uint32_t intrs, eintrs; 699 700 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 701 702 /* In case the interrupt occurs before initialization has completed. */ 703 if (sc == NULL) { 704 #ifdef DIAGNOSTIC 705 printf("ehci_intr1: sc == NULL\n"); 706 #endif 707 return 0; 708 } 709 710 KASSERT(mutex_owned(&sc->sc_intr_lock)); 711 712 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 713 if (!intrs) 714 return 0; 715 716 eintrs = intrs & sc->sc_eintrs; 717 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 718 EOREAD4(sc, EHCI_USBSTS), eintrs); 719 if (!eintrs) 720 return 0; 721 722 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 723 if (eintrs & EHCI_STS_IAA) { 724 DPRINTF("door bell", 0, 0, 0, 0); 725 kpreempt_disable(); 726 KASSERT(sc->sc_doorbell_si != NULL); 727 softint_schedule(sc->sc_doorbell_si); 728 kpreempt_enable(); 729 eintrs &= ~EHCI_STS_IAA; 730 } 731 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 732 DPRINTF("INT=%jd ERRINT=%jd", 733 eintrs & EHCI_STS_INT ? 1 : 0, 734 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 735 usb_schedsoftintr(&sc->sc_bus); 736 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 737 } 738 if (eintrs & EHCI_STS_HSE) { 739 printf("%s: unrecoverable error, controller halted\n", 740 device_xname(sc->sc_dev)); 741 /* XXX what else */ 742 } 743 if (eintrs & EHCI_STS_PCD) { 744 kpreempt_disable(); 745 KASSERT(sc->sc_pcd_si != NULL); 746 softint_schedule(sc->sc_pcd_si); 747 kpreempt_enable(); 748 eintrs &= ~EHCI_STS_PCD; 749 } 750 751 if (eintrs != 0) { 752 /* Block unprocessed interrupts. */ 753 sc->sc_eintrs &= ~eintrs; 754 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 755 printf("%s: blocking intrs 0x%x\n", 756 device_xname(sc->sc_dev), eintrs); 757 } 758 759 return 1; 760 } 761 762 Static void 763 ehci_doorbell(void *addr) 764 { 765 ehci_softc_t *sc = addr; 766 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 cv_broadcast(&sc->sc_doorbell); 770 mutex_exit(&sc->sc_lock); 771 } 772 773 Static void 774 ehci_pcd(void *addr) 775 { 776 ehci_softc_t *sc = addr; 777 struct usbd_xfer *xfer; 778 u_char *p; 779 int i, m; 780 781 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 782 783 mutex_enter(&sc->sc_lock); 784 xfer = sc->sc_intrxfer; 785 786 if (xfer == NULL) { 787 /* Just ignore the change. */ 788 goto done; 789 } 790 791 p = xfer->ux_buf; 792 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 793 memset(p, 0, xfer->ux_length); 794 for (i = 1; i <= m; i++) { 795 /* Pick out CHANGE bits from the status reg. */ 796 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 797 p[i/8] |= 1 << (i%8); 798 if (i % 8 == 7) 799 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 800 } 801 xfer->ux_actlen = xfer->ux_length; 802 xfer->ux_status = USBD_NORMAL_COMPLETION; 803 804 usb_transfer_complete(xfer); 805 806 done: 807 mutex_exit(&sc->sc_lock); 808 } 809 810 Static void 811 ehci_softintr(void *v) 812 { 813 struct usbd_bus *bus = v; 814 ehci_softc_t *sc = EHCI_BUS2SC(bus); 815 struct ehci_xfer *ex, *nextex; 816 817 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 818 819 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 820 821 ex_completeq_t cq; 822 TAILQ_INIT(&cq); 823 824 /* 825 * The only explanation I can think of for why EHCI is as brain dead 826 * as UHCI interrupt-wise is that Intel was involved in both. 827 * An interrupt just tells us that something is done, we have no 828 * clue what, so we need to scan through all active transfers. :-( 829 */ 830 831 /* 832 * ehci_idone will remove transfer from sc->sc_intrhead if it's 833 * complete and add to our cq list 834 * 835 */ 836 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 837 switch (ex->ex_type) { 838 case EX_CTRL: 839 case EX_BULK: 840 case EX_INTR: 841 ehci_check_qh_intr(sc, ex, &cq); 842 break; 843 case EX_ISOC: 844 ehci_check_itd_intr(sc, ex, &cq); 845 break; 846 case EX_FS_ISOC: 847 ehci_check_sitd_intr(sc, ex, &cq); 848 break; 849 default: 850 KASSERT(false); 851 } 852 853 } 854 855 /* 856 * We abuse ex_next for the interrupt and complete lists and 857 * interrupt transfers will get re-added here so use 858 * the _SAFE version of TAILQ_FOREACH. 859 */ 860 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 861 usb_transfer_complete(&ex->ex_xfer); 862 } 863 864 /* Schedule a callout to catch any dropped transactions. */ 865 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 866 !TAILQ_EMPTY(&sc->sc_intrhead)) 867 callout_reset(&sc->sc_tmo_intrlist, 868 hz, ehci_intrlist_timeout, sc); 869 } 870 871 Static void 872 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 873 { 874 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 875 uint32_t status; 876 877 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 878 879 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 880 881 if (ex->ex_type == EX_CTRL) { 882 fsqtd = ex->ex_setup; 883 lsqtd = ex->ex_status; 884 } else { 885 fsqtd = ex->ex_sqtdstart; 886 lsqtd = ex->ex_sqtdend; 887 } 888 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 889 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 890 891 /* 892 * If the last TD is still active we need to check whether there 893 * is an error somewhere in the middle, or whether there was a 894 * short packet (SPD and not ACTIVE). 895 */ 896 usb_syncmem(&lsqtd->dma, 897 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 898 sizeof(lsqtd->qtd.qtd_status), 899 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 900 status = le32toh(lsqtd->qtd.qtd_status); 901 usb_syncmem(&lsqtd->dma, 902 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 903 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 904 if (status & EHCI_QTD_ACTIVE) { 905 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 906 907 /* last qTD has already been checked */ 908 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 909 usb_syncmem(&sqtd->dma, 910 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 911 sizeof(sqtd->qtd.qtd_status), 912 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 913 status = le32toh(sqtd->qtd.qtd_status); 914 usb_syncmem(&sqtd->dma, 915 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 916 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 917 /* If there's an active QTD the xfer isn't done. */ 918 if (status & EHCI_QTD_ACTIVE) 919 break; 920 /* Any kind of error makes the xfer done. */ 921 if (status & EHCI_QTD_HALTED) 922 goto done; 923 /* Handle short packets */ 924 if (EHCI_QTD_GET_BYTES(status) != 0) { 925 /* 926 * If we get here for a control transfer then 927 * we need to let the hardware complete the 928 * status phase. That is, we're not done 929 * quite yet. 930 * 931 * Otherwise, we're done. 932 */ 933 if (ex->ex_type == EX_CTRL) { 934 break; 935 } 936 goto done; 937 } 938 } 939 DPRINTFN(10, "ex=%#jx std=%#jx still active", 940 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 941 #ifdef EHCI_DEBUG 942 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 943 ehci_dump_sqtds(ex->ex_sqtdstart); 944 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 945 #endif 946 return; 947 } 948 done: 949 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 950 ehci_idone(ex, cq); 951 } 952 953 Static void 954 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 955 { 956 ehci_soft_itd_t *itd; 957 int i; 958 959 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 960 961 KASSERT(mutex_owned(&sc->sc_lock)); 962 963 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 964 return; 965 966 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 967 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 968 969 itd = ex->ex_itdend; 970 971 /* 972 * check no active transfers in last itd, meaning we're finished 973 */ 974 975 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 976 sizeof(itd->itd.itd_ctl), 977 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 978 979 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 980 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 981 break; 982 } 983 984 if (i == EHCI_ITD_NUFRAMES) { 985 goto done; /* All 8 descriptors inactive, it's done */ 986 } 987 988 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 989 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 990 991 DPRINTFN(10, "ex %#jx itd %#jx still active", 992 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 993 return; 994 done: 995 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 996 ehci_idone(ex, cq); 997 } 998 999 void 1000 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1001 { 1002 ehci_soft_sitd_t *sitd; 1003 1004 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1005 1006 KASSERT(mutex_owned(&sc->sc_lock)); 1007 1008 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1009 return; 1010 1011 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1012 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1013 1014 sitd = ex->ex_sitdend; 1015 1016 /* 1017 * check no active transfers in last sitd, meaning we're finished 1018 */ 1019 1020 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1021 sizeof(sitd->sitd.sitd_trans), 1022 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1023 1024 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1025 1026 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1027 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1028 1029 if (active) 1030 return; 1031 1032 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1033 ehci_idone(ex, cq); 1034 } 1035 1036 Static void 1037 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1038 { 1039 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1040 struct usbd_xfer *xfer = &ex->ex_xfer; 1041 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1042 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1043 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1044 uint32_t status = 0, nstatus = 0; 1045 int actlen = 0; 1046 1047 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1048 1049 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1050 1051 /* 1052 * If software has completed it, either by cancellation 1053 * or timeout, drop it on the floor. 1054 */ 1055 if (xfer->ux_status != USBD_IN_PROGRESS) { 1056 KASSERT(xfer->ux_status == USBD_CANCELLED || 1057 xfer->ux_status == USBD_TIMEOUT); 1058 DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1059 return; 1060 } 1061 1062 /* 1063 * We are completing the xfer. Cancel the timeout if we can, 1064 * but only asynchronously. See ehci_cancel_timeout_async for 1065 * why we need not wait for the callout or task here. 1066 */ 1067 ehci_cancel_timeout_async(xfer); 1068 1069 #ifdef DIAGNOSTIC 1070 #ifdef EHCI_DEBUG 1071 if (ex->ex_isdone) { 1072 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1073 ehci_dump_exfer(ex); 1074 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1075 } 1076 #endif 1077 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1078 ex->ex_type, xfer->ux_status); 1079 ex->ex_isdone = true; 1080 #endif 1081 1082 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1083 (uintptr_t)epipe, 0, 0); 1084 1085 /* The transfer is done, compute actual length and status. */ 1086 if (ex->ex_type == EX_ISOC) { 1087 /* HS isoc transfer */ 1088 1089 struct ehci_soft_itd *itd; 1090 int i, nframes, len, uframes; 1091 1092 nframes = 0; 1093 1094 #ifdef EHCI_DEBUG 1095 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1096 ehci_dump_itds(ex->ex_itdstart); 1097 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1098 #endif 1099 1100 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1101 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1102 1103 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1104 usb_syncmem(&itd->dma, 1105 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1106 sizeof(itd->itd.itd_ctl), 1107 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1108 1109 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1110 /* 1111 * XXX - driver didn't fill in the frame full 1112 * of uframes. This leads to scheduling 1113 * inefficiencies, but working around 1114 * this doubles complexity of tracking 1115 * an xfer. 1116 */ 1117 if (nframes >= xfer->ux_nframes) 1118 break; 1119 1120 status = le32toh(itd->itd.itd_ctl[i]); 1121 len = EHCI_ITD_GET_LEN(status); 1122 if (EHCI_ITD_GET_STATUS(status) != 0) 1123 len = 0; /*No valid data on error*/ 1124 1125 xfer->ux_frlengths[nframes++] = len; 1126 actlen += len; 1127 } 1128 usb_syncmem(&itd->dma, 1129 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1130 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1131 1132 if (nframes >= xfer->ux_nframes) 1133 break; 1134 } 1135 1136 xfer->ux_actlen = actlen; 1137 xfer->ux_status = USBD_NORMAL_COMPLETION; 1138 goto end; 1139 } else if (ex->ex_type == EX_FS_ISOC) { 1140 /* FS isoc transfer */ 1141 struct ehci_soft_sitd *sitd; 1142 int nframes, len; 1143 1144 nframes = 0; 1145 1146 for (sitd = ex->ex_sitdstart; sitd != NULL; 1147 sitd = sitd->xfer_next) { 1148 usb_syncmem(&sitd->dma, 1149 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1150 sizeof(sitd->sitd.sitd_trans), 1151 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1152 1153 /* 1154 * XXX - driver didn't fill in the frame full 1155 * of uframes. This leads to scheduling 1156 * inefficiencies, but working around 1157 * this doubles complexity of tracking 1158 * an xfer. 1159 */ 1160 if (nframes >= xfer->ux_nframes) 1161 break; 1162 1163 status = le32toh(sitd->sitd.sitd_trans); 1164 usb_syncmem(&sitd->dma, 1165 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1166 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1167 1168 len = EHCI_SITD_GET_LEN(status); 1169 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1170 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1171 /* No valid data on error */ 1172 len = xfer->ux_frlengths[nframes]; 1173 } 1174 1175 /* 1176 * frlengths[i]: # of bytes to send 1177 * len: # of bytes host didn't send 1178 */ 1179 xfer->ux_frlengths[nframes] -= len; 1180 /* frlengths[i]: # of bytes host sent */ 1181 actlen += xfer->ux_frlengths[nframes++]; 1182 1183 if (nframes >= xfer->ux_nframes) 1184 break; 1185 } 1186 1187 xfer->ux_actlen = actlen; 1188 xfer->ux_status = USBD_NORMAL_COMPLETION; 1189 goto end; 1190 } 1191 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1192 ex->ex_type == EX_BULK); 1193 1194 /* Continue processing xfers using queue heads */ 1195 if (ex->ex_type == EX_CTRL) { 1196 fsqtd = ex->ex_setup; 1197 lsqtd = ex->ex_status; 1198 } else { 1199 fsqtd = ex->ex_sqtdstart; 1200 lsqtd = ex->ex_sqtdend; 1201 } 1202 #ifdef EHCI_DEBUG 1203 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1204 ehci_dump_sqtds(fsqtd); 1205 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1206 #endif 1207 1208 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1209 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1210 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1211 nstatus = le32toh(sqtd->qtd.qtd_status); 1212 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1213 BUS_DMASYNC_PREREAD); 1214 if (nstatus & EHCI_QTD_ACTIVE) 1215 break; 1216 1217 status = nstatus; 1218 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1219 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1220 } 1221 1222 /* 1223 * If there are left over TDs we need to update the toggle. 1224 * The default pipe doesn't need it since control transfers 1225 * start the toggle at 0 every time. 1226 * For a short transfer we need to update the toggle for the missing 1227 * packets within the qTD. 1228 */ 1229 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1230 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1231 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1232 status, nstatus, 0, 0); 1233 #if 0 1234 ehci_dump_sqh(epipe->sqh); 1235 ehci_dump_sqtds(ex->ex_sqtdstart); 1236 #endif 1237 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1238 } 1239 1240 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1241 status, 0); 1242 xfer->ux_actlen = actlen; 1243 if (status & EHCI_QTD_HALTED) { 1244 #ifdef EHCI_DEBUG 1245 DPRINTF("halted addr=%jd endpt=0x%02jx", 1246 xfer->ux_pipe->up_dev->ud_addr, 1247 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1248 0, 0); 1249 DPRINTF("cerr=%jd pid=%jd", 1250 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1251 0, 0); 1252 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1253 status & EHCI_QTD_ACTIVE ? 1 : 0, 1254 status & EHCI_QTD_HALTED ? 1 : 0, 1255 status & EHCI_QTD_BUFERR ? 1 : 0, 1256 status & EHCI_QTD_BABBLE ? 1 : 0); 1257 1258 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1259 status & EHCI_QTD_XACTERR ? 1 : 0, 1260 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1261 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1262 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1263 1264 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1265 ehci_dump_sqh(epipe->sqh); 1266 ehci_dump_sqtds(ex->ex_sqtdstart); 1267 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1268 #endif 1269 /* low&full speed has an extra error flag */ 1270 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1271 EHCI_QH_SPEED_HIGH) 1272 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1273 else 1274 status &= EHCI_QTD_STATERRS; 1275 if (status == 0) /* no other errors means a stall */ { 1276 xfer->ux_status = USBD_STALLED; 1277 } else { 1278 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1279 } 1280 /* XXX need to reset TT on missed microframe */ 1281 if (status & EHCI_QTD_MISSEDMICRO) { 1282 printf("%s: missed microframe, TT reset not " 1283 "implemented, hub might be inoperational\n", 1284 device_xname(sc->sc_dev)); 1285 } 1286 } else { 1287 xfer->ux_status = USBD_NORMAL_COMPLETION; 1288 } 1289 1290 end: 1291 1292 ehci_del_intr_list(sc, ex); 1293 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1294 1295 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1296 } 1297 1298 Static void 1299 ehci_poll(struct usbd_bus *bus) 1300 { 1301 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1302 1303 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1304 1305 #ifdef EHCI_DEBUG 1306 static int last; 1307 int new; 1308 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1309 if (new != last) { 1310 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1311 last = new; 1312 } 1313 #endif 1314 1315 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1316 mutex_spin_enter(&sc->sc_intr_lock); 1317 ehci_intr1(sc); 1318 mutex_spin_exit(&sc->sc_intr_lock); 1319 } 1320 } 1321 1322 void 1323 ehci_childdet(device_t self, device_t child) 1324 { 1325 struct ehci_softc *sc = device_private(self); 1326 1327 KASSERT(sc->sc_child == child); 1328 sc->sc_child = NULL; 1329 } 1330 1331 int 1332 ehci_detach(struct ehci_softc *sc, int flags) 1333 { 1334 int rv = 0; 1335 1336 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1337 1338 if (sc->sc_child != NULL) { 1339 rv = config_detach(sc->sc_child, flags); 1340 if (rv != 0) 1341 return rv; 1342 } 1343 1344 if (sc->sc_ncomp > 0) { 1345 mutex_enter(&sc->sc_complock); 1346 /* XXX try to halt callout instead of waiting */ 1347 while (sc->sc_comp_state == CO_SCHED) 1348 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1349 mutex_exit(&sc->sc_complock); 1350 1351 callout_halt(&sc->sc_compcallout, NULL); 1352 callout_destroy(&sc->sc_compcallout); 1353 cv_destroy(&sc->sc_compcv); 1354 mutex_destroy(&sc->sc_complock); 1355 } 1356 1357 callout_halt(&sc->sc_tmo_intrlist, NULL); 1358 callout_destroy(&sc->sc_tmo_intrlist); 1359 1360 /* XXX free other data structures */ 1361 if (sc->sc_softitds) { 1362 kmem_free(sc->sc_softitds, 1363 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1364 } 1365 cv_destroy(&sc->sc_doorbell); 1366 1367 #if 0 1368 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1369 softint_disestablish(sc->sc_doorbell_si); 1370 softint_disestablish(sc->sc_pcd_si); 1371 mutex_destroy(&sc->sc_lock); 1372 mutex_destroy(&sc->sc_intr_lock); 1373 #endif 1374 1375 pool_cache_destroy(sc->sc_xferpool); 1376 1377 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1378 1379 return rv; 1380 } 1381 1382 int 1383 ehci_activate(device_t self, enum devact act) 1384 { 1385 struct ehci_softc *sc = device_private(self); 1386 1387 switch (act) { 1388 case DVACT_DEACTIVATE: 1389 sc->sc_dying = 1; 1390 return 0; 1391 default: 1392 return EOPNOTSUPP; 1393 } 1394 } 1395 1396 /* 1397 * Handle suspend/resume. 1398 * 1399 * We need to switch to polling mode here, because this routine is 1400 * called from an interrupt context. This is all right since we 1401 * are almost suspended anyway. 1402 * 1403 * Note that this power handler isn't to be registered directly; the 1404 * bus glue needs to call out to it. 1405 */ 1406 bool 1407 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1408 { 1409 ehci_softc_t *sc = device_private(dv); 1410 int i; 1411 uint32_t cmd, hcr; 1412 1413 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1414 1415 mutex_spin_enter(&sc->sc_intr_lock); 1416 sc->sc_bus.ub_usepolling++; 1417 mutex_spin_exit(&sc->sc_intr_lock); 1418 1419 for (i = 1; i <= sc->sc_noport; i++) { 1420 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1421 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1422 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1423 } 1424 1425 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1426 1427 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1428 EOWRITE4(sc, EHCI_USBCMD, cmd); 1429 1430 for (i = 0; i < 100; i++) { 1431 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1432 if (hcr == 0) 1433 break; 1434 1435 usb_delay_ms(&sc->sc_bus, 1); 1436 } 1437 if (hcr != 0) 1438 printf("%s: reset timeout\n", device_xname(dv)); 1439 1440 cmd &= ~EHCI_CMD_RS; 1441 EOWRITE4(sc, EHCI_USBCMD, cmd); 1442 1443 for (i = 0; i < 100; i++) { 1444 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1445 if (hcr == EHCI_STS_HCH) 1446 break; 1447 1448 usb_delay_ms(&sc->sc_bus, 1); 1449 } 1450 if (hcr != EHCI_STS_HCH) 1451 printf("%s: config timeout\n", device_xname(dv)); 1452 1453 mutex_spin_enter(&sc->sc_intr_lock); 1454 sc->sc_bus.ub_usepolling--; 1455 mutex_spin_exit(&sc->sc_intr_lock); 1456 1457 return true; 1458 } 1459 1460 bool 1461 ehci_resume(device_t dv, const pmf_qual_t *qual) 1462 { 1463 ehci_softc_t *sc = device_private(dv); 1464 int i; 1465 uint32_t cmd, hcr; 1466 1467 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1468 1469 /* restore things in case the bios sucks */ 1470 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1471 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1472 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1473 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1474 1475 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1476 1477 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1478 1479 hcr = 0; 1480 for (i = 1; i <= sc->sc_noport; i++) { 1481 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1482 if ((cmd & EHCI_PS_PO) == 0 && 1483 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1484 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1485 hcr = 1; 1486 } 1487 } 1488 1489 if (hcr) { 1490 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1491 1492 for (i = 1; i <= sc->sc_noport; i++) { 1493 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1494 if ((cmd & EHCI_PS_PO) == 0 && 1495 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1496 EOWRITE4(sc, EHCI_PORTSC(i), 1497 cmd & ~EHCI_PS_FPR); 1498 } 1499 } 1500 1501 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1502 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1503 1504 for (i = 0; i < 100; i++) { 1505 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1506 if (hcr != EHCI_STS_HCH) 1507 break; 1508 1509 usb_delay_ms(&sc->sc_bus, 1); 1510 } 1511 if (hcr == EHCI_STS_HCH) 1512 printf("%s: config timeout\n", device_xname(dv)); 1513 1514 return true; 1515 } 1516 1517 /* 1518 * Shut down the controller when the system is going down. 1519 */ 1520 bool 1521 ehci_shutdown(device_t self, int flags) 1522 { 1523 ehci_softc_t *sc = device_private(self); 1524 1525 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1526 1527 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1528 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1529 return true; 1530 } 1531 1532 Static struct usbd_xfer * 1533 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1534 { 1535 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1536 struct usbd_xfer *xfer; 1537 1538 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1539 if (xfer != NULL) { 1540 memset(xfer, 0, sizeof(struct ehci_xfer)); 1541 1542 /* Initialise this always so we can call remove on it. */ 1543 usb_init_task(&xfer->ux_aborttask, ehci_timeout_task, xfer, 1544 USB_TASKQ_MPSAFE); 1545 #ifdef DIAGNOSTIC 1546 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1547 ex->ex_isdone = true; 1548 xfer->ux_state = XFER_BUSY; 1549 #endif 1550 } 1551 return xfer; 1552 } 1553 1554 Static void 1555 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1556 { 1557 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1558 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1559 1560 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1561 xfer->ux_status == USBD_NOT_STARTED, 1562 "xfer %p state %d\n", xfer, xfer->ux_state); 1563 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1564 1565 #ifdef DIAGNOSTIC 1566 xfer->ux_state = XFER_FREE; 1567 #endif 1568 1569 pool_cache_put(sc->sc_xferpool, xfer); 1570 } 1571 1572 Static void 1573 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1574 { 1575 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1576 1577 *lock = &sc->sc_lock; 1578 } 1579 1580 Static void 1581 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1582 { 1583 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1584 1585 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1586 1587 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1588 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1589 #ifdef EHCI_DEBUG 1590 if (ehcidebug) 1591 usbd_dump_pipe(pipe); 1592 #endif 1593 epipe->nexttoggle = 0; 1594 } 1595 1596 Static void 1597 ehci_noop(struct usbd_pipe *pipe) 1598 { 1599 } 1600 1601 #ifdef EHCI_DEBUG 1602 /* 1603 * Unused function - this is meant to be called from a kernel 1604 * debugger. 1605 */ 1606 void 1607 ehci_dump(void) 1608 { 1609 ehci_softc_t *sc = theehci; 1610 int i; 1611 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1612 EOREAD4(sc, EHCI_USBCMD), 1613 EOREAD4(sc, EHCI_USBSTS), 1614 EOREAD4(sc, EHCI_USBINTR)); 1615 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1616 EOREAD4(sc, EHCI_FRINDEX), 1617 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1618 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1619 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1620 for (i = 1; i <= sc->sc_noport; i++) 1621 printf("port %d status=0x%08x\n", i, 1622 EOREAD4(sc, EHCI_PORTSC(i))); 1623 } 1624 1625 Static void 1626 ehci_dump_regs(ehci_softc_t *sc) 1627 { 1628 int i; 1629 1630 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1631 1632 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1633 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1634 EOREAD4(sc, EHCI_USBINTR), 0); 1635 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1636 "async = 0x%08jx", 1637 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1638 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1639 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1640 for (i = 1; i <= sc->sc_noport; i += 2) { 1641 if (i == sc->sc_noport) { 1642 DPRINTF("port %jd status = 0x%08jx", i, 1643 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1644 } else { 1645 DPRINTF("port %jd status = 0x%08jx port %jd " 1646 "status = 0x%08jx", 1647 i, EOREAD4(sc, EHCI_PORTSC(i)), 1648 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1649 } 1650 } 1651 } 1652 1653 #define ehci_dump_link(link, type) do { \ 1654 DPRINTF(" link 0x%08jx (T = %jd):", \ 1655 link, \ 1656 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1657 if (type) { \ 1658 DPRINTF( \ 1659 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1660 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1661 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1662 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1663 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1664 } \ 1665 } while(0) 1666 1667 Static void 1668 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1669 { 1670 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1671 int i; 1672 uint32_t stop = 0; 1673 1674 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1675 ehci_dump_sqtd(sqtd); 1676 usb_syncmem(&sqtd->dma, 1677 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1678 sizeof(sqtd->qtd), 1679 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1680 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1681 usb_syncmem(&sqtd->dma, 1682 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1683 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1684 } 1685 if (!stop) 1686 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1687 } 1688 1689 Static void 1690 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1691 { 1692 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1693 1694 usb_syncmem(&sqtd->dma, sqtd->offs, 1695 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1696 1697 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1698 0, 0); 1699 ehci_dump_qtd(&sqtd->qtd); 1700 1701 usb_syncmem(&sqtd->dma, sqtd->offs, 1702 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1703 } 1704 1705 Static void 1706 ehci_dump_qtd(ehci_qtd_t *qtd) 1707 { 1708 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1709 uint32_t s = le32toh(qtd->qtd_status); 1710 1711 DPRINTFN(10, 1712 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1713 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1714 DPRINTFN(10, 1715 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1716 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1717 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1718 DPRINTFN(10, 1719 " cerr = %jd pid = %jd stat = %jx", 1720 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1721 0); 1722 DPRINTFN(10, 1723 "active =%jd halted=%jd buferr=%jd babble=%jd", 1724 s & EHCI_QTD_ACTIVE ? 1 : 0, 1725 s & EHCI_QTD_HALTED ? 1 : 0, 1726 s & EHCI_QTD_BUFERR ? 1 : 0, 1727 s & EHCI_QTD_BABBLE ? 1 : 0); 1728 DPRINTFN(10, 1729 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1730 s & EHCI_QTD_XACTERR ? 1 : 0, 1731 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1732 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1733 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1734 DPRINTFN(10, 1735 "buffer[0] = %#jx buffer[1] = %#jx " 1736 "buffer[2] = %#jx buffer[3] = %#jx", 1737 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1738 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1739 DPRINTFN(10, 1740 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1741 } 1742 1743 Static void 1744 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1745 { 1746 ehci_qh_t *qh = &sqh->qh; 1747 ehci_link_t link; 1748 uint32_t endp, endphub; 1749 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1750 1751 usb_syncmem(&sqh->dma, sqh->offs, 1752 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1753 1754 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1755 link = le32toh(qh->qh_link); 1756 ehci_dump_link(link, true); 1757 1758 endp = le32toh(qh->qh_endp); 1759 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1760 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1761 "eps = %jd", 1762 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1763 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1764 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1765 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1766 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1767 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1768 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1769 1770 endphub = le32toh(qh->qh_endphub); 1771 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1772 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1773 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1774 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1775 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1776 EHCI_QH_GET_MULT(endphub), 0); 1777 1778 link = le32toh(qh->qh_curqtd); 1779 ehci_dump_link(link, false); 1780 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1781 ehci_dump_qtd(&qh->qh_qtd); 1782 1783 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1784 BUS_DMASYNC_PREREAD); 1785 } 1786 1787 Static void 1788 ehci_dump_itds(ehci_soft_itd_t *itd) 1789 { 1790 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1791 int i; 1792 uint32_t stop = 0; 1793 1794 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1795 ehci_dump_itd(itd); 1796 usb_syncmem(&itd->dma, 1797 itd->offs + offsetof(ehci_itd_t, itd_next), 1798 sizeof(itd->itd), 1799 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1800 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1801 usb_syncmem(&itd->dma, 1802 itd->offs + offsetof(ehci_itd_t, itd_next), 1803 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1804 } 1805 if (!stop) 1806 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1807 } 1808 1809 Static void 1810 ehci_dump_itd(struct ehci_soft_itd *itd) 1811 { 1812 ehci_isoc_trans_t t; 1813 ehci_isoc_bufr_ptr_t b, b2, b3; 1814 int i; 1815 1816 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1817 1818 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1819 1820 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1821 t = le32toh(itd->itd.itd_ctl[i]); 1822 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1823 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1824 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1825 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1826 EHCI_ITD_GET_OFFS(t), 0); 1827 } 1828 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1829 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1830 DPRINTF(" %jx", 1831 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1832 1833 b = le32toh(itd->itd.itd_bufr[0]); 1834 b2 = le32toh(itd->itd.itd_bufr[1]); 1835 b3 = le32toh(itd->itd.itd_bufr[2]); 1836 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1837 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1838 DPRINTF(" maxpkt = %jx multi = %jx", 1839 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1840 } 1841 1842 Static void 1843 ehci_dump_sitd(struct ehci_soft_itd *itd) 1844 { 1845 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1846 1847 DPRINTF("SITD %#jx next = %p prev = %#jx", 1848 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1849 (uintptr_t)itd->frame_list.prev, 0); 1850 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1851 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1852 } 1853 1854 Static void 1855 ehci_dump_exfer(struct ehci_xfer *ex) 1856 { 1857 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1858 1859 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1860 ex->ex_isdone, 0); 1861 1862 switch (ex->ex_type) { 1863 case EX_CTRL: 1864 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1865 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1866 (uintptr_t)ex->ex_status, 0); 1867 break; 1868 case EX_BULK: 1869 case EX_INTR: 1870 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1871 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1872 0, 0); 1873 break; 1874 case EX_ISOC: 1875 DPRINTF(" itdstart = %#jx itdend = %#jx", 1876 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1877 break; 1878 case EX_FS_ISOC: 1879 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1880 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1881 0, 0); 1882 break; 1883 default: 1884 DPRINTF(" unknown type", 0, 0, 0, 0); 1885 } 1886 } 1887 #endif 1888 1889 Static usbd_status 1890 ehci_open(struct usbd_pipe *pipe) 1891 { 1892 struct usbd_device *dev = pipe->up_dev; 1893 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1894 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1895 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1896 uint8_t addr = dev->ud_addr; 1897 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1898 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1899 ehci_soft_qh_t *sqh; 1900 usbd_status err; 1901 int ival, speed, naks; 1902 int hshubaddr, hshubport; 1903 1904 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1905 1906 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1907 ed->bEndpointAddress, rhaddr); 1908 1909 if (dev->ud_myhsport) { 1910 /* 1911 * When directly attached FS/LS device while doing embedded 1912 * transaction translations and we are the hub, set the hub 1913 * address to 0 (us). 1914 */ 1915 if (!(sc->sc_flags & EHCIF_ETTF) 1916 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1917 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1918 } else { 1919 hshubaddr = 0; 1920 } 1921 hshubport = dev->ud_myhsport->up_portno; 1922 } else { 1923 hshubaddr = 0; 1924 hshubport = 0; 1925 } 1926 1927 if (sc->sc_dying) 1928 return USBD_IOERROR; 1929 1930 /* toggle state needed for bulk endpoints */ 1931 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1932 1933 if (addr == rhaddr) { 1934 switch (ed->bEndpointAddress) { 1935 case USB_CONTROL_ENDPOINT: 1936 pipe->up_methods = &roothub_ctrl_methods; 1937 break; 1938 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1939 pipe->up_methods = &ehci_root_intr_methods; 1940 break; 1941 default: 1942 DPRINTF("bad bEndpointAddress 0x%02jx", 1943 ed->bEndpointAddress, 0, 0, 0); 1944 return USBD_INVAL; 1945 } 1946 return USBD_NORMAL_COMPLETION; 1947 } 1948 1949 /* XXX All this stuff is only valid for async. */ 1950 switch (dev->ud_speed) { 1951 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1952 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1953 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1954 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1955 } 1956 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1957 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1958 0); 1959 return USBD_INVAL; 1960 } 1961 1962 /* 1963 * For interrupt transfer, nak throttling must be disabled, but for 1964 * the other transfer type, nak throttling should be enabled from the 1965 * viewpoint that avoids the memory thrashing. 1966 */ 1967 naks = (xfertype == UE_INTERRUPT) ? 0 1968 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1969 1970 /* Allocate sqh for everything, save isoc xfers */ 1971 if (xfertype != UE_ISOCHRONOUS) { 1972 sqh = ehci_alloc_sqh(sc); 1973 if (sqh == NULL) 1974 return USBD_NOMEM; 1975 /* qh_link filled when the QH is added */ 1976 sqh->qh.qh_endp = htole32( 1977 EHCI_QH_SET_ADDR(addr) | 1978 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1979 EHCI_QH_SET_EPS(speed) | 1980 EHCI_QH_DTC | 1981 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1982 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1983 EHCI_QH_CTL : 0) | 1984 EHCI_QH_SET_NRL(naks) 1985 ); 1986 sqh->qh.qh_endphub = htole32( 1987 EHCI_QH_SET_MULT(1) | 1988 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1989 ); 1990 if (speed != EHCI_QH_SPEED_HIGH) 1991 sqh->qh.qh_endphub |= htole32( 1992 EHCI_QH_SET_PORT(hshubport) | 1993 EHCI_QH_SET_HUBA(hshubaddr) | 1994 (xfertype == UE_INTERRUPT ? 1995 EHCI_QH_SET_CMASK(0x08) : 0) 1996 ); 1997 sqh->qh.qh_curqtd = EHCI_NULL; 1998 /* Fill the overlay qTD */ 1999 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2000 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2001 sqh->qh.qh_qtd.qtd_status = htole32(0); 2002 2003 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2004 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2005 epipe->sqh = sqh; 2006 } else { 2007 sqh = NULL; 2008 } /*xfertype == UE_ISOC*/ 2009 2010 switch (xfertype) { 2011 case UE_CONTROL: 2012 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2013 0, &epipe->ctrl.reqdma); 2014 #ifdef EHCI_DEBUG 2015 if (err) 2016 printf("ehci_open: usb_allocmem()=%d\n", err); 2017 #endif 2018 if (err) 2019 goto bad; 2020 pipe->up_methods = &ehci_device_ctrl_methods; 2021 mutex_enter(&sc->sc_lock); 2022 ehci_add_qh(sc, sqh, sc->sc_async_head); 2023 mutex_exit(&sc->sc_lock); 2024 break; 2025 case UE_BULK: 2026 pipe->up_methods = &ehci_device_bulk_methods; 2027 mutex_enter(&sc->sc_lock); 2028 ehci_add_qh(sc, sqh, sc->sc_async_head); 2029 mutex_exit(&sc->sc_lock); 2030 break; 2031 case UE_INTERRUPT: 2032 pipe->up_methods = &ehci_device_intr_methods; 2033 ival = pipe->up_interval; 2034 if (ival == USBD_DEFAULT_INTERVAL) { 2035 if (speed == EHCI_QH_SPEED_HIGH) { 2036 if (ed->bInterval > 16) { 2037 /* 2038 * illegal with high-speed, but there 2039 * were documentation bugs in the spec, 2040 * so be generous 2041 */ 2042 ival = 256; 2043 } else 2044 ival = (1 << (ed->bInterval - 1)) / 8; 2045 } else 2046 ival = ed->bInterval; 2047 } 2048 err = ehci_device_setintr(sc, sqh, ival); 2049 if (err) 2050 goto bad; 2051 break; 2052 case UE_ISOCHRONOUS: 2053 pipe->up_serialise = false; 2054 if (speed == EHCI_QH_SPEED_HIGH) 2055 pipe->up_methods = &ehci_device_isoc_methods; 2056 else 2057 pipe->up_methods = &ehci_device_fs_isoc_methods; 2058 if (ed->bInterval == 0 || ed->bInterval > 16) { 2059 printf("ehci: opening pipe with invalid bInterval\n"); 2060 err = USBD_INVAL; 2061 goto bad; 2062 } 2063 if (UGETW(ed->wMaxPacketSize) == 0) { 2064 printf("ehci: zero length endpoint open request\n"); 2065 err = USBD_INVAL; 2066 goto bad; 2067 } 2068 epipe->isoc.next_frame = 0; 2069 epipe->isoc.cur_xfers = 0; 2070 break; 2071 default: 2072 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2073 err = USBD_INVAL; 2074 goto bad; 2075 } 2076 return USBD_NORMAL_COMPLETION; 2077 2078 bad: 2079 if (sqh != NULL) { 2080 mutex_enter(&sc->sc_lock); 2081 ehci_free_sqh(sc, sqh); 2082 mutex_exit(&sc->sc_lock); 2083 } 2084 return err; 2085 } 2086 2087 /* 2088 * Add an ED to the schedule. Called with USB lock held. 2089 */ 2090 Static void 2091 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2092 { 2093 2094 KASSERT(mutex_owned(&sc->sc_lock)); 2095 2096 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2097 2098 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2099 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2100 2101 sqh->next = head->next; 2102 sqh->qh.qh_link = head->qh.qh_link; 2103 2104 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2105 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2106 2107 head->next = sqh; 2108 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2109 2110 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2111 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2112 2113 #ifdef EHCI_DEBUG 2114 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2115 ehci_dump_sqh(sqh); 2116 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2117 #endif 2118 } 2119 2120 /* 2121 * Remove an ED from the schedule. Called with USB lock held. 2122 */ 2123 Static void 2124 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2125 { 2126 ehci_soft_qh_t *p; 2127 2128 KASSERT(mutex_owned(&sc->sc_lock)); 2129 2130 /* XXX */ 2131 for (p = head; p != NULL && p->next != sqh; p = p->next) 2132 ; 2133 if (p == NULL) 2134 panic("ehci_rem_qh: ED not found"); 2135 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2136 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2137 p->next = sqh->next; 2138 p->qh.qh_link = sqh->qh.qh_link; 2139 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2140 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2141 2142 ehci_sync_hc(sc); 2143 } 2144 2145 Static void 2146 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2147 { 2148 int i; 2149 uint32_t status; 2150 2151 /* Save toggle bit and ping status. */ 2152 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2153 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2154 status = sqh->qh.qh_qtd.qtd_status & 2155 htole32(EHCI_QTD_TOGGLE_MASK | 2156 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2157 /* Set HALTED to make hw leave it alone. */ 2158 sqh->qh.qh_qtd.qtd_status = 2159 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2160 usb_syncmem(&sqh->dma, 2161 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2162 sizeof(sqh->qh.qh_qtd.qtd_status), 2163 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2164 sqh->qh.qh_curqtd = 0; 2165 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2166 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2167 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2168 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2169 sqh->sqtd = sqtd; 2170 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2171 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2172 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2173 sqh->qh.qh_qtd.qtd_status = status; 2174 usb_syncmem(&sqh->dma, 2175 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2176 sizeof(sqh->qh.qh_qtd.qtd_status), 2177 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2178 } 2179 2180 /* 2181 * Ensure that the HC has released all references to the QH. We do this 2182 * by asking for a Async Advance Doorbell interrupt and then we wait for 2183 * the interrupt. 2184 * To make this easier we first obtain exclusive use of the doorbell. 2185 */ 2186 Static void 2187 ehci_sync_hc(ehci_softc_t *sc) 2188 { 2189 int error __diagused; 2190 2191 KASSERT(mutex_owned(&sc->sc_lock)); 2192 2193 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2194 2195 if (sc->sc_dying) { 2196 DPRINTF("dying", 0, 0, 0, 0); 2197 return; 2198 } 2199 2200 /* ask for doorbell */ 2201 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2202 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2203 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2204 2205 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2206 2207 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2208 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2209 #ifdef DIAGNOSTIC 2210 if (error == EWOULDBLOCK) { 2211 printf("ehci_sync_hc: timed out\n"); 2212 } else if (error) { 2213 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2214 } 2215 #endif 2216 } 2217 2218 Static void 2219 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2220 { 2221 2222 KASSERT(mutex_owned(&sc->sc_lock)); 2223 2224 for (; itd != NULL; itd = itd->xfer_next) { 2225 struct ehci_soft_itd *prev = itd->frame_list.prev; 2226 2227 /* Unlink itd from hardware chain, or frame array */ 2228 if (prev == NULL) { /* We're at the table head */ 2229 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2230 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2231 usb_syncmem(&sc->sc_fldma, 2232 sizeof(ehci_link_t) * itd->slot, 2233 sizeof(ehci_link_t), 2234 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2235 2236 if (itd->frame_list.next != NULL) 2237 itd->frame_list.next->frame_list.prev = NULL; 2238 } else { 2239 /* XXX this part is untested... */ 2240 prev->itd.itd_next = itd->itd.itd_next; 2241 usb_syncmem(&itd->dma, 2242 itd->offs + offsetof(ehci_itd_t, itd_next), 2243 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2244 2245 prev->frame_list.next = itd->frame_list.next; 2246 if (itd->frame_list.next != NULL) 2247 itd->frame_list.next->frame_list.prev = prev; 2248 } 2249 } 2250 } 2251 2252 Static void 2253 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2254 { 2255 struct ehci_soft_itd *next; 2256 2257 mutex_enter(&sc->sc_lock); 2258 next = NULL; 2259 for (; itd != NULL; itd = next) { 2260 next = itd->xfer_next; 2261 ehci_free_itd_locked(sc, itd); 2262 } 2263 mutex_exit(&sc->sc_lock); 2264 } 2265 2266 Static void 2267 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2268 { 2269 2270 KASSERT(mutex_owned(&sc->sc_lock)); 2271 2272 for (; sitd != NULL; sitd = sitd->xfer_next) { 2273 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2274 2275 /* Unlink sitd from hardware chain, or frame array */ 2276 if (prev == NULL) { /* We're at the table head */ 2277 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2278 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2279 usb_syncmem(&sc->sc_fldma, 2280 sizeof(ehci_link_t) * sitd->slot, 2281 sizeof(ehci_link_t), 2282 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2283 2284 if (sitd->frame_list.next != NULL) 2285 sitd->frame_list.next->frame_list.prev = NULL; 2286 } else { 2287 /* XXX this part is untested... */ 2288 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2289 usb_syncmem(&sitd->dma, 2290 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2291 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2292 2293 prev->frame_list.next = sitd->frame_list.next; 2294 if (sitd->frame_list.next != NULL) 2295 sitd->frame_list.next->frame_list.prev = prev; 2296 } 2297 } 2298 } 2299 2300 Static void 2301 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2302 { 2303 2304 mutex_enter(&sc->sc_lock); 2305 struct ehci_soft_sitd *next = NULL; 2306 for (; sitd != NULL; sitd = next) { 2307 next = sitd->xfer_next; 2308 ehci_free_sitd_locked(sc, sitd); 2309 } 2310 mutex_exit(&sc->sc_lock); 2311 } 2312 2313 /***********/ 2314 2315 Static int 2316 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2317 void *buf, int buflen) 2318 { 2319 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2320 usb_hub_descriptor_t hubd; 2321 usb_port_status_t ps; 2322 uint16_t len, value, index; 2323 int l, totlen = 0; 2324 int port, i; 2325 uint32_t v; 2326 2327 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2328 2329 if (sc->sc_dying) 2330 return -1; 2331 2332 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2333 0, 0); 2334 2335 len = UGETW(req->wLength); 2336 value = UGETW(req->wValue); 2337 index = UGETW(req->wIndex); 2338 2339 #define C(x,y) ((x) | ((y) << 8)) 2340 switch (C(req->bRequest, req->bmRequestType)) { 2341 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2342 if (len == 0) 2343 break; 2344 switch (value) { 2345 #define sd ((usb_string_descriptor_t *)buf) 2346 case C(2, UDESC_STRING): 2347 /* Product */ 2348 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2349 break; 2350 #undef sd 2351 default: 2352 /* default from usbroothub */ 2353 return buflen; 2354 } 2355 break; 2356 2357 /* Hub requests */ 2358 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2359 break; 2360 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2361 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2362 value, 0, 0); 2363 if (index < 1 || index > sc->sc_noport) { 2364 return -1; 2365 } 2366 port = EHCI_PORTSC(index); 2367 v = EOREAD4(sc, port); 2368 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2369 v &= ~EHCI_PS_CLEAR; 2370 switch (value) { 2371 case UHF_PORT_ENABLE: 2372 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2373 break; 2374 case UHF_PORT_SUSPEND: 2375 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2376 break; 2377 v &= ~EHCI_PS_SUSP; 2378 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2379 /* see USB2 spec ch. 7.1.7.7 */ 2380 usb_delay_ms(&sc->sc_bus, 20); 2381 EOWRITE4(sc, port, v); 2382 usb_delay_ms(&sc->sc_bus, 2); 2383 #ifdef DEBUG 2384 v = EOREAD4(sc, port); 2385 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2386 printf("ehci: resume failed: %x\n", v); 2387 #endif 2388 break; 2389 case UHF_PORT_POWER: 2390 if (sc->sc_hasppc) 2391 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2392 break; 2393 case UHF_PORT_TEST: 2394 DPRINTF("clear port test %jd", index, 0, 0, 0); 2395 break; 2396 case UHF_PORT_INDICATOR: 2397 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2398 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2399 break; 2400 case UHF_C_PORT_CONNECTION: 2401 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2402 break; 2403 case UHF_C_PORT_ENABLE: 2404 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2405 break; 2406 case UHF_C_PORT_SUSPEND: 2407 /* how? */ 2408 break; 2409 case UHF_C_PORT_OVER_CURRENT: 2410 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2411 break; 2412 case UHF_C_PORT_RESET: 2413 sc->sc_isreset[index] = 0; 2414 break; 2415 default: 2416 return -1; 2417 } 2418 #if 0 2419 switch(value) { 2420 case UHF_C_PORT_CONNECTION: 2421 case UHF_C_PORT_ENABLE: 2422 case UHF_C_PORT_SUSPEND: 2423 case UHF_C_PORT_OVER_CURRENT: 2424 case UHF_C_PORT_RESET: 2425 default: 2426 break; 2427 } 2428 #endif 2429 break; 2430 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2431 if (len == 0) 2432 break; 2433 if ((value & 0xff) != 0) { 2434 return -1; 2435 } 2436 totlen = uimin(buflen, sizeof(hubd)); 2437 memcpy(&hubd, buf, totlen); 2438 hubd.bNbrPorts = sc->sc_noport; 2439 v = EOREAD4(sc, EHCI_HCSPARAMS); 2440 USETW(hubd.wHubCharacteristics, 2441 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2442 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2443 ? UHD_PORT_IND : 0); 2444 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2445 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2446 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2447 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2448 totlen = uimin(totlen, hubd.bDescLength); 2449 memcpy(buf, &hubd, totlen); 2450 break; 2451 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2452 if (len != 4) { 2453 return -1; 2454 } 2455 memset(buf, 0, len); /* ? XXX */ 2456 totlen = len; 2457 break; 2458 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2459 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2460 if (index < 1 || index > sc->sc_noport) { 2461 return -1; 2462 } 2463 if (len != 4) { 2464 return -1; 2465 } 2466 v = EOREAD4(sc, EHCI_PORTSC(index)); 2467 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2468 2469 i = UPS_HIGH_SPEED; 2470 if (sc->sc_flags & EHCIF_ETTF) { 2471 /* 2472 * If we are doing embedded transaction translation, 2473 * then directly attached LS/FS devices are reset by 2474 * the EHCI controller itself. PSPD is encoded 2475 * the same way as in USBSTATUS. 2476 */ 2477 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2478 } 2479 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2480 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2481 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2482 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2483 if (v & EHCI_PS_PR) i |= UPS_RESET; 2484 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2485 if (sc->sc_vendor_port_status) 2486 i = sc->sc_vendor_port_status(sc, v, i); 2487 USETW(ps.wPortStatus, i); 2488 i = 0; 2489 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2490 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2491 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2492 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2493 USETW(ps.wPortChange, i); 2494 totlen = uimin(len, sizeof(ps)); 2495 memcpy(buf, &ps, totlen); 2496 break; 2497 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2498 return -1; 2499 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2500 break; 2501 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2502 if (index < 1 || index > sc->sc_noport) { 2503 return -1; 2504 } 2505 port = EHCI_PORTSC(index); 2506 v = EOREAD4(sc, port); 2507 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2508 v &= ~EHCI_PS_CLEAR; 2509 switch(value) { 2510 case UHF_PORT_ENABLE: 2511 EOWRITE4(sc, port, v | EHCI_PS_PE); 2512 break; 2513 case UHF_PORT_SUSPEND: 2514 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2515 break; 2516 case UHF_PORT_RESET: 2517 DPRINTF("reset port %jd", index, 0, 0, 0); 2518 if (EHCI_PS_IS_LOWSPEED(v) 2519 && sc->sc_ncomp > 0 2520 && !(sc->sc_flags & EHCIF_ETTF)) { 2521 /* 2522 * Low speed device on non-ETTF controller or 2523 * unaccompanied controller, give up ownership. 2524 */ 2525 ehci_disown(sc, index, 1); 2526 break; 2527 } 2528 /* Start reset sequence. */ 2529 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2530 EOWRITE4(sc, port, v | EHCI_PS_PR); 2531 /* Wait for reset to complete. */ 2532 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2533 if (sc->sc_dying) { 2534 return -1; 2535 } 2536 /* 2537 * An embedded transaction translator will automatically 2538 * terminate the reset sequence so there's no need to 2539 * it. 2540 */ 2541 v = EOREAD4(sc, port); 2542 if (v & EHCI_PS_PR) { 2543 /* Terminate reset sequence. */ 2544 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2545 /* Wait for HC to complete reset. */ 2546 usb_delay_ms(&sc->sc_bus, 2547 EHCI_PORT_RESET_COMPLETE); 2548 if (sc->sc_dying) { 2549 return -1; 2550 } 2551 } 2552 2553 v = EOREAD4(sc, port); 2554 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2555 if (v & EHCI_PS_PR) { 2556 printf("%s: port reset timeout\n", 2557 device_xname(sc->sc_dev)); 2558 return USBD_TIMEOUT; 2559 } 2560 if (!(v & EHCI_PS_PE)) { 2561 /* Not a high speed device, give up ownership.*/ 2562 ehci_disown(sc, index, 0); 2563 break; 2564 } 2565 sc->sc_isreset[index] = 1; 2566 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2567 v, 0, 0); 2568 break; 2569 case UHF_PORT_POWER: 2570 DPRINTF("set port power %jd (has PPC = %jd)", index, 2571 sc->sc_hasppc, 0, 0); 2572 if (sc->sc_hasppc) 2573 EOWRITE4(sc, port, v | EHCI_PS_PP); 2574 break; 2575 case UHF_PORT_TEST: 2576 DPRINTF("set port test %jd", index, 0, 0, 0); 2577 break; 2578 case UHF_PORT_INDICATOR: 2579 DPRINTF("set port ind %jd", index, 0, 0, 0); 2580 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2581 break; 2582 default: 2583 return -1; 2584 } 2585 break; 2586 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2587 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2588 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2589 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2590 break; 2591 default: 2592 /* default from usbroothub */ 2593 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2594 2595 return buflen; 2596 } 2597 2598 DPRINTF("returning %jd", totlen, 0, 0, 0); 2599 2600 return totlen; 2601 } 2602 2603 /* 2604 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2605 * 2606 * This pile of garbage below works around the following problem without 2607 * holding boots with no hand-over devices present, while penalising 2608 * boots where the first ehci probe hands off devices with a 5 second 2609 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2610 * for RB_SINGLE, but the same basic issue exists. 2611 * 2612 * The way ehci hand-off works, the companion controller does not get the 2613 * device until after its initial bus explore, so the reference dropped 2614 * after the first explore is not enough. 5 seconds should be enough, 2615 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2616 * 2617 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2618 * if the callback is scheduled. CO_DONE is set when the callout has 2619 * called config_pending_decr(). 2620 * 2621 * There's a mutex, a cv and a callout here, and we delay detach if the 2622 * callout has been set. 2623 */ 2624 #ifndef EHCI_DISOWN_DELAY_SECONDS 2625 #define EHCI_DISOWN_DELAY_SECONDS 5 2626 #endif 2627 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2628 2629 static void 2630 ehci_disown_callback(void *arg) 2631 { 2632 ehci_softc_t *sc = arg; 2633 2634 config_pending_decr(sc->sc_dev); 2635 2636 mutex_enter(&sc->sc_complock); 2637 KASSERT(sc->sc_comp_state == CO_SCHED); 2638 sc->sc_comp_state = CO_DONE; 2639 cv_signal(&sc->sc_compcv); 2640 mutex_exit(&sc->sc_complock); 2641 } 2642 2643 static void 2644 ehci_disown_sched_callback(ehci_softc_t *sc) 2645 { 2646 extern bool root_is_mounted; 2647 2648 mutex_enter(&sc->sc_complock); 2649 2650 if (root_is_mounted || 2651 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2652 sc->sc_comp_state != CO_EARLY) { 2653 mutex_exit(&sc->sc_complock); 2654 return; 2655 } 2656 2657 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2658 ehci_disown_callback, &sc->sc_dev); 2659 sc->sc_comp_state = CO_SCHED; 2660 2661 mutex_exit(&sc->sc_complock); 2662 2663 config_pending_incr(sc->sc_dev); 2664 aprint_normal("delaying %s by %u seconds due to USB owner change.", 2665 (boothowto & RB_ASKNAME) == 0 ? "ask root" : "single user", 2666 ehci_disown_delay_seconds); 2667 } 2668 2669 Static void 2670 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2671 { 2672 int port; 2673 uint32_t v; 2674 2675 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2676 2677 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2678 if (sc->sc_npcomp != 0) { 2679 int i = (index-1) / sc->sc_npcomp; 2680 if (i < sc->sc_ncomp) { 2681 ehci_disown_sched_callback(sc); 2682 #ifdef DIAGNOSTIC 2683 printf("%s: handing over %s speed device on " 2684 "port %d to %s\n", 2685 device_xname(sc->sc_dev), 2686 lowspeed ? "low" : "full", 2687 index, sc->sc_comps[i] ? 2688 device_xname(sc->sc_comps[i]) : 2689 "companion controller"); 2690 } else { 2691 printf("%s: strange port\n", 2692 device_xname(sc->sc_dev)); 2693 #endif 2694 } 2695 } else { 2696 #ifdef DIAGNOSTIC 2697 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2698 #endif 2699 } 2700 port = EHCI_PORTSC(index); 2701 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2702 EOWRITE4(sc, port, v | EHCI_PS_PO); 2703 } 2704 2705 Static usbd_status 2706 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2707 { 2708 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2709 usbd_status err; 2710 2711 /* Insert last in queue. */ 2712 mutex_enter(&sc->sc_lock); 2713 err = usb_insert_transfer(xfer); 2714 mutex_exit(&sc->sc_lock); 2715 if (err) 2716 return err; 2717 2718 /* Pipe isn't running, start first */ 2719 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2720 } 2721 2722 Static usbd_status 2723 ehci_root_intr_start(struct usbd_xfer *xfer) 2724 { 2725 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2726 const bool polling = sc->sc_bus.ub_usepolling; 2727 2728 if (sc->sc_dying) 2729 return USBD_IOERROR; 2730 2731 if (!polling) 2732 mutex_enter(&sc->sc_lock); 2733 sc->sc_intrxfer = xfer; 2734 if (!polling) 2735 mutex_exit(&sc->sc_lock); 2736 2737 return USBD_IN_PROGRESS; 2738 } 2739 2740 /* Abort a root interrupt request. */ 2741 Static void 2742 ehci_root_intr_abort(struct usbd_xfer *xfer) 2743 { 2744 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2745 2746 KASSERT(mutex_owned(&sc->sc_lock)); 2747 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2748 2749 sc->sc_intrxfer = NULL; 2750 2751 xfer->ux_status = USBD_CANCELLED; 2752 usb_transfer_complete(xfer); 2753 } 2754 2755 /* Close the root pipe. */ 2756 Static void 2757 ehci_root_intr_close(struct usbd_pipe *pipe) 2758 { 2759 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2760 2761 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2762 2763 KASSERT(mutex_owned(&sc->sc_lock)); 2764 2765 sc->sc_intrxfer = NULL; 2766 } 2767 2768 Static void 2769 ehci_root_intr_done(struct usbd_xfer *xfer) 2770 { 2771 } 2772 2773 /************************/ 2774 2775 Static ehci_soft_qh_t * 2776 ehci_alloc_sqh(ehci_softc_t *sc) 2777 { 2778 ehci_soft_qh_t *sqh; 2779 usbd_status err; 2780 int i, offs; 2781 usb_dma_t dma; 2782 2783 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2784 2785 mutex_enter(&sc->sc_lock); 2786 if (sc->sc_freeqhs == NULL) { 2787 DPRINTF("allocating chunk", 0, 0, 0, 0); 2788 mutex_exit(&sc->sc_lock); 2789 2790 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2791 EHCI_PAGE_SIZE, &dma); 2792 #ifdef EHCI_DEBUG 2793 if (err) 2794 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2795 #endif 2796 if (err) 2797 return NULL; 2798 2799 mutex_enter(&sc->sc_lock); 2800 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2801 offs = i * EHCI_SQH_SIZE; 2802 sqh = KERNADDR(&dma, offs); 2803 sqh->physaddr = DMAADDR(&dma, offs); 2804 sqh->dma = dma; 2805 sqh->offs = offs; 2806 sqh->next = sc->sc_freeqhs; 2807 sc->sc_freeqhs = sqh; 2808 } 2809 } 2810 sqh = sc->sc_freeqhs; 2811 sc->sc_freeqhs = sqh->next; 2812 mutex_exit(&sc->sc_lock); 2813 2814 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2815 sqh->next = NULL; 2816 return sqh; 2817 } 2818 2819 Static void 2820 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2821 { 2822 KASSERT(mutex_owned(&sc->sc_lock)); 2823 2824 sqh->next = sc->sc_freeqhs; 2825 sc->sc_freeqhs = sqh; 2826 } 2827 2828 Static ehci_soft_qtd_t * 2829 ehci_alloc_sqtd(ehci_softc_t *sc) 2830 { 2831 ehci_soft_qtd_t *sqtd = NULL; 2832 usbd_status err; 2833 int i, offs; 2834 usb_dma_t dma; 2835 2836 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2837 2838 mutex_enter(&sc->sc_lock); 2839 if (sc->sc_freeqtds == NULL) { 2840 DPRINTF("allocating chunk", 0, 0, 0, 0); 2841 mutex_exit(&sc->sc_lock); 2842 2843 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2844 EHCI_PAGE_SIZE, &dma); 2845 #ifdef EHCI_DEBUG 2846 if (err) 2847 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2848 #endif 2849 if (err) 2850 goto done; 2851 2852 mutex_enter(&sc->sc_lock); 2853 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2854 offs = i * EHCI_SQTD_SIZE; 2855 sqtd = KERNADDR(&dma, offs); 2856 sqtd->physaddr = DMAADDR(&dma, offs); 2857 sqtd->dma = dma; 2858 sqtd->offs = offs; 2859 2860 sqtd->nextqtd = sc->sc_freeqtds; 2861 sc->sc_freeqtds = sqtd; 2862 } 2863 } 2864 2865 sqtd = sc->sc_freeqtds; 2866 sc->sc_freeqtds = sqtd->nextqtd; 2867 mutex_exit(&sc->sc_lock); 2868 2869 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2870 sqtd->nextqtd = NULL; 2871 sqtd->xfer = NULL; 2872 2873 done: 2874 return sqtd; 2875 } 2876 2877 Static void 2878 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2879 { 2880 2881 mutex_enter(&sc->sc_lock); 2882 sqtd->nextqtd = sc->sc_freeqtds; 2883 sc->sc_freeqtds = sqtd; 2884 mutex_exit(&sc->sc_lock); 2885 } 2886 2887 Static int 2888 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2889 int alen, int rd, ehci_soft_qtd_t **sp) 2890 { 2891 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2892 uint16_t flags = xfer->ux_flags; 2893 2894 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2895 2896 ASSERT_SLEEPABLE(); 2897 KASSERT(sp); 2898 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2899 2900 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2901 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2902 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2903 KM_SLEEP); 2904 exfer->ex_nsqtd = nsqtd; 2905 2906 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2907 alen, nsqtd, flags); 2908 2909 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2910 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2911 if (cur == NULL) 2912 goto nomem; 2913 exfer->ex_sqtds[j++] = cur; 2914 2915 cur->xfer = xfer; 2916 cur->len = 0; 2917 2918 } 2919 2920 *sp = exfer->ex_sqtds[0]; 2921 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2922 2923 return 0; 2924 2925 nomem: 2926 ehci_free_sqtds(sc, exfer); 2927 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2928 DPRINTF("no memory", 0, 0, 0, 0); 2929 return ENOMEM; 2930 } 2931 2932 Static void 2933 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2934 { 2935 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2936 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2937 2938 mutex_enter(&sc->sc_lock); 2939 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2940 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2941 2942 if (sqtd == NULL) 2943 break; 2944 2945 sqtd->nextqtd = sc->sc_freeqtds; 2946 sc->sc_freeqtds = sqtd; 2947 } 2948 mutex_exit(&sc->sc_lock); 2949 } 2950 2951 Static void 2952 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2953 { 2954 if (prev) { 2955 prev->nextqtd = sqtd; 2956 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2957 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2958 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2959 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2960 } 2961 } 2962 2963 Static void 2964 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2965 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2966 { 2967 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2968 usb_dma_t *dma = &xfer->ux_dmabuf; 2969 uint16_t flags = xfer->ux_flags; 2970 ehci_soft_qtd_t *sqtd, *prev; 2971 int tog = *toggle; 2972 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2973 int len = length; 2974 2975 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2976 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2977 len, isread, tog); 2978 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2979 0, 0, 0); 2980 2981 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2982 2983 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2984 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2985 EHCI_QTD_SET_CERR(3) 2986 ; 2987 2988 sqtd = prev = NULL; 2989 size_t curoffs = 0; 2990 size_t j = 0; 2991 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2992 sqtd = exfer->ex_sqtds[j++]; 2993 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 2994 (uintptr_t)prev, 0); 2995 2996 /* 2997 * The EHCI hardware can handle at most 5 pages and they do 2998 * not have to be contiguous 2999 */ 3000 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3001 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3002 size_t curlen = len; 3003 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3004 /* must use multiple TDs, fill as much as possible. */ 3005 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3006 3007 /* the length must be a multiple of the max size */ 3008 curlen -= curlen % mps; 3009 } 3010 KASSERT(curlen != 0); 3011 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3012 curoffs, 0); 3013 3014 /* Fill the qTD */ 3015 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3016 sqtd->qtd.qtd_status = htole32( 3017 qtdstatus | 3018 EHCI_QTD_SET_BYTES(curlen) | 3019 EHCI_QTD_SET_TOGGLE(tog)); 3020 3021 /* Find number of pages we'll be using, insert dma addresses */ 3022 size_t pages = EHCI_NPAGES(curlen); 3023 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3024 size_t pageoffs = EHCI_PAGE(curoffs); 3025 for (size_t i = 0; i < pages; i++) { 3026 paddr_t a = DMAADDR(dma, 3027 pageoffs + i * EHCI_PAGE_SIZE); 3028 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 3029 /* Cast up to avoid compiler warnings */ 3030 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 3031 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3032 i, pages, 3033 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3034 le32toh(sqtd->qtd.qtd_buffer[i])); 3035 } 3036 /* First buffer pointer requires a page offset to start at */ 3037 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3038 3039 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3040 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3041 3042 sqtd->len = curlen; 3043 3044 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3045 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3046 3047 ehci_append_sqtd(sqtd, prev); 3048 3049 if (((curlen + mps - 1) / mps) & 1) { 3050 tog ^= 1; 3051 } 3052 3053 curoffs += curlen; 3054 len -= curlen; 3055 } 3056 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3057 xfer, length, len, mps, exfer->ex_nsqtd, j); 3058 3059 if (!isread && 3060 (flags & USBD_FORCE_SHORT_XFER) && 3061 length % mps == 0) { 3062 /* Force a 0 length transfer at the end. */ 3063 3064 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3065 exfer->ex_nsqtd); 3066 prev = sqtd; 3067 sqtd = exfer->ex_sqtds[j++]; 3068 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3069 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3070 sqtd->qtd.qtd_status = htole32( 3071 qtdstatus | 3072 EHCI_QTD_SET_BYTES(0) | 3073 EHCI_QTD_SET_TOGGLE(tog)); 3074 3075 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3076 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3077 3078 ehci_append_sqtd(sqtd, prev); 3079 tog ^= 1; 3080 } 3081 3082 *lsqtd = sqtd; 3083 *toggle = tog; 3084 } 3085 3086 Static ehci_soft_itd_t * 3087 ehci_alloc_itd(ehci_softc_t *sc) 3088 { 3089 struct ehci_soft_itd *itd, *freeitd; 3090 usbd_status err; 3091 usb_dma_t dma; 3092 3093 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3094 3095 mutex_enter(&sc->sc_lock); 3096 3097 freeitd = LIST_FIRST(&sc->sc_freeitds); 3098 if (freeitd == NULL) { 3099 DPRINTF("allocating chunk", 0, 0, 0, 0); 3100 mutex_exit(&sc->sc_lock); 3101 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3102 EHCI_PAGE_SIZE, &dma); 3103 3104 if (err) { 3105 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3106 return NULL; 3107 } 3108 mutex_enter(&sc->sc_lock); 3109 3110 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3111 int offs = i * EHCI_ITD_SIZE; 3112 itd = KERNADDR(&dma, offs); 3113 itd->physaddr = DMAADDR(&dma, offs); 3114 itd->dma = dma; 3115 itd->offs = offs; 3116 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3117 } 3118 freeitd = LIST_FIRST(&sc->sc_freeitds); 3119 } 3120 3121 itd = freeitd; 3122 LIST_REMOVE(itd, free_list); 3123 mutex_exit(&sc->sc_lock); 3124 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3125 3126 itd->frame_list.next = NULL; 3127 itd->frame_list.prev = NULL; 3128 itd->xfer_next = NULL; 3129 itd->slot = 0; 3130 3131 return itd; 3132 } 3133 3134 Static ehci_soft_sitd_t * 3135 ehci_alloc_sitd(ehci_softc_t *sc) 3136 { 3137 struct ehci_soft_sitd *sitd, *freesitd; 3138 usbd_status err; 3139 int i, offs; 3140 usb_dma_t dma; 3141 3142 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3143 3144 mutex_enter(&sc->sc_lock); 3145 freesitd = LIST_FIRST(&sc->sc_freesitds); 3146 if (freesitd == NULL) { 3147 DPRINTF("allocating chunk", 0, 0, 0, 0); 3148 mutex_exit(&sc->sc_lock); 3149 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3150 EHCI_PAGE_SIZE, &dma); 3151 3152 if (err) { 3153 DPRINTF("alloc returned %jd", err, 0, 0, 3154 0); 3155 return NULL; 3156 } 3157 3158 mutex_enter(&sc->sc_lock); 3159 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3160 offs = i * EHCI_SITD_SIZE; 3161 sitd = KERNADDR(&dma, offs); 3162 sitd->physaddr = DMAADDR(&dma, offs); 3163 sitd->dma = dma; 3164 sitd->offs = offs; 3165 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3166 } 3167 freesitd = LIST_FIRST(&sc->sc_freesitds); 3168 } 3169 3170 sitd = freesitd; 3171 LIST_REMOVE(sitd, free_list); 3172 mutex_exit(&sc->sc_lock); 3173 3174 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3175 3176 sitd->frame_list.next = NULL; 3177 sitd->frame_list.prev = NULL; 3178 sitd->xfer_next = NULL; 3179 sitd->slot = 0; 3180 3181 return sitd; 3182 } 3183 3184 /****************/ 3185 3186 /* 3187 * Close a reqular pipe. 3188 * Assumes that there are no pending transactions. 3189 */ 3190 Static void 3191 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3192 { 3193 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3194 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3195 ehci_soft_qh_t *sqh = epipe->sqh; 3196 3197 KASSERT(mutex_owned(&sc->sc_lock)); 3198 3199 ehci_rem_qh(sc, sqh, head); 3200 ehci_free_sqh(sc, epipe->sqh); 3201 } 3202 3203 /* 3204 * Cancel or timeout a device request. We have two cases to deal with 3205 * 3206 * 1) A driver wants to stop scheduled or inflight transfers 3207 * 2) A transfer has timed out 3208 * 3209 * have (partially) happened since the hardware runs concurrently. 3210 * 3211 * Transfer state is protected by the bus lock and we set the transfer status 3212 * as soon as either of the above happens (with bus lock held). 3213 * 3214 * Then we arrange for the hardware to tells us that it is not still 3215 * processing the TDs by setting the QH halted bit and wait for the ehci 3216 * door bell 3217 */ 3218 Static void 3219 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3220 { 3221 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3222 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3223 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3224 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3225 ehci_soft_qh_t *sqh = epipe->sqh; 3226 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3227 ehci_physaddr_t cur; 3228 uint32_t qhstatus; 3229 int hit; 3230 3231 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 3232 "invalid status for abort: %d", (int)status); 3233 3234 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3235 3236 KASSERT(mutex_owned(&sc->sc_lock)); 3237 ASSERT_SLEEPABLE(); 3238 3239 /* 3240 * Nobody else can set this status: only one caller can time 3241 * out, and only one caller can synchronously abort. So the 3242 * status can't be the status we're trying to set this to. 3243 */ 3244 KASSERT(xfer->ux_status != status); 3245 3246 /* 3247 * If host controller or timer interrupt has completed it, too 3248 * late to abort. Forget about it. 3249 */ 3250 if (xfer->ux_status != USBD_IN_PROGRESS) 3251 return; 3252 3253 if (status == USBD_CANCELLED) { 3254 /* 3255 * We are synchronously aborting. Cancel the timeout 3256 * if we can, but only asynchronously. See 3257 * ehci_cancel_timeout_async for why we need not wait 3258 * for the callout or task here. 3259 */ 3260 ehci_cancel_timeout_async(xfer); 3261 } else { 3262 /* 3263 * Otherwise, we are timing out. No action needed to 3264 * cancel the timeout because we _are_ the timeout. 3265 * This case should happen only via the timeout task, 3266 * invoked via the callout. 3267 */ 3268 KASSERT(status == USBD_TIMEOUT); 3269 } 3270 3271 /* We beat everyone else. Claim the status. */ 3272 xfer->ux_status = status; 3273 3274 /* 3275 * If we're dying, skip the hardware action and just notify the 3276 * software that we're done. 3277 */ 3278 if (sc->sc_dying) { 3279 goto dying; 3280 } 3281 3282 /* 3283 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3284 */ 3285 ehci_del_intr_list(sc, exfer); 3286 3287 usb_syncmem(&sqh->dma, 3288 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3289 sizeof(sqh->qh.qh_qtd.qtd_status), 3290 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3291 qhstatus = sqh->qh.qh_qtd.qtd_status; 3292 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3293 usb_syncmem(&sqh->dma, 3294 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3295 sizeof(sqh->qh.qh_qtd.qtd_status), 3296 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3297 3298 if (exfer->ex_type == EX_CTRL) { 3299 fsqtd = exfer->ex_setup; 3300 lsqtd = exfer->ex_status; 3301 } else { 3302 fsqtd = exfer->ex_sqtdstart; 3303 lsqtd = exfer->ex_sqtdend; 3304 } 3305 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3306 usb_syncmem(&sqtd->dma, 3307 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3308 sizeof(sqtd->qtd.qtd_status), 3309 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3310 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3311 usb_syncmem(&sqtd->dma, 3312 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3313 sizeof(sqtd->qtd.qtd_status), 3314 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3315 if (sqtd == lsqtd) 3316 break; 3317 } 3318 3319 /* 3320 * HC Step 2: Wait until we know hardware has finished any possible 3321 * use of the xfer. 3322 */ 3323 ehci_sync_hc(sc); 3324 3325 /* 3326 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3327 * The complication here is that the hardware may have executed 3328 * beyond the xfer we're trying to abort. So as we're scanning 3329 * the TDs of this xfer we check if the hardware points to 3330 * any of them. 3331 */ 3332 3333 usb_syncmem(&sqh->dma, 3334 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3335 sizeof(sqh->qh.qh_curqtd), 3336 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3337 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3338 hit = 0; 3339 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3340 hit |= cur == sqtd->physaddr; 3341 if (sqtd == lsqtd) 3342 break; 3343 } 3344 sqtd = sqtd->nextqtd; 3345 /* Zap curqtd register if hardware pointed inside the xfer. */ 3346 if (hit && sqtd != NULL) { 3347 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3348 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3349 usb_syncmem(&sqh->dma, 3350 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3351 sizeof(sqh->qh.qh_curqtd), 3352 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3353 sqh->qh.qh_qtd.qtd_status = qhstatus; 3354 usb_syncmem(&sqh->dma, 3355 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3356 sizeof(sqh->qh.qh_qtd.qtd_status), 3357 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3358 } else { 3359 DPRINTF("no hit", 0, 0, 0, 0); 3360 usb_syncmem(&sqh->dma, 3361 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3362 sizeof(sqh->qh.qh_curqtd), 3363 BUS_DMASYNC_PREREAD); 3364 } 3365 3366 /* 3367 * Final step: Notify completion to waiting xfers. 3368 */ 3369 dying: 3370 #ifdef DIAGNOSTIC 3371 exfer->ex_isdone = true; 3372 #endif 3373 usb_transfer_complete(xfer); 3374 DPRINTFN(14, "end", 0, 0, 0, 0); 3375 3376 KASSERT(mutex_owned(&sc->sc_lock)); 3377 } 3378 3379 Static void 3380 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3381 { 3382 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3383 ehci_isoc_trans_t trans_status; 3384 struct ehci_xfer *exfer; 3385 ehci_softc_t *sc; 3386 struct ehci_soft_itd *itd; 3387 struct ehci_soft_sitd *sitd; 3388 int i; 3389 3390 KASSERTMSG(status == USBD_CANCELLED, 3391 "invalid status for abort: %d", (int)status); 3392 3393 exfer = EHCI_XFER2EXFER(xfer); 3394 sc = EHCI_XFER2SC(xfer); 3395 3396 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3397 (uintptr_t)xfer->ux_pipe, 0, 0); 3398 3399 KASSERT(mutex_owned(&sc->sc_lock)); 3400 ASSERT_SLEEPABLE(); 3401 3402 /* No timeout or task here. */ 3403 3404 /* 3405 * The xfer cannot have been cancelled already. It is the 3406 * responsibility of the caller of usbd_abort_pipe not to try 3407 * to abort a pipe multiple times, whether concurrently or 3408 * sequentially. 3409 */ 3410 KASSERT(xfer->ux_status != USBD_CANCELLED); 3411 3412 /* If anyone else beat us, we're done. */ 3413 if (xfer->ux_status != USBD_IN_PROGRESS) 3414 return; 3415 3416 /* We beat everyone else. Claim the status. */ 3417 xfer->ux_status = status; 3418 3419 /* 3420 * If we're dying, skip the hardware action and just notify the 3421 * software that we're done. 3422 */ 3423 if (sc->sc_dying) { 3424 goto dying; 3425 } 3426 3427 /* 3428 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3429 */ 3430 ehci_del_intr_list(sc, exfer); 3431 3432 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3433 for (itd = exfer->ex_itdstart; itd != NULL; 3434 itd = itd->xfer_next) { 3435 usb_syncmem(&itd->dma, 3436 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3437 sizeof(itd->itd.itd_ctl), 3438 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3439 3440 for (i = 0; i < 8; i++) { 3441 trans_status = le32toh(itd->itd.itd_ctl[i]); 3442 trans_status &= ~EHCI_ITD_ACTIVE; 3443 itd->itd.itd_ctl[i] = htole32(trans_status); 3444 } 3445 3446 usb_syncmem(&itd->dma, 3447 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3448 sizeof(itd->itd.itd_ctl), 3449 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3450 } 3451 } else { 3452 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3453 sitd = sitd->xfer_next) { 3454 usb_syncmem(&sitd->dma, 3455 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3456 sizeof(sitd->sitd.sitd_buffer), 3457 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3458 3459 trans_status = le32toh(sitd->sitd.sitd_trans); 3460 trans_status &= ~EHCI_SITD_ACTIVE; 3461 sitd->sitd.sitd_trans = htole32(trans_status); 3462 3463 usb_syncmem(&sitd->dma, 3464 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3465 sizeof(sitd->sitd.sitd_buffer), 3466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3467 } 3468 } 3469 3470 dying: 3471 #ifdef DIAGNOSTIC 3472 exfer->ex_isdone = true; 3473 #endif 3474 usb_transfer_complete(xfer); 3475 DPRINTFN(14, "end", 0, 0, 0, 0); 3476 3477 KASSERT(mutex_owned(&sc->sc_lock)); 3478 } 3479 3480 /* 3481 * ehci_timeout(xfer) 3482 * 3483 * Called at IPL_SOFTCLOCK when too much time has elapsed waiting 3484 * for xfer to complete. Since we can't abort the xfer at 3485 * IPL_SOFTCLOCK, defer to a usb_task to run it in thread context, 3486 * unless the xfer has completed or aborted concurrently -- and if 3487 * the xfer has also been resubmitted, take care of rescheduling 3488 * the callout. 3489 */ 3490 Static void 3491 ehci_timeout(void *addr) 3492 { 3493 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3494 struct usbd_xfer *xfer = addr; 3495 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3496 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3497 3498 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3499 #ifdef EHCI_DEBUG 3500 if (ehcidebug >= 2) { 3501 struct usbd_pipe *pipe = xfer->ux_pipe; 3502 usbd_dump_pipe(pipe); 3503 } 3504 #endif 3505 3506 /* Acquire the lock so we can transition the timeout state. */ 3507 mutex_enter(&sc->sc_lock); 3508 3509 /* 3510 * Use ehci_probe_timeout to check whether the timeout is still 3511 * valid, or to reschedule the callout if necessary. If it is 3512 * still valid, schedule the task. 3513 */ 3514 if (ehci_probe_timeout(xfer)) 3515 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3516 3517 /* 3518 * Notify ehci_cancel_timeout_async that we may have scheduled 3519 * the task. This causes callout_invoking to return false in 3520 * ehci_cancel_timeout_async so that it can tell which stage in 3521 * the callout->task->abort process we're at. 3522 */ 3523 callout_ack(&xfer->ux_callout); 3524 3525 /* All done -- release the lock. */ 3526 mutex_exit(&sc->sc_lock); 3527 } 3528 3529 /* 3530 * ehci_timeout_task(xfer) 3531 * 3532 * Called in thread context when too much time has elapsed waiting 3533 * for xfer to complete. Issue ehci_abort_xfer(USBD_TIMEOUT), 3534 * unless the xfer has completed or aborted concurrently -- and if 3535 * the xfer has also been resubmitted, take care of rescheduling 3536 * the callout. 3537 */ 3538 Static void 3539 ehci_timeout_task(void *addr) 3540 { 3541 struct usbd_xfer *xfer = addr; 3542 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3543 3544 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3545 3546 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3547 3548 /* Acquire the lock so we can transition the timeout state. */ 3549 mutex_enter(&sc->sc_lock); 3550 3551 /* 3552 * Use ehci_probe_timeout to check whether the timeout is still 3553 * valid, or to reschedule the callout if necessary. If it is 3554 * still valid, schedule the task. 3555 */ 3556 if (ehci_probe_timeout(xfer)) 3557 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3558 3559 /* All done -- release the lock. */ 3560 mutex_exit(&sc->sc_lock); 3561 } 3562 3563 /* 3564 * ehci_probe_timeout(xfer) 3565 * 3566 * Probe the status of xfer's timeout. Acknowledge and process a 3567 * request to reschedule. Return true if the timeout is still 3568 * valid and the caller should take further action (queueing a 3569 * task or aborting the xfer), false if it must stop here. 3570 */ 3571 Static bool 3572 ehci_probe_timeout(struct usbd_xfer *xfer) 3573 { 3574 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3575 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 3576 bool valid; 3577 3578 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3579 3580 /* The timeout must be set. */ 3581 KASSERT(xfer->ux_timeout_set); 3582 3583 /* 3584 * Neither callout nor task may be pending; they execute 3585 * alternately in lock step. 3586 */ 3587 KASSERT(!callout_pending(&xfer->ux_callout)); 3588 KASSERT(!usb_task_pending(xfer->ux_pipe->up_dev, &xfer->ux_aborttask)); 3589 3590 /* There are a few cases... */ 3591 if (sc->sc_dying) { 3592 /* Host controller dying. Drop it all on the floor. */ 3593 xfer->ux_timeout_set = false; 3594 xfer->ux_timeout_reset = false; 3595 valid = false; 3596 } else if (xfer->ux_timeout_reset) { 3597 /* 3598 * The xfer completed _and_ got resubmitted while we 3599 * waited for the lock. Acknowledge the request to 3600 * reschedule, and reschedule it if there is a timeout 3601 * and the bus is not polling. 3602 */ 3603 xfer->ux_timeout_reset = false; 3604 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3605 KASSERT(xfer->ux_timeout_set); 3606 callout_schedule(&xfer->ux_callout, 3607 mstohz(xfer->ux_timeout)); 3608 } else { 3609 /* No more callout or task scheduled. */ 3610 xfer->ux_timeout_set = false; 3611 } 3612 valid = false; 3613 } else if (xfer->ux_status != USBD_IN_PROGRESS) { 3614 /* 3615 * The xfer has completed by hardware completion or by 3616 * software abort, and has not been resubmitted, so the 3617 * timeout must be unset, and is no longer valid for 3618 * the caller. 3619 */ 3620 xfer->ux_timeout_set = false; 3621 valid = false; 3622 } else { 3623 /* 3624 * The xfer has not yet completed, so the timeout is 3625 * valid. 3626 */ 3627 valid = true; 3628 } 3629 3630 /* Any reset must have been processed. */ 3631 KASSERT(!xfer->ux_timeout_reset); 3632 3633 /* 3634 * Either we claim the timeout is set, or the callout is idle. 3635 * If the timeout is still set, we may be handing off to the 3636 * task instead, so this is an if but not an iff. 3637 */ 3638 KASSERT(xfer->ux_timeout_set || !callout_pending(&xfer->ux_callout)); 3639 3640 /* 3641 * The task must be idle now. 3642 * 3643 * - If the caller is the callout, _and_ the timeout is still 3644 * valid, the caller will schedule it, but it hasn't been 3645 * scheduled yet. (If the timeout is not valid, the task 3646 * should not be scheduled.) 3647 * 3648 * - If the caller is the task, it cannot be scheduled again 3649 * until the callout runs again, which won't happen until we 3650 * next release the lock. 3651 */ 3652 KASSERT(!usb_task_pending(xfer->ux_pipe->up_dev, &xfer->ux_aborttask)); 3653 3654 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3655 3656 return valid; 3657 } 3658 3659 /* 3660 * ehci_schedule_timeout(xfer) 3661 * 3662 * Ensure that xfer has a timeout. If the callout is already 3663 * queued or the task is already running, request that they 3664 * reschedule the callout. If not, and if we're not polling, 3665 * schedule the callout anew. 3666 */ 3667 Static void 3668 ehci_schedule_timeout(struct usbd_xfer *xfer) 3669 { 3670 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3671 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3672 3673 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3674 3675 if (xfer->ux_timeout_set) { 3676 /* 3677 * Callout or task has fired from a prior completed 3678 * xfer but has not yet noticed that the xfer is done. 3679 * Ask it to reschedule itself to ux_timeout. 3680 */ 3681 xfer->ux_timeout_reset = true; 3682 } else if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3683 /* Callout is not scheduled. Schedule it. */ 3684 KASSERT(!callout_pending(&xfer->ux_callout)); 3685 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3686 ehci_timeout, xfer); 3687 xfer->ux_timeout_set = true; 3688 } 3689 3690 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3691 } 3692 3693 /* 3694 * ehci_cancel_timeout_async(xfer) 3695 * 3696 * Cancel the callout and the task of xfer, which have not yet run 3697 * to completion, but don't wait for the callout or task to finish 3698 * running. 3699 * 3700 * If they have already fired, at worst they are waiting for the 3701 * bus lock. They will see that the xfer is no longer in progress 3702 * and give up, or they will see that the xfer has been 3703 * resubmitted with a new timeout and reschedule the callout. 3704 * 3705 * If a resubmitted request completed so fast that the callout 3706 * didn't have time to process a timer reset, just cancel the 3707 * timer reset. 3708 */ 3709 Static void 3710 ehci_cancel_timeout_async(struct usbd_xfer *xfer) 3711 { 3712 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3713 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 3714 3715 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3716 3717 KASSERT(xfer->ux_timeout_set); 3718 xfer->ux_timeout_reset = false; 3719 if (!callout_stop(&xfer->ux_callout)) { 3720 /* 3721 * We stopped the callout before it ran. The timeout 3722 * is no longer set. 3723 */ 3724 xfer->ux_timeout_set = false; 3725 } else if (callout_invoking(&xfer->ux_callout)) { 3726 /* 3727 * The callout has begun to run but it has not yet 3728 * acquired the lock and called callout_ack. The task 3729 * cannot be queued yet, and the callout cannot have 3730 * been rescheduled yet. 3731 * 3732 * By the time the callout acquires the lock, we will 3733 * have transitioned from USBD_IN_PROGRESS to a 3734 * completed status, and possibly also resubmitted the 3735 * xfer and set xfer->ux_timeout_reset = true. In both 3736 * cases, the callout will DTRT, so no further action 3737 * is needed here. 3738 */ 3739 } else if (usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask)) { 3740 /* 3741 * The callout had fired and scheduled the task, but we 3742 * stopped the task before it could run. The timeout 3743 * is therefore no longer set -- the next resubmission 3744 * of the xfer must schedule a new timeout. 3745 * 3746 * The callout should not be be pending at this point: 3747 * it is scheduled only under the lock, and only when 3748 * xfer->ux_timeout_set is false, or by the callout or 3749 * task itself when xfer->ux_timeout_reset is true. 3750 */ 3751 xfer->ux_timeout_set = false; 3752 } 3753 3754 /* 3755 * The callout cannot be scheduled and the task cannot be 3756 * queued at this point. Either we cancelled them, or they are 3757 * already running and waiting for the bus lock. 3758 */ 3759 KASSERT(!callout_pending(&xfer->ux_callout)); 3760 KASSERT(!usb_task_pending(xfer->ux_pipe->up_dev, &xfer->ux_aborttask)); 3761 3762 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3763 } 3764 3765 /************************/ 3766 3767 Static int 3768 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3769 { 3770 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3771 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3772 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3773 usb_device_request_t *req = &xfer->ux_request; 3774 ehci_soft_qtd_t *setup, *status, *next; 3775 int isread = req->bmRequestType & UT_READ; 3776 int len = xfer->ux_bufsize; 3777 int err; 3778 3779 exfer->ex_type = EX_CTRL; 3780 exfer->ex_status = NULL; 3781 exfer->ex_data = NULL; 3782 exfer->ex_setup = ehci_alloc_sqtd(sc); 3783 if (exfer->ex_setup == NULL) { 3784 err = ENOMEM; 3785 goto bad1; 3786 } 3787 exfer->ex_status = ehci_alloc_sqtd(sc); 3788 if (exfer->ex_status == NULL) { 3789 err = ENOMEM; 3790 goto bad2; 3791 } 3792 setup = exfer->ex_setup; 3793 status = exfer->ex_status; 3794 exfer->ex_nsqtd = 0; 3795 next = status; 3796 /* Set up data transaction */ 3797 if (len != 0) { 3798 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3799 &exfer->ex_data); 3800 if (err) 3801 goto bad3; 3802 next = exfer->ex_data; 3803 } 3804 3805 /* Clear toggle */ 3806 setup->qtd.qtd_status = htole32( 3807 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3808 EHCI_QTD_SET_TOGGLE(0) | 3809 EHCI_QTD_SET_BYTES(sizeof(*req)) 3810 ); 3811 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3812 setup->qtd.qtd_buffer_hi[0] = 0; 3813 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3814 setup->nextqtd = next; 3815 setup->xfer = xfer; 3816 setup->len = sizeof(*req); 3817 3818 status->qtd.qtd_status = htole32( 3819 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3820 EHCI_QTD_SET_TOGGLE(1) | 3821 EHCI_QTD_IOC 3822 ); 3823 status->qtd.qtd_buffer[0] = 0; 3824 status->qtd.qtd_buffer_hi[0] = 0; 3825 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3826 status->nextqtd = NULL; 3827 status->xfer = xfer; 3828 status->len = 0; 3829 3830 return 0; 3831 bad3: 3832 ehci_free_sqtd(sc, exfer->ex_status); 3833 bad2: 3834 ehci_free_sqtd(sc, exfer->ex_setup); 3835 bad1: 3836 return err; 3837 } 3838 3839 Static void 3840 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3841 { 3842 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3843 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3844 3845 KASSERT(ex->ex_type == EX_CTRL); 3846 3847 ehci_free_sqtd(sc, ex->ex_setup); 3848 ehci_free_sqtd(sc, ex->ex_status); 3849 ehci_free_sqtds(sc, ex); 3850 if (ex->ex_nsqtd) 3851 kmem_free(ex->ex_sqtds, 3852 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3853 } 3854 3855 Static usbd_status 3856 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3857 { 3858 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3859 usbd_status err; 3860 3861 /* Insert last in queue. */ 3862 mutex_enter(&sc->sc_lock); 3863 err = usb_insert_transfer(xfer); 3864 mutex_exit(&sc->sc_lock); 3865 if (err) 3866 return err; 3867 3868 /* Pipe isn't running, start first */ 3869 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3870 } 3871 3872 Static usbd_status 3873 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3874 { 3875 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3876 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3877 usb_device_request_t *req = &xfer->ux_request; 3878 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3879 ehci_soft_qtd_t *setup, *status, *next; 3880 ehci_soft_qh_t *sqh; 3881 const bool polling = sc->sc_bus.ub_usepolling; 3882 3883 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3884 3885 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3886 3887 if (sc->sc_dying) 3888 return USBD_IOERROR; 3889 3890 const int isread = req->bmRequestType & UT_READ; 3891 const int len = UGETW(req->wLength); 3892 3893 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3894 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3895 UGETW(req->wIndex)); 3896 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3897 len, epipe->pipe.up_dev->ud_addr, 3898 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3899 3900 sqh = epipe->sqh; 3901 3902 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3903 "address QH %" __PRIuBIT " pipe %d\n", 3904 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3905 epipe->pipe.up_dev->ud_addr); 3906 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3907 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3908 "MPS QH %" __PRIuBIT " pipe %d\n", 3909 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3910 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3911 3912 setup = exfer->ex_setup; 3913 status = exfer->ex_status; 3914 3915 DPRINTF("setup %#jx status %#jx data %#jx", 3916 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3917 KASSERTMSG(setup != NULL && status != NULL, 3918 "Failed memory allocation, setup %p status %p", 3919 setup, status); 3920 3921 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3922 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3923 3924 /* Clear toggle */ 3925 setup->qtd.qtd_status &= ~htole32( 3926 EHCI_QTD_STATUS_MASK | 3927 EHCI_QTD_BYTES_MASK | 3928 EHCI_QTD_TOGGLE_MASK | 3929 EHCI_QTD_CERR_MASK 3930 ); 3931 setup->qtd.qtd_status |= htole32( 3932 EHCI_QTD_ACTIVE | 3933 EHCI_QTD_SET_CERR(3) | 3934 EHCI_QTD_SET_TOGGLE(0) | 3935 EHCI_QTD_SET_BYTES(sizeof(*req)) 3936 ); 3937 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3938 setup->qtd.qtd_buffer_hi[0] = 0; 3939 3940 next = status; 3941 status->qtd.qtd_status &= ~htole32( 3942 EHCI_QTD_STATUS_MASK | 3943 EHCI_QTD_PID_MASK | 3944 EHCI_QTD_BYTES_MASK | 3945 EHCI_QTD_TOGGLE_MASK | 3946 EHCI_QTD_CERR_MASK 3947 ); 3948 status->qtd.qtd_status |= htole32( 3949 EHCI_QTD_ACTIVE | 3950 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3951 EHCI_QTD_SET_CERR(3) | 3952 EHCI_QTD_SET_TOGGLE(1) | 3953 EHCI_QTD_SET_BYTES(0) | 3954 EHCI_QTD_IOC 3955 ); 3956 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3957 3958 KASSERT(exfer->ex_isdone); 3959 #ifdef DIAGNOSTIC 3960 exfer->ex_isdone = false; 3961 #endif 3962 3963 /* Set up data transaction */ 3964 if (len != 0) { 3965 ehci_soft_qtd_t *end; 3966 3967 /* Start toggle at 1. */ 3968 int toggle = 1; 3969 next = exfer->ex_data; 3970 KASSERTMSG(next != NULL, "Failed memory allocation"); 3971 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3972 end->nextqtd = status; 3973 end->qtd.qtd_next = end->qtd.qtd_altnext = 3974 htole32(status->physaddr); 3975 3976 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3977 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3978 3979 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3980 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3981 } 3982 3983 setup->nextqtd = next; 3984 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3985 3986 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3987 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3988 3989 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3990 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3991 3992 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3993 3994 #ifdef EHCI_DEBUG 3995 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3996 ehci_dump_sqh(sqh); 3997 ehci_dump_sqtds(setup); 3998 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3999 #endif 4000 4001 if (!polling) 4002 mutex_enter(&sc->sc_lock); 4003 4004 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 4005 ehci_set_qh_qtd(sqh, setup); 4006 ehci_schedule_timeout(xfer); 4007 ehci_add_intr_list(sc, exfer); 4008 xfer->ux_status = USBD_IN_PROGRESS; 4009 if (!polling) 4010 mutex_exit(&sc->sc_lock); 4011 4012 #if 0 4013 #ifdef EHCI_DEBUG 4014 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 4015 // delay(10000); 4016 ehci_dump_regs(sc); 4017 ehci_dump_sqh(sc->sc_async_head); 4018 ehci_dump_sqh(sqh); 4019 ehci_dump_sqtds(setup); 4020 #endif 4021 #endif 4022 4023 return USBD_IN_PROGRESS; 4024 } 4025 4026 Static void 4027 ehci_device_ctrl_done(struct usbd_xfer *xfer) 4028 { 4029 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4030 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4031 usb_device_request_t *req = &xfer->ux_request; 4032 int len = UGETW(req->wLength); 4033 int rd = req->bmRequestType & UT_READ; 4034 4035 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4036 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4037 4038 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4039 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 4040 4041 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 4042 BUS_DMASYNC_POSTWRITE); 4043 if (len) 4044 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4045 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4046 4047 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4048 } 4049 4050 /* Abort a device control request. */ 4051 Static void 4052 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 4053 { 4054 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4055 4056 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4057 ehci_abort_xfer(xfer, USBD_CANCELLED); 4058 } 4059 4060 /* Close a device control pipe. */ 4061 Static void 4062 ehci_device_ctrl_close(struct usbd_pipe *pipe) 4063 { 4064 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4065 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 4066 4067 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4068 4069 KASSERT(mutex_owned(&sc->sc_lock)); 4070 4071 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4072 4073 ehci_close_pipe(pipe, sc->sc_async_head); 4074 } 4075 4076 /* 4077 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 4078 * qTD status, or miss signalling occasionally under heavy load. If the host 4079 * machine is too fast, we we can miss transaction completion - when we scan 4080 * the active list the transaction still seems to be active. This generally 4081 * exhibits itself as a umass stall that never recovers. 4082 * 4083 * We work around this behaviour by setting up this callback after any softintr 4084 * that completes with transactions still pending, giving us another chance to 4085 * check for completion after the writeback has taken place. 4086 */ 4087 Static void 4088 ehci_intrlist_timeout(void *arg) 4089 { 4090 ehci_softc_t *sc = arg; 4091 4092 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4093 4094 usb_schedsoftintr(&sc->sc_bus); 4095 } 4096 4097 /************************/ 4098 4099 Static int 4100 ehci_device_bulk_init(struct usbd_xfer *xfer) 4101 { 4102 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4103 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4104 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4105 int endpt = ed->bEndpointAddress; 4106 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4107 int len = xfer->ux_bufsize; 4108 int err = 0; 4109 4110 exfer->ex_type = EX_BULK; 4111 exfer->ex_nsqtd = 0; 4112 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4113 &exfer->ex_sqtdstart); 4114 4115 return err; 4116 } 4117 4118 Static void 4119 ehci_device_bulk_fini(struct usbd_xfer *xfer) 4120 { 4121 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4122 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4123 4124 KASSERT(ex->ex_type == EX_BULK); 4125 4126 ehci_free_sqtds(sc, ex); 4127 if (ex->ex_nsqtd) 4128 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4129 } 4130 4131 Static usbd_status 4132 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 4133 { 4134 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4135 usbd_status err; 4136 4137 /* Insert last in queue. */ 4138 mutex_enter(&sc->sc_lock); 4139 err = usb_insert_transfer(xfer); 4140 mutex_exit(&sc->sc_lock); 4141 if (err) 4142 return err; 4143 4144 /* Pipe isn't running, start first */ 4145 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4146 } 4147 4148 Static usbd_status 4149 ehci_device_bulk_start(struct usbd_xfer *xfer) 4150 { 4151 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4152 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4153 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4154 ehci_soft_qh_t *sqh; 4155 ehci_soft_qtd_t *end; 4156 int len, isread, endpt; 4157 const bool polling = sc->sc_bus.ub_usepolling; 4158 4159 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4160 4161 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4162 xfer->ux_flags, 0); 4163 4164 if (sc->sc_dying) 4165 return USBD_IOERROR; 4166 4167 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4168 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4169 4170 len = xfer->ux_length; 4171 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4172 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4173 sqh = epipe->sqh; 4174 4175 KASSERT(exfer->ex_isdone); 4176 #ifdef DIAGNOSTIC 4177 exfer->ex_isdone = false; 4178 #endif 4179 4180 /* Take lock here to protect nexttoggle */ 4181 if (!polling) 4182 mutex_enter(&sc->sc_lock); 4183 4184 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4185 4186 exfer->ex_sqtdend = end; 4187 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4188 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4189 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4190 4191 #ifdef EHCI_DEBUG 4192 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4193 ehci_dump_sqh(sqh); 4194 ehci_dump_sqtds(exfer->ex_sqtdstart); 4195 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4196 #endif 4197 4198 if (xfer->ux_length) 4199 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4200 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4201 4202 /* also does usb_syncmem(sqh) */ 4203 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4204 ehci_schedule_timeout(xfer); 4205 ehci_add_intr_list(sc, exfer); 4206 xfer->ux_status = USBD_IN_PROGRESS; 4207 if (!polling) 4208 mutex_exit(&sc->sc_lock); 4209 4210 #if 0 4211 #ifdef EHCI_DEBUG 4212 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4213 // delay(10000); 4214 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4215 ehci_dump_regs(sc); 4216 #if 0 4217 printf("async_head:\n"); 4218 ehci_dump_sqh(sc->sc_async_head); 4219 #endif 4220 DPRINTF("sqh:", 0, 0, 0, 0); 4221 ehci_dump_sqh(sqh); 4222 ehci_dump_sqtds(exfer->ex_sqtdstart); 4223 #endif 4224 #endif 4225 4226 return USBD_IN_PROGRESS; 4227 } 4228 4229 Static void 4230 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4231 { 4232 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4233 4234 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 4235 ehci_abort_xfer(xfer, USBD_CANCELLED); 4236 } 4237 4238 /* 4239 * Close a device bulk pipe. 4240 */ 4241 Static void 4242 ehci_device_bulk_close(struct usbd_pipe *pipe) 4243 { 4244 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4245 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4246 4247 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4248 4249 KASSERT(mutex_owned(&sc->sc_lock)); 4250 4251 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4252 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4253 ehci_close_pipe(pipe, sc->sc_async_head); 4254 } 4255 4256 Static void 4257 ehci_device_bulk_done(struct usbd_xfer *xfer) 4258 { 4259 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4260 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4261 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4262 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4263 4264 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4265 4266 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4267 4268 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4269 4270 if (xfer->ux_length) 4271 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4272 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4273 4274 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4275 } 4276 4277 /************************/ 4278 4279 Static usbd_status 4280 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4281 { 4282 struct ehci_soft_islot *isp; 4283 int islot, lev; 4284 4285 /* Find a poll rate that is large enough. */ 4286 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4287 if (EHCI_ILEV_IVAL(lev) <= ival) 4288 break; 4289 4290 /* Pick an interrupt slot at the right level. */ 4291 /* XXX could do better than picking at random */ 4292 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4293 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4294 4295 sqh->islot = islot; 4296 isp = &sc->sc_islots[islot]; 4297 mutex_enter(&sc->sc_lock); 4298 ehci_add_qh(sc, sqh, isp->sqh); 4299 mutex_exit(&sc->sc_lock); 4300 4301 return USBD_NORMAL_COMPLETION; 4302 } 4303 4304 Static int 4305 ehci_device_intr_init(struct usbd_xfer *xfer) 4306 { 4307 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4308 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4309 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4310 int endpt = ed->bEndpointAddress; 4311 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4312 int len = xfer->ux_bufsize; 4313 int err; 4314 4315 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4316 4317 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4318 xfer->ux_flags, 0); 4319 4320 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4321 KASSERT(len != 0); 4322 4323 exfer->ex_type = EX_INTR; 4324 exfer->ex_nsqtd = 0; 4325 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4326 &exfer->ex_sqtdstart); 4327 4328 return err; 4329 } 4330 4331 Static void 4332 ehci_device_intr_fini(struct usbd_xfer *xfer) 4333 { 4334 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4335 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4336 4337 KASSERT(ex->ex_type == EX_INTR); 4338 4339 ehci_free_sqtds(sc, ex); 4340 if (ex->ex_nsqtd) 4341 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4342 } 4343 4344 Static usbd_status 4345 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4346 { 4347 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4348 usbd_status err; 4349 4350 /* Insert last in queue. */ 4351 mutex_enter(&sc->sc_lock); 4352 err = usb_insert_transfer(xfer); 4353 mutex_exit(&sc->sc_lock); 4354 if (err) 4355 return err; 4356 4357 /* 4358 * Pipe isn't running (otherwise err would be USBD_INPROG), 4359 * so start it first. 4360 */ 4361 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4362 } 4363 4364 Static usbd_status 4365 ehci_device_intr_start(struct usbd_xfer *xfer) 4366 { 4367 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4368 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4369 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4370 ehci_soft_qtd_t *end; 4371 ehci_soft_qh_t *sqh; 4372 int len, isread, endpt; 4373 const bool polling = sc->sc_bus.ub_usepolling; 4374 4375 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4376 4377 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4378 xfer->ux_flags, 0); 4379 4380 if (sc->sc_dying) 4381 return USBD_IOERROR; 4382 4383 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4384 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4385 4386 len = xfer->ux_length; 4387 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4388 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4389 sqh = epipe->sqh; 4390 4391 KASSERT(exfer->ex_isdone); 4392 #ifdef DIAGNOSTIC 4393 exfer->ex_isdone = false; 4394 #endif 4395 4396 /* Take lock to protect nexttoggle */ 4397 if (!polling) 4398 mutex_enter(&sc->sc_lock); 4399 4400 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4401 4402 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4403 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4404 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4405 exfer->ex_sqtdend = end; 4406 4407 #ifdef EHCI_DEBUG 4408 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4409 ehci_dump_sqh(sqh); 4410 ehci_dump_sqtds(exfer->ex_sqtdstart); 4411 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4412 #endif 4413 4414 if (xfer->ux_length) 4415 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4416 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4417 4418 /* also does usb_syncmem(sqh) */ 4419 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4420 ehci_schedule_timeout(xfer); 4421 ehci_add_intr_list(sc, exfer); 4422 xfer->ux_status = USBD_IN_PROGRESS; 4423 if (!polling) 4424 mutex_exit(&sc->sc_lock); 4425 4426 #if 0 4427 #ifdef EHCI_DEBUG 4428 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4429 // delay(10000); 4430 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4431 ehci_dump_regs(sc); 4432 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4433 ehci_dump_sqh(sqh); 4434 ehci_dump_sqtds(exfer->ex_sqtdstart); 4435 #endif 4436 #endif 4437 4438 return USBD_IN_PROGRESS; 4439 } 4440 4441 Static void 4442 ehci_device_intr_abort(struct usbd_xfer *xfer) 4443 { 4444 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4445 4446 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4447 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4448 4449 /* 4450 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4451 * async doorbell. That's dependent on the async list, wheras 4452 * intr xfers are periodic, should not use this? 4453 */ 4454 ehci_abort_xfer(xfer, USBD_CANCELLED); 4455 } 4456 4457 Static void 4458 ehci_device_intr_close(struct usbd_pipe *pipe) 4459 { 4460 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4461 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4462 struct ehci_soft_islot *isp; 4463 4464 KASSERT(mutex_owned(&sc->sc_lock)); 4465 4466 isp = &sc->sc_islots[epipe->sqh->islot]; 4467 ehci_close_pipe(pipe, isp->sqh); 4468 } 4469 4470 Static void 4471 ehci_device_intr_done(struct usbd_xfer *xfer) 4472 { 4473 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4474 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4475 4476 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4477 4478 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4479 4480 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4481 4482 if (xfer->ux_length) { 4483 int isread, endpt; 4484 4485 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4486 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4487 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4488 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4489 } 4490 } 4491 4492 /************************/ 4493 Static int 4494 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4495 { 4496 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4497 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4498 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4499 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4500 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4501 int i, k, frames; 4502 u_int huba, dir; 4503 int err; 4504 4505 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4506 4507 start = NULL; 4508 sitd = NULL; 4509 4510 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4511 xfer->ux_flags, 0); 4512 4513 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4514 KASSERT(xfer->ux_nframes != 0); 4515 KASSERT(exfer->ex_isdone); 4516 4517 exfer->ex_type = EX_FS_ISOC; 4518 /* 4519 * Step 1: Allocate and initialize sitds. 4520 */ 4521 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4522 if (i > 16 || i == 0) { 4523 /* Spec page 271 says intervals > 16 are invalid */ 4524 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4525 4526 return EINVAL; 4527 } 4528 4529 frames = xfer->ux_nframes; 4530 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4531 sitd = ehci_alloc_sitd(sc); 4532 if (sitd == NULL) { 4533 err = ENOMEM; 4534 goto fail; 4535 } 4536 4537 if (prev) 4538 prev->xfer_next = sitd; 4539 else 4540 start = sitd; 4541 4542 huba = dev->ud_myhsport->up_parent->ud_addr; 4543 4544 #if 0 4545 if (sc->sc_flags & EHCIF_FREESCALE) { 4546 // Set hub address to 0 if embedded TT is used. 4547 if (huba == sc->sc_addr) 4548 huba = 0; 4549 } 4550 #endif 4551 4552 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4553 dir = UE_GET_DIR(k) ? 1 : 0; 4554 sitd->sitd.sitd_endp = 4555 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4556 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4557 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4558 EHCI_SITD_SET_HUBA(huba) | 4559 EHCI_SITD_SET_DIR(dir)); 4560 4561 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4562 } /* End of frame */ 4563 4564 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4565 4566 stop = sitd; 4567 stop->xfer_next = NULL; 4568 exfer->ex_sitdstart = start; 4569 exfer->ex_sitdend = stop; 4570 4571 return 0; 4572 4573 fail: 4574 mutex_enter(&sc->sc_lock); 4575 ehci_soft_sitd_t *next; 4576 for (sitd = start; sitd; sitd = next) { 4577 next = sitd->xfer_next; 4578 ehci_free_sitd_locked(sc, sitd); 4579 } 4580 mutex_exit(&sc->sc_lock); 4581 4582 return err; 4583 } 4584 4585 Static void 4586 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4587 { 4588 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4589 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4590 4591 KASSERT(ex->ex_type == EX_FS_ISOC); 4592 4593 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4594 } 4595 4596 Static usbd_status 4597 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4598 { 4599 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4600 usbd_status __diagused err; 4601 4602 mutex_enter(&sc->sc_lock); 4603 err = usb_insert_transfer(xfer); 4604 mutex_exit(&sc->sc_lock); 4605 4606 KASSERT(err == USBD_NORMAL_COMPLETION); 4607 4608 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4609 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4610 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4611 ehci_soft_sitd_t *sitd; 4612 usb_dma_t *dma_buf; 4613 int i, j, k, frames; 4614 int offs, total_length; 4615 int frindex; 4616 u_int dir; 4617 4618 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4619 4620 sitd = NULL; 4621 total_length = 0; 4622 4623 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4624 xfer->ux_flags, 0); 4625 4626 if (sc->sc_dying) 4627 return USBD_IOERROR; 4628 4629 /* 4630 * To avoid complication, don't allow a request right now that'll span 4631 * the entire frame table. To within 4 frames, to allow some leeway 4632 * on either side of where the hc currently is. 4633 */ 4634 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4635 xfer->ux_nframes >= sc->sc_flsize - 4) { 4636 printf("ehci: isoc descriptor requested that spans the entire" 4637 "frametable, too many frames\n"); 4638 return USBD_INVAL; 4639 } 4640 4641 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4642 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4643 KASSERT(exfer->ex_isdone); 4644 #ifdef DIAGNOSTIC 4645 exfer->ex_isdone = false; 4646 #endif 4647 4648 /* 4649 * Step 1: Initialize sitds. 4650 */ 4651 4652 frames = xfer->ux_nframes; 4653 dma_buf = &xfer->ux_dmabuf; 4654 offs = 0; 4655 4656 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4657 i++, sitd = sitd->xfer_next) { 4658 KASSERT(sitd != NULL); 4659 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4660 4661 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4662 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4663 4664 /* Set page0 index and offset - TP and T-offset are set below */ 4665 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4666 4667 total_length += xfer->ux_frlengths[i]; 4668 offs += xfer->ux_frlengths[i]; 4669 4670 sitd->sitd.sitd_buffer[1] = 4671 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4672 4673 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4674 4675 #if 0 4676 if (sc->sc_flags & EHCIF_FREESCALE) { 4677 // Set hub address to 0 if embedded TT is used. 4678 if (huba == sc->sc_addr) 4679 huba = 0; 4680 } 4681 #endif 4682 4683 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4684 dir = UE_GET_DIR(k) ? 1 : 0; 4685 KASSERT(sitd->sitd.sitd_endp == htole32( 4686 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4687 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4688 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4689 EHCI_SITD_SET_HUBA(huba) | 4690 EHCI_SITD_SET_DIR(dir))); 4691 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4692 4693 uint8_t sa = 0; 4694 uint8_t sb = 0; 4695 u_int temp, tlen; 4696 4697 if (dir == 0) { /* OUT */ 4698 temp = 0; 4699 tlen = xfer->ux_frlengths[i]; 4700 if (tlen <= 188) { 4701 temp |= 1; /* T-count = 1, TP = ALL */ 4702 tlen = 1; 4703 } else { 4704 tlen += 187; 4705 tlen /= 188; 4706 temp |= tlen; /* T-count = [1..6] */ 4707 temp |= 8; /* TP = Begin */ 4708 } 4709 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4710 4711 tlen += sa; 4712 4713 if (tlen >= 8) { 4714 sb = 0; 4715 } else { 4716 sb = (1 << tlen); 4717 } 4718 4719 sa = (1 << sa); 4720 sa = (sb - sa) & 0x3F; 4721 sb = 0; 4722 } else { 4723 sb = (-(4 << sa)) & 0xFE; 4724 sa = (1 << sa) & 0x3F; 4725 sa = 0x01; 4726 sb = 0xfc; 4727 } 4728 4729 sitd->sitd.sitd_sched = htole32( 4730 EHCI_SITD_SET_SMASK(sa) | 4731 EHCI_SITD_SET_CMASK(sb) 4732 ); 4733 4734 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4735 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4736 } /* End of frame */ 4737 4738 sitd = exfer->ex_sitdend; 4739 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4740 4741 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4742 sizeof(sitd->sitd.sitd_trans), 4743 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4744 4745 if (total_length) 4746 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4748 4749 /* 4750 * Part 2: Transfer descriptors have now been set up, now they must 4751 * be scheduled into the periodic frame list. Erk. Not wanting to 4752 * complicate matters, transfer is denied if the transfer spans 4753 * more than the period frame list. 4754 */ 4755 4756 mutex_enter(&sc->sc_lock); 4757 4758 /* Start inserting frames */ 4759 if (epipe->isoc.cur_xfers > 0) { 4760 frindex = epipe->isoc.next_frame; 4761 } else { 4762 frindex = EOREAD4(sc, EHCI_FRINDEX); 4763 frindex = frindex >> 3; /* Erase microframe index */ 4764 frindex += 2; 4765 } 4766 4767 if (frindex >= sc->sc_flsize) 4768 frindex &= (sc->sc_flsize - 1); 4769 4770 /* Whats the frame interval? */ 4771 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4772 4773 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4774 j++, sitd = sitd->xfer_next) { 4775 KASSERT(sitd); 4776 4777 usb_syncmem(&sc->sc_fldma, 4778 sizeof(ehci_link_t) * frindex, 4779 sizeof(ehci_link_t), 4780 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4781 4782 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4783 if (sitd->sitd.sitd_next == 0) 4784 /* 4785 * FIXME: frindex table gets initialized to NULL 4786 * or EHCI_NULL? 4787 */ 4788 sitd->sitd.sitd_next = EHCI_NULL; 4789 4790 usb_syncmem(&sitd->dma, 4791 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4792 sizeof(ehci_sitd_t), 4793 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4794 4795 sc->sc_flist[frindex] = 4796 htole32(EHCI_LINK_SITD | sitd->physaddr); 4797 4798 usb_syncmem(&sc->sc_fldma, 4799 sizeof(ehci_link_t) * frindex, 4800 sizeof(ehci_link_t), 4801 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4802 4803 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4804 sc->sc_softsitds[frindex] = sitd; 4805 if (sitd->frame_list.next != NULL) 4806 sitd->frame_list.next->frame_list.prev = sitd; 4807 sitd->slot = frindex; 4808 sitd->frame_list.prev = NULL; 4809 4810 frindex += i; 4811 if (frindex >= sc->sc_flsize) 4812 frindex -= sc->sc_flsize; 4813 } 4814 4815 epipe->isoc.cur_xfers++; 4816 epipe->isoc.next_frame = frindex; 4817 4818 ehci_add_intr_list(sc, exfer); 4819 xfer->ux_status = USBD_IN_PROGRESS; 4820 mutex_exit(&sc->sc_lock); 4821 4822 return USBD_IN_PROGRESS; 4823 } 4824 4825 Static void 4826 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4827 { 4828 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4829 4830 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4831 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4832 } 4833 4834 Static void 4835 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4836 { 4837 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4838 4839 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4840 } 4841 4842 Static void 4843 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4844 { 4845 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4846 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4847 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4848 4849 KASSERT(mutex_owned(&sc->sc_lock)); 4850 4851 epipe->isoc.cur_xfers--; 4852 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4853 4854 if (xfer->ux_length) 4855 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4856 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4857 } 4858 4859 /* -------------------------------------------------------------------------- */ 4860 4861 Static int 4862 ehci_device_isoc_init(struct usbd_xfer *xfer) 4863 { 4864 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4865 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4866 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4867 ehci_soft_itd_t *itd, *prev, *start, *stop; 4868 int i, j, k; 4869 int frames, ufrperframe; 4870 int err; 4871 4872 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4873 4874 start = NULL; 4875 prev = NULL; 4876 itd = NULL; 4877 4878 KASSERT(xfer->ux_nframes != 0); 4879 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4880 KASSERT(exfer->ex_isdone); 4881 4882 exfer->ex_type = EX_ISOC; 4883 4884 /* 4885 * Step 1: Allocate and initialize itds, how many do we need? 4886 * One per transfer if interval >= 8 microframes, less if we use 4887 * multiple microframes per frame. 4888 */ 4889 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4890 if (i > 16 || i == 0) { 4891 /* Spec page 271 says intervals > 16 are invalid */ 4892 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4893 return USBD_INVAL; 4894 } 4895 4896 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4897 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4898 4899 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4900 itd = ehci_alloc_itd(sc); 4901 if (itd == NULL) { 4902 err = ENOMEM; 4903 goto fail; 4904 } 4905 4906 if (prev != NULL) { 4907 /* Maybe not as it's updated by the scheduling? */ 4908 prev->itd.itd_next = 4909 htole32(itd->physaddr | EHCI_LINK_ITD); 4910 4911 prev->xfer_next = itd; 4912 } else { 4913 start = itd; 4914 } 4915 4916 /* 4917 * Other special values 4918 */ 4919 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4920 itd->itd.itd_bufr[0] = htole32( 4921 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4922 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4923 4924 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4925 ? 1 : 0; 4926 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4927 itd->itd.itd_bufr[1] |= htole32( 4928 EHCI_ITD_SET_DIR(k) | 4929 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4930 4931 /* FIXME: handle invalid trans - should be done in openpipe */ 4932 itd->itd.itd_bufr[2] |= 4933 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4934 } /* End of frame */ 4935 4936 stop = itd; 4937 stop->xfer_next = NULL; 4938 4939 exfer->ex_itdstart = start; 4940 exfer->ex_itdend = stop; 4941 4942 return 0; 4943 fail: 4944 mutex_enter(&sc->sc_lock); 4945 ehci_soft_itd_t *next; 4946 for (itd = start; itd; itd = next) { 4947 next = itd->xfer_next; 4948 ehci_free_itd_locked(sc, itd); 4949 } 4950 mutex_exit(&sc->sc_lock); 4951 4952 return err; 4953 4954 } 4955 4956 Static void 4957 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4958 { 4959 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4960 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4961 4962 KASSERT(ex->ex_type == EX_ISOC); 4963 4964 ehci_free_itd_chain(sc, ex->ex_itdstart); 4965 } 4966 4967 Static usbd_status 4968 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4969 { 4970 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4971 usbd_status __diagused err; 4972 4973 mutex_enter(&sc->sc_lock); 4974 err = usb_insert_transfer(xfer); 4975 mutex_exit(&sc->sc_lock); 4976 4977 KASSERT(err == USBD_NORMAL_COMPLETION); 4978 4979 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4980 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4981 ehci_soft_itd_t *itd, *prev; 4982 usb_dma_t *dma_buf; 4983 int i, j; 4984 int frames, uframes, ufrperframe; 4985 int trans_count, offs, total_length; 4986 int frindex; 4987 4988 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4989 4990 prev = NULL; 4991 itd = NULL; 4992 trans_count = 0; 4993 total_length = 0; 4994 4995 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4996 4997 if (sc->sc_dying) 4998 return USBD_IOERROR; 4999 5000 /* 5001 * To avoid complication, don't allow a request right now that'll span 5002 * the entire frame table. To within 4 frames, to allow some leeway 5003 * on either side of where the hc currently is. 5004 */ 5005 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 5006 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 5007 DPRINTF( 5008 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 5009 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 5010 return USBD_INVAL; 5011 } 5012 5013 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 5014 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 5015 KASSERT(exfer->ex_isdone); 5016 #ifdef DIAGNOSTIC 5017 exfer->ex_isdone = false; 5018 #endif 5019 5020 /* 5021 * Step 1: Re-Initialize itds 5022 */ 5023 5024 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 5025 if (i > 16 || i == 0) { 5026 /* Spec page 271 says intervals > 16 are invalid */ 5027 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 5028 return USBD_INVAL; 5029 } 5030 5031 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 5032 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 5033 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 5034 5035 if (frames == 0) { 5036 DPRINTF("frames == 0", 0, 0, 0, 0); 5037 return USBD_INVAL; 5038 } 5039 5040 dma_buf = &xfer->ux_dmabuf; 5041 offs = 0; 5042 5043 itd = exfer->ex_itdstart; 5044 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 5045 int froffs = offs; 5046 5047 if (prev != NULL) { 5048 prev->itd.itd_next = 5049 htole32(itd->physaddr | EHCI_LINK_ITD); 5050 usb_syncmem(&prev->dma, 5051 prev->offs + offsetof(ehci_itd_t, itd_next), 5052 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 5053 prev->xfer_next = itd; 5054 } 5055 5056 /* 5057 * Step 1.5, initialize uframes 5058 */ 5059 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 5060 /* Calculate which page in the list this starts in */ 5061 int addr = DMAADDR(dma_buf, froffs); 5062 addr = EHCI_PAGE_OFFSET(addr); 5063 addr += (offs - froffs); 5064 addr = EHCI_PAGE(addr); 5065 addr /= EHCI_PAGE_SIZE; 5066 5067 /* 5068 * This gets the initial offset into the first page, 5069 * looks how far further along the current uframe 5070 * offset is. Works out how many pages that is. 5071 */ 5072 5073 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 5074 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 5075 EHCI_ITD_SET_PG(addr) | 5076 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 5077 5078 total_length += xfer->ux_frlengths[trans_count]; 5079 offs += xfer->ux_frlengths[trans_count]; 5080 trans_count++; 5081 5082 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 5083 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 5084 break; 5085 } 5086 } 5087 5088 /* 5089 * Step 1.75, set buffer pointers. To simplify matters, all 5090 * pointers are filled out for the next 7 hardware pages in 5091 * the dma block, so no need to worry what pages to cover 5092 * and what to not. 5093 */ 5094 5095 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 5096 /* 5097 * Don't try to lookup a page that's past the end 5098 * of buffer 5099 */ 5100 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 5101 if (page_offs >= dma_buf->udma_block->size) 5102 break; 5103 5104 uint64_t page = DMAADDR(dma_buf, page_offs); 5105 page = EHCI_PAGE(page); 5106 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 5107 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 5108 } 5109 /* 5110 * Other special values 5111 */ 5112 5113 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 5114 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 5115 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 5116 5117 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 5118 ? 1 : 0; 5119 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 5120 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 5121 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 5122 5123 /* FIXME: handle invalid trans */ 5124 itd->itd.itd_bufr[2] |= 5125 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 5126 5127 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 5128 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5129 5130 prev = itd; 5131 } /* End of frame */ 5132 5133 if (total_length) 5134 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 5135 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5136 5137 /* 5138 * Part 2: Transfer descriptors have now been set up, now they must 5139 * be scheduled into the period frame list. Erk. Not wanting to 5140 * complicate matters, transfer is denied if the transfer spans 5141 * more than the period frame list. 5142 */ 5143 5144 mutex_enter(&sc->sc_lock); 5145 5146 /* Start inserting frames */ 5147 if (epipe->isoc.cur_xfers > 0) { 5148 frindex = epipe->isoc.next_frame; 5149 } else { 5150 frindex = EOREAD4(sc, EHCI_FRINDEX); 5151 frindex = frindex >> 3; /* Erase microframe index */ 5152 frindex += 2; 5153 } 5154 5155 if (frindex >= sc->sc_flsize) 5156 frindex &= (sc->sc_flsize - 1); 5157 5158 /* What's the frame interval? */ 5159 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 5160 if (i / USB_UFRAMES_PER_FRAME == 0) 5161 i = 1; 5162 else 5163 i /= USB_UFRAMES_PER_FRAME; 5164 5165 itd = exfer->ex_itdstart; 5166 for (j = 0; j < frames; j++) { 5167 KASSERTMSG(itd != NULL, "frame %d\n", j); 5168 5169 usb_syncmem(&sc->sc_fldma, 5170 sizeof(ehci_link_t) * frindex, 5171 sizeof(ehci_link_t), 5172 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5173 5174 itd->itd.itd_next = sc->sc_flist[frindex]; 5175 if (itd->itd.itd_next == 0) 5176 /* 5177 * FIXME: frindex table gets initialized to NULL 5178 * or EHCI_NULL? 5179 */ 5180 itd->itd.itd_next = EHCI_NULL; 5181 5182 usb_syncmem(&itd->dma, 5183 itd->offs + offsetof(ehci_itd_t, itd_next), 5184 sizeof(itd->itd.itd_next), 5185 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5186 5187 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 5188 5189 usb_syncmem(&sc->sc_fldma, 5190 sizeof(ehci_link_t) * frindex, 5191 sizeof(ehci_link_t), 5192 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 5193 5194 itd->frame_list.next = sc->sc_softitds[frindex]; 5195 sc->sc_softitds[frindex] = itd; 5196 if (itd->frame_list.next != NULL) 5197 itd->frame_list.next->frame_list.prev = itd; 5198 itd->slot = frindex; 5199 itd->frame_list.prev = NULL; 5200 5201 frindex += i; 5202 if (frindex >= sc->sc_flsize) 5203 frindex -= sc->sc_flsize; 5204 5205 itd = itd->xfer_next; 5206 } 5207 5208 epipe->isoc.cur_xfers++; 5209 epipe->isoc.next_frame = frindex; 5210 5211 ehci_add_intr_list(sc, exfer); 5212 xfer->ux_status = USBD_IN_PROGRESS; 5213 mutex_exit(&sc->sc_lock); 5214 5215 return USBD_IN_PROGRESS; 5216 } 5217 5218 Static void 5219 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5220 { 5221 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 5222 5223 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 5224 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5225 } 5226 5227 Static void 5228 ehci_device_isoc_close(struct usbd_pipe *pipe) 5229 { 5230 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 5231 5232 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 5233 } 5234 5235 Static void 5236 ehci_device_isoc_done(struct usbd_xfer *xfer) 5237 { 5238 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5239 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5240 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5241 5242 KASSERT(mutex_owned(&sc->sc_lock)); 5243 5244 epipe->isoc.cur_xfers--; 5245 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5246 if (xfer->ux_length) 5247 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5248 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5249 } 5250
Indexes created Thu Oct 02 01:09:59 GMT 2025