ehci.c revision 1.287
1 /* $NetBSD: ehci.c,v 1.287 2021/12/05 11:05:37 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna.com.au), and 11 * Nick Hudson . 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 37 * 38 * The EHCI 1.0 spec can be found at 39 * http://www.intel.com/technology/usb/spec.htm 40 * and the USB 2.0 spec at 41 * http://www.usb.org/developers/docs/ 42 * 43 */ 44 45 /* 46 * TODO: 47 * 1) hold off explorations by companion controllers until ehci has started. 48 * 49 * 2) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 3) Command failures are not recovered correctly. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.287 2021/12/05 11:05:37 riastradh Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #ifdef _KERNEL_OPT 63 #include "opt_usb.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #include <sys/bus.h> 69 #include <sys/cpu.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/kmem.h> 73 #include <sys/mutex.h> 74 #include <sys/proc.h> 75 #include <sys/queue.h> 76 #include <sys/select.h> 77 #include <sys/sysctl.h> 78 #include <sys/systm.h> 79 #include <sys/reboot.h> 80 81 #include <machine/endian.h> 82 83 #include <dev/usb/usb.h> 84 #include <dev/usb/usbdi.h> 85 #include <dev/usb/usbdivar.h> 86 #include <dev/usb/usbhist.h> 87 #include <dev/usb/usb_mem.h> 88 #include <dev/usb/usb_quirks.h> 89 90 #include <dev/usb/ehcireg.h> 91 #include <dev/usb/ehcivar.h> 92 #include <dev/usb/usbroothub.h> 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 static int ehcidebug = 0; 99 100 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 101 { 102 int err; 103 const struct sysctlnode *rnode; 104 const struct sysctlnode *cnode; 105 106 err = sysctl_createv(clog, 0, NULL, &rnode, 107 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 108 SYSCTL_DESCR("ehci global controls"), 109 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 110 111 if (err) 112 goto fail; 113 114 /* control debugging printfs */ 115 err = sysctl_createv(clog, 0, &rnode, &cnode, 116 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 117 "debug", SYSCTL_DESCR("Enable debugging output"), 118 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 119 if (err) 120 goto fail; 121 122 return; 123 fail: 124 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 125 } 126 127 #endif /* EHCI_DEBUG */ 128 #endif /* USB_DEBUG */ 129 130 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 131 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 132 #define EHCIHIST_FUNC() USBHIST_FUNC() 133 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 134 135 struct ehci_pipe { 136 struct usbd_pipe pipe; 137 int nexttoggle; 138 139 ehci_soft_qh_t *sqh; 140 union { 141 /* Control pipe */ 142 struct { 143 usb_dma_t reqdma; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 u_int length; 148 } intr; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 }; 155 }; 156 157 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 158 159 Static usbd_status ehci_open(struct usbd_pipe *); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_intrlist_timeout(void *); 171 Static void ehci_doorbell(void *); 172 Static void ehci_pcd(void *); 173 174 Static struct usbd_xfer * 175 ehci_allocx(struct usbd_bus *, unsigned int); 176 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 177 178 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 179 Static bool ehci_dying(struct usbd_bus *); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abortx(struct usbd_xfer *); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_abortx = ehci_abortx, 323 .ubm_dying = ehci_dying, 324 .ubm_getlock = ehci_get_lock, 325 .ubm_rhctrl = ehci_roothub_ctrl, 326 }; 327 328 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 329 .upm_transfer = ehci_root_intr_transfer, 330 .upm_start = ehci_root_intr_start, 331 .upm_abort = ehci_root_intr_abort, 332 .upm_close = ehci_root_intr_close, 333 .upm_cleartoggle = ehci_noop, 334 .upm_done = ehci_root_intr_done, 335 }; 336 337 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 338 .upm_init = ehci_device_ctrl_init, 339 .upm_fini = ehci_device_ctrl_fini, 340 .upm_transfer = ehci_device_ctrl_transfer, 341 .upm_start = ehci_device_ctrl_start, 342 .upm_abort = ehci_device_ctrl_abort, 343 .upm_close = ehci_device_ctrl_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_ctrl_done, 346 }; 347 348 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 349 .upm_init = ehci_device_intr_init, 350 .upm_fini = ehci_device_intr_fini, 351 .upm_transfer = ehci_device_intr_transfer, 352 .upm_start = ehci_device_intr_start, 353 .upm_abort = ehci_device_intr_abort, 354 .upm_close = ehci_device_intr_close, 355 .upm_cleartoggle = ehci_device_clear_toggle, 356 .upm_done = ehci_device_intr_done, 357 }; 358 359 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 360 .upm_init = ehci_device_bulk_init, 361 .upm_fini = ehci_device_bulk_fini, 362 .upm_transfer = ehci_device_bulk_transfer, 363 .upm_start = ehci_device_bulk_start, 364 .upm_abort = ehci_device_bulk_abort, 365 .upm_close = ehci_device_bulk_close, 366 .upm_cleartoggle = ehci_device_clear_toggle, 367 .upm_done = ehci_device_bulk_done, 368 }; 369 370 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 371 .upm_init = ehci_device_isoc_init, 372 .upm_fini = ehci_device_isoc_fini, 373 .upm_transfer = ehci_device_isoc_transfer, 374 .upm_abort = ehci_device_isoc_abort, 375 .upm_close = ehci_device_isoc_close, 376 .upm_cleartoggle = ehci_noop, 377 .upm_done = ehci_device_isoc_done, 378 }; 379 380 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 381 .upm_init = ehci_device_fs_isoc_init, 382 .upm_fini = ehci_device_fs_isoc_fini, 383 .upm_transfer = ehci_device_fs_isoc_transfer, 384 .upm_abort = ehci_device_fs_isoc_abort, 385 .upm_close = ehci_device_fs_isoc_close, 386 .upm_cleartoggle = ehci_noop, 387 .upm_done = ehci_device_fs_isoc_done, 388 }; 389 390 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 391 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 392 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 393 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 394 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 395 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 396 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 397 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 398 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 399 }; 400 401 int 402 ehci_init(ehci_softc_t *sc) 403 { 404 uint32_t vers, sparams, cparams, hcr; 405 u_int i; 406 usbd_status err; 407 ehci_soft_qh_t *sqh; 408 u_int ncomp; 409 410 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 411 #ifdef EHCI_DEBUG 412 theehci = sc; 413 #endif 414 415 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 416 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 417 cv_init(&sc->sc_doorbell, "ehcidb"); 418 419 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 420 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 421 422 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 423 ehci_doorbell, sc); 424 KASSERT(sc->sc_doorbell_si != NULL); 425 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 426 ehci_pcd, sc); 427 KASSERT(sc->sc_pcd_si != NULL); 428 429 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 430 431 vers = EREAD2(sc, EHCI_HCIVERSION); 432 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 433 vers >> 8, vers & 0xff); 434 435 sparams = EREAD4(sc, EHCI_HCSPARAMS); 436 DPRINTF("sparams=%#jx", sparams, 0, 0, 0); 437 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 438 ncomp = EHCI_HCS_N_CC(sparams); 439 if (ncomp != sc->sc_ncomp) { 440 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 441 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 442 #if NOHCI == 0 || NUHCI == 0 443 aprint_error("%s: ohci or uhci probably not configured\n", 444 device_xname(sc->sc_dev)); 445 #endif 446 if (ncomp < sc->sc_ncomp) 447 sc->sc_ncomp = ncomp; 448 } 449 if (sc->sc_ncomp > 0) { 450 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 451 aprint_normal_dev(sc->sc_dev, 452 "%d companion controller%s, %d port%s%s", 453 sc->sc_ncomp, 454 sc->sc_ncomp!=1 ? "s" : "", 455 EHCI_HCS_N_PCC(sparams), 456 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 457 sc->sc_ncomp!=1 ? " each" : ""); 458 if (sc->sc_comps[0]) { 459 aprint_normal(":"); 460 for (i = 0; i < sc->sc_ncomp; i++) 461 aprint_normal(" %s", 462 device_xname(sc->sc_comps[i])); 463 } 464 aprint_normal("\n"); 465 466 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 467 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 468 cv_init(&sc->sc_compcv, "ehciccv"); 469 sc->sc_comp_state = CO_EARLY; 470 } 471 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 472 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 473 474 cparams = EREAD4(sc, EHCI_HCCPARAMS); 475 DPRINTF("cparams=%#jx", cparams, 0, 0, 0); 476 477 if (EHCI_HCC_64BIT(cparams)) { 478 /* MUST clear segment register if 64 bit capable. */ 479 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 480 } 481 482 if (cparams & EHCI_HCC_IST_FULLFRAME) { 483 sc->sc_istthreshold = 0; 484 } else { 485 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 486 } 487 488 sc->sc_bus.ub_revision = USBREV_2_0; 489 sc->sc_bus.ub_usedma = true; 490 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 491 492 /* Reset the controller */ 493 DPRINTF("resetting", 0, 0, 0, 0); 494 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 495 usb_delay_ms(&sc->sc_bus, 1); 496 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 497 for (i = 0; i < 100; i++) { 498 usb_delay_ms(&sc->sc_bus, 1); 499 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 500 if (!hcr) 501 break; 502 } 503 if (hcr) { 504 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 505 return EIO; 506 } 507 if (sc->sc_vendor_init) 508 sc->sc_vendor_init(sc); 509 510 /* XXX need proper intr scheduling */ 511 sc->sc_rand = 96; 512 513 /* frame list size at default, read back what we got and use that */ 514 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 515 case 0: sc->sc_flsize = 1024; break; 516 case 1: sc->sc_flsize = 512; break; 517 case 2: sc->sc_flsize = 256; break; 518 case 3: return EIO; 519 } 520 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 521 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 522 if (err) 523 return err; 524 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 525 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 526 527 for (i = 0; i < sc->sc_flsize; i++) { 528 sc->sc_flist[i] = EHCI_NULL; 529 } 530 531 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 532 533 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 534 KM_SLEEP); 535 LIST_INIT(&sc->sc_freeitds); 536 LIST_INIT(&sc->sc_freesitds); 537 TAILQ_INIT(&sc->sc_intrhead); 538 539 /* Set up the bus struct. */ 540 sc->sc_bus.ub_methods = &ehci_bus_methods; 541 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 542 543 sc->sc_eintrs = EHCI_NORMAL_INTRS; 544 545 /* 546 * Allocate the interrupt dummy QHs. These are arranged to give poll 547 * intervals that are powers of 2 times 1ms. 548 */ 549 for (i = 0; i < EHCI_INTRQHS; i++) { 550 sqh = ehci_alloc_sqh(sc); 551 if (sqh == NULL) { 552 err = ENOMEM; 553 goto bad1; 554 } 555 sc->sc_islots[i].sqh = sqh; 556 } 557 for (i = 0; i < EHCI_INTRQHS; i++) { 558 sqh = sc->sc_islots[i].sqh; 559 if (i == 0) { 560 /* The last (1ms) QH terminates. */ 561 sqh->qh.qh_link = EHCI_NULL; 562 sqh->next = NULL; 563 } else { 564 /* Otherwise the next QH has half the poll interval */ 565 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 566 sqh->qh.qh_link = htole32(sqh->next->physaddr | 567 EHCI_LINK_QH); 568 } 569 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 570 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 571 sqh->qh.qh_curqtd = EHCI_NULL; 572 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 573 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 574 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 575 sqh->sqtd = NULL; 576 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 577 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 578 } 579 /* Point the frame list at the last level (128ms). */ 580 for (i = 0; i < sc->sc_flsize; i++) { 581 int j; 582 583 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 584 revbits[i & (EHCI_MAX_POLLRATE-1)]; 585 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 586 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 587 i)].sqh->physaddr); 588 } 589 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 590 BUS_DMASYNC_PREWRITE); 591 592 /* Allocate dummy QH that starts the async list. */ 593 sqh = ehci_alloc_sqh(sc); 594 if (sqh == NULL) { 595 err = ENOMEM; 596 goto bad1; 597 } 598 /* Fill the QH */ 599 sqh->qh.qh_endp = 600 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 601 sqh->qh.qh_link = 602 htole32(sqh->physaddr | EHCI_LINK_QH); 603 sqh->qh.qh_curqtd = EHCI_NULL; 604 sqh->next = NULL; 605 /* Fill the overlay qTD */ 606 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 607 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 608 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 609 sqh->sqtd = NULL; 610 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 611 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 612 #ifdef EHCI_DEBUG 613 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 614 ehci_dump_sqh(sqh); 615 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 616 #endif 617 618 /* Point to async list */ 619 sc->sc_async_head = sqh; 620 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 621 622 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 623 624 /* Turn on controller */ 625 EOWRITE4(sc, EHCI_USBCMD, 626 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 627 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 628 EHCI_CMD_ASE | 629 EHCI_CMD_PSE | 630 EHCI_CMD_RS); 631 632 /* Take over port ownership */ 633 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 634 635 for (i = 0; i < 100; i++) { 636 usb_delay_ms(&sc->sc_bus, 1); 637 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 638 if (!hcr) 639 break; 640 } 641 if (hcr) { 642 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 643 return EIO; 644 } 645 646 /* Enable interrupts */ 647 DPRINTF("enabling interrupts", 0, 0, 0, 0); 648 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 649 650 return 0; 651 652 #if 0 653 bad2: 654 ehci_free_sqh(sc, sc->sc_async_head); 655 #endif 656 bad1: 657 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 658 return err; 659 } 660 661 int 662 ehci_intr(void *v) 663 { 664 ehci_softc_t *sc = v; 665 int ret = 0; 666 667 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 668 669 if (sc == NULL) 670 return 0; 671 672 mutex_spin_enter(&sc->sc_intr_lock); 673 674 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 675 goto done; 676 677 /* If we get an interrupt while polling, then just ignore it. */ 678 if (sc->sc_bus.ub_usepolling) { 679 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 680 681 if (intrs) 682 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 683 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 684 goto done; 685 } 686 687 ret = ehci_intr1(sc); 688 689 done: 690 mutex_spin_exit(&sc->sc_intr_lock); 691 return ret; 692 } 693 694 Static int 695 ehci_intr1(ehci_softc_t *sc) 696 { 697 uint32_t intrs, eintrs; 698 699 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 700 701 /* In case the interrupt occurs before initialization has completed. */ 702 if (sc == NULL) { 703 #ifdef DIAGNOSTIC 704 printf("ehci_intr1: sc == NULL\n"); 705 #endif 706 return 0; 707 } 708 709 KASSERT(mutex_owned(&sc->sc_intr_lock)); 710 711 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 712 if (!intrs) 713 return 0; 714 715 eintrs = intrs & sc->sc_eintrs; 716 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 717 EOREAD4(sc, EHCI_USBSTS), eintrs); 718 if (!eintrs) 719 return 0; 720 721 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 722 if (eintrs & EHCI_STS_IAA) { 723 DPRINTF("door bell", 0, 0, 0, 0); 724 kpreempt_disable(); 725 KASSERT(sc->sc_doorbell_si != NULL); 726 softint_schedule(sc->sc_doorbell_si); 727 kpreempt_enable(); 728 eintrs &= ~EHCI_STS_IAA; 729 } 730 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 731 DPRINTF("INT=%jd ERRINT=%jd", 732 eintrs & EHCI_STS_INT ? 1 : 0, 733 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 734 usb_schedsoftintr(&sc->sc_bus); 735 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 736 } 737 if (eintrs & EHCI_STS_HSE) { 738 printf("%s: unrecoverable error, controller halted\n", 739 device_xname(sc->sc_dev)); 740 /* XXX what else */ 741 } 742 if (eintrs & EHCI_STS_PCD) { 743 kpreempt_disable(); 744 KASSERT(sc->sc_pcd_si != NULL); 745 softint_schedule(sc->sc_pcd_si); 746 kpreempt_enable(); 747 eintrs &= ~EHCI_STS_PCD; 748 } 749 750 if (eintrs != 0) { 751 /* Block unprocessed interrupts. */ 752 sc->sc_eintrs &= ~eintrs; 753 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 754 printf("%s: blocking intrs %#x\n", 755 device_xname(sc->sc_dev), eintrs); 756 } 757 758 return 1; 759 } 760 761 Static void 762 ehci_doorbell(void *addr) 763 { 764 ehci_softc_t *sc = addr; 765 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 766 767 mutex_enter(&sc->sc_lock); 768 cv_broadcast(&sc->sc_doorbell); 769 mutex_exit(&sc->sc_lock); 770 } 771 772 Static void 773 ehci_pcd(void *addr) 774 { 775 ehci_softc_t *sc = addr; 776 struct usbd_xfer *xfer; 777 u_char *p; 778 int i, m; 779 780 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 781 782 mutex_enter(&sc->sc_lock); 783 xfer = sc->sc_intrxfer; 784 785 if (xfer == NULL) { 786 /* Just ignore the change. */ 787 goto done; 788 } 789 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 790 791 p = xfer->ux_buf; 792 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 793 memset(p, 0, xfer->ux_length); 794 for (i = 1; i <= m; i++) { 795 /* Pick out CHANGE bits from the status reg. */ 796 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 797 p[i/8] |= 1 << (i%8); 798 if (i % 8 == 7) 799 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 800 } 801 xfer->ux_actlen = xfer->ux_length; 802 xfer->ux_status = USBD_NORMAL_COMPLETION; 803 804 usb_transfer_complete(xfer); 805 806 done: 807 mutex_exit(&sc->sc_lock); 808 } 809 810 Static void 811 ehci_softintr(void *v) 812 { 813 struct usbd_bus *bus = v; 814 ehci_softc_t *sc = EHCI_BUS2SC(bus); 815 struct ehci_xfer *ex, *nextex; 816 817 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 818 819 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 820 821 ex_completeq_t cq; 822 TAILQ_INIT(&cq); 823 824 /* 825 * The only explanation I can think of for why EHCI is as brain dead 826 * as UHCI interrupt-wise is that Intel was involved in both. 827 * An interrupt just tells us that something is done, we have no 828 * clue what, so we need to scan through all active transfers. :-( 829 */ 830 831 /* 832 * ehci_idone will remove transfer from sc->sc_intrhead if it's 833 * complete and add to our cq list 834 * 835 */ 836 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 837 switch (ex->ex_type) { 838 case EX_CTRL: 839 case EX_BULK: 840 case EX_INTR: 841 ehci_check_qh_intr(sc, ex, &cq); 842 break; 843 case EX_ISOC: 844 ehci_check_itd_intr(sc, ex, &cq); 845 break; 846 case EX_FS_ISOC: 847 ehci_check_sitd_intr(sc, ex, &cq); 848 break; 849 default: 850 KASSERT(false); 851 } 852 853 } 854 855 /* 856 * We abuse ex_next for the interrupt and complete lists and 857 * interrupt transfers will get re-added here so use 858 * the _SAFE version of TAILQ_FOREACH. 859 */ 860 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 861 usb_transfer_complete(&ex->ex_xfer); 862 } 863 864 /* Schedule a callout to catch any dropped transactions. */ 865 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 866 !TAILQ_EMPTY(&sc->sc_intrhead)) 867 callout_reset(&sc->sc_tmo_intrlist, 868 hz, ehci_intrlist_timeout, sc); 869 } 870 871 Static void 872 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 873 { 874 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 875 uint32_t status; 876 877 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 878 879 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 880 881 if (ex->ex_type == EX_CTRL) { 882 fsqtd = ex->ex_setup; 883 lsqtd = ex->ex_status; 884 } else { 885 fsqtd = ex->ex_sqtdstart; 886 lsqtd = ex->ex_sqtdend; 887 } 888 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 889 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 890 891 /* 892 * If the last TD is still active we need to check whether there 893 * is an error somewhere in the middle, or whether there was a 894 * short packet (SPD and not ACTIVE). 895 */ 896 usb_syncmem(&lsqtd->dma, 897 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 898 sizeof(lsqtd->qtd.qtd_status), 899 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 900 status = le32toh(lsqtd->qtd.qtd_status); 901 usb_syncmem(&lsqtd->dma, 902 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 903 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 904 if (status & EHCI_QTD_ACTIVE) { 905 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 906 907 /* last qTD has already been checked */ 908 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 909 usb_syncmem(&sqtd->dma, 910 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 911 sizeof(sqtd->qtd.qtd_status), 912 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 913 status = le32toh(sqtd->qtd.qtd_status); 914 usb_syncmem(&sqtd->dma, 915 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 916 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 917 /* If there's an active QTD the xfer isn't done. */ 918 if (status & EHCI_QTD_ACTIVE) 919 break; 920 /* Any kind of error makes the xfer done. */ 921 if (status & EHCI_QTD_HALTED) 922 goto done; 923 /* Handle short packets */ 924 if (EHCI_QTD_GET_BYTES(status) != 0) { 925 /* 926 * If we get here for a control transfer then 927 * we need to let the hardware complete the 928 * status phase. That is, we're not done 929 * quite yet. 930 * 931 * Otherwise, we're done. 932 */ 933 if (ex->ex_type == EX_CTRL) { 934 break; 935 } 936 goto done; 937 } 938 } 939 DPRINTFN(10, "ex=%#jx std=%#jx still active", 940 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 941 #ifdef EHCI_DEBUG 942 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 943 ehci_dump_sqtds(ex->ex_sqtdstart); 944 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 945 #endif 946 return; 947 } 948 done: 949 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 950 ehci_idone(ex, cq); 951 } 952 953 Static void 954 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 955 { 956 ehci_soft_itd_t *itd; 957 int i; 958 959 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 960 961 KASSERT(mutex_owned(&sc->sc_lock)); 962 963 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 964 return; 965 966 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 967 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 968 969 itd = ex->ex_itdend; 970 971 /* 972 * check no active transfers in last itd, meaning we're finished 973 */ 974 975 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 976 sizeof(itd->itd.itd_ctl), 977 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 978 979 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 980 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 981 break; 982 } 983 984 if (i == EHCI_ITD_NUFRAMES) { 985 goto done; /* All 8 descriptors inactive, it's done */ 986 } 987 988 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 989 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 990 991 DPRINTFN(10, "ex %#jx itd %#jx still active", 992 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 993 return; 994 done: 995 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 996 ehci_idone(ex, cq); 997 } 998 999 void 1000 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1001 { 1002 ehci_soft_sitd_t *sitd; 1003 1004 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1005 1006 KASSERT(mutex_owned(&sc->sc_lock)); 1007 1008 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1009 return; 1010 1011 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1012 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1013 1014 sitd = ex->ex_sitdend; 1015 1016 /* 1017 * check no active transfers in last sitd, meaning we're finished 1018 */ 1019 1020 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1021 sizeof(sitd->sitd.sitd_trans), 1022 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1023 1024 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1025 1026 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1027 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1028 1029 if (active) 1030 return; 1031 1032 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1033 ehci_idone(ex, cq); 1034 } 1035 1036 Static void 1037 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1038 { 1039 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1040 struct usbd_xfer *xfer = &ex->ex_xfer; 1041 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1042 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1043 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1044 uint32_t status = 0, nstatus = 0; 1045 int actlen = 0; 1046 1047 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1048 1049 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1050 1051 /* 1052 * Try to claim this xfer for completion. If it has already 1053 * completed or aborted, drop it on the floor. 1054 */ 1055 if (!usbd_xfer_trycomplete(xfer)) 1056 return; 1057 1058 #ifdef DIAGNOSTIC 1059 #ifdef EHCI_DEBUG 1060 if (ex->ex_isdone) { 1061 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1062 ehci_dump_exfer(ex); 1063 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1064 } 1065 #endif 1066 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1067 ex->ex_type, xfer->ux_status); 1068 ex->ex_isdone = true; 1069 #endif 1070 1071 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1072 (uintptr_t)epipe, 0, 0); 1073 1074 /* The transfer is done, compute actual length and status. */ 1075 if (ex->ex_type == EX_ISOC) { 1076 /* HS isoc transfer */ 1077 1078 struct ehci_soft_itd *itd; 1079 int i, nframes, len, uframes; 1080 1081 nframes = 0; 1082 1083 #ifdef EHCI_DEBUG 1084 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1085 ehci_dump_itds(ex->ex_itdstart); 1086 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1087 #endif 1088 1089 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1090 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1091 1092 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1093 usb_syncmem(&itd->dma, 1094 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1095 sizeof(itd->itd.itd_ctl), 1096 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1097 1098 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1099 /* 1100 * XXX - driver didn't fill in the frame full 1101 * of uframes. This leads to scheduling 1102 * inefficiencies, but working around 1103 * this doubles complexity of tracking 1104 * an xfer. 1105 */ 1106 if (nframes >= xfer->ux_nframes) 1107 break; 1108 1109 status = le32toh(itd->itd.itd_ctl[i]); 1110 len = EHCI_ITD_GET_LEN(status); 1111 if (EHCI_ITD_GET_STATUS(status) != 0) 1112 len = 0; /*No valid data on error*/ 1113 1114 xfer->ux_frlengths[nframes++] = len; 1115 actlen += len; 1116 } 1117 usb_syncmem(&itd->dma, 1118 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1119 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1120 1121 if (nframes >= xfer->ux_nframes) 1122 break; 1123 } 1124 1125 xfer->ux_actlen = actlen; 1126 xfer->ux_status = USBD_NORMAL_COMPLETION; 1127 goto end; 1128 } else if (ex->ex_type == EX_FS_ISOC) { 1129 /* FS isoc transfer */ 1130 struct ehci_soft_sitd *sitd; 1131 int nframes, len; 1132 1133 nframes = 0; 1134 1135 for (sitd = ex->ex_sitdstart; sitd != NULL; 1136 sitd = sitd->xfer_next) { 1137 usb_syncmem(&sitd->dma, 1138 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1139 sizeof(sitd->sitd.sitd_trans), 1140 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1141 1142 /* 1143 * XXX - driver didn't fill in the frame full 1144 * of uframes. This leads to scheduling 1145 * inefficiencies, but working around 1146 * this doubles complexity of tracking 1147 * an xfer. 1148 */ 1149 if (nframes >= xfer->ux_nframes) 1150 break; 1151 1152 status = le32toh(sitd->sitd.sitd_trans); 1153 usb_syncmem(&sitd->dma, 1154 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1155 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1156 1157 len = EHCI_SITD_GET_LEN(status); 1158 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1159 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1160 /* No valid data on error */ 1161 len = xfer->ux_frlengths[nframes]; 1162 } 1163 1164 /* 1165 * frlengths[i]: # of bytes to send 1166 * len: # of bytes host didn't send 1167 */ 1168 xfer->ux_frlengths[nframes] -= len; 1169 /* frlengths[i]: # of bytes host sent */ 1170 actlen += xfer->ux_frlengths[nframes++]; 1171 1172 if (nframes >= xfer->ux_nframes) 1173 break; 1174 } 1175 1176 xfer->ux_actlen = actlen; 1177 xfer->ux_status = USBD_NORMAL_COMPLETION; 1178 goto end; 1179 } 1180 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1181 ex->ex_type == EX_BULK); 1182 1183 /* Continue processing xfers using queue heads */ 1184 if (ex->ex_type == EX_CTRL) { 1185 fsqtd = ex->ex_setup; 1186 lsqtd = ex->ex_status; 1187 } else { 1188 fsqtd = ex->ex_sqtdstart; 1189 lsqtd = ex->ex_sqtdend; 1190 } 1191 #ifdef EHCI_DEBUG 1192 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1193 ehci_dump_sqtds(fsqtd); 1194 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1195 #endif 1196 1197 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1198 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1199 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1200 nstatus = le32toh(sqtd->qtd.qtd_status); 1201 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1202 BUS_DMASYNC_PREREAD); 1203 if (nstatus & EHCI_QTD_ACTIVE) 1204 break; 1205 1206 status = nstatus; 1207 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1208 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1209 } 1210 1211 /* 1212 * If there are left over TDs we need to update the toggle. 1213 * The default pipe doesn't need it since control transfers 1214 * start the toggle at 0 every time. 1215 * For a short transfer we need to update the toggle for the missing 1216 * packets within the qTD. 1217 */ 1218 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1219 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1220 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1221 status, nstatus, 0, 0); 1222 #if 0 1223 ehci_dump_sqh(epipe->sqh); 1224 ehci_dump_sqtds(ex->ex_sqtdstart); 1225 #endif 1226 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1227 } 1228 1229 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1230 status, 0); 1231 xfer->ux_actlen = actlen; 1232 if (status & EHCI_QTD_HALTED) { 1233 #ifdef EHCI_DEBUG 1234 DPRINTF("halted addr=%jd endpt=0x%02jx", 1235 xfer->ux_pipe->up_dev->ud_addr, 1236 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1237 0, 0); 1238 DPRINTF("cerr=%jd pid=%jd", 1239 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1240 0, 0); 1241 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1242 status & EHCI_QTD_ACTIVE ? 1 : 0, 1243 status & EHCI_QTD_HALTED ? 1 : 0, 1244 status & EHCI_QTD_BUFERR ? 1 : 0, 1245 status & EHCI_QTD_BABBLE ? 1 : 0); 1246 1247 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1248 status & EHCI_QTD_XACTERR ? 1 : 0, 1249 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1250 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1251 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1252 1253 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1254 ehci_dump_sqh(epipe->sqh); 1255 ehci_dump_sqtds(ex->ex_sqtdstart); 1256 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1257 #endif 1258 /* low&full speed has an extra error flag */ 1259 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1260 EHCI_QH_SPEED_HIGH) 1261 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1262 else 1263 status &= EHCI_QTD_STATERRS; 1264 if (status == 0) /* no other errors means a stall */ { 1265 xfer->ux_status = USBD_STALLED; 1266 } else { 1267 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1268 } 1269 /* XXX need to reset TT on missed microframe */ 1270 if (status & EHCI_QTD_MISSEDMICRO) { 1271 printf("%s: missed microframe, TT reset not " 1272 "implemented, hub might be inoperational\n", 1273 device_xname(sc->sc_dev)); 1274 } 1275 } else { 1276 xfer->ux_status = USBD_NORMAL_COMPLETION; 1277 } 1278 1279 end: 1280 1281 ehci_del_intr_list(sc, ex); 1282 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1283 1284 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1285 } 1286 1287 Static void 1288 ehci_poll(struct usbd_bus *bus) 1289 { 1290 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1291 1292 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1293 1294 #ifdef EHCI_DEBUG 1295 static int last; 1296 int new; 1297 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1298 if (new != last) { 1299 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1300 last = new; 1301 } 1302 #endif 1303 1304 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1305 mutex_spin_enter(&sc->sc_intr_lock); 1306 ehci_intr1(sc); 1307 mutex_spin_exit(&sc->sc_intr_lock); 1308 } 1309 } 1310 1311 void 1312 ehci_childdet(device_t self, device_t child) 1313 { 1314 struct ehci_softc *sc = device_private(self); 1315 1316 KASSERT(sc->sc_child == child); 1317 sc->sc_child = NULL; 1318 } 1319 1320 int 1321 ehci_detach(struct ehci_softc *sc, int flags) 1322 { 1323 int rv = 0; 1324 1325 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1326 1327 if (sc->sc_child != NULL) { 1328 rv = config_detach(sc->sc_child, flags); 1329 if (rv != 0) 1330 return rv; 1331 } 1332 1333 if (sc->sc_ncomp > 0) { 1334 mutex_enter(&sc->sc_complock); 1335 /* XXX try to halt callout instead of waiting */ 1336 while (sc->sc_comp_state == CO_SCHED) 1337 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1338 mutex_exit(&sc->sc_complock); 1339 1340 callout_halt(&sc->sc_compcallout, NULL); 1341 callout_destroy(&sc->sc_compcallout); 1342 cv_destroy(&sc->sc_compcv); 1343 mutex_destroy(&sc->sc_complock); 1344 } 1345 1346 callout_halt(&sc->sc_tmo_intrlist, NULL); 1347 callout_destroy(&sc->sc_tmo_intrlist); 1348 1349 /* XXX free other data structures */ 1350 if (sc->sc_softitds) { 1351 kmem_free(sc->sc_softitds, 1352 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1353 } 1354 cv_destroy(&sc->sc_doorbell); 1355 1356 #if 0 1357 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1358 softint_disestablish(sc->sc_doorbell_si); 1359 softint_disestablish(sc->sc_pcd_si); 1360 mutex_destroy(&sc->sc_lock); 1361 mutex_destroy(&sc->sc_intr_lock); 1362 #endif 1363 1364 pool_cache_destroy(sc->sc_xferpool); 1365 1366 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1367 1368 return rv; 1369 } 1370 1371 int 1372 ehci_activate(device_t self, enum devact act) 1373 { 1374 struct ehci_softc *sc = device_private(self); 1375 1376 switch (act) { 1377 case DVACT_DEACTIVATE: 1378 sc->sc_dying = 1; 1379 return 0; 1380 default: 1381 return EOPNOTSUPP; 1382 } 1383 } 1384 1385 /* 1386 * Handle suspend/resume. 1387 * 1388 * Note that this power handler isn't to be registered directly; the 1389 * bus glue needs to call out to it. 1390 */ 1391 bool 1392 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1393 { 1394 ehci_softc_t *sc = device_private(dv); 1395 int i; 1396 uint32_t cmd, hcr; 1397 1398 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1399 1400 mutex_enter(&sc->sc_lock); 1401 1402 for (i = 1; i <= sc->sc_noport; i++) { 1403 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1404 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1405 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1406 } 1407 1408 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1409 1410 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1411 EOWRITE4(sc, EHCI_USBCMD, cmd); 1412 1413 for (i = 0; i < 100; i++) { 1414 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1415 if (hcr == 0) 1416 break; 1417 1418 usb_delay_ms(&sc->sc_bus, 1); 1419 } 1420 if (hcr != 0) 1421 printf("%s: reset timeout\n", device_xname(dv)); 1422 1423 cmd &= ~EHCI_CMD_RS; 1424 EOWRITE4(sc, EHCI_USBCMD, cmd); 1425 1426 for (i = 0; i < 100; i++) { 1427 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1428 if (hcr == EHCI_STS_HCH) 1429 break; 1430 1431 usb_delay_ms(&sc->sc_bus, 1); 1432 } 1433 if (hcr != EHCI_STS_HCH) 1434 printf("%s: config timeout\n", device_xname(dv)); 1435 1436 mutex_exit(&sc->sc_lock); 1437 1438 return true; 1439 } 1440 1441 bool 1442 ehci_resume(device_t dv, const pmf_qual_t *qual) 1443 { 1444 ehci_softc_t *sc = device_private(dv); 1445 int i; 1446 uint32_t cmd, hcr; 1447 1448 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1449 1450 mutex_enter(&sc->sc_lock); 1451 1452 /* restore things in case the bios sucks */ 1453 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1454 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1455 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1456 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1457 1458 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1459 1460 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1461 1462 hcr = 0; 1463 for (i = 1; i <= sc->sc_noport; i++) { 1464 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1465 if ((cmd & EHCI_PS_PO) == 0 && 1466 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1467 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1468 hcr = 1; 1469 } 1470 } 1471 1472 if (hcr) { 1473 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1474 1475 for (i = 1; i <= sc->sc_noport; i++) { 1476 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1477 if ((cmd & EHCI_PS_PO) == 0 && 1478 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1479 EOWRITE4(sc, EHCI_PORTSC(i), 1480 cmd & ~EHCI_PS_FPR); 1481 } 1482 } 1483 1484 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1485 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1486 1487 for (i = 0; i < 100; i++) { 1488 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1489 if (hcr != EHCI_STS_HCH) 1490 break; 1491 1492 usb_delay_ms(&sc->sc_bus, 1); 1493 } 1494 if (hcr == EHCI_STS_HCH) 1495 printf("%s: config timeout\n", device_xname(dv)); 1496 1497 mutex_exit(&sc->sc_lock); 1498 1499 return true; 1500 } 1501 1502 /* 1503 * Shut down the controller when the system is going down. 1504 */ 1505 bool 1506 ehci_shutdown(device_t self, int flags) 1507 { 1508 ehci_softc_t *sc = device_private(self); 1509 1510 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1511 1512 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1513 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1514 return true; 1515 } 1516 1517 Static struct usbd_xfer * 1518 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1519 { 1520 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1521 struct usbd_xfer *xfer; 1522 1523 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1524 if (xfer != NULL) { 1525 memset(xfer, 0, sizeof(struct ehci_xfer)); 1526 1527 #ifdef DIAGNOSTIC 1528 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1529 ex->ex_isdone = true; 1530 xfer->ux_state = XFER_BUSY; 1531 #endif 1532 } 1533 return xfer; 1534 } 1535 1536 Static void 1537 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1538 { 1539 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1540 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1541 1542 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1543 xfer->ux_status == USBD_NOT_STARTED, 1544 "xfer %p state %d\n", xfer, xfer->ux_state); 1545 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1546 1547 #ifdef DIAGNOSTIC 1548 xfer->ux_state = XFER_FREE; 1549 #endif 1550 1551 pool_cache_put(sc->sc_xferpool, xfer); 1552 } 1553 1554 Static bool 1555 ehci_dying(struct usbd_bus *bus) 1556 { 1557 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1558 1559 return sc->sc_dying; 1560 } 1561 1562 Static void 1563 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1564 { 1565 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1566 1567 *lock = &sc->sc_lock; 1568 } 1569 1570 Static void 1571 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1572 { 1573 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1574 1575 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1576 1577 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1578 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1579 #ifdef EHCI_DEBUG 1580 if (ehcidebug) 1581 usbd_dump_pipe(pipe); 1582 #endif 1583 epipe->nexttoggle = 0; 1584 } 1585 1586 Static void 1587 ehci_noop(struct usbd_pipe *pipe) 1588 { 1589 } 1590 1591 #ifdef EHCI_DEBUG 1592 /* 1593 * Unused function - this is meant to be called from a kernel 1594 * debugger. 1595 */ 1596 void 1597 ehci_dump(void) 1598 { 1599 ehci_softc_t *sc = theehci; 1600 int i; 1601 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1602 EOREAD4(sc, EHCI_USBCMD), 1603 EOREAD4(sc, EHCI_USBSTS), 1604 EOREAD4(sc, EHCI_USBINTR)); 1605 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1606 EOREAD4(sc, EHCI_FRINDEX), 1607 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1608 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1609 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1610 for (i = 1; i <= sc->sc_noport; i++) 1611 printf("port %d status=0x%08x\n", i, 1612 EOREAD4(sc, EHCI_PORTSC(i))); 1613 } 1614 1615 Static void 1616 ehci_dump_regs(ehci_softc_t *sc) 1617 { 1618 int i; 1619 1620 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1621 1622 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1623 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1624 EOREAD4(sc, EHCI_USBINTR), 0); 1625 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1626 "async = 0x%08jx", 1627 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1628 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1629 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1630 for (i = 1; i <= sc->sc_noport; i += 2) { 1631 if (i == sc->sc_noport) { 1632 DPRINTF("port %jd status = 0x%08jx", i, 1633 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1634 } else { 1635 DPRINTF("port %jd status = 0x%08jx port %jd " 1636 "status = 0x%08jx", 1637 i, EOREAD4(sc, EHCI_PORTSC(i)), 1638 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1639 } 1640 } 1641 } 1642 1643 #define ehci_dump_link(link, type) do { \ 1644 DPRINTF(" link 0x%08jx (T = %jd):", \ 1645 link, \ 1646 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1647 if (type) { \ 1648 DPRINTF( \ 1649 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1650 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1651 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1652 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1653 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1654 } \ 1655 } while(0) 1656 1657 Static void 1658 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1659 { 1660 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1661 int i; 1662 uint32_t stop = 0; 1663 1664 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1665 ehci_dump_sqtd(sqtd); 1666 usb_syncmem(&sqtd->dma, 1667 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1668 sizeof(sqtd->qtd), 1669 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1670 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1671 usb_syncmem(&sqtd->dma, 1672 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1673 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1674 } 1675 if (!stop) 1676 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1677 } 1678 1679 Static void 1680 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1681 { 1682 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1683 1684 usb_syncmem(&sqtd->dma, sqtd->offs, 1685 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1686 1687 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1688 0, 0); 1689 ehci_dump_qtd(&sqtd->qtd); 1690 1691 usb_syncmem(&sqtd->dma, sqtd->offs, 1692 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1693 } 1694 1695 Static void 1696 ehci_dump_qtd(ehci_qtd_t *qtd) 1697 { 1698 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1699 uint32_t s = le32toh(qtd->qtd_status); 1700 1701 DPRINTFN(10, 1702 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1703 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1704 DPRINTFN(10, 1705 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1706 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1707 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1708 DPRINTFN(10, 1709 " cerr = %jd pid = %jd stat = %jx", 1710 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1711 0); 1712 DPRINTFN(10, 1713 "active =%jd halted=%jd buferr=%jd babble=%jd", 1714 s & EHCI_QTD_ACTIVE ? 1 : 0, 1715 s & EHCI_QTD_HALTED ? 1 : 0, 1716 s & EHCI_QTD_BUFERR ? 1 : 0, 1717 s & EHCI_QTD_BABBLE ? 1 : 0); 1718 DPRINTFN(10, 1719 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1720 s & EHCI_QTD_XACTERR ? 1 : 0, 1721 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1722 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1723 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1724 DPRINTFN(10, 1725 "buffer[0] = %#jx buffer[1] = %#jx " 1726 "buffer[2] = %#jx buffer[3] = %#jx", 1727 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1728 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1729 DPRINTFN(10, 1730 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1731 } 1732 1733 Static void 1734 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1735 { 1736 ehci_qh_t *qh = &sqh->qh; 1737 ehci_link_t link; 1738 uint32_t endp, endphub; 1739 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1740 1741 usb_syncmem(&sqh->dma, sqh->offs, 1742 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1743 1744 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1745 link = le32toh(qh->qh_link); 1746 ehci_dump_link(link, true); 1747 1748 endp = le32toh(qh->qh_endp); 1749 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1750 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1751 "eps = %jd", 1752 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1753 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1754 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1755 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1756 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1757 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1758 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1759 1760 endphub = le32toh(qh->qh_endphub); 1761 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1762 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1763 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1764 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1765 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1766 EHCI_QH_GET_MULT(endphub), 0); 1767 1768 link = le32toh(qh->qh_curqtd); 1769 ehci_dump_link(link, false); 1770 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1771 ehci_dump_qtd(&qh->qh_qtd); 1772 1773 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1774 BUS_DMASYNC_PREREAD); 1775 } 1776 1777 Static void 1778 ehci_dump_itds(ehci_soft_itd_t *itd) 1779 { 1780 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1781 int i; 1782 uint32_t stop = 0; 1783 1784 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1785 ehci_dump_itd(itd); 1786 usb_syncmem(&itd->dma, 1787 itd->offs + offsetof(ehci_itd_t, itd_next), 1788 sizeof(itd->itd), 1789 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1790 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1791 usb_syncmem(&itd->dma, 1792 itd->offs + offsetof(ehci_itd_t, itd_next), 1793 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1794 } 1795 if (!stop) 1796 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1797 } 1798 1799 Static void 1800 ehci_dump_itd(struct ehci_soft_itd *itd) 1801 { 1802 ehci_isoc_trans_t t; 1803 ehci_isoc_bufr_ptr_t b, b2, b3; 1804 int i; 1805 1806 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1807 1808 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1809 1810 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1811 t = le32toh(itd->itd.itd_ctl[i]); 1812 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1813 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1814 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1815 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1816 EHCI_ITD_GET_OFFS(t), 0); 1817 } 1818 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1819 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1820 DPRINTF(" %jx", 1821 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1822 1823 b = le32toh(itd->itd.itd_bufr[0]); 1824 b2 = le32toh(itd->itd.itd_bufr[1]); 1825 b3 = le32toh(itd->itd.itd_bufr[2]); 1826 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1827 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1828 DPRINTF(" maxpkt = %jx multi = %jx", 1829 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1830 } 1831 1832 Static void 1833 ehci_dump_sitd(struct ehci_soft_itd *itd) 1834 { 1835 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1836 1837 DPRINTF("SITD %#jx next = %p prev = %#jx", 1838 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1839 (uintptr_t)itd->frame_list.prev, 0); 1840 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1841 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1842 } 1843 1844 Static void 1845 ehci_dump_exfer(struct ehci_xfer *ex) 1846 { 1847 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1848 1849 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1850 ex->ex_isdone, 0); 1851 1852 switch (ex->ex_type) { 1853 case EX_CTRL: 1854 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1855 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1856 (uintptr_t)ex->ex_status, 0); 1857 break; 1858 case EX_BULK: 1859 case EX_INTR: 1860 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1861 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1862 0, 0); 1863 break; 1864 case EX_ISOC: 1865 DPRINTF(" itdstart = %#jx itdend = %#jx", 1866 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1867 break; 1868 case EX_FS_ISOC: 1869 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1870 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1871 0, 0); 1872 break; 1873 default: 1874 DPRINTF(" unknown type", 0, 0, 0, 0); 1875 } 1876 } 1877 #endif 1878 1879 Static usbd_status 1880 ehci_open(struct usbd_pipe *pipe) 1881 { 1882 struct usbd_device *dev = pipe->up_dev; 1883 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1884 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1885 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1886 uint8_t addr = dev->ud_addr; 1887 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1888 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1889 ehci_soft_qh_t *sqh; 1890 usbd_status err; 1891 int ival, speed, naks; 1892 int hshubaddr, hshubport; 1893 1894 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1895 1896 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1897 ed->bEndpointAddress, rhaddr); 1898 1899 if (dev->ud_myhsport) { 1900 /* 1901 * When directly attached FS/LS device while doing embedded 1902 * transaction translations and we are the hub, set the hub 1903 * address to 0 (us). 1904 */ 1905 if (!(sc->sc_flags & EHCIF_ETTF) 1906 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1907 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1908 } else { 1909 hshubaddr = 0; 1910 } 1911 hshubport = dev->ud_myhsport->up_portno; 1912 } else { 1913 hshubaddr = 0; 1914 hshubport = 0; 1915 } 1916 1917 if (sc->sc_dying) 1918 return USBD_IOERROR; 1919 1920 /* toggle state needed for bulk endpoints */ 1921 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1922 1923 if (addr == rhaddr) { 1924 switch (ed->bEndpointAddress) { 1925 case USB_CONTROL_ENDPOINT: 1926 pipe->up_methods = &roothub_ctrl_methods; 1927 break; 1928 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1929 pipe->up_methods = &ehci_root_intr_methods; 1930 break; 1931 default: 1932 DPRINTF("bad bEndpointAddress 0x%02jx", 1933 ed->bEndpointAddress, 0, 0, 0); 1934 return USBD_INVAL; 1935 } 1936 return USBD_NORMAL_COMPLETION; 1937 } 1938 1939 /* XXX All this stuff is only valid for async. */ 1940 switch (dev->ud_speed) { 1941 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1942 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1943 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1944 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1945 } 1946 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1947 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1948 0); 1949 return USBD_INVAL; 1950 } 1951 1952 /* 1953 * For interrupt transfer, nak throttling must be disabled, but for 1954 * the other transfer type, nak throttling should be enabled from the 1955 * viewpoint that avoids the memory thrashing. 1956 */ 1957 naks = (xfertype == UE_INTERRUPT) ? 0 1958 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1959 1960 /* Allocate sqh for everything, save isoc xfers */ 1961 if (xfertype != UE_ISOCHRONOUS) { 1962 sqh = ehci_alloc_sqh(sc); 1963 if (sqh == NULL) 1964 return USBD_NOMEM; 1965 /* qh_link filled when the QH is added */ 1966 sqh->qh.qh_endp = htole32( 1967 EHCI_QH_SET_ADDR(addr) | 1968 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1969 EHCI_QH_SET_EPS(speed) | 1970 EHCI_QH_DTC | 1971 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1972 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1973 EHCI_QH_CTL : 0) | 1974 EHCI_QH_SET_NRL(naks) 1975 ); 1976 sqh->qh.qh_endphub = htole32( 1977 EHCI_QH_SET_MULT(1) | 1978 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1979 ); 1980 if (speed != EHCI_QH_SPEED_HIGH) 1981 sqh->qh.qh_endphub |= htole32( 1982 EHCI_QH_SET_PORT(hshubport) | 1983 EHCI_QH_SET_HUBA(hshubaddr) | 1984 (xfertype == UE_INTERRUPT ? 1985 EHCI_QH_SET_CMASK(0x08) : 0) 1986 ); 1987 sqh->qh.qh_curqtd = EHCI_NULL; 1988 /* Fill the overlay qTD */ 1989 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1990 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1991 sqh->qh.qh_qtd.qtd_status = htole32(0); 1992 1993 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1994 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1995 epipe->sqh = sqh; 1996 } else { 1997 sqh = NULL; 1998 } /*xfertype == UE_ISOC*/ 1999 2000 switch (xfertype) { 2001 case UE_CONTROL: 2002 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 2003 0, USBMALLOC_COHERENT, &epipe->ctrl.reqdma); 2004 #ifdef EHCI_DEBUG 2005 if (err) 2006 printf("ehci_open: usb_allocmem()=%d\n", err); 2007 #endif 2008 if (err) 2009 goto bad; 2010 pipe->up_methods = &ehci_device_ctrl_methods; 2011 mutex_enter(&sc->sc_lock); 2012 ehci_add_qh(sc, sqh, sc->sc_async_head); 2013 mutex_exit(&sc->sc_lock); 2014 break; 2015 case UE_BULK: 2016 pipe->up_methods = &ehci_device_bulk_methods; 2017 mutex_enter(&sc->sc_lock); 2018 ehci_add_qh(sc, sqh, sc->sc_async_head); 2019 mutex_exit(&sc->sc_lock); 2020 break; 2021 case UE_INTERRUPT: 2022 pipe->up_methods = &ehci_device_intr_methods; 2023 ival = pipe->up_interval; 2024 if (ival == USBD_DEFAULT_INTERVAL) { 2025 if (speed == EHCI_QH_SPEED_HIGH) { 2026 if (ed->bInterval > 16) { 2027 /* 2028 * illegal with high-speed, but there 2029 * were documentation bugs in the spec, 2030 * so be generous 2031 */ 2032 ival = 256; 2033 } else 2034 ival = (1 << (ed->bInterval - 1)) / 8; 2035 } else 2036 ival = ed->bInterval; 2037 } 2038 err = ehci_device_setintr(sc, sqh, ival); 2039 if (err) 2040 goto bad; 2041 break; 2042 case UE_ISOCHRONOUS: 2043 pipe->up_serialise = false; 2044 if (speed == EHCI_QH_SPEED_HIGH) 2045 pipe->up_methods = &ehci_device_isoc_methods; 2046 else 2047 pipe->up_methods = &ehci_device_fs_isoc_methods; 2048 if (ed->bInterval == 0 || ed->bInterval > 16) { 2049 printf("ehci: opening pipe with invalid bInterval\n"); 2050 err = USBD_INVAL; 2051 goto bad; 2052 } 2053 if (UGETW(ed->wMaxPacketSize) == 0) { 2054 printf("ehci: zero length endpoint open request\n"); 2055 err = USBD_INVAL; 2056 goto bad; 2057 } 2058 epipe->isoc.next_frame = 0; 2059 epipe->isoc.cur_xfers = 0; 2060 break; 2061 default: 2062 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2063 err = USBD_INVAL; 2064 goto bad; 2065 } 2066 return USBD_NORMAL_COMPLETION; 2067 2068 bad: 2069 if (sqh != NULL) { 2070 mutex_enter(&sc->sc_lock); 2071 ehci_free_sqh(sc, sqh); 2072 mutex_exit(&sc->sc_lock); 2073 } 2074 return err; 2075 } 2076 2077 /* 2078 * Add an ED to the schedule. Called with USB lock held. 2079 */ 2080 Static void 2081 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2082 { 2083 2084 KASSERT(mutex_owned(&sc->sc_lock)); 2085 2086 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2087 2088 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2089 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2090 2091 sqh->next = head->next; 2092 sqh->qh.qh_link = head->qh.qh_link; 2093 2094 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2095 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2096 2097 head->next = sqh; 2098 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2099 2100 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2101 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2102 2103 #ifdef EHCI_DEBUG 2104 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2105 ehci_dump_sqh(sqh); 2106 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2107 #endif 2108 } 2109 2110 /* 2111 * Remove an ED from the schedule. Called with USB lock held. 2112 */ 2113 Static void 2114 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2115 { 2116 ehci_soft_qh_t *p; 2117 2118 KASSERT(mutex_owned(&sc->sc_lock)); 2119 2120 /* XXX */ 2121 for (p = head; p != NULL && p->next != sqh; p = p->next) 2122 ; 2123 if (p == NULL) 2124 panic("ehci_rem_qh: ED not found"); 2125 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2126 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2127 p->next = sqh->next; 2128 p->qh.qh_link = sqh->qh.qh_link; 2129 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2130 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2131 2132 ehci_sync_hc(sc); 2133 } 2134 2135 Static void 2136 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2137 { 2138 int i; 2139 uint32_t status; 2140 2141 /* Save toggle bit and ping status. */ 2142 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2144 status = sqh->qh.qh_qtd.qtd_status & 2145 htole32(EHCI_QTD_TOGGLE_MASK | 2146 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2147 /* Set HALTED to make hw leave it alone. */ 2148 sqh->qh.qh_qtd.qtd_status = 2149 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2150 usb_syncmem(&sqh->dma, 2151 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2152 sizeof(sqh->qh.qh_qtd.qtd_status), 2153 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2154 sqh->qh.qh_curqtd = 0; 2155 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2156 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2157 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2158 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2159 sqh->sqtd = sqtd; 2160 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2161 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2162 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2163 sqh->qh.qh_qtd.qtd_status = status; 2164 usb_syncmem(&sqh->dma, 2165 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2166 sizeof(sqh->qh.qh_qtd.qtd_status), 2167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2168 } 2169 2170 /* 2171 * Ensure that the HC has released all references to the QH. We do this 2172 * by asking for a Async Advance Doorbell interrupt and then we wait for 2173 * the interrupt. 2174 * To make this easier we first obtain exclusive use of the doorbell. 2175 */ 2176 Static void 2177 ehci_sync_hc(ehci_softc_t *sc) 2178 { 2179 int error __diagused; 2180 2181 KASSERT(mutex_owned(&sc->sc_lock)); 2182 2183 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2184 2185 if (sc->sc_dying) { 2186 DPRINTF("dying", 0, 0, 0, 0); 2187 return; 2188 } 2189 2190 /* ask for doorbell */ 2191 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2192 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2193 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2194 2195 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2196 2197 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2198 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2199 #ifdef DIAGNOSTIC 2200 if (error == EWOULDBLOCK) { 2201 printf("ehci_sync_hc: timed out\n"); 2202 } else if (error) { 2203 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2204 } 2205 #endif 2206 } 2207 2208 Static void 2209 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2210 { 2211 2212 KASSERT(mutex_owned(&sc->sc_lock)); 2213 2214 for (; itd != NULL; itd = itd->xfer_next) { 2215 struct ehci_soft_itd *prev = itd->frame_list.prev; 2216 2217 /* Unlink itd from hardware chain, or frame array */ 2218 if (prev == NULL) { /* We're at the table head */ 2219 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2220 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2221 usb_syncmem(&sc->sc_fldma, 2222 sizeof(ehci_link_t) * itd->slot, 2223 sizeof(ehci_link_t), 2224 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2225 2226 if (itd->frame_list.next != NULL) 2227 itd->frame_list.next->frame_list.prev = NULL; 2228 } else { 2229 /* XXX this part is untested... */ 2230 prev->itd.itd_next = itd->itd.itd_next; 2231 usb_syncmem(&itd->dma, 2232 itd->offs + offsetof(ehci_itd_t, itd_next), 2233 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2234 2235 prev->frame_list.next = itd->frame_list.next; 2236 if (itd->frame_list.next != NULL) 2237 itd->frame_list.next->frame_list.prev = prev; 2238 } 2239 } 2240 } 2241 2242 Static void 2243 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2244 { 2245 struct ehci_soft_itd *next; 2246 2247 mutex_enter(&sc->sc_lock); 2248 next = NULL; 2249 for (; itd != NULL; itd = next) { 2250 next = itd->xfer_next; 2251 ehci_free_itd_locked(sc, itd); 2252 } 2253 mutex_exit(&sc->sc_lock); 2254 } 2255 2256 Static void 2257 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2258 { 2259 2260 KASSERT(mutex_owned(&sc->sc_lock)); 2261 2262 for (; sitd != NULL; sitd = sitd->xfer_next) { 2263 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2264 2265 /* Unlink sitd from hardware chain, or frame array */ 2266 if (prev == NULL) { /* We're at the table head */ 2267 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2268 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2269 usb_syncmem(&sc->sc_fldma, 2270 sizeof(ehci_link_t) * sitd->slot, 2271 sizeof(ehci_link_t), 2272 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2273 2274 if (sitd->frame_list.next != NULL) 2275 sitd->frame_list.next->frame_list.prev = NULL; 2276 } else { 2277 /* XXX this part is untested... */ 2278 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2279 usb_syncmem(&sitd->dma, 2280 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2281 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2282 2283 prev->frame_list.next = sitd->frame_list.next; 2284 if (sitd->frame_list.next != NULL) 2285 sitd->frame_list.next->frame_list.prev = prev; 2286 } 2287 } 2288 } 2289 2290 Static void 2291 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2292 { 2293 2294 mutex_enter(&sc->sc_lock); 2295 struct ehci_soft_sitd *next = NULL; 2296 for (; sitd != NULL; sitd = next) { 2297 next = sitd->xfer_next; 2298 ehci_free_sitd_locked(sc, sitd); 2299 } 2300 mutex_exit(&sc->sc_lock); 2301 } 2302 2303 /***********/ 2304 2305 Static int 2306 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2307 void *buf, int buflen) 2308 { 2309 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2310 usb_hub_descriptor_t hubd; 2311 usb_port_status_t ps; 2312 uint16_t len, value, index; 2313 int l, totlen = 0; 2314 int port, i; 2315 uint32_t v; 2316 2317 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2318 2319 if (sc->sc_dying) 2320 return -1; 2321 2322 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2323 0, 0); 2324 2325 len = UGETW(req->wLength); 2326 value = UGETW(req->wValue); 2327 index = UGETW(req->wIndex); 2328 2329 #define C(x,y) ((x) | ((y) << 8)) 2330 switch (C(req->bRequest, req->bmRequestType)) { 2331 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2332 if (len == 0) 2333 break; 2334 switch (value) { 2335 #define sd ((usb_string_descriptor_t *)buf) 2336 case C(2, UDESC_STRING): 2337 /* Product */ 2338 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2339 break; 2340 #undef sd 2341 default: 2342 /* default from usbroothub */ 2343 return buflen; 2344 } 2345 break; 2346 2347 /* Hub requests */ 2348 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2349 break; 2350 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2351 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2352 value, 0, 0); 2353 if (index < 1 || index > sc->sc_noport) { 2354 return -1; 2355 } 2356 port = EHCI_PORTSC(index); 2357 v = EOREAD4(sc, port); 2358 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2359 v &= ~EHCI_PS_CLEAR; 2360 switch (value) { 2361 case UHF_PORT_ENABLE: 2362 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2363 break; 2364 case UHF_PORT_SUSPEND: 2365 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2366 break; 2367 v &= ~EHCI_PS_SUSP; 2368 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2369 /* see USB2 spec ch. 7.1.7.7 */ 2370 usb_delay_ms(&sc->sc_bus, 20); 2371 EOWRITE4(sc, port, v); 2372 usb_delay_ms(&sc->sc_bus, 2); 2373 #ifdef DEBUG 2374 v = EOREAD4(sc, port); 2375 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2376 printf("ehci: resume failed: %x\n", v); 2377 #endif 2378 break; 2379 case UHF_PORT_POWER: 2380 if (sc->sc_hasppc) 2381 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2382 break; 2383 case UHF_PORT_TEST: 2384 DPRINTF("clear port test %jd", index, 0, 0, 0); 2385 break; 2386 case UHF_PORT_INDICATOR: 2387 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2388 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2389 break; 2390 case UHF_C_PORT_CONNECTION: 2391 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2392 break; 2393 case UHF_C_PORT_ENABLE: 2394 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2395 break; 2396 case UHF_C_PORT_SUSPEND: 2397 /* how? */ 2398 break; 2399 case UHF_C_PORT_OVER_CURRENT: 2400 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2401 break; 2402 case UHF_C_PORT_RESET: 2403 sc->sc_isreset[index] = 0; 2404 break; 2405 default: 2406 return -1; 2407 } 2408 #if 0 2409 switch(value) { 2410 case UHF_C_PORT_CONNECTION: 2411 case UHF_C_PORT_ENABLE: 2412 case UHF_C_PORT_SUSPEND: 2413 case UHF_C_PORT_OVER_CURRENT: 2414 case UHF_C_PORT_RESET: 2415 default: 2416 break; 2417 } 2418 #endif 2419 break; 2420 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2421 if (len == 0) 2422 break; 2423 if ((value & 0xff) != 0) { 2424 return -1; 2425 } 2426 totlen = uimin(buflen, sizeof(hubd)); 2427 memcpy(&hubd, buf, totlen); 2428 hubd.bNbrPorts = sc->sc_noport; 2429 v = EOREAD4(sc, EHCI_HCSPARAMS); 2430 USETW(hubd.wHubCharacteristics, 2431 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2432 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2433 ? UHD_PORT_IND : 0); 2434 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2435 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2436 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2437 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2438 totlen = uimin(totlen, hubd.bDescLength); 2439 memcpy(buf, &hubd, totlen); 2440 break; 2441 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2442 if (len != 4) { 2443 return -1; 2444 } 2445 memset(buf, 0, len); /* ? XXX */ 2446 totlen = len; 2447 break; 2448 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2449 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2450 if (index < 1 || index > sc->sc_noport) { 2451 return -1; 2452 } 2453 if (len != 4) { 2454 return -1; 2455 } 2456 v = EOREAD4(sc, EHCI_PORTSC(index)); 2457 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2458 2459 i = UPS_HIGH_SPEED; 2460 if (sc->sc_flags & EHCIF_ETTF) { 2461 /* 2462 * If we are doing embedded transaction translation, 2463 * then directly attached LS/FS devices are reset by 2464 * the EHCI controller itself. PSPD is encoded 2465 * the same way as in USBSTATUS. 2466 */ 2467 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2468 } 2469 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2470 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2471 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2472 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2473 if (v & EHCI_PS_PR) i |= UPS_RESET; 2474 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2475 if (sc->sc_vendor_port_status) 2476 i = sc->sc_vendor_port_status(sc, v, i); 2477 USETW(ps.wPortStatus, i); 2478 i = 0; 2479 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2480 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2481 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2482 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2483 USETW(ps.wPortChange, i); 2484 totlen = uimin(len, sizeof(ps)); 2485 memcpy(buf, &ps, totlen); 2486 break; 2487 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2488 return -1; 2489 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2490 break; 2491 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2492 if (index < 1 || index > sc->sc_noport) { 2493 return -1; 2494 } 2495 port = EHCI_PORTSC(index); 2496 v = EOREAD4(sc, port); 2497 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2498 v &= ~EHCI_PS_CLEAR; 2499 switch(value) { 2500 case UHF_PORT_ENABLE: 2501 EOWRITE4(sc, port, v | EHCI_PS_PE); 2502 break; 2503 case UHF_PORT_SUSPEND: 2504 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2505 break; 2506 case UHF_PORT_RESET: 2507 DPRINTF("reset port %jd", index, 0, 0, 0); 2508 if (EHCI_PS_IS_LOWSPEED(v) 2509 && sc->sc_ncomp > 0 2510 && !(sc->sc_flags & EHCIF_ETTF)) { 2511 /* 2512 * Low speed device on non-ETTF controller or 2513 * unaccompanied controller, give up ownership. 2514 */ 2515 ehci_disown(sc, index, 1); 2516 break; 2517 } 2518 /* Start reset sequence. */ 2519 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2520 EOWRITE4(sc, port, v | EHCI_PS_PR); 2521 /* Wait for reset to complete. */ 2522 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2523 if (sc->sc_dying) { 2524 return -1; 2525 } 2526 /* 2527 * An embedded transaction translator will automatically 2528 * terminate the reset sequence so there's no need to 2529 * it. 2530 */ 2531 v = EOREAD4(sc, port); 2532 if (v & EHCI_PS_PR) { 2533 /* Terminate reset sequence. */ 2534 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2535 /* Wait for HC to complete reset. */ 2536 usb_delay_ms(&sc->sc_bus, 2537 EHCI_PORT_RESET_COMPLETE); 2538 if (sc->sc_dying) { 2539 return -1; 2540 } 2541 } 2542 2543 v = EOREAD4(sc, port); 2544 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2545 if (v & EHCI_PS_PR) { 2546 printf("%s: port reset timeout\n", 2547 device_xname(sc->sc_dev)); 2548 return USBD_TIMEOUT; 2549 } 2550 if (!(v & EHCI_PS_PE)) { 2551 /* Not a high speed device, give up ownership.*/ 2552 ehci_disown(sc, index, 0); 2553 break; 2554 } 2555 sc->sc_isreset[index] = 1; 2556 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2557 v, 0, 0); 2558 break; 2559 case UHF_PORT_POWER: 2560 DPRINTF("set port power %jd (has PPC = %jd)", index, 2561 sc->sc_hasppc, 0, 0); 2562 if (sc->sc_hasppc) 2563 EOWRITE4(sc, port, v | EHCI_PS_PP); 2564 break; 2565 case UHF_PORT_TEST: 2566 DPRINTF("set port test %jd", index, 0, 0, 0); 2567 break; 2568 case UHF_PORT_INDICATOR: 2569 DPRINTF("set port ind %jd", index, 0, 0, 0); 2570 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2571 break; 2572 default: 2573 return -1; 2574 } 2575 break; 2576 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2577 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2578 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2579 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2580 break; 2581 default: 2582 /* default from usbroothub */ 2583 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2584 2585 return buflen; 2586 } 2587 2588 DPRINTF("returning %jd", totlen, 0, 0, 0); 2589 2590 return totlen; 2591 } 2592 2593 /* 2594 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2595 * 2596 * This pile of garbage below works around the following problem without 2597 * holding boots with no hand-over devices present, while penalising 2598 * boots where the first ehci probe hands off devices with a 5 second 2599 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2600 * for RB_SINGLE, but the same basic issue exists. 2601 * 2602 * The way ehci hand-off works, the companion controller does not get the 2603 * device until after its initial bus explore, so the reference dropped 2604 * after the first explore is not enough. 5 seconds should be enough, 2605 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2606 * 2607 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2608 * if the callback is scheduled. CO_DONE is set when the callout has 2609 * called config_pending_decr(). 2610 * 2611 * There's a mutex, a cv and a callout here, and we delay detach if the 2612 * callout has been set. 2613 */ 2614 #ifndef EHCI_DISOWN_DELAY_SECONDS 2615 #define EHCI_DISOWN_DELAY_SECONDS 5 2616 #endif 2617 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2618 2619 static void 2620 ehci_disown_callback(void *arg) 2621 { 2622 ehci_softc_t *sc = arg; 2623 2624 config_pending_decr(sc->sc_dev); 2625 2626 mutex_enter(&sc->sc_complock); 2627 KASSERT(sc->sc_comp_state == CO_SCHED); 2628 sc->sc_comp_state = CO_DONE; 2629 cv_signal(&sc->sc_compcv); 2630 mutex_exit(&sc->sc_complock); 2631 } 2632 2633 static void 2634 ehci_disown_sched_callback(ehci_softc_t *sc) 2635 { 2636 extern bool root_is_mounted; 2637 2638 mutex_enter(&sc->sc_complock); 2639 2640 if (root_is_mounted || 2641 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2642 sc->sc_comp_state != CO_EARLY) { 2643 mutex_exit(&sc->sc_complock); 2644 return; 2645 } 2646 2647 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2648 ehci_disown_callback, &sc->sc_dev); 2649 sc->sc_comp_state = CO_SCHED; 2650 2651 mutex_exit(&sc->sc_complock); 2652 2653 config_pending_incr(sc->sc_dev); 2654 aprint_normal("delaying %s by %u seconds due to USB owner change.\n", 2655 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user", 2656 ehci_disown_delay_seconds); 2657 } 2658 2659 Static void 2660 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2661 { 2662 int port; 2663 uint32_t v; 2664 2665 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2666 2667 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2668 if (sc->sc_npcomp != 0) { 2669 int i = (index-1) / sc->sc_npcomp; 2670 if (i < sc->sc_ncomp) { 2671 ehci_disown_sched_callback(sc); 2672 #ifdef DIAGNOSTIC 2673 printf("%s: handing over %s speed device on " 2674 "port %d to %s\n", 2675 device_xname(sc->sc_dev), 2676 lowspeed ? "low" : "full", 2677 index, sc->sc_comps[i] ? 2678 device_xname(sc->sc_comps[i]) : 2679 "companion controller"); 2680 } else { 2681 printf("%s: strange port\n", 2682 device_xname(sc->sc_dev)); 2683 #endif 2684 } 2685 } else { 2686 #ifdef DIAGNOSTIC 2687 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2688 #endif 2689 } 2690 port = EHCI_PORTSC(index); 2691 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2692 EOWRITE4(sc, port, v | EHCI_PS_PO); 2693 } 2694 2695 Static usbd_status 2696 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2697 { 2698 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2699 usbd_status err; 2700 2701 /* Insert last in queue. */ 2702 mutex_enter(&sc->sc_lock); 2703 err = usb_insert_transfer(xfer); 2704 mutex_exit(&sc->sc_lock); 2705 if (err) 2706 return err; 2707 2708 /* Pipe isn't running, start first */ 2709 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2710 } 2711 2712 Static usbd_status 2713 ehci_root_intr_start(struct usbd_xfer *xfer) 2714 { 2715 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2716 const bool polling = sc->sc_bus.ub_usepolling; 2717 2718 if (sc->sc_dying) 2719 return USBD_IOERROR; 2720 2721 if (!polling) 2722 mutex_enter(&sc->sc_lock); 2723 KASSERT(sc->sc_intrxfer == NULL); 2724 sc->sc_intrxfer = xfer; 2725 xfer->ux_status = USBD_IN_PROGRESS; 2726 if (!polling) 2727 mutex_exit(&sc->sc_lock); 2728 2729 return USBD_IN_PROGRESS; 2730 } 2731 2732 /* Abort a root interrupt request. */ 2733 Static void 2734 ehci_root_intr_abort(struct usbd_xfer *xfer) 2735 { 2736 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2737 2738 KASSERT(mutex_owned(&sc->sc_lock)); 2739 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2740 2741 /* If xfer has already completed, nothing to do here. */ 2742 if (sc->sc_intrxfer == NULL) 2743 return; 2744 2745 /* 2746 * Otherwise, sc->sc_intrxfer had better be this transfer. 2747 * Cancel it. 2748 */ 2749 KASSERT(sc->sc_intrxfer == xfer); 2750 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2751 xfer->ux_status = USBD_CANCELLED; 2752 usb_transfer_complete(xfer); 2753 } 2754 2755 /* Close the root pipe. */ 2756 Static void 2757 ehci_root_intr_close(struct usbd_pipe *pipe) 2758 { 2759 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2760 2761 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2762 2763 KASSERT(mutex_owned(&sc->sc_lock)); 2764 2765 /* 2766 * Caller must guarantee the xfer has completed first, by 2767 * closing the pipe only after normal completion or an abort. 2768 */ 2769 KASSERT(sc->sc_intrxfer == NULL); 2770 } 2771 2772 Static void 2773 ehci_root_intr_done(struct usbd_xfer *xfer) 2774 { 2775 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2776 2777 KASSERT(mutex_owned(&sc->sc_lock)); 2778 2779 /* Claim the xfer so it doesn't get completed again. */ 2780 KASSERT(sc->sc_intrxfer == xfer); 2781 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2782 sc->sc_intrxfer = NULL; 2783 } 2784 2785 /************************/ 2786 2787 Static ehci_soft_qh_t * 2788 ehci_alloc_sqh(ehci_softc_t *sc) 2789 { 2790 ehci_soft_qh_t *sqh; 2791 usbd_status err; 2792 int i, offs; 2793 usb_dma_t dma; 2794 2795 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2796 2797 mutex_enter(&sc->sc_lock); 2798 if (sc->sc_freeqhs == NULL) { 2799 DPRINTF("allocating chunk", 0, 0, 0, 0); 2800 mutex_exit(&sc->sc_lock); 2801 2802 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2803 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2804 #ifdef EHCI_DEBUG 2805 if (err) 2806 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2807 #endif 2808 if (err) 2809 return NULL; 2810 2811 mutex_enter(&sc->sc_lock); 2812 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2813 offs = i * EHCI_SQH_SIZE; 2814 sqh = KERNADDR(&dma, offs); 2815 sqh->physaddr = DMAADDR(&dma, offs); 2816 sqh->dma = dma; 2817 sqh->offs = offs; 2818 sqh->next = sc->sc_freeqhs; 2819 sc->sc_freeqhs = sqh; 2820 } 2821 } 2822 sqh = sc->sc_freeqhs; 2823 sc->sc_freeqhs = sqh->next; 2824 mutex_exit(&sc->sc_lock); 2825 2826 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2827 sqh->next = NULL; 2828 return sqh; 2829 } 2830 2831 Static void 2832 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2833 { 2834 KASSERT(mutex_owned(&sc->sc_lock)); 2835 2836 sqh->next = sc->sc_freeqhs; 2837 sc->sc_freeqhs = sqh; 2838 } 2839 2840 Static ehci_soft_qtd_t * 2841 ehci_alloc_sqtd(ehci_softc_t *sc) 2842 { 2843 ehci_soft_qtd_t *sqtd = NULL; 2844 int i, offs; 2845 usb_dma_t dma; 2846 2847 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2848 2849 mutex_enter(&sc->sc_lock); 2850 if (sc->sc_freeqtds == NULL) { 2851 DPRINTF("allocating chunk", 0, 0, 0, 0); 2852 mutex_exit(&sc->sc_lock); 2853 2854 int err = usb_allocmem(&sc->sc_bus, 2855 EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2856 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, 2857 &dma); 2858 #ifdef EHCI_DEBUG 2859 if (err) 2860 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2861 #endif 2862 if (err) 2863 goto done; 2864 2865 mutex_enter(&sc->sc_lock); 2866 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2867 offs = i * EHCI_SQTD_SIZE; 2868 sqtd = KERNADDR(&dma, offs); 2869 sqtd->physaddr = DMAADDR(&dma, offs); 2870 sqtd->dma = dma; 2871 sqtd->offs = offs; 2872 2873 sqtd->nextqtd = sc->sc_freeqtds; 2874 sc->sc_freeqtds = sqtd; 2875 } 2876 } 2877 2878 sqtd = sc->sc_freeqtds; 2879 sc->sc_freeqtds = sqtd->nextqtd; 2880 mutex_exit(&sc->sc_lock); 2881 2882 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2883 sqtd->nextqtd = NULL; 2884 sqtd->xfer = NULL; 2885 2886 done: 2887 return sqtd; 2888 } 2889 2890 Static void 2891 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2892 { 2893 2894 mutex_enter(&sc->sc_lock); 2895 sqtd->nextqtd = sc->sc_freeqtds; 2896 sc->sc_freeqtds = sqtd; 2897 mutex_exit(&sc->sc_lock); 2898 } 2899 2900 Static int 2901 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2902 int alen, int rd, ehci_soft_qtd_t **sp) 2903 { 2904 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2905 uint16_t flags = xfer->ux_flags; 2906 2907 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2908 2909 ASSERT_SLEEPABLE(); 2910 KASSERT(sp); 2911 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2912 2913 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2914 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 2915 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2916 KM_SLEEP); 2917 exfer->ex_nsqtd = nsqtd; 2918 2919 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2920 alen, nsqtd, flags); 2921 2922 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2923 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2924 if (cur == NULL) 2925 goto nomem; 2926 exfer->ex_sqtds[j++] = cur; 2927 2928 cur->xfer = xfer; 2929 cur->len = 0; 2930 2931 } 2932 2933 *sp = exfer->ex_sqtds[0]; 2934 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2935 2936 return 0; 2937 2938 nomem: 2939 ehci_free_sqtds(sc, exfer); 2940 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2941 DPRINTF("no memory", 0, 0, 0, 0); 2942 return ENOMEM; 2943 } 2944 2945 Static void 2946 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2947 { 2948 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2949 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2950 2951 mutex_enter(&sc->sc_lock); 2952 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2953 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2954 2955 if (sqtd == NULL) 2956 break; 2957 2958 sqtd->nextqtd = sc->sc_freeqtds; 2959 sc->sc_freeqtds = sqtd; 2960 } 2961 mutex_exit(&sc->sc_lock); 2962 } 2963 2964 Static void 2965 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2966 { 2967 if (prev) { 2968 prev->nextqtd = sqtd; 2969 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2970 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2971 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2972 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2973 } 2974 } 2975 2976 Static void 2977 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2978 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2979 { 2980 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2981 usb_dma_t *dma = &xfer->ux_dmabuf; 2982 uint16_t flags = xfer->ux_flags; 2983 ehci_soft_qtd_t *sqtd, *prev; 2984 int tog = *toggle; 2985 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2986 int len = length; 2987 2988 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2989 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2990 len, isread, tog); 2991 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2992 0, 0, 0); 2993 2994 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2995 2996 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2997 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2998 EHCI_QTD_SET_CERR(3) 2999 ; 3000 3001 sqtd = prev = NULL; 3002 size_t curoffs = 0; 3003 size_t j = 0; 3004 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3005 sqtd = exfer->ex_sqtds[j++]; 3006 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3007 (uintptr_t)prev, 0); 3008 3009 /* 3010 * The EHCI hardware can handle at most 5 pages and they do 3011 * not have to be contiguous 3012 */ 3013 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3014 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3015 size_t curlen = len; 3016 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3017 /* must use multiple TDs, fill as much as possible. */ 3018 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3019 3020 /* the length must be a multiple of the max size */ 3021 curlen -= curlen % mps; 3022 } 3023 KASSERT(curlen != 0); 3024 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3025 curoffs, 0); 3026 3027 /* Fill the qTD */ 3028 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3029 sqtd->qtd.qtd_status = htole32( 3030 qtdstatus | 3031 EHCI_QTD_SET_BYTES(curlen) | 3032 EHCI_QTD_SET_TOGGLE(tog)); 3033 3034 /* Find number of pages we'll be using, insert dma addresses */ 3035 size_t pages = EHCI_NPAGES(curlen); 3036 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3037 size_t pageoffs = EHCI_PAGE(curoffs); 3038 for (size_t i = 0; i < pages; i++) { 3039 paddr_t a = EHCI_PAGE(DMAADDR(dma, 3040 pageoffs + i * EHCI_PAGE_SIZE)); 3041 sqtd->qtd.qtd_buffer[i] = htole32(BUS_ADDR_LO32(a)); 3042 sqtd->qtd.qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a)); 3043 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3044 i, pages, 3045 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3046 le32toh(sqtd->qtd.qtd_buffer[i])); 3047 } 3048 /* First buffer pointer requires a page offset to start at */ 3049 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3050 3051 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3052 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3053 3054 sqtd->len = curlen; 3055 3056 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3057 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3058 3059 ehci_append_sqtd(sqtd, prev); 3060 3061 if (howmany(curlen, mps) & 1) { 3062 tog ^= 1; 3063 } 3064 3065 curoffs += curlen; 3066 len -= curlen; 3067 } 3068 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3069 xfer, length, len, mps, exfer->ex_nsqtd, j); 3070 3071 if (!isread && 3072 (flags & USBD_FORCE_SHORT_XFER) && 3073 length % mps == 0) { 3074 /* Force a 0 length transfer at the end. */ 3075 3076 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3077 exfer->ex_nsqtd); 3078 prev = sqtd; 3079 sqtd = exfer->ex_sqtds[j++]; 3080 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3081 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3082 sqtd->qtd.qtd_status = htole32( 3083 qtdstatus | 3084 EHCI_QTD_SET_BYTES(0) | 3085 EHCI_QTD_SET_TOGGLE(tog)); 3086 3087 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3088 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3089 3090 ehci_append_sqtd(sqtd, prev); 3091 tog ^= 1; 3092 } 3093 3094 *lsqtd = sqtd; 3095 *toggle = tog; 3096 } 3097 3098 Static ehci_soft_itd_t * 3099 ehci_alloc_itd(ehci_softc_t *sc) 3100 { 3101 struct ehci_soft_itd *itd, *freeitd; 3102 usb_dma_t dma; 3103 3104 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3105 3106 mutex_enter(&sc->sc_lock); 3107 3108 freeitd = LIST_FIRST(&sc->sc_freeitds); 3109 if (freeitd == NULL) { 3110 DPRINTF("allocating chunk", 0, 0, 0, 0); 3111 mutex_exit(&sc->sc_lock); 3112 int err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3113 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3114 3115 if (err) { 3116 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3117 return NULL; 3118 } 3119 mutex_enter(&sc->sc_lock); 3120 3121 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3122 int offs = i * EHCI_ITD_SIZE; 3123 itd = KERNADDR(&dma, offs); 3124 itd->physaddr = DMAADDR(&dma, offs); 3125 itd->dma = dma; 3126 itd->offs = offs; 3127 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3128 } 3129 freeitd = LIST_FIRST(&sc->sc_freeitds); 3130 } 3131 3132 itd = freeitd; 3133 LIST_REMOVE(itd, free_list); 3134 mutex_exit(&sc->sc_lock); 3135 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3136 3137 itd->frame_list.next = NULL; 3138 itd->frame_list.prev = NULL; 3139 itd->xfer_next = NULL; 3140 itd->slot = 0; 3141 3142 return itd; 3143 } 3144 3145 Static ehci_soft_sitd_t * 3146 ehci_alloc_sitd(ehci_softc_t *sc) 3147 { 3148 struct ehci_soft_sitd *sitd, *freesitd; 3149 int i, offs; 3150 usb_dma_t dma; 3151 3152 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3153 3154 mutex_enter(&sc->sc_lock); 3155 freesitd = LIST_FIRST(&sc->sc_freesitds); 3156 if (freesitd == NULL) { 3157 DPRINTF("allocating chunk", 0, 0, 0, 0); 3158 mutex_exit(&sc->sc_lock); 3159 int err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3160 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3161 3162 if (err) { 3163 DPRINTF("alloc returned %jd", err, 0, 0, 3164 0); 3165 return NULL; 3166 } 3167 3168 mutex_enter(&sc->sc_lock); 3169 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3170 offs = i * EHCI_SITD_SIZE; 3171 sitd = KERNADDR(&dma, offs); 3172 sitd->physaddr = DMAADDR(&dma, offs); 3173 sitd->dma = dma; 3174 sitd->offs = offs; 3175 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3176 } 3177 freesitd = LIST_FIRST(&sc->sc_freesitds); 3178 } 3179 3180 sitd = freesitd; 3181 LIST_REMOVE(sitd, free_list); 3182 mutex_exit(&sc->sc_lock); 3183 3184 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3185 3186 sitd->frame_list.next = NULL; 3187 sitd->frame_list.prev = NULL; 3188 sitd->xfer_next = NULL; 3189 sitd->slot = 0; 3190 3191 return sitd; 3192 } 3193 3194 /****************/ 3195 3196 /* 3197 * Close a reqular pipe. 3198 * Assumes that there are no pending transactions. 3199 */ 3200 Static void 3201 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3202 { 3203 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3204 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3205 ehci_soft_qh_t *sqh = epipe->sqh; 3206 3207 KASSERT(mutex_owned(&sc->sc_lock)); 3208 3209 ehci_rem_qh(sc, sqh, head); 3210 ehci_free_sqh(sc, epipe->sqh); 3211 } 3212 3213 /* 3214 * Arrange for the hardware to tells us that it is not still 3215 * processing the TDs by setting the QH halted bit and wait for the ehci 3216 * door bell 3217 */ 3218 Static void 3219 ehci_abortx(struct usbd_xfer *xfer) 3220 { 3221 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3222 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3223 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3224 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3225 ehci_soft_qh_t *sqh = epipe->sqh; 3226 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3227 ehci_physaddr_t cur; 3228 uint32_t qhstatus; 3229 int hit; 3230 3231 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3232 3233 KASSERT(mutex_owned(&sc->sc_lock)); 3234 ASSERT_SLEEPABLE(); 3235 3236 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3237 xfer->ux_status == USBD_TIMEOUT), 3238 "bad abort status: %d", xfer->ux_status); 3239 3240 /* 3241 * If we're dying, skip the hardware action and just notify the 3242 * software that we're done. 3243 */ 3244 if (sc->sc_dying) { 3245 goto dying; 3246 } 3247 3248 /* 3249 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3250 */ 3251 ehci_del_intr_list(sc, exfer); 3252 3253 usb_syncmem(&sqh->dma, 3254 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3255 sizeof(sqh->qh.qh_qtd.qtd_status), 3256 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3257 qhstatus = sqh->qh.qh_qtd.qtd_status; 3258 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3259 usb_syncmem(&sqh->dma, 3260 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3261 sizeof(sqh->qh.qh_qtd.qtd_status), 3262 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3263 3264 if (exfer->ex_type == EX_CTRL) { 3265 fsqtd = exfer->ex_setup; 3266 lsqtd = exfer->ex_status; 3267 } else { 3268 fsqtd = exfer->ex_sqtdstart; 3269 lsqtd = exfer->ex_sqtdend; 3270 } 3271 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3272 usb_syncmem(&sqtd->dma, 3273 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3274 sizeof(sqtd->qtd.qtd_status), 3275 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3276 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3277 usb_syncmem(&sqtd->dma, 3278 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3279 sizeof(sqtd->qtd.qtd_status), 3280 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3281 if (sqtd == lsqtd) 3282 break; 3283 } 3284 3285 /* 3286 * HC Step 2: Wait until we know hardware has finished any possible 3287 * use of the xfer. 3288 */ 3289 ehci_sync_hc(sc); 3290 3291 /* 3292 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3293 * The complication here is that the hardware may have executed 3294 * beyond the xfer we're trying to abort. So as we're scanning 3295 * the TDs of this xfer we check if the hardware points to 3296 * any of them. 3297 */ 3298 3299 usb_syncmem(&sqh->dma, 3300 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3301 sizeof(sqh->qh.qh_curqtd), 3302 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3303 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3304 hit = 0; 3305 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3306 hit |= cur == sqtd->physaddr; 3307 if (sqtd == lsqtd) 3308 break; 3309 } 3310 sqtd = sqtd->nextqtd; 3311 /* Zap curqtd register if hardware pointed inside the xfer. */ 3312 if (hit && sqtd != NULL) { 3313 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3314 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3315 usb_syncmem(&sqh->dma, 3316 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3317 sizeof(sqh->qh.qh_curqtd), 3318 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3319 sqh->qh.qh_qtd.qtd_status = qhstatus; 3320 usb_syncmem(&sqh->dma, 3321 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3322 sizeof(sqh->qh.qh_qtd.qtd_status), 3323 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3324 } else { 3325 DPRINTF("no hit", 0, 0, 0, 0); 3326 usb_syncmem(&sqh->dma, 3327 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3328 sizeof(sqh->qh.qh_curqtd), 3329 BUS_DMASYNC_PREREAD); 3330 } 3331 3332 /* 3333 * Final step: Notify completion to waiting xfers. 3334 */ 3335 dying: 3336 #ifdef DIAGNOSTIC 3337 exfer->ex_isdone = true; 3338 #endif 3339 usb_transfer_complete(xfer); 3340 DPRINTFN(14, "end", 0, 0, 0, 0); 3341 3342 KASSERT(mutex_owned(&sc->sc_lock)); 3343 } 3344 3345 Static void 3346 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3347 { 3348 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3349 ehci_isoc_trans_t trans_status; 3350 struct ehci_xfer *exfer; 3351 ehci_softc_t *sc; 3352 struct ehci_soft_itd *itd; 3353 struct ehci_soft_sitd *sitd; 3354 int i; 3355 3356 KASSERTMSG(status == USBD_CANCELLED, 3357 "invalid status for abort: %d", (int)status); 3358 3359 exfer = EHCI_XFER2EXFER(xfer); 3360 sc = EHCI_XFER2SC(xfer); 3361 3362 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3363 (uintptr_t)xfer->ux_pipe, 0, 0); 3364 3365 KASSERT(mutex_owned(&sc->sc_lock)); 3366 ASSERT_SLEEPABLE(); 3367 3368 /* No timeout or task here. */ 3369 3370 /* 3371 * The xfer cannot have been cancelled already. It is the 3372 * responsibility of the caller of usbd_abort_pipe not to try 3373 * to abort a pipe multiple times, whether concurrently or 3374 * sequentially. 3375 */ 3376 KASSERT(xfer->ux_status != USBD_CANCELLED); 3377 3378 /* If anyone else beat us, we're done. */ 3379 if (xfer->ux_status != USBD_IN_PROGRESS) 3380 return; 3381 3382 /* We beat everyone else. Claim the status. */ 3383 xfer->ux_status = status; 3384 3385 /* 3386 * If we're dying, skip the hardware action and just notify the 3387 * software that we're done. 3388 */ 3389 if (sc->sc_dying) { 3390 goto dying; 3391 } 3392 3393 /* 3394 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3395 */ 3396 ehci_del_intr_list(sc, exfer); 3397 3398 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3399 for (itd = exfer->ex_itdstart; itd != NULL; 3400 itd = itd->xfer_next) { 3401 usb_syncmem(&itd->dma, 3402 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3403 sizeof(itd->itd.itd_ctl), 3404 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3405 3406 for (i = 0; i < 8; i++) { 3407 trans_status = le32toh(itd->itd.itd_ctl[i]); 3408 trans_status &= ~EHCI_ITD_ACTIVE; 3409 itd->itd.itd_ctl[i] = htole32(trans_status); 3410 } 3411 3412 usb_syncmem(&itd->dma, 3413 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3414 sizeof(itd->itd.itd_ctl), 3415 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3416 } 3417 } else { 3418 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3419 sitd = sitd->xfer_next) { 3420 usb_syncmem(&sitd->dma, 3421 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3422 sizeof(sitd->sitd.sitd_buffer), 3423 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3424 3425 trans_status = le32toh(sitd->sitd.sitd_trans); 3426 trans_status &= ~EHCI_SITD_ACTIVE; 3427 sitd->sitd.sitd_trans = htole32(trans_status); 3428 3429 usb_syncmem(&sitd->dma, 3430 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3431 sizeof(sitd->sitd.sitd_buffer), 3432 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3433 } 3434 } 3435 3436 dying: 3437 #ifdef DIAGNOSTIC 3438 exfer->ex_isdone = true; 3439 #endif 3440 usb_transfer_complete(xfer); 3441 DPRINTFN(14, "end", 0, 0, 0, 0); 3442 3443 KASSERT(mutex_owned(&sc->sc_lock)); 3444 } 3445 3446 /************************/ 3447 3448 Static int 3449 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3450 { 3451 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3452 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3453 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3454 usb_device_request_t *req = &xfer->ux_request; 3455 ehci_soft_qtd_t *setup, *status, *next; 3456 int isread = req->bmRequestType & UT_READ; 3457 int len = xfer->ux_bufsize; 3458 int err; 3459 3460 exfer->ex_type = EX_CTRL; 3461 exfer->ex_status = NULL; 3462 exfer->ex_data = NULL; 3463 exfer->ex_setup = ehci_alloc_sqtd(sc); 3464 if (exfer->ex_setup == NULL) { 3465 err = ENOMEM; 3466 goto bad1; 3467 } 3468 exfer->ex_status = ehci_alloc_sqtd(sc); 3469 if (exfer->ex_status == NULL) { 3470 err = ENOMEM; 3471 goto bad2; 3472 } 3473 setup = exfer->ex_setup; 3474 status = exfer->ex_status; 3475 exfer->ex_nsqtd = 0; 3476 next = status; 3477 /* Set up data transaction */ 3478 if (len != 0) { 3479 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3480 &exfer->ex_data); 3481 if (err) 3482 goto bad3; 3483 next = exfer->ex_data; 3484 } 3485 3486 /* Clear toggle */ 3487 setup->qtd.qtd_status = htole32( 3488 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3489 EHCI_QTD_SET_TOGGLE(0) | 3490 EHCI_QTD_SET_BYTES(sizeof(*req)) 3491 ); 3492 3493 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3494 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3495 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3496 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3497 setup->nextqtd = next; 3498 setup->xfer = xfer; 3499 setup->len = sizeof(*req); 3500 3501 status->qtd.qtd_status = htole32( 3502 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3503 EHCI_QTD_SET_TOGGLE(1) | 3504 EHCI_QTD_IOC 3505 ); 3506 status->qtd.qtd_buffer[0] = 0; 3507 status->qtd.qtd_buffer_hi[0] = 0; 3508 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3509 status->nextqtd = NULL; 3510 status->xfer = xfer; 3511 status->len = 0; 3512 3513 return 0; 3514 bad3: 3515 ehci_free_sqtd(sc, exfer->ex_status); 3516 bad2: 3517 ehci_free_sqtd(sc, exfer->ex_setup); 3518 bad1: 3519 return err; 3520 } 3521 3522 Static void 3523 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3524 { 3525 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3526 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3527 3528 KASSERT(ex->ex_type == EX_CTRL); 3529 3530 ehci_free_sqtd(sc, ex->ex_setup); 3531 ehci_free_sqtd(sc, ex->ex_status); 3532 ehci_free_sqtds(sc, ex); 3533 if (ex->ex_nsqtd) 3534 kmem_free(ex->ex_sqtds, 3535 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3536 } 3537 3538 Static usbd_status 3539 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3540 { 3541 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3542 usbd_status err; 3543 3544 /* Insert last in queue. */ 3545 mutex_enter(&sc->sc_lock); 3546 err = usb_insert_transfer(xfer); 3547 mutex_exit(&sc->sc_lock); 3548 if (err) 3549 return err; 3550 3551 /* Pipe isn't running, start first */ 3552 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3553 } 3554 3555 Static usbd_status 3556 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3557 { 3558 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3559 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3560 usb_device_request_t *req = &xfer->ux_request; 3561 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3562 ehci_soft_qtd_t *setup, *status, *next; 3563 ehci_soft_qh_t *sqh; 3564 const bool polling = sc->sc_bus.ub_usepolling; 3565 3566 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3567 3568 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3569 3570 if (sc->sc_dying) 3571 return USBD_IOERROR; 3572 3573 const int isread = req->bmRequestType & UT_READ; 3574 const int len = UGETW(req->wLength); 3575 3576 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3577 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3578 UGETW(req->wIndex)); 3579 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3580 len, epipe->pipe.up_dev->ud_addr, 3581 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3582 3583 sqh = epipe->sqh; 3584 3585 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3586 "address QH %" __PRIuBIT " pipe %d\n", 3587 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3588 epipe->pipe.up_dev->ud_addr); 3589 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3590 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3591 "MPS QH %" __PRIuBIT " pipe %d\n", 3592 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3593 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3594 3595 setup = exfer->ex_setup; 3596 status = exfer->ex_status; 3597 3598 DPRINTF("setup %#jx status %#jx data %#jx", 3599 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3600 KASSERTMSG(setup != NULL && status != NULL, 3601 "Failed memory allocation, setup %p status %p", 3602 setup, status); 3603 3604 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3605 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3606 3607 /* Clear toggle */ 3608 setup->qtd.qtd_status &= ~htole32( 3609 EHCI_QTD_STATUS_MASK | 3610 EHCI_QTD_BYTES_MASK | 3611 EHCI_QTD_TOGGLE_MASK | 3612 EHCI_QTD_CERR_MASK 3613 ); 3614 setup->qtd.qtd_status |= htole32( 3615 EHCI_QTD_ACTIVE | 3616 EHCI_QTD_SET_CERR(3) | 3617 EHCI_QTD_SET_TOGGLE(0) | 3618 EHCI_QTD_SET_BYTES(sizeof(*req)) 3619 ); 3620 3621 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3622 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3623 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3624 3625 next = status; 3626 status->qtd.qtd_status &= ~htole32( 3627 EHCI_QTD_STATUS_MASK | 3628 EHCI_QTD_PID_MASK | 3629 EHCI_QTD_BYTES_MASK | 3630 EHCI_QTD_TOGGLE_MASK | 3631 EHCI_QTD_CERR_MASK 3632 ); 3633 status->qtd.qtd_status |= htole32( 3634 EHCI_QTD_ACTIVE | 3635 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3636 EHCI_QTD_SET_CERR(3) | 3637 EHCI_QTD_SET_TOGGLE(1) | 3638 EHCI_QTD_SET_BYTES(0) | 3639 EHCI_QTD_IOC 3640 ); 3641 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3642 3643 KASSERT(exfer->ex_isdone); 3644 #ifdef DIAGNOSTIC 3645 exfer->ex_isdone = false; 3646 #endif 3647 3648 /* Set up data transaction */ 3649 if (len != 0) { 3650 ehci_soft_qtd_t *end; 3651 3652 /* Start toggle at 1. */ 3653 int toggle = 1; 3654 next = exfer->ex_data; 3655 KASSERTMSG(next != NULL, "Failed memory allocation"); 3656 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3657 end->nextqtd = status; 3658 end->qtd.qtd_next = end->qtd.qtd_altnext = 3659 htole32(status->physaddr); 3660 3661 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3662 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3663 3664 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3665 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3666 } 3667 3668 setup->nextqtd = next; 3669 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3670 3671 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3672 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3673 3674 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3675 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3676 3677 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3678 3679 #ifdef EHCI_DEBUG 3680 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3681 ehci_dump_sqh(sqh); 3682 ehci_dump_sqtds(setup); 3683 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3684 #endif 3685 3686 if (!polling) 3687 mutex_enter(&sc->sc_lock); 3688 3689 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3690 ehci_set_qh_qtd(sqh, setup); 3691 usbd_xfer_schedule_timeout(xfer); 3692 ehci_add_intr_list(sc, exfer); 3693 xfer->ux_status = USBD_IN_PROGRESS; 3694 if (!polling) 3695 mutex_exit(&sc->sc_lock); 3696 3697 #if 0 3698 #ifdef EHCI_DEBUG 3699 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3700 // delay(10000); 3701 ehci_dump_regs(sc); 3702 ehci_dump_sqh(sc->sc_async_head); 3703 ehci_dump_sqh(sqh); 3704 ehci_dump_sqtds(setup); 3705 #endif 3706 #endif 3707 3708 return USBD_IN_PROGRESS; 3709 } 3710 3711 Static void 3712 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3713 { 3714 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3715 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3716 usb_device_request_t *req = &xfer->ux_request; 3717 int len = UGETW(req->wLength); 3718 int rd = req->bmRequestType & UT_READ; 3719 3720 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3721 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3722 3723 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3724 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3725 3726 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3727 BUS_DMASYNC_POSTWRITE); 3728 if (len) 3729 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3730 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3731 3732 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3733 } 3734 3735 /* Abort a device control request. */ 3736 Static void 3737 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3738 { 3739 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3740 3741 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3742 usbd_xfer_abort(xfer); 3743 } 3744 3745 /* Close a device control pipe. */ 3746 Static void 3747 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3748 { 3749 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3750 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3751 3752 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3753 3754 KASSERT(mutex_owned(&sc->sc_lock)); 3755 3756 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3757 3758 ehci_close_pipe(pipe, sc->sc_async_head); 3759 3760 usb_freemem(&sc->sc_bus, &epipe->ctrl.reqdma); 3761 } 3762 3763 /* 3764 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3765 * qTD status, or miss signalling occasionally under heavy load. If the host 3766 * machine is too fast, we can miss transaction completion - when we scan 3767 * the active list the transaction still seems to be active. This generally 3768 * exhibits itself as a umass stall that never recovers. 3769 * 3770 * We work around this behaviour by setting up this callback after any softintr 3771 * that completes with transactions still pending, giving us another chance to 3772 * check for completion after the writeback has taken place. 3773 */ 3774 Static void 3775 ehci_intrlist_timeout(void *arg) 3776 { 3777 ehci_softc_t *sc = arg; 3778 3779 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3780 3781 usb_schedsoftintr(&sc->sc_bus); 3782 } 3783 3784 /************************/ 3785 3786 Static int 3787 ehci_device_bulk_init(struct usbd_xfer *xfer) 3788 { 3789 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3790 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3791 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3792 int endpt = ed->bEndpointAddress; 3793 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3794 int len = xfer->ux_bufsize; 3795 int err = 0; 3796 3797 exfer->ex_type = EX_BULK; 3798 exfer->ex_nsqtd = 0; 3799 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3800 &exfer->ex_sqtdstart); 3801 3802 return err; 3803 } 3804 3805 Static void 3806 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3807 { 3808 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3809 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3810 3811 KASSERT(ex->ex_type == EX_BULK); 3812 3813 ehci_free_sqtds(sc, ex); 3814 if (ex->ex_nsqtd) 3815 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3816 } 3817 3818 Static usbd_status 3819 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3820 { 3821 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3822 usbd_status err; 3823 3824 /* Insert last in queue. */ 3825 mutex_enter(&sc->sc_lock); 3826 err = usb_insert_transfer(xfer); 3827 mutex_exit(&sc->sc_lock); 3828 if (err) 3829 return err; 3830 3831 /* Pipe isn't running, start first */ 3832 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3833 } 3834 3835 Static usbd_status 3836 ehci_device_bulk_start(struct usbd_xfer *xfer) 3837 { 3838 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3839 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3840 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3841 ehci_soft_qh_t *sqh; 3842 ehci_soft_qtd_t *end; 3843 int len, isread, endpt; 3844 const bool polling = sc->sc_bus.ub_usepolling; 3845 3846 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3847 3848 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3849 xfer->ux_flags, 0); 3850 3851 if (sc->sc_dying) 3852 return USBD_IOERROR; 3853 3854 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3855 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3856 3857 len = xfer->ux_length; 3858 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3859 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3860 sqh = epipe->sqh; 3861 3862 KASSERT(exfer->ex_isdone); 3863 #ifdef DIAGNOSTIC 3864 exfer->ex_isdone = false; 3865 #endif 3866 3867 /* Take lock here to protect nexttoggle */ 3868 if (!polling) 3869 mutex_enter(&sc->sc_lock); 3870 3871 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3872 3873 exfer->ex_sqtdend = end; 3874 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3875 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3876 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3877 3878 #ifdef EHCI_DEBUG 3879 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3880 ehci_dump_sqh(sqh); 3881 ehci_dump_sqtds(exfer->ex_sqtdstart); 3882 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3883 #endif 3884 3885 if (xfer->ux_length) 3886 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3887 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3888 3889 /* also does usb_syncmem(sqh) */ 3890 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3891 usbd_xfer_schedule_timeout(xfer); 3892 ehci_add_intr_list(sc, exfer); 3893 xfer->ux_status = USBD_IN_PROGRESS; 3894 if (!polling) 3895 mutex_exit(&sc->sc_lock); 3896 3897 #if 0 3898 #ifdef EHCI_DEBUG 3899 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3900 // delay(10000); 3901 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3902 ehci_dump_regs(sc); 3903 #if 0 3904 printf("async_head:\n"); 3905 ehci_dump_sqh(sc->sc_async_head); 3906 #endif 3907 DPRINTF("sqh:", 0, 0, 0, 0); 3908 ehci_dump_sqh(sqh); 3909 ehci_dump_sqtds(exfer->ex_sqtdstart); 3910 #endif 3911 #endif 3912 3913 return USBD_IN_PROGRESS; 3914 } 3915 3916 Static void 3917 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3918 { 3919 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3920 3921 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3922 usbd_xfer_abort(xfer); 3923 } 3924 3925 /* 3926 * Close a device bulk pipe. 3927 */ 3928 Static void 3929 ehci_device_bulk_close(struct usbd_pipe *pipe) 3930 { 3931 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3932 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3933 3934 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3935 3936 KASSERT(mutex_owned(&sc->sc_lock)); 3937 3938 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3939 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3940 ehci_close_pipe(pipe, sc->sc_async_head); 3941 } 3942 3943 Static void 3944 ehci_device_bulk_done(struct usbd_xfer *xfer) 3945 { 3946 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3947 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3948 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3949 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3950 3951 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3952 3953 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 3954 3955 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3956 3957 if (xfer->ux_length) 3958 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3959 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3960 3961 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3962 } 3963 3964 /************************/ 3965 3966 Static usbd_status 3967 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3968 { 3969 struct ehci_soft_islot *isp; 3970 int islot, lev; 3971 3972 /* Find a poll rate that is large enough. */ 3973 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3974 if (EHCI_ILEV_IVAL(lev) <= ival) 3975 break; 3976 3977 /* Pick an interrupt slot at the right level. */ 3978 /* XXX could do better than picking at random */ 3979 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3980 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3981 3982 sqh->islot = islot; 3983 isp = &sc->sc_islots[islot]; 3984 mutex_enter(&sc->sc_lock); 3985 ehci_add_qh(sc, sqh, isp->sqh); 3986 mutex_exit(&sc->sc_lock); 3987 3988 return USBD_NORMAL_COMPLETION; 3989 } 3990 3991 Static int 3992 ehci_device_intr_init(struct usbd_xfer *xfer) 3993 { 3994 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3995 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3996 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3997 int endpt = ed->bEndpointAddress; 3998 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3999 int len = xfer->ux_bufsize; 4000 int err; 4001 4002 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4003 4004 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4005 xfer->ux_flags, 0); 4006 4007 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4008 KASSERT(len != 0); 4009 4010 exfer->ex_type = EX_INTR; 4011 exfer->ex_nsqtd = 0; 4012 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4013 &exfer->ex_sqtdstart); 4014 4015 return err; 4016 } 4017 4018 Static void 4019 ehci_device_intr_fini(struct usbd_xfer *xfer) 4020 { 4021 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4022 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4023 4024 KASSERT(ex->ex_type == EX_INTR); 4025 4026 ehci_free_sqtds(sc, ex); 4027 if (ex->ex_nsqtd) 4028 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4029 } 4030 4031 Static usbd_status 4032 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4033 { 4034 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4035 usbd_status err; 4036 4037 /* Insert last in queue. */ 4038 mutex_enter(&sc->sc_lock); 4039 err = usb_insert_transfer(xfer); 4040 mutex_exit(&sc->sc_lock); 4041 if (err) 4042 return err; 4043 4044 /* 4045 * Pipe isn't running (otherwise err would be USBD_INPROG), 4046 * so start it first. 4047 */ 4048 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4049 } 4050 4051 Static usbd_status 4052 ehci_device_intr_start(struct usbd_xfer *xfer) 4053 { 4054 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4055 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4056 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4057 ehci_soft_qtd_t *end; 4058 ehci_soft_qh_t *sqh; 4059 int len, isread, endpt; 4060 const bool polling = sc->sc_bus.ub_usepolling; 4061 4062 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4063 4064 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4065 xfer->ux_flags, 0); 4066 4067 if (sc->sc_dying) 4068 return USBD_IOERROR; 4069 4070 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4071 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4072 4073 len = xfer->ux_length; 4074 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4075 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4076 sqh = epipe->sqh; 4077 4078 KASSERT(exfer->ex_isdone); 4079 #ifdef DIAGNOSTIC 4080 exfer->ex_isdone = false; 4081 #endif 4082 4083 /* Take lock to protect nexttoggle */ 4084 if (!polling) 4085 mutex_enter(&sc->sc_lock); 4086 4087 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4088 4089 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4090 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4091 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4092 exfer->ex_sqtdend = end; 4093 4094 #ifdef EHCI_DEBUG 4095 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4096 ehci_dump_sqh(sqh); 4097 ehci_dump_sqtds(exfer->ex_sqtdstart); 4098 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4099 #endif 4100 4101 if (xfer->ux_length) 4102 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4103 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4104 4105 /* also does usb_syncmem(sqh) */ 4106 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4107 usbd_xfer_schedule_timeout(xfer); 4108 ehci_add_intr_list(sc, exfer); 4109 xfer->ux_status = USBD_IN_PROGRESS; 4110 if (!polling) 4111 mutex_exit(&sc->sc_lock); 4112 4113 #if 0 4114 #ifdef EHCI_DEBUG 4115 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4116 // delay(10000); 4117 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4118 ehci_dump_regs(sc); 4119 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4120 ehci_dump_sqh(sqh); 4121 ehci_dump_sqtds(exfer->ex_sqtdstart); 4122 #endif 4123 #endif 4124 4125 return USBD_IN_PROGRESS; 4126 } 4127 4128 Static void 4129 ehci_device_intr_abort(struct usbd_xfer *xfer) 4130 { 4131 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4132 4133 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4134 4135 /* 4136 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4137 * async doorbell. That's dependent on the async list, wheras 4138 * intr xfers are periodic, should not use this? 4139 */ 4140 usbd_xfer_abort(xfer); 4141 } 4142 4143 Static void 4144 ehci_device_intr_close(struct usbd_pipe *pipe) 4145 { 4146 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4147 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4148 struct ehci_soft_islot *isp; 4149 4150 KASSERT(mutex_owned(&sc->sc_lock)); 4151 4152 isp = &sc->sc_islots[epipe->sqh->islot]; 4153 ehci_close_pipe(pipe, isp->sqh); 4154 } 4155 4156 Static void 4157 ehci_device_intr_done(struct usbd_xfer *xfer) 4158 { 4159 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4160 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4161 4162 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4163 4164 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4165 4166 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4167 4168 if (xfer->ux_length) { 4169 int isread, endpt; 4170 4171 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4172 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4173 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4174 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4175 } 4176 } 4177 4178 /************************/ 4179 Static int 4180 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4181 { 4182 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4183 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4184 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4185 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4186 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4187 int i, k, frames; 4188 u_int huba, dir; 4189 int err; 4190 4191 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4192 4193 start = NULL; 4194 sitd = NULL; 4195 4196 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4197 xfer->ux_flags, 0); 4198 4199 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4200 KASSERT(xfer->ux_nframes != 0); 4201 KASSERT(exfer->ex_isdone); 4202 4203 exfer->ex_type = EX_FS_ISOC; 4204 /* 4205 * Step 1: Allocate and initialize sitds. 4206 */ 4207 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4208 if (i > 16 || i == 0) { 4209 /* Spec page 271 says intervals > 16 are invalid */ 4210 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4211 4212 return EINVAL; 4213 } 4214 4215 frames = xfer->ux_nframes; 4216 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4217 sitd = ehci_alloc_sitd(sc); 4218 if (sitd == NULL) { 4219 err = ENOMEM; 4220 goto fail; 4221 } 4222 4223 if (prev) 4224 prev->xfer_next = sitd; 4225 else 4226 start = sitd; 4227 4228 huba = dev->ud_myhsport->up_parent->ud_addr; 4229 4230 #if 0 4231 if (sc->sc_flags & EHCIF_FREESCALE) { 4232 // Set hub address to 0 if embedded TT is used. 4233 if (huba == sc->sc_addr) 4234 huba = 0; 4235 } 4236 #endif 4237 4238 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4239 dir = UE_GET_DIR(k) ? 1 : 0; 4240 sitd->sitd.sitd_endp = 4241 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4242 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4243 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4244 EHCI_SITD_SET_HUBA(huba) | 4245 EHCI_SITD_SET_DIR(dir)); 4246 4247 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4248 } /* End of frame */ 4249 4250 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4251 4252 stop = sitd; 4253 stop->xfer_next = NULL; 4254 exfer->ex_sitdstart = start; 4255 exfer->ex_sitdend = stop; 4256 4257 return 0; 4258 4259 fail: 4260 mutex_enter(&sc->sc_lock); 4261 ehci_soft_sitd_t *next; 4262 for (sitd = start; sitd; sitd = next) { 4263 next = sitd->xfer_next; 4264 ehci_free_sitd_locked(sc, sitd); 4265 } 4266 mutex_exit(&sc->sc_lock); 4267 4268 return err; 4269 } 4270 4271 Static void 4272 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4273 { 4274 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4275 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4276 4277 KASSERT(ex->ex_type == EX_FS_ISOC); 4278 4279 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4280 } 4281 4282 Static usbd_status 4283 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4284 { 4285 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4286 usbd_status __diagused err; 4287 4288 mutex_enter(&sc->sc_lock); 4289 err = usb_insert_transfer(xfer); 4290 mutex_exit(&sc->sc_lock); 4291 4292 KASSERT(err == USBD_NORMAL_COMPLETION); 4293 4294 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4295 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4296 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4297 ehci_soft_sitd_t *sitd; 4298 usb_dma_t *dma_buf; 4299 int i, j, k, frames; 4300 int offs; 4301 int frindex; 4302 u_int dir; 4303 4304 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4305 4306 sitd = NULL; 4307 4308 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4309 xfer->ux_flags, 0); 4310 4311 if (sc->sc_dying) 4312 return USBD_IOERROR; 4313 4314 /* 4315 * To avoid complication, don't allow a request right now that'll span 4316 * the entire frame table. To within 4 frames, to allow some leeway 4317 * on either side of where the hc currently is. 4318 */ 4319 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4320 xfer->ux_nframes >= sc->sc_flsize - 4) { 4321 printf("ehci: isoc descriptor requested that spans the entire" 4322 "frametable, too many frames\n"); 4323 return USBD_INVAL; 4324 } 4325 4326 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4327 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4328 KASSERT(exfer->ex_isdone); 4329 #ifdef DIAGNOSTIC 4330 exfer->ex_isdone = false; 4331 #endif 4332 4333 /* 4334 * Step 1: Initialize sitds. 4335 */ 4336 4337 frames = xfer->ux_nframes; 4338 dma_buf = &xfer->ux_dmabuf; 4339 offs = 0; 4340 4341 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4342 i++, sitd = sitd->xfer_next) { 4343 KASSERT(sitd != NULL); 4344 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4345 4346 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4347 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4348 4349 /* Set page0 index and offset - TP and T-offset are set below */ 4350 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4351 4352 offs += xfer->ux_frlengths[i]; 4353 4354 sitd->sitd.sitd_buffer[1] = 4355 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4356 4357 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4358 4359 #if 0 4360 if (sc->sc_flags & EHCIF_FREESCALE) { 4361 // Set hub address to 0 if embedded TT is used. 4362 if (huba == sc->sc_addr) 4363 huba = 0; 4364 } 4365 #endif 4366 4367 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4368 dir = UE_GET_DIR(k) ? 1 : 0; 4369 KASSERT(sitd->sitd.sitd_endp == htole32( 4370 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4371 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4372 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4373 EHCI_SITD_SET_HUBA(huba) | 4374 EHCI_SITD_SET_DIR(dir))); 4375 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4376 4377 uint8_t sa = 0; 4378 uint8_t sb = 0; 4379 u_int temp, tlen; 4380 4381 if (dir == 0) { /* OUT */ 4382 temp = 0; 4383 tlen = xfer->ux_frlengths[i]; 4384 if (tlen <= 188) { 4385 temp |= 1; /* T-count = 1, TP = ALL */ 4386 tlen = 1; 4387 } else { 4388 tlen += 187; 4389 tlen /= 188; 4390 temp |= tlen; /* T-count = [1..6] */ 4391 temp |= 8; /* TP = Begin */ 4392 } 4393 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4394 4395 tlen += sa; 4396 4397 if (tlen >= 8) { 4398 sb = 0; 4399 } else { 4400 sb = (1 << tlen); 4401 } 4402 4403 sa = (1 << sa); 4404 sa = (sb - sa) & 0x3F; 4405 sb = 0; 4406 } else { 4407 sb = (-(4 << sa)) & 0xFE; 4408 sa = (1 << sa) & 0x3F; 4409 sa = 0x01; 4410 sb = 0xfc; 4411 } 4412 4413 sitd->sitd.sitd_sched = htole32( 4414 EHCI_SITD_SET_SMASK(sa) | 4415 EHCI_SITD_SET_CMASK(sb) 4416 ); 4417 4418 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4420 } /* End of frame */ 4421 4422 sitd = exfer->ex_sitdend; 4423 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4424 4425 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4426 sizeof(sitd->sitd.sitd_trans), 4427 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4428 4429 if (xfer->ux_length) 4430 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4431 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4432 4433 /* 4434 * Part 2: Transfer descriptors have now been set up, now they must 4435 * be scheduled into the periodic frame list. Erk. Not wanting to 4436 * complicate matters, transfer is denied if the transfer spans 4437 * more than the period frame list. 4438 */ 4439 4440 mutex_enter(&sc->sc_lock); 4441 4442 /* Start inserting frames */ 4443 if (epipe->isoc.cur_xfers > 0) { 4444 frindex = epipe->isoc.next_frame; 4445 } else { 4446 frindex = EOREAD4(sc, EHCI_FRINDEX); 4447 frindex = frindex >> 3; /* Erase microframe index */ 4448 frindex += 2; 4449 } 4450 4451 if (frindex >= sc->sc_flsize) 4452 frindex &= (sc->sc_flsize - 1); 4453 4454 /* Whats the frame interval? */ 4455 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4456 4457 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4458 j++, sitd = sitd->xfer_next) { 4459 KASSERT(sitd); 4460 4461 usb_syncmem(&sc->sc_fldma, 4462 sizeof(ehci_link_t) * frindex, 4463 sizeof(ehci_link_t), 4464 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4465 4466 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4467 if (sitd->sitd.sitd_next == 0) 4468 /* 4469 * FIXME: frindex table gets initialized to NULL 4470 * or EHCI_NULL? 4471 */ 4472 sitd->sitd.sitd_next = EHCI_NULL; 4473 4474 usb_syncmem(&sitd->dma, 4475 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4476 sizeof(ehci_sitd_t), 4477 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4478 4479 sc->sc_flist[frindex] = 4480 htole32(EHCI_LINK_SITD | sitd->physaddr); 4481 4482 usb_syncmem(&sc->sc_fldma, 4483 sizeof(ehci_link_t) * frindex, 4484 sizeof(ehci_link_t), 4485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4486 4487 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4488 sc->sc_softsitds[frindex] = sitd; 4489 if (sitd->frame_list.next != NULL) 4490 sitd->frame_list.next->frame_list.prev = sitd; 4491 sitd->slot = frindex; 4492 sitd->frame_list.prev = NULL; 4493 4494 frindex += i; 4495 if (frindex >= sc->sc_flsize) 4496 frindex -= sc->sc_flsize; 4497 } 4498 4499 epipe->isoc.cur_xfers++; 4500 epipe->isoc.next_frame = frindex; 4501 4502 ehci_add_intr_list(sc, exfer); 4503 xfer->ux_status = USBD_IN_PROGRESS; 4504 mutex_exit(&sc->sc_lock); 4505 4506 return USBD_IN_PROGRESS; 4507 } 4508 4509 Static void 4510 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4511 { 4512 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4513 4514 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4515 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4516 } 4517 4518 Static void 4519 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4520 { 4521 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4522 4523 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4524 } 4525 4526 Static void 4527 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4528 { 4529 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4530 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4531 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4532 4533 KASSERT(mutex_owned(&sc->sc_lock)); 4534 4535 epipe->isoc.cur_xfers--; 4536 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4537 4538 if (xfer->ux_length) 4539 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4540 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4541 } 4542 4543 /* -------------------------------------------------------------------------- */ 4544 4545 Static int 4546 ehci_device_isoc_init(struct usbd_xfer *xfer) 4547 { 4548 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4549 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4550 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4551 ehci_soft_itd_t *itd, *prev, *start, *stop; 4552 int i, j, k; 4553 int frames, ufrperframe; 4554 int err; 4555 4556 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4557 4558 start = NULL; 4559 prev = NULL; 4560 itd = NULL; 4561 4562 KASSERT(xfer->ux_nframes != 0); 4563 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4564 KASSERT(exfer->ex_isdone); 4565 4566 exfer->ex_type = EX_ISOC; 4567 4568 /* 4569 * Step 1: Allocate and initialize itds, how many do we need? 4570 * One per transfer if interval >= 8 microframes, less if we use 4571 * multiple microframes per frame. 4572 */ 4573 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4574 if (i > 16 || i == 0) { 4575 /* Spec page 271 says intervals > 16 are invalid */ 4576 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4577 return USBD_INVAL; 4578 } 4579 4580 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4581 frames = howmany(xfer->ux_nframes, ufrperframe); 4582 4583 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4584 itd = ehci_alloc_itd(sc); 4585 if (itd == NULL) { 4586 err = ENOMEM; 4587 goto fail; 4588 } 4589 4590 if (prev != NULL) { 4591 /* Maybe not as it's updated by the scheduling? */ 4592 prev->itd.itd_next = 4593 htole32(itd->physaddr | EHCI_LINK_ITD); 4594 4595 prev->xfer_next = itd; 4596 } else { 4597 start = itd; 4598 } 4599 4600 /* 4601 * Other special values 4602 */ 4603 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4604 itd->itd.itd_bufr[0] = htole32( 4605 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4606 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4607 4608 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4609 ? 1 : 0; 4610 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4611 itd->itd.itd_bufr[1] |= htole32( 4612 EHCI_ITD_SET_DIR(k) | 4613 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4614 4615 /* FIXME: handle invalid trans - should be done in openpipe */ 4616 itd->itd.itd_bufr[2] |= 4617 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4618 } /* End of frame */ 4619 4620 stop = itd; 4621 stop->xfer_next = NULL; 4622 4623 exfer->ex_itdstart = start; 4624 exfer->ex_itdend = stop; 4625 4626 return 0; 4627 fail: 4628 mutex_enter(&sc->sc_lock); 4629 ehci_soft_itd_t *next; 4630 for (itd = start; itd; itd = next) { 4631 next = itd->xfer_next; 4632 ehci_free_itd_locked(sc, itd); 4633 } 4634 mutex_exit(&sc->sc_lock); 4635 4636 return err; 4637 4638 } 4639 4640 Static void 4641 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4642 { 4643 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4644 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4645 4646 KASSERT(ex->ex_type == EX_ISOC); 4647 4648 ehci_free_itd_chain(sc, ex->ex_itdstart); 4649 } 4650 4651 Static usbd_status 4652 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4653 { 4654 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4655 usbd_status __diagused err; 4656 4657 mutex_enter(&sc->sc_lock); 4658 err = usb_insert_transfer(xfer); 4659 mutex_exit(&sc->sc_lock); 4660 4661 KASSERT(err == USBD_NORMAL_COMPLETION); 4662 4663 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4664 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4665 ehci_soft_itd_t *itd, *prev; 4666 usb_dma_t *dma_buf; 4667 int i, j; 4668 int frames, uframes, ufrperframe; 4669 int trans_count, offs; 4670 int frindex; 4671 4672 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4673 4674 prev = NULL; 4675 itd = NULL; 4676 trans_count = 0; 4677 4678 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4679 4680 if (sc->sc_dying) 4681 return USBD_IOERROR; 4682 4683 /* 4684 * To avoid complication, don't allow a request right now that'll span 4685 * the entire frame table. To within 4 frames, to allow some leeway 4686 * on either side of where the hc currently is. 4687 */ 4688 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4689 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4690 DPRINTF( 4691 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4692 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4693 return USBD_INVAL; 4694 } 4695 4696 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4697 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4698 KASSERT(exfer->ex_isdone); 4699 #ifdef DIAGNOSTIC 4700 exfer->ex_isdone = false; 4701 #endif 4702 4703 /* 4704 * Step 1: Re-Initialize itds 4705 */ 4706 4707 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4708 if (i > 16 || i == 0) { 4709 /* Spec page 271 says intervals > 16 are invalid */ 4710 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4711 return USBD_INVAL; 4712 } 4713 4714 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4715 frames = howmany(xfer->ux_nframes, ufrperframe); 4716 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4717 4718 if (frames == 0) { 4719 DPRINTF("frames == 0", 0, 0, 0, 0); 4720 return USBD_INVAL; 4721 } 4722 4723 dma_buf = &xfer->ux_dmabuf; 4724 offs = 0; 4725 4726 itd = exfer->ex_itdstart; 4727 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4728 int froffs = offs; 4729 4730 if (prev != NULL) { 4731 prev->itd.itd_next = 4732 htole32(itd->physaddr | EHCI_LINK_ITD); 4733 usb_syncmem(&prev->dma, 4734 prev->offs + offsetof(ehci_itd_t, itd_next), 4735 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4736 prev->xfer_next = itd; 4737 } 4738 4739 /* 4740 * Step 1.5, initialize uframes 4741 */ 4742 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4743 /* Calculate which page in the list this starts in */ 4744 int addr = DMAADDR(dma_buf, froffs); 4745 addr = EHCI_PAGE_OFFSET(addr); 4746 addr += (offs - froffs); 4747 addr = EHCI_PAGE(addr); 4748 addr /= EHCI_PAGE_SIZE; 4749 4750 /* 4751 * This gets the initial offset into the first page, 4752 * looks how far further along the current uframe 4753 * offset is. Works out how many pages that is. 4754 */ 4755 4756 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4757 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4758 EHCI_ITD_SET_PG(addr) | 4759 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4760 4761 offs += xfer->ux_frlengths[trans_count]; 4762 trans_count++; 4763 4764 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4765 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4766 break; 4767 } 4768 } 4769 4770 /* 4771 * Step 1.75, set buffer pointers. To simplify matters, all 4772 * pointers are filled out for the next 7 hardware pages in 4773 * the dma block, so no need to worry what pages to cover 4774 * and what to not. 4775 */ 4776 4777 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4778 /* 4779 * Don't try to lookup a page that's past the end 4780 * of buffer 4781 */ 4782 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4783 if (page_offs >= dma_buf->udma_block->size) 4784 break; 4785 4786 uint64_t page = DMAADDR(dma_buf, page_offs); 4787 page = EHCI_PAGE(page); 4788 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4789 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4790 } 4791 /* 4792 * Other special values 4793 */ 4794 4795 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4796 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4797 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4798 4799 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4800 ? 1 : 0; 4801 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4802 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4803 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4804 4805 /* FIXME: handle invalid trans */ 4806 itd->itd.itd_bufr[2] |= 4807 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4808 4809 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4810 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4811 4812 prev = itd; 4813 } /* End of frame */ 4814 4815 if (xfer->ux_length) 4816 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4817 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4818 4819 /* 4820 * Part 2: Transfer descriptors have now been set up, now they must 4821 * be scheduled into the period frame list. Erk. Not wanting to 4822 * complicate matters, transfer is denied if the transfer spans 4823 * more than the period frame list. 4824 */ 4825 4826 mutex_enter(&sc->sc_lock); 4827 4828 /* Start inserting frames */ 4829 if (epipe->isoc.cur_xfers > 0) { 4830 frindex = epipe->isoc.next_frame; 4831 } else { 4832 frindex = EOREAD4(sc, EHCI_FRINDEX); 4833 frindex = frindex >> 3; /* Erase microframe index */ 4834 frindex += 2; 4835 } 4836 4837 if (frindex >= sc->sc_flsize) 4838 frindex &= (sc->sc_flsize - 1); 4839 4840 /* What's the frame interval? */ 4841 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4842 if (i / USB_UFRAMES_PER_FRAME == 0) 4843 i = 1; 4844 else 4845 i /= USB_UFRAMES_PER_FRAME; 4846 4847 itd = exfer->ex_itdstart; 4848 for (j = 0; j < frames; j++) { 4849 KASSERTMSG(itd != NULL, "frame %d\n", j); 4850 4851 usb_syncmem(&sc->sc_fldma, 4852 sizeof(ehci_link_t) * frindex, 4853 sizeof(ehci_link_t), 4854 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4855 4856 itd->itd.itd_next = sc->sc_flist[frindex]; 4857 if (itd->itd.itd_next == 0) 4858 /* 4859 * FIXME: frindex table gets initialized to NULL 4860 * or EHCI_NULL? 4861 */ 4862 itd->itd.itd_next = EHCI_NULL; 4863 4864 usb_syncmem(&itd->dma, 4865 itd->offs + offsetof(ehci_itd_t, itd_next), 4866 sizeof(itd->itd.itd_next), 4867 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4868 4869 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4870 4871 usb_syncmem(&sc->sc_fldma, 4872 sizeof(ehci_link_t) * frindex, 4873 sizeof(ehci_link_t), 4874 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4875 4876 itd->frame_list.next = sc->sc_softitds[frindex]; 4877 sc->sc_softitds[frindex] = itd; 4878 if (itd->frame_list.next != NULL) 4879 itd->frame_list.next->frame_list.prev = itd; 4880 itd->slot = frindex; 4881 itd->frame_list.prev = NULL; 4882 4883 frindex += i; 4884 if (frindex >= sc->sc_flsize) 4885 frindex -= sc->sc_flsize; 4886 4887 itd = itd->xfer_next; 4888 } 4889 4890 epipe->isoc.cur_xfers++; 4891 epipe->isoc.next_frame = frindex; 4892 4893 ehci_add_intr_list(sc, exfer); 4894 xfer->ux_status = USBD_IN_PROGRESS; 4895 mutex_exit(&sc->sc_lock); 4896 4897 return USBD_IN_PROGRESS; 4898 } 4899 4900 Static void 4901 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4902 { 4903 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4904 4905 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4906 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4907 } 4908 4909 Static void 4910 ehci_device_isoc_close(struct usbd_pipe *pipe) 4911 { 4912 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4913 4914 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4915 } 4916 4917 Static void 4918 ehci_device_isoc_done(struct usbd_xfer *xfer) 4919 { 4920 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4921 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4922 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4923 4924 KASSERT(mutex_owned(&sc->sc_lock)); 4925 4926 epipe->isoc.cur_xfers--; 4927 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4928 if (xfer->ux_length) 4929 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4930 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4931 } 4932
Indexes created Mon Sep 22 13:09:51 GMT 2025