ehci.c revision 1.293
1 /* $NetBSD: ehci.c,v 1.293 2021/12/21 09:51:22 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna.com.au), and 11 * Nick Hudson . 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 37 * 38 * The EHCI 1.0 spec can be found at 39 * http://www.intel.com/technology/usb/spec.htm 40 * and the USB 2.0 spec at 41 * http://www.usb.org/developers/docs/ 42 * 43 */ 44 45 /* 46 * TODO: 47 * 1) hold off explorations by companion controllers until ehci has started. 48 * 49 * 2) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 3) Command failures are not recovered correctly. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.293 2021/12/21 09:51:22 skrll Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #ifdef _KERNEL_OPT 63 #include "opt_usb.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #include <sys/bus.h> 69 #include <sys/cpu.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/kmem.h> 73 #include <sys/mutex.h> 74 #include <sys/proc.h> 75 #include <sys/queue.h> 76 #include <sys/select.h> 77 #include <sys/sysctl.h> 78 #include <sys/systm.h> 79 #include <sys/reboot.h> 80 81 #include <machine/endian.h> 82 83 #include <dev/usb/usb.h> 84 #include <dev/usb/usbdi.h> 85 #include <dev/usb/usbdivar.h> 86 #include <dev/usb/usbhist.h> 87 #include <dev/usb/usb_mem.h> 88 #include <dev/usb/usb_quirks.h> 89 90 #include <dev/usb/ehcireg.h> 91 #include <dev/usb/ehcivar.h> 92 #include <dev/usb/usbroothub.h> 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 static int ehcidebug = 0; 99 100 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 101 { 102 int err; 103 const struct sysctlnode *rnode; 104 const struct sysctlnode *cnode; 105 106 err = sysctl_createv(clog, 0, NULL, &rnode, 107 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 108 SYSCTL_DESCR("ehci global controls"), 109 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 110 111 if (err) 112 goto fail; 113 114 /* control debugging printfs */ 115 err = sysctl_createv(clog, 0, &rnode, &cnode, 116 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 117 "debug", SYSCTL_DESCR("Enable debugging output"), 118 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 119 if (err) 120 goto fail; 121 122 return; 123 fail: 124 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 125 } 126 127 #endif /* EHCI_DEBUG */ 128 #endif /* USB_DEBUG */ 129 130 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 131 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 132 #define EHCIHIST_FUNC() USBHIST_FUNC() 133 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 134 135 struct ehci_pipe { 136 struct usbd_pipe pipe; 137 int nexttoggle; 138 139 ehci_soft_qh_t *sqh; 140 union { 141 /* Control pipe */ 142 struct { 143 usb_dma_t reqdma; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 u_int length; 148 } intr; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 }; 155 }; 156 157 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 158 159 Static usbd_status ehci_open(struct usbd_pipe *); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_intrlist_timeout(void *); 171 Static void ehci_doorbell(void *); 172 Static void ehci_pcd(void *); 173 174 Static struct usbd_xfer * 175 ehci_allocx(struct usbd_bus *, unsigned int); 176 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 177 178 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 179 Static bool ehci_dying(struct usbd_bus *); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abortx(struct usbd_xfer *); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_abortx = ehci_abortx, 323 .ubm_dying = ehci_dying, 324 .ubm_getlock = ehci_get_lock, 325 .ubm_rhctrl = ehci_roothub_ctrl, 326 }; 327 328 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 329 .upm_transfer = ehci_root_intr_transfer, 330 .upm_start = ehci_root_intr_start, 331 .upm_abort = ehci_root_intr_abort, 332 .upm_close = ehci_root_intr_close, 333 .upm_cleartoggle = ehci_noop, 334 .upm_done = ehci_root_intr_done, 335 }; 336 337 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 338 .upm_init = ehci_device_ctrl_init, 339 .upm_fini = ehci_device_ctrl_fini, 340 .upm_transfer = ehci_device_ctrl_transfer, 341 .upm_start = ehci_device_ctrl_start, 342 .upm_abort = ehci_device_ctrl_abort, 343 .upm_close = ehci_device_ctrl_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_ctrl_done, 346 }; 347 348 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 349 .upm_init = ehci_device_intr_init, 350 .upm_fini = ehci_device_intr_fini, 351 .upm_transfer = ehci_device_intr_transfer, 352 .upm_start = ehci_device_intr_start, 353 .upm_abort = ehci_device_intr_abort, 354 .upm_close = ehci_device_intr_close, 355 .upm_cleartoggle = ehci_device_clear_toggle, 356 .upm_done = ehci_device_intr_done, 357 }; 358 359 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 360 .upm_init = ehci_device_bulk_init, 361 .upm_fini = ehci_device_bulk_fini, 362 .upm_transfer = ehci_device_bulk_transfer, 363 .upm_start = ehci_device_bulk_start, 364 .upm_abort = ehci_device_bulk_abort, 365 .upm_close = ehci_device_bulk_close, 366 .upm_cleartoggle = ehci_device_clear_toggle, 367 .upm_done = ehci_device_bulk_done, 368 }; 369 370 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 371 .upm_init = ehci_device_isoc_init, 372 .upm_fini = ehci_device_isoc_fini, 373 .upm_transfer = ehci_device_isoc_transfer, 374 .upm_abort = ehci_device_isoc_abort, 375 .upm_close = ehci_device_isoc_close, 376 .upm_cleartoggle = ehci_noop, 377 .upm_done = ehci_device_isoc_done, 378 }; 379 380 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 381 .upm_init = ehci_device_fs_isoc_init, 382 .upm_fini = ehci_device_fs_isoc_fini, 383 .upm_transfer = ehci_device_fs_isoc_transfer, 384 .upm_abort = ehci_device_fs_isoc_abort, 385 .upm_close = ehci_device_fs_isoc_close, 386 .upm_cleartoggle = ehci_noop, 387 .upm_done = ehci_device_fs_isoc_done, 388 }; 389 390 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 391 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 392 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 393 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 394 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 395 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 396 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 397 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 398 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 399 }; 400 401 int 402 ehci_init(ehci_softc_t *sc) 403 { 404 uint32_t vers, hcr; 405 u_int i; 406 int err; 407 ehci_soft_qh_t *sqh; 408 u_int ncomp; 409 410 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 411 #ifdef EHCI_DEBUG 412 theehci = sc; 413 #endif 414 415 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 416 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 417 cv_init(&sc->sc_doorbell, "ehcidb"); 418 419 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 420 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 421 422 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 423 ehci_doorbell, sc); 424 KASSERT(sc->sc_doorbell_si != NULL); 425 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 426 ehci_pcd, sc); 427 KASSERT(sc->sc_pcd_si != NULL); 428 429 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 430 431 vers = EREAD2(sc, EHCI_HCIVERSION); 432 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 433 vers >> 8, vers & 0xff); 434 435 const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS); 436 DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0); 437 sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams); 438 ncomp = EHCI_HCS_N_CC(hcsparams); 439 if (ncomp != sc->sc_ncomp) { 440 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 441 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 442 #if NOHCI == 0 || NUHCI == 0 443 aprint_error("%s: ohci or uhci probably not configured\n", 444 device_xname(sc->sc_dev)); 445 #endif 446 if (ncomp < sc->sc_ncomp) 447 sc->sc_ncomp = ncomp; 448 } 449 if (sc->sc_ncomp > 0) { 450 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 451 aprint_normal_dev(sc->sc_dev, 452 "%d companion controller%s, %d port%s%s", 453 sc->sc_ncomp, 454 sc->sc_ncomp!=1 ? "s" : "", 455 EHCI_HCS_N_PCC(hcsparams), 456 EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "", 457 sc->sc_ncomp!=1 ? " each" : ""); 458 if (sc->sc_comps[0]) { 459 aprint_normal(":"); 460 for (i = 0; i < sc->sc_ncomp; i++) 461 aprint_normal(" %s", 462 device_xname(sc->sc_comps[i])); 463 } 464 aprint_normal("\n"); 465 466 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 467 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 468 cv_init(&sc->sc_compcv, "ehciccv"); 469 sc->sc_comp_state = CO_EARLY; 470 } 471 sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams); 472 sc->sc_hasppc = EHCI_HCS_PPC(hcsparams); 473 474 const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS); 475 DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0); 476 477 if (EHCI_HCC_64BIT(hccparams)) { 478 /* MUST clear segment register if 64 bit capable. */ 479 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 480 } 481 482 if (hccparams & EHCI_HCC_IST_FULLFRAME) { 483 sc->sc_istthreshold = 0; 484 } else { 485 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams); 486 } 487 488 sc->sc_bus.ub_revision = USBREV_2_0; 489 sc->sc_bus.ub_usedma = true; 490 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 491 492 /* Reset the controller */ 493 DPRINTF("resetting", 0, 0, 0, 0); 494 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 495 usb_delay_ms(&sc->sc_bus, 1); 496 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 497 for (i = 0; i < 100; i++) { 498 usb_delay_ms(&sc->sc_bus, 1); 499 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 500 if (!hcr) 501 break; 502 } 503 if (hcr) { 504 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 505 return EIO; 506 } 507 if (sc->sc_vendor_init) 508 sc->sc_vendor_init(sc); 509 510 /* XXX need proper intr scheduling */ 511 sc->sc_rand = 96; 512 513 /* frame list size at default, read back what we got and use that */ 514 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 515 case 0: sc->sc_flsize = 1024; break; 516 case 1: sc->sc_flsize = 512; break; 517 case 2: sc->sc_flsize = 256; break; 518 case 3: return EIO; 519 } 520 err = usb_allocmem(sc->sc_bus.ub_dmatag, 521 sc->sc_flsize * sizeof(ehci_link_t), 522 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 523 if (err) 524 return err; 525 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 526 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 527 528 for (i = 0; i < sc->sc_flsize; i++) { 529 sc->sc_flist[i] = EHCI_NULL; 530 } 531 532 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 533 534 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 535 KM_SLEEP); 536 LIST_INIT(&sc->sc_freeitds); 537 LIST_INIT(&sc->sc_freesitds); 538 TAILQ_INIT(&sc->sc_intrhead); 539 540 /* Set up the bus struct. */ 541 sc->sc_bus.ub_methods = &ehci_bus_methods; 542 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 543 544 sc->sc_eintrs = EHCI_NORMAL_INTRS; 545 546 /* 547 * Allocate the interrupt dummy QHs. These are arranged to give poll 548 * intervals that are powers of 2 times 1ms. 549 */ 550 for (i = 0; i < EHCI_INTRQHS; i++) { 551 sqh = ehci_alloc_sqh(sc); 552 if (sqh == NULL) { 553 err = ENOMEM; 554 goto bad1; 555 } 556 sc->sc_islots[i].sqh = sqh; 557 } 558 for (i = 0; i < EHCI_INTRQHS; i++) { 559 sqh = sc->sc_islots[i].sqh; 560 if (i == 0) { 561 /* The last (1ms) QH terminates. */ 562 sqh->qh.qh_link = EHCI_NULL; 563 sqh->next = NULL; 564 } else { 565 /* Otherwise the next QH has half the poll interval */ 566 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 567 sqh->qh.qh_link = htole32(sqh->next->physaddr | 568 EHCI_LINK_QH); 569 } 570 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 571 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 572 sqh->qh.qh_curqtd = EHCI_NULL; 573 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 574 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 575 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 576 sqh->sqtd = NULL; 577 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 578 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 579 } 580 /* Point the frame list at the last level (128ms). */ 581 for (i = 0; i < sc->sc_flsize; i++) { 582 int j; 583 584 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 585 revbits[i & (EHCI_MAX_POLLRATE-1)]; 586 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 587 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 588 i)].sqh->physaddr); 589 } 590 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 591 BUS_DMASYNC_PREWRITE); 592 593 /* Allocate dummy QH that starts the async list. */ 594 sqh = ehci_alloc_sqh(sc); 595 if (sqh == NULL) { 596 err = ENOMEM; 597 goto bad1; 598 } 599 /* Fill the QH */ 600 sqh->qh.qh_endp = 601 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 602 sqh->qh.qh_link = 603 htole32(sqh->physaddr | EHCI_LINK_QH); 604 sqh->qh.qh_curqtd = EHCI_NULL; 605 sqh->next = NULL; 606 /* Fill the overlay qTD */ 607 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 608 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 609 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 610 sqh->sqtd = NULL; 611 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 612 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 613 #ifdef EHCI_DEBUG 614 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 615 ehci_dump_sqh(sqh); 616 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 617 #endif 618 619 /* Point to async list */ 620 sc->sc_async_head = sqh; 621 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 622 623 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 624 625 /* Turn on controller */ 626 EOWRITE4(sc, EHCI_USBCMD, 627 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 628 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 629 EHCI_CMD_ASE | 630 EHCI_CMD_PSE | 631 EHCI_CMD_RS); 632 633 /* Take over port ownership */ 634 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 635 636 for (i = 0; i < 100; i++) { 637 usb_delay_ms(&sc->sc_bus, 1); 638 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 639 if (!hcr) 640 break; 641 } 642 if (hcr) { 643 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 644 return EIO; 645 } 646 647 /* Enable interrupts */ 648 DPRINTF("enabling interrupts", 0, 0, 0, 0); 649 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 650 651 return 0; 652 653 #if 0 654 bad2: 655 ehci_free_sqh(sc, sc->sc_async_head); 656 #endif 657 bad1: 658 usb_freemem(&sc->sc_fldma); 659 return err; 660 } 661 662 int 663 ehci_intr(void *v) 664 { 665 ehci_softc_t *sc = v; 666 int ret = 0; 667 668 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 669 670 if (sc == NULL) 671 return 0; 672 673 mutex_spin_enter(&sc->sc_intr_lock); 674 675 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 676 goto done; 677 678 /* If we get an interrupt while polling, then just ignore it. */ 679 if (sc->sc_bus.ub_usepolling) { 680 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 681 682 if (intrs) 683 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 684 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 685 goto done; 686 } 687 688 ret = ehci_intr1(sc); 689 690 done: 691 mutex_spin_exit(&sc->sc_intr_lock); 692 return ret; 693 } 694 695 Static int 696 ehci_intr1(ehci_softc_t *sc) 697 { 698 uint32_t intrs, eintrs; 699 700 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 701 702 /* In case the interrupt occurs before initialization has completed. */ 703 if (sc == NULL) { 704 #ifdef DIAGNOSTIC 705 printf("ehci_intr1: sc == NULL\n"); 706 #endif 707 return 0; 708 } 709 710 KASSERT(mutex_owned(&sc->sc_intr_lock)); 711 712 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 713 if (!intrs) 714 return 0; 715 716 eintrs = intrs & sc->sc_eintrs; 717 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 718 EOREAD4(sc, EHCI_USBSTS), eintrs); 719 if (!eintrs) 720 return 0; 721 722 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 723 if (eintrs & EHCI_STS_IAA) { 724 DPRINTF("door bell", 0, 0, 0, 0); 725 kpreempt_disable(); 726 KASSERT(sc->sc_doorbell_si != NULL); 727 softint_schedule(sc->sc_doorbell_si); 728 kpreempt_enable(); 729 eintrs &= ~EHCI_STS_IAA; 730 } 731 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 732 DPRINTF("INT=%jd ERRINT=%jd", 733 eintrs & EHCI_STS_INT ? 1 : 0, 734 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 735 usb_schedsoftintr(&sc->sc_bus); 736 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 737 } 738 if (eintrs & EHCI_STS_HSE) { 739 printf("%s: unrecoverable error, controller halted\n", 740 device_xname(sc->sc_dev)); 741 /* XXX what else */ 742 } 743 if (eintrs & EHCI_STS_PCD) { 744 kpreempt_disable(); 745 KASSERT(sc->sc_pcd_si != NULL); 746 softint_schedule(sc->sc_pcd_si); 747 kpreempt_enable(); 748 eintrs &= ~EHCI_STS_PCD; 749 } 750 751 if (eintrs != 0) { 752 /* Block unprocessed interrupts. */ 753 sc->sc_eintrs &= ~eintrs; 754 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 755 printf("%s: blocking intrs %#x\n", 756 device_xname(sc->sc_dev), eintrs); 757 } 758 759 return 1; 760 } 761 762 Static void 763 ehci_doorbell(void *addr) 764 { 765 ehci_softc_t *sc = addr; 766 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 cv_broadcast(&sc->sc_doorbell); 770 mutex_exit(&sc->sc_lock); 771 } 772 773 Static void 774 ehci_pcd(void *addr) 775 { 776 ehci_softc_t *sc = addr; 777 struct usbd_xfer *xfer; 778 u_char *p; 779 int i, m; 780 781 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 782 783 mutex_enter(&sc->sc_lock); 784 xfer = sc->sc_intrxfer; 785 786 if (xfer == NULL) { 787 /* Just ignore the change. */ 788 goto done; 789 } 790 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 791 792 p = xfer->ux_buf; 793 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 794 memset(p, 0, xfer->ux_length); 795 for (i = 1; i <= m; i++) { 796 /* Pick out CHANGE bits from the status reg. */ 797 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 798 p[i/8] |= 1 << (i%8); 799 if (i % 8 == 7) 800 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 801 } 802 xfer->ux_actlen = xfer->ux_length; 803 xfer->ux_status = USBD_NORMAL_COMPLETION; 804 805 usb_transfer_complete(xfer); 806 807 done: 808 mutex_exit(&sc->sc_lock); 809 } 810 811 Static void 812 ehci_softintr(void *v) 813 { 814 struct usbd_bus *bus = v; 815 ehci_softc_t *sc = EHCI_BUS2SC(bus); 816 struct ehci_xfer *ex, *nextex; 817 818 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 819 820 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 821 822 ex_completeq_t cq; 823 TAILQ_INIT(&cq); 824 825 /* 826 * The only explanation I can think of for why EHCI is as brain dead 827 * as UHCI interrupt-wise is that Intel was involved in both. 828 * An interrupt just tells us that something is done, we have no 829 * clue what, so we need to scan through all active transfers. :-( 830 */ 831 832 /* 833 * ehci_idone will remove transfer from sc->sc_intrhead if it's 834 * complete and add to our cq list 835 * 836 */ 837 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 838 switch (ex->ex_type) { 839 case EX_CTRL: 840 case EX_BULK: 841 case EX_INTR: 842 ehci_check_qh_intr(sc, ex, &cq); 843 break; 844 case EX_ISOC: 845 ehci_check_itd_intr(sc, ex, &cq); 846 break; 847 case EX_FS_ISOC: 848 ehci_check_sitd_intr(sc, ex, &cq); 849 break; 850 default: 851 KASSERT(false); 852 } 853 854 } 855 856 /* 857 * We abuse ex_next for the interrupt and complete lists and 858 * interrupt transfers will get re-added here so use 859 * the _SAFE version of TAILQ_FOREACH. 860 */ 861 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 862 usb_transfer_complete(&ex->ex_xfer); 863 } 864 865 /* Schedule a callout to catch any dropped transactions. */ 866 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 867 !TAILQ_EMPTY(&sc->sc_intrhead)) 868 callout_reset(&sc->sc_tmo_intrlist, 869 hz, ehci_intrlist_timeout, sc); 870 } 871 872 Static void 873 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 874 { 875 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 876 uint32_t status; 877 878 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 879 880 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 881 882 if (ex->ex_type == EX_CTRL) { 883 fsqtd = ex->ex_setup; 884 lsqtd = ex->ex_status; 885 } else { 886 fsqtd = ex->ex_sqtdstart; 887 lsqtd = ex->ex_sqtdend; 888 } 889 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 890 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 891 892 /* 893 * If the last TD is still active we need to check whether there 894 * is an error somewhere in the middle, or whether there was a 895 * short packet (SPD and not ACTIVE). 896 */ 897 usb_syncmem(&lsqtd->dma, 898 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 899 sizeof(lsqtd->qtd.qtd_status), 900 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 901 status = le32toh(lsqtd->qtd.qtd_status); 902 usb_syncmem(&lsqtd->dma, 903 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 904 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 905 if (status & EHCI_QTD_ACTIVE) { 906 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 907 908 /* last qTD has already been checked */ 909 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 910 usb_syncmem(&sqtd->dma, 911 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 912 sizeof(sqtd->qtd.qtd_status), 913 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 914 status = le32toh(sqtd->qtd.qtd_status); 915 usb_syncmem(&sqtd->dma, 916 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 917 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 918 /* If there's an active QTD the xfer isn't done. */ 919 if (status & EHCI_QTD_ACTIVE) 920 break; 921 /* Any kind of error makes the xfer done. */ 922 if (status & EHCI_QTD_HALTED) 923 goto done; 924 /* Handle short packets */ 925 if (EHCI_QTD_GET_BYTES(status) != 0) { 926 /* 927 * If we get here for a control transfer then 928 * we need to let the hardware complete the 929 * status phase. That is, we're not done 930 * quite yet. 931 * 932 * Otherwise, we're done. 933 */ 934 if (ex->ex_type == EX_CTRL) { 935 break; 936 } 937 goto done; 938 } 939 } 940 DPRINTFN(10, "ex=%#jx std=%#jx still active", 941 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 942 #ifdef EHCI_DEBUG 943 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 944 ehci_dump_sqtds(ex->ex_sqtdstart); 945 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 946 #endif 947 return; 948 } 949 done: 950 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 951 ehci_idone(ex, cq); 952 } 953 954 Static void 955 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 956 { 957 ehci_soft_itd_t *itd; 958 int i; 959 960 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 961 962 KASSERT(mutex_owned(&sc->sc_lock)); 963 964 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 965 return; 966 967 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 968 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 969 970 itd = ex->ex_itdend; 971 972 /* 973 * check no active transfers in last itd, meaning we're finished 974 */ 975 976 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 977 sizeof(itd->itd.itd_ctl), 978 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 979 980 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 981 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 982 break; 983 } 984 985 if (i == EHCI_ITD_NUFRAMES) { 986 goto done; /* All 8 descriptors inactive, it's done */ 987 } 988 989 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 990 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 991 992 DPRINTFN(10, "ex %#jx itd %#jx still active", 993 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 994 return; 995 done: 996 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 997 ehci_idone(ex, cq); 998 } 999 1000 void 1001 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1002 { 1003 ehci_soft_sitd_t *sitd; 1004 1005 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1006 1007 KASSERT(mutex_owned(&sc->sc_lock)); 1008 1009 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1010 return; 1011 1012 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1013 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1014 1015 sitd = ex->ex_sitdend; 1016 1017 /* 1018 * check no active transfers in last sitd, meaning we're finished 1019 */ 1020 1021 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1022 sizeof(sitd->sitd.sitd_trans), 1023 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1024 1025 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1026 1027 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1028 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1029 1030 if (active) 1031 return; 1032 1033 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1034 ehci_idone(ex, cq); 1035 } 1036 1037 Static void 1038 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1039 { 1040 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1041 struct usbd_xfer *xfer = &ex->ex_xfer; 1042 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1043 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1044 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1045 uint32_t status = 0, nstatus = 0; 1046 int actlen = 0; 1047 1048 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1049 1050 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1051 1052 /* 1053 * Try to claim this xfer for completion. If it has already 1054 * completed or aborted, drop it on the floor. 1055 */ 1056 if (!usbd_xfer_trycomplete(xfer)) 1057 return; 1058 1059 #ifdef DIAGNOSTIC 1060 #ifdef EHCI_DEBUG 1061 if (ex->ex_isdone) { 1062 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1063 ehci_dump_exfer(ex); 1064 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1065 } 1066 #endif 1067 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1068 ex->ex_type, xfer->ux_status); 1069 ex->ex_isdone = true; 1070 #endif 1071 1072 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1073 (uintptr_t)epipe, 0, 0); 1074 1075 /* The transfer is done, compute actual length and status. */ 1076 if (ex->ex_type == EX_ISOC) { 1077 /* HS isoc transfer */ 1078 1079 struct ehci_soft_itd *itd; 1080 int i, nframes, len, uframes; 1081 1082 nframes = 0; 1083 1084 #ifdef EHCI_DEBUG 1085 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1086 ehci_dump_itds(ex->ex_itdstart); 1087 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1088 #endif 1089 1090 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1091 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1092 1093 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1094 usb_syncmem(&itd->dma, 1095 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1096 sizeof(itd->itd.itd_ctl), 1097 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1098 1099 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1100 /* 1101 * XXX - driver didn't fill in the frame full 1102 * of uframes. This leads to scheduling 1103 * inefficiencies, but working around 1104 * this doubles complexity of tracking 1105 * an xfer. 1106 */ 1107 if (nframes >= xfer->ux_nframes) 1108 break; 1109 1110 status = le32toh(itd->itd.itd_ctl[i]); 1111 len = EHCI_ITD_GET_LEN(status); 1112 if (EHCI_ITD_GET_STATUS(status) != 0) 1113 len = 0; /*No valid data on error*/ 1114 1115 xfer->ux_frlengths[nframes++] = len; 1116 actlen += len; 1117 } 1118 usb_syncmem(&itd->dma, 1119 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1120 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1121 1122 if (nframes >= xfer->ux_nframes) 1123 break; 1124 } 1125 1126 xfer->ux_actlen = actlen; 1127 xfer->ux_status = USBD_NORMAL_COMPLETION; 1128 goto end; 1129 } else if (ex->ex_type == EX_FS_ISOC) { 1130 /* FS isoc transfer */ 1131 struct ehci_soft_sitd *sitd; 1132 int nframes, len; 1133 1134 nframes = 0; 1135 1136 for (sitd = ex->ex_sitdstart; sitd != NULL; 1137 sitd = sitd->xfer_next) { 1138 usb_syncmem(&sitd->dma, 1139 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1140 sizeof(sitd->sitd.sitd_trans), 1141 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1142 1143 /* 1144 * XXX - driver didn't fill in the frame full 1145 * of uframes. This leads to scheduling 1146 * inefficiencies, but working around 1147 * this doubles complexity of tracking 1148 * an xfer. 1149 */ 1150 if (nframes >= xfer->ux_nframes) 1151 break; 1152 1153 status = le32toh(sitd->sitd.sitd_trans); 1154 usb_syncmem(&sitd->dma, 1155 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1156 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1157 1158 len = EHCI_SITD_GET_LEN(status); 1159 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1160 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1161 /* No valid data on error */ 1162 len = xfer->ux_frlengths[nframes]; 1163 } 1164 1165 /* 1166 * frlengths[i]: # of bytes to send 1167 * len: # of bytes host didn't send 1168 */ 1169 xfer->ux_frlengths[nframes] -= len; 1170 /* frlengths[i]: # of bytes host sent */ 1171 actlen += xfer->ux_frlengths[nframes++]; 1172 1173 if (nframes >= xfer->ux_nframes) 1174 break; 1175 } 1176 1177 xfer->ux_actlen = actlen; 1178 xfer->ux_status = USBD_NORMAL_COMPLETION; 1179 goto end; 1180 } 1181 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1182 ex->ex_type == EX_BULK); 1183 1184 /* Continue processing xfers using queue heads */ 1185 if (ex->ex_type == EX_CTRL) { 1186 fsqtd = ex->ex_setup; 1187 lsqtd = ex->ex_status; 1188 } else { 1189 fsqtd = ex->ex_sqtdstart; 1190 lsqtd = ex->ex_sqtdend; 1191 } 1192 #ifdef EHCI_DEBUG 1193 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1194 ehci_dump_sqtds(fsqtd); 1195 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1196 #endif 1197 1198 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1199 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1200 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1201 nstatus = le32toh(sqtd->qtd.qtd_status); 1202 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1203 BUS_DMASYNC_PREREAD); 1204 if (nstatus & EHCI_QTD_ACTIVE) 1205 break; 1206 1207 status = nstatus; 1208 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1209 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1210 } 1211 1212 /* 1213 * If there are left over TDs we need to update the toggle. 1214 * The default pipe doesn't need it since control transfers 1215 * start the toggle at 0 every time. 1216 * For a short transfer we need to update the toggle for the missing 1217 * packets within the qTD. 1218 */ 1219 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1220 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1221 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1222 status, nstatus, 0, 0); 1223 #if 0 1224 ehci_dump_sqh(epipe->sqh); 1225 ehci_dump_sqtds(ex->ex_sqtdstart); 1226 #endif 1227 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1228 } 1229 1230 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1231 status, 0); 1232 xfer->ux_actlen = actlen; 1233 if (status & EHCI_QTD_HALTED) { 1234 #ifdef EHCI_DEBUG 1235 DPRINTF("halted addr=%jd endpt=0x%02jx", 1236 xfer->ux_pipe->up_dev->ud_addr, 1237 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1238 0, 0); 1239 DPRINTF("cerr=%jd pid=%jd", 1240 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1241 0, 0); 1242 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1243 status & EHCI_QTD_ACTIVE ? 1 : 0, 1244 status & EHCI_QTD_HALTED ? 1 : 0, 1245 status & EHCI_QTD_BUFERR ? 1 : 0, 1246 status & EHCI_QTD_BABBLE ? 1 : 0); 1247 1248 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1249 status & EHCI_QTD_XACTERR ? 1 : 0, 1250 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1251 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1252 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1253 1254 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1255 ehci_dump_sqh(epipe->sqh); 1256 ehci_dump_sqtds(ex->ex_sqtdstart); 1257 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1258 #endif 1259 /* low&full speed has an extra error flag */ 1260 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1261 EHCI_QH_SPEED_HIGH) 1262 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1263 else 1264 status &= EHCI_QTD_STATERRS; 1265 if (status == 0) /* no other errors means a stall */ { 1266 xfer->ux_status = USBD_STALLED; 1267 } else { 1268 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1269 } 1270 /* XXX need to reset TT on missed microframe */ 1271 if (status & EHCI_QTD_MISSEDMICRO) { 1272 printf("%s: missed microframe, TT reset not " 1273 "implemented, hub might be inoperational\n", 1274 device_xname(sc->sc_dev)); 1275 } 1276 } else { 1277 xfer->ux_status = USBD_NORMAL_COMPLETION; 1278 } 1279 1280 end: 1281 1282 ehci_del_intr_list(sc, ex); 1283 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1284 1285 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1286 } 1287 1288 Static void 1289 ehci_poll(struct usbd_bus *bus) 1290 { 1291 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1292 1293 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1294 1295 #ifdef EHCI_DEBUG 1296 static int last; 1297 int new; 1298 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1299 if (new != last) { 1300 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1301 last = new; 1302 } 1303 #endif 1304 1305 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1306 mutex_spin_enter(&sc->sc_intr_lock); 1307 ehci_intr1(sc); 1308 mutex_spin_exit(&sc->sc_intr_lock); 1309 } 1310 } 1311 1312 void 1313 ehci_childdet(device_t self, device_t child) 1314 { 1315 struct ehci_softc *sc = device_private(self); 1316 1317 KASSERT(sc->sc_child == child); 1318 sc->sc_child = NULL; 1319 } 1320 1321 int 1322 ehci_detach(struct ehci_softc *sc, int flags) 1323 { 1324 int rv = 0; 1325 1326 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1327 1328 if (sc->sc_child != NULL) { 1329 rv = config_detach(sc->sc_child, flags); 1330 if (rv != 0) 1331 return rv; 1332 } 1333 1334 if (sc->sc_ncomp > 0) { 1335 mutex_enter(&sc->sc_complock); 1336 /* XXX try to halt callout instead of waiting */ 1337 while (sc->sc_comp_state == CO_SCHED) 1338 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1339 mutex_exit(&sc->sc_complock); 1340 1341 callout_halt(&sc->sc_compcallout, NULL); 1342 callout_destroy(&sc->sc_compcallout); 1343 cv_destroy(&sc->sc_compcv); 1344 mutex_destroy(&sc->sc_complock); 1345 } 1346 1347 callout_halt(&sc->sc_tmo_intrlist, NULL); 1348 callout_destroy(&sc->sc_tmo_intrlist); 1349 1350 /* XXX free other data structures */ 1351 if (sc->sc_softitds) { 1352 kmem_free(sc->sc_softitds, 1353 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1354 } 1355 cv_destroy(&sc->sc_doorbell); 1356 1357 #if 0 1358 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1359 softint_disestablish(sc->sc_doorbell_si); 1360 softint_disestablish(sc->sc_pcd_si); 1361 mutex_destroy(&sc->sc_lock); 1362 mutex_destroy(&sc->sc_intr_lock); 1363 #endif 1364 1365 pool_cache_destroy(sc->sc_xferpool); 1366 1367 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1368 1369 return rv; 1370 } 1371 1372 int 1373 ehci_activate(device_t self, enum devact act) 1374 { 1375 struct ehci_softc *sc = device_private(self); 1376 1377 switch (act) { 1378 case DVACT_DEACTIVATE: 1379 sc->sc_dying = 1; 1380 return 0; 1381 default: 1382 return EOPNOTSUPP; 1383 } 1384 } 1385 1386 /* 1387 * Handle suspend/resume. 1388 * 1389 * Note that this power handler isn't to be registered directly; the 1390 * bus glue needs to call out to it. 1391 */ 1392 bool 1393 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1394 { 1395 ehci_softc_t *sc = device_private(dv); 1396 int i; 1397 uint32_t cmd, hcr; 1398 1399 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1400 1401 mutex_enter(&sc->sc_lock); 1402 1403 for (i = 1; i <= sc->sc_noport; i++) { 1404 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1405 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1406 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1407 } 1408 1409 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1410 1411 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1412 EOWRITE4(sc, EHCI_USBCMD, cmd); 1413 1414 for (i = 0; i < 100; i++) { 1415 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1416 if (hcr == 0) 1417 break; 1418 1419 usb_delay_ms(&sc->sc_bus, 1); 1420 } 1421 if (hcr != 0) 1422 printf("%s: reset timeout\n", device_xname(dv)); 1423 1424 cmd &= ~EHCI_CMD_RS; 1425 EOWRITE4(sc, EHCI_USBCMD, cmd); 1426 1427 for (i = 0; i < 100; i++) { 1428 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1429 if (hcr == EHCI_STS_HCH) 1430 break; 1431 1432 usb_delay_ms(&sc->sc_bus, 1); 1433 } 1434 if (hcr != EHCI_STS_HCH) 1435 printf("%s: config timeout\n", device_xname(dv)); 1436 1437 mutex_exit(&sc->sc_lock); 1438 1439 return true; 1440 } 1441 1442 bool 1443 ehci_resume(device_t dv, const pmf_qual_t *qual) 1444 { 1445 ehci_softc_t *sc = device_private(dv); 1446 int i; 1447 uint32_t cmd, hcr; 1448 1449 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1450 1451 mutex_enter(&sc->sc_lock); 1452 1453 /* restore things in case the bios sucks */ 1454 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1455 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1456 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1457 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1458 1459 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1460 1461 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1462 1463 hcr = 0; 1464 for (i = 1; i <= sc->sc_noport; i++) { 1465 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1466 if ((cmd & EHCI_PS_PO) == 0 && 1467 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1468 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1469 hcr = 1; 1470 } 1471 } 1472 1473 if (hcr) { 1474 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1475 1476 for (i = 1; i <= sc->sc_noport; i++) { 1477 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1478 if ((cmd & EHCI_PS_PO) == 0 && 1479 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1480 EOWRITE4(sc, EHCI_PORTSC(i), 1481 cmd & ~EHCI_PS_FPR); 1482 } 1483 } 1484 1485 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1486 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1487 1488 for (i = 0; i < 100; i++) { 1489 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1490 if (hcr != EHCI_STS_HCH) 1491 break; 1492 1493 usb_delay_ms(&sc->sc_bus, 1); 1494 } 1495 if (hcr == EHCI_STS_HCH) 1496 printf("%s: config timeout\n", device_xname(dv)); 1497 1498 mutex_exit(&sc->sc_lock); 1499 1500 return true; 1501 } 1502 1503 /* 1504 * Shut down the controller when the system is going down. 1505 */ 1506 bool 1507 ehci_shutdown(device_t self, int flags) 1508 { 1509 ehci_softc_t *sc = device_private(self); 1510 1511 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1512 1513 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1514 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1515 return true; 1516 } 1517 1518 Static struct usbd_xfer * 1519 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1520 { 1521 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1522 struct usbd_xfer *xfer; 1523 1524 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1525 if (xfer != NULL) { 1526 memset(xfer, 0, sizeof(struct ehci_xfer)); 1527 1528 #ifdef DIAGNOSTIC 1529 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1530 ex->ex_isdone = true; 1531 xfer->ux_state = XFER_BUSY; 1532 #endif 1533 } 1534 return xfer; 1535 } 1536 1537 Static void 1538 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1539 { 1540 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1541 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1542 1543 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1544 xfer->ux_status == USBD_NOT_STARTED, 1545 "xfer %p state %d\n", xfer, xfer->ux_state); 1546 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1547 1548 #ifdef DIAGNOSTIC 1549 xfer->ux_state = XFER_FREE; 1550 #endif 1551 1552 pool_cache_put(sc->sc_xferpool, xfer); 1553 } 1554 1555 Static bool 1556 ehci_dying(struct usbd_bus *bus) 1557 { 1558 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1559 1560 return sc->sc_dying; 1561 } 1562 1563 Static void 1564 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1565 { 1566 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1567 1568 *lock = &sc->sc_lock; 1569 } 1570 1571 Static void 1572 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1573 { 1574 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1575 1576 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1577 1578 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1579 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1580 #ifdef EHCI_DEBUG 1581 if (ehcidebug) 1582 usbd_dump_pipe(pipe); 1583 #endif 1584 epipe->nexttoggle = 0; 1585 } 1586 1587 Static void 1588 ehci_noop(struct usbd_pipe *pipe) 1589 { 1590 } 1591 1592 #ifdef EHCI_DEBUG 1593 /* 1594 * Unused function - this is meant to be called from a kernel 1595 * debugger. 1596 */ 1597 void 1598 ehci_dump(void) 1599 { 1600 ehci_softc_t *sc = theehci; 1601 int i; 1602 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1603 EOREAD4(sc, EHCI_USBCMD), 1604 EOREAD4(sc, EHCI_USBSTS), 1605 EOREAD4(sc, EHCI_USBINTR)); 1606 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1607 EOREAD4(sc, EHCI_FRINDEX), 1608 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1609 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1610 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1611 for (i = 1; i <= sc->sc_noport; i++) 1612 printf("port %d status=0x%08x\n", i, 1613 EOREAD4(sc, EHCI_PORTSC(i))); 1614 } 1615 1616 Static void 1617 ehci_dump_regs(ehci_softc_t *sc) 1618 { 1619 int i; 1620 1621 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1622 1623 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1624 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1625 EOREAD4(sc, EHCI_USBINTR), 0); 1626 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1627 "async = 0x%08jx", 1628 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1629 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1630 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1631 for (i = 1; i <= sc->sc_noport; i += 2) { 1632 if (i == sc->sc_noport) { 1633 DPRINTF("port %jd status = 0x%08jx", i, 1634 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1635 } else { 1636 DPRINTF("port %jd status = 0x%08jx port %jd " 1637 "status = 0x%08jx", 1638 i, EOREAD4(sc, EHCI_PORTSC(i)), 1639 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1640 } 1641 } 1642 } 1643 1644 #define ehci_dump_link(link, type) do { \ 1645 DPRINTF(" link 0x%08jx (T = %jd):", \ 1646 link, \ 1647 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1648 if (type) { \ 1649 DPRINTF( \ 1650 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1651 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1652 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1653 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1654 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1655 } \ 1656 } while(0) 1657 1658 Static void 1659 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1660 { 1661 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1662 int i; 1663 uint32_t stop = 0; 1664 1665 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1666 ehci_dump_sqtd(sqtd); 1667 usb_syncmem(&sqtd->dma, 1668 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1669 sizeof(sqtd->qtd), 1670 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1671 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1672 usb_syncmem(&sqtd->dma, 1673 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1674 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1675 } 1676 if (!stop) 1677 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1678 } 1679 1680 Static void 1681 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1682 { 1683 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1684 1685 usb_syncmem(&sqtd->dma, sqtd->offs, 1686 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1687 1688 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1689 0, 0); 1690 ehci_dump_qtd(&sqtd->qtd); 1691 1692 usb_syncmem(&sqtd->dma, sqtd->offs, 1693 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1694 } 1695 1696 Static void 1697 ehci_dump_qtd(ehci_qtd_t *qtd) 1698 { 1699 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1700 uint32_t s = le32toh(qtd->qtd_status); 1701 1702 DPRINTFN(10, 1703 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1704 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1705 DPRINTFN(10, 1706 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1707 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1708 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1709 DPRINTFN(10, 1710 " cerr = %jd pid = %jd stat = %jx", 1711 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1712 0); 1713 DPRINTFN(10, 1714 "active =%jd halted=%jd buferr=%jd babble=%jd", 1715 s & EHCI_QTD_ACTIVE ? 1 : 0, 1716 s & EHCI_QTD_HALTED ? 1 : 0, 1717 s & EHCI_QTD_BUFERR ? 1 : 0, 1718 s & EHCI_QTD_BABBLE ? 1 : 0); 1719 DPRINTFN(10, 1720 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1721 s & EHCI_QTD_XACTERR ? 1 : 0, 1722 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1723 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1724 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1725 DPRINTFN(10, 1726 "buffer[0] = %#jx buffer[1] = %#jx " 1727 "buffer[2] = %#jx buffer[3] = %#jx", 1728 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1729 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1730 DPRINTFN(10, 1731 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1732 } 1733 1734 Static void 1735 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1736 { 1737 ehci_qh_t *qh = &sqh->qh; 1738 ehci_link_t link; 1739 uint32_t endp, endphub; 1740 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1741 1742 usb_syncmem(&sqh->dma, sqh->offs, 1743 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1744 1745 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1746 link = le32toh(qh->qh_link); 1747 ehci_dump_link(link, true); 1748 1749 endp = le32toh(qh->qh_endp); 1750 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1751 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1752 "eps = %jd", 1753 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1754 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1755 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1756 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1757 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1758 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1759 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1760 1761 endphub = le32toh(qh->qh_endphub); 1762 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1763 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1764 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1765 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1766 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1767 EHCI_QH_GET_MULT(endphub), 0); 1768 1769 link = le32toh(qh->qh_curqtd); 1770 ehci_dump_link(link, false); 1771 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1772 ehci_dump_qtd(&qh->qh_qtd); 1773 1774 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1775 BUS_DMASYNC_PREREAD); 1776 } 1777 1778 Static void 1779 ehci_dump_itds(ehci_soft_itd_t *itd) 1780 { 1781 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1782 int i; 1783 uint32_t stop = 0; 1784 1785 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1786 ehci_dump_itd(itd); 1787 usb_syncmem(&itd->dma, 1788 itd->offs + offsetof(ehci_itd_t, itd_next), 1789 sizeof(itd->itd), 1790 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1791 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1792 usb_syncmem(&itd->dma, 1793 itd->offs + offsetof(ehci_itd_t, itd_next), 1794 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1795 } 1796 if (!stop) 1797 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1798 } 1799 1800 Static void 1801 ehci_dump_itd(struct ehci_soft_itd *itd) 1802 { 1803 ehci_isoc_trans_t t; 1804 ehci_isoc_bufr_ptr_t b, b2, b3; 1805 int i; 1806 1807 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1808 1809 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1810 1811 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1812 t = le32toh(itd->itd.itd_ctl[i]); 1813 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1814 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1815 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1816 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1817 EHCI_ITD_GET_OFFS(t), 0); 1818 } 1819 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1820 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1821 DPRINTF(" %jx", 1822 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1823 1824 b = le32toh(itd->itd.itd_bufr[0]); 1825 b2 = le32toh(itd->itd.itd_bufr[1]); 1826 b3 = le32toh(itd->itd.itd_bufr[2]); 1827 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1828 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1829 DPRINTF(" maxpkt = %jx multi = %jx", 1830 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1831 } 1832 1833 Static void 1834 ehci_dump_sitd(struct ehci_soft_itd *itd) 1835 { 1836 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1837 1838 DPRINTF("SITD %#jx next = %p prev = %#jx", 1839 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1840 (uintptr_t)itd->frame_list.prev, 0); 1841 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1842 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1843 } 1844 1845 Static void 1846 ehci_dump_exfer(struct ehci_xfer *ex) 1847 { 1848 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1849 1850 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1851 ex->ex_isdone, 0); 1852 1853 switch (ex->ex_type) { 1854 case EX_CTRL: 1855 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1856 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1857 (uintptr_t)ex->ex_status, 0); 1858 break; 1859 case EX_BULK: 1860 case EX_INTR: 1861 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1862 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1863 0, 0); 1864 break; 1865 case EX_ISOC: 1866 DPRINTF(" itdstart = %#jx itdend = %#jx", 1867 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1868 break; 1869 case EX_FS_ISOC: 1870 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1871 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1872 0, 0); 1873 break; 1874 default: 1875 DPRINTF(" unknown type", 0, 0, 0, 0); 1876 } 1877 } 1878 #endif 1879 1880 Static usbd_status 1881 ehci_open(struct usbd_pipe *pipe) 1882 { 1883 struct usbd_device *dev = pipe->up_dev; 1884 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1885 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1886 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1887 uint8_t addr = dev->ud_addr; 1888 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1889 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1890 ehci_soft_qh_t *sqh; 1891 usbd_status err; 1892 int ival, speed, naks; 1893 int hshubaddr, hshubport; 1894 1895 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1896 1897 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1898 ed->bEndpointAddress, rhaddr); 1899 1900 if (dev->ud_myhsport) { 1901 /* 1902 * When directly attached FS/LS device while doing embedded 1903 * transaction translations and we are the hub, set the hub 1904 * address to 0 (us). 1905 */ 1906 if (!(sc->sc_flags & EHCIF_ETTF) 1907 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1908 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1909 } else { 1910 hshubaddr = 0; 1911 } 1912 hshubport = dev->ud_myhsport->up_portno; 1913 } else { 1914 hshubaddr = 0; 1915 hshubport = 0; 1916 } 1917 1918 if (sc->sc_dying) 1919 return USBD_IOERROR; 1920 1921 /* toggle state needed for bulk endpoints */ 1922 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1923 1924 if (addr == rhaddr) { 1925 switch (ed->bEndpointAddress) { 1926 case USB_CONTROL_ENDPOINT: 1927 pipe->up_methods = &roothub_ctrl_methods; 1928 break; 1929 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1930 pipe->up_methods = &ehci_root_intr_methods; 1931 break; 1932 default: 1933 DPRINTF("bad bEndpointAddress 0x%02jx", 1934 ed->bEndpointAddress, 0, 0, 0); 1935 return USBD_INVAL; 1936 } 1937 return USBD_NORMAL_COMPLETION; 1938 } 1939 1940 /* XXX All this stuff is only valid for async. */ 1941 switch (dev->ud_speed) { 1942 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1943 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1944 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1945 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1946 } 1947 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1948 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1949 0); 1950 return USBD_INVAL; 1951 } 1952 1953 /* 1954 * For interrupt transfer, nak throttling must be disabled, but for 1955 * the other transfer type, nak throttling should be enabled from the 1956 * viewpoint that avoids the memory thrashing. 1957 */ 1958 naks = (xfertype == UE_INTERRUPT) ? 0 1959 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1960 1961 /* Allocate sqh for everything, save isoc xfers */ 1962 if (xfertype != UE_ISOCHRONOUS) { 1963 sqh = ehci_alloc_sqh(sc); 1964 if (sqh == NULL) 1965 return USBD_NOMEM; 1966 /* qh_link filled when the QH is added */ 1967 sqh->qh.qh_endp = htole32( 1968 EHCI_QH_SET_ADDR(addr) | 1969 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1970 EHCI_QH_SET_EPS(speed) | 1971 EHCI_QH_DTC | 1972 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1973 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1974 EHCI_QH_CTL : 0) | 1975 EHCI_QH_SET_NRL(naks) 1976 ); 1977 sqh->qh.qh_endphub = htole32( 1978 EHCI_QH_SET_MULT(1) | 1979 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1980 ); 1981 if (speed != EHCI_QH_SPEED_HIGH) 1982 sqh->qh.qh_endphub |= htole32( 1983 EHCI_QH_SET_PORT(hshubport) | 1984 EHCI_QH_SET_HUBA(hshubaddr) | 1985 (xfertype == UE_INTERRUPT ? 1986 EHCI_QH_SET_CMASK(0x08) : 0) 1987 ); 1988 sqh->qh.qh_curqtd = EHCI_NULL; 1989 /* Fill the overlay qTD */ 1990 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1991 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1992 sqh->qh.qh_qtd.qtd_status = htole32(0); 1993 1994 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1995 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1996 epipe->sqh = sqh; 1997 } else { 1998 sqh = NULL; 1999 } /*xfertype == UE_ISOC*/ 2000 2001 switch (xfertype) { 2002 case UE_CONTROL: 2003 err = usb_allocmem(sc->sc_bus.ub_dmatag, sizeof(usb_device_request_t), 2004 0, USBMALLOC_COHERENT, &epipe->ctrl.reqdma); 2005 #ifdef EHCI_DEBUG 2006 if (err) 2007 printf("ehci_open: usb_allocmem()=%d\n", err); 2008 #endif 2009 if (err) 2010 goto bad; 2011 pipe->up_methods = &ehci_device_ctrl_methods; 2012 mutex_enter(&sc->sc_lock); 2013 ehci_add_qh(sc, sqh, sc->sc_async_head); 2014 mutex_exit(&sc->sc_lock); 2015 break; 2016 case UE_BULK: 2017 pipe->up_methods = &ehci_device_bulk_methods; 2018 mutex_enter(&sc->sc_lock); 2019 ehci_add_qh(sc, sqh, sc->sc_async_head); 2020 mutex_exit(&sc->sc_lock); 2021 break; 2022 case UE_INTERRUPT: 2023 pipe->up_methods = &ehci_device_intr_methods; 2024 ival = pipe->up_interval; 2025 if (ival == USBD_DEFAULT_INTERVAL) { 2026 if (speed == EHCI_QH_SPEED_HIGH) { 2027 if (ed->bInterval > 16) { 2028 /* 2029 * illegal with high-speed, but there 2030 * were documentation bugs in the spec, 2031 * so be generous 2032 */ 2033 ival = 256; 2034 } else 2035 ival = (1 << (ed->bInterval - 1)) / 8; 2036 } else 2037 ival = ed->bInterval; 2038 } 2039 err = ehci_device_setintr(sc, sqh, ival); 2040 if (err) 2041 goto bad; 2042 break; 2043 case UE_ISOCHRONOUS: 2044 pipe->up_serialise = false; 2045 if (speed == EHCI_QH_SPEED_HIGH) 2046 pipe->up_methods = &ehci_device_isoc_methods; 2047 else 2048 pipe->up_methods = &ehci_device_fs_isoc_methods; 2049 if (ed->bInterval == 0 || ed->bInterval > 16) { 2050 printf("ehci: opening pipe with invalid bInterval\n"); 2051 err = USBD_INVAL; 2052 goto bad; 2053 } 2054 if (UGETW(ed->wMaxPacketSize) == 0) { 2055 printf("ehci: zero length endpoint open request\n"); 2056 err = USBD_INVAL; 2057 goto bad; 2058 } 2059 epipe->isoc.next_frame = 0; 2060 epipe->isoc.cur_xfers = 0; 2061 break; 2062 default: 2063 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2064 err = USBD_INVAL; 2065 goto bad; 2066 } 2067 return USBD_NORMAL_COMPLETION; 2068 2069 bad: 2070 if (sqh != NULL) { 2071 mutex_enter(&sc->sc_lock); 2072 ehci_free_sqh(sc, sqh); 2073 mutex_exit(&sc->sc_lock); 2074 } 2075 return err; 2076 } 2077 2078 /* 2079 * Add an ED to the schedule. Called with USB lock held. 2080 */ 2081 Static void 2082 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2083 { 2084 2085 KASSERT(mutex_owned(&sc->sc_lock)); 2086 2087 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2088 2089 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2090 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2091 2092 sqh->next = head->next; 2093 sqh->qh.qh_link = head->qh.qh_link; 2094 2095 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2096 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2097 2098 head->next = sqh; 2099 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2100 2101 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2102 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2103 2104 #ifdef EHCI_DEBUG 2105 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2106 ehci_dump_sqh(sqh); 2107 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2108 #endif 2109 } 2110 2111 /* 2112 * Remove an ED from the schedule. Called with USB lock held. 2113 */ 2114 Static void 2115 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2116 { 2117 ehci_soft_qh_t *p; 2118 2119 KASSERT(mutex_owned(&sc->sc_lock)); 2120 2121 /* XXX */ 2122 for (p = head; p != NULL && p->next != sqh; p = p->next) 2123 ; 2124 if (p == NULL) 2125 panic("ehci_rem_qh: ED not found"); 2126 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2127 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2128 p->next = sqh->next; 2129 p->qh.qh_link = sqh->qh.qh_link; 2130 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2131 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2132 2133 ehci_sync_hc(sc); 2134 } 2135 2136 Static void 2137 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2138 { 2139 int i; 2140 uint32_t status; 2141 2142 /* Save toggle bit and ping status. */ 2143 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2144 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2145 status = sqh->qh.qh_qtd.qtd_status & 2146 htole32(EHCI_QTD_TOGGLE_MASK | 2147 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2148 /* Set HALTED to make hw leave it alone. */ 2149 sqh->qh.qh_qtd.qtd_status = 2150 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2151 usb_syncmem(&sqh->dma, 2152 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2153 sizeof(sqh->qh.qh_qtd.qtd_status), 2154 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2155 sqh->qh.qh_curqtd = 0; 2156 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2157 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2158 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2159 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2160 sqh->sqtd = sqtd; 2161 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2163 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2164 sqh->qh.qh_qtd.qtd_status = status; 2165 usb_syncmem(&sqh->dma, 2166 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2167 sizeof(sqh->qh.qh_qtd.qtd_status), 2168 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2169 } 2170 2171 /* 2172 * Ensure that the HC has released all references to the QH. We do this 2173 * by asking for a Async Advance Doorbell interrupt and then we wait for 2174 * the interrupt. 2175 * To make this easier we first obtain exclusive use of the doorbell. 2176 */ 2177 Static void 2178 ehci_sync_hc(ehci_softc_t *sc) 2179 { 2180 int error __diagused; 2181 2182 KASSERT(mutex_owned(&sc->sc_lock)); 2183 2184 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2185 2186 if (sc->sc_dying) { 2187 DPRINTF("dying", 0, 0, 0, 0); 2188 return; 2189 } 2190 2191 /* ask for doorbell */ 2192 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2193 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2194 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2195 2196 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2197 2198 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2199 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2200 #ifdef DIAGNOSTIC 2201 if (error == EWOULDBLOCK) { 2202 printf("ehci_sync_hc: timed out\n"); 2203 } else if (error) { 2204 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2205 } 2206 #endif 2207 } 2208 2209 Static void 2210 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2211 { 2212 2213 KASSERT(mutex_owned(&sc->sc_lock)); 2214 2215 for (; itd != NULL; itd = itd->xfer_next) { 2216 struct ehci_soft_itd *prev = itd->frame_list.prev; 2217 2218 /* Unlink itd from hardware chain, or frame array */ 2219 if (prev == NULL) { /* We're at the table head */ 2220 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2221 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2222 usb_syncmem(&sc->sc_fldma, 2223 sizeof(ehci_link_t) * itd->slot, 2224 sizeof(ehci_link_t), 2225 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2226 2227 if (itd->frame_list.next != NULL) 2228 itd->frame_list.next->frame_list.prev = NULL; 2229 } else { 2230 /* XXX this part is untested... */ 2231 prev->itd.itd_next = itd->itd.itd_next; 2232 usb_syncmem(&itd->dma, 2233 itd->offs + offsetof(ehci_itd_t, itd_next), 2234 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2235 2236 prev->frame_list.next = itd->frame_list.next; 2237 if (itd->frame_list.next != NULL) 2238 itd->frame_list.next->frame_list.prev = prev; 2239 } 2240 } 2241 } 2242 2243 Static void 2244 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2245 { 2246 struct ehci_soft_itd *next; 2247 2248 mutex_enter(&sc->sc_lock); 2249 next = NULL; 2250 for (; itd != NULL; itd = next) { 2251 next = itd->xfer_next; 2252 ehci_free_itd_locked(sc, itd); 2253 } 2254 mutex_exit(&sc->sc_lock); 2255 } 2256 2257 Static void 2258 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2259 { 2260 2261 KASSERT(mutex_owned(&sc->sc_lock)); 2262 2263 for (; sitd != NULL; sitd = sitd->xfer_next) { 2264 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2265 2266 /* Unlink sitd from hardware chain, or frame array */ 2267 if (prev == NULL) { /* We're at the table head */ 2268 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2269 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2270 usb_syncmem(&sc->sc_fldma, 2271 sizeof(ehci_link_t) * sitd->slot, 2272 sizeof(ehci_link_t), 2273 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2274 2275 if (sitd->frame_list.next != NULL) 2276 sitd->frame_list.next->frame_list.prev = NULL; 2277 } else { 2278 /* XXX this part is untested... */ 2279 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2280 usb_syncmem(&sitd->dma, 2281 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2282 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2283 2284 prev->frame_list.next = sitd->frame_list.next; 2285 if (sitd->frame_list.next != NULL) 2286 sitd->frame_list.next->frame_list.prev = prev; 2287 } 2288 } 2289 } 2290 2291 Static void 2292 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2293 { 2294 2295 mutex_enter(&sc->sc_lock); 2296 struct ehci_soft_sitd *next = NULL; 2297 for (; sitd != NULL; sitd = next) { 2298 next = sitd->xfer_next; 2299 ehci_free_sitd_locked(sc, sitd); 2300 } 2301 mutex_exit(&sc->sc_lock); 2302 } 2303 2304 /***********/ 2305 2306 Static int 2307 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2308 void *buf, int buflen) 2309 { 2310 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2311 usb_hub_descriptor_t hubd; 2312 usb_port_status_t ps; 2313 uint16_t len, value, index; 2314 int l, totlen = 0; 2315 int port, i; 2316 uint32_t v; 2317 2318 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2319 2320 if (sc->sc_dying) 2321 return -1; 2322 2323 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2324 0, 0); 2325 2326 len = UGETW(req->wLength); 2327 value = UGETW(req->wValue); 2328 index = UGETW(req->wIndex); 2329 2330 #define C(x,y) ((x) | ((y) << 8)) 2331 switch (C(req->bRequest, req->bmRequestType)) { 2332 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2333 if (len == 0) 2334 break; 2335 switch (value) { 2336 #define sd ((usb_string_descriptor_t *)buf) 2337 case C(2, UDESC_STRING): 2338 /* Product */ 2339 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2340 break; 2341 #undef sd 2342 default: 2343 /* default from usbroothub */ 2344 return buflen; 2345 } 2346 break; 2347 2348 /* Hub requests */ 2349 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2350 break; 2351 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2352 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2353 value, 0, 0); 2354 if (index < 1 || index > sc->sc_noport) { 2355 return -1; 2356 } 2357 port = EHCI_PORTSC(index); 2358 v = EOREAD4(sc, port); 2359 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2360 v &= ~EHCI_PS_CLEAR; 2361 switch (value) { 2362 case UHF_PORT_ENABLE: 2363 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2364 break; 2365 case UHF_PORT_SUSPEND: 2366 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2367 break; 2368 v &= ~EHCI_PS_SUSP; 2369 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2370 /* see USB2 spec ch. 7.1.7.7 */ 2371 usb_delay_ms(&sc->sc_bus, 20); 2372 EOWRITE4(sc, port, v); 2373 usb_delay_ms(&sc->sc_bus, 2); 2374 #ifdef DEBUG 2375 v = EOREAD4(sc, port); 2376 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2377 printf("ehci: resume failed: %x\n", v); 2378 #endif 2379 break; 2380 case UHF_PORT_POWER: 2381 if (sc->sc_hasppc) 2382 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2383 break; 2384 case UHF_PORT_TEST: 2385 DPRINTF("clear port test %jd", index, 0, 0, 0); 2386 break; 2387 case UHF_PORT_INDICATOR: 2388 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2389 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2390 break; 2391 case UHF_C_PORT_CONNECTION: 2392 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2393 break; 2394 case UHF_C_PORT_ENABLE: 2395 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2396 break; 2397 case UHF_C_PORT_SUSPEND: 2398 /* how? */ 2399 break; 2400 case UHF_C_PORT_OVER_CURRENT: 2401 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2402 break; 2403 case UHF_C_PORT_RESET: 2404 sc->sc_isreset[index] = 0; 2405 break; 2406 default: 2407 return -1; 2408 } 2409 #if 0 2410 switch(value) { 2411 case UHF_C_PORT_CONNECTION: 2412 case UHF_C_PORT_ENABLE: 2413 case UHF_C_PORT_SUSPEND: 2414 case UHF_C_PORT_OVER_CURRENT: 2415 case UHF_C_PORT_RESET: 2416 default: 2417 break; 2418 } 2419 #endif 2420 break; 2421 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2422 if (len == 0) 2423 break; 2424 if ((value & 0xff) != 0) { 2425 return -1; 2426 } 2427 totlen = uimin(buflen, sizeof(hubd)); 2428 memcpy(&hubd, buf, totlen); 2429 hubd.bNbrPorts = sc->sc_noport; 2430 v = EREAD4(sc, EHCI_HCSPARAMS); 2431 USETW(hubd.wHubCharacteristics, 2432 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2433 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2434 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2435 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2436 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2437 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2438 totlen = uimin(totlen, hubd.bDescLength); 2439 memcpy(buf, &hubd, totlen); 2440 break; 2441 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2442 if (len != 4) { 2443 return -1; 2444 } 2445 memset(buf, 0, len); /* ? XXX */ 2446 totlen = len; 2447 break; 2448 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2449 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2450 if (index < 1 || index > sc->sc_noport) { 2451 return -1; 2452 } 2453 if (len != 4) { 2454 return -1; 2455 } 2456 v = EOREAD4(sc, EHCI_PORTSC(index)); 2457 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2458 2459 i = UPS_HIGH_SPEED; 2460 if (sc->sc_flags & EHCIF_ETTF) { 2461 /* 2462 * If we are doing embedded transaction translation, 2463 * then directly attached LS/FS devices are reset by 2464 * the EHCI controller itself. PSPD is encoded 2465 * the same way as in USBSTATUS. 2466 */ 2467 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2468 } 2469 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2470 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2471 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2472 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2473 if (v & EHCI_PS_PR) i |= UPS_RESET; 2474 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2475 if (sc->sc_vendor_port_status) 2476 i = sc->sc_vendor_port_status(sc, v, i); 2477 USETW(ps.wPortStatus, i); 2478 i = 0; 2479 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2480 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2481 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2482 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2483 USETW(ps.wPortChange, i); 2484 totlen = uimin(len, sizeof(ps)); 2485 memcpy(buf, &ps, totlen); 2486 break; 2487 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2488 return -1; 2489 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2490 break; 2491 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2492 if (index < 1 || index > sc->sc_noport) { 2493 return -1; 2494 } 2495 port = EHCI_PORTSC(index); 2496 v = EOREAD4(sc, port); 2497 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2498 v &= ~EHCI_PS_CLEAR; 2499 switch(value) { 2500 case UHF_PORT_ENABLE: 2501 EOWRITE4(sc, port, v | EHCI_PS_PE); 2502 break; 2503 case UHF_PORT_SUSPEND: 2504 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2505 break; 2506 case UHF_PORT_RESET: 2507 DPRINTF("reset port %jd", index, 0, 0, 0); 2508 if (EHCI_PS_IS_LOWSPEED(v) 2509 && sc->sc_ncomp > 0 2510 && !(sc->sc_flags & EHCIF_ETTF)) { 2511 /* 2512 * Low speed device on non-ETTF controller or 2513 * unaccompanied controller, give up ownership. 2514 */ 2515 ehci_disown(sc, index, 1); 2516 break; 2517 } 2518 /* Start reset sequence. */ 2519 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2520 EOWRITE4(sc, port, v | EHCI_PS_PR); 2521 /* Wait for reset to complete. */ 2522 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2523 if (sc->sc_dying) { 2524 return -1; 2525 } 2526 /* 2527 * An embedded transaction translator will automatically 2528 * terminate the reset sequence so there's no need to 2529 * it. 2530 */ 2531 v = EOREAD4(sc, port); 2532 if (v & EHCI_PS_PR) { 2533 /* Terminate reset sequence. */ 2534 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2535 /* Wait for HC to complete reset. */ 2536 usb_delay_ms(&sc->sc_bus, 2537 EHCI_PORT_RESET_COMPLETE); 2538 if (sc->sc_dying) { 2539 return -1; 2540 } 2541 } 2542 2543 v = EOREAD4(sc, port); 2544 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2545 if (v & EHCI_PS_PR) { 2546 printf("%s: port reset timeout\n", 2547 device_xname(sc->sc_dev)); 2548 return USBD_TIMEOUT; 2549 } 2550 if (!(v & EHCI_PS_PE)) { 2551 /* Not a high speed device, give up ownership.*/ 2552 ehci_disown(sc, index, 0); 2553 break; 2554 } 2555 sc->sc_isreset[index] = 1; 2556 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2557 v, 0, 0); 2558 break; 2559 case UHF_PORT_POWER: 2560 DPRINTF("set port power %jd (has PPC = %jd)", index, 2561 sc->sc_hasppc, 0, 0); 2562 if (sc->sc_hasppc) 2563 EOWRITE4(sc, port, v | EHCI_PS_PP); 2564 break; 2565 case UHF_PORT_TEST: 2566 DPRINTF("set port test %jd", index, 0, 0, 0); 2567 break; 2568 case UHF_PORT_INDICATOR: 2569 DPRINTF("set port ind %jd", index, 0, 0, 0); 2570 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2571 break; 2572 default: 2573 return -1; 2574 } 2575 break; 2576 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2577 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2578 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2579 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2580 break; 2581 default: 2582 /* default from usbroothub */ 2583 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2584 2585 return buflen; 2586 } 2587 2588 DPRINTF("returning %jd", totlen, 0, 0, 0); 2589 2590 return totlen; 2591 } 2592 2593 /* 2594 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2595 * 2596 * This pile of garbage below works around the following problem without 2597 * holding boots with no hand-over devices present, while penalising 2598 * boots where the first ehci probe hands off devices with a 5 second 2599 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2600 * for RB_SINGLE, but the same basic issue exists. 2601 * 2602 * The way ehci hand-off works, the companion controller does not get the 2603 * device until after its initial bus explore, so the reference dropped 2604 * after the first explore is not enough. 5 seconds should be enough, 2605 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2606 * 2607 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2608 * if the callback is scheduled. CO_DONE is set when the callout has 2609 * called config_pending_decr(). 2610 * 2611 * There's a mutex, a cv and a callout here, and we delay detach if the 2612 * callout has been set. 2613 */ 2614 #ifndef EHCI_DISOWN_DELAY_SECONDS 2615 #define EHCI_DISOWN_DELAY_SECONDS 5 2616 #endif 2617 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2618 2619 static void 2620 ehci_disown_callback(void *arg) 2621 { 2622 ehci_softc_t *sc = arg; 2623 2624 config_pending_decr(sc->sc_dev); 2625 2626 mutex_enter(&sc->sc_complock); 2627 KASSERT(sc->sc_comp_state == CO_SCHED); 2628 sc->sc_comp_state = CO_DONE; 2629 cv_signal(&sc->sc_compcv); 2630 mutex_exit(&sc->sc_complock); 2631 } 2632 2633 static void 2634 ehci_disown_sched_callback(ehci_softc_t *sc) 2635 { 2636 extern bool root_is_mounted; 2637 2638 mutex_enter(&sc->sc_complock); 2639 2640 if (root_is_mounted || 2641 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2642 sc->sc_comp_state != CO_EARLY) { 2643 mutex_exit(&sc->sc_complock); 2644 return; 2645 } 2646 2647 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2648 ehci_disown_callback, &sc->sc_dev); 2649 sc->sc_comp_state = CO_SCHED; 2650 2651 mutex_exit(&sc->sc_complock); 2652 2653 config_pending_incr(sc->sc_dev); 2654 aprint_normal("delaying %s by %u seconds due to USB owner change.\n", 2655 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user", 2656 ehci_disown_delay_seconds); 2657 } 2658 2659 Static void 2660 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2661 { 2662 int port; 2663 uint32_t v; 2664 2665 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2666 2667 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2668 if (sc->sc_npcomp != 0) { 2669 int i = (index-1) / sc->sc_npcomp; 2670 if (i < sc->sc_ncomp) { 2671 ehci_disown_sched_callback(sc); 2672 #ifdef DIAGNOSTIC 2673 printf("%s: handing over %s speed device on " 2674 "port %d to %s\n", 2675 device_xname(sc->sc_dev), 2676 lowspeed ? "low" : "full", 2677 index, sc->sc_comps[i] ? 2678 device_xname(sc->sc_comps[i]) : 2679 "companion controller"); 2680 } else { 2681 printf("%s: strange port\n", 2682 device_xname(sc->sc_dev)); 2683 #endif 2684 } 2685 } else { 2686 #ifdef DIAGNOSTIC 2687 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2688 #endif 2689 } 2690 port = EHCI_PORTSC(index); 2691 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2692 EOWRITE4(sc, port, v | EHCI_PS_PO); 2693 } 2694 2695 Static usbd_status 2696 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2697 { 2698 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2699 usbd_status err; 2700 2701 /* Insert last in queue. */ 2702 mutex_enter(&sc->sc_lock); 2703 err = usb_insert_transfer(xfer); 2704 mutex_exit(&sc->sc_lock); 2705 if (err) 2706 return err; 2707 2708 /* Pipe isn't running, start first */ 2709 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2710 } 2711 2712 Static usbd_status 2713 ehci_root_intr_start(struct usbd_xfer *xfer) 2714 { 2715 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2716 const bool polling = sc->sc_bus.ub_usepolling; 2717 2718 if (sc->sc_dying) 2719 return USBD_IOERROR; 2720 2721 if (!polling) 2722 mutex_enter(&sc->sc_lock); 2723 KASSERT(sc->sc_intrxfer == NULL); 2724 sc->sc_intrxfer = xfer; 2725 xfer->ux_status = USBD_IN_PROGRESS; 2726 if (!polling) 2727 mutex_exit(&sc->sc_lock); 2728 2729 return USBD_IN_PROGRESS; 2730 } 2731 2732 /* Abort a root interrupt request. */ 2733 Static void 2734 ehci_root_intr_abort(struct usbd_xfer *xfer) 2735 { 2736 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2737 2738 KASSERT(mutex_owned(&sc->sc_lock)); 2739 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2740 2741 /* If xfer has already completed, nothing to do here. */ 2742 if (sc->sc_intrxfer == NULL) 2743 return; 2744 2745 /* 2746 * Otherwise, sc->sc_intrxfer had better be this transfer. 2747 * Cancel it. 2748 */ 2749 KASSERT(sc->sc_intrxfer == xfer); 2750 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2751 xfer->ux_status = USBD_CANCELLED; 2752 usb_transfer_complete(xfer); 2753 } 2754 2755 /* Close the root pipe. */ 2756 Static void 2757 ehci_root_intr_close(struct usbd_pipe *pipe) 2758 { 2759 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2760 2761 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2762 2763 KASSERT(mutex_owned(&sc->sc_lock)); 2764 2765 /* 2766 * Caller must guarantee the xfer has completed first, by 2767 * closing the pipe only after normal completion or an abort. 2768 */ 2769 KASSERT(sc->sc_intrxfer == NULL); 2770 } 2771 2772 Static void 2773 ehci_root_intr_done(struct usbd_xfer *xfer) 2774 { 2775 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2776 2777 KASSERT(mutex_owned(&sc->sc_lock)); 2778 2779 /* Claim the xfer so it doesn't get completed again. */ 2780 KASSERT(sc->sc_intrxfer == xfer); 2781 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2782 sc->sc_intrxfer = NULL; 2783 } 2784 2785 /************************/ 2786 2787 Static ehci_soft_qh_t * 2788 ehci_alloc_sqh(ehci_softc_t *sc) 2789 { 2790 ehci_soft_qh_t *sqh; 2791 2792 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2793 2794 mutex_enter(&sc->sc_lock); 2795 if (sc->sc_freeqhs == NULL) { 2796 DPRINTF("allocating chunk", 0, 0, 0, 0); 2797 mutex_exit(&sc->sc_lock); 2798 2799 usb_dma_t dma; 2800 int err = usb_allocmem(sc->sc_bus.ub_dmatag, 2801 EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2802 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2803 2804 if (err) { 2805 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2806 return NULL; 2807 } 2808 2809 mutex_enter(&sc->sc_lock); 2810 for (size_t i = 0; i < EHCI_SQH_CHUNK; i++) { 2811 const int offs = i * EHCI_SQH_SIZE; 2812 const bus_addr_t baddr = DMAADDR(&dma, offs); 2813 2814 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2815 2816 sqh = KERNADDR(&dma, offs); 2817 sqh->physaddr = BUS_ADDR_LO32(baddr); 2818 sqh->dma = dma; 2819 sqh->offs = offs; 2820 2821 sqh->next = sc->sc_freeqhs; 2822 sc->sc_freeqhs = sqh; 2823 } 2824 } 2825 sqh = sc->sc_freeqhs; 2826 sc->sc_freeqhs = sqh->next; 2827 mutex_exit(&sc->sc_lock); 2828 2829 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2830 sqh->next = NULL; 2831 return sqh; 2832 } 2833 2834 Static void 2835 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2836 { 2837 KASSERT(mutex_owned(&sc->sc_lock)); 2838 2839 sqh->next = sc->sc_freeqhs; 2840 sc->sc_freeqhs = sqh; 2841 } 2842 2843 Static ehci_soft_qtd_t * 2844 ehci_alloc_sqtd(ehci_softc_t *sc) 2845 { 2846 ehci_soft_qtd_t *sqtd = NULL; 2847 2848 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2849 2850 mutex_enter(&sc->sc_lock); 2851 if (sc->sc_freeqtds == NULL) { 2852 DPRINTF("allocating chunk", 0, 0, 0, 0); 2853 mutex_exit(&sc->sc_lock); 2854 2855 usb_dma_t dma; 2856 int err = usb_allocmem(sc->sc_bus.ub_dmatag, 2857 EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK, 2858 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2859 2860 if (err) { 2861 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2862 return NULL; 2863 } 2864 2865 mutex_enter(&sc->sc_lock); 2866 for (size_t i = 0; i < EHCI_SQTD_CHUNK; i++) { 2867 const int offs = i * EHCI_SQTD_SIZE; 2868 const bus_addr_t baddr = DMAADDR(&dma, offs); 2869 2870 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2871 2872 sqtd = KERNADDR(&dma, offs); 2873 sqtd->physaddr = BUS_ADDR_LO32(baddr); 2874 sqtd->dma = dma; 2875 sqtd->offs = offs; 2876 2877 sqtd->nextqtd = sc->sc_freeqtds; 2878 sc->sc_freeqtds = sqtd; 2879 } 2880 } 2881 2882 sqtd = sc->sc_freeqtds; 2883 sc->sc_freeqtds = sqtd->nextqtd; 2884 mutex_exit(&sc->sc_lock); 2885 2886 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2887 sqtd->nextqtd = NULL; 2888 sqtd->xfer = NULL; 2889 2890 return sqtd; 2891 } 2892 2893 Static void 2894 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2895 { 2896 2897 mutex_enter(&sc->sc_lock); 2898 sqtd->nextqtd = sc->sc_freeqtds; 2899 sc->sc_freeqtds = sqtd; 2900 mutex_exit(&sc->sc_lock); 2901 } 2902 2903 Static int 2904 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2905 int alen, int rd, ehci_soft_qtd_t **sp) 2906 { 2907 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2908 uint16_t flags = xfer->ux_flags; 2909 2910 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2911 2912 ASSERT_SLEEPABLE(); 2913 KASSERT(sp); 2914 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2915 2916 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2917 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 2918 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2919 KM_SLEEP); 2920 exfer->ex_nsqtd = nsqtd; 2921 2922 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2923 alen, nsqtd, flags); 2924 2925 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2926 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2927 if (cur == NULL) 2928 goto nomem; 2929 exfer->ex_sqtds[j++] = cur; 2930 2931 cur->xfer = xfer; 2932 cur->len = 0; 2933 2934 } 2935 2936 *sp = exfer->ex_sqtds[0]; 2937 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2938 2939 return 0; 2940 2941 nomem: 2942 ehci_free_sqtds(sc, exfer); 2943 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2944 DPRINTF("no memory", 0, 0, 0, 0); 2945 return ENOMEM; 2946 } 2947 2948 Static void 2949 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2950 { 2951 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2952 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2953 2954 mutex_enter(&sc->sc_lock); 2955 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2956 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2957 2958 if (sqtd == NULL) 2959 break; 2960 2961 sqtd->nextqtd = sc->sc_freeqtds; 2962 sc->sc_freeqtds = sqtd; 2963 } 2964 mutex_exit(&sc->sc_lock); 2965 } 2966 2967 Static void 2968 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2969 { 2970 if (prev) { 2971 prev->nextqtd = sqtd; 2972 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2973 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2974 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2975 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2976 } 2977 } 2978 2979 Static void 2980 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2981 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2982 { 2983 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2984 usb_dma_t *dma = &xfer->ux_dmabuf; 2985 uint16_t flags = xfer->ux_flags; 2986 ehci_soft_qtd_t *sqtd, *prev; 2987 int tog = *toggle; 2988 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2989 int len = length; 2990 2991 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2992 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2993 len, isread, tog); 2994 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 2995 0, 0, 0); 2996 2997 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2998 2999 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3000 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3001 EHCI_QTD_SET_CERR(3) 3002 ; 3003 3004 sqtd = prev = NULL; 3005 size_t curoffs = 0; 3006 size_t j = 0; 3007 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3008 sqtd = exfer->ex_sqtds[j++]; 3009 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3010 (uintptr_t)prev, 0); 3011 3012 /* 3013 * The EHCI hardware can handle at most 5 pages and they do 3014 * not have to be contiguous 3015 */ 3016 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3017 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3018 size_t curlen = len; 3019 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3020 /* must use multiple TDs, fill as much as possible. */ 3021 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3022 3023 /* the length must be a multiple of the max size */ 3024 curlen -= curlen % mps; 3025 } 3026 KASSERT(curlen != 0); 3027 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3028 curoffs, 0); 3029 3030 /* Fill the qTD */ 3031 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3032 sqtd->qtd.qtd_status = htole32( 3033 qtdstatus | 3034 EHCI_QTD_SET_BYTES(curlen) | 3035 EHCI_QTD_SET_TOGGLE(tog)); 3036 3037 /* Find number of pages we'll be using, insert dma addresses */ 3038 size_t pages = EHCI_NPAGES(curlen); 3039 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3040 size_t pageoffs = EHCI_PAGE(curoffs); 3041 for (size_t i = 0; i < pages; i++) { 3042 paddr_t a = EHCI_PAGE(DMAADDR(dma, 3043 pageoffs + i * EHCI_PAGE_SIZE)); 3044 sqtd->qtd.qtd_buffer[i] = htole32(BUS_ADDR_LO32(a)); 3045 sqtd->qtd.qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a)); 3046 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3047 i, pages, 3048 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3049 le32toh(sqtd->qtd.qtd_buffer[i])); 3050 } 3051 /* First buffer pointer requires a page offset to start at */ 3052 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3053 3054 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3055 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3056 3057 sqtd->len = curlen; 3058 3059 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3060 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3061 3062 ehci_append_sqtd(sqtd, prev); 3063 3064 if (howmany(curlen, mps) & 1) { 3065 tog ^= 1; 3066 } 3067 3068 curoffs += curlen; 3069 len -= curlen; 3070 } 3071 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3072 xfer, length, len, mps, exfer->ex_nsqtd, j); 3073 3074 if (!isread && 3075 (flags & USBD_FORCE_SHORT_XFER) && 3076 length % mps == 0) { 3077 /* Force a 0 length transfer at the end. */ 3078 3079 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3080 exfer->ex_nsqtd); 3081 prev = sqtd; 3082 sqtd = exfer->ex_sqtds[j++]; 3083 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3084 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3085 sqtd->qtd.qtd_status = htole32( 3086 qtdstatus | 3087 EHCI_QTD_SET_BYTES(0) | 3088 EHCI_QTD_SET_TOGGLE(tog)); 3089 3090 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3091 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3092 3093 ehci_append_sqtd(sqtd, prev); 3094 tog ^= 1; 3095 } 3096 3097 *lsqtd = sqtd; 3098 *toggle = tog; 3099 } 3100 3101 Static ehci_soft_itd_t * 3102 ehci_alloc_itd(ehci_softc_t *sc) 3103 { 3104 struct ehci_soft_itd *itd, *freeitd; 3105 3106 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3107 3108 mutex_enter(&sc->sc_lock); 3109 3110 freeitd = LIST_FIRST(&sc->sc_freeitds); 3111 if (freeitd == NULL) { 3112 DPRINTF("allocating chunk", 0, 0, 0, 0); 3113 mutex_exit(&sc->sc_lock); 3114 3115 usb_dma_t dma; 3116 int err = usb_allocmem(sc->sc_bus.ub_dmatag, 3117 EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3118 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3119 3120 if (err) { 3121 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3122 return NULL; 3123 } 3124 3125 mutex_enter(&sc->sc_lock); 3126 for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) { 3127 const int offs = i * EHCI_ITD_SIZE; 3128 const bus_addr_t baddr = DMAADDR(&dma, offs); 3129 3130 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3131 3132 itd = KERNADDR(&dma, offs); 3133 itd->physaddr = BUS_ADDR_LO32(baddr); 3134 itd->dma = dma; 3135 itd->offs = offs; 3136 3137 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3138 } 3139 freeitd = LIST_FIRST(&sc->sc_freeitds); 3140 } 3141 3142 itd = freeitd; 3143 LIST_REMOVE(itd, free_list); 3144 mutex_exit(&sc->sc_lock); 3145 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3146 3147 itd->frame_list.next = NULL; 3148 itd->frame_list.prev = NULL; 3149 itd->xfer_next = NULL; 3150 itd->slot = 0; 3151 3152 return itd; 3153 } 3154 3155 Static ehci_soft_sitd_t * 3156 ehci_alloc_sitd(ehci_softc_t *sc) 3157 { 3158 struct ehci_soft_sitd *sitd, *freesitd; 3159 3160 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3161 3162 mutex_enter(&sc->sc_lock); 3163 freesitd = LIST_FIRST(&sc->sc_freesitds); 3164 if (freesitd == NULL) { 3165 3166 DPRINTF("allocating chunk", 0, 0, 0, 0); 3167 mutex_exit(&sc->sc_lock); 3168 3169 usb_dma_t dma; 3170 int err = usb_allocmem(sc->sc_bus.ub_dmatag, 3171 EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3172 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3173 3174 if (err) { 3175 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3176 return NULL; 3177 } 3178 3179 mutex_enter(&sc->sc_lock); 3180 for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) { 3181 const int offs = i * EHCI_SITD_SIZE; 3182 const bus_addr_t baddr = DMAADDR(&dma, offs); 3183 3184 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3185 3186 sitd = KERNADDR(&dma, offs); 3187 sitd->physaddr = BUS_ADDR_LO32(baddr); 3188 sitd->dma = dma; 3189 sitd->offs = offs; 3190 3191 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3192 } 3193 freesitd = LIST_FIRST(&sc->sc_freesitds); 3194 } 3195 3196 sitd = freesitd; 3197 LIST_REMOVE(sitd, free_list); 3198 mutex_exit(&sc->sc_lock); 3199 3200 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3201 3202 sitd->frame_list.next = NULL; 3203 sitd->frame_list.prev = NULL; 3204 sitd->xfer_next = NULL; 3205 sitd->slot = 0; 3206 3207 return sitd; 3208 } 3209 3210 /****************/ 3211 3212 /* 3213 * Close a reqular pipe. 3214 * Assumes that there are no pending transactions. 3215 */ 3216 Static void 3217 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3218 { 3219 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3220 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3221 ehci_soft_qh_t *sqh = epipe->sqh; 3222 3223 KASSERT(mutex_owned(&sc->sc_lock)); 3224 3225 ehci_rem_qh(sc, sqh, head); 3226 ehci_free_sqh(sc, epipe->sqh); 3227 } 3228 3229 /* 3230 * Arrange for the hardware to tells us that it is not still 3231 * processing the TDs by setting the QH halted bit and wait for the ehci 3232 * door bell 3233 */ 3234 Static void 3235 ehci_abortx(struct usbd_xfer *xfer) 3236 { 3237 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3238 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3239 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3240 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3241 ehci_soft_qh_t *sqh = epipe->sqh; 3242 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3243 ehci_physaddr_t cur; 3244 uint32_t qhstatus; 3245 int hit; 3246 3247 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3248 3249 KASSERT(mutex_owned(&sc->sc_lock)); 3250 ASSERT_SLEEPABLE(); 3251 3252 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3253 xfer->ux_status == USBD_TIMEOUT), 3254 "bad abort status: %d", xfer->ux_status); 3255 3256 /* 3257 * If we're dying, skip the hardware action and just notify the 3258 * software that we're done. 3259 */ 3260 if (sc->sc_dying) { 3261 goto dying; 3262 } 3263 3264 /* 3265 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3266 */ 3267 ehci_del_intr_list(sc, exfer); 3268 3269 usb_syncmem(&sqh->dma, 3270 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3271 sizeof(sqh->qh.qh_qtd.qtd_status), 3272 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3273 qhstatus = sqh->qh.qh_qtd.qtd_status; 3274 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3275 usb_syncmem(&sqh->dma, 3276 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3277 sizeof(sqh->qh.qh_qtd.qtd_status), 3278 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3279 3280 if (exfer->ex_type == EX_CTRL) { 3281 fsqtd = exfer->ex_setup; 3282 lsqtd = exfer->ex_status; 3283 } else { 3284 fsqtd = exfer->ex_sqtdstart; 3285 lsqtd = exfer->ex_sqtdend; 3286 } 3287 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3288 usb_syncmem(&sqtd->dma, 3289 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3290 sizeof(sqtd->qtd.qtd_status), 3291 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3292 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3293 usb_syncmem(&sqtd->dma, 3294 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3295 sizeof(sqtd->qtd.qtd_status), 3296 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3297 if (sqtd == lsqtd) 3298 break; 3299 } 3300 3301 /* 3302 * HC Step 2: Wait until we know hardware has finished any possible 3303 * use of the xfer. 3304 */ 3305 ehci_sync_hc(sc); 3306 3307 /* 3308 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3309 * The complication here is that the hardware may have executed 3310 * beyond the xfer we're trying to abort. So as we're scanning 3311 * the TDs of this xfer we check if the hardware points to 3312 * any of them. 3313 */ 3314 3315 usb_syncmem(&sqh->dma, 3316 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3317 sizeof(sqh->qh.qh_curqtd), 3318 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3319 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3320 hit = 0; 3321 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3322 hit |= cur == sqtd->physaddr; 3323 if (sqtd == lsqtd) 3324 break; 3325 } 3326 sqtd = sqtd->nextqtd; 3327 /* Zap curqtd register if hardware pointed inside the xfer. */ 3328 if (hit && sqtd != NULL) { 3329 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3330 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3331 usb_syncmem(&sqh->dma, 3332 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3333 sizeof(sqh->qh.qh_curqtd), 3334 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3335 sqh->qh.qh_qtd.qtd_status = qhstatus; 3336 usb_syncmem(&sqh->dma, 3337 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3338 sizeof(sqh->qh.qh_qtd.qtd_status), 3339 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3340 } else { 3341 DPRINTF("no hit", 0, 0, 0, 0); 3342 usb_syncmem(&sqh->dma, 3343 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3344 sizeof(sqh->qh.qh_curqtd), 3345 BUS_DMASYNC_PREREAD); 3346 } 3347 3348 /* 3349 * Final step: Notify completion to waiting xfers. 3350 */ 3351 dying: 3352 #ifdef DIAGNOSTIC 3353 exfer->ex_isdone = true; 3354 #endif 3355 usb_transfer_complete(xfer); 3356 DPRINTFN(14, "end", 0, 0, 0, 0); 3357 3358 KASSERT(mutex_owned(&sc->sc_lock)); 3359 } 3360 3361 Static void 3362 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3363 { 3364 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3365 ehci_isoc_trans_t trans_status; 3366 struct ehci_xfer *exfer; 3367 ehci_softc_t *sc; 3368 struct ehci_soft_itd *itd; 3369 struct ehci_soft_sitd *sitd; 3370 int i; 3371 3372 KASSERTMSG(status == USBD_CANCELLED, 3373 "invalid status for abort: %d", (int)status); 3374 3375 exfer = EHCI_XFER2EXFER(xfer); 3376 sc = EHCI_XFER2SC(xfer); 3377 3378 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3379 (uintptr_t)xfer->ux_pipe, 0, 0); 3380 3381 KASSERT(mutex_owned(&sc->sc_lock)); 3382 ASSERT_SLEEPABLE(); 3383 3384 /* No timeout or task here. */ 3385 3386 /* 3387 * The xfer cannot have been cancelled already. It is the 3388 * responsibility of the caller of usbd_abort_pipe not to try 3389 * to abort a pipe multiple times, whether concurrently or 3390 * sequentially. 3391 */ 3392 KASSERT(xfer->ux_status != USBD_CANCELLED); 3393 3394 /* If anyone else beat us, we're done. */ 3395 if (xfer->ux_status != USBD_IN_PROGRESS) 3396 return; 3397 3398 /* We beat everyone else. Claim the status. */ 3399 xfer->ux_status = status; 3400 3401 /* 3402 * If we're dying, skip the hardware action and just notify the 3403 * software that we're done. 3404 */ 3405 if (sc->sc_dying) { 3406 goto dying; 3407 } 3408 3409 /* 3410 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3411 */ 3412 ehci_del_intr_list(sc, exfer); 3413 3414 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3415 for (itd = exfer->ex_itdstart; itd != NULL; 3416 itd = itd->xfer_next) { 3417 usb_syncmem(&itd->dma, 3418 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3419 sizeof(itd->itd.itd_ctl), 3420 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3421 3422 for (i = 0; i < 8; i++) { 3423 trans_status = le32toh(itd->itd.itd_ctl[i]); 3424 trans_status &= ~EHCI_ITD_ACTIVE; 3425 itd->itd.itd_ctl[i] = htole32(trans_status); 3426 } 3427 3428 usb_syncmem(&itd->dma, 3429 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3430 sizeof(itd->itd.itd_ctl), 3431 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3432 } 3433 } else { 3434 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3435 sitd = sitd->xfer_next) { 3436 usb_syncmem(&sitd->dma, 3437 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3438 sizeof(sitd->sitd.sitd_buffer), 3439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3440 3441 trans_status = le32toh(sitd->sitd.sitd_trans); 3442 trans_status &= ~EHCI_SITD_ACTIVE; 3443 sitd->sitd.sitd_trans = htole32(trans_status); 3444 3445 usb_syncmem(&sitd->dma, 3446 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3447 sizeof(sitd->sitd.sitd_buffer), 3448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3449 } 3450 } 3451 3452 dying: 3453 #ifdef DIAGNOSTIC 3454 exfer->ex_isdone = true; 3455 #endif 3456 usb_transfer_complete(xfer); 3457 DPRINTFN(14, "end", 0, 0, 0, 0); 3458 3459 KASSERT(mutex_owned(&sc->sc_lock)); 3460 } 3461 3462 /************************/ 3463 3464 Static int 3465 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3466 { 3467 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3468 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3469 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3470 usb_device_request_t *req = &xfer->ux_request; 3471 ehci_soft_qtd_t *setup, *status, *next; 3472 int isread = req->bmRequestType & UT_READ; 3473 int len = xfer->ux_bufsize; 3474 int err; 3475 3476 exfer->ex_type = EX_CTRL; 3477 exfer->ex_status = NULL; 3478 exfer->ex_data = NULL; 3479 exfer->ex_setup = ehci_alloc_sqtd(sc); 3480 if (exfer->ex_setup == NULL) { 3481 err = ENOMEM; 3482 goto bad1; 3483 } 3484 exfer->ex_status = ehci_alloc_sqtd(sc); 3485 if (exfer->ex_status == NULL) { 3486 err = ENOMEM; 3487 goto bad2; 3488 } 3489 setup = exfer->ex_setup; 3490 status = exfer->ex_status; 3491 exfer->ex_nsqtd = 0; 3492 next = status; 3493 /* Set up data transaction */ 3494 if (len != 0) { 3495 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3496 &exfer->ex_data); 3497 if (err) 3498 goto bad3; 3499 next = exfer->ex_data; 3500 } 3501 3502 /* Clear toggle */ 3503 setup->qtd.qtd_status = htole32( 3504 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3505 EHCI_QTD_SET_TOGGLE(0) | 3506 EHCI_QTD_SET_BYTES(sizeof(*req)) 3507 ); 3508 3509 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3510 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3511 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3512 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3513 setup->nextqtd = next; 3514 setup->xfer = xfer; 3515 setup->len = sizeof(*req); 3516 3517 status->qtd.qtd_status = htole32( 3518 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3519 EHCI_QTD_SET_TOGGLE(1) | 3520 EHCI_QTD_IOC 3521 ); 3522 status->qtd.qtd_buffer[0] = 0; 3523 status->qtd.qtd_buffer_hi[0] = 0; 3524 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3525 status->nextqtd = NULL; 3526 status->xfer = xfer; 3527 status->len = 0; 3528 3529 return 0; 3530 bad3: 3531 ehci_free_sqtd(sc, exfer->ex_status); 3532 bad2: 3533 ehci_free_sqtd(sc, exfer->ex_setup); 3534 bad1: 3535 return err; 3536 } 3537 3538 Static void 3539 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3540 { 3541 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3542 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3543 3544 KASSERT(ex->ex_type == EX_CTRL); 3545 3546 ehci_free_sqtd(sc, ex->ex_setup); 3547 ehci_free_sqtd(sc, ex->ex_status); 3548 ehci_free_sqtds(sc, ex); 3549 if (ex->ex_nsqtd) 3550 kmem_free(ex->ex_sqtds, 3551 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3552 } 3553 3554 Static usbd_status 3555 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3556 { 3557 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3558 usbd_status err; 3559 3560 /* Insert last in queue. */ 3561 mutex_enter(&sc->sc_lock); 3562 err = usb_insert_transfer(xfer); 3563 mutex_exit(&sc->sc_lock); 3564 if (err) 3565 return err; 3566 3567 /* Pipe isn't running, start first */ 3568 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3569 } 3570 3571 Static usbd_status 3572 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3573 { 3574 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3575 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3576 usb_device_request_t *req = &xfer->ux_request; 3577 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3578 ehci_soft_qtd_t *setup, *status, *next; 3579 ehci_soft_qh_t *sqh; 3580 const bool polling = sc->sc_bus.ub_usepolling; 3581 3582 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3583 3584 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3585 3586 if (sc->sc_dying) 3587 return USBD_IOERROR; 3588 3589 const int isread = req->bmRequestType & UT_READ; 3590 const int len = UGETW(req->wLength); 3591 3592 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3593 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3594 UGETW(req->wIndex)); 3595 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3596 len, epipe->pipe.up_dev->ud_addr, 3597 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3598 3599 sqh = epipe->sqh; 3600 3601 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3602 "address QH %" __PRIuBIT " pipe %d\n", 3603 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3604 epipe->pipe.up_dev->ud_addr); 3605 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3606 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3607 "MPS QH %" __PRIuBIT " pipe %d\n", 3608 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3609 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3610 3611 setup = exfer->ex_setup; 3612 status = exfer->ex_status; 3613 3614 DPRINTF("setup %#jx status %#jx data %#jx", 3615 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3616 KASSERTMSG(setup != NULL && status != NULL, 3617 "Failed memory allocation, setup %p status %p", 3618 setup, status); 3619 3620 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3621 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3622 3623 /* Clear toggle */ 3624 setup->qtd.qtd_status &= ~htole32( 3625 EHCI_QTD_STATUS_MASK | 3626 EHCI_QTD_BYTES_MASK | 3627 EHCI_QTD_TOGGLE_MASK | 3628 EHCI_QTD_CERR_MASK 3629 ); 3630 setup->qtd.qtd_status |= htole32( 3631 EHCI_QTD_ACTIVE | 3632 EHCI_QTD_SET_CERR(3) | 3633 EHCI_QTD_SET_TOGGLE(0) | 3634 EHCI_QTD_SET_BYTES(sizeof(*req)) 3635 ); 3636 3637 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3638 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3639 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3640 3641 next = status; 3642 status->qtd.qtd_status &= ~htole32( 3643 EHCI_QTD_STATUS_MASK | 3644 EHCI_QTD_PID_MASK | 3645 EHCI_QTD_BYTES_MASK | 3646 EHCI_QTD_TOGGLE_MASK | 3647 EHCI_QTD_CERR_MASK 3648 ); 3649 status->qtd.qtd_status |= htole32( 3650 EHCI_QTD_ACTIVE | 3651 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3652 EHCI_QTD_SET_CERR(3) | 3653 EHCI_QTD_SET_TOGGLE(1) | 3654 EHCI_QTD_SET_BYTES(0) | 3655 EHCI_QTD_IOC 3656 ); 3657 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3658 3659 KASSERT(exfer->ex_isdone); 3660 #ifdef DIAGNOSTIC 3661 exfer->ex_isdone = false; 3662 #endif 3663 3664 /* Set up data transaction */ 3665 if (len != 0) { 3666 ehci_soft_qtd_t *end; 3667 3668 /* Start toggle at 1. */ 3669 int toggle = 1; 3670 next = exfer->ex_data; 3671 KASSERTMSG(next != NULL, "Failed memory allocation"); 3672 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3673 end->nextqtd = status; 3674 end->qtd.qtd_next = end->qtd.qtd_altnext = 3675 htole32(status->physaddr); 3676 3677 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3678 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3679 3680 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3681 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3682 } 3683 3684 setup->nextqtd = next; 3685 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3686 3687 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3688 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3689 3690 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3691 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3692 3693 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3694 3695 #ifdef EHCI_DEBUG 3696 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3697 ehci_dump_sqh(sqh); 3698 ehci_dump_sqtds(setup); 3699 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3700 #endif 3701 3702 if (!polling) 3703 mutex_enter(&sc->sc_lock); 3704 3705 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3706 ehci_set_qh_qtd(sqh, setup); 3707 usbd_xfer_schedule_timeout(xfer); 3708 ehci_add_intr_list(sc, exfer); 3709 xfer->ux_status = USBD_IN_PROGRESS; 3710 if (!polling) 3711 mutex_exit(&sc->sc_lock); 3712 3713 #if 0 3714 #ifdef EHCI_DEBUG 3715 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3716 // delay(10000); 3717 ehci_dump_regs(sc); 3718 ehci_dump_sqh(sc->sc_async_head); 3719 ehci_dump_sqh(sqh); 3720 ehci_dump_sqtds(setup); 3721 #endif 3722 #endif 3723 3724 return USBD_IN_PROGRESS; 3725 } 3726 3727 Static void 3728 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3729 { 3730 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3731 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3732 usb_device_request_t *req = &xfer->ux_request; 3733 int len = UGETW(req->wLength); 3734 int rd = req->bmRequestType & UT_READ; 3735 3736 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3737 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3738 3739 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3740 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3741 3742 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3743 BUS_DMASYNC_POSTWRITE); 3744 if (len) 3745 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3746 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3747 3748 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3749 } 3750 3751 /* Abort a device control request. */ 3752 Static void 3753 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3754 { 3755 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3756 3757 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3758 usbd_xfer_abort(xfer); 3759 } 3760 3761 /* Close a device control pipe. */ 3762 Static void 3763 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3764 { 3765 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3766 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3767 3768 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3769 3770 KASSERT(mutex_owned(&sc->sc_lock)); 3771 3772 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3773 3774 ehci_close_pipe(pipe, sc->sc_async_head); 3775 3776 usb_freemem(&epipe->ctrl.reqdma); 3777 } 3778 3779 /* 3780 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3781 * qTD status, or miss signalling occasionally under heavy load. If the host 3782 * machine is too fast, we can miss transaction completion - when we scan 3783 * the active list the transaction still seems to be active. This generally 3784 * exhibits itself as a umass stall that never recovers. 3785 * 3786 * We work around this behaviour by setting up this callback after any softintr 3787 * that completes with transactions still pending, giving us another chance to 3788 * check for completion after the writeback has taken place. 3789 */ 3790 Static void 3791 ehci_intrlist_timeout(void *arg) 3792 { 3793 ehci_softc_t *sc = arg; 3794 3795 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3796 3797 usb_schedsoftintr(&sc->sc_bus); 3798 } 3799 3800 /************************/ 3801 3802 Static int 3803 ehci_device_bulk_init(struct usbd_xfer *xfer) 3804 { 3805 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3806 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3807 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3808 int endpt = ed->bEndpointAddress; 3809 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3810 int len = xfer->ux_bufsize; 3811 int err = 0; 3812 3813 exfer->ex_type = EX_BULK; 3814 exfer->ex_nsqtd = 0; 3815 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3816 &exfer->ex_sqtdstart); 3817 3818 return err; 3819 } 3820 3821 Static void 3822 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3823 { 3824 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3825 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3826 3827 KASSERT(ex->ex_type == EX_BULK); 3828 3829 ehci_free_sqtds(sc, ex); 3830 if (ex->ex_nsqtd) 3831 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3832 } 3833 3834 Static usbd_status 3835 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3836 { 3837 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3838 usbd_status err; 3839 3840 /* Insert last in queue. */ 3841 mutex_enter(&sc->sc_lock); 3842 err = usb_insert_transfer(xfer); 3843 mutex_exit(&sc->sc_lock); 3844 if (err) 3845 return err; 3846 3847 /* Pipe isn't running, start first */ 3848 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3849 } 3850 3851 Static usbd_status 3852 ehci_device_bulk_start(struct usbd_xfer *xfer) 3853 { 3854 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3855 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3856 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3857 ehci_soft_qh_t *sqh; 3858 ehci_soft_qtd_t *end; 3859 int len, isread, endpt; 3860 const bool polling = sc->sc_bus.ub_usepolling; 3861 3862 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3863 3864 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3865 xfer->ux_flags, 0); 3866 3867 if (sc->sc_dying) 3868 return USBD_IOERROR; 3869 3870 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3871 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3872 3873 len = xfer->ux_length; 3874 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3875 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3876 sqh = epipe->sqh; 3877 3878 KASSERT(exfer->ex_isdone); 3879 #ifdef DIAGNOSTIC 3880 exfer->ex_isdone = false; 3881 #endif 3882 3883 /* Take lock here to protect nexttoggle */ 3884 if (!polling) 3885 mutex_enter(&sc->sc_lock); 3886 3887 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3888 3889 exfer->ex_sqtdend = end; 3890 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3891 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3893 3894 #ifdef EHCI_DEBUG 3895 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3896 ehci_dump_sqh(sqh); 3897 ehci_dump_sqtds(exfer->ex_sqtdstart); 3898 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3899 #endif 3900 3901 if (xfer->ux_length) 3902 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3903 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3904 3905 /* also does usb_syncmem(sqh) */ 3906 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3907 usbd_xfer_schedule_timeout(xfer); 3908 ehci_add_intr_list(sc, exfer); 3909 xfer->ux_status = USBD_IN_PROGRESS; 3910 if (!polling) 3911 mutex_exit(&sc->sc_lock); 3912 3913 #if 0 3914 #ifdef EHCI_DEBUG 3915 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3916 // delay(10000); 3917 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3918 ehci_dump_regs(sc); 3919 #if 0 3920 printf("async_head:\n"); 3921 ehci_dump_sqh(sc->sc_async_head); 3922 #endif 3923 DPRINTF("sqh:", 0, 0, 0, 0); 3924 ehci_dump_sqh(sqh); 3925 ehci_dump_sqtds(exfer->ex_sqtdstart); 3926 #endif 3927 #endif 3928 3929 return USBD_IN_PROGRESS; 3930 } 3931 3932 Static void 3933 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3934 { 3935 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3936 3937 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3938 usbd_xfer_abort(xfer); 3939 } 3940 3941 /* 3942 * Close a device bulk pipe. 3943 */ 3944 Static void 3945 ehci_device_bulk_close(struct usbd_pipe *pipe) 3946 { 3947 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3948 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3949 3950 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3951 3952 KASSERT(mutex_owned(&sc->sc_lock)); 3953 3954 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3955 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3956 ehci_close_pipe(pipe, sc->sc_async_head); 3957 } 3958 3959 Static void 3960 ehci_device_bulk_done(struct usbd_xfer *xfer) 3961 { 3962 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3963 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3964 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3965 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3966 3967 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3968 3969 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 3970 3971 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3972 3973 if (xfer->ux_length) 3974 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3975 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3976 3977 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3978 } 3979 3980 /************************/ 3981 3982 Static usbd_status 3983 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3984 { 3985 struct ehci_soft_islot *isp; 3986 int islot, lev; 3987 3988 /* Find a poll rate that is large enough. */ 3989 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3990 if (EHCI_ILEV_IVAL(lev) <= ival) 3991 break; 3992 3993 /* Pick an interrupt slot at the right level. */ 3994 /* XXX could do better than picking at random */ 3995 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3996 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3997 3998 sqh->islot = islot; 3999 isp = &sc->sc_islots[islot]; 4000 mutex_enter(&sc->sc_lock); 4001 ehci_add_qh(sc, sqh, isp->sqh); 4002 mutex_exit(&sc->sc_lock); 4003 4004 return USBD_NORMAL_COMPLETION; 4005 } 4006 4007 Static int 4008 ehci_device_intr_init(struct usbd_xfer *xfer) 4009 { 4010 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4011 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4012 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4013 int endpt = ed->bEndpointAddress; 4014 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4015 int len = xfer->ux_bufsize; 4016 int err; 4017 4018 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4019 4020 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4021 xfer->ux_flags, 0); 4022 4023 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4024 KASSERT(len != 0); 4025 4026 exfer->ex_type = EX_INTR; 4027 exfer->ex_nsqtd = 0; 4028 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4029 &exfer->ex_sqtdstart); 4030 4031 return err; 4032 } 4033 4034 Static void 4035 ehci_device_intr_fini(struct usbd_xfer *xfer) 4036 { 4037 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4038 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4039 4040 KASSERT(ex->ex_type == EX_INTR); 4041 4042 ehci_free_sqtds(sc, ex); 4043 if (ex->ex_nsqtd) 4044 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4045 } 4046 4047 Static usbd_status 4048 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4049 { 4050 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4051 usbd_status err; 4052 4053 /* Insert last in queue. */ 4054 mutex_enter(&sc->sc_lock); 4055 err = usb_insert_transfer(xfer); 4056 mutex_exit(&sc->sc_lock); 4057 if (err) 4058 return err; 4059 4060 /* 4061 * Pipe isn't running (otherwise err would be USBD_INPROG), 4062 * so start it first. 4063 */ 4064 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4065 } 4066 4067 Static usbd_status 4068 ehci_device_intr_start(struct usbd_xfer *xfer) 4069 { 4070 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4071 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4072 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4073 ehci_soft_qtd_t *end; 4074 ehci_soft_qh_t *sqh; 4075 int len, isread, endpt; 4076 const bool polling = sc->sc_bus.ub_usepolling; 4077 4078 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4079 4080 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4081 xfer->ux_flags, 0); 4082 4083 if (sc->sc_dying) 4084 return USBD_IOERROR; 4085 4086 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4087 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4088 4089 len = xfer->ux_length; 4090 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4091 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4092 sqh = epipe->sqh; 4093 4094 KASSERT(exfer->ex_isdone); 4095 #ifdef DIAGNOSTIC 4096 exfer->ex_isdone = false; 4097 #endif 4098 4099 /* Take lock to protect nexttoggle */ 4100 if (!polling) 4101 mutex_enter(&sc->sc_lock); 4102 4103 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4104 4105 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4106 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4107 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4108 exfer->ex_sqtdend = end; 4109 4110 #ifdef EHCI_DEBUG 4111 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4112 ehci_dump_sqh(sqh); 4113 ehci_dump_sqtds(exfer->ex_sqtdstart); 4114 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4115 #endif 4116 4117 if (xfer->ux_length) 4118 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4119 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4120 4121 /* also does usb_syncmem(sqh) */ 4122 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4123 usbd_xfer_schedule_timeout(xfer); 4124 ehci_add_intr_list(sc, exfer); 4125 xfer->ux_status = USBD_IN_PROGRESS; 4126 if (!polling) 4127 mutex_exit(&sc->sc_lock); 4128 4129 #if 0 4130 #ifdef EHCI_DEBUG 4131 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4132 // delay(10000); 4133 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4134 ehci_dump_regs(sc); 4135 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4136 ehci_dump_sqh(sqh); 4137 ehci_dump_sqtds(exfer->ex_sqtdstart); 4138 #endif 4139 #endif 4140 4141 return USBD_IN_PROGRESS; 4142 } 4143 4144 Static void 4145 ehci_device_intr_abort(struct usbd_xfer *xfer) 4146 { 4147 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4148 4149 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4150 4151 /* 4152 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4153 * async doorbell. That's dependent on the async list, wheras 4154 * intr xfers are periodic, should not use this? 4155 */ 4156 usbd_xfer_abort(xfer); 4157 } 4158 4159 Static void 4160 ehci_device_intr_close(struct usbd_pipe *pipe) 4161 { 4162 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4163 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4164 struct ehci_soft_islot *isp; 4165 4166 KASSERT(mutex_owned(&sc->sc_lock)); 4167 4168 isp = &sc->sc_islots[epipe->sqh->islot]; 4169 ehci_close_pipe(pipe, isp->sqh); 4170 } 4171 4172 Static void 4173 ehci_device_intr_done(struct usbd_xfer *xfer) 4174 { 4175 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4176 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4177 4178 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4179 4180 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4181 4182 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4183 4184 if (xfer->ux_length) { 4185 int isread, endpt; 4186 4187 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4188 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4189 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4190 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4191 } 4192 } 4193 4194 /************************/ 4195 Static int 4196 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4197 { 4198 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4199 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4200 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4201 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4202 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4203 int i, k, frames; 4204 u_int huba, dir; 4205 int err; 4206 4207 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4208 4209 start = NULL; 4210 sitd = NULL; 4211 4212 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4213 xfer->ux_flags, 0); 4214 4215 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4216 KASSERT(xfer->ux_nframes != 0); 4217 KASSERT(exfer->ex_isdone); 4218 4219 exfer->ex_type = EX_FS_ISOC; 4220 /* 4221 * Step 1: Allocate and initialize sitds. 4222 */ 4223 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4224 if (i > 16 || i == 0) { 4225 /* Spec page 271 says intervals > 16 are invalid */ 4226 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4227 4228 return EINVAL; 4229 } 4230 4231 frames = xfer->ux_nframes; 4232 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4233 sitd = ehci_alloc_sitd(sc); 4234 if (sitd == NULL) { 4235 err = ENOMEM; 4236 goto fail; 4237 } 4238 4239 if (prev) 4240 prev->xfer_next = sitd; 4241 else 4242 start = sitd; 4243 4244 huba = dev->ud_myhsport->up_parent->ud_addr; 4245 4246 #if 0 4247 if (sc->sc_flags & EHCIF_FREESCALE) { 4248 // Set hub address to 0 if embedded TT is used. 4249 if (huba == sc->sc_addr) 4250 huba = 0; 4251 } 4252 #endif 4253 4254 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4255 dir = UE_GET_DIR(k) ? 1 : 0; 4256 sitd->sitd.sitd_endp = 4257 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4258 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4259 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4260 EHCI_SITD_SET_HUBA(huba) | 4261 EHCI_SITD_SET_DIR(dir)); 4262 4263 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4264 } /* End of frame */ 4265 4266 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4267 4268 stop = sitd; 4269 stop->xfer_next = NULL; 4270 exfer->ex_sitdstart = start; 4271 exfer->ex_sitdend = stop; 4272 4273 return 0; 4274 4275 fail: 4276 mutex_enter(&sc->sc_lock); 4277 ehci_soft_sitd_t *next; 4278 for (sitd = start; sitd; sitd = next) { 4279 next = sitd->xfer_next; 4280 ehci_free_sitd_locked(sc, sitd); 4281 } 4282 mutex_exit(&sc->sc_lock); 4283 4284 return err; 4285 } 4286 4287 Static void 4288 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4289 { 4290 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4291 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4292 4293 KASSERT(ex->ex_type == EX_FS_ISOC); 4294 4295 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4296 } 4297 4298 Static usbd_status 4299 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4300 { 4301 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4302 usbd_status __diagused err; 4303 4304 mutex_enter(&sc->sc_lock); 4305 err = usb_insert_transfer(xfer); 4306 mutex_exit(&sc->sc_lock); 4307 4308 KASSERT(err == USBD_NORMAL_COMPLETION); 4309 4310 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4311 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4312 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4313 ehci_soft_sitd_t *sitd; 4314 usb_dma_t *dma_buf; 4315 int i, j, k, frames; 4316 int offs; 4317 int frindex; 4318 u_int dir; 4319 4320 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4321 4322 sitd = NULL; 4323 4324 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4325 xfer->ux_flags, 0); 4326 4327 if (sc->sc_dying) 4328 return USBD_IOERROR; 4329 4330 /* 4331 * To avoid complication, don't allow a request right now that'll span 4332 * the entire frame table. To within 4 frames, to allow some leeway 4333 * on either side of where the hc currently is. 4334 */ 4335 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4336 xfer->ux_nframes >= sc->sc_flsize - 4) { 4337 printf("ehci: isoc descriptor requested that spans the entire" 4338 "frametable, too many frames\n"); 4339 return USBD_INVAL; 4340 } 4341 4342 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4343 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4344 KASSERT(exfer->ex_isdone); 4345 #ifdef DIAGNOSTIC 4346 exfer->ex_isdone = false; 4347 #endif 4348 4349 /* 4350 * Step 1: Initialize sitds. 4351 */ 4352 4353 frames = xfer->ux_nframes; 4354 dma_buf = &xfer->ux_dmabuf; 4355 offs = 0; 4356 4357 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4358 i++, sitd = sitd->xfer_next) { 4359 KASSERT(sitd != NULL); 4360 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4361 4362 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4363 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4364 4365 /* Set page0 index and offset - TP and T-offset are set below */ 4366 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4367 4368 offs += xfer->ux_frlengths[i]; 4369 4370 sitd->sitd.sitd_buffer[1] = 4371 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4372 4373 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4374 4375 #if 0 4376 if (sc->sc_flags & EHCIF_FREESCALE) { 4377 // Set hub address to 0 if embedded TT is used. 4378 if (huba == sc->sc_addr) 4379 huba = 0; 4380 } 4381 #endif 4382 4383 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4384 dir = UE_GET_DIR(k) ? 1 : 0; 4385 KASSERT(sitd->sitd.sitd_endp == htole32( 4386 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4387 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4388 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4389 EHCI_SITD_SET_HUBA(huba) | 4390 EHCI_SITD_SET_DIR(dir))); 4391 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4392 4393 uint8_t sa = 0; 4394 uint8_t sb = 0; 4395 u_int temp, tlen; 4396 4397 if (dir == 0) { /* OUT */ 4398 temp = 0; 4399 tlen = xfer->ux_frlengths[i]; 4400 if (tlen <= 188) { 4401 temp |= 1; /* T-count = 1, TP = ALL */ 4402 tlen = 1; 4403 } else { 4404 tlen += 187; 4405 tlen /= 188; 4406 temp |= tlen; /* T-count = [1..6] */ 4407 temp |= 8; /* TP = Begin */ 4408 } 4409 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4410 4411 tlen += sa; 4412 4413 if (tlen >= 8) { 4414 sb = 0; 4415 } else { 4416 sb = (1 << tlen); 4417 } 4418 4419 sa = (1 << sa); 4420 sa = (sb - sa) & 0x3F; 4421 sb = 0; 4422 } else { 4423 sb = (-(4 << sa)) & 0xFE; 4424 sa = (1 << sa) & 0x3F; 4425 sa = 0x01; 4426 sb = 0xfc; 4427 } 4428 4429 sitd->sitd.sitd_sched = htole32( 4430 EHCI_SITD_SET_SMASK(sa) | 4431 EHCI_SITD_SET_CMASK(sb) 4432 ); 4433 4434 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4436 } /* End of frame */ 4437 4438 sitd = exfer->ex_sitdend; 4439 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4440 4441 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4442 sizeof(sitd->sitd.sitd_trans), 4443 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4444 4445 if (xfer->ux_length) 4446 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4447 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4448 4449 /* 4450 * Part 2: Transfer descriptors have now been set up, now they must 4451 * be scheduled into the periodic frame list. Erk. Not wanting to 4452 * complicate matters, transfer is denied if the transfer spans 4453 * more than the period frame list. 4454 */ 4455 4456 mutex_enter(&sc->sc_lock); 4457 4458 /* Start inserting frames */ 4459 if (epipe->isoc.cur_xfers > 0) { 4460 frindex = epipe->isoc.next_frame; 4461 } else { 4462 frindex = EOREAD4(sc, EHCI_FRINDEX); 4463 frindex = frindex >> 3; /* Erase microframe index */ 4464 frindex += 2; 4465 } 4466 4467 if (frindex >= sc->sc_flsize) 4468 frindex &= (sc->sc_flsize - 1); 4469 4470 /* Whats the frame interval? */ 4471 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4472 4473 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4474 j++, sitd = sitd->xfer_next) { 4475 KASSERT(sitd); 4476 4477 usb_syncmem(&sc->sc_fldma, 4478 sizeof(ehci_link_t) * frindex, 4479 sizeof(ehci_link_t), 4480 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4481 4482 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4483 if (sitd->sitd.sitd_next == 0) 4484 /* 4485 * FIXME: frindex table gets initialized to NULL 4486 * or EHCI_NULL? 4487 */ 4488 sitd->sitd.sitd_next = EHCI_NULL; 4489 4490 usb_syncmem(&sitd->dma, 4491 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4492 sizeof(ehci_sitd_t), 4493 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4494 4495 sc->sc_flist[frindex] = 4496 htole32(EHCI_LINK_SITD | sitd->physaddr); 4497 4498 usb_syncmem(&sc->sc_fldma, 4499 sizeof(ehci_link_t) * frindex, 4500 sizeof(ehci_link_t), 4501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4502 4503 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4504 sc->sc_softsitds[frindex] = sitd; 4505 if (sitd->frame_list.next != NULL) 4506 sitd->frame_list.next->frame_list.prev = sitd; 4507 sitd->slot = frindex; 4508 sitd->frame_list.prev = NULL; 4509 4510 frindex += i; 4511 if (frindex >= sc->sc_flsize) 4512 frindex -= sc->sc_flsize; 4513 } 4514 4515 epipe->isoc.cur_xfers++; 4516 epipe->isoc.next_frame = frindex; 4517 4518 ehci_add_intr_list(sc, exfer); 4519 xfer->ux_status = USBD_IN_PROGRESS; 4520 mutex_exit(&sc->sc_lock); 4521 4522 return USBD_IN_PROGRESS; 4523 } 4524 4525 Static void 4526 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4527 { 4528 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4529 4530 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4531 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4532 } 4533 4534 Static void 4535 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4536 { 4537 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4538 4539 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4540 } 4541 4542 Static void 4543 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4544 { 4545 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4546 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4547 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4548 4549 KASSERT(mutex_owned(&sc->sc_lock)); 4550 4551 epipe->isoc.cur_xfers--; 4552 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4553 4554 if (xfer->ux_length) 4555 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4556 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4557 } 4558 4559 /* -------------------------------------------------------------------------- */ 4560 4561 Static int 4562 ehci_device_isoc_init(struct usbd_xfer *xfer) 4563 { 4564 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4565 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4566 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4567 ehci_soft_itd_t *itd, *prev, *start, *stop; 4568 int i, j, k; 4569 int frames, ufrperframe; 4570 int err; 4571 4572 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4573 4574 start = NULL; 4575 prev = NULL; 4576 itd = NULL; 4577 4578 KASSERT(xfer->ux_nframes != 0); 4579 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4580 KASSERT(exfer->ex_isdone); 4581 4582 exfer->ex_type = EX_ISOC; 4583 4584 /* 4585 * Step 1: Allocate and initialize itds, how many do we need? 4586 * One per transfer if interval >= 8 microframes, less if we use 4587 * multiple microframes per frame. 4588 */ 4589 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4590 if (i > 16 || i == 0) { 4591 /* Spec page 271 says intervals > 16 are invalid */ 4592 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4593 return USBD_INVAL; 4594 } 4595 4596 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4597 frames = howmany(xfer->ux_nframes, ufrperframe); 4598 4599 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4600 itd = ehci_alloc_itd(sc); 4601 if (itd == NULL) { 4602 err = ENOMEM; 4603 goto fail; 4604 } 4605 4606 if (prev != NULL) { 4607 /* Maybe not as it's updated by the scheduling? */ 4608 prev->itd.itd_next = 4609 htole32(itd->physaddr | EHCI_LINK_ITD); 4610 4611 prev->xfer_next = itd; 4612 } else { 4613 start = itd; 4614 } 4615 4616 /* 4617 * Other special values 4618 */ 4619 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4620 itd->itd.itd_bufr[0] = htole32( 4621 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4622 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4623 4624 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4625 ? 1 : 0; 4626 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4627 itd->itd.itd_bufr[1] |= htole32( 4628 EHCI_ITD_SET_DIR(k) | 4629 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4630 4631 /* FIXME: handle invalid trans - should be done in openpipe */ 4632 itd->itd.itd_bufr[2] |= 4633 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4634 } /* End of frame */ 4635 4636 stop = itd; 4637 stop->xfer_next = NULL; 4638 4639 exfer->ex_itdstart = start; 4640 exfer->ex_itdend = stop; 4641 4642 return 0; 4643 fail: 4644 mutex_enter(&sc->sc_lock); 4645 ehci_soft_itd_t *next; 4646 for (itd = start; itd; itd = next) { 4647 next = itd->xfer_next; 4648 ehci_free_itd_locked(sc, itd); 4649 } 4650 mutex_exit(&sc->sc_lock); 4651 4652 return err; 4653 4654 } 4655 4656 Static void 4657 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4658 { 4659 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4660 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4661 4662 KASSERT(ex->ex_type == EX_ISOC); 4663 4664 ehci_free_itd_chain(sc, ex->ex_itdstart); 4665 } 4666 4667 Static usbd_status 4668 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4669 { 4670 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4671 usbd_status __diagused err; 4672 4673 mutex_enter(&sc->sc_lock); 4674 err = usb_insert_transfer(xfer); 4675 mutex_exit(&sc->sc_lock); 4676 4677 KASSERT(err == USBD_NORMAL_COMPLETION); 4678 4679 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4680 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4681 ehci_soft_itd_t *itd, *prev; 4682 usb_dma_t *dma_buf; 4683 int i, j; 4684 int frames, uframes, ufrperframe; 4685 int trans_count, offs; 4686 int frindex; 4687 4688 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4689 4690 prev = NULL; 4691 itd = NULL; 4692 trans_count = 0; 4693 4694 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4695 4696 if (sc->sc_dying) 4697 return USBD_IOERROR; 4698 4699 /* 4700 * To avoid complication, don't allow a request right now that'll span 4701 * the entire frame table. To within 4 frames, to allow some leeway 4702 * on either side of where the hc currently is. 4703 */ 4704 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4705 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4706 DPRINTF( 4707 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4708 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4709 return USBD_INVAL; 4710 } 4711 4712 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4713 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4714 KASSERT(exfer->ex_isdone); 4715 #ifdef DIAGNOSTIC 4716 exfer->ex_isdone = false; 4717 #endif 4718 4719 /* 4720 * Step 1: Re-Initialize itds 4721 */ 4722 4723 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4724 if (i > 16 || i == 0) { 4725 /* Spec page 271 says intervals > 16 are invalid */ 4726 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4727 return USBD_INVAL; 4728 } 4729 4730 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4731 frames = howmany(xfer->ux_nframes, ufrperframe); 4732 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4733 4734 if (frames == 0) { 4735 DPRINTF("frames == 0", 0, 0, 0, 0); 4736 return USBD_INVAL; 4737 } 4738 4739 dma_buf = &xfer->ux_dmabuf; 4740 offs = 0; 4741 4742 itd = exfer->ex_itdstart; 4743 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4744 int froffs = offs; 4745 4746 if (prev != NULL) { 4747 prev->itd.itd_next = 4748 htole32(itd->physaddr | EHCI_LINK_ITD); 4749 usb_syncmem(&prev->dma, 4750 prev->offs + offsetof(ehci_itd_t, itd_next), 4751 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4752 prev->xfer_next = itd; 4753 } 4754 4755 /* 4756 * Step 1.5, initialize uframes 4757 */ 4758 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4759 /* Calculate which page in the list this starts in */ 4760 int addr = DMAADDR(dma_buf, froffs); 4761 addr = EHCI_PAGE_OFFSET(addr); 4762 addr += (offs - froffs); 4763 addr = EHCI_PAGE(addr); 4764 addr /= EHCI_PAGE_SIZE; 4765 4766 /* 4767 * This gets the initial offset into the first page, 4768 * looks how far further along the current uframe 4769 * offset is. Works out how many pages that is. 4770 */ 4771 4772 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4773 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4774 EHCI_ITD_SET_PG(addr) | 4775 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4776 4777 offs += xfer->ux_frlengths[trans_count]; 4778 trans_count++; 4779 4780 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4781 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4782 break; 4783 } 4784 } 4785 4786 /* 4787 * Step 1.75, set buffer pointers. To simplify matters, all 4788 * pointers are filled out for the next 7 hardware pages in 4789 * the dma block, so no need to worry what pages to cover 4790 * and what to not. 4791 */ 4792 4793 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4794 /* 4795 * Don't try to lookup a page that's past the end 4796 * of buffer 4797 */ 4798 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4799 if (page_offs >= dma_buf->udma_block->size) 4800 break; 4801 4802 uint64_t page = DMAADDR(dma_buf, page_offs); 4803 page = EHCI_PAGE(page); 4804 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4805 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4806 } 4807 /* 4808 * Other special values 4809 */ 4810 4811 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4812 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4813 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4814 4815 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4816 ? 1 : 0; 4817 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4818 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4819 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4820 4821 /* FIXME: handle invalid trans */ 4822 itd->itd.itd_bufr[2] |= 4823 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4824 4825 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4826 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4827 4828 prev = itd; 4829 } /* End of frame */ 4830 4831 if (xfer->ux_length) 4832 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4833 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4834 4835 /* 4836 * Part 2: Transfer descriptors have now been set up, now they must 4837 * be scheduled into the period frame list. Erk. Not wanting to 4838 * complicate matters, transfer is denied if the transfer spans 4839 * more than the period frame list. 4840 */ 4841 4842 mutex_enter(&sc->sc_lock); 4843 4844 /* Start inserting frames */ 4845 if (epipe->isoc.cur_xfers > 0) { 4846 frindex = epipe->isoc.next_frame; 4847 } else { 4848 frindex = EOREAD4(sc, EHCI_FRINDEX); 4849 frindex = frindex >> 3; /* Erase microframe index */ 4850 frindex += 2; 4851 } 4852 4853 if (frindex >= sc->sc_flsize) 4854 frindex &= (sc->sc_flsize - 1); 4855 4856 /* What's the frame interval? */ 4857 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4858 if (i / USB_UFRAMES_PER_FRAME == 0) 4859 i = 1; 4860 else 4861 i /= USB_UFRAMES_PER_FRAME; 4862 4863 itd = exfer->ex_itdstart; 4864 for (j = 0; j < frames; j++) { 4865 KASSERTMSG(itd != NULL, "frame %d\n", j); 4866 4867 usb_syncmem(&sc->sc_fldma, 4868 sizeof(ehci_link_t) * frindex, 4869 sizeof(ehci_link_t), 4870 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4871 4872 itd->itd.itd_next = sc->sc_flist[frindex]; 4873 if (itd->itd.itd_next == 0) 4874 /* 4875 * FIXME: frindex table gets initialized to NULL 4876 * or EHCI_NULL? 4877 */ 4878 itd->itd.itd_next = EHCI_NULL; 4879 4880 usb_syncmem(&itd->dma, 4881 itd->offs + offsetof(ehci_itd_t, itd_next), 4882 sizeof(itd->itd.itd_next), 4883 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4884 4885 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4886 4887 usb_syncmem(&sc->sc_fldma, 4888 sizeof(ehci_link_t) * frindex, 4889 sizeof(ehci_link_t), 4890 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4891 4892 itd->frame_list.next = sc->sc_softitds[frindex]; 4893 sc->sc_softitds[frindex] = itd; 4894 if (itd->frame_list.next != NULL) 4895 itd->frame_list.next->frame_list.prev = itd; 4896 itd->slot = frindex; 4897 itd->frame_list.prev = NULL; 4898 4899 frindex += i; 4900 if (frindex >= sc->sc_flsize) 4901 frindex -= sc->sc_flsize; 4902 4903 itd = itd->xfer_next; 4904 } 4905 4906 epipe->isoc.cur_xfers++; 4907 epipe->isoc.next_frame = frindex; 4908 4909 ehci_add_intr_list(sc, exfer); 4910 xfer->ux_status = USBD_IN_PROGRESS; 4911 mutex_exit(&sc->sc_lock); 4912 4913 return USBD_IN_PROGRESS; 4914 } 4915 4916 Static void 4917 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4918 { 4919 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4920 4921 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4922 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4923 } 4924 4925 Static void 4926 ehci_device_isoc_close(struct usbd_pipe *pipe) 4927 { 4928 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4929 4930 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4931 } 4932 4933 Static void 4934 ehci_device_isoc_done(struct usbd_xfer *xfer) 4935 { 4936 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4937 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4938 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4939 4940 KASSERT(mutex_owned(&sc->sc_lock)); 4941 4942 epipe->isoc.cur_xfers--; 4943 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4944 if (xfer->ux_length) 4945 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4946 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4947 } 4948
Indexes created Tue Sep 23 23:09:58 GMT 2025