ehci.c revision 1.297
1 /* $NetBSD: ehci.c,v 1.297 2021/12/22 21:45:02 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna.com.au), and 11 * Nick Hudson . 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 37 * 38 * The EHCI 1.0 spec can be found at 39 * http://www.intel.com/technology/usb/spec.htm 40 * and the USB 2.0 spec at 41 * http://www.usb.org/developers/docs/ 42 * 43 */ 44 45 /* 46 * TODO: 47 * 1) hold off explorations by companion controllers until ehci has started. 48 * 49 * 2) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 3) Command failures are not recovered correctly. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.297 2021/12/22 21:45:02 skrll Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #ifdef _KERNEL_OPT 63 #include "opt_usb.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #include <sys/bus.h> 69 #include <sys/cpu.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/kmem.h> 73 #include <sys/mutex.h> 74 #include <sys/proc.h> 75 #include <sys/queue.h> 76 #include <sys/select.h> 77 #include <sys/sysctl.h> 78 #include <sys/systm.h> 79 #include <sys/reboot.h> 80 81 #include <machine/endian.h> 82 83 #include <dev/usb/usb.h> 84 #include <dev/usb/usbdi.h> 85 #include <dev/usb/usbdivar.h> 86 #include <dev/usb/usbhist.h> 87 #include <dev/usb/usb_mem.h> 88 #include <dev/usb/usb_quirks.h> 89 90 #include <dev/usb/ehcireg.h> 91 #include <dev/usb/ehcivar.h> 92 #include <dev/usb/usbroothub.h> 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 static int ehcidebug = 0; 99 100 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 101 { 102 int err; 103 const struct sysctlnode *rnode; 104 const struct sysctlnode *cnode; 105 106 err = sysctl_createv(clog, 0, NULL, &rnode, 107 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 108 SYSCTL_DESCR("ehci global controls"), 109 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 110 111 if (err) 112 goto fail; 113 114 /* control debugging printfs */ 115 err = sysctl_createv(clog, 0, &rnode, &cnode, 116 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 117 "debug", SYSCTL_DESCR("Enable debugging output"), 118 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 119 if (err) 120 goto fail; 121 122 return; 123 fail: 124 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 125 } 126 127 #endif /* EHCI_DEBUG */ 128 #endif /* USB_DEBUG */ 129 130 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 131 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 132 #define EHCIHIST_FUNC() USBHIST_FUNC() 133 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 134 135 struct ehci_pipe { 136 struct usbd_pipe pipe; 137 int nexttoggle; 138 139 ehci_soft_qh_t *sqh; 140 union { 141 /* Control pipe */ 142 struct { 143 usb_dma_t reqdma; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 u_int length; 148 } intr; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 }; 155 }; 156 157 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 158 159 Static usbd_status ehci_open(struct usbd_pipe *); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_intrlist_timeout(void *); 171 Static void ehci_doorbell(void *); 172 Static void ehci_pcd(void *); 173 174 Static struct usbd_xfer * 175 ehci_allocx(struct usbd_bus *, unsigned int); 176 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 177 178 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 179 Static bool ehci_dying(struct usbd_bus *); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abortx(struct usbd_xfer *); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_abortx = ehci_abortx, 323 .ubm_dying = ehci_dying, 324 .ubm_getlock = ehci_get_lock, 325 .ubm_rhctrl = ehci_roothub_ctrl, 326 }; 327 328 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 329 .upm_transfer = ehci_root_intr_transfer, 330 .upm_start = ehci_root_intr_start, 331 .upm_abort = ehci_root_intr_abort, 332 .upm_close = ehci_root_intr_close, 333 .upm_cleartoggle = ehci_noop, 334 .upm_done = ehci_root_intr_done, 335 }; 336 337 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 338 .upm_init = ehci_device_ctrl_init, 339 .upm_fini = ehci_device_ctrl_fini, 340 .upm_transfer = ehci_device_ctrl_transfer, 341 .upm_start = ehci_device_ctrl_start, 342 .upm_abort = ehci_device_ctrl_abort, 343 .upm_close = ehci_device_ctrl_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_ctrl_done, 346 }; 347 348 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 349 .upm_init = ehci_device_intr_init, 350 .upm_fini = ehci_device_intr_fini, 351 .upm_transfer = ehci_device_intr_transfer, 352 .upm_start = ehci_device_intr_start, 353 .upm_abort = ehci_device_intr_abort, 354 .upm_close = ehci_device_intr_close, 355 .upm_cleartoggle = ehci_device_clear_toggle, 356 .upm_done = ehci_device_intr_done, 357 }; 358 359 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 360 .upm_init = ehci_device_bulk_init, 361 .upm_fini = ehci_device_bulk_fini, 362 .upm_transfer = ehci_device_bulk_transfer, 363 .upm_start = ehci_device_bulk_start, 364 .upm_abort = ehci_device_bulk_abort, 365 .upm_close = ehci_device_bulk_close, 366 .upm_cleartoggle = ehci_device_clear_toggle, 367 .upm_done = ehci_device_bulk_done, 368 }; 369 370 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 371 .upm_init = ehci_device_isoc_init, 372 .upm_fini = ehci_device_isoc_fini, 373 .upm_transfer = ehci_device_isoc_transfer, 374 .upm_abort = ehci_device_isoc_abort, 375 .upm_close = ehci_device_isoc_close, 376 .upm_cleartoggle = ehci_noop, 377 .upm_done = ehci_device_isoc_done, 378 }; 379 380 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 381 .upm_init = ehci_device_fs_isoc_init, 382 .upm_fini = ehci_device_fs_isoc_fini, 383 .upm_transfer = ehci_device_fs_isoc_transfer, 384 .upm_abort = ehci_device_fs_isoc_abort, 385 .upm_close = ehci_device_fs_isoc_close, 386 .upm_cleartoggle = ehci_noop, 387 .upm_done = ehci_device_fs_isoc_done, 388 }; 389 390 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 391 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 392 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 393 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 394 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 395 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 396 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 397 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 398 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 399 }; 400 401 int 402 ehci_init(ehci_softc_t *sc) 403 { 404 uint32_t vers, hcr; 405 u_int i; 406 int err; 407 ehci_soft_qh_t *sqh; 408 u_int ncomp; 409 410 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 411 #ifdef EHCI_DEBUG 412 theehci = sc; 413 #endif 414 415 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 416 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 417 cv_init(&sc->sc_doorbell, "ehcidb"); 418 419 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 420 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 421 422 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 423 ehci_doorbell, sc); 424 KASSERT(sc->sc_doorbell_si != NULL); 425 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 426 ehci_pcd, sc); 427 KASSERT(sc->sc_pcd_si != NULL); 428 429 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 430 431 vers = EREAD2(sc, EHCI_HCIVERSION); 432 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 433 vers >> 8, vers & 0xff); 434 435 const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS); 436 DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0); 437 sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams); 438 ncomp = EHCI_HCS_N_CC(hcsparams); 439 if (ncomp != sc->sc_ncomp) { 440 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 441 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 442 #if NOHCI == 0 || NUHCI == 0 443 aprint_error("%s: ohci or uhci probably not configured\n", 444 device_xname(sc->sc_dev)); 445 #endif 446 if (ncomp < sc->sc_ncomp) 447 sc->sc_ncomp = ncomp; 448 } 449 if (sc->sc_ncomp > 0) { 450 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 451 aprint_normal_dev(sc->sc_dev, 452 "%d companion controller%s, %d port%s%s", 453 sc->sc_ncomp, 454 sc->sc_ncomp!=1 ? "s" : "", 455 EHCI_HCS_N_PCC(hcsparams), 456 EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "", 457 sc->sc_ncomp!=1 ? " each" : ""); 458 if (sc->sc_comps[0]) { 459 aprint_normal(":"); 460 for (i = 0; i < sc->sc_ncomp; i++) 461 aprint_normal(" %s", 462 device_xname(sc->sc_comps[i])); 463 } 464 aprint_normal("\n"); 465 466 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 467 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 468 cv_init(&sc->sc_compcv, "ehciccv"); 469 sc->sc_comp_state = CO_EARLY; 470 } 471 sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams); 472 sc->sc_hasppc = EHCI_HCS_PPC(hcsparams); 473 474 const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS); 475 DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0); 476 477 if (EHCI_HCC_64BIT(hccparams)) { 478 /* MUST clear segment register if 64 bit capable. */ 479 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 480 } 481 482 if (hccparams & EHCI_HCC_IST_FULLFRAME) { 483 sc->sc_istthreshold = 0; 484 } else { 485 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams); 486 } 487 488 sc->sc_bus.ub_revision = USBREV_2_0; 489 sc->sc_bus.ub_usedma = true; 490 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 491 492 /* 493 * The bus attachment code will possibly provide a 64bit DMA 494 * tag which we now limit to the bottom 4G range as 495 * 496 * - that's as much as ehci can address in its QH, TD, iTD, and siTD 497 * structures; and 498 * - the driver doesn't currently set EHCI_CTRLDSSEGMENT to anything 499 * other than 0. 500 */ 501 bus_dma_tag_t ntag; 502 sc->sc_dmatag = sc->sc_bus.ub_dmatag; 503 err = bus_dmatag_subregion(sc->sc_bus.ub_dmatag, 0, UINT32_MAX, 504 &ntag, 0); 505 if (err == 0) { 506 sc->sc_dmatag = ntag; 507 aprint_normal_dev(sc->sc_dev, "Using DMA subregion for control" 508 " data structures\n"); 509 } 510 511 /* Reset the controller */ 512 DPRINTF("resetting", 0, 0, 0, 0); 513 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 514 usb_delay_ms(&sc->sc_bus, 1); 515 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 516 for (i = 0; i < 100; i++) { 517 usb_delay_ms(&sc->sc_bus, 1); 518 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 519 if (!hcr) 520 break; 521 } 522 if (hcr) { 523 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 524 err = EIO; 525 goto fail1; 526 } 527 if (sc->sc_vendor_init) 528 sc->sc_vendor_init(sc); 529 530 /* XXX need proper intr scheduling */ 531 sc->sc_rand = 96; 532 533 /* frame list size at default, read back what we got and use that */ 534 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 535 case 0: sc->sc_flsize = 1024; break; 536 case 1: sc->sc_flsize = 512; break; 537 case 2: sc->sc_flsize = 256; break; 538 case 3: 539 err = EIO; 540 goto fail1; 541 } 542 err = usb_allocmem(sc->sc_bus.ub_dmatag, 543 sc->sc_flsize * sizeof(ehci_link_t), 544 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 545 if (err) { 546 aprint_error_dev(sc->sc_dev, "failed to allocate frame list\n"); 547 goto fail1; 548 } 549 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 550 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 551 552 for (i = 0; i < sc->sc_flsize; i++) { 553 sc->sc_flist[i] = EHCI_NULL; 554 } 555 556 KASSERT(BUS_ADDR_HI32(DMAADDR(&sc->sc_fldma, 0)) == 0); 557 uint32_t lo32 = BUS_ADDR_LO32(DMAADDR(&sc->sc_fldma, 0)); 558 559 EOWRITE4(sc, EHCI_PERIODICLISTBASE, lo32); 560 561 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 562 KM_SLEEP); 563 LIST_INIT(&sc->sc_freeitds); 564 LIST_INIT(&sc->sc_freesitds); 565 TAILQ_INIT(&sc->sc_intrhead); 566 567 /* Set up the bus struct. */ 568 sc->sc_bus.ub_methods = &ehci_bus_methods; 569 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 570 571 sc->sc_eintrs = EHCI_NORMAL_INTRS; 572 573 /* 574 * Allocate the interrupt dummy QHs. These are arranged to give poll 575 * intervals that are powers of 2 times 1ms. 576 */ 577 memset(sc->sc_islots, 0, sizeof(sc->sc_islots)); 578 for (i = 0; i < EHCI_INTRQHS; i++) { 579 sqh = ehci_alloc_sqh(sc); 580 if (sqh == NULL) { 581 err = ENOMEM; 582 goto fail2; 583 } 584 sc->sc_islots[i].sqh = sqh; 585 } 586 for (i = 0; i < EHCI_INTRQHS; i++) { 587 sqh = sc->sc_islots[i].sqh; 588 if (i == 0) { 589 /* The last (1ms) QH terminates. */ 590 sqh->qh.qh_link = EHCI_NULL; 591 sqh->next = NULL; 592 } else { 593 /* Otherwise the next QH has half the poll interval */ 594 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 595 sqh->qh.qh_link = htole32(sqh->next->physaddr | 596 EHCI_LINK_QH); 597 } 598 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 599 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 600 sqh->qh.qh_curqtd = EHCI_NULL; 601 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 602 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 603 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 604 sqh->sqtd = NULL; 605 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 607 } 608 /* Point the frame list at the last level (128ms). */ 609 for (i = 0; i < sc->sc_flsize; i++) { 610 int j; 611 612 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 613 revbits[i & (EHCI_MAX_POLLRATE-1)]; 614 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 615 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 616 i)].sqh->physaddr); 617 } 618 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 619 BUS_DMASYNC_PREWRITE); 620 621 /* Allocate dummy QH that starts the async list. */ 622 sqh = ehci_alloc_sqh(sc); 623 if (sqh == NULL) { 624 err = ENOMEM; 625 goto fail2; 626 } 627 /* Fill the QH */ 628 sqh->qh.qh_endp = 629 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 630 sqh->qh.qh_link = 631 htole32(sqh->physaddr | EHCI_LINK_QH); 632 sqh->qh.qh_curqtd = EHCI_NULL; 633 sqh->next = NULL; 634 /* Fill the overlay qTD */ 635 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 636 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 637 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 638 sqh->sqtd = NULL; 639 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 640 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 641 #ifdef EHCI_DEBUG 642 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 643 ehci_dump_sqh(sqh); 644 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 645 #endif 646 647 /* Point to async list */ 648 sc->sc_async_head = sqh; 649 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 650 651 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 652 653 /* Turn on controller */ 654 EOWRITE4(sc, EHCI_USBCMD, 655 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 656 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 657 EHCI_CMD_ASE | 658 EHCI_CMD_PSE | 659 EHCI_CMD_RS); 660 661 /* Take over port ownership */ 662 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 663 664 for (i = 0; i < 100; i++) { 665 usb_delay_ms(&sc->sc_bus, 1); 666 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 667 if (!hcr) 668 break; 669 } 670 if (hcr) { 671 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 672 err = EIO; 673 goto fail3; 674 } 675 676 /* Enable interrupts */ 677 DPRINTF("enabling interrupts", 0, 0, 0, 0); 678 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 679 680 return 0; 681 682 fail3: 683 ehci_free_sqh(sc, sc->sc_async_head); 684 685 fail2: 686 for (i = 0; i < EHCI_INTRQHS; i++) { 687 sqh = sc->sc_islots[i].sqh; 688 if (sqh) 689 ehci_free_sqh(sc, sqh); 690 } 691 692 kmem_free(sc->sc_softitds, sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 693 usb_freemem(&sc->sc_fldma); 694 695 fail1: 696 softint_disestablish(sc->sc_doorbell_si); 697 softint_disestablish(sc->sc_pcd_si); 698 mutex_destroy(&sc->sc_lock); 699 mutex_destroy(&sc->sc_intr_lock); 700 701 return err; 702 } 703 704 int 705 ehci_intr(void *v) 706 { 707 ehci_softc_t *sc = v; 708 int ret = 0; 709 710 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 711 712 if (sc == NULL) 713 return 0; 714 715 mutex_spin_enter(&sc->sc_intr_lock); 716 717 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 718 goto done; 719 720 /* If we get an interrupt while polling, then just ignore it. */ 721 if (sc->sc_bus.ub_usepolling) { 722 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 723 724 if (intrs) 725 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 726 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 727 goto done; 728 } 729 730 ret = ehci_intr1(sc); 731 732 done: 733 mutex_spin_exit(&sc->sc_intr_lock); 734 return ret; 735 } 736 737 Static int 738 ehci_intr1(ehci_softc_t *sc) 739 { 740 uint32_t intrs, eintrs; 741 742 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 743 744 /* In case the interrupt occurs before initialization has completed. */ 745 if (sc == NULL) { 746 #ifdef DIAGNOSTIC 747 printf("ehci_intr1: sc == NULL\n"); 748 #endif 749 return 0; 750 } 751 752 KASSERT(mutex_owned(&sc->sc_intr_lock)); 753 754 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 755 if (!intrs) 756 return 0; 757 758 eintrs = intrs & sc->sc_eintrs; 759 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 760 EOREAD4(sc, EHCI_USBSTS), eintrs); 761 if (!eintrs) 762 return 0; 763 764 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 765 if (eintrs & EHCI_STS_IAA) { 766 DPRINTF("door bell", 0, 0, 0, 0); 767 kpreempt_disable(); 768 KASSERT(sc->sc_doorbell_si != NULL); 769 softint_schedule(sc->sc_doorbell_si); 770 kpreempt_enable(); 771 eintrs &= ~EHCI_STS_IAA; 772 } 773 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 774 DPRINTF("INT=%jd ERRINT=%jd", 775 eintrs & EHCI_STS_INT ? 1 : 0, 776 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 777 usb_schedsoftintr(&sc->sc_bus); 778 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 779 } 780 if (eintrs & EHCI_STS_HSE) { 781 printf("%s: unrecoverable error, controller halted\n", 782 device_xname(sc->sc_dev)); 783 /* XXX what else */ 784 } 785 if (eintrs & EHCI_STS_PCD) { 786 kpreempt_disable(); 787 KASSERT(sc->sc_pcd_si != NULL); 788 softint_schedule(sc->sc_pcd_si); 789 kpreempt_enable(); 790 eintrs &= ~EHCI_STS_PCD; 791 } 792 793 if (eintrs != 0) { 794 /* Block unprocessed interrupts. */ 795 sc->sc_eintrs &= ~eintrs; 796 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 797 printf("%s: blocking intrs %#x\n", 798 device_xname(sc->sc_dev), eintrs); 799 } 800 801 return 1; 802 } 803 804 Static void 805 ehci_doorbell(void *addr) 806 { 807 ehci_softc_t *sc = addr; 808 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 809 810 mutex_enter(&sc->sc_lock); 811 cv_broadcast(&sc->sc_doorbell); 812 mutex_exit(&sc->sc_lock); 813 } 814 815 Static void 816 ehci_pcd(void *addr) 817 { 818 ehci_softc_t *sc = addr; 819 struct usbd_xfer *xfer; 820 u_char *p; 821 int i, m; 822 823 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 824 825 mutex_enter(&sc->sc_lock); 826 xfer = sc->sc_intrxfer; 827 828 if (xfer == NULL) { 829 /* Just ignore the change. */ 830 goto done; 831 } 832 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 833 834 p = xfer->ux_buf; 835 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 836 memset(p, 0, xfer->ux_length); 837 for (i = 1; i <= m; i++) { 838 /* Pick out CHANGE bits from the status reg. */ 839 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 840 p[i/8] |= 1 << (i%8); 841 if (i % 8 == 7) 842 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 843 } 844 xfer->ux_actlen = xfer->ux_length; 845 xfer->ux_status = USBD_NORMAL_COMPLETION; 846 847 usb_transfer_complete(xfer); 848 849 done: 850 mutex_exit(&sc->sc_lock); 851 } 852 853 Static void 854 ehci_softintr(void *v) 855 { 856 struct usbd_bus *bus = v; 857 ehci_softc_t *sc = EHCI_BUS2SC(bus); 858 struct ehci_xfer *ex, *nextex; 859 860 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 861 862 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 863 864 ex_completeq_t cq; 865 TAILQ_INIT(&cq); 866 867 /* 868 * The only explanation I can think of for why EHCI is as brain dead 869 * as UHCI interrupt-wise is that Intel was involved in both. 870 * An interrupt just tells us that something is done, we have no 871 * clue what, so we need to scan through all active transfers. :-( 872 */ 873 874 /* 875 * ehci_idone will remove transfer from sc->sc_intrhead if it's 876 * complete and add to our cq list 877 * 878 */ 879 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 880 switch (ex->ex_type) { 881 case EX_CTRL: 882 case EX_BULK: 883 case EX_INTR: 884 ehci_check_qh_intr(sc, ex, &cq); 885 break; 886 case EX_ISOC: 887 ehci_check_itd_intr(sc, ex, &cq); 888 break; 889 case EX_FS_ISOC: 890 ehci_check_sitd_intr(sc, ex, &cq); 891 break; 892 default: 893 KASSERT(false); 894 } 895 896 } 897 898 /* 899 * We abuse ex_next for the interrupt and complete lists and 900 * interrupt transfers will get re-added here so use 901 * the _SAFE version of TAILQ_FOREACH. 902 */ 903 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 904 usb_transfer_complete(&ex->ex_xfer); 905 } 906 907 /* Schedule a callout to catch any dropped transactions. */ 908 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 909 !TAILQ_EMPTY(&sc->sc_intrhead)) 910 callout_reset(&sc->sc_tmo_intrlist, 911 hz, ehci_intrlist_timeout, sc); 912 } 913 914 Static void 915 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 916 { 917 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 918 uint32_t status; 919 920 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 921 922 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 923 924 if (ex->ex_type == EX_CTRL) { 925 fsqtd = ex->ex_setup; 926 lsqtd = ex->ex_status; 927 } else { 928 fsqtd = ex->ex_sqtdstart; 929 lsqtd = ex->ex_sqtdend; 930 } 931 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 932 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 933 934 /* 935 * If the last TD is still active we need to check whether there 936 * is an error somewhere in the middle, or whether there was a 937 * short packet (SPD and not ACTIVE). 938 */ 939 usb_syncmem(&lsqtd->dma, 940 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 941 sizeof(lsqtd->qtd.qtd_status), 942 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 943 status = le32toh(lsqtd->qtd.qtd_status); 944 usb_syncmem(&lsqtd->dma, 945 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 946 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 947 if (status & EHCI_QTD_ACTIVE) { 948 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 949 950 /* last qTD has already been checked */ 951 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 952 usb_syncmem(&sqtd->dma, 953 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 954 sizeof(sqtd->qtd.qtd_status), 955 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 956 status = le32toh(sqtd->qtd.qtd_status); 957 usb_syncmem(&sqtd->dma, 958 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 959 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 960 /* If there's an active QTD the xfer isn't done. */ 961 if (status & EHCI_QTD_ACTIVE) 962 break; 963 /* Any kind of error makes the xfer done. */ 964 if (status & EHCI_QTD_HALTED) 965 goto done; 966 /* Handle short packets */ 967 if (EHCI_QTD_GET_BYTES(status) != 0) { 968 /* 969 * If we get here for a control transfer then 970 * we need to let the hardware complete the 971 * status phase. That is, we're not done 972 * quite yet. 973 * 974 * Otherwise, we're done. 975 */ 976 if (ex->ex_type == EX_CTRL) { 977 break; 978 } 979 goto done; 980 } 981 } 982 DPRINTFN(10, "ex=%#jx std=%#jx still active", 983 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 984 #ifdef EHCI_DEBUG 985 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 986 ehci_dump_sqtds(ex->ex_sqtdstart); 987 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 988 #endif 989 return; 990 } 991 done: 992 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 993 ehci_idone(ex, cq); 994 } 995 996 Static void 997 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 998 { 999 ehci_soft_itd_t *itd; 1000 int i; 1001 1002 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1003 1004 KASSERT(mutex_owned(&sc->sc_lock)); 1005 1006 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1007 return; 1008 1009 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 1010 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 1011 1012 itd = ex->ex_itdend; 1013 1014 /* 1015 * check no active transfers in last itd, meaning we're finished 1016 */ 1017 1018 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1019 sizeof(itd->itd.itd_ctl), 1020 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1021 1022 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1023 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 1024 break; 1025 } 1026 1027 if (i == EHCI_ITD_NUFRAMES) { 1028 goto done; /* All 8 descriptors inactive, it's done */ 1029 } 1030 1031 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1032 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1033 1034 DPRINTFN(10, "ex %#jx itd %#jx still active", 1035 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 1036 return; 1037 done: 1038 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 1039 ehci_idone(ex, cq); 1040 } 1041 1042 void 1043 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1044 { 1045 ehci_soft_sitd_t *sitd; 1046 1047 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1048 1049 KASSERT(mutex_owned(&sc->sc_lock)); 1050 1051 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1052 return; 1053 1054 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1055 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1056 1057 sitd = ex->ex_sitdend; 1058 1059 /* 1060 * check no active transfers in last sitd, meaning we're finished 1061 */ 1062 1063 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1064 sizeof(sitd->sitd.sitd_trans), 1065 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1066 1067 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1068 1069 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1070 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1071 1072 if (active) 1073 return; 1074 1075 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1076 ehci_idone(ex, cq); 1077 } 1078 1079 Static void 1080 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1081 { 1082 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1083 struct usbd_xfer *xfer = &ex->ex_xfer; 1084 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1085 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1086 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1087 uint32_t status = 0, nstatus = 0; 1088 int actlen = 0; 1089 1090 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1091 1092 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1093 1094 /* 1095 * Try to claim this xfer for completion. If it has already 1096 * completed or aborted, drop it on the floor. 1097 */ 1098 if (!usbd_xfer_trycomplete(xfer)) 1099 return; 1100 1101 #ifdef DIAGNOSTIC 1102 #ifdef EHCI_DEBUG 1103 if (ex->ex_isdone) { 1104 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1105 ehci_dump_exfer(ex); 1106 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1107 } 1108 #endif 1109 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1110 ex->ex_type, xfer->ux_status); 1111 ex->ex_isdone = true; 1112 #endif 1113 1114 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1115 (uintptr_t)epipe, 0, 0); 1116 1117 /* The transfer is done, compute actual length and status. */ 1118 if (ex->ex_type == EX_ISOC) { 1119 /* HS isoc transfer */ 1120 1121 struct ehci_soft_itd *itd; 1122 int i, nframes, len, uframes; 1123 1124 nframes = 0; 1125 1126 #ifdef EHCI_DEBUG 1127 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1128 ehci_dump_itds(ex->ex_itdstart); 1129 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1130 #endif 1131 1132 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1133 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1134 1135 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1136 usb_syncmem(&itd->dma, 1137 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1138 sizeof(itd->itd.itd_ctl), 1139 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1140 1141 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1142 /* 1143 * XXX - driver didn't fill in the frame full 1144 * of uframes. This leads to scheduling 1145 * inefficiencies, but working around 1146 * this doubles complexity of tracking 1147 * an xfer. 1148 */ 1149 if (nframes >= xfer->ux_nframes) 1150 break; 1151 1152 status = le32toh(itd->itd.itd_ctl[i]); 1153 len = EHCI_ITD_GET_LEN(status); 1154 if (EHCI_ITD_GET_STATUS(status) != 0) 1155 len = 0; /*No valid data on error*/ 1156 1157 xfer->ux_frlengths[nframes++] = len; 1158 actlen += len; 1159 } 1160 usb_syncmem(&itd->dma, 1161 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1162 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1163 1164 if (nframes >= xfer->ux_nframes) 1165 break; 1166 } 1167 1168 xfer->ux_actlen = actlen; 1169 xfer->ux_status = USBD_NORMAL_COMPLETION; 1170 goto end; 1171 } else if (ex->ex_type == EX_FS_ISOC) { 1172 /* FS isoc transfer */ 1173 struct ehci_soft_sitd *sitd; 1174 int nframes, len; 1175 1176 nframes = 0; 1177 1178 for (sitd = ex->ex_sitdstart; sitd != NULL; 1179 sitd = sitd->xfer_next) { 1180 usb_syncmem(&sitd->dma, 1181 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1182 sizeof(sitd->sitd.sitd_trans), 1183 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1184 1185 /* 1186 * XXX - driver didn't fill in the frame full 1187 * of uframes. This leads to scheduling 1188 * inefficiencies, but working around 1189 * this doubles complexity of tracking 1190 * an xfer. 1191 */ 1192 if (nframes >= xfer->ux_nframes) 1193 break; 1194 1195 status = le32toh(sitd->sitd.sitd_trans); 1196 usb_syncmem(&sitd->dma, 1197 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1198 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1199 1200 len = EHCI_SITD_GET_LEN(status); 1201 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1202 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1203 /* No valid data on error */ 1204 len = xfer->ux_frlengths[nframes]; 1205 } 1206 1207 /* 1208 * frlengths[i]: # of bytes to send 1209 * len: # of bytes host didn't send 1210 */ 1211 xfer->ux_frlengths[nframes] -= len; 1212 /* frlengths[i]: # of bytes host sent */ 1213 actlen += xfer->ux_frlengths[nframes++]; 1214 1215 if (nframes >= xfer->ux_nframes) 1216 break; 1217 } 1218 1219 xfer->ux_actlen = actlen; 1220 xfer->ux_status = USBD_NORMAL_COMPLETION; 1221 goto end; 1222 } 1223 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1224 ex->ex_type == EX_BULK); 1225 1226 /* Continue processing xfers using queue heads */ 1227 if (ex->ex_type == EX_CTRL) { 1228 fsqtd = ex->ex_setup; 1229 lsqtd = ex->ex_status; 1230 } else { 1231 fsqtd = ex->ex_sqtdstart; 1232 lsqtd = ex->ex_sqtdend; 1233 } 1234 #ifdef EHCI_DEBUG 1235 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1236 ehci_dump_sqtds(fsqtd); 1237 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1238 #endif 1239 1240 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1241 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1242 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1243 nstatus = le32toh(sqtd->qtd.qtd_status); 1244 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1245 BUS_DMASYNC_PREREAD); 1246 if (nstatus & EHCI_QTD_ACTIVE) 1247 break; 1248 1249 status = nstatus; 1250 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1251 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1252 } 1253 1254 /* 1255 * If there are left over TDs we need to update the toggle. 1256 * The default pipe doesn't need it since control transfers 1257 * start the toggle at 0 every time. 1258 * For a short transfer we need to update the toggle for the missing 1259 * packets within the qTD. 1260 */ 1261 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1262 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1263 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1264 status, nstatus, 0, 0); 1265 #if 0 1266 ehci_dump_sqh(epipe->sqh); 1267 ehci_dump_sqtds(ex->ex_sqtdstart); 1268 #endif 1269 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1270 } 1271 1272 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1273 status, 0); 1274 xfer->ux_actlen = actlen; 1275 if (status & EHCI_QTD_HALTED) { 1276 #ifdef EHCI_DEBUG 1277 DPRINTF("halted addr=%jd endpt=0x%02jx", 1278 xfer->ux_pipe->up_dev->ud_addr, 1279 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1280 0, 0); 1281 DPRINTF("cerr=%jd pid=%jd", 1282 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1283 0, 0); 1284 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1285 status & EHCI_QTD_ACTIVE ? 1 : 0, 1286 status & EHCI_QTD_HALTED ? 1 : 0, 1287 status & EHCI_QTD_BUFERR ? 1 : 0, 1288 status & EHCI_QTD_BABBLE ? 1 : 0); 1289 1290 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1291 status & EHCI_QTD_XACTERR ? 1 : 0, 1292 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1293 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1294 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1295 1296 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1297 ehci_dump_sqh(epipe->sqh); 1298 ehci_dump_sqtds(ex->ex_sqtdstart); 1299 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1300 #endif 1301 /* low&full speed has an extra error flag */ 1302 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1303 EHCI_QH_SPEED_HIGH) 1304 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1305 else 1306 status &= EHCI_QTD_STATERRS; 1307 if (status == 0) /* no other errors means a stall */ { 1308 xfer->ux_status = USBD_STALLED; 1309 } else { 1310 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1311 } 1312 /* XXX need to reset TT on missed microframe */ 1313 if (status & EHCI_QTD_MISSEDMICRO) { 1314 printf("%s: missed microframe, TT reset not " 1315 "implemented, hub might be inoperational\n", 1316 device_xname(sc->sc_dev)); 1317 } 1318 } else { 1319 xfer->ux_status = USBD_NORMAL_COMPLETION; 1320 } 1321 1322 end: 1323 1324 ehci_del_intr_list(sc, ex); 1325 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1326 1327 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1328 } 1329 1330 Static void 1331 ehci_poll(struct usbd_bus *bus) 1332 { 1333 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1334 1335 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1336 1337 #ifdef EHCI_DEBUG 1338 static int last; 1339 int new; 1340 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1341 if (new != last) { 1342 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1343 last = new; 1344 } 1345 #endif 1346 1347 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1348 mutex_spin_enter(&sc->sc_intr_lock); 1349 ehci_intr1(sc); 1350 mutex_spin_exit(&sc->sc_intr_lock); 1351 } 1352 } 1353 1354 void 1355 ehci_childdet(device_t self, device_t child) 1356 { 1357 struct ehci_softc *sc = device_private(self); 1358 1359 KASSERT(sc->sc_child == child); 1360 sc->sc_child = NULL; 1361 } 1362 1363 int 1364 ehci_detach(struct ehci_softc *sc, int flags) 1365 { 1366 int rv = 0; 1367 1368 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1369 1370 if (sc->sc_child != NULL) { 1371 rv = config_detach(sc->sc_child, flags); 1372 if (rv != 0) 1373 return rv; 1374 } 1375 1376 if (sc->sc_ncomp > 0) { 1377 mutex_enter(&sc->sc_complock); 1378 /* XXX try to halt callout instead of waiting */ 1379 while (sc->sc_comp_state == CO_SCHED) 1380 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1381 mutex_exit(&sc->sc_complock); 1382 1383 callout_halt(&sc->sc_compcallout, NULL); 1384 callout_destroy(&sc->sc_compcallout); 1385 cv_destroy(&sc->sc_compcv); 1386 mutex_destroy(&sc->sc_complock); 1387 } 1388 1389 callout_halt(&sc->sc_tmo_intrlist, NULL); 1390 callout_destroy(&sc->sc_tmo_intrlist); 1391 1392 /* XXX free other data structures */ 1393 if (sc->sc_softitds) { 1394 kmem_free(sc->sc_softitds, 1395 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1396 } 1397 cv_destroy(&sc->sc_doorbell); 1398 1399 #if 0 1400 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1401 softint_disestablish(sc->sc_doorbell_si); 1402 softint_disestablish(sc->sc_pcd_si); 1403 mutex_destroy(&sc->sc_lock); 1404 mutex_destroy(&sc->sc_intr_lock); 1405 #endif 1406 1407 pool_cache_destroy(sc->sc_xferpool); 1408 1409 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1410 1411 return rv; 1412 } 1413 1414 int 1415 ehci_activate(device_t self, enum devact act) 1416 { 1417 struct ehci_softc *sc = device_private(self); 1418 1419 switch (act) { 1420 case DVACT_DEACTIVATE: 1421 sc->sc_dying = 1; 1422 return 0; 1423 default: 1424 return EOPNOTSUPP; 1425 } 1426 } 1427 1428 /* 1429 * Handle suspend/resume. 1430 * 1431 * Note that this power handler isn't to be registered directly; the 1432 * bus glue needs to call out to it. 1433 */ 1434 bool 1435 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1436 { 1437 ehci_softc_t *sc = device_private(dv); 1438 int i; 1439 uint32_t cmd, hcr; 1440 1441 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1442 1443 mutex_enter(&sc->sc_lock); 1444 1445 for (i = 1; i <= sc->sc_noport; i++) { 1446 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1447 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1448 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1449 } 1450 1451 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1452 1453 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1454 EOWRITE4(sc, EHCI_USBCMD, cmd); 1455 1456 for (i = 0; i < 100; i++) { 1457 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1458 if (hcr == 0) 1459 break; 1460 1461 usb_delay_ms(&sc->sc_bus, 1); 1462 } 1463 if (hcr != 0) 1464 printf("%s: reset timeout\n", device_xname(dv)); 1465 1466 cmd &= ~EHCI_CMD_RS; 1467 EOWRITE4(sc, EHCI_USBCMD, cmd); 1468 1469 for (i = 0; i < 100; i++) { 1470 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1471 if (hcr == EHCI_STS_HCH) 1472 break; 1473 1474 usb_delay_ms(&sc->sc_bus, 1); 1475 } 1476 if (hcr != EHCI_STS_HCH) 1477 printf("%s: config timeout\n", device_xname(dv)); 1478 1479 mutex_exit(&sc->sc_lock); 1480 1481 return true; 1482 } 1483 1484 bool 1485 ehci_resume(device_t dv, const pmf_qual_t *qual) 1486 { 1487 ehci_softc_t *sc = device_private(dv); 1488 int i; 1489 uint32_t cmd, hcr; 1490 1491 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1492 1493 mutex_enter(&sc->sc_lock); 1494 1495 /* restore things in case the bios sucks */ 1496 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1497 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1498 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1499 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1500 1501 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1502 1503 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1504 1505 hcr = 0; 1506 for (i = 1; i <= sc->sc_noport; i++) { 1507 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1508 if ((cmd & EHCI_PS_PO) == 0 && 1509 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1510 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1511 hcr = 1; 1512 } 1513 } 1514 1515 if (hcr) { 1516 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1517 1518 for (i = 1; i <= sc->sc_noport; i++) { 1519 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1520 if ((cmd & EHCI_PS_PO) == 0 && 1521 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1522 EOWRITE4(sc, EHCI_PORTSC(i), 1523 cmd & ~EHCI_PS_FPR); 1524 } 1525 } 1526 1527 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1528 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1529 1530 for (i = 0; i < 100; i++) { 1531 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1532 if (hcr != EHCI_STS_HCH) 1533 break; 1534 1535 usb_delay_ms(&sc->sc_bus, 1); 1536 } 1537 if (hcr == EHCI_STS_HCH) 1538 printf("%s: config timeout\n", device_xname(dv)); 1539 1540 mutex_exit(&sc->sc_lock); 1541 1542 return true; 1543 } 1544 1545 /* 1546 * Shut down the controller when the system is going down. 1547 */ 1548 bool 1549 ehci_shutdown(device_t self, int flags) 1550 { 1551 ehci_softc_t *sc = device_private(self); 1552 1553 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1554 1555 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1556 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1557 return true; 1558 } 1559 1560 Static struct usbd_xfer * 1561 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1562 { 1563 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1564 struct usbd_xfer *xfer; 1565 1566 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1567 if (xfer != NULL) { 1568 memset(xfer, 0, sizeof(struct ehci_xfer)); 1569 1570 #ifdef DIAGNOSTIC 1571 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1572 ex->ex_isdone = true; 1573 xfer->ux_state = XFER_BUSY; 1574 #endif 1575 } 1576 return xfer; 1577 } 1578 1579 Static void 1580 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1581 { 1582 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1583 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1584 1585 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1586 xfer->ux_status == USBD_NOT_STARTED, 1587 "xfer %p state %d\n", xfer, xfer->ux_state); 1588 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1589 1590 #ifdef DIAGNOSTIC 1591 xfer->ux_state = XFER_FREE; 1592 #endif 1593 1594 pool_cache_put(sc->sc_xferpool, xfer); 1595 } 1596 1597 Static bool 1598 ehci_dying(struct usbd_bus *bus) 1599 { 1600 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1601 1602 return sc->sc_dying; 1603 } 1604 1605 Static void 1606 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1607 { 1608 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1609 1610 *lock = &sc->sc_lock; 1611 } 1612 1613 Static void 1614 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1615 { 1616 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1617 1618 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1619 1620 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1621 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1622 #ifdef EHCI_DEBUG 1623 if (ehcidebug) 1624 usbd_dump_pipe(pipe); 1625 #endif 1626 epipe->nexttoggle = 0; 1627 } 1628 1629 Static void 1630 ehci_noop(struct usbd_pipe *pipe) 1631 { 1632 } 1633 1634 #ifdef EHCI_DEBUG 1635 /* 1636 * Unused function - this is meant to be called from a kernel 1637 * debugger. 1638 */ 1639 void 1640 ehci_dump(void) 1641 { 1642 ehci_softc_t *sc = theehci; 1643 int i; 1644 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1645 EOREAD4(sc, EHCI_USBCMD), 1646 EOREAD4(sc, EHCI_USBSTS), 1647 EOREAD4(sc, EHCI_USBINTR)); 1648 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1649 EOREAD4(sc, EHCI_FRINDEX), 1650 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1651 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1652 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1653 for (i = 1; i <= sc->sc_noport; i++) 1654 printf("port %d status=0x%08x\n", i, 1655 EOREAD4(sc, EHCI_PORTSC(i))); 1656 } 1657 1658 Static void 1659 ehci_dump_regs(ehci_softc_t *sc) 1660 { 1661 int i; 1662 1663 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1664 1665 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1666 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1667 EOREAD4(sc, EHCI_USBINTR), 0); 1668 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1669 "async = 0x%08jx", 1670 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1671 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1672 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1673 for (i = 1; i <= sc->sc_noport; i += 2) { 1674 if (i == sc->sc_noport) { 1675 DPRINTF("port %jd status = 0x%08jx", i, 1676 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1677 } else { 1678 DPRINTF("port %jd status = 0x%08jx port %jd " 1679 "status = 0x%08jx", 1680 i, EOREAD4(sc, EHCI_PORTSC(i)), 1681 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1682 } 1683 } 1684 } 1685 1686 #define ehci_dump_link(link, type) do { \ 1687 DPRINTF(" link 0x%08jx (T = %jd):", \ 1688 link, \ 1689 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1690 if (type) { \ 1691 DPRINTF( \ 1692 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1693 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1694 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1695 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1696 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1697 } \ 1698 } while(0) 1699 1700 Static void 1701 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1702 { 1703 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1704 int i; 1705 uint32_t stop = 0; 1706 1707 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1708 ehci_dump_sqtd(sqtd); 1709 usb_syncmem(&sqtd->dma, 1710 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1711 sizeof(sqtd->qtd), 1712 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1713 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1714 usb_syncmem(&sqtd->dma, 1715 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1716 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1717 } 1718 if (!stop) 1719 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1720 } 1721 1722 Static void 1723 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1724 { 1725 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1726 1727 usb_syncmem(&sqtd->dma, sqtd->offs, 1728 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1729 1730 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1731 0, 0); 1732 ehci_dump_qtd(&sqtd->qtd); 1733 1734 usb_syncmem(&sqtd->dma, sqtd->offs, 1735 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1736 } 1737 1738 Static void 1739 ehci_dump_qtd(ehci_qtd_t *qtd) 1740 { 1741 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1742 uint32_t s = le32toh(qtd->qtd_status); 1743 1744 DPRINTFN(10, 1745 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1746 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1747 DPRINTFN(10, 1748 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1749 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1750 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1751 DPRINTFN(10, 1752 " cerr = %jd pid = %jd stat = %jx", 1753 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1754 0); 1755 DPRINTFN(10, 1756 "active =%jd halted=%jd buferr=%jd babble=%jd", 1757 s & EHCI_QTD_ACTIVE ? 1 : 0, 1758 s & EHCI_QTD_HALTED ? 1 : 0, 1759 s & EHCI_QTD_BUFERR ? 1 : 0, 1760 s & EHCI_QTD_BABBLE ? 1 : 0); 1761 DPRINTFN(10, 1762 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1763 s & EHCI_QTD_XACTERR ? 1 : 0, 1764 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1765 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1766 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1767 DPRINTFN(10, 1768 "buffer[0] = %#jx buffer[1] = %#jx " 1769 "buffer[2] = %#jx buffer[3] = %#jx", 1770 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1771 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1772 DPRINTFN(10, 1773 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1774 } 1775 1776 Static void 1777 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1778 { 1779 ehci_qh_t *qh = &sqh->qh; 1780 ehci_link_t link; 1781 uint32_t endp, endphub; 1782 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1783 1784 usb_syncmem(&sqh->dma, sqh->offs, 1785 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1786 1787 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1788 link = le32toh(qh->qh_link); 1789 ehci_dump_link(link, true); 1790 1791 endp = le32toh(qh->qh_endp); 1792 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1793 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1794 "eps = %jd", 1795 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1796 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1797 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1798 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1799 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1800 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1801 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1802 1803 endphub = le32toh(qh->qh_endphub); 1804 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1805 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1806 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1807 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1808 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1809 EHCI_QH_GET_MULT(endphub), 0); 1810 1811 link = le32toh(qh->qh_curqtd); 1812 ehci_dump_link(link, false); 1813 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1814 ehci_dump_qtd(&qh->qh_qtd); 1815 1816 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1817 BUS_DMASYNC_PREREAD); 1818 } 1819 1820 Static void 1821 ehci_dump_itds(ehci_soft_itd_t *itd) 1822 { 1823 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1824 int i; 1825 uint32_t stop = 0; 1826 1827 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1828 ehci_dump_itd(itd); 1829 usb_syncmem(&itd->dma, 1830 itd->offs + offsetof(ehci_itd_t, itd_next), 1831 sizeof(itd->itd), 1832 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1833 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1834 usb_syncmem(&itd->dma, 1835 itd->offs + offsetof(ehci_itd_t, itd_next), 1836 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1837 } 1838 if (!stop) 1839 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1840 } 1841 1842 Static void 1843 ehci_dump_itd(struct ehci_soft_itd *itd) 1844 { 1845 ehci_isoc_trans_t t; 1846 ehci_isoc_bufr_ptr_t b, b2, b3; 1847 int i; 1848 1849 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1850 1851 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1852 1853 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1854 t = le32toh(itd->itd.itd_ctl[i]); 1855 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1856 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1857 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1858 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1859 EHCI_ITD_GET_OFFS(t), 0); 1860 } 1861 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1862 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1863 DPRINTF(" %jx", 1864 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1865 1866 b = le32toh(itd->itd.itd_bufr[0]); 1867 b2 = le32toh(itd->itd.itd_bufr[1]); 1868 b3 = le32toh(itd->itd.itd_bufr[2]); 1869 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1870 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1871 DPRINTF(" maxpkt = %jx multi = %jx", 1872 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1873 } 1874 1875 Static void 1876 ehci_dump_sitd(struct ehci_soft_itd *itd) 1877 { 1878 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1879 1880 DPRINTF("SITD %#jx next = %p prev = %#jx", 1881 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1882 (uintptr_t)itd->frame_list.prev, 0); 1883 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1884 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1885 } 1886 1887 Static void 1888 ehci_dump_exfer(struct ehci_xfer *ex) 1889 { 1890 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1891 1892 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1893 ex->ex_isdone, 0); 1894 1895 switch (ex->ex_type) { 1896 case EX_CTRL: 1897 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1898 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1899 (uintptr_t)ex->ex_status, 0); 1900 break; 1901 case EX_BULK: 1902 case EX_INTR: 1903 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1904 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1905 0, 0); 1906 break; 1907 case EX_ISOC: 1908 DPRINTF(" itdstart = %#jx itdend = %#jx", 1909 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1910 break; 1911 case EX_FS_ISOC: 1912 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1913 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1914 0, 0); 1915 break; 1916 default: 1917 DPRINTF(" unknown type", 0, 0, 0, 0); 1918 } 1919 } 1920 #endif 1921 1922 Static usbd_status 1923 ehci_open(struct usbd_pipe *pipe) 1924 { 1925 struct usbd_device *dev = pipe->up_dev; 1926 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1927 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1928 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1929 uint8_t addr = dev->ud_addr; 1930 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1931 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1932 ehci_soft_qh_t *sqh; 1933 usbd_status err; 1934 int ival, speed, naks; 1935 int hshubaddr, hshubport; 1936 1937 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1938 1939 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1940 ed->bEndpointAddress, rhaddr); 1941 1942 if (dev->ud_myhsport) { 1943 /* 1944 * When directly attached FS/LS device while doing embedded 1945 * transaction translations and we are the hub, set the hub 1946 * address to 0 (us). 1947 */ 1948 if (!(sc->sc_flags & EHCIF_ETTF) 1949 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1950 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1951 } else { 1952 hshubaddr = 0; 1953 } 1954 hshubport = dev->ud_myhsport->up_portno; 1955 } else { 1956 hshubaddr = 0; 1957 hshubport = 0; 1958 } 1959 1960 if (sc->sc_dying) 1961 return USBD_IOERROR; 1962 1963 /* toggle state needed for bulk endpoints */ 1964 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1965 1966 if (addr == rhaddr) { 1967 switch (ed->bEndpointAddress) { 1968 case USB_CONTROL_ENDPOINT: 1969 pipe->up_methods = &roothub_ctrl_methods; 1970 break; 1971 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1972 pipe->up_methods = &ehci_root_intr_methods; 1973 break; 1974 default: 1975 DPRINTF("bad bEndpointAddress 0x%02jx", 1976 ed->bEndpointAddress, 0, 0, 0); 1977 return USBD_INVAL; 1978 } 1979 return USBD_NORMAL_COMPLETION; 1980 } 1981 1982 /* XXX All this stuff is only valid for async. */ 1983 switch (dev->ud_speed) { 1984 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1985 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1986 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1987 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1988 } 1989 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1990 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 1991 0); 1992 return USBD_INVAL; 1993 } 1994 1995 /* 1996 * For interrupt transfer, nak throttling must be disabled, but for 1997 * the other transfer type, nak throttling should be enabled from the 1998 * viewpoint that avoids the memory thrashing. 1999 */ 2000 naks = (xfertype == UE_INTERRUPT) ? 0 2001 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 2002 2003 /* Allocate sqh for everything, save isoc xfers */ 2004 if (xfertype != UE_ISOCHRONOUS) { 2005 sqh = ehci_alloc_sqh(sc); 2006 if (sqh == NULL) 2007 return USBD_NOMEM; 2008 /* qh_link filled when the QH is added */ 2009 sqh->qh.qh_endp = htole32( 2010 EHCI_QH_SET_ADDR(addr) | 2011 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 2012 EHCI_QH_SET_EPS(speed) | 2013 EHCI_QH_DTC | 2014 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 2015 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 2016 EHCI_QH_CTL : 0) | 2017 EHCI_QH_SET_NRL(naks) 2018 ); 2019 sqh->qh.qh_endphub = htole32( 2020 EHCI_QH_SET_MULT(1) | 2021 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 2022 ); 2023 if (speed != EHCI_QH_SPEED_HIGH) 2024 sqh->qh.qh_endphub |= htole32( 2025 EHCI_QH_SET_PORT(hshubport) | 2026 EHCI_QH_SET_HUBA(hshubaddr) | 2027 (xfertype == UE_INTERRUPT ? 2028 EHCI_QH_SET_CMASK(0x08) : 0) 2029 ); 2030 sqh->qh.qh_curqtd = EHCI_NULL; 2031 /* Fill the overlay qTD */ 2032 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2033 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2034 sqh->qh.qh_qtd.qtd_status = htole32(0); 2035 2036 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2037 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2038 epipe->sqh = sqh; 2039 } else { 2040 sqh = NULL; 2041 } /*xfertype == UE_ISOC*/ 2042 2043 switch (xfertype) { 2044 case UE_CONTROL: 2045 /* we can use 64bit DMA for the reqdma buffer */ 2046 err = usb_allocmem(sc->sc_bus.ub_dmatag, 2047 sizeof(usb_device_request_t), 0, USBMALLOC_COHERENT, 2048 &epipe->ctrl.reqdma); 2049 #ifdef EHCI_DEBUG 2050 if (err) 2051 printf("ehci_open: usb_allocmem()=%d\n", err); 2052 #endif 2053 if (err) 2054 goto bad; 2055 pipe->up_methods = &ehci_device_ctrl_methods; 2056 mutex_enter(&sc->sc_lock); 2057 ehci_add_qh(sc, sqh, sc->sc_async_head); 2058 mutex_exit(&sc->sc_lock); 2059 break; 2060 case UE_BULK: 2061 pipe->up_methods = &ehci_device_bulk_methods; 2062 mutex_enter(&sc->sc_lock); 2063 ehci_add_qh(sc, sqh, sc->sc_async_head); 2064 mutex_exit(&sc->sc_lock); 2065 break; 2066 case UE_INTERRUPT: 2067 pipe->up_methods = &ehci_device_intr_methods; 2068 ival = pipe->up_interval; 2069 if (ival == USBD_DEFAULT_INTERVAL) { 2070 if (speed == EHCI_QH_SPEED_HIGH) { 2071 if (ed->bInterval > 16) { 2072 /* 2073 * illegal with high-speed, but there 2074 * were documentation bugs in the spec, 2075 * so be generous 2076 */ 2077 ival = 256; 2078 } else 2079 ival = (1 << (ed->bInterval - 1)) / 8; 2080 } else 2081 ival = ed->bInterval; 2082 } 2083 err = ehci_device_setintr(sc, sqh, ival); 2084 if (err) 2085 goto bad; 2086 break; 2087 case UE_ISOCHRONOUS: 2088 pipe->up_serialise = false; 2089 if (speed == EHCI_QH_SPEED_HIGH) 2090 pipe->up_methods = &ehci_device_isoc_methods; 2091 else 2092 pipe->up_methods = &ehci_device_fs_isoc_methods; 2093 if (ed->bInterval == 0 || ed->bInterval > 16) { 2094 printf("ehci: opening pipe with invalid bInterval\n"); 2095 err = USBD_INVAL; 2096 goto bad; 2097 } 2098 if (UGETW(ed->wMaxPacketSize) == 0) { 2099 printf("ehci: zero length endpoint open request\n"); 2100 err = USBD_INVAL; 2101 goto bad; 2102 } 2103 epipe->isoc.next_frame = 0; 2104 epipe->isoc.cur_xfers = 0; 2105 break; 2106 default: 2107 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2108 err = USBD_INVAL; 2109 goto bad; 2110 } 2111 return USBD_NORMAL_COMPLETION; 2112 2113 bad: 2114 if (sqh != NULL) { 2115 mutex_enter(&sc->sc_lock); 2116 ehci_free_sqh(sc, sqh); 2117 mutex_exit(&sc->sc_lock); 2118 } 2119 return err; 2120 } 2121 2122 /* 2123 * Add an ED to the schedule. Called with USB lock held. 2124 */ 2125 Static void 2126 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2127 { 2128 2129 KASSERT(mutex_owned(&sc->sc_lock)); 2130 2131 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2132 2133 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2134 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2135 2136 sqh->next = head->next; 2137 sqh->qh.qh_link = head->qh.qh_link; 2138 2139 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2140 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2141 2142 head->next = sqh; 2143 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2144 2145 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2146 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2147 2148 #ifdef EHCI_DEBUG 2149 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2150 ehci_dump_sqh(sqh); 2151 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2152 #endif 2153 } 2154 2155 /* 2156 * Remove an ED from the schedule. Called with USB lock held. 2157 */ 2158 Static void 2159 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2160 { 2161 ehci_soft_qh_t *p; 2162 2163 KASSERT(mutex_owned(&sc->sc_lock)); 2164 2165 /* XXX */ 2166 for (p = head; p != NULL && p->next != sqh; p = p->next) 2167 ; 2168 if (p == NULL) 2169 panic("ehci_rem_qh: ED not found"); 2170 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2171 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2172 p->next = sqh->next; 2173 p->qh.qh_link = sqh->qh.qh_link; 2174 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2175 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2176 2177 ehci_sync_hc(sc); 2178 } 2179 2180 Static void 2181 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2182 { 2183 int i; 2184 uint32_t status; 2185 2186 /* Save toggle bit and ping status. */ 2187 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2188 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2189 status = sqh->qh.qh_qtd.qtd_status & 2190 htole32(EHCI_QTD_TOGGLE_MASK | 2191 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2192 /* Set HALTED to make hw leave it alone. */ 2193 sqh->qh.qh_qtd.qtd_status = 2194 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2195 usb_syncmem(&sqh->dma, 2196 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2197 sizeof(sqh->qh.qh_qtd.qtd_status), 2198 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2199 sqh->qh.qh_curqtd = 0; 2200 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2201 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2202 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2203 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2204 sqh->sqtd = sqtd; 2205 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2206 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2207 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2208 sqh->qh.qh_qtd.qtd_status = status; 2209 usb_syncmem(&sqh->dma, 2210 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2211 sizeof(sqh->qh.qh_qtd.qtd_status), 2212 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2213 } 2214 2215 /* 2216 * Ensure that the HC has released all references to the QH. We do this 2217 * by asking for a Async Advance Doorbell interrupt and then we wait for 2218 * the interrupt. 2219 * To make this easier we first obtain exclusive use of the doorbell. 2220 */ 2221 Static void 2222 ehci_sync_hc(ehci_softc_t *sc) 2223 { 2224 int error __diagused; 2225 2226 KASSERT(mutex_owned(&sc->sc_lock)); 2227 2228 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2229 2230 if (sc->sc_dying) { 2231 DPRINTF("dying", 0, 0, 0, 0); 2232 return; 2233 } 2234 2235 /* ask for doorbell */ 2236 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2237 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2238 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2239 2240 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2241 2242 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2243 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2244 #ifdef DIAGNOSTIC 2245 if (error == EWOULDBLOCK) { 2246 printf("ehci_sync_hc: timed out\n"); 2247 } else if (error) { 2248 printf("ehci_sync_hc: cv_timedwait: error %d\n", error); 2249 } 2250 #endif 2251 } 2252 2253 Static void 2254 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2255 { 2256 2257 KASSERT(mutex_owned(&sc->sc_lock)); 2258 2259 for (; itd != NULL; itd = itd->xfer_next) { 2260 struct ehci_soft_itd *prev = itd->frame_list.prev; 2261 2262 /* Unlink itd from hardware chain, or frame array */ 2263 if (prev == NULL) { /* We're at the table head */ 2264 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2265 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2266 usb_syncmem(&sc->sc_fldma, 2267 sizeof(ehci_link_t) * itd->slot, 2268 sizeof(ehci_link_t), 2269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2270 2271 if (itd->frame_list.next != NULL) 2272 itd->frame_list.next->frame_list.prev = NULL; 2273 } else { 2274 /* XXX this part is untested... */ 2275 prev->itd.itd_next = itd->itd.itd_next; 2276 usb_syncmem(&itd->dma, 2277 itd->offs + offsetof(ehci_itd_t, itd_next), 2278 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2279 2280 prev->frame_list.next = itd->frame_list.next; 2281 if (itd->frame_list.next != NULL) 2282 itd->frame_list.next->frame_list.prev = prev; 2283 } 2284 } 2285 } 2286 2287 Static void 2288 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2289 { 2290 struct ehci_soft_itd *next; 2291 2292 mutex_enter(&sc->sc_lock); 2293 next = NULL; 2294 for (; itd != NULL; itd = next) { 2295 next = itd->xfer_next; 2296 ehci_free_itd_locked(sc, itd); 2297 } 2298 mutex_exit(&sc->sc_lock); 2299 } 2300 2301 Static void 2302 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2303 { 2304 2305 KASSERT(mutex_owned(&sc->sc_lock)); 2306 2307 for (; sitd != NULL; sitd = sitd->xfer_next) { 2308 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2309 2310 /* Unlink sitd from hardware chain, or frame array */ 2311 if (prev == NULL) { /* We're at the table head */ 2312 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2313 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2314 usb_syncmem(&sc->sc_fldma, 2315 sizeof(ehci_link_t) * sitd->slot, 2316 sizeof(ehci_link_t), 2317 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2318 2319 if (sitd->frame_list.next != NULL) 2320 sitd->frame_list.next->frame_list.prev = NULL; 2321 } else { 2322 /* XXX this part is untested... */ 2323 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2324 usb_syncmem(&sitd->dma, 2325 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2326 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2327 2328 prev->frame_list.next = sitd->frame_list.next; 2329 if (sitd->frame_list.next != NULL) 2330 sitd->frame_list.next->frame_list.prev = prev; 2331 } 2332 } 2333 } 2334 2335 Static void 2336 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2337 { 2338 2339 mutex_enter(&sc->sc_lock); 2340 struct ehci_soft_sitd *next = NULL; 2341 for (; sitd != NULL; sitd = next) { 2342 next = sitd->xfer_next; 2343 ehci_free_sitd_locked(sc, sitd); 2344 } 2345 mutex_exit(&sc->sc_lock); 2346 } 2347 2348 /***********/ 2349 2350 Static int 2351 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2352 void *buf, int buflen) 2353 { 2354 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2355 usb_hub_descriptor_t hubd; 2356 usb_port_status_t ps; 2357 uint16_t len, value, index; 2358 int l, totlen = 0; 2359 int port, i; 2360 uint32_t v; 2361 2362 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2363 2364 if (sc->sc_dying) 2365 return -1; 2366 2367 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2368 0, 0); 2369 2370 len = UGETW(req->wLength); 2371 value = UGETW(req->wValue); 2372 index = UGETW(req->wIndex); 2373 2374 #define C(x,y) ((x) | ((y) << 8)) 2375 switch (C(req->bRequest, req->bmRequestType)) { 2376 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2377 if (len == 0) 2378 break; 2379 switch (value) { 2380 #define sd ((usb_string_descriptor_t *)buf) 2381 case C(2, UDESC_STRING): 2382 /* Product */ 2383 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2384 break; 2385 #undef sd 2386 default: 2387 /* default from usbroothub */ 2388 return buflen; 2389 } 2390 break; 2391 2392 /* Hub requests */ 2393 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2394 break; 2395 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2396 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2397 value, 0, 0); 2398 if (index < 1 || index > sc->sc_noport) { 2399 return -1; 2400 } 2401 port = EHCI_PORTSC(index); 2402 v = EOREAD4(sc, port); 2403 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2404 v &= ~EHCI_PS_CLEAR; 2405 switch (value) { 2406 case UHF_PORT_ENABLE: 2407 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2408 break; 2409 case UHF_PORT_SUSPEND: 2410 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2411 break; 2412 v &= ~EHCI_PS_SUSP; 2413 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2414 /* see USB2 spec ch. 7.1.7.7 */ 2415 usb_delay_ms(&sc->sc_bus, 20); 2416 EOWRITE4(sc, port, v); 2417 usb_delay_ms(&sc->sc_bus, 2); 2418 #ifdef DEBUG 2419 v = EOREAD4(sc, port); 2420 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2421 printf("ehci: resume failed: %x\n", v); 2422 #endif 2423 break; 2424 case UHF_PORT_POWER: 2425 if (sc->sc_hasppc) 2426 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2427 break; 2428 case UHF_PORT_TEST: 2429 DPRINTF("clear port test %jd", index, 0, 0, 0); 2430 break; 2431 case UHF_PORT_INDICATOR: 2432 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2433 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2434 break; 2435 case UHF_C_PORT_CONNECTION: 2436 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2437 break; 2438 case UHF_C_PORT_ENABLE: 2439 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2440 break; 2441 case UHF_C_PORT_SUSPEND: 2442 /* how? */ 2443 break; 2444 case UHF_C_PORT_OVER_CURRENT: 2445 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2446 break; 2447 case UHF_C_PORT_RESET: 2448 sc->sc_isreset[index] = 0; 2449 break; 2450 default: 2451 return -1; 2452 } 2453 #if 0 2454 switch(value) { 2455 case UHF_C_PORT_CONNECTION: 2456 case UHF_C_PORT_ENABLE: 2457 case UHF_C_PORT_SUSPEND: 2458 case UHF_C_PORT_OVER_CURRENT: 2459 case UHF_C_PORT_RESET: 2460 default: 2461 break; 2462 } 2463 #endif 2464 break; 2465 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2466 if (len == 0) 2467 break; 2468 if ((value & 0xff) != 0) { 2469 return -1; 2470 } 2471 totlen = uimin(buflen, sizeof(hubd)); 2472 memcpy(&hubd, buf, totlen); 2473 hubd.bNbrPorts = sc->sc_noport; 2474 v = EREAD4(sc, EHCI_HCSPARAMS); 2475 USETW(hubd.wHubCharacteristics, 2476 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2477 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2478 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2479 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2480 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2481 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2482 totlen = uimin(totlen, hubd.bDescLength); 2483 memcpy(buf, &hubd, totlen); 2484 break; 2485 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2486 if (len != 4) { 2487 return -1; 2488 } 2489 memset(buf, 0, len); /* ? XXX */ 2490 totlen = len; 2491 break; 2492 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2493 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2494 if (index < 1 || index > sc->sc_noport) { 2495 return -1; 2496 } 2497 if (len != 4) { 2498 return -1; 2499 } 2500 v = EOREAD4(sc, EHCI_PORTSC(index)); 2501 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2502 2503 i = UPS_HIGH_SPEED; 2504 if (sc->sc_flags & EHCIF_ETTF) { 2505 /* 2506 * If we are doing embedded transaction translation, 2507 * then directly attached LS/FS devices are reset by 2508 * the EHCI controller itself. PSPD is encoded 2509 * the same way as in USBSTATUS. 2510 */ 2511 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2512 } 2513 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2514 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2515 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2516 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2517 if (v & EHCI_PS_PR) i |= UPS_RESET; 2518 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2519 if (sc->sc_vendor_port_status) 2520 i = sc->sc_vendor_port_status(sc, v, i); 2521 USETW(ps.wPortStatus, i); 2522 i = 0; 2523 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2524 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2525 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2526 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2527 USETW(ps.wPortChange, i); 2528 totlen = uimin(len, sizeof(ps)); 2529 memcpy(buf, &ps, totlen); 2530 break; 2531 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2532 return -1; 2533 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2534 break; 2535 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2536 if (index < 1 || index > sc->sc_noport) { 2537 return -1; 2538 } 2539 port = EHCI_PORTSC(index); 2540 v = EOREAD4(sc, port); 2541 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2542 v &= ~EHCI_PS_CLEAR; 2543 switch(value) { 2544 case UHF_PORT_ENABLE: 2545 EOWRITE4(sc, port, v | EHCI_PS_PE); 2546 break; 2547 case UHF_PORT_SUSPEND: 2548 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2549 break; 2550 case UHF_PORT_RESET: 2551 DPRINTF("reset port %jd", index, 0, 0, 0); 2552 if (EHCI_PS_IS_LOWSPEED(v) 2553 && sc->sc_ncomp > 0 2554 && !(sc->sc_flags & EHCIF_ETTF)) { 2555 /* 2556 * Low speed device on non-ETTF controller or 2557 * unaccompanied controller, give up ownership. 2558 */ 2559 ehci_disown(sc, index, 1); 2560 break; 2561 } 2562 /* Start reset sequence. */ 2563 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2564 EOWRITE4(sc, port, v | EHCI_PS_PR); 2565 /* Wait for reset to complete. */ 2566 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2567 if (sc->sc_dying) { 2568 return -1; 2569 } 2570 /* 2571 * An embedded transaction translator will automatically 2572 * terminate the reset sequence so there's no need to 2573 * it. 2574 */ 2575 v = EOREAD4(sc, port); 2576 if (v & EHCI_PS_PR) { 2577 /* Terminate reset sequence. */ 2578 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2579 /* Wait for HC to complete reset. */ 2580 usb_delay_ms(&sc->sc_bus, 2581 EHCI_PORT_RESET_COMPLETE); 2582 if (sc->sc_dying) { 2583 return -1; 2584 } 2585 } 2586 2587 v = EOREAD4(sc, port); 2588 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2589 if (v & EHCI_PS_PR) { 2590 printf("%s: port reset timeout\n", 2591 device_xname(sc->sc_dev)); 2592 return USBD_TIMEOUT; 2593 } 2594 if (!(v & EHCI_PS_PE)) { 2595 /* Not a high speed device, give up ownership.*/ 2596 ehci_disown(sc, index, 0); 2597 break; 2598 } 2599 sc->sc_isreset[index] = 1; 2600 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2601 v, 0, 0); 2602 break; 2603 case UHF_PORT_POWER: 2604 DPRINTF("set port power %jd (has PPC = %jd)", index, 2605 sc->sc_hasppc, 0, 0); 2606 if (sc->sc_hasppc) 2607 EOWRITE4(sc, port, v | EHCI_PS_PP); 2608 break; 2609 case UHF_PORT_TEST: 2610 DPRINTF("set port test %jd", index, 0, 0, 0); 2611 break; 2612 case UHF_PORT_INDICATOR: 2613 DPRINTF("set port ind %jd", index, 0, 0, 0); 2614 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2615 break; 2616 default: 2617 return -1; 2618 } 2619 break; 2620 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2621 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2622 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2623 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2624 break; 2625 default: 2626 /* default from usbroothub */ 2627 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2628 2629 return buflen; 2630 } 2631 2632 DPRINTF("returning %jd", totlen, 0, 0, 0); 2633 2634 return totlen; 2635 } 2636 2637 /* 2638 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2639 * 2640 * This pile of garbage below works around the following problem without 2641 * holding boots with no hand-over devices present, while penalising 2642 * boots where the first ehci probe hands off devices with a 5 second 2643 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2644 * for RB_SINGLE, but the same basic issue exists. 2645 * 2646 * The way ehci hand-off works, the companion controller does not get the 2647 * device until after its initial bus explore, so the reference dropped 2648 * after the first explore is not enough. 5 seconds should be enough, 2649 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2650 * 2651 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2652 * if the callback is scheduled. CO_DONE is set when the callout has 2653 * called config_pending_decr(). 2654 * 2655 * There's a mutex, a cv and a callout here, and we delay detach if the 2656 * callout has been set. 2657 */ 2658 #ifndef EHCI_DISOWN_DELAY_SECONDS 2659 #define EHCI_DISOWN_DELAY_SECONDS 5 2660 #endif 2661 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2662 2663 static void 2664 ehci_disown_callback(void *arg) 2665 { 2666 ehci_softc_t *sc = arg; 2667 2668 config_pending_decr(sc->sc_dev); 2669 2670 mutex_enter(&sc->sc_complock); 2671 KASSERT(sc->sc_comp_state == CO_SCHED); 2672 sc->sc_comp_state = CO_DONE; 2673 cv_signal(&sc->sc_compcv); 2674 mutex_exit(&sc->sc_complock); 2675 } 2676 2677 static void 2678 ehci_disown_sched_callback(ehci_softc_t *sc) 2679 { 2680 extern bool root_is_mounted; 2681 2682 mutex_enter(&sc->sc_complock); 2683 2684 if (root_is_mounted || 2685 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2686 sc->sc_comp_state != CO_EARLY) { 2687 mutex_exit(&sc->sc_complock); 2688 return; 2689 } 2690 2691 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2692 ehci_disown_callback, &sc->sc_dev); 2693 sc->sc_comp_state = CO_SCHED; 2694 2695 mutex_exit(&sc->sc_complock); 2696 2697 config_pending_incr(sc->sc_dev); 2698 aprint_normal("delaying %s by %u seconds due to USB owner change.\n", 2699 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user", 2700 ehci_disown_delay_seconds); 2701 } 2702 2703 Static void 2704 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2705 { 2706 int port; 2707 uint32_t v; 2708 2709 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2710 2711 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2712 if (sc->sc_npcomp != 0) { 2713 int i = (index-1) / sc->sc_npcomp; 2714 if (i < sc->sc_ncomp) { 2715 ehci_disown_sched_callback(sc); 2716 #ifdef DIAGNOSTIC 2717 printf("%s: handing over %s speed device on " 2718 "port %d to %s\n", 2719 device_xname(sc->sc_dev), 2720 lowspeed ? "low" : "full", 2721 index, sc->sc_comps[i] ? 2722 device_xname(sc->sc_comps[i]) : 2723 "companion controller"); 2724 } else { 2725 printf("%s: strange port\n", 2726 device_xname(sc->sc_dev)); 2727 #endif 2728 } 2729 } else { 2730 #ifdef DIAGNOSTIC 2731 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2732 #endif 2733 } 2734 port = EHCI_PORTSC(index); 2735 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2736 EOWRITE4(sc, port, v | EHCI_PS_PO); 2737 } 2738 2739 Static usbd_status 2740 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2741 { 2742 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2743 usbd_status err; 2744 2745 /* Insert last in queue. */ 2746 mutex_enter(&sc->sc_lock); 2747 err = usb_insert_transfer(xfer); 2748 mutex_exit(&sc->sc_lock); 2749 if (err) 2750 return err; 2751 2752 /* Pipe isn't running, start first */ 2753 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2754 } 2755 2756 Static usbd_status 2757 ehci_root_intr_start(struct usbd_xfer *xfer) 2758 { 2759 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2760 const bool polling = sc->sc_bus.ub_usepolling; 2761 2762 if (sc->sc_dying) 2763 return USBD_IOERROR; 2764 2765 if (!polling) 2766 mutex_enter(&sc->sc_lock); 2767 KASSERT(sc->sc_intrxfer == NULL); 2768 sc->sc_intrxfer = xfer; 2769 xfer->ux_status = USBD_IN_PROGRESS; 2770 if (!polling) 2771 mutex_exit(&sc->sc_lock); 2772 2773 return USBD_IN_PROGRESS; 2774 } 2775 2776 /* Abort a root interrupt request. */ 2777 Static void 2778 ehci_root_intr_abort(struct usbd_xfer *xfer) 2779 { 2780 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2781 2782 KASSERT(mutex_owned(&sc->sc_lock)); 2783 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2784 2785 /* If xfer has already completed, nothing to do here. */ 2786 if (sc->sc_intrxfer == NULL) 2787 return; 2788 2789 /* 2790 * Otherwise, sc->sc_intrxfer had better be this transfer. 2791 * Cancel it. 2792 */ 2793 KASSERT(sc->sc_intrxfer == xfer); 2794 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2795 xfer->ux_status = USBD_CANCELLED; 2796 usb_transfer_complete(xfer); 2797 } 2798 2799 /* Close the root pipe. */ 2800 Static void 2801 ehci_root_intr_close(struct usbd_pipe *pipe) 2802 { 2803 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2804 2805 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2806 2807 KASSERT(mutex_owned(&sc->sc_lock)); 2808 2809 /* 2810 * Caller must guarantee the xfer has completed first, by 2811 * closing the pipe only after normal completion or an abort. 2812 */ 2813 KASSERT(sc->sc_intrxfer == NULL); 2814 } 2815 2816 Static void 2817 ehci_root_intr_done(struct usbd_xfer *xfer) 2818 { 2819 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2820 2821 KASSERT(mutex_owned(&sc->sc_lock)); 2822 2823 /* Claim the xfer so it doesn't get completed again. */ 2824 KASSERT(sc->sc_intrxfer == xfer); 2825 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2826 sc->sc_intrxfer = NULL; 2827 } 2828 2829 /************************/ 2830 2831 Static ehci_soft_qh_t * 2832 ehci_alloc_sqh(ehci_softc_t *sc) 2833 { 2834 ehci_soft_qh_t *sqh; 2835 2836 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2837 2838 mutex_enter(&sc->sc_lock); 2839 if (sc->sc_freeqhs == NULL) { 2840 DPRINTF("allocating chunk", 0, 0, 0, 0); 2841 mutex_exit(&sc->sc_lock); 2842 2843 usb_dma_t dma; 2844 int err = usb_allocmem(sc->sc_dmatag, 2845 EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2846 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2847 2848 if (err) { 2849 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2850 return NULL; 2851 } 2852 2853 mutex_enter(&sc->sc_lock); 2854 for (size_t i = 0; i < EHCI_SQH_CHUNK; i++) { 2855 const int offs = i * EHCI_SQH_SIZE; 2856 const bus_addr_t baddr = DMAADDR(&dma, offs); 2857 2858 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2859 2860 sqh = KERNADDR(&dma, offs); 2861 sqh->physaddr = BUS_ADDR_LO32(baddr); 2862 sqh->dma = dma; 2863 sqh->offs = offs; 2864 2865 sqh->next = sc->sc_freeqhs; 2866 sc->sc_freeqhs = sqh; 2867 } 2868 } 2869 sqh = sc->sc_freeqhs; 2870 sc->sc_freeqhs = sqh->next; 2871 mutex_exit(&sc->sc_lock); 2872 2873 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2874 sqh->next = NULL; 2875 return sqh; 2876 } 2877 2878 Static void 2879 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2880 { 2881 KASSERT(mutex_owned(&sc->sc_lock)); 2882 2883 sqh->next = sc->sc_freeqhs; 2884 sc->sc_freeqhs = sqh; 2885 } 2886 2887 Static ehci_soft_qtd_t * 2888 ehci_alloc_sqtd(ehci_softc_t *sc) 2889 { 2890 ehci_soft_qtd_t *sqtd = NULL; 2891 2892 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2893 2894 mutex_enter(&sc->sc_lock); 2895 if (sc->sc_freeqtds == NULL) { 2896 DPRINTF("allocating chunk", 0, 0, 0, 0); 2897 mutex_exit(&sc->sc_lock); 2898 2899 usb_dma_t dma; 2900 int err = usb_allocmem(sc->sc_dmatag, 2901 EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK, 2902 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2903 2904 if (err) { 2905 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2906 return NULL; 2907 } 2908 2909 mutex_enter(&sc->sc_lock); 2910 for (size_t i = 0; i < EHCI_SQTD_CHUNK; i++) { 2911 const int offs = i * EHCI_SQTD_SIZE; 2912 const bus_addr_t baddr = DMAADDR(&dma, offs); 2913 2914 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2915 2916 sqtd = KERNADDR(&dma, offs); 2917 sqtd->physaddr = BUS_ADDR_LO32(baddr); 2918 sqtd->dma = dma; 2919 sqtd->offs = offs; 2920 2921 sqtd->nextqtd = sc->sc_freeqtds; 2922 sc->sc_freeqtds = sqtd; 2923 } 2924 } 2925 2926 sqtd = sc->sc_freeqtds; 2927 sc->sc_freeqtds = sqtd->nextqtd; 2928 mutex_exit(&sc->sc_lock); 2929 2930 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2931 sqtd->nextqtd = NULL; 2932 sqtd->xfer = NULL; 2933 2934 return sqtd; 2935 } 2936 2937 Static void 2938 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2939 { 2940 2941 mutex_enter(&sc->sc_lock); 2942 sqtd->nextqtd = sc->sc_freeqtds; 2943 sc->sc_freeqtds = sqtd; 2944 mutex_exit(&sc->sc_lock); 2945 } 2946 2947 Static int 2948 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2949 int alen, int rd, ehci_soft_qtd_t **sp) 2950 { 2951 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2952 uint16_t flags = xfer->ux_flags; 2953 2954 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2955 2956 ASSERT_SLEEPABLE(); 2957 KASSERT(sp); 2958 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2959 2960 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2961 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 2962 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2963 KM_SLEEP); 2964 exfer->ex_nsqtd = nsqtd; 2965 2966 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 2967 alen, nsqtd, flags); 2968 2969 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2970 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2971 if (cur == NULL) 2972 goto nomem; 2973 exfer->ex_sqtds[j++] = cur; 2974 2975 cur->xfer = xfer; 2976 cur->len = 0; 2977 2978 } 2979 2980 *sp = exfer->ex_sqtds[0]; 2981 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 2982 2983 return 0; 2984 2985 nomem: 2986 ehci_free_sqtds(sc, exfer); 2987 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2988 DPRINTF("no memory", 0, 0, 0, 0); 2989 return ENOMEM; 2990 } 2991 2992 Static void 2993 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2994 { 2995 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2996 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 2997 2998 mutex_enter(&sc->sc_lock); 2999 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 3000 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 3001 3002 if (sqtd == NULL) 3003 break; 3004 3005 sqtd->nextqtd = sc->sc_freeqtds; 3006 sc->sc_freeqtds = sqtd; 3007 } 3008 mutex_exit(&sc->sc_lock); 3009 } 3010 3011 Static void 3012 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 3013 { 3014 if (prev) { 3015 prev->nextqtd = sqtd; 3016 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3017 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3018 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 3019 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3020 } 3021 } 3022 3023 Static void 3024 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3025 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3026 { 3027 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3028 usb_dma_t *dma = &xfer->ux_dmabuf; 3029 uint16_t flags = xfer->ux_flags; 3030 ehci_soft_qtd_t *sqtd, *prev; 3031 int tog = *toggle; 3032 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3033 int len = length; 3034 3035 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3036 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 3037 len, isread, tog); 3038 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 3039 0, 0, 0); 3040 3041 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 3042 3043 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3044 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3045 EHCI_QTD_SET_CERR(3) 3046 ; 3047 3048 sqtd = prev = NULL; 3049 size_t curoffs = 0; 3050 size_t j = 0; 3051 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3052 sqtd = exfer->ex_sqtds[j++]; 3053 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3054 (uintptr_t)prev, 0); 3055 3056 /* 3057 * The EHCI hardware can handle at most 5 pages and they do 3058 * not have to be contiguous 3059 */ 3060 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3061 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3062 size_t curlen = len; 3063 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3064 /* must use multiple TDs, fill as much as possible. */ 3065 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3066 3067 /* the length must be a multiple of the max size */ 3068 curlen -= curlen % mps; 3069 } 3070 KASSERT(curlen != 0); 3071 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3072 curoffs, 0); 3073 3074 /* Fill the qTD */ 3075 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3076 sqtd->qtd.qtd_status = htole32( 3077 qtdstatus | 3078 EHCI_QTD_SET_BYTES(curlen) | 3079 EHCI_QTD_SET_TOGGLE(tog)); 3080 3081 /* Find number of pages we'll be using, insert dma addresses */ 3082 size_t pages = EHCI_NPAGES(curlen); 3083 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3084 size_t pageoffs = EHCI_PAGE(curoffs); 3085 for (size_t i = 0; i < pages; i++) { 3086 paddr_t a = EHCI_PAGE(DMAADDR(dma, 3087 pageoffs + i * EHCI_PAGE_SIZE)); 3088 sqtd->qtd.qtd_buffer[i] = htole32(BUS_ADDR_LO32(a)); 3089 sqtd->qtd.qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a)); 3090 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3091 i, pages, 3092 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3093 le32toh(sqtd->qtd.qtd_buffer[i])); 3094 } 3095 /* First buffer pointer requires a page offset to start at */ 3096 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3097 3098 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3099 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3100 3101 sqtd->len = curlen; 3102 3103 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3104 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3105 3106 ehci_append_sqtd(sqtd, prev); 3107 3108 if (howmany(curlen, mps) & 1) { 3109 tog ^= 1; 3110 } 3111 3112 curoffs += curlen; 3113 len -= curlen; 3114 } 3115 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3116 xfer, length, len, mps, exfer->ex_nsqtd, j); 3117 3118 if (!isread && 3119 (flags & USBD_FORCE_SHORT_XFER) && 3120 length % mps == 0) { 3121 /* Force a 0 length transfer at the end. */ 3122 3123 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3124 exfer->ex_nsqtd); 3125 prev = sqtd; 3126 sqtd = exfer->ex_sqtds[j++]; 3127 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3128 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3129 sqtd->qtd.qtd_status = htole32( 3130 qtdstatus | 3131 EHCI_QTD_SET_BYTES(0) | 3132 EHCI_QTD_SET_TOGGLE(tog)); 3133 3134 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3135 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3136 3137 ehci_append_sqtd(sqtd, prev); 3138 tog ^= 1; 3139 } 3140 3141 *lsqtd = sqtd; 3142 *toggle = tog; 3143 } 3144 3145 Static ehci_soft_itd_t * 3146 ehci_alloc_itd(ehci_softc_t *sc) 3147 { 3148 struct ehci_soft_itd *itd, *freeitd; 3149 3150 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3151 3152 mutex_enter(&sc->sc_lock); 3153 3154 freeitd = LIST_FIRST(&sc->sc_freeitds); 3155 if (freeitd == NULL) { 3156 DPRINTF("allocating chunk", 0, 0, 0, 0); 3157 mutex_exit(&sc->sc_lock); 3158 3159 usb_dma_t dma; 3160 int err = usb_allocmem(sc->sc_dmatag, 3161 EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3162 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3163 3164 if (err) { 3165 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3166 return NULL; 3167 } 3168 3169 mutex_enter(&sc->sc_lock); 3170 for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) { 3171 const int offs = i * EHCI_ITD_SIZE; 3172 const bus_addr_t baddr = DMAADDR(&dma, offs); 3173 3174 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3175 3176 itd = KERNADDR(&dma, offs); 3177 itd->physaddr = BUS_ADDR_LO32(baddr); 3178 itd->dma = dma; 3179 itd->offs = offs; 3180 3181 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3182 } 3183 freeitd = LIST_FIRST(&sc->sc_freeitds); 3184 } 3185 3186 itd = freeitd; 3187 LIST_REMOVE(itd, free_list); 3188 mutex_exit(&sc->sc_lock); 3189 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3190 3191 itd->frame_list.next = NULL; 3192 itd->frame_list.prev = NULL; 3193 itd->xfer_next = NULL; 3194 itd->slot = 0; 3195 3196 return itd; 3197 } 3198 3199 Static ehci_soft_sitd_t * 3200 ehci_alloc_sitd(ehci_softc_t *sc) 3201 { 3202 struct ehci_soft_sitd *sitd, *freesitd; 3203 3204 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3205 3206 mutex_enter(&sc->sc_lock); 3207 freesitd = LIST_FIRST(&sc->sc_freesitds); 3208 if (freesitd == NULL) { 3209 DPRINTF("allocating chunk", 0, 0, 0, 0); 3210 mutex_exit(&sc->sc_lock); 3211 3212 usb_dma_t dma; 3213 int err = usb_allocmem(sc->sc_bus.ub_dmatag, 3214 EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3215 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3216 3217 if (err) { 3218 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3219 return NULL; 3220 } 3221 3222 mutex_enter(&sc->sc_lock); 3223 for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) { 3224 const int offs = i * EHCI_SITD_SIZE; 3225 const bus_addr_t baddr = DMAADDR(&dma, offs); 3226 3227 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3228 3229 sitd = KERNADDR(&dma, offs); 3230 sitd->physaddr = BUS_ADDR_LO32(baddr); 3231 sitd->dma = dma; 3232 sitd->offs = offs; 3233 3234 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3235 } 3236 freesitd = LIST_FIRST(&sc->sc_freesitds); 3237 } 3238 3239 sitd = freesitd; 3240 LIST_REMOVE(sitd, free_list); 3241 mutex_exit(&sc->sc_lock); 3242 3243 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3244 3245 sitd->frame_list.next = NULL; 3246 sitd->frame_list.prev = NULL; 3247 sitd->xfer_next = NULL; 3248 sitd->slot = 0; 3249 3250 return sitd; 3251 } 3252 3253 /****************/ 3254 3255 /* 3256 * Close a reqular pipe. 3257 * Assumes that there are no pending transactions. 3258 */ 3259 Static void 3260 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3261 { 3262 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3263 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3264 ehci_soft_qh_t *sqh = epipe->sqh; 3265 3266 KASSERT(mutex_owned(&sc->sc_lock)); 3267 3268 ehci_rem_qh(sc, sqh, head); 3269 ehci_free_sqh(sc, epipe->sqh); 3270 } 3271 3272 /* 3273 * Arrange for the hardware to tells us that it is not still 3274 * processing the TDs by setting the QH halted bit and wait for the ehci 3275 * door bell 3276 */ 3277 Static void 3278 ehci_abortx(struct usbd_xfer *xfer) 3279 { 3280 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3281 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3282 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3283 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3284 ehci_soft_qh_t *sqh = epipe->sqh; 3285 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3286 ehci_physaddr_t cur; 3287 uint32_t qhstatus; 3288 int hit; 3289 3290 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3291 3292 KASSERT(mutex_owned(&sc->sc_lock)); 3293 ASSERT_SLEEPABLE(); 3294 3295 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3296 xfer->ux_status == USBD_TIMEOUT), 3297 "bad abort status: %d", xfer->ux_status); 3298 3299 /* 3300 * If we're dying, skip the hardware action and just notify the 3301 * software that we're done. 3302 */ 3303 if (sc->sc_dying) { 3304 goto dying; 3305 } 3306 3307 /* 3308 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3309 */ 3310 ehci_del_intr_list(sc, exfer); 3311 3312 usb_syncmem(&sqh->dma, 3313 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3314 sizeof(sqh->qh.qh_qtd.qtd_status), 3315 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3316 qhstatus = sqh->qh.qh_qtd.qtd_status; 3317 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3318 usb_syncmem(&sqh->dma, 3319 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3320 sizeof(sqh->qh.qh_qtd.qtd_status), 3321 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3322 3323 if (exfer->ex_type == EX_CTRL) { 3324 fsqtd = exfer->ex_setup; 3325 lsqtd = exfer->ex_status; 3326 } else { 3327 fsqtd = exfer->ex_sqtdstart; 3328 lsqtd = exfer->ex_sqtdend; 3329 } 3330 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3331 usb_syncmem(&sqtd->dma, 3332 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3333 sizeof(sqtd->qtd.qtd_status), 3334 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3335 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3336 usb_syncmem(&sqtd->dma, 3337 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3338 sizeof(sqtd->qtd.qtd_status), 3339 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3340 if (sqtd == lsqtd) 3341 break; 3342 } 3343 3344 /* 3345 * HC Step 2: Wait until we know hardware has finished any possible 3346 * use of the xfer. 3347 */ 3348 ehci_sync_hc(sc); 3349 3350 /* 3351 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3352 * The complication here is that the hardware may have executed 3353 * beyond the xfer we're trying to abort. So as we're scanning 3354 * the TDs of this xfer we check if the hardware points to 3355 * any of them. 3356 */ 3357 3358 usb_syncmem(&sqh->dma, 3359 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3360 sizeof(sqh->qh.qh_curqtd), 3361 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3362 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3363 hit = 0; 3364 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3365 hit |= cur == sqtd->physaddr; 3366 if (sqtd == lsqtd) 3367 break; 3368 } 3369 sqtd = sqtd->nextqtd; 3370 /* Zap curqtd register if hardware pointed inside the xfer. */ 3371 if (hit && sqtd != NULL) { 3372 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3373 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3374 usb_syncmem(&sqh->dma, 3375 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3376 sizeof(sqh->qh.qh_curqtd), 3377 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3378 sqh->qh.qh_qtd.qtd_status = qhstatus; 3379 usb_syncmem(&sqh->dma, 3380 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3381 sizeof(sqh->qh.qh_qtd.qtd_status), 3382 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3383 } else { 3384 DPRINTF("no hit", 0, 0, 0, 0); 3385 usb_syncmem(&sqh->dma, 3386 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3387 sizeof(sqh->qh.qh_curqtd), 3388 BUS_DMASYNC_PREREAD); 3389 } 3390 3391 /* 3392 * Final step: Notify completion to waiting xfers. 3393 */ 3394 dying: 3395 #ifdef DIAGNOSTIC 3396 exfer->ex_isdone = true; 3397 #endif 3398 usb_transfer_complete(xfer); 3399 DPRINTFN(14, "end", 0, 0, 0, 0); 3400 3401 KASSERT(mutex_owned(&sc->sc_lock)); 3402 } 3403 3404 Static void 3405 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3406 { 3407 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3408 ehci_isoc_trans_t trans_status; 3409 struct ehci_xfer *exfer; 3410 ehci_softc_t *sc; 3411 struct ehci_soft_itd *itd; 3412 struct ehci_soft_sitd *sitd; 3413 int i; 3414 3415 KASSERTMSG(status == USBD_CANCELLED, 3416 "invalid status for abort: %d", (int)status); 3417 3418 exfer = EHCI_XFER2EXFER(xfer); 3419 sc = EHCI_XFER2SC(xfer); 3420 3421 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3422 (uintptr_t)xfer->ux_pipe, 0, 0); 3423 3424 KASSERT(mutex_owned(&sc->sc_lock)); 3425 ASSERT_SLEEPABLE(); 3426 3427 /* No timeout or task here. */ 3428 3429 /* 3430 * The xfer cannot have been cancelled already. It is the 3431 * responsibility of the caller of usbd_abort_pipe not to try 3432 * to abort a pipe multiple times, whether concurrently or 3433 * sequentially. 3434 */ 3435 KASSERT(xfer->ux_status != USBD_CANCELLED); 3436 3437 /* If anyone else beat us, we're done. */ 3438 if (xfer->ux_status != USBD_IN_PROGRESS) 3439 return; 3440 3441 /* We beat everyone else. Claim the status. */ 3442 xfer->ux_status = status; 3443 3444 /* 3445 * If we're dying, skip the hardware action and just notify the 3446 * software that we're done. 3447 */ 3448 if (sc->sc_dying) { 3449 goto dying; 3450 } 3451 3452 /* 3453 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3454 */ 3455 ehci_del_intr_list(sc, exfer); 3456 3457 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3458 for (itd = exfer->ex_itdstart; itd != NULL; 3459 itd = itd->xfer_next) { 3460 usb_syncmem(&itd->dma, 3461 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3462 sizeof(itd->itd.itd_ctl), 3463 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3464 3465 for (i = 0; i < 8; i++) { 3466 trans_status = le32toh(itd->itd.itd_ctl[i]); 3467 trans_status &= ~EHCI_ITD_ACTIVE; 3468 itd->itd.itd_ctl[i] = htole32(trans_status); 3469 } 3470 3471 usb_syncmem(&itd->dma, 3472 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3473 sizeof(itd->itd.itd_ctl), 3474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3475 } 3476 } else { 3477 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3478 sitd = sitd->xfer_next) { 3479 usb_syncmem(&sitd->dma, 3480 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3481 sizeof(sitd->sitd.sitd_buffer), 3482 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3483 3484 trans_status = le32toh(sitd->sitd.sitd_trans); 3485 trans_status &= ~EHCI_SITD_ACTIVE; 3486 sitd->sitd.sitd_trans = htole32(trans_status); 3487 3488 usb_syncmem(&sitd->dma, 3489 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3490 sizeof(sitd->sitd.sitd_buffer), 3491 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3492 } 3493 } 3494 3495 dying: 3496 #ifdef DIAGNOSTIC 3497 exfer->ex_isdone = true; 3498 #endif 3499 usb_transfer_complete(xfer); 3500 DPRINTFN(14, "end", 0, 0, 0, 0); 3501 3502 KASSERT(mutex_owned(&sc->sc_lock)); 3503 } 3504 3505 /************************/ 3506 3507 Static int 3508 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3509 { 3510 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3511 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3512 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3513 usb_device_request_t *req = &xfer->ux_request; 3514 ehci_soft_qtd_t *setup, *status, *next; 3515 int isread = req->bmRequestType & UT_READ; 3516 int len = xfer->ux_bufsize; 3517 int err; 3518 3519 exfer->ex_type = EX_CTRL; 3520 exfer->ex_status = NULL; 3521 exfer->ex_data = NULL; 3522 exfer->ex_setup = ehci_alloc_sqtd(sc); 3523 if (exfer->ex_setup == NULL) { 3524 err = ENOMEM; 3525 goto bad1; 3526 } 3527 exfer->ex_status = ehci_alloc_sqtd(sc); 3528 if (exfer->ex_status == NULL) { 3529 err = ENOMEM; 3530 goto bad2; 3531 } 3532 setup = exfer->ex_setup; 3533 status = exfer->ex_status; 3534 exfer->ex_nsqtd = 0; 3535 next = status; 3536 /* Set up data transaction */ 3537 if (len != 0) { 3538 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3539 &exfer->ex_data); 3540 if (err) 3541 goto bad3; 3542 next = exfer->ex_data; 3543 } 3544 3545 /* Clear toggle */ 3546 setup->qtd.qtd_status = htole32( 3547 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3548 EHCI_QTD_SET_TOGGLE(0) | 3549 EHCI_QTD_SET_BYTES(sizeof(*req)) 3550 ); 3551 3552 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3553 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3554 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3555 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3556 setup->nextqtd = next; 3557 setup->xfer = xfer; 3558 setup->len = sizeof(*req); 3559 3560 status->qtd.qtd_status = htole32( 3561 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3562 EHCI_QTD_SET_TOGGLE(1) | 3563 EHCI_QTD_IOC 3564 ); 3565 status->qtd.qtd_buffer[0] = 0; 3566 status->qtd.qtd_buffer_hi[0] = 0; 3567 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3568 status->nextqtd = NULL; 3569 status->xfer = xfer; 3570 status->len = 0; 3571 3572 return 0; 3573 bad3: 3574 ehci_free_sqtd(sc, exfer->ex_status); 3575 bad2: 3576 ehci_free_sqtd(sc, exfer->ex_setup); 3577 bad1: 3578 return err; 3579 } 3580 3581 Static void 3582 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3583 { 3584 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3585 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3586 3587 KASSERT(ex->ex_type == EX_CTRL); 3588 3589 ehci_free_sqtd(sc, ex->ex_setup); 3590 ehci_free_sqtd(sc, ex->ex_status); 3591 ehci_free_sqtds(sc, ex); 3592 if (ex->ex_nsqtd) 3593 kmem_free(ex->ex_sqtds, 3594 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3595 } 3596 3597 Static usbd_status 3598 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3599 { 3600 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3601 usbd_status err; 3602 3603 /* Insert last in queue. */ 3604 mutex_enter(&sc->sc_lock); 3605 err = usb_insert_transfer(xfer); 3606 mutex_exit(&sc->sc_lock); 3607 if (err) 3608 return err; 3609 3610 /* Pipe isn't running, start first */ 3611 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3612 } 3613 3614 Static usbd_status 3615 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3616 { 3617 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3618 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3619 usb_device_request_t *req = &xfer->ux_request; 3620 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3621 ehci_soft_qtd_t *setup, *status, *next; 3622 ehci_soft_qh_t *sqh; 3623 const bool polling = sc->sc_bus.ub_usepolling; 3624 3625 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3626 3627 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3628 3629 if (sc->sc_dying) 3630 return USBD_IOERROR; 3631 3632 const int isread = req->bmRequestType & UT_READ; 3633 const int len = UGETW(req->wLength); 3634 3635 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3636 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3637 UGETW(req->wIndex)); 3638 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3639 len, epipe->pipe.up_dev->ud_addr, 3640 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3641 3642 sqh = epipe->sqh; 3643 3644 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3645 "address QH %" __PRIuBIT " pipe %d\n", 3646 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3647 epipe->pipe.up_dev->ud_addr); 3648 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3649 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3650 "MPS QH %" __PRIuBIT " pipe %d\n", 3651 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3652 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3653 3654 setup = exfer->ex_setup; 3655 status = exfer->ex_status; 3656 3657 DPRINTF("setup %#jx status %#jx data %#jx", 3658 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3659 KASSERTMSG(setup != NULL && status != NULL, 3660 "Failed memory allocation, setup %p status %p", 3661 setup, status); 3662 3663 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3664 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3665 3666 /* Clear toggle */ 3667 setup->qtd.qtd_status &= ~htole32( 3668 EHCI_QTD_STATUS_MASK | 3669 EHCI_QTD_BYTES_MASK | 3670 EHCI_QTD_TOGGLE_MASK | 3671 EHCI_QTD_CERR_MASK 3672 ); 3673 setup->qtd.qtd_status |= htole32( 3674 EHCI_QTD_ACTIVE | 3675 EHCI_QTD_SET_CERR(3) | 3676 EHCI_QTD_SET_TOGGLE(0) | 3677 EHCI_QTD_SET_BYTES(sizeof(*req)) 3678 ); 3679 3680 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3681 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3682 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3683 3684 next = status; 3685 status->qtd.qtd_status &= ~htole32( 3686 EHCI_QTD_STATUS_MASK | 3687 EHCI_QTD_PID_MASK | 3688 EHCI_QTD_BYTES_MASK | 3689 EHCI_QTD_TOGGLE_MASK | 3690 EHCI_QTD_CERR_MASK 3691 ); 3692 status->qtd.qtd_status |= htole32( 3693 EHCI_QTD_ACTIVE | 3694 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3695 EHCI_QTD_SET_CERR(3) | 3696 EHCI_QTD_SET_TOGGLE(1) | 3697 EHCI_QTD_SET_BYTES(0) | 3698 EHCI_QTD_IOC 3699 ); 3700 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3701 3702 KASSERT(exfer->ex_isdone); 3703 #ifdef DIAGNOSTIC 3704 exfer->ex_isdone = false; 3705 #endif 3706 3707 /* Set up data transaction */ 3708 if (len != 0) { 3709 ehci_soft_qtd_t *end; 3710 3711 /* Start toggle at 1. */ 3712 int toggle = 1; 3713 next = exfer->ex_data; 3714 KASSERTMSG(next != NULL, "Failed memory allocation"); 3715 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3716 end->nextqtd = status; 3717 end->qtd.qtd_next = end->qtd.qtd_altnext = 3718 htole32(status->physaddr); 3719 3720 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3721 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3722 3723 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3724 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3725 } 3726 3727 setup->nextqtd = next; 3728 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3729 3730 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3731 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3732 3733 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3734 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3735 3736 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3737 3738 #ifdef EHCI_DEBUG 3739 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3740 ehci_dump_sqh(sqh); 3741 ehci_dump_sqtds(setup); 3742 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3743 #endif 3744 3745 if (!polling) 3746 mutex_enter(&sc->sc_lock); 3747 3748 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3749 ehci_set_qh_qtd(sqh, setup); 3750 usbd_xfer_schedule_timeout(xfer); 3751 ehci_add_intr_list(sc, exfer); 3752 xfer->ux_status = USBD_IN_PROGRESS; 3753 if (!polling) 3754 mutex_exit(&sc->sc_lock); 3755 3756 #if 0 3757 #ifdef EHCI_DEBUG 3758 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3759 // delay(10000); 3760 ehci_dump_regs(sc); 3761 ehci_dump_sqh(sc->sc_async_head); 3762 ehci_dump_sqh(sqh); 3763 ehci_dump_sqtds(setup); 3764 #endif 3765 #endif 3766 3767 return USBD_IN_PROGRESS; 3768 } 3769 3770 Static void 3771 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3772 { 3773 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3774 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3775 usb_device_request_t *req = &xfer->ux_request; 3776 int len = UGETW(req->wLength); 3777 int rd = req->bmRequestType & UT_READ; 3778 3779 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3780 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3781 3782 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3783 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3784 3785 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3786 BUS_DMASYNC_POSTWRITE); 3787 if (len) 3788 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3789 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3790 3791 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3792 } 3793 3794 /* Abort a device control request. */ 3795 Static void 3796 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3797 { 3798 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3799 3800 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3801 usbd_xfer_abort(xfer); 3802 } 3803 3804 /* Close a device control pipe. */ 3805 Static void 3806 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3807 { 3808 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3809 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3810 3811 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3812 3813 KASSERT(mutex_owned(&sc->sc_lock)); 3814 3815 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3816 3817 ehci_close_pipe(pipe, sc->sc_async_head); 3818 3819 usb_freemem(&epipe->ctrl.reqdma); 3820 } 3821 3822 /* 3823 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3824 * qTD status, or miss signalling occasionally under heavy load. If the host 3825 * machine is too fast, we can miss transaction completion - when we scan 3826 * the active list the transaction still seems to be active. This generally 3827 * exhibits itself as a umass stall that never recovers. 3828 * 3829 * We work around this behaviour by setting up this callback after any softintr 3830 * that completes with transactions still pending, giving us another chance to 3831 * check for completion after the writeback has taken place. 3832 */ 3833 Static void 3834 ehci_intrlist_timeout(void *arg) 3835 { 3836 ehci_softc_t *sc = arg; 3837 3838 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3839 3840 usb_schedsoftintr(&sc->sc_bus); 3841 } 3842 3843 /************************/ 3844 3845 Static int 3846 ehci_device_bulk_init(struct usbd_xfer *xfer) 3847 { 3848 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3849 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3850 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3851 int endpt = ed->bEndpointAddress; 3852 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3853 int len = xfer->ux_bufsize; 3854 int err = 0; 3855 3856 exfer->ex_type = EX_BULK; 3857 exfer->ex_nsqtd = 0; 3858 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3859 &exfer->ex_sqtdstart); 3860 3861 return err; 3862 } 3863 3864 Static void 3865 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3866 { 3867 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3868 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3869 3870 KASSERT(ex->ex_type == EX_BULK); 3871 3872 ehci_free_sqtds(sc, ex); 3873 if (ex->ex_nsqtd) 3874 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3875 } 3876 3877 Static usbd_status 3878 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3879 { 3880 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3881 usbd_status err; 3882 3883 /* Insert last in queue. */ 3884 mutex_enter(&sc->sc_lock); 3885 err = usb_insert_transfer(xfer); 3886 mutex_exit(&sc->sc_lock); 3887 if (err) 3888 return err; 3889 3890 /* Pipe isn't running, start first */ 3891 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3892 } 3893 3894 Static usbd_status 3895 ehci_device_bulk_start(struct usbd_xfer *xfer) 3896 { 3897 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3898 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3899 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3900 ehci_soft_qh_t *sqh; 3901 ehci_soft_qtd_t *end; 3902 int len, isread, endpt; 3903 const bool polling = sc->sc_bus.ub_usepolling; 3904 3905 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3906 3907 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3908 xfer->ux_flags, 0); 3909 3910 if (sc->sc_dying) 3911 return USBD_IOERROR; 3912 3913 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3914 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3915 3916 len = xfer->ux_length; 3917 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3918 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3919 sqh = epipe->sqh; 3920 3921 KASSERT(exfer->ex_isdone); 3922 #ifdef DIAGNOSTIC 3923 exfer->ex_isdone = false; 3924 #endif 3925 3926 /* Take lock here to protect nexttoggle */ 3927 if (!polling) 3928 mutex_enter(&sc->sc_lock); 3929 3930 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3931 3932 exfer->ex_sqtdend = end; 3933 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3934 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3935 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3936 3937 #ifdef EHCI_DEBUG 3938 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3939 ehci_dump_sqh(sqh); 3940 ehci_dump_sqtds(exfer->ex_sqtdstart); 3941 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3942 #endif 3943 3944 if (xfer->ux_length) 3945 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3946 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3947 3948 /* also does usb_syncmem(sqh) */ 3949 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3950 usbd_xfer_schedule_timeout(xfer); 3951 ehci_add_intr_list(sc, exfer); 3952 xfer->ux_status = USBD_IN_PROGRESS; 3953 if (!polling) 3954 mutex_exit(&sc->sc_lock); 3955 3956 #if 0 3957 #ifdef EHCI_DEBUG 3958 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3959 // delay(10000); 3960 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3961 ehci_dump_regs(sc); 3962 #if 0 3963 printf("async_head:\n"); 3964 ehci_dump_sqh(sc->sc_async_head); 3965 #endif 3966 DPRINTF("sqh:", 0, 0, 0, 0); 3967 ehci_dump_sqh(sqh); 3968 ehci_dump_sqtds(exfer->ex_sqtdstart); 3969 #endif 3970 #endif 3971 3972 return USBD_IN_PROGRESS; 3973 } 3974 3975 Static void 3976 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3977 { 3978 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3979 3980 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3981 usbd_xfer_abort(xfer); 3982 } 3983 3984 /* 3985 * Close a device bulk pipe. 3986 */ 3987 Static void 3988 ehci_device_bulk_close(struct usbd_pipe *pipe) 3989 { 3990 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3991 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3992 3993 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3994 3995 KASSERT(mutex_owned(&sc->sc_lock)); 3996 3997 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3998 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3999 ehci_close_pipe(pipe, sc->sc_async_head); 4000 } 4001 4002 Static void 4003 ehci_device_bulk_done(struct usbd_xfer *xfer) 4004 { 4005 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4006 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4007 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4008 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4009 4010 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4011 4012 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4013 4014 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4015 4016 if (xfer->ux_length) 4017 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4018 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4019 4020 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4021 } 4022 4023 /************************/ 4024 4025 Static usbd_status 4026 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4027 { 4028 struct ehci_soft_islot *isp; 4029 int islot, lev; 4030 4031 /* Find a poll rate that is large enough. */ 4032 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4033 if (EHCI_ILEV_IVAL(lev) <= ival) 4034 break; 4035 4036 /* Pick an interrupt slot at the right level. */ 4037 /* XXX could do better than picking at random */ 4038 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4039 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4040 4041 sqh->islot = islot; 4042 isp = &sc->sc_islots[islot]; 4043 mutex_enter(&sc->sc_lock); 4044 ehci_add_qh(sc, sqh, isp->sqh); 4045 mutex_exit(&sc->sc_lock); 4046 4047 return USBD_NORMAL_COMPLETION; 4048 } 4049 4050 Static int 4051 ehci_device_intr_init(struct usbd_xfer *xfer) 4052 { 4053 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4054 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4055 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4056 int endpt = ed->bEndpointAddress; 4057 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4058 int len = xfer->ux_bufsize; 4059 int err; 4060 4061 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4062 4063 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4064 xfer->ux_flags, 0); 4065 4066 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4067 KASSERT(len != 0); 4068 4069 exfer->ex_type = EX_INTR; 4070 exfer->ex_nsqtd = 0; 4071 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4072 &exfer->ex_sqtdstart); 4073 4074 return err; 4075 } 4076 4077 Static void 4078 ehci_device_intr_fini(struct usbd_xfer *xfer) 4079 { 4080 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4081 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4082 4083 KASSERT(ex->ex_type == EX_INTR); 4084 4085 ehci_free_sqtds(sc, ex); 4086 if (ex->ex_nsqtd) 4087 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4088 } 4089 4090 Static usbd_status 4091 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4092 { 4093 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4094 usbd_status err; 4095 4096 /* Insert last in queue. */ 4097 mutex_enter(&sc->sc_lock); 4098 err = usb_insert_transfer(xfer); 4099 mutex_exit(&sc->sc_lock); 4100 if (err) 4101 return err; 4102 4103 /* 4104 * Pipe isn't running (otherwise err would be USBD_INPROG), 4105 * so start it first. 4106 */ 4107 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4108 } 4109 4110 Static usbd_status 4111 ehci_device_intr_start(struct usbd_xfer *xfer) 4112 { 4113 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4114 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4115 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4116 ehci_soft_qtd_t *end; 4117 ehci_soft_qh_t *sqh; 4118 int len, isread, endpt; 4119 const bool polling = sc->sc_bus.ub_usepolling; 4120 4121 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4122 4123 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4124 xfer->ux_flags, 0); 4125 4126 if (sc->sc_dying) 4127 return USBD_IOERROR; 4128 4129 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4130 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4131 4132 len = xfer->ux_length; 4133 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4134 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4135 sqh = epipe->sqh; 4136 4137 KASSERT(exfer->ex_isdone); 4138 #ifdef DIAGNOSTIC 4139 exfer->ex_isdone = false; 4140 #endif 4141 4142 /* Take lock to protect nexttoggle */ 4143 if (!polling) 4144 mutex_enter(&sc->sc_lock); 4145 4146 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4147 4148 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4149 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4150 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4151 exfer->ex_sqtdend = end; 4152 4153 #ifdef EHCI_DEBUG 4154 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4155 ehci_dump_sqh(sqh); 4156 ehci_dump_sqtds(exfer->ex_sqtdstart); 4157 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4158 #endif 4159 4160 if (xfer->ux_length) 4161 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4162 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4163 4164 /* also does usb_syncmem(sqh) */ 4165 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4166 usbd_xfer_schedule_timeout(xfer); 4167 ehci_add_intr_list(sc, exfer); 4168 xfer->ux_status = USBD_IN_PROGRESS; 4169 if (!polling) 4170 mutex_exit(&sc->sc_lock); 4171 4172 #if 0 4173 #ifdef EHCI_DEBUG 4174 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4175 // delay(10000); 4176 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4177 ehci_dump_regs(sc); 4178 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4179 ehci_dump_sqh(sqh); 4180 ehci_dump_sqtds(exfer->ex_sqtdstart); 4181 #endif 4182 #endif 4183 4184 return USBD_IN_PROGRESS; 4185 } 4186 4187 Static void 4188 ehci_device_intr_abort(struct usbd_xfer *xfer) 4189 { 4190 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4191 4192 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4193 4194 /* 4195 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4196 * async doorbell. That's dependent on the async list, wheras 4197 * intr xfers are periodic, should not use this? 4198 */ 4199 usbd_xfer_abort(xfer); 4200 } 4201 4202 Static void 4203 ehci_device_intr_close(struct usbd_pipe *pipe) 4204 { 4205 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4206 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4207 struct ehci_soft_islot *isp; 4208 4209 KASSERT(mutex_owned(&sc->sc_lock)); 4210 4211 isp = &sc->sc_islots[epipe->sqh->islot]; 4212 ehci_close_pipe(pipe, isp->sqh); 4213 } 4214 4215 Static void 4216 ehci_device_intr_done(struct usbd_xfer *xfer) 4217 { 4218 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4219 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4220 4221 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4222 4223 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4224 4225 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4226 4227 if (xfer->ux_length) { 4228 int isread, endpt; 4229 4230 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4231 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4232 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4233 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4234 } 4235 } 4236 4237 /************************/ 4238 Static int 4239 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4240 { 4241 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4242 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4243 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4244 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4245 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4246 int i, k, frames; 4247 u_int huba, dir; 4248 int err; 4249 4250 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4251 4252 start = NULL; 4253 sitd = NULL; 4254 4255 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4256 xfer->ux_flags, 0); 4257 4258 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4259 KASSERT(xfer->ux_nframes != 0); 4260 KASSERT(exfer->ex_isdone); 4261 4262 exfer->ex_type = EX_FS_ISOC; 4263 /* 4264 * Step 1: Allocate and initialize sitds. 4265 */ 4266 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4267 if (i > 16 || i == 0) { 4268 /* Spec page 271 says intervals > 16 are invalid */ 4269 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4270 4271 return EINVAL; 4272 } 4273 4274 frames = xfer->ux_nframes; 4275 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4276 sitd = ehci_alloc_sitd(sc); 4277 if (sitd == NULL) { 4278 err = ENOMEM; 4279 goto fail; 4280 } 4281 4282 if (prev) 4283 prev->xfer_next = sitd; 4284 else 4285 start = sitd; 4286 4287 huba = dev->ud_myhsport->up_parent->ud_addr; 4288 4289 #if 0 4290 if (sc->sc_flags & EHCIF_FREESCALE) { 4291 // Set hub address to 0 if embedded TT is used. 4292 if (huba == sc->sc_addr) 4293 huba = 0; 4294 } 4295 #endif 4296 4297 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4298 dir = UE_GET_DIR(k) ? 1 : 0; 4299 sitd->sitd.sitd_endp = 4300 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4301 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4302 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4303 EHCI_SITD_SET_HUBA(huba) | 4304 EHCI_SITD_SET_DIR(dir)); 4305 4306 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4307 } /* End of frame */ 4308 4309 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4310 4311 stop = sitd; 4312 stop->xfer_next = NULL; 4313 exfer->ex_sitdstart = start; 4314 exfer->ex_sitdend = stop; 4315 4316 return 0; 4317 4318 fail: 4319 mutex_enter(&sc->sc_lock); 4320 ehci_soft_sitd_t *next; 4321 for (sitd = start; sitd; sitd = next) { 4322 next = sitd->xfer_next; 4323 ehci_free_sitd_locked(sc, sitd); 4324 } 4325 mutex_exit(&sc->sc_lock); 4326 4327 return err; 4328 } 4329 4330 Static void 4331 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4332 { 4333 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4334 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4335 4336 KASSERT(ex->ex_type == EX_FS_ISOC); 4337 4338 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4339 } 4340 4341 Static usbd_status 4342 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4343 { 4344 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4345 usbd_status __diagused err; 4346 4347 mutex_enter(&sc->sc_lock); 4348 err = usb_insert_transfer(xfer); 4349 mutex_exit(&sc->sc_lock); 4350 4351 KASSERT(err == USBD_NORMAL_COMPLETION); 4352 4353 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4354 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4355 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4356 ehci_soft_sitd_t *sitd; 4357 usb_dma_t *dma_buf; 4358 int i, j, k, frames; 4359 int offs; 4360 int frindex; 4361 u_int dir; 4362 4363 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4364 4365 sitd = NULL; 4366 4367 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4368 xfer->ux_flags, 0); 4369 4370 if (sc->sc_dying) 4371 return USBD_IOERROR; 4372 4373 /* 4374 * To avoid complication, don't allow a request right now that'll span 4375 * the entire frame table. To within 4 frames, to allow some leeway 4376 * on either side of where the hc currently is. 4377 */ 4378 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4379 xfer->ux_nframes >= sc->sc_flsize - 4) { 4380 printf("ehci: isoc descriptor requested that spans the entire" 4381 "frametable, too many frames\n"); 4382 return USBD_INVAL; 4383 } 4384 4385 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4386 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4387 KASSERT(exfer->ex_isdone); 4388 #ifdef DIAGNOSTIC 4389 exfer->ex_isdone = false; 4390 #endif 4391 4392 /* 4393 * Step 1: Initialize sitds. 4394 */ 4395 4396 frames = xfer->ux_nframes; 4397 dma_buf = &xfer->ux_dmabuf; 4398 offs = 0; 4399 4400 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4401 i++, sitd = sitd->xfer_next) { 4402 KASSERT(sitd != NULL); 4403 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4404 4405 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4406 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4407 4408 /* Set page0 index and offset - TP and T-offset are set below */ 4409 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4410 4411 offs += xfer->ux_frlengths[i]; 4412 4413 sitd->sitd.sitd_buffer[1] = 4414 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4415 4416 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4417 4418 #if 0 4419 if (sc->sc_flags & EHCIF_FREESCALE) { 4420 // Set hub address to 0 if embedded TT is used. 4421 if (huba == sc->sc_addr) 4422 huba = 0; 4423 } 4424 #endif 4425 4426 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4427 dir = UE_GET_DIR(k) ? 1 : 0; 4428 KASSERT(sitd->sitd.sitd_endp == htole32( 4429 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4430 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4431 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4432 EHCI_SITD_SET_HUBA(huba) | 4433 EHCI_SITD_SET_DIR(dir))); 4434 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4435 4436 uint8_t sa = 0; 4437 uint8_t sb = 0; 4438 u_int temp, tlen; 4439 4440 if (dir == 0) { /* OUT */ 4441 temp = 0; 4442 tlen = xfer->ux_frlengths[i]; 4443 if (tlen <= 188) { 4444 temp |= 1; /* T-count = 1, TP = ALL */ 4445 tlen = 1; 4446 } else { 4447 tlen += 187; 4448 tlen /= 188; 4449 temp |= tlen; /* T-count = [1..6] */ 4450 temp |= 8; /* TP = Begin */ 4451 } 4452 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4453 4454 tlen += sa; 4455 4456 if (tlen >= 8) { 4457 sb = 0; 4458 } else { 4459 sb = (1 << tlen); 4460 } 4461 4462 sa = (1 << sa); 4463 sa = (sb - sa) & 0x3F; 4464 sb = 0; 4465 } else { 4466 sb = (-(4 << sa)) & 0xFE; 4467 sa = (1 << sa) & 0x3F; 4468 sa = 0x01; 4469 sb = 0xfc; 4470 } 4471 4472 sitd->sitd.sitd_sched = htole32( 4473 EHCI_SITD_SET_SMASK(sa) | 4474 EHCI_SITD_SET_CMASK(sb) 4475 ); 4476 4477 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4478 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4479 } /* End of frame */ 4480 4481 sitd = exfer->ex_sitdend; 4482 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4483 4484 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4485 sizeof(sitd->sitd.sitd_trans), 4486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4487 4488 if (xfer->ux_length) 4489 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4491 4492 /* 4493 * Part 2: Transfer descriptors have now been set up, now they must 4494 * be scheduled into the periodic frame list. Erk. Not wanting to 4495 * complicate matters, transfer is denied if the transfer spans 4496 * more than the period frame list. 4497 */ 4498 4499 mutex_enter(&sc->sc_lock); 4500 4501 /* Start inserting frames */ 4502 if (epipe->isoc.cur_xfers > 0) { 4503 frindex = epipe->isoc.next_frame; 4504 } else { 4505 frindex = EOREAD4(sc, EHCI_FRINDEX); 4506 frindex = frindex >> 3; /* Erase microframe index */ 4507 frindex += 2; 4508 } 4509 4510 if (frindex >= sc->sc_flsize) 4511 frindex &= (sc->sc_flsize - 1); 4512 4513 /* Whats the frame interval? */ 4514 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4515 4516 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4517 j++, sitd = sitd->xfer_next) { 4518 KASSERT(sitd); 4519 4520 usb_syncmem(&sc->sc_fldma, 4521 sizeof(ehci_link_t) * frindex, 4522 sizeof(ehci_link_t), 4523 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4524 4525 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4526 if (sitd->sitd.sitd_next == 0) 4527 /* 4528 * FIXME: frindex table gets initialized to NULL 4529 * or EHCI_NULL? 4530 */ 4531 sitd->sitd.sitd_next = EHCI_NULL; 4532 4533 usb_syncmem(&sitd->dma, 4534 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4535 sizeof(ehci_sitd_t), 4536 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4537 4538 sc->sc_flist[frindex] = 4539 htole32(EHCI_LINK_SITD | sitd->physaddr); 4540 4541 usb_syncmem(&sc->sc_fldma, 4542 sizeof(ehci_link_t) * frindex, 4543 sizeof(ehci_link_t), 4544 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4545 4546 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4547 sc->sc_softsitds[frindex] = sitd; 4548 if (sitd->frame_list.next != NULL) 4549 sitd->frame_list.next->frame_list.prev = sitd; 4550 sitd->slot = frindex; 4551 sitd->frame_list.prev = NULL; 4552 4553 frindex += i; 4554 if (frindex >= sc->sc_flsize) 4555 frindex -= sc->sc_flsize; 4556 } 4557 4558 epipe->isoc.cur_xfers++; 4559 epipe->isoc.next_frame = frindex; 4560 4561 ehci_add_intr_list(sc, exfer); 4562 xfer->ux_status = USBD_IN_PROGRESS; 4563 mutex_exit(&sc->sc_lock); 4564 4565 return USBD_IN_PROGRESS; 4566 } 4567 4568 Static void 4569 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4570 { 4571 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4572 4573 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4574 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4575 } 4576 4577 Static void 4578 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4579 { 4580 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4581 4582 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4583 } 4584 4585 Static void 4586 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4587 { 4588 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4589 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4590 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4591 4592 KASSERT(mutex_owned(&sc->sc_lock)); 4593 4594 epipe->isoc.cur_xfers--; 4595 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4596 4597 if (xfer->ux_length) 4598 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4599 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4600 } 4601 4602 /* -------------------------------------------------------------------------- */ 4603 4604 Static int 4605 ehci_device_isoc_init(struct usbd_xfer *xfer) 4606 { 4607 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4608 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4609 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4610 ehci_soft_itd_t *itd, *prev, *start, *stop; 4611 int i, j, k; 4612 int frames, ufrperframe; 4613 int err; 4614 4615 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4616 4617 start = NULL; 4618 prev = NULL; 4619 itd = NULL; 4620 4621 KASSERT(xfer->ux_nframes != 0); 4622 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4623 KASSERT(exfer->ex_isdone); 4624 4625 exfer->ex_type = EX_ISOC; 4626 4627 /* 4628 * Step 1: Allocate and initialize itds, how many do we need? 4629 * One per transfer if interval >= 8 microframes, less if we use 4630 * multiple microframes per frame. 4631 */ 4632 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4633 if (i > 16 || i == 0) { 4634 /* Spec page 271 says intervals > 16 are invalid */ 4635 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4636 return USBD_INVAL; 4637 } 4638 4639 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4640 frames = howmany(xfer->ux_nframes, ufrperframe); 4641 4642 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4643 itd = ehci_alloc_itd(sc); 4644 if (itd == NULL) { 4645 err = ENOMEM; 4646 goto fail; 4647 } 4648 4649 if (prev != NULL) { 4650 /* Maybe not as it's updated by the scheduling? */ 4651 prev->itd.itd_next = 4652 htole32(itd->physaddr | EHCI_LINK_ITD); 4653 4654 prev->xfer_next = itd; 4655 } else { 4656 start = itd; 4657 } 4658 4659 /* 4660 * Other special values 4661 */ 4662 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4663 itd->itd.itd_bufr[0] = htole32( 4664 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4665 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4666 4667 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4668 ? 1 : 0; 4669 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4670 itd->itd.itd_bufr[1] |= htole32( 4671 EHCI_ITD_SET_DIR(k) | 4672 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4673 4674 /* FIXME: handle invalid trans - should be done in openpipe */ 4675 itd->itd.itd_bufr[2] |= 4676 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4677 } /* End of frame */ 4678 4679 stop = itd; 4680 stop->xfer_next = NULL; 4681 4682 exfer->ex_itdstart = start; 4683 exfer->ex_itdend = stop; 4684 4685 return 0; 4686 fail: 4687 mutex_enter(&sc->sc_lock); 4688 ehci_soft_itd_t *next; 4689 for (itd = start; itd; itd = next) { 4690 next = itd->xfer_next; 4691 ehci_free_itd_locked(sc, itd); 4692 } 4693 mutex_exit(&sc->sc_lock); 4694 4695 return err; 4696 4697 } 4698 4699 Static void 4700 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4701 { 4702 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4703 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4704 4705 KASSERT(ex->ex_type == EX_ISOC); 4706 4707 ehci_free_itd_chain(sc, ex->ex_itdstart); 4708 } 4709 4710 Static usbd_status 4711 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4712 { 4713 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4714 usbd_status __diagused err; 4715 4716 mutex_enter(&sc->sc_lock); 4717 err = usb_insert_transfer(xfer); 4718 mutex_exit(&sc->sc_lock); 4719 4720 KASSERT(err == USBD_NORMAL_COMPLETION); 4721 4722 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4723 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4724 ehci_soft_itd_t *itd, *prev; 4725 usb_dma_t *dma_buf; 4726 int i, j; 4727 int frames, uframes, ufrperframe; 4728 int trans_count, offs; 4729 int frindex; 4730 4731 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4732 4733 prev = NULL; 4734 itd = NULL; 4735 trans_count = 0; 4736 4737 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4738 4739 if (sc->sc_dying) 4740 return USBD_IOERROR; 4741 4742 /* 4743 * To avoid complication, don't allow a request right now that'll span 4744 * the entire frame table. To within 4 frames, to allow some leeway 4745 * on either side of where the hc currently is. 4746 */ 4747 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4748 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4749 DPRINTF( 4750 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4751 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4752 return USBD_INVAL; 4753 } 4754 4755 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4756 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4757 KASSERT(exfer->ex_isdone); 4758 #ifdef DIAGNOSTIC 4759 exfer->ex_isdone = false; 4760 #endif 4761 4762 /* 4763 * Step 1: Re-Initialize itds 4764 */ 4765 4766 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4767 if (i > 16 || i == 0) { 4768 /* Spec page 271 says intervals > 16 are invalid */ 4769 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4770 return USBD_INVAL; 4771 } 4772 4773 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4774 frames = howmany(xfer->ux_nframes, ufrperframe); 4775 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4776 4777 if (frames == 0) { 4778 DPRINTF("frames == 0", 0, 0, 0, 0); 4779 return USBD_INVAL; 4780 } 4781 4782 dma_buf = &xfer->ux_dmabuf; 4783 offs = 0; 4784 4785 itd = exfer->ex_itdstart; 4786 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4787 int froffs = offs; 4788 4789 if (prev != NULL) { 4790 prev->itd.itd_next = 4791 htole32(itd->physaddr | EHCI_LINK_ITD); 4792 usb_syncmem(&prev->dma, 4793 prev->offs + offsetof(ehci_itd_t, itd_next), 4794 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4795 prev->xfer_next = itd; 4796 } 4797 4798 /* 4799 * Step 1.5, initialize uframes 4800 */ 4801 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4802 /* Calculate which page in the list this starts in */ 4803 int addr = DMAADDR(dma_buf, froffs); 4804 addr = EHCI_PAGE_OFFSET(addr); 4805 addr += (offs - froffs); 4806 addr = EHCI_PAGE(addr); 4807 addr /= EHCI_PAGE_SIZE; 4808 4809 /* 4810 * This gets the initial offset into the first page, 4811 * looks how far further along the current uframe 4812 * offset is. Works out how many pages that is. 4813 */ 4814 4815 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4816 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4817 EHCI_ITD_SET_PG(addr) | 4818 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4819 4820 offs += xfer->ux_frlengths[trans_count]; 4821 trans_count++; 4822 4823 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4824 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4825 break; 4826 } 4827 } 4828 4829 /* 4830 * Step 1.75, set buffer pointers. To simplify matters, all 4831 * pointers are filled out for the next 7 hardware pages in 4832 * the dma block, so no need to worry what pages to cover 4833 * and what to not. 4834 */ 4835 4836 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4837 /* 4838 * Don't try to lookup a page that's past the end 4839 * of buffer 4840 */ 4841 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4842 if (page_offs >= dma_buf->udma_block->size) 4843 break; 4844 4845 uint64_t page = DMAADDR(dma_buf, page_offs); 4846 page = EHCI_PAGE(page); 4847 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4848 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4849 } 4850 /* 4851 * Other special values 4852 */ 4853 4854 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4855 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4856 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4857 4858 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4859 ? 1 : 0; 4860 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4861 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4862 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4863 4864 /* FIXME: handle invalid trans */ 4865 itd->itd.itd_bufr[2] |= 4866 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4867 4868 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4869 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4870 4871 prev = itd; 4872 } /* End of frame */ 4873 4874 if (xfer->ux_length) 4875 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4877 4878 /* 4879 * Part 2: Transfer descriptors have now been set up, now they must 4880 * be scheduled into the period frame list. Erk. Not wanting to 4881 * complicate matters, transfer is denied if the transfer spans 4882 * more than the period frame list. 4883 */ 4884 4885 mutex_enter(&sc->sc_lock); 4886 4887 /* Start inserting frames */ 4888 if (epipe->isoc.cur_xfers > 0) { 4889 frindex = epipe->isoc.next_frame; 4890 } else { 4891 frindex = EOREAD4(sc, EHCI_FRINDEX); 4892 frindex = frindex >> 3; /* Erase microframe index */ 4893 frindex += 2; 4894 } 4895 4896 if (frindex >= sc->sc_flsize) 4897 frindex &= (sc->sc_flsize - 1); 4898 4899 /* What's the frame interval? */ 4900 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4901 if (i / USB_UFRAMES_PER_FRAME == 0) 4902 i = 1; 4903 else 4904 i /= USB_UFRAMES_PER_FRAME; 4905 4906 itd = exfer->ex_itdstart; 4907 for (j = 0; j < frames; j++) { 4908 KASSERTMSG(itd != NULL, "frame %d\n", j); 4909 4910 usb_syncmem(&sc->sc_fldma, 4911 sizeof(ehci_link_t) * frindex, 4912 sizeof(ehci_link_t), 4913 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4914 4915 itd->itd.itd_next = sc->sc_flist[frindex]; 4916 if (itd->itd.itd_next == 0) 4917 /* 4918 * FIXME: frindex table gets initialized to NULL 4919 * or EHCI_NULL? 4920 */ 4921 itd->itd.itd_next = EHCI_NULL; 4922 4923 usb_syncmem(&itd->dma, 4924 itd->offs + offsetof(ehci_itd_t, itd_next), 4925 sizeof(itd->itd.itd_next), 4926 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4927 4928 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4929 4930 usb_syncmem(&sc->sc_fldma, 4931 sizeof(ehci_link_t) * frindex, 4932 sizeof(ehci_link_t), 4933 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4934 4935 itd->frame_list.next = sc->sc_softitds[frindex]; 4936 sc->sc_softitds[frindex] = itd; 4937 if (itd->frame_list.next != NULL) 4938 itd->frame_list.next->frame_list.prev = itd; 4939 itd->slot = frindex; 4940 itd->frame_list.prev = NULL; 4941 4942 frindex += i; 4943 if (frindex >= sc->sc_flsize) 4944 frindex -= sc->sc_flsize; 4945 4946 itd = itd->xfer_next; 4947 } 4948 4949 epipe->isoc.cur_xfers++; 4950 epipe->isoc.next_frame = frindex; 4951 4952 ehci_add_intr_list(sc, exfer); 4953 xfer->ux_status = USBD_IN_PROGRESS; 4954 mutex_exit(&sc->sc_lock); 4955 4956 return USBD_IN_PROGRESS; 4957 } 4958 4959 Static void 4960 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4961 { 4962 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4963 4964 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4965 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4966 } 4967 4968 Static void 4969 ehci_device_isoc_close(struct usbd_pipe *pipe) 4970 { 4971 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4972 4973 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4974 } 4975 4976 Static void 4977 ehci_device_isoc_done(struct usbd_xfer *xfer) 4978 { 4979 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4980 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4981 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4982 4983 KASSERT(mutex_owned(&sc->sc_lock)); 4984 4985 epipe->isoc.cur_xfers--; 4986 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4987 if (xfer->ux_length) 4988 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4989 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4990 } 4991
Indexes created Mon Sep 22 13:09:51 GMT 2025