ehci.c revision 1.312
1 /* $NetBSD: ehci.c,v 1.312 2022/12/13 21:11:00 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna.com.au), and 11 * Nick Hudson . 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 37 * 38 * The EHCI 1.0 spec can be found at 39 * http://www.intel.com/technology/usb/spec.htm 40 * and the USB 2.0 spec at 41 * http://www.usb.org/developers/docs/ 42 * 43 */ 44 45 /* 46 * TODO: 47 * 1) hold off explorations by companion controllers until ehci has started. 48 * 49 * 2) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 3) Command failures are not recovered correctly. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.312 2022/12/13 21:11:00 jakllsch Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #ifdef _KERNEL_OPT 63 #include "opt_usb.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #include <sys/bus.h> 69 #include <sys/cpu.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/kmem.h> 73 #include <sys/mutex.h> 74 #include <sys/proc.h> 75 #include <sys/queue.h> 76 #include <sys/select.h> 77 #include <sys/sysctl.h> 78 #include <sys/systm.h> 79 #include <sys/reboot.h> 80 81 #include <machine/endian.h> 82 83 #include <dev/usb/usb.h> 84 #include <dev/usb/usbdi.h> 85 #include <dev/usb/usbdivar.h> 86 #include <dev/usb/usbhist.h> 87 #include <dev/usb/usb_mem.h> 88 #include <dev/usb/usb_quirks.h> 89 90 #include <dev/usb/ehcireg.h> 91 #include <dev/usb/ehcivar.h> 92 #include <dev/usb/usbroothub.h> 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 static int ehcidebug = 0; 99 100 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 101 { 102 int err; 103 const struct sysctlnode *rnode; 104 const struct sysctlnode *cnode; 105 106 err = sysctl_createv(clog, 0, NULL, &rnode, 107 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 108 SYSCTL_DESCR("ehci global controls"), 109 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 110 111 if (err) 112 goto fail; 113 114 /* control debugging printfs */ 115 err = sysctl_createv(clog, 0, &rnode, &cnode, 116 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 117 "debug", SYSCTL_DESCR("Enable debugging output"), 118 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 119 if (err) 120 goto fail; 121 122 return; 123 fail: 124 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 125 } 126 127 #endif /* EHCI_DEBUG */ 128 #endif /* USB_DEBUG */ 129 130 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 131 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 132 #define EHCIHIST_FUNC() USBHIST_FUNC() 133 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 134 135 struct ehci_pipe { 136 struct usbd_pipe pipe; 137 int nexttoggle; 138 139 ehci_soft_qh_t *sqh; 140 union { 141 /* Control pipe */ 142 struct { 143 usb_dma_t reqdma; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 u_int length; 148 } intr; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 }; 155 }; 156 157 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 158 159 Static usbd_status ehci_open(struct usbd_pipe *); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_intrlist_timeout(void *); 171 Static void ehci_doorbell(void *); 172 Static void ehci_pcd(void *); 173 174 Static struct usbd_xfer * 175 ehci_allocx(struct usbd_bus *, unsigned int); 176 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 177 178 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 179 Static bool ehci_dying(struct usbd_bus *); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abortx(struct usbd_xfer *); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_abortx = ehci_abortx, 323 .ubm_dying = ehci_dying, 324 .ubm_getlock = ehci_get_lock, 325 .ubm_rhctrl = ehci_roothub_ctrl, 326 }; 327 328 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 329 .upm_transfer = ehci_root_intr_transfer, 330 .upm_start = ehci_root_intr_start, 331 .upm_abort = ehci_root_intr_abort, 332 .upm_close = ehci_root_intr_close, 333 .upm_cleartoggle = ehci_noop, 334 .upm_done = ehci_root_intr_done, 335 }; 336 337 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 338 .upm_init = ehci_device_ctrl_init, 339 .upm_fini = ehci_device_ctrl_fini, 340 .upm_transfer = ehci_device_ctrl_transfer, 341 .upm_start = ehci_device_ctrl_start, 342 .upm_abort = ehci_device_ctrl_abort, 343 .upm_close = ehci_device_ctrl_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_ctrl_done, 346 }; 347 348 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 349 .upm_init = ehci_device_intr_init, 350 .upm_fini = ehci_device_intr_fini, 351 .upm_transfer = ehci_device_intr_transfer, 352 .upm_start = ehci_device_intr_start, 353 .upm_abort = ehci_device_intr_abort, 354 .upm_close = ehci_device_intr_close, 355 .upm_cleartoggle = ehci_device_clear_toggle, 356 .upm_done = ehci_device_intr_done, 357 }; 358 359 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 360 .upm_init = ehci_device_bulk_init, 361 .upm_fini = ehci_device_bulk_fini, 362 .upm_transfer = ehci_device_bulk_transfer, 363 .upm_start = ehci_device_bulk_start, 364 .upm_abort = ehci_device_bulk_abort, 365 .upm_close = ehci_device_bulk_close, 366 .upm_cleartoggle = ehci_device_clear_toggle, 367 .upm_done = ehci_device_bulk_done, 368 }; 369 370 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 371 .upm_init = ehci_device_isoc_init, 372 .upm_fini = ehci_device_isoc_fini, 373 .upm_transfer = ehci_device_isoc_transfer, 374 .upm_abort = ehci_device_isoc_abort, 375 .upm_close = ehci_device_isoc_close, 376 .upm_cleartoggle = ehci_noop, 377 .upm_done = ehci_device_isoc_done, 378 }; 379 380 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 381 .upm_init = ehci_device_fs_isoc_init, 382 .upm_fini = ehci_device_fs_isoc_fini, 383 .upm_transfer = ehci_device_fs_isoc_transfer, 384 .upm_abort = ehci_device_fs_isoc_abort, 385 .upm_close = ehci_device_fs_isoc_close, 386 .upm_cleartoggle = ehci_noop, 387 .upm_done = ehci_device_fs_isoc_done, 388 }; 389 390 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 391 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 392 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 393 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 394 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 395 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 396 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 397 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 398 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 399 }; 400 401 int 402 ehci_init(ehci_softc_t *sc) 403 { 404 uint32_t vers, hcr; 405 u_int i; 406 int err; 407 ehci_soft_qh_t *sqh; 408 u_int ncomp; 409 410 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 411 #ifdef EHCI_DEBUG 412 theehci = sc; 413 #endif 414 415 mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE); 416 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 417 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 418 cv_init(&sc->sc_doorbell, "ehcidb"); 419 420 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 421 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 422 423 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 424 ehci_doorbell, sc); 425 KASSERT(sc->sc_doorbell_si != NULL); 426 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 427 ehci_pcd, sc); 428 KASSERT(sc->sc_pcd_si != NULL); 429 430 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 431 432 vers = EREAD2(sc, EHCI_HCIVERSION); 433 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 434 vers >> 8, vers & 0xff); 435 436 const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS); 437 DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0); 438 sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams); 439 ncomp = EHCI_HCS_N_CC(hcsparams); 440 if (ncomp != sc->sc_ncomp) { 441 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 442 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 443 #if NOHCI == 0 || NUHCI == 0 444 aprint_error("%s: ohci or uhci probably not configured\n", 445 device_xname(sc->sc_dev)); 446 #endif 447 if (ncomp < sc->sc_ncomp) 448 sc->sc_ncomp = ncomp; 449 } 450 if (sc->sc_ncomp > 0) { 451 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 452 aprint_normal_dev(sc->sc_dev, 453 "%d companion controller%s, %d port%s%s", 454 sc->sc_ncomp, 455 sc->sc_ncomp!=1 ? "s" : "", 456 EHCI_HCS_N_PCC(hcsparams), 457 EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "", 458 sc->sc_ncomp!=1 ? " each" : ""); 459 if (sc->sc_comps[0]) { 460 aprint_normal(":"); 461 for (i = 0; i < sc->sc_ncomp; i++) 462 aprint_normal(" %s", 463 device_xname(sc->sc_comps[i])); 464 } 465 aprint_normal("\n"); 466 467 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 468 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 469 cv_init(&sc->sc_compcv, "ehciccv"); 470 sc->sc_comp_state = CO_EARLY; 471 } 472 sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams); 473 sc->sc_hasppc = EHCI_HCS_PPC(hcsparams); 474 475 const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS); 476 DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0); 477 478 if (EHCI_HCC_64BIT(hccparams)) { 479 /* MUST clear segment register if 64 bit capable. */ 480 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 481 } 482 483 if (hccparams & EHCI_HCC_IST_FULLFRAME) { 484 sc->sc_istthreshold = 0; 485 } else { 486 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams); 487 } 488 489 sc->sc_bus.ub_revision = USBREV_2_0; 490 sc->sc_bus.ub_usedma = true; 491 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 492 493 /* 494 * The bus attachment code will possibly provide a 64bit DMA 495 * tag which we now limit to the bottom 4G range as 496 * 497 * - that's as much as ehci can address in its QH, TD, iTD, and siTD 498 * structures; and 499 * - the driver doesn't currently set EHCI_CTRLDSSEGMENT to anything 500 * other than 0. 501 */ 502 bus_dma_tag_t ntag = sc->sc_bus.ub_dmatag; 503 sc->sc_dmatag = sc->sc_bus.ub_dmatag; 504 err = bus_dmatag_subregion(sc->sc_bus.ub_dmatag, 0, UINT32_MAX, 505 &ntag, 0); 506 if (err == 0) { 507 sc->sc_dmatag = ntag; 508 aprint_normal_dev(sc->sc_dev, "Using DMA subregion for control" 509 " data structures\n"); 510 } 511 512 /* Reset the controller */ 513 DPRINTF("resetting", 0, 0, 0, 0); 514 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 515 usb_delay_ms(&sc->sc_bus, 1); 516 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 517 for (i = 0; i < 100; i++) { 518 usb_delay_ms(&sc->sc_bus, 1); 519 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 520 if (!hcr) 521 break; 522 } 523 if (hcr) { 524 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 525 err = EIO; 526 goto fail1; 527 } 528 if (sc->sc_vendor_init) 529 sc->sc_vendor_init(sc); 530 531 /* XXX need proper intr scheduling */ 532 sc->sc_rand = 96; 533 534 /* frame list size at default, read back what we got and use that */ 535 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 536 case 0: sc->sc_flsize = 1024; break; 537 case 1: sc->sc_flsize = 512; break; 538 case 2: sc->sc_flsize = 256; break; 539 case 3: 540 err = EIO; 541 goto fail1; 542 } 543 err = usb_allocmem(sc->sc_dmatag, 544 sc->sc_flsize * sizeof(ehci_link_t), 545 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 546 if (err) { 547 aprint_error_dev(sc->sc_dev, "failed to allocate frame list\n"); 548 goto fail1; 549 } 550 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 551 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 552 553 for (i = 0; i < sc->sc_flsize; i++) { 554 sc->sc_flist[i] = EHCI_NULL; 555 } 556 557 const bus_addr_t flba = DMAADDR(&sc->sc_fldma, 0); 558 const uint32_t hi32 = BUS_ADDR_HI32(flba); 559 if (hi32 != 0) { 560 aprint_error_dev(sc->sc_dev, "DMA memory segment error (%08x)\n", 561 hi32); 562 goto fail2; 563 } 564 565 const uint32_t lo32 = BUS_ADDR_LO32(flba); 566 EOWRITE4(sc, EHCI_PERIODICLISTBASE, lo32); 567 568 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 569 KM_SLEEP); 570 LIST_INIT(&sc->sc_freeitds); 571 LIST_INIT(&sc->sc_freesitds); 572 TAILQ_INIT(&sc->sc_intrhead); 573 574 /* Set up the bus struct. */ 575 sc->sc_bus.ub_methods = &ehci_bus_methods; 576 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 577 578 sc->sc_eintrs = EHCI_NORMAL_INTRS; 579 580 /* 581 * Allocate the interrupt dummy QHs. These are arranged to give poll 582 * intervals that are powers of 2 times 1ms. 583 */ 584 memset(sc->sc_islots, 0, sizeof(sc->sc_islots)); 585 for (i = 0; i < EHCI_INTRQHS; i++) { 586 sqh = ehci_alloc_sqh(sc); 587 if (sqh == NULL) { 588 err = ENOMEM; 589 goto fail3; 590 } 591 sc->sc_islots[i].sqh = sqh; 592 } 593 for (i = 0; i < EHCI_INTRQHS; i++) { 594 sqh = sc->sc_islots[i].sqh; 595 if (i == 0) { 596 /* The last (1ms) QH terminates. */ 597 sqh->qh.qh_link = EHCI_NULL; 598 sqh->next = NULL; 599 } else { 600 /* Otherwise the next QH has half the poll interval */ 601 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 602 sqh->qh.qh_link = htole32(sqh->next->physaddr | 603 EHCI_LINK_QH); 604 } 605 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 606 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 607 sqh->qh.qh_curqtd = EHCI_NULL; 608 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 609 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 610 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 611 sqh->sqtd = NULL; 612 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 613 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 614 } 615 /* Point the frame list at the last level (128ms). */ 616 for (i = 0; i < sc->sc_flsize; i++) { 617 int j; 618 619 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 620 revbits[i & (EHCI_MAX_POLLRATE-1)]; 621 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 622 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 623 i)].sqh->physaddr); 624 } 625 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 626 BUS_DMASYNC_PREWRITE); 627 628 /* Allocate dummy QH that starts the async list. */ 629 sqh = ehci_alloc_sqh(sc); 630 if (sqh == NULL) { 631 err = ENOMEM; 632 goto fail3; 633 } 634 /* Fill the QH */ 635 sqh->qh.qh_endp = 636 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 637 sqh->qh.qh_link = 638 htole32(sqh->physaddr | EHCI_LINK_QH); 639 sqh->qh.qh_curqtd = EHCI_NULL; 640 sqh->next = NULL; 641 /* Fill the overlay qTD */ 642 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 643 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 644 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 645 sqh->sqtd = NULL; 646 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 647 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 648 #ifdef EHCI_DEBUG 649 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 650 ehci_dump_sqh(sqh); 651 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 652 #endif 653 654 /* Point to async list */ 655 sc->sc_async_head = sqh; 656 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 657 658 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 659 660 /* Turn on controller */ 661 EOWRITE4(sc, EHCI_USBCMD, 662 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 663 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 664 EHCI_CMD_ASE | 665 EHCI_CMD_PSE | 666 EHCI_CMD_RS); 667 668 /* Take over port ownership */ 669 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 670 671 for (i = 0; i < 100; i++) { 672 usb_delay_ms(&sc->sc_bus, 1); 673 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 674 if (!hcr) 675 break; 676 } 677 if (hcr) { 678 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 679 err = EIO; 680 goto fail4; 681 } 682 683 /* Enable interrupts */ 684 DPRINTF("enabling interrupts", 0, 0, 0, 0); 685 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 686 687 return 0; 688 689 fail4: 690 ehci_free_sqh(sc, sc->sc_async_head); 691 692 fail3: 693 for (i = 0; i < EHCI_INTRQHS; i++) { 694 sqh = sc->sc_islots[i].sqh; 695 if (sqh) 696 ehci_free_sqh(sc, sqh); 697 } 698 699 kmem_free(sc->sc_softitds, sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 700 701 fail2: 702 usb_freemem(&sc->sc_fldma); 703 704 fail1: 705 softint_disestablish(sc->sc_doorbell_si); 706 softint_disestablish(sc->sc_pcd_si); 707 mutex_destroy(&sc->sc_rhlock); 708 mutex_destroy(&sc->sc_lock); 709 mutex_destroy(&sc->sc_intr_lock); 710 711 return err; 712 } 713 714 int 715 ehci_intr(void *v) 716 { 717 ehci_softc_t *sc = v; 718 int ret = 0; 719 720 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 721 722 if (sc == NULL) 723 return 0; 724 725 mutex_spin_enter(&sc->sc_intr_lock); 726 727 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 728 goto done; 729 730 /* If we get an interrupt while polling, then just ignore it. */ 731 if (sc->sc_bus.ub_usepolling) { 732 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 733 734 if (intrs) 735 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 736 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 737 goto done; 738 } 739 740 ret = ehci_intr1(sc); 741 742 done: 743 mutex_spin_exit(&sc->sc_intr_lock); 744 return ret; 745 } 746 747 Static int 748 ehci_intr1(ehci_softc_t *sc) 749 { 750 uint32_t intrs, eintrs; 751 752 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 753 754 /* In case the interrupt occurs before initialization has completed. */ 755 if (sc == NULL) { 756 #ifdef DIAGNOSTIC 757 printf("ehci_intr1: sc == NULL\n"); 758 #endif 759 return 0; 760 } 761 762 KASSERT(mutex_owned(&sc->sc_intr_lock)); 763 764 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 765 if (!intrs) 766 return 0; 767 768 eintrs = intrs & sc->sc_eintrs; 769 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 770 EOREAD4(sc, EHCI_USBSTS), eintrs); 771 if (!eintrs) 772 return 0; 773 774 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 775 if (eintrs & EHCI_STS_IAA) { 776 DPRINTF("door bell", 0, 0, 0, 0); 777 kpreempt_disable(); 778 KASSERT(sc->sc_doorbell_si != NULL); 779 softint_schedule(sc->sc_doorbell_si); 780 kpreempt_enable(); 781 eintrs &= ~EHCI_STS_IAA; 782 } 783 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 784 DPRINTF("INT=%jd ERRINT=%jd", 785 eintrs & EHCI_STS_INT ? 1 : 0, 786 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 787 usb_schedsoftintr(&sc->sc_bus); 788 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 789 } 790 if (eintrs & EHCI_STS_HSE) { 791 printf("%s: unrecoverable error, controller halted\n", 792 device_xname(sc->sc_dev)); 793 /* XXX what else */ 794 } 795 if (eintrs & EHCI_STS_PCD) { 796 kpreempt_disable(); 797 KASSERT(sc->sc_pcd_si != NULL); 798 softint_schedule(sc->sc_pcd_si); 799 kpreempt_enable(); 800 eintrs &= ~EHCI_STS_PCD; 801 } 802 803 if (eintrs != 0) { 804 /* Block unprocessed interrupts. */ 805 sc->sc_eintrs &= ~eintrs; 806 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 807 printf("%s: blocking intrs %#x\n", 808 device_xname(sc->sc_dev), eintrs); 809 } 810 811 return 1; 812 } 813 814 Static void 815 ehci_doorbell(void *addr) 816 { 817 ehci_softc_t *sc = addr; 818 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 819 820 mutex_enter(&sc->sc_lock); 821 if (sc->sc_doorbelllwp == NULL) 822 DPRINTF("spurious doorbell interrupt", 0, 0, 0, 0); 823 sc->sc_doorbelllwp = NULL; 824 cv_signal(&sc->sc_doorbell); 825 mutex_exit(&sc->sc_lock); 826 } 827 828 Static void 829 ehci_pcd(void *addr) 830 { 831 ehci_softc_t *sc = addr; 832 struct usbd_xfer *xfer; 833 u_char *p; 834 int i, m; 835 836 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 837 838 mutex_enter(&sc->sc_lock); 839 xfer = sc->sc_intrxfer; 840 841 if (xfer == NULL) { 842 /* Just ignore the change. */ 843 goto done; 844 } 845 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 846 847 p = xfer->ux_buf; 848 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 849 memset(p, 0, xfer->ux_length); 850 for (i = 1; i <= m; i++) { 851 /* Pick out CHANGE bits from the status reg. */ 852 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 853 p[i/8] |= 1 << (i%8); 854 if (i % 8 == 7) 855 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 856 } 857 xfer->ux_actlen = xfer->ux_length; 858 xfer->ux_status = USBD_NORMAL_COMPLETION; 859 860 usb_transfer_complete(xfer); 861 862 done: 863 mutex_exit(&sc->sc_lock); 864 } 865 866 Static void 867 ehci_softintr(void *v) 868 { 869 struct usbd_bus *bus = v; 870 ehci_softc_t *sc = EHCI_BUS2SC(bus); 871 struct ehci_xfer *ex, *nextex; 872 873 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 874 875 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 876 877 ex_completeq_t cq; 878 TAILQ_INIT(&cq); 879 880 /* 881 * The only explanation I can think of for why EHCI is as brain dead 882 * as UHCI interrupt-wise is that Intel was involved in both. 883 * An interrupt just tells us that something is done, we have no 884 * clue what, so we need to scan through all active transfers. :-( 885 */ 886 887 /* 888 * ehci_idone will remove transfer from sc->sc_intrhead if it's 889 * complete and add to our cq list 890 * 891 */ 892 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 893 switch (ex->ex_type) { 894 case EX_CTRL: 895 case EX_BULK: 896 case EX_INTR: 897 ehci_check_qh_intr(sc, ex, &cq); 898 break; 899 case EX_ISOC: 900 ehci_check_itd_intr(sc, ex, &cq); 901 break; 902 case EX_FS_ISOC: 903 ehci_check_sitd_intr(sc, ex, &cq); 904 break; 905 default: 906 KASSERT(false); 907 } 908 909 } 910 911 /* 912 * We abuse ex_next for the interrupt and complete lists and 913 * interrupt transfers will get re-added here so use 914 * the _SAFE version of TAILQ_FOREACH. 915 */ 916 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 917 usb_transfer_complete(&ex->ex_xfer); 918 } 919 920 /* Schedule a callout to catch any dropped transactions. */ 921 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 922 !TAILQ_EMPTY(&sc->sc_intrhead)) 923 callout_reset(&sc->sc_tmo_intrlist, 924 hz, ehci_intrlist_timeout, sc); 925 } 926 927 Static void 928 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 929 { 930 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 931 uint32_t status; 932 933 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 934 935 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 936 937 if (ex->ex_type == EX_CTRL) { 938 fsqtd = ex->ex_setup; 939 lsqtd = ex->ex_status; 940 } else { 941 fsqtd = ex->ex_sqtdstart; 942 lsqtd = ex->ex_sqtdend; 943 } 944 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 945 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 946 947 /* 948 * If the last TD is still active we need to check whether there 949 * is an error somewhere in the middle, or whether there was a 950 * short packet (SPD and not ACTIVE). 951 */ 952 usb_syncmem(&lsqtd->dma, 953 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 954 sizeof(lsqtd->qtd.qtd_status), 955 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 956 status = le32toh(lsqtd->qtd.qtd_status); 957 usb_syncmem(&lsqtd->dma, 958 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 959 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 960 if (status & EHCI_QTD_ACTIVE) { 961 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 962 963 /* last qTD has already been checked */ 964 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 965 usb_syncmem(&sqtd->dma, 966 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 967 sizeof(sqtd->qtd.qtd_status), 968 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 969 status = le32toh(sqtd->qtd.qtd_status); 970 usb_syncmem(&sqtd->dma, 971 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 972 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 973 /* If there's an active QTD the xfer isn't done. */ 974 if (status & EHCI_QTD_ACTIVE) 975 break; 976 /* Any kind of error makes the xfer done. */ 977 if (status & EHCI_QTD_HALTED) 978 goto done; 979 /* Handle short packets */ 980 if (EHCI_QTD_GET_BYTES(status) != 0) { 981 /* 982 * If we get here for a control transfer then 983 * we need to let the hardware complete the 984 * status phase. That is, we're not done 985 * quite yet. 986 * 987 * Otherwise, we're done. 988 */ 989 if (ex->ex_type == EX_CTRL) { 990 break; 991 } 992 goto done; 993 } 994 } 995 DPRINTFN(10, "ex=%#jx std=%#jx still active", 996 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 997 #ifdef EHCI_DEBUG 998 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 999 ehci_dump_sqtds(ex->ex_sqtdstart); 1000 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 1001 #endif 1002 return; 1003 } 1004 done: 1005 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1006 ehci_idone(ex, cq); 1007 } 1008 1009 Static void 1010 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1011 { 1012 ehci_soft_itd_t *itd; 1013 int i; 1014 1015 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1016 1017 KASSERT(mutex_owned(&sc->sc_lock)); 1018 1019 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1020 return; 1021 1022 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 1023 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 1024 1025 itd = ex->ex_itdend; 1026 1027 /* 1028 * check no active transfers in last itd, meaning we're finished 1029 */ 1030 1031 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1032 sizeof(itd->itd.itd_ctl), 1033 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1034 1035 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1036 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 1037 break; 1038 } 1039 1040 if (i == EHCI_ITD_NUFRAMES) { 1041 goto done; /* All 8 descriptors inactive, it's done */ 1042 } 1043 1044 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1045 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1046 1047 DPRINTFN(10, "ex %#jx itd %#jx still active", 1048 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 1049 return; 1050 done: 1051 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 1052 ehci_idone(ex, cq); 1053 } 1054 1055 void 1056 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1057 { 1058 ehci_soft_sitd_t *sitd; 1059 1060 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1061 1062 KASSERT(mutex_owned(&sc->sc_lock)); 1063 1064 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1065 return; 1066 1067 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1068 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1069 1070 sitd = ex->ex_sitdend; 1071 1072 /* 1073 * check no active transfers in last sitd, meaning we're finished 1074 */ 1075 1076 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1077 sizeof(sitd->sitd.sitd_trans), 1078 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1079 1080 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1081 1082 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1083 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1084 1085 if (active) 1086 return; 1087 1088 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1089 ehci_idone(ex, cq); 1090 } 1091 1092 Static void 1093 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1094 { 1095 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1096 struct usbd_xfer *xfer = &ex->ex_xfer; 1097 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1098 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1099 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1100 uint32_t status = 0, nstatus = 0; 1101 int actlen = 0; 1102 1103 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1104 1105 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1106 1107 /* 1108 * Try to claim this xfer for completion. If it has already 1109 * completed or aborted, drop it on the floor. 1110 */ 1111 if (!usbd_xfer_trycomplete(xfer)) 1112 return; 1113 1114 #ifdef DIAGNOSTIC 1115 #ifdef EHCI_DEBUG 1116 if (ex->ex_isdone) { 1117 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1118 ehci_dump_exfer(ex); 1119 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1120 } 1121 #endif 1122 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1123 ex->ex_type, xfer->ux_status); 1124 ex->ex_isdone = true; 1125 #endif 1126 1127 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1128 (uintptr_t)epipe, 0, 0); 1129 1130 /* The transfer is done, compute actual length and status. */ 1131 if (ex->ex_type == EX_ISOC) { 1132 /* HS isoc transfer */ 1133 1134 struct ehci_soft_itd *itd; 1135 int i, nframes, len, uframes; 1136 1137 nframes = 0; 1138 1139 #ifdef EHCI_DEBUG 1140 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1141 ehci_dump_itds(ex->ex_itdstart); 1142 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1143 #endif 1144 1145 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1146 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1147 1148 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1149 usb_syncmem(&itd->dma, 1150 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1151 sizeof(itd->itd.itd_ctl), 1152 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1153 1154 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1155 /* 1156 * XXX - driver didn't fill in the frame full 1157 * of uframes. This leads to scheduling 1158 * inefficiencies, but working around 1159 * this doubles complexity of tracking 1160 * an xfer. 1161 */ 1162 if (nframes >= xfer->ux_nframes) 1163 break; 1164 1165 status = le32toh(itd->itd.itd_ctl[i]); 1166 len = EHCI_ITD_GET_LEN(status); 1167 if (EHCI_ITD_GET_STATUS(status) != 0) 1168 len = 0; /*No valid data on error*/ 1169 1170 xfer->ux_frlengths[nframes++] = len; 1171 actlen += len; 1172 } 1173 usb_syncmem(&itd->dma, 1174 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1175 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1176 1177 if (nframes >= xfer->ux_nframes) 1178 break; 1179 } 1180 1181 xfer->ux_actlen = actlen; 1182 xfer->ux_status = USBD_NORMAL_COMPLETION; 1183 goto end; 1184 } else if (ex->ex_type == EX_FS_ISOC) { 1185 /* FS isoc transfer */ 1186 struct ehci_soft_sitd *sitd; 1187 int nframes, len; 1188 1189 nframes = 0; 1190 1191 for (sitd = ex->ex_sitdstart; sitd != NULL; 1192 sitd = sitd->xfer_next) { 1193 usb_syncmem(&sitd->dma, 1194 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1195 sizeof(sitd->sitd.sitd_trans), 1196 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1197 1198 /* 1199 * XXX - driver didn't fill in the frame full 1200 * of uframes. This leads to scheduling 1201 * inefficiencies, but working around 1202 * this doubles complexity of tracking 1203 * an xfer. 1204 */ 1205 if (nframes >= xfer->ux_nframes) 1206 break; 1207 1208 status = le32toh(sitd->sitd.sitd_trans); 1209 usb_syncmem(&sitd->dma, 1210 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1211 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1212 1213 len = EHCI_SITD_GET_LEN(status); 1214 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1215 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1216 /* No valid data on error */ 1217 len = xfer->ux_frlengths[nframes]; 1218 } 1219 1220 /* 1221 * frlengths[i]: # of bytes to send 1222 * len: # of bytes host didn't send 1223 */ 1224 xfer->ux_frlengths[nframes] -= len; 1225 /* frlengths[i]: # of bytes host sent */ 1226 actlen += xfer->ux_frlengths[nframes++]; 1227 1228 if (nframes >= xfer->ux_nframes) 1229 break; 1230 } 1231 1232 xfer->ux_actlen = actlen; 1233 xfer->ux_status = USBD_NORMAL_COMPLETION; 1234 goto end; 1235 } 1236 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1237 ex->ex_type == EX_BULK); 1238 1239 /* Continue processing xfers using queue heads */ 1240 if (ex->ex_type == EX_CTRL) { 1241 fsqtd = ex->ex_setup; 1242 lsqtd = ex->ex_status; 1243 } else { 1244 fsqtd = ex->ex_sqtdstart; 1245 lsqtd = ex->ex_sqtdend; 1246 } 1247 #ifdef EHCI_DEBUG 1248 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1249 ehci_dump_sqtds(fsqtd); 1250 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1251 #endif 1252 1253 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1254 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1255 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1256 nstatus = le32toh(sqtd->qtd.qtd_status); 1257 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1258 BUS_DMASYNC_PREREAD); 1259 if (nstatus & EHCI_QTD_ACTIVE) 1260 break; 1261 1262 status = nstatus; 1263 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1264 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1265 } 1266 1267 /* 1268 * If there are left over TDs we need to update the toggle. 1269 * The default pipe doesn't need it since control transfers 1270 * start the toggle at 0 every time. 1271 * For a short transfer we need to update the toggle for the missing 1272 * packets within the qTD. 1273 */ 1274 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1275 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1276 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1277 status, nstatus, 0, 0); 1278 #if 0 1279 ehci_dump_sqh(epipe->sqh); 1280 ehci_dump_sqtds(ex->ex_sqtdstart); 1281 #endif 1282 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1283 } 1284 1285 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1286 status, 0); 1287 xfer->ux_actlen = actlen; 1288 if (status & EHCI_QTD_HALTED) { 1289 #ifdef EHCI_DEBUG 1290 DPRINTF("halted addr=%jd endpt=0x%02jx", 1291 xfer->ux_pipe->up_dev->ud_addr, 1292 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1293 0, 0); 1294 DPRINTF("cerr=%jd pid=%jd", 1295 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1296 0, 0); 1297 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1298 status & EHCI_QTD_ACTIVE ? 1 : 0, 1299 status & EHCI_QTD_HALTED ? 1 : 0, 1300 status & EHCI_QTD_BUFERR ? 1 : 0, 1301 status & EHCI_QTD_BABBLE ? 1 : 0); 1302 1303 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1304 status & EHCI_QTD_XACTERR ? 1 : 0, 1305 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1306 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1307 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1308 1309 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1310 ehci_dump_sqh(epipe->sqh); 1311 ehci_dump_sqtds(ex->ex_sqtdstart); 1312 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1313 #endif 1314 /* low&full speed has an extra error flag */ 1315 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1316 EHCI_QH_SPEED_HIGH) 1317 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1318 else 1319 status &= EHCI_QTD_STATERRS; 1320 if (status == 0) /* no other errors means a stall */ { 1321 xfer->ux_status = USBD_STALLED; 1322 } else { 1323 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1324 } 1325 /* XXX need to reset TT on missed microframe */ 1326 if (status & EHCI_QTD_MISSEDMICRO) { 1327 printf("%s: missed microframe, TT reset not " 1328 "implemented, hub might be inoperational\n", 1329 device_xname(sc->sc_dev)); 1330 } 1331 } else { 1332 xfer->ux_status = USBD_NORMAL_COMPLETION; 1333 } 1334 1335 end: 1336 1337 ehci_del_intr_list(sc, ex); 1338 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1339 1340 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1341 } 1342 1343 Static void 1344 ehci_poll(struct usbd_bus *bus) 1345 { 1346 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1347 1348 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1349 1350 #ifdef EHCI_DEBUG 1351 static int last; 1352 int new; 1353 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1354 if (new != last) { 1355 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1356 last = new; 1357 } 1358 #endif 1359 1360 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1361 mutex_spin_enter(&sc->sc_intr_lock); 1362 ehci_intr1(sc); 1363 mutex_spin_exit(&sc->sc_intr_lock); 1364 } 1365 } 1366 1367 void 1368 ehci_childdet(device_t self, device_t child) 1369 { 1370 struct ehci_softc *sc = device_private(self); 1371 1372 KASSERT(sc->sc_child == child); 1373 sc->sc_child = NULL; 1374 } 1375 1376 int 1377 ehci_detach(struct ehci_softc *sc, int flags) 1378 { 1379 int rv = 0; 1380 1381 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1382 1383 if (sc->sc_child != NULL) { 1384 rv = config_detach(sc->sc_child, flags); 1385 if (rv != 0) 1386 return rv; 1387 } 1388 1389 if (sc->sc_ncomp > 0) { 1390 mutex_enter(&sc->sc_complock); 1391 /* XXX try to halt callout instead of waiting */ 1392 while (sc->sc_comp_state == CO_SCHED) 1393 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1394 mutex_exit(&sc->sc_complock); 1395 1396 callout_halt(&sc->sc_compcallout, NULL); 1397 callout_destroy(&sc->sc_compcallout); 1398 cv_destroy(&sc->sc_compcv); 1399 mutex_destroy(&sc->sc_complock); 1400 } 1401 1402 callout_halt(&sc->sc_tmo_intrlist, NULL); 1403 callout_destroy(&sc->sc_tmo_intrlist); 1404 1405 /* XXX free other data structures */ 1406 if (sc->sc_softitds) { 1407 kmem_free(sc->sc_softitds, 1408 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1409 } 1410 cv_destroy(&sc->sc_doorbell); 1411 1412 #if 0 1413 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1414 softint_disestablish(sc->sc_doorbell_si); 1415 softint_disestablish(sc->sc_pcd_si); 1416 mutex_destroy(&sc->sc_rhlock); 1417 mutex_destroy(&sc->sc_lock); 1418 mutex_destroy(&sc->sc_intr_lock); 1419 #endif 1420 1421 pool_cache_destroy(sc->sc_xferpool); 1422 1423 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1424 1425 return rv; 1426 } 1427 1428 int 1429 ehci_activate(device_t self, enum devact act) 1430 { 1431 struct ehci_softc *sc = device_private(self); 1432 1433 switch (act) { 1434 case DVACT_DEACTIVATE: 1435 sc->sc_dying = 1; 1436 return 0; 1437 default: 1438 return EOPNOTSUPP; 1439 } 1440 } 1441 1442 /* 1443 * Handle suspend/resume. 1444 * 1445 * Note that this power handler isn't to be registered directly; the 1446 * bus glue needs to call out to it. 1447 */ 1448 bool 1449 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1450 { 1451 ehci_softc_t *sc = device_private(dv); 1452 int i; 1453 uint32_t cmd, hcr; 1454 1455 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1456 1457 mutex_enter(&sc->sc_rhlock); 1458 1459 for (i = 1; i <= sc->sc_noport; i++) { 1460 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1461 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1462 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1463 } 1464 1465 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1466 1467 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1468 EOWRITE4(sc, EHCI_USBCMD, cmd); 1469 1470 for (i = 0; i < 100; i++) { 1471 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1472 if (hcr == 0) 1473 break; 1474 1475 usb_delay_ms(&sc->sc_bus, 1); 1476 } 1477 if (hcr != 0) 1478 printf("%s: reset timeout\n", device_xname(dv)); 1479 1480 cmd &= ~EHCI_CMD_RS; 1481 EOWRITE4(sc, EHCI_USBCMD, cmd); 1482 1483 for (i = 0; i < 100; i++) { 1484 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1485 if (hcr == EHCI_STS_HCH) 1486 break; 1487 1488 usb_delay_ms(&sc->sc_bus, 1); 1489 } 1490 if (hcr != EHCI_STS_HCH) 1491 printf("%s: config timeout\n", device_xname(dv)); 1492 1493 mutex_exit(&sc->sc_rhlock); 1494 1495 return true; 1496 } 1497 1498 bool 1499 ehci_resume(device_t dv, const pmf_qual_t *qual) 1500 { 1501 ehci_softc_t *sc = device_private(dv); 1502 int i; 1503 uint32_t cmd, hcr; 1504 1505 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1506 1507 mutex_enter(&sc->sc_rhlock); 1508 1509 /* restore things in case the bios sucks */ 1510 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1511 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1512 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1513 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1514 1515 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1516 1517 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1518 1519 hcr = 0; 1520 for (i = 1; i <= sc->sc_noport; i++) { 1521 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1522 if ((cmd & EHCI_PS_PO) == 0 && 1523 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1524 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1525 hcr = 1; 1526 } 1527 } 1528 1529 if (hcr) { 1530 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1531 1532 for (i = 1; i <= sc->sc_noport; i++) { 1533 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1534 if ((cmd & EHCI_PS_PO) == 0 && 1535 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1536 EOWRITE4(sc, EHCI_PORTSC(i), 1537 cmd & ~EHCI_PS_FPR); 1538 } 1539 } 1540 1541 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1542 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1543 1544 for (i = 0; i < 100; i++) { 1545 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1546 if (hcr != EHCI_STS_HCH) 1547 break; 1548 1549 usb_delay_ms(&sc->sc_bus, 1); 1550 } 1551 if (hcr == EHCI_STS_HCH) 1552 printf("%s: config timeout\n", device_xname(dv)); 1553 1554 mutex_exit(&sc->sc_rhlock); 1555 1556 return true; 1557 } 1558 1559 /* 1560 * Shut down the controller when the system is going down. 1561 */ 1562 bool 1563 ehci_shutdown(device_t self, int flags) 1564 { 1565 ehci_softc_t *sc = device_private(self); 1566 1567 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1568 1569 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1570 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1571 return true; 1572 } 1573 1574 Static struct usbd_xfer * 1575 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1576 { 1577 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1578 struct usbd_xfer *xfer; 1579 1580 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1581 if (xfer != NULL) { 1582 memset(xfer, 0, sizeof(struct ehci_xfer)); 1583 1584 #ifdef DIAGNOSTIC 1585 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1586 ex->ex_isdone = true; 1587 xfer->ux_state = XFER_BUSY; 1588 #endif 1589 } 1590 return xfer; 1591 } 1592 1593 Static void 1594 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1595 { 1596 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1597 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1598 1599 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1600 xfer->ux_status == USBD_NOT_STARTED, 1601 "xfer %p state %d\n", xfer, xfer->ux_state); 1602 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1603 1604 #ifdef DIAGNOSTIC 1605 xfer->ux_state = XFER_FREE; 1606 #endif 1607 1608 pool_cache_put(sc->sc_xferpool, xfer); 1609 } 1610 1611 Static bool 1612 ehci_dying(struct usbd_bus *bus) 1613 { 1614 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1615 1616 return sc->sc_dying; 1617 } 1618 1619 Static void 1620 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1621 { 1622 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1623 1624 *lock = &sc->sc_lock; 1625 } 1626 1627 Static void 1628 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1629 { 1630 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1631 1632 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1633 1634 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1635 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1636 #ifdef EHCI_DEBUG 1637 if (ehcidebug) 1638 usbd_dump_pipe(pipe); 1639 #endif 1640 epipe->nexttoggle = 0; 1641 } 1642 1643 Static void 1644 ehci_noop(struct usbd_pipe *pipe) 1645 { 1646 } 1647 1648 #ifdef EHCI_DEBUG 1649 /* 1650 * Unused function - this is meant to be called from a kernel 1651 * debugger. 1652 */ 1653 void 1654 ehci_dump(void) 1655 { 1656 ehci_softc_t *sc = theehci; 1657 int i; 1658 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1659 EOREAD4(sc, EHCI_USBCMD), 1660 EOREAD4(sc, EHCI_USBSTS), 1661 EOREAD4(sc, EHCI_USBINTR)); 1662 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1663 EOREAD4(sc, EHCI_FRINDEX), 1664 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1665 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1666 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1667 for (i = 1; i <= sc->sc_noport; i++) 1668 printf("port %d status=0x%08x\n", i, 1669 EOREAD4(sc, EHCI_PORTSC(i))); 1670 } 1671 1672 Static void 1673 ehci_dump_regs(ehci_softc_t *sc) 1674 { 1675 int i; 1676 1677 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1678 1679 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1680 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1681 EOREAD4(sc, EHCI_USBINTR), 0); 1682 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1683 "async = 0x%08jx", 1684 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1685 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1686 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1687 for (i = 1; i <= sc->sc_noport; i += 2) { 1688 if (i == sc->sc_noport) { 1689 DPRINTF("port %jd status = 0x%08jx", i, 1690 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1691 } else { 1692 DPRINTF("port %jd status = 0x%08jx port %jd " 1693 "status = 0x%08jx", 1694 i, EOREAD4(sc, EHCI_PORTSC(i)), 1695 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1696 } 1697 } 1698 } 1699 1700 #define ehci_dump_link(link, type) do { \ 1701 DPRINTF(" link 0x%08jx (T = %jd):", \ 1702 link, \ 1703 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1704 if (type) { \ 1705 DPRINTF( \ 1706 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1707 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1708 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1709 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1710 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1711 } \ 1712 } while(0) 1713 1714 Static void 1715 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1716 { 1717 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1718 int i; 1719 uint32_t stop = 0; 1720 1721 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1722 ehci_dump_sqtd(sqtd); 1723 usb_syncmem(&sqtd->dma, 1724 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1725 sizeof(sqtd->qtd), 1726 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1727 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1728 usb_syncmem(&sqtd->dma, 1729 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1730 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1731 } 1732 if (!stop) 1733 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1734 } 1735 1736 Static void 1737 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1738 { 1739 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1740 1741 usb_syncmem(&sqtd->dma, sqtd->offs, 1742 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1743 1744 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1745 0, 0); 1746 ehci_dump_qtd(&sqtd->qtd); 1747 1748 usb_syncmem(&sqtd->dma, sqtd->offs, 1749 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1750 } 1751 1752 Static void 1753 ehci_dump_qtd(ehci_qtd_t *qtd) 1754 { 1755 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1756 uint32_t s = le32toh(qtd->qtd_status); 1757 1758 DPRINTFN(10, 1759 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1760 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1761 DPRINTFN(10, 1762 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1763 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1764 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1765 DPRINTFN(10, 1766 " cerr = %jd pid = %jd stat = %jx", 1767 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1768 0); 1769 DPRINTFN(10, 1770 "active =%jd halted=%jd buferr=%jd babble=%jd", 1771 s & EHCI_QTD_ACTIVE ? 1 : 0, 1772 s & EHCI_QTD_HALTED ? 1 : 0, 1773 s & EHCI_QTD_BUFERR ? 1 : 0, 1774 s & EHCI_QTD_BABBLE ? 1 : 0); 1775 DPRINTFN(10, 1776 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1777 s & EHCI_QTD_XACTERR ? 1 : 0, 1778 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1779 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1780 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1781 DPRINTFN(10, 1782 "buffer[0] = %#jx buffer[1] = %#jx " 1783 "buffer[2] = %#jx buffer[3] = %#jx", 1784 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1785 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1786 DPRINTFN(10, 1787 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1788 } 1789 1790 Static void 1791 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1792 { 1793 ehci_qh_t *qh = &sqh->qh; 1794 ehci_link_t link; 1795 uint32_t endp, endphub; 1796 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1797 1798 usb_syncmem(&sqh->dma, sqh->offs, 1799 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1800 1801 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1802 link = le32toh(qh->qh_link); 1803 ehci_dump_link(link, true); 1804 1805 endp = le32toh(qh->qh_endp); 1806 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1807 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1808 "eps = %jd", 1809 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1810 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1811 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1812 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1813 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1814 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1815 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1816 1817 endphub = le32toh(qh->qh_endphub); 1818 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1819 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1820 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1821 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1822 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1823 EHCI_QH_GET_MULT(endphub), 0); 1824 1825 link = le32toh(qh->qh_curqtd); 1826 ehci_dump_link(link, false); 1827 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1828 ehci_dump_qtd(&qh->qh_qtd); 1829 1830 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1831 BUS_DMASYNC_PREREAD); 1832 } 1833 1834 Static void 1835 ehci_dump_itds(ehci_soft_itd_t *itd) 1836 { 1837 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1838 int i; 1839 uint32_t stop = 0; 1840 1841 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1842 ehci_dump_itd(itd); 1843 usb_syncmem(&itd->dma, 1844 itd->offs + offsetof(ehci_itd_t, itd_next), 1845 sizeof(itd->itd), 1846 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1847 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1848 usb_syncmem(&itd->dma, 1849 itd->offs + offsetof(ehci_itd_t, itd_next), 1850 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1851 } 1852 if (!stop) 1853 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1854 } 1855 1856 Static void 1857 ehci_dump_itd(struct ehci_soft_itd *itd) 1858 { 1859 ehci_isoc_trans_t t; 1860 ehci_isoc_bufr_ptr_t b, b2, b3; 1861 int i; 1862 1863 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1864 1865 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1866 1867 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1868 t = le32toh(itd->itd.itd_ctl[i]); 1869 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1870 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1871 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1872 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1873 EHCI_ITD_GET_OFFS(t), 0); 1874 } 1875 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1876 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1877 DPRINTF(" %jx", 1878 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1879 1880 b = le32toh(itd->itd.itd_bufr[0]); 1881 b2 = le32toh(itd->itd.itd_bufr[1]); 1882 b3 = le32toh(itd->itd.itd_bufr[2]); 1883 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1884 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1885 DPRINTF(" maxpkt = %jx multi = %jx", 1886 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1887 } 1888 1889 Static void 1890 ehci_dump_sitd(struct ehci_soft_itd *itd) 1891 { 1892 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1893 1894 DPRINTF("SITD %#jx next = %p prev = %#jx", 1895 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1896 (uintptr_t)itd->frame_list.prev, 0); 1897 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1898 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1899 } 1900 1901 Static void 1902 ehci_dump_exfer(struct ehci_xfer *ex) 1903 { 1904 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1905 1906 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1907 ex->ex_isdone, 0); 1908 1909 switch (ex->ex_type) { 1910 case EX_CTRL: 1911 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1912 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1913 (uintptr_t)ex->ex_status, 0); 1914 break; 1915 case EX_BULK: 1916 case EX_INTR: 1917 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1918 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1919 0, 0); 1920 break; 1921 case EX_ISOC: 1922 DPRINTF(" itdstart = %#jx itdend = %#jx", 1923 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1924 break; 1925 case EX_FS_ISOC: 1926 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1927 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1928 0, 0); 1929 break; 1930 default: 1931 DPRINTF(" unknown type", 0, 0, 0, 0); 1932 } 1933 } 1934 #endif 1935 1936 Static usbd_status 1937 ehci_open(struct usbd_pipe *pipe) 1938 { 1939 struct usbd_device *dev = pipe->up_dev; 1940 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1941 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1942 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1943 uint8_t addr = dev->ud_addr; 1944 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1945 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1946 ehci_soft_qh_t *sqh; 1947 usbd_status err; 1948 int ival, speed, naks; 1949 int hshubaddr, hshubport; 1950 1951 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1952 1953 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1954 ed->bEndpointAddress, rhaddr); 1955 1956 if (dev->ud_myhsport) { 1957 /* 1958 * When directly attached FS/LS device while doing embedded 1959 * transaction translations and we are the hub, set the hub 1960 * address to 0 (us). 1961 */ 1962 if (!(sc->sc_flags & EHCIF_ETTF) 1963 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1964 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1965 } else { 1966 hshubaddr = 0; 1967 } 1968 hshubport = dev->ud_myhsport->up_portno; 1969 } else { 1970 hshubaddr = 0; 1971 hshubport = 0; 1972 } 1973 1974 if (sc->sc_dying) 1975 return USBD_IOERROR; 1976 1977 /* toggle state needed for bulk endpoints */ 1978 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1979 1980 if (addr == rhaddr) { 1981 switch (ed->bEndpointAddress) { 1982 case USB_CONTROL_ENDPOINT: 1983 pipe->up_methods = &roothub_ctrl_methods; 1984 break; 1985 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1986 pipe->up_methods = &ehci_root_intr_methods; 1987 break; 1988 default: 1989 DPRINTF("bad bEndpointAddress 0x%02jx", 1990 ed->bEndpointAddress, 0, 0, 0); 1991 return USBD_INVAL; 1992 } 1993 return USBD_NORMAL_COMPLETION; 1994 } 1995 1996 /* XXX All this stuff is only valid for async. */ 1997 switch (dev->ud_speed) { 1998 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1999 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 2000 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 2001 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 2002 } 2003 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 2004 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 2005 0); 2006 return USBD_INVAL; 2007 } 2008 2009 /* 2010 * For interrupt transfer, nak throttling must be disabled, but for 2011 * the other transfer type, nak throttling should be enabled from the 2012 * viewpoint that avoids the memory thrashing. 2013 */ 2014 naks = (xfertype == UE_INTERRUPT) ? 0 2015 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 2016 2017 /* Allocate sqh for everything, save isoc xfers */ 2018 if (xfertype != UE_ISOCHRONOUS) { 2019 sqh = ehci_alloc_sqh(sc); 2020 if (sqh == NULL) 2021 return USBD_NOMEM; 2022 /* qh_link filled when the QH is added */ 2023 sqh->qh.qh_endp = htole32( 2024 EHCI_QH_SET_ADDR(addr) | 2025 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 2026 EHCI_QH_SET_EPS(speed) | 2027 EHCI_QH_DTC | 2028 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 2029 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 2030 EHCI_QH_CTL : 0) | 2031 EHCI_QH_SET_NRL(naks) 2032 ); 2033 sqh->qh.qh_endphub = htole32( 2034 EHCI_QH_SET_MULT(1) | 2035 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 2036 ); 2037 if (speed != EHCI_QH_SPEED_HIGH) 2038 sqh->qh.qh_endphub |= htole32( 2039 EHCI_QH_SET_PORT(hshubport) | 2040 EHCI_QH_SET_HUBA(hshubaddr) | 2041 (xfertype == UE_INTERRUPT ? 2042 EHCI_QH_SET_CMASK(0x08) : 0) 2043 ); 2044 sqh->qh.qh_curqtd = EHCI_NULL; 2045 /* Fill the overlay qTD */ 2046 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2047 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2048 sqh->qh.qh_qtd.qtd_status = htole32(0); 2049 2050 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2051 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2052 epipe->sqh = sqh; 2053 } else { 2054 sqh = NULL; 2055 } /*xfertype == UE_ISOC*/ 2056 2057 switch (xfertype) { 2058 case UE_CONTROL: 2059 /* we can use 64bit DMA for the reqdma buffer */ 2060 err = usb_allocmem(sc->sc_bus.ub_dmatag, 2061 sizeof(usb_device_request_t), 0, USBMALLOC_COHERENT, 2062 &epipe->ctrl.reqdma); 2063 #ifdef EHCI_DEBUG 2064 if (err) 2065 printf("ehci_open: usb_allocmem()=%d\n", err); 2066 #endif 2067 if (err) 2068 goto bad; 2069 pipe->up_methods = &ehci_device_ctrl_methods; 2070 mutex_enter(&sc->sc_lock); 2071 ehci_add_qh(sc, sqh, sc->sc_async_head); 2072 mutex_exit(&sc->sc_lock); 2073 break; 2074 case UE_BULK: 2075 pipe->up_methods = &ehci_device_bulk_methods; 2076 mutex_enter(&sc->sc_lock); 2077 ehci_add_qh(sc, sqh, sc->sc_async_head); 2078 mutex_exit(&sc->sc_lock); 2079 break; 2080 case UE_INTERRUPT: 2081 pipe->up_methods = &ehci_device_intr_methods; 2082 ival = pipe->up_interval; 2083 if (ival == USBD_DEFAULT_INTERVAL) { 2084 if (speed == EHCI_QH_SPEED_HIGH) { 2085 if (ed->bInterval > 16) { 2086 /* 2087 * illegal with high-speed, but there 2088 * were documentation bugs in the spec, 2089 * so be generous 2090 */ 2091 ival = 256; 2092 } else 2093 ival = (1 << (ed->bInterval - 1)) / 8; 2094 } else 2095 ival = ed->bInterval; 2096 } 2097 err = ehci_device_setintr(sc, sqh, ival); 2098 if (err) 2099 goto bad; 2100 break; 2101 case UE_ISOCHRONOUS: 2102 pipe->up_serialise = false; 2103 if (speed == EHCI_QH_SPEED_HIGH) 2104 pipe->up_methods = &ehci_device_isoc_methods; 2105 else 2106 pipe->up_methods = &ehci_device_fs_isoc_methods; 2107 if (ed->bInterval == 0 || ed->bInterval > 16) { 2108 printf("ehci: opening pipe with invalid bInterval\n"); 2109 err = USBD_INVAL; 2110 goto bad; 2111 } 2112 if (UGETW(ed->wMaxPacketSize) == 0) { 2113 printf("ehci: zero length endpoint open request\n"); 2114 err = USBD_INVAL; 2115 goto bad; 2116 } 2117 epipe->isoc.next_frame = 0; 2118 epipe->isoc.cur_xfers = 0; 2119 break; 2120 default: 2121 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2122 err = USBD_INVAL; 2123 goto bad; 2124 } 2125 return USBD_NORMAL_COMPLETION; 2126 2127 bad: 2128 if (sqh != NULL) { 2129 mutex_enter(&sc->sc_lock); 2130 ehci_free_sqh(sc, sqh); 2131 mutex_exit(&sc->sc_lock); 2132 } 2133 return err; 2134 } 2135 2136 /* 2137 * Add an ED to the schedule. Called with USB lock held. 2138 */ 2139 Static void 2140 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2141 { 2142 2143 KASSERT(mutex_owned(&sc->sc_lock)); 2144 2145 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2146 2147 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2148 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2149 2150 sqh->next = head->next; 2151 sqh->qh.qh_link = head->qh.qh_link; 2152 2153 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2154 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2155 2156 head->next = sqh; 2157 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2158 2159 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2160 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2161 2162 #ifdef EHCI_DEBUG 2163 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2164 ehci_dump_sqh(sqh); 2165 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2166 #endif 2167 } 2168 2169 /* 2170 * Remove an ED from the schedule. Called with USB lock held. 2171 */ 2172 Static void 2173 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2174 { 2175 ehci_soft_qh_t *p; 2176 2177 KASSERT(mutex_owned(&sc->sc_lock)); 2178 2179 /* XXX */ 2180 for (p = head; p != NULL && p->next != sqh; p = p->next) 2181 ; 2182 if (p == NULL) 2183 panic("ehci_rem_qh: ED not found"); 2184 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2185 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2186 p->next = sqh->next; 2187 p->qh.qh_link = sqh->qh.qh_link; 2188 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2189 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2190 2191 ehci_sync_hc(sc); 2192 } 2193 2194 Static void 2195 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2196 { 2197 int i; 2198 uint32_t status; 2199 2200 /* Save toggle bit and ping status. */ 2201 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2202 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2203 status = sqh->qh.qh_qtd.qtd_status & 2204 htole32(EHCI_QTD_TOGGLE_MASK | 2205 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2206 /* Set HALTED to make hw leave it alone. */ 2207 sqh->qh.qh_qtd.qtd_status = 2208 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2209 usb_syncmem(&sqh->dma, 2210 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2211 sizeof(sqh->qh.qh_qtd.qtd_status), 2212 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2213 sqh->qh.qh_curqtd = 0; 2214 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2215 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2216 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2217 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2218 sqh->sqtd = sqtd; 2219 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2221 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2222 sqh->qh.qh_qtd.qtd_status = status; 2223 usb_syncmem(&sqh->dma, 2224 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2225 sizeof(sqh->qh.qh_qtd.qtd_status), 2226 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2227 } 2228 2229 /* 2230 * Ensure that the HC has released all references to the QH. We do this 2231 * by asking for a Async Advance Doorbell interrupt and then we wait for 2232 * the interrupt. 2233 * To make this easier we first obtain exclusive use of the doorbell. 2234 * 2235 * Releases the bus lock to sleep while waiting for interrupt. 2236 */ 2237 Static void 2238 ehci_sync_hc(ehci_softc_t *sc) 2239 { 2240 unsigned delta = hz; 2241 unsigned starttime = getticks(); 2242 unsigned endtime = starttime + delta; 2243 unsigned now; 2244 2245 KASSERT(mutex_owned(&sc->sc_lock)); 2246 2247 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2248 2249 if (sc->sc_dying) { 2250 DPRINTF("dying", 0, 0, 0, 0); 2251 return; 2252 } 2253 2254 /* 2255 * Wait until any concurrent ehci_sync_hc has completed so we 2256 * have exclusive access to the doorbell. 2257 */ 2258 while (sc->sc_doorbelllwp) 2259 cv_wait(&sc->sc_doorbell, &sc->sc_lock); 2260 sc->sc_doorbelllwp = curlwp; 2261 2262 /* ask for doorbell */ 2263 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2264 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2265 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2266 2267 /* 2268 * Wait for the ehci to ring our doorbell. 2269 */ 2270 while (sc->sc_doorbelllwp == curlwp) { 2271 now = getticks(); 2272 if (endtime - now > delta) { 2273 sc->sc_doorbelllwp = NULL; 2274 cv_signal(&sc->sc_doorbell); 2275 DPRINTF("doorbell timeout", 0, 0, 0, 0); 2276 #ifdef DIAGNOSTIC /* XXX DIAGNOSTIC abuse, do this differently */ 2277 printf("ehci_sync_hc: timed out\n"); 2278 #endif 2279 break; 2280 } 2281 (void)cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, 2282 endtime - now); 2283 } 2284 2285 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2286 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2287 } 2288 2289 Static void 2290 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2291 { 2292 2293 KASSERT(mutex_owned(&sc->sc_lock)); 2294 2295 for (; itd != NULL; itd = itd->xfer_next) { 2296 struct ehci_soft_itd *prev = itd->frame_list.prev; 2297 2298 /* Unlink itd from hardware chain, or frame array */ 2299 if (prev == NULL) { /* We're at the table head */ 2300 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2301 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2302 usb_syncmem(&sc->sc_fldma, 2303 sizeof(ehci_link_t) * itd->slot, 2304 sizeof(ehci_link_t), 2305 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2306 2307 if (itd->frame_list.next != NULL) 2308 itd->frame_list.next->frame_list.prev = NULL; 2309 } else { 2310 /* XXX this part is untested... */ 2311 prev->itd.itd_next = itd->itd.itd_next; 2312 usb_syncmem(&itd->dma, 2313 itd->offs + offsetof(ehci_itd_t, itd_next), 2314 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2315 2316 prev->frame_list.next = itd->frame_list.next; 2317 if (itd->frame_list.next != NULL) 2318 itd->frame_list.next->frame_list.prev = prev; 2319 } 2320 } 2321 } 2322 2323 Static void 2324 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2325 { 2326 struct ehci_soft_itd *next; 2327 2328 mutex_enter(&sc->sc_lock); 2329 next = NULL; 2330 for (; itd != NULL; itd = next) { 2331 next = itd->xfer_next; 2332 ehci_free_itd_locked(sc, itd); 2333 } 2334 mutex_exit(&sc->sc_lock); 2335 } 2336 2337 Static void 2338 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2339 { 2340 2341 KASSERT(mutex_owned(&sc->sc_lock)); 2342 2343 for (; sitd != NULL; sitd = sitd->xfer_next) { 2344 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2345 2346 /* Unlink sitd from hardware chain, or frame array */ 2347 if (prev == NULL) { /* We're at the table head */ 2348 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2349 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2350 usb_syncmem(&sc->sc_fldma, 2351 sizeof(ehci_link_t) * sitd->slot, 2352 sizeof(ehci_link_t), 2353 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2354 2355 if (sitd->frame_list.next != NULL) 2356 sitd->frame_list.next->frame_list.prev = NULL; 2357 } else { 2358 /* XXX this part is untested... */ 2359 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2360 usb_syncmem(&sitd->dma, 2361 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2362 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2363 2364 prev->frame_list.next = sitd->frame_list.next; 2365 if (sitd->frame_list.next != NULL) 2366 sitd->frame_list.next->frame_list.prev = prev; 2367 } 2368 } 2369 } 2370 2371 Static void 2372 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2373 { 2374 2375 mutex_enter(&sc->sc_lock); 2376 struct ehci_soft_sitd *next = NULL; 2377 for (; sitd != NULL; sitd = next) { 2378 next = sitd->xfer_next; 2379 ehci_free_sitd_locked(sc, sitd); 2380 } 2381 mutex_exit(&sc->sc_lock); 2382 } 2383 2384 /***********/ 2385 2386 static int 2387 ehci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req, 2388 void *buf, int buflen) 2389 { 2390 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2391 usb_hub_descriptor_t hubd; 2392 usb_port_status_t ps; 2393 uint16_t len, value, index; 2394 int l, totlen = 0; 2395 int port, i; 2396 uint32_t v; 2397 2398 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2399 2400 KASSERT(mutex_owned(&sc->sc_rhlock)); 2401 2402 if (sc->sc_dying) 2403 return -1; 2404 2405 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2406 0, 0); 2407 2408 len = UGETW(req->wLength); 2409 value = UGETW(req->wValue); 2410 index = UGETW(req->wIndex); 2411 2412 #define C(x,y) ((x) | ((y) << 8)) 2413 switch (C(req->bRequest, req->bmRequestType)) { 2414 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2415 if (len == 0) 2416 break; 2417 switch (value) { 2418 #define sd ((usb_string_descriptor_t *)buf) 2419 case C(2, UDESC_STRING): 2420 /* Product */ 2421 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2422 break; 2423 #undef sd 2424 default: 2425 /* default from usbroothub */ 2426 return buflen; 2427 } 2428 break; 2429 2430 /* Hub requests */ 2431 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2432 break; 2433 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2434 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2435 value, 0, 0); 2436 if (index < 1 || index > sc->sc_noport) { 2437 return -1; 2438 } 2439 port = EHCI_PORTSC(index); 2440 v = EOREAD4(sc, port); 2441 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2442 v &= ~EHCI_PS_CLEAR; 2443 switch (value) { 2444 case UHF_PORT_ENABLE: 2445 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2446 break; 2447 case UHF_PORT_SUSPEND: 2448 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2449 break; 2450 v &= ~EHCI_PS_SUSP; 2451 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2452 /* see USB2 spec ch. 7.1.7.7 */ 2453 usb_delay_ms(&sc->sc_bus, 20); 2454 EOWRITE4(sc, port, v); 2455 usb_delay_ms(&sc->sc_bus, 2); 2456 #ifdef DEBUG 2457 v = EOREAD4(sc, port); 2458 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2459 printf("ehci: resume failed: %x\n", v); 2460 #endif 2461 break; 2462 case UHF_PORT_POWER: 2463 if (sc->sc_hasppc) 2464 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2465 break; 2466 case UHF_PORT_TEST: 2467 DPRINTF("clear port test %jd", index, 0, 0, 0); 2468 break; 2469 case UHF_PORT_INDICATOR: 2470 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2471 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2472 break; 2473 case UHF_C_PORT_CONNECTION: 2474 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2475 break; 2476 case UHF_C_PORT_ENABLE: 2477 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2478 break; 2479 case UHF_C_PORT_SUSPEND: 2480 /* how? */ 2481 break; 2482 case UHF_C_PORT_OVER_CURRENT: 2483 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2484 break; 2485 case UHF_C_PORT_RESET: 2486 sc->sc_isreset[index] = 0; 2487 break; 2488 default: 2489 return -1; 2490 } 2491 #if 0 2492 switch(value) { 2493 case UHF_C_PORT_CONNECTION: 2494 case UHF_C_PORT_ENABLE: 2495 case UHF_C_PORT_SUSPEND: 2496 case UHF_C_PORT_OVER_CURRENT: 2497 case UHF_C_PORT_RESET: 2498 default: 2499 break; 2500 } 2501 #endif 2502 break; 2503 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2504 if (len == 0) 2505 break; 2506 if ((value & 0xff) != 0) { 2507 return -1; 2508 } 2509 totlen = uimin(buflen, sizeof(hubd)); 2510 memcpy(&hubd, buf, totlen); 2511 hubd.bNbrPorts = sc->sc_noport; 2512 v = EREAD4(sc, EHCI_HCSPARAMS); 2513 USETW(hubd.wHubCharacteristics, 2514 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2515 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2516 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2517 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2518 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2519 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2520 totlen = uimin(totlen, hubd.bDescLength); 2521 memcpy(buf, &hubd, totlen); 2522 break; 2523 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2524 if (len != 4) { 2525 return -1; 2526 } 2527 memset(buf, 0, len); /* ? XXX */ 2528 totlen = len; 2529 break; 2530 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2531 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2532 if (index < 1 || index > sc->sc_noport) { 2533 return -1; 2534 } 2535 if (len != 4) { 2536 return -1; 2537 } 2538 v = EOREAD4(sc, EHCI_PORTSC(index)); 2539 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2540 2541 i = UPS_HIGH_SPEED; 2542 if (sc->sc_flags & EHCIF_ETTF) { 2543 /* 2544 * If we are doing embedded transaction translation, 2545 * then directly attached LS/FS devices are reset by 2546 * the EHCI controller itself. PSPD is encoded 2547 * the same way as in USBSTATUS. 2548 */ 2549 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2550 } 2551 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2552 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2553 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2554 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2555 if (v & EHCI_PS_PR) i |= UPS_RESET; 2556 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2557 if (sc->sc_vendor_port_status) 2558 i = sc->sc_vendor_port_status(sc, v, i); 2559 USETW(ps.wPortStatus, i); 2560 i = 0; 2561 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2562 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2563 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2564 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2565 USETW(ps.wPortChange, i); 2566 totlen = uimin(len, sizeof(ps)); 2567 memcpy(buf, &ps, totlen); 2568 break; 2569 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2570 return -1; 2571 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2572 break; 2573 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2574 if (index < 1 || index > sc->sc_noport) { 2575 return -1; 2576 } 2577 port = EHCI_PORTSC(index); 2578 v = EOREAD4(sc, port); 2579 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2580 v &= ~EHCI_PS_CLEAR; 2581 switch(value) { 2582 case UHF_PORT_ENABLE: 2583 EOWRITE4(sc, port, v | EHCI_PS_PE); 2584 break; 2585 case UHF_PORT_SUSPEND: 2586 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2587 break; 2588 case UHF_PORT_RESET: 2589 DPRINTF("reset port %jd", index, 0, 0, 0); 2590 if (EHCI_PS_IS_LOWSPEED(v) 2591 && sc->sc_ncomp > 0 2592 && !(sc->sc_flags & EHCIF_ETTF)) { 2593 /* 2594 * Low speed device on non-ETTF controller or 2595 * unaccompanied controller, give up ownership. 2596 */ 2597 ehci_disown(sc, index, 1); 2598 break; 2599 } 2600 /* Start reset sequence. */ 2601 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2602 EOWRITE4(sc, port, v | EHCI_PS_PR); 2603 /* Wait for reset to complete. */ 2604 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2605 if (sc->sc_dying) { 2606 return -1; 2607 } 2608 /* 2609 * An embedded transaction translator will automatically 2610 * terminate the reset sequence so there's no need to 2611 * it. 2612 */ 2613 v = EOREAD4(sc, port); 2614 if (v & EHCI_PS_PR) { 2615 /* Terminate reset sequence. */ 2616 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2617 /* Wait for HC to complete reset. */ 2618 usb_delay_ms(&sc->sc_bus, 2619 EHCI_PORT_RESET_COMPLETE); 2620 if (sc->sc_dying) { 2621 return -1; 2622 } 2623 } 2624 2625 v = EOREAD4(sc, port); 2626 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2627 if (v & EHCI_PS_PR) { 2628 printf("%s: port reset timeout\n", 2629 device_xname(sc->sc_dev)); 2630 return USBD_TIMEOUT; 2631 } 2632 if (!(v & EHCI_PS_PE)) { 2633 /* Not a high speed device, give up ownership.*/ 2634 ehci_disown(sc, index, 0); 2635 break; 2636 } 2637 sc->sc_isreset[index] = 1; 2638 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2639 v, 0, 0); 2640 break; 2641 case UHF_PORT_POWER: 2642 DPRINTF("set port power %jd (has PPC = %jd)", index, 2643 sc->sc_hasppc, 0, 0); 2644 if (sc->sc_hasppc) 2645 EOWRITE4(sc, port, v | EHCI_PS_PP); 2646 break; 2647 case UHF_PORT_TEST: 2648 DPRINTF("set port test %jd", index, 0, 0, 0); 2649 break; 2650 case UHF_PORT_INDICATOR: 2651 DPRINTF("set port ind %jd", index, 0, 0, 0); 2652 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2653 break; 2654 default: 2655 return -1; 2656 } 2657 break; 2658 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2659 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2660 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2661 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2662 break; 2663 default: 2664 /* default from usbroothub */ 2665 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2666 2667 return buflen; 2668 } 2669 2670 DPRINTF("returning %jd", totlen, 0, 0, 0); 2671 2672 return totlen; 2673 } 2674 2675 Static int 2676 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2677 void *buf, int buflen) 2678 { 2679 struct ehci_softc *sc = EHCI_BUS2SC(bus); 2680 int actlen; 2681 2682 mutex_enter(&sc->sc_rhlock); 2683 actlen = ehci_roothub_ctrl_locked(bus, req, buf, buflen); 2684 mutex_exit(&sc->sc_rhlock); 2685 2686 return actlen; 2687 } 2688 2689 /* 2690 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2691 * 2692 * This pile of garbage below works around the following problem without 2693 * holding boots with no hand-over devices present, while penalising 2694 * boots where the first ehci probe hands off devices with a 5 second 2695 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2696 * for RB_SINGLE, but the same basic issue exists. 2697 * 2698 * The way ehci hand-off works, the companion controller does not get the 2699 * device until after its initial bus explore, so the reference dropped 2700 * after the first explore is not enough. 5 seconds should be enough, 2701 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2702 * 2703 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2704 * if the callback is scheduled. CO_DONE is set when the callout has 2705 * called config_pending_decr(). 2706 * 2707 * There's a mutex, a cv and a callout here, and we delay detach if the 2708 * callout has been set. 2709 */ 2710 #ifndef EHCI_DISOWN_DELAY_SECONDS 2711 #define EHCI_DISOWN_DELAY_SECONDS 5 2712 #endif 2713 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2714 2715 static void 2716 ehci_disown_callback(void *arg) 2717 { 2718 ehci_softc_t *sc = arg; 2719 2720 config_pending_decr(sc->sc_dev); 2721 2722 mutex_enter(&sc->sc_complock); 2723 KASSERT(sc->sc_comp_state == CO_SCHED); 2724 sc->sc_comp_state = CO_DONE; 2725 cv_signal(&sc->sc_compcv); 2726 mutex_exit(&sc->sc_complock); 2727 } 2728 2729 static void 2730 ehci_disown_sched_callback(ehci_softc_t *sc) 2731 { 2732 extern bool root_is_mounted; 2733 2734 mutex_enter(&sc->sc_complock); 2735 2736 if (root_is_mounted || 2737 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2738 sc->sc_comp_state != CO_EARLY) { 2739 mutex_exit(&sc->sc_complock); 2740 return; 2741 } 2742 2743 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2744 ehci_disown_callback, &sc->sc_dev); 2745 sc->sc_comp_state = CO_SCHED; 2746 2747 mutex_exit(&sc->sc_complock); 2748 2749 config_pending_incr(sc->sc_dev); 2750 aprint_normal_dev(sc->sc_dev, 2751 "delaying %s by %u seconds due to USB owner change.\n", 2752 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user", 2753 ehci_disown_delay_seconds); 2754 } 2755 2756 Static void 2757 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2758 { 2759 int port; 2760 uint32_t v; 2761 2762 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2763 2764 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2765 if (sc->sc_npcomp != 0) { 2766 int i = (index-1) / sc->sc_npcomp; 2767 if (i < sc->sc_ncomp) { 2768 ehci_disown_sched_callback(sc); 2769 #ifdef DIAGNOSTIC 2770 printf("%s: handing over %s speed device on " 2771 "port %d to %s\n", 2772 device_xname(sc->sc_dev), 2773 lowspeed ? "low" : "full", 2774 index, sc->sc_comps[i] ? 2775 device_xname(sc->sc_comps[i]) : 2776 "companion controller"); 2777 } else { 2778 printf("%s: strange port\n", 2779 device_xname(sc->sc_dev)); 2780 #endif 2781 } 2782 } else { 2783 #ifdef DIAGNOSTIC 2784 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2785 #endif 2786 } 2787 port = EHCI_PORTSC(index); 2788 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2789 EOWRITE4(sc, port, v | EHCI_PS_PO); 2790 } 2791 2792 Static usbd_status 2793 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2794 { 2795 2796 /* Pipe isn't running, start first */ 2797 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2798 } 2799 2800 Static usbd_status 2801 ehci_root_intr_start(struct usbd_xfer *xfer) 2802 { 2803 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2804 2805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2806 2807 if (sc->sc_dying) 2808 return USBD_IOERROR; 2809 2810 KASSERT(sc->sc_intrxfer == NULL); 2811 sc->sc_intrxfer = xfer; 2812 xfer->ux_status = USBD_IN_PROGRESS; 2813 2814 return USBD_IN_PROGRESS; 2815 } 2816 2817 /* Abort a root interrupt request. */ 2818 Static void 2819 ehci_root_intr_abort(struct usbd_xfer *xfer) 2820 { 2821 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2822 2823 KASSERT(mutex_owned(&sc->sc_lock)); 2824 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2825 2826 /* If xfer has already completed, nothing to do here. */ 2827 if (sc->sc_intrxfer == NULL) 2828 return; 2829 2830 /* 2831 * Otherwise, sc->sc_intrxfer had better be this transfer. 2832 * Cancel it. 2833 */ 2834 KASSERT(sc->sc_intrxfer == xfer); 2835 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2836 xfer->ux_status = USBD_CANCELLED; 2837 usb_transfer_complete(xfer); 2838 } 2839 2840 /* Close the root pipe. */ 2841 Static void 2842 ehci_root_intr_close(struct usbd_pipe *pipe) 2843 { 2844 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2845 2846 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2847 2848 KASSERT(mutex_owned(&sc->sc_lock)); 2849 2850 /* 2851 * Caller must guarantee the xfer has completed first, by 2852 * closing the pipe only after normal completion or an abort. 2853 */ 2854 KASSERT(sc->sc_intrxfer == NULL); 2855 } 2856 2857 Static void 2858 ehci_root_intr_done(struct usbd_xfer *xfer) 2859 { 2860 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2861 2862 KASSERT(mutex_owned(&sc->sc_lock)); 2863 2864 /* Claim the xfer so it doesn't get completed again. */ 2865 KASSERT(sc->sc_intrxfer == xfer); 2866 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2867 sc->sc_intrxfer = NULL; 2868 } 2869 2870 /************************/ 2871 2872 Static ehci_soft_qh_t * 2873 ehci_alloc_sqh(ehci_softc_t *sc) 2874 { 2875 ehci_soft_qh_t *sqh; 2876 2877 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2878 2879 mutex_enter(&sc->sc_lock); 2880 if (sc->sc_freeqhs == NULL) { 2881 DPRINTF("allocating chunk", 0, 0, 0, 0); 2882 mutex_exit(&sc->sc_lock); 2883 2884 usb_dma_t dma; 2885 int err = usb_allocmem(sc->sc_dmatag, 2886 EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2887 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2888 2889 if (err) { 2890 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2891 return NULL; 2892 } 2893 2894 mutex_enter(&sc->sc_lock); 2895 for (size_t i = 0; i < EHCI_SQH_CHUNK; i++) { 2896 const int offs = i * EHCI_SQH_SIZE; 2897 const bus_addr_t baddr = DMAADDR(&dma, offs); 2898 2899 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2900 2901 sqh = KERNADDR(&dma, offs); 2902 sqh->physaddr = BUS_ADDR_LO32(baddr); 2903 sqh->dma = dma; 2904 sqh->offs = offs; 2905 2906 sqh->next = sc->sc_freeqhs; 2907 sc->sc_freeqhs = sqh; 2908 } 2909 } 2910 sqh = sc->sc_freeqhs; 2911 sc->sc_freeqhs = sqh->next; 2912 mutex_exit(&sc->sc_lock); 2913 2914 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2915 sqh->next = NULL; 2916 return sqh; 2917 } 2918 2919 Static void 2920 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2921 { 2922 KASSERT(mutex_owned(&sc->sc_lock)); 2923 2924 sqh->next = sc->sc_freeqhs; 2925 sc->sc_freeqhs = sqh; 2926 } 2927 2928 Static ehci_soft_qtd_t * 2929 ehci_alloc_sqtd(ehci_softc_t *sc) 2930 { 2931 ehci_soft_qtd_t *sqtd = NULL; 2932 2933 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2934 2935 mutex_enter(&sc->sc_lock); 2936 if (sc->sc_freeqtds == NULL) { 2937 DPRINTF("allocating chunk", 0, 0, 0, 0); 2938 mutex_exit(&sc->sc_lock); 2939 2940 usb_dma_t dma; 2941 int err = usb_allocmem(sc->sc_dmatag, 2942 EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK, 2943 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2944 2945 if (err) { 2946 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2947 return NULL; 2948 } 2949 2950 mutex_enter(&sc->sc_lock); 2951 for (size_t i = 0; i < EHCI_SQTD_CHUNK; i++) { 2952 const int offs = i * EHCI_SQTD_SIZE; 2953 const bus_addr_t baddr = DMAADDR(&dma, offs); 2954 2955 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2956 2957 sqtd = KERNADDR(&dma, offs); 2958 sqtd->physaddr = BUS_ADDR_LO32(baddr); 2959 sqtd->dma = dma; 2960 sqtd->offs = offs; 2961 2962 sqtd->nextqtd = sc->sc_freeqtds; 2963 sc->sc_freeqtds = sqtd; 2964 } 2965 } 2966 2967 sqtd = sc->sc_freeqtds; 2968 sc->sc_freeqtds = sqtd->nextqtd; 2969 mutex_exit(&sc->sc_lock); 2970 2971 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2972 sqtd->nextqtd = NULL; 2973 sqtd->xfer = NULL; 2974 2975 return sqtd; 2976 } 2977 2978 Static void 2979 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2980 { 2981 2982 mutex_enter(&sc->sc_lock); 2983 sqtd->nextqtd = sc->sc_freeqtds; 2984 sc->sc_freeqtds = sqtd; 2985 mutex_exit(&sc->sc_lock); 2986 } 2987 2988 Static int 2989 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2990 int alen, int rd, ehci_soft_qtd_t **sp) 2991 { 2992 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2993 uint16_t flags = xfer->ux_flags; 2994 2995 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2996 2997 ASSERT_SLEEPABLE(); 2998 KASSERT(sp); 2999 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 3000 3001 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 3002 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 3003 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 3004 KM_SLEEP); 3005 exfer->ex_nsqtd = nsqtd; 3006 3007 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 3008 alen, nsqtd, flags); 3009 3010 for (size_t j = 0; j < exfer->ex_nsqtd;) { 3011 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 3012 if (cur == NULL) 3013 goto nomem; 3014 exfer->ex_sqtds[j++] = cur; 3015 3016 cur->xfer = xfer; 3017 cur->len = 0; 3018 3019 } 3020 3021 *sp = exfer->ex_sqtds[0]; 3022 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 3023 3024 return 0; 3025 3026 nomem: 3027 ehci_free_sqtds(sc, exfer); 3028 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 3029 DPRINTF("no memory", 0, 0, 0, 0); 3030 return ENOMEM; 3031 } 3032 3033 Static void 3034 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 3035 { 3036 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3037 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 3038 3039 mutex_enter(&sc->sc_lock); 3040 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 3041 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 3042 3043 if (sqtd == NULL) 3044 break; 3045 3046 sqtd->nextqtd = sc->sc_freeqtds; 3047 sc->sc_freeqtds = sqtd; 3048 } 3049 mutex_exit(&sc->sc_lock); 3050 } 3051 3052 Static void 3053 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 3054 { 3055 if (prev) { 3056 prev->nextqtd = sqtd; 3057 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3058 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3059 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 3060 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3061 } 3062 } 3063 3064 Static void 3065 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3066 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3067 { 3068 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3069 usb_dma_t *dma = &xfer->ux_dmabuf; 3070 uint16_t flags = xfer->ux_flags; 3071 ehci_soft_qtd_t *sqtd, *prev; 3072 int tog = *toggle; 3073 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3074 int len = length; 3075 3076 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3077 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 3078 len, isread, tog); 3079 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 3080 0, 0, 0); 3081 3082 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 3083 3084 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3085 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3086 EHCI_QTD_SET_CERR(3) 3087 ; 3088 3089 sqtd = prev = NULL; 3090 size_t curoffs = 0; 3091 size_t j = 0; 3092 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3093 sqtd = exfer->ex_sqtds[j++]; 3094 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3095 (uintptr_t)prev, 0); 3096 3097 /* 3098 * The EHCI hardware can handle at most 5 pages and they do 3099 * not have to be contiguous 3100 */ 3101 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3102 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3103 size_t curlen = len; 3104 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3105 /* must use multiple TDs, fill as much as possible. */ 3106 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3107 3108 /* the length must be a multiple of the max size */ 3109 curlen -= curlen % mps; 3110 } 3111 KASSERT(curlen != 0); 3112 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3113 curoffs, 0); 3114 3115 /* Fill the qTD */ 3116 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3117 sqtd->qtd.qtd_status = htole32( 3118 qtdstatus | 3119 EHCI_QTD_SET_BYTES(curlen) | 3120 EHCI_QTD_SET_TOGGLE(tog)); 3121 3122 /* Find number of pages we'll be using, insert dma addresses */ 3123 size_t pages = EHCI_NPAGES(curlen); 3124 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3125 size_t pageoffs = EHCI_PAGE(curoffs); 3126 for (size_t i = 0; i < pages; i++) { 3127 paddr_t a = EHCI_PAGE(DMAADDR(dma, 3128 pageoffs + i * EHCI_PAGE_SIZE)); 3129 sqtd->qtd.qtd_buffer[i] = htole32(BUS_ADDR_LO32(a)); 3130 sqtd->qtd.qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a)); 3131 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3132 i, pages, 3133 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3134 le32toh(sqtd->qtd.qtd_buffer[i])); 3135 } 3136 /* First buffer pointer requires a page offset to start at */ 3137 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3138 3139 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3140 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3141 3142 sqtd->len = curlen; 3143 3144 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3145 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3146 3147 ehci_append_sqtd(sqtd, prev); 3148 3149 if (howmany(curlen, mps) & 1) { 3150 tog ^= 1; 3151 } 3152 3153 curoffs += curlen; 3154 len -= curlen; 3155 } 3156 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3157 xfer, length, len, mps, exfer->ex_nsqtd, j); 3158 3159 if (!isread && 3160 (flags & USBD_FORCE_SHORT_XFER) && 3161 length % mps == 0) { 3162 /* Force a 0 length transfer at the end. */ 3163 3164 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3165 exfer->ex_nsqtd); 3166 prev = sqtd; 3167 sqtd = exfer->ex_sqtds[j++]; 3168 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3169 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3170 sqtd->qtd.qtd_status = htole32( 3171 qtdstatus | 3172 EHCI_QTD_SET_BYTES(0) | 3173 EHCI_QTD_SET_TOGGLE(tog)); 3174 3175 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3177 3178 ehci_append_sqtd(sqtd, prev); 3179 tog ^= 1; 3180 } 3181 3182 *lsqtd = sqtd; 3183 *toggle = tog; 3184 } 3185 3186 Static ehci_soft_itd_t * 3187 ehci_alloc_itd(ehci_softc_t *sc) 3188 { 3189 struct ehci_soft_itd *itd, *freeitd; 3190 3191 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3192 3193 mutex_enter(&sc->sc_lock); 3194 3195 freeitd = LIST_FIRST(&sc->sc_freeitds); 3196 if (freeitd == NULL) { 3197 DPRINTF("allocating chunk", 0, 0, 0, 0); 3198 mutex_exit(&sc->sc_lock); 3199 3200 usb_dma_t dma; 3201 int err = usb_allocmem(sc->sc_dmatag, 3202 EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3203 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3204 3205 if (err) { 3206 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3207 return NULL; 3208 } 3209 3210 mutex_enter(&sc->sc_lock); 3211 for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) { 3212 const int offs = i * EHCI_ITD_SIZE; 3213 const bus_addr_t baddr = DMAADDR(&dma, offs); 3214 3215 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3216 3217 itd = KERNADDR(&dma, offs); 3218 itd->physaddr = BUS_ADDR_LO32(baddr); 3219 itd->dma = dma; 3220 itd->offs = offs; 3221 3222 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3223 } 3224 freeitd = LIST_FIRST(&sc->sc_freeitds); 3225 } 3226 3227 itd = freeitd; 3228 LIST_REMOVE(itd, free_list); 3229 mutex_exit(&sc->sc_lock); 3230 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3231 3232 itd->frame_list.next = NULL; 3233 itd->frame_list.prev = NULL; 3234 itd->xfer_next = NULL; 3235 itd->slot = 0; 3236 3237 return itd; 3238 } 3239 3240 Static ehci_soft_sitd_t * 3241 ehci_alloc_sitd(ehci_softc_t *sc) 3242 { 3243 struct ehci_soft_sitd *sitd, *freesitd; 3244 3245 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3246 3247 mutex_enter(&sc->sc_lock); 3248 freesitd = LIST_FIRST(&sc->sc_freesitds); 3249 if (freesitd == NULL) { 3250 DPRINTF("allocating chunk", 0, 0, 0, 0); 3251 mutex_exit(&sc->sc_lock); 3252 3253 usb_dma_t dma; 3254 int err = usb_allocmem(sc->sc_dmatag, 3255 EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3256 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3257 3258 if (err) { 3259 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3260 return NULL; 3261 } 3262 3263 mutex_enter(&sc->sc_lock); 3264 for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) { 3265 const int offs = i * EHCI_SITD_SIZE; 3266 const bus_addr_t baddr = DMAADDR(&dma, offs); 3267 3268 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3269 3270 sitd = KERNADDR(&dma, offs); 3271 sitd->physaddr = BUS_ADDR_LO32(baddr); 3272 sitd->dma = dma; 3273 sitd->offs = offs; 3274 3275 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3276 } 3277 freesitd = LIST_FIRST(&sc->sc_freesitds); 3278 } 3279 3280 sitd = freesitd; 3281 LIST_REMOVE(sitd, free_list); 3282 mutex_exit(&sc->sc_lock); 3283 3284 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3285 3286 sitd->frame_list.next = NULL; 3287 sitd->frame_list.prev = NULL; 3288 sitd->xfer_next = NULL; 3289 sitd->slot = 0; 3290 3291 return sitd; 3292 } 3293 3294 /****************/ 3295 3296 /* 3297 * Close a reqular pipe. 3298 * Assumes that there are no pending transactions. 3299 */ 3300 Static void 3301 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3302 { 3303 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3304 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3305 ehci_soft_qh_t *sqh = epipe->sqh; 3306 3307 KASSERT(mutex_owned(&sc->sc_lock)); 3308 3309 ehci_rem_qh(sc, sqh, head); 3310 ehci_free_sqh(sc, epipe->sqh); 3311 } 3312 3313 /* 3314 * Arrange for the hardware to tells us that it is not still 3315 * processing the TDs by setting the QH halted bit and wait for the ehci 3316 * door bell 3317 */ 3318 Static void 3319 ehci_abortx(struct usbd_xfer *xfer) 3320 { 3321 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3322 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3323 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3324 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3325 ehci_soft_qh_t *sqh = epipe->sqh; 3326 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3327 ehci_physaddr_t cur; 3328 uint32_t qhstatus; 3329 int hit; 3330 3331 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3332 3333 KASSERT(mutex_owned(&sc->sc_lock)); 3334 ASSERT_SLEEPABLE(); 3335 3336 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3337 xfer->ux_status == USBD_TIMEOUT), 3338 "bad abort status: %d", xfer->ux_status); 3339 3340 /* 3341 * If we're dying, skip the hardware action and just notify the 3342 * software that we're done. 3343 */ 3344 if (sc->sc_dying) { 3345 goto dying; 3346 } 3347 3348 /* 3349 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3350 */ 3351 ehci_del_intr_list(sc, exfer); 3352 3353 usb_syncmem(&sqh->dma, 3354 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3355 sizeof(sqh->qh.qh_qtd.qtd_status), 3356 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3357 qhstatus = sqh->qh.qh_qtd.qtd_status; 3358 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3359 usb_syncmem(&sqh->dma, 3360 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3361 sizeof(sqh->qh.qh_qtd.qtd_status), 3362 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3363 3364 if (exfer->ex_type == EX_CTRL) { 3365 fsqtd = exfer->ex_setup; 3366 lsqtd = exfer->ex_status; 3367 } else { 3368 fsqtd = exfer->ex_sqtdstart; 3369 lsqtd = exfer->ex_sqtdend; 3370 } 3371 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3372 usb_syncmem(&sqtd->dma, 3373 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3374 sizeof(sqtd->qtd.qtd_status), 3375 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3376 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3377 usb_syncmem(&sqtd->dma, 3378 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3379 sizeof(sqtd->qtd.qtd_status), 3380 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3381 if (sqtd == lsqtd) 3382 break; 3383 } 3384 3385 /* 3386 * HC Step 2: Wait until we know hardware has finished any possible 3387 * use of the xfer. 3388 */ 3389 ehci_sync_hc(sc); 3390 3391 /* 3392 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3393 * The complication here is that the hardware may have executed 3394 * beyond the xfer we're trying to abort. So as we're scanning 3395 * the TDs of this xfer we check if the hardware points to 3396 * any of them. 3397 */ 3398 3399 usb_syncmem(&sqh->dma, 3400 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3401 sizeof(sqh->qh.qh_curqtd), 3402 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3403 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3404 hit = 0; 3405 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3406 hit |= cur == sqtd->physaddr; 3407 if (sqtd == lsqtd) 3408 break; 3409 } 3410 sqtd = sqtd->nextqtd; 3411 /* Zap curqtd register if hardware pointed inside the xfer. */ 3412 if (hit && sqtd != NULL) { 3413 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3414 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3415 usb_syncmem(&sqh->dma, 3416 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3417 sizeof(sqh->qh.qh_curqtd), 3418 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3419 sqh->qh.qh_qtd.qtd_status = qhstatus; 3420 usb_syncmem(&sqh->dma, 3421 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3422 sizeof(sqh->qh.qh_qtd.qtd_status), 3423 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3424 } else { 3425 DPRINTF("no hit", 0, 0, 0, 0); 3426 usb_syncmem(&sqh->dma, 3427 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3428 sizeof(sqh->qh.qh_curqtd), 3429 BUS_DMASYNC_PREREAD); 3430 } 3431 3432 dying: 3433 #ifdef DIAGNOSTIC 3434 exfer->ex_isdone = true; 3435 #endif 3436 DPRINTFN(14, "end", 0, 0, 0, 0); 3437 3438 KASSERT(mutex_owned(&sc->sc_lock)); 3439 } 3440 3441 Static void 3442 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3443 { 3444 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3445 ehci_isoc_trans_t trans_status; 3446 struct ehci_xfer *exfer; 3447 ehci_softc_t *sc; 3448 struct ehci_soft_itd *itd; 3449 struct ehci_soft_sitd *sitd; 3450 int i; 3451 3452 KASSERTMSG(status == USBD_CANCELLED, 3453 "invalid status for abort: %d", (int)status); 3454 3455 exfer = EHCI_XFER2EXFER(xfer); 3456 sc = EHCI_XFER2SC(xfer); 3457 3458 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3459 (uintptr_t)xfer->ux_pipe, 0, 0); 3460 3461 KASSERT(mutex_owned(&sc->sc_lock)); 3462 ASSERT_SLEEPABLE(); 3463 3464 /* No timeout or task here. */ 3465 3466 /* 3467 * The xfer cannot have been cancelled already. It is the 3468 * responsibility of the caller of usbd_abort_pipe not to try 3469 * to abort a pipe multiple times, whether concurrently or 3470 * sequentially. 3471 */ 3472 KASSERT(xfer->ux_status != USBD_CANCELLED); 3473 3474 /* If anyone else beat us, we're done. */ 3475 if (xfer->ux_status != USBD_IN_PROGRESS) 3476 return; 3477 3478 /* We beat everyone else. Claim the status. */ 3479 xfer->ux_status = status; 3480 3481 /* 3482 * If we're dying, skip the hardware action and just notify the 3483 * software that we're done. 3484 */ 3485 if (sc->sc_dying) { 3486 goto dying; 3487 } 3488 3489 /* 3490 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3491 */ 3492 ehci_del_intr_list(sc, exfer); 3493 3494 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3495 for (itd = exfer->ex_itdstart; itd != NULL; 3496 itd = itd->xfer_next) { 3497 usb_syncmem(&itd->dma, 3498 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3499 sizeof(itd->itd.itd_ctl), 3500 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3501 3502 for (i = 0; i < 8; i++) { 3503 trans_status = le32toh(itd->itd.itd_ctl[i]); 3504 trans_status &= ~EHCI_ITD_ACTIVE; 3505 itd->itd.itd_ctl[i] = htole32(trans_status); 3506 } 3507 3508 usb_syncmem(&itd->dma, 3509 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3510 sizeof(itd->itd.itd_ctl), 3511 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3512 } 3513 } else { 3514 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3515 sitd = sitd->xfer_next) { 3516 usb_syncmem(&sitd->dma, 3517 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3518 sizeof(sitd->sitd.sitd_buffer), 3519 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3520 3521 trans_status = le32toh(sitd->sitd.sitd_trans); 3522 trans_status &= ~EHCI_SITD_ACTIVE; 3523 sitd->sitd.sitd_trans = htole32(trans_status); 3524 3525 usb_syncmem(&sitd->dma, 3526 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3527 sizeof(sitd->sitd.sitd_buffer), 3528 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3529 } 3530 } 3531 3532 dying: 3533 #ifdef DIAGNOSTIC 3534 exfer->ex_isdone = true; 3535 #endif 3536 usb_transfer_complete(xfer); 3537 DPRINTFN(14, "end", 0, 0, 0, 0); 3538 3539 KASSERT(mutex_owned(&sc->sc_lock)); 3540 } 3541 3542 /************************/ 3543 3544 Static int 3545 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3546 { 3547 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3548 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3549 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3550 usb_device_request_t *req = &xfer->ux_request; 3551 ehci_soft_qtd_t *setup, *status, *next; 3552 int isread = req->bmRequestType & UT_READ; 3553 int len = xfer->ux_bufsize; 3554 int err; 3555 3556 exfer->ex_type = EX_CTRL; 3557 exfer->ex_status = NULL; 3558 exfer->ex_data = NULL; 3559 exfer->ex_setup = ehci_alloc_sqtd(sc); 3560 if (exfer->ex_setup == NULL) { 3561 err = ENOMEM; 3562 goto bad1; 3563 } 3564 exfer->ex_status = ehci_alloc_sqtd(sc); 3565 if (exfer->ex_status == NULL) { 3566 err = ENOMEM; 3567 goto bad2; 3568 } 3569 setup = exfer->ex_setup; 3570 status = exfer->ex_status; 3571 exfer->ex_nsqtd = 0; 3572 next = status; 3573 /* Set up data transaction */ 3574 if (len != 0) { 3575 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3576 &exfer->ex_data); 3577 if (err) 3578 goto bad3; 3579 next = exfer->ex_data; 3580 } 3581 3582 /* Clear toggle */ 3583 setup->qtd.qtd_status = htole32( 3584 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3585 EHCI_QTD_SET_TOGGLE(0) | 3586 EHCI_QTD_SET_BYTES(sizeof(*req)) 3587 ); 3588 3589 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3590 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3591 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3592 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3593 setup->nextqtd = next; 3594 setup->xfer = xfer; 3595 setup->len = sizeof(*req); 3596 3597 status->qtd.qtd_status = htole32( 3598 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3599 EHCI_QTD_SET_TOGGLE(1) | 3600 EHCI_QTD_IOC 3601 ); 3602 status->qtd.qtd_buffer[0] = 0; 3603 status->qtd.qtd_buffer_hi[0] = 0; 3604 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3605 status->nextqtd = NULL; 3606 status->xfer = xfer; 3607 status->len = 0; 3608 3609 return 0; 3610 bad3: 3611 ehci_free_sqtd(sc, exfer->ex_status); 3612 bad2: 3613 ehci_free_sqtd(sc, exfer->ex_setup); 3614 bad1: 3615 return err; 3616 } 3617 3618 Static void 3619 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3620 { 3621 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3622 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3623 3624 KASSERT(ex->ex_type == EX_CTRL); 3625 3626 ehci_free_sqtd(sc, ex->ex_setup); 3627 ehci_free_sqtd(sc, ex->ex_status); 3628 ehci_free_sqtds(sc, ex); 3629 if (ex->ex_nsqtd) 3630 kmem_free(ex->ex_sqtds, 3631 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3632 } 3633 3634 Static usbd_status 3635 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3636 { 3637 3638 /* Pipe isn't running, start first */ 3639 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3640 } 3641 3642 Static usbd_status 3643 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3644 { 3645 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3646 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3647 usb_device_request_t *req = &xfer->ux_request; 3648 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3649 ehci_soft_qtd_t *setup, *status, *next; 3650 ehci_soft_qh_t *sqh; 3651 3652 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3653 3654 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3655 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3656 3657 if (sc->sc_dying) 3658 return USBD_IOERROR; 3659 3660 const int isread = req->bmRequestType & UT_READ; 3661 const int len = UGETW(req->wLength); 3662 3663 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3664 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3665 UGETW(req->wIndex)); 3666 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3667 len, epipe->pipe.up_dev->ud_addr, 3668 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3669 3670 sqh = epipe->sqh; 3671 3672 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3673 "address QH %" __PRIuBIT " pipe %d\n", 3674 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3675 epipe->pipe.up_dev->ud_addr); 3676 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3677 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3678 "MPS QH %" __PRIuBIT " pipe %d\n", 3679 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3680 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3681 3682 setup = exfer->ex_setup; 3683 status = exfer->ex_status; 3684 3685 DPRINTF("setup %#jx status %#jx data %#jx", 3686 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3687 KASSERTMSG(setup != NULL && status != NULL, 3688 "Failed memory allocation, setup %p status %p", 3689 setup, status); 3690 3691 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3692 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3693 3694 /* Clear toggle */ 3695 setup->qtd.qtd_status &= ~htole32( 3696 EHCI_QTD_STATUS_MASK | 3697 EHCI_QTD_BYTES_MASK | 3698 EHCI_QTD_TOGGLE_MASK | 3699 EHCI_QTD_CERR_MASK 3700 ); 3701 setup->qtd.qtd_status |= htole32( 3702 EHCI_QTD_ACTIVE | 3703 EHCI_QTD_SET_CERR(3) | 3704 EHCI_QTD_SET_TOGGLE(0) | 3705 EHCI_QTD_SET_BYTES(sizeof(*req)) 3706 ); 3707 3708 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3709 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3710 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3711 3712 next = status; 3713 status->qtd.qtd_status &= ~htole32( 3714 EHCI_QTD_STATUS_MASK | 3715 EHCI_QTD_PID_MASK | 3716 EHCI_QTD_BYTES_MASK | 3717 EHCI_QTD_TOGGLE_MASK | 3718 EHCI_QTD_CERR_MASK 3719 ); 3720 status->qtd.qtd_status |= htole32( 3721 EHCI_QTD_ACTIVE | 3722 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3723 EHCI_QTD_SET_CERR(3) | 3724 EHCI_QTD_SET_TOGGLE(1) | 3725 EHCI_QTD_SET_BYTES(0) | 3726 EHCI_QTD_IOC 3727 ); 3728 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3729 3730 KASSERT(exfer->ex_isdone); 3731 #ifdef DIAGNOSTIC 3732 exfer->ex_isdone = false; 3733 #endif 3734 3735 /* Set up data transaction */ 3736 if (len != 0) { 3737 ehci_soft_qtd_t *end; 3738 3739 /* Start toggle at 1. */ 3740 int toggle = 1; 3741 next = exfer->ex_data; 3742 KASSERTMSG(next != NULL, "Failed memory allocation"); 3743 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3744 end->nextqtd = status; 3745 end->qtd.qtd_next = end->qtd.qtd_altnext = 3746 htole32(status->physaddr); 3747 3748 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3749 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3750 3751 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3752 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3753 } 3754 3755 setup->nextqtd = next; 3756 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3757 3758 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3759 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3760 3761 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3762 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3763 3764 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3765 3766 #ifdef EHCI_DEBUG 3767 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3768 ehci_dump_sqh(sqh); 3769 ehci_dump_sqtds(setup); 3770 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3771 #endif 3772 3773 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3774 ehci_set_qh_qtd(sqh, setup); 3775 usbd_xfer_schedule_timeout(xfer); 3776 ehci_add_intr_list(sc, exfer); 3777 xfer->ux_status = USBD_IN_PROGRESS; 3778 3779 #if 0 3780 #ifdef EHCI_DEBUG 3781 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3782 // delay(10000); 3783 ehci_dump_regs(sc); 3784 ehci_dump_sqh(sc->sc_async_head); 3785 ehci_dump_sqh(sqh); 3786 ehci_dump_sqtds(setup); 3787 #endif 3788 #endif 3789 3790 return USBD_IN_PROGRESS; 3791 } 3792 3793 Static void 3794 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3795 { 3796 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3797 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3798 usb_device_request_t *req = &xfer->ux_request; 3799 int len = UGETW(req->wLength); 3800 int rd = req->bmRequestType & UT_READ; 3801 3802 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3803 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3804 3805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3806 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3807 3808 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3809 BUS_DMASYNC_POSTWRITE); 3810 if (len) 3811 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3812 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3813 3814 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3815 } 3816 3817 /* Abort a device control request. */ 3818 Static void 3819 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3820 { 3821 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3822 3823 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3824 usbd_xfer_abort(xfer); 3825 } 3826 3827 /* Close a device control pipe. */ 3828 Static void 3829 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3830 { 3831 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3832 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3833 3834 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3835 3836 KASSERT(mutex_owned(&sc->sc_lock)); 3837 3838 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3839 3840 ehci_close_pipe(pipe, sc->sc_async_head); 3841 3842 usb_freemem(&epipe->ctrl.reqdma); 3843 } 3844 3845 /* 3846 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3847 * qTD status, or miss signalling occasionally under heavy load. If the host 3848 * machine is too fast, we can miss transaction completion - when we scan 3849 * the active list the transaction still seems to be active. This generally 3850 * exhibits itself as a umass stall that never recovers. 3851 * 3852 * We work around this behaviour by setting up this callback after any softintr 3853 * that completes with transactions still pending, giving us another chance to 3854 * check for completion after the writeback has taken place. 3855 */ 3856 Static void 3857 ehci_intrlist_timeout(void *arg) 3858 { 3859 ehci_softc_t *sc = arg; 3860 3861 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3862 3863 usb_schedsoftintr(&sc->sc_bus); 3864 } 3865 3866 /************************/ 3867 3868 Static int 3869 ehci_device_bulk_init(struct usbd_xfer *xfer) 3870 { 3871 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3872 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3873 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3874 int endpt = ed->bEndpointAddress; 3875 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3876 int len = xfer->ux_bufsize; 3877 int err = 0; 3878 3879 exfer->ex_type = EX_BULK; 3880 exfer->ex_nsqtd = 0; 3881 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3882 &exfer->ex_sqtdstart); 3883 3884 return err; 3885 } 3886 3887 Static void 3888 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3889 { 3890 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3891 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3892 3893 KASSERT(ex->ex_type == EX_BULK); 3894 3895 ehci_free_sqtds(sc, ex); 3896 if (ex->ex_nsqtd) 3897 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3898 } 3899 3900 Static usbd_status 3901 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3902 { 3903 3904 /* Pipe isn't running, start first */ 3905 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3906 } 3907 3908 Static usbd_status 3909 ehci_device_bulk_start(struct usbd_xfer *xfer) 3910 { 3911 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3912 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3913 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3914 ehci_soft_qh_t *sqh; 3915 ehci_soft_qtd_t *end; 3916 int len, isread, endpt; 3917 3918 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3919 3920 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3921 xfer->ux_flags, 0); 3922 3923 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3924 3925 if (sc->sc_dying) 3926 return USBD_IOERROR; 3927 3928 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3929 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3930 3931 len = xfer->ux_length; 3932 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3933 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3934 sqh = epipe->sqh; 3935 3936 KASSERT(exfer->ex_isdone); 3937 #ifdef DIAGNOSTIC 3938 exfer->ex_isdone = false; 3939 #endif 3940 3941 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3942 3943 exfer->ex_sqtdend = end; 3944 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3945 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3946 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3947 3948 #ifdef EHCI_DEBUG 3949 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3950 ehci_dump_sqh(sqh); 3951 ehci_dump_sqtds(exfer->ex_sqtdstart); 3952 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3953 #endif 3954 3955 if (xfer->ux_length) 3956 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3957 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3958 3959 /* also does usb_syncmem(sqh) */ 3960 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3961 usbd_xfer_schedule_timeout(xfer); 3962 ehci_add_intr_list(sc, exfer); 3963 xfer->ux_status = USBD_IN_PROGRESS; 3964 3965 #if 0 3966 #ifdef EHCI_DEBUG 3967 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3968 // delay(10000); 3969 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3970 ehci_dump_regs(sc); 3971 #if 0 3972 printf("async_head:\n"); 3973 ehci_dump_sqh(sc->sc_async_head); 3974 #endif 3975 DPRINTF("sqh:", 0, 0, 0, 0); 3976 ehci_dump_sqh(sqh); 3977 ehci_dump_sqtds(exfer->ex_sqtdstart); 3978 #endif 3979 #endif 3980 3981 return USBD_IN_PROGRESS; 3982 } 3983 3984 Static void 3985 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3986 { 3987 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3988 3989 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 3990 usbd_xfer_abort(xfer); 3991 } 3992 3993 /* 3994 * Close a device bulk pipe. 3995 */ 3996 Static void 3997 ehci_device_bulk_close(struct usbd_pipe *pipe) 3998 { 3999 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4000 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4001 4002 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4003 4004 KASSERT(mutex_owned(&sc->sc_lock)); 4005 4006 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4007 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4008 ehci_close_pipe(pipe, sc->sc_async_head); 4009 } 4010 4011 Static void 4012 ehci_device_bulk_done(struct usbd_xfer *xfer) 4013 { 4014 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4015 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4016 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4017 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4018 4019 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4020 4021 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4022 4023 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4024 4025 if (xfer->ux_length) 4026 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4027 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4028 4029 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4030 } 4031 4032 /************************/ 4033 4034 Static usbd_status 4035 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4036 { 4037 struct ehci_soft_islot *isp; 4038 int islot, lev; 4039 4040 /* Find a poll rate that is large enough. */ 4041 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4042 if (EHCI_ILEV_IVAL(lev) <= ival) 4043 break; 4044 4045 /* Pick an interrupt slot at the right level. */ 4046 /* XXX could do better than picking at random */ 4047 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4048 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4049 4050 sqh->islot = islot; 4051 isp = &sc->sc_islots[islot]; 4052 mutex_enter(&sc->sc_lock); 4053 ehci_add_qh(sc, sqh, isp->sqh); 4054 mutex_exit(&sc->sc_lock); 4055 4056 return USBD_NORMAL_COMPLETION; 4057 } 4058 4059 Static int 4060 ehci_device_intr_init(struct usbd_xfer *xfer) 4061 { 4062 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4063 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4064 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4065 int endpt = ed->bEndpointAddress; 4066 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4067 int len = xfer->ux_bufsize; 4068 int err; 4069 4070 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4071 4072 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4073 xfer->ux_flags, 0); 4074 4075 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4076 KASSERT(len != 0); 4077 4078 exfer->ex_type = EX_INTR; 4079 exfer->ex_nsqtd = 0; 4080 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4081 &exfer->ex_sqtdstart); 4082 4083 return err; 4084 } 4085 4086 Static void 4087 ehci_device_intr_fini(struct usbd_xfer *xfer) 4088 { 4089 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4090 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4091 4092 KASSERT(ex->ex_type == EX_INTR); 4093 4094 ehci_free_sqtds(sc, ex); 4095 if (ex->ex_nsqtd) 4096 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4097 } 4098 4099 Static usbd_status 4100 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4101 { 4102 4103 /* Pipe isn't running, so start it first. */ 4104 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4105 } 4106 4107 Static usbd_status 4108 ehci_device_intr_start(struct usbd_xfer *xfer) 4109 { 4110 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4111 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4112 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4113 ehci_soft_qtd_t *end; 4114 ehci_soft_qh_t *sqh; 4115 int len, isread, endpt; 4116 4117 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4118 4119 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4120 xfer->ux_flags, 0); 4121 4122 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4123 4124 if (sc->sc_dying) 4125 return USBD_IOERROR; 4126 4127 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4128 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4129 4130 len = xfer->ux_length; 4131 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4132 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4133 sqh = epipe->sqh; 4134 4135 KASSERT(exfer->ex_isdone); 4136 #ifdef DIAGNOSTIC 4137 exfer->ex_isdone = false; 4138 #endif 4139 4140 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4141 4142 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4143 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4144 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4145 exfer->ex_sqtdend = end; 4146 4147 #ifdef EHCI_DEBUG 4148 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4149 ehci_dump_sqh(sqh); 4150 ehci_dump_sqtds(exfer->ex_sqtdstart); 4151 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4152 #endif 4153 4154 if (xfer->ux_length) 4155 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4156 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4157 4158 /* also does usb_syncmem(sqh) */ 4159 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4160 usbd_xfer_schedule_timeout(xfer); 4161 ehci_add_intr_list(sc, exfer); 4162 xfer->ux_status = USBD_IN_PROGRESS; 4163 4164 #if 0 4165 #ifdef EHCI_DEBUG 4166 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4167 // delay(10000); 4168 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4169 ehci_dump_regs(sc); 4170 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4171 ehci_dump_sqh(sqh); 4172 ehci_dump_sqtds(exfer->ex_sqtdstart); 4173 #endif 4174 #endif 4175 4176 return USBD_IN_PROGRESS; 4177 } 4178 4179 Static void 4180 ehci_device_intr_abort(struct usbd_xfer *xfer) 4181 { 4182 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4183 4184 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4185 4186 /* 4187 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4188 * async doorbell. That's dependent on the async list, wheras 4189 * intr xfers are periodic, should not use this? 4190 */ 4191 usbd_xfer_abort(xfer); 4192 } 4193 4194 Static void 4195 ehci_device_intr_close(struct usbd_pipe *pipe) 4196 { 4197 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4198 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4199 struct ehci_soft_islot *isp; 4200 4201 KASSERT(mutex_owned(&sc->sc_lock)); 4202 4203 isp = &sc->sc_islots[epipe->sqh->islot]; 4204 ehci_close_pipe(pipe, isp->sqh); 4205 } 4206 4207 Static void 4208 ehci_device_intr_done(struct usbd_xfer *xfer) 4209 { 4210 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4211 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4212 4213 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4214 4215 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4216 4217 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4218 4219 if (xfer->ux_length) { 4220 int isread, endpt; 4221 4222 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4223 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4224 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4225 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4226 } 4227 } 4228 4229 /************************/ 4230 Static int 4231 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4232 { 4233 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4234 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4235 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4236 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4237 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4238 int i, k, frames; 4239 u_int huba, dir; 4240 int err; 4241 4242 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4243 4244 start = NULL; 4245 sitd = NULL; 4246 4247 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4248 xfer->ux_flags, 0); 4249 4250 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4251 KASSERT(xfer->ux_nframes != 0); 4252 KASSERT(exfer->ex_isdone); 4253 4254 exfer->ex_type = EX_FS_ISOC; 4255 /* 4256 * Step 1: Allocate and initialize sitds. 4257 */ 4258 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4259 if (i > 16 || i == 0) { 4260 /* Spec page 271 says intervals > 16 are invalid */ 4261 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4262 4263 return EINVAL; 4264 } 4265 4266 frames = xfer->ux_nframes; 4267 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4268 sitd = ehci_alloc_sitd(sc); 4269 if (sitd == NULL) { 4270 err = ENOMEM; 4271 goto fail; 4272 } 4273 4274 if (prev) 4275 prev->xfer_next = sitd; 4276 else 4277 start = sitd; 4278 4279 huba = dev->ud_myhsport->up_parent->ud_addr; 4280 4281 #if 0 4282 if (sc->sc_flags & EHCIF_FREESCALE) { 4283 // Set hub address to 0 if embedded TT is used. 4284 if (huba == sc->sc_addr) 4285 huba = 0; 4286 } 4287 #endif 4288 4289 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4290 dir = UE_GET_DIR(k) ? 1 : 0; 4291 sitd->sitd.sitd_endp = 4292 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4293 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4294 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4295 EHCI_SITD_SET_HUBA(huba) | 4296 EHCI_SITD_SET_DIR(dir)); 4297 4298 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4299 } /* End of frame */ 4300 4301 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4302 4303 stop = sitd; 4304 stop->xfer_next = NULL; 4305 exfer->ex_sitdstart = start; 4306 exfer->ex_sitdend = stop; 4307 4308 return 0; 4309 4310 fail: 4311 mutex_enter(&sc->sc_lock); 4312 ehci_soft_sitd_t *next; 4313 for (sitd = start; sitd; sitd = next) { 4314 next = sitd->xfer_next; 4315 ehci_free_sitd_locked(sc, sitd); 4316 } 4317 mutex_exit(&sc->sc_lock); 4318 4319 return err; 4320 } 4321 4322 Static void 4323 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4324 { 4325 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4326 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4327 4328 KASSERT(ex->ex_type == EX_FS_ISOC); 4329 4330 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4331 } 4332 4333 Static usbd_status 4334 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4335 { 4336 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4337 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4338 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4339 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4340 ehci_soft_sitd_t *sitd; 4341 usb_dma_t *dma_buf; 4342 int i, j, k, frames; 4343 int offs; 4344 int frindex; 4345 u_int dir; 4346 4347 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4348 4349 sitd = NULL; 4350 4351 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4352 xfer->ux_flags, 0); 4353 4354 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4355 4356 if (sc->sc_dying) 4357 return USBD_IOERROR; 4358 4359 /* 4360 * To avoid complication, don't allow a request right now that'll span 4361 * the entire frame table. To within 4 frames, to allow some leeway 4362 * on either side of where the hc currently is. 4363 */ 4364 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4365 xfer->ux_nframes >= sc->sc_flsize - 4) { 4366 printf("ehci: isoc descriptor requested that spans the entire" 4367 " frametable, too many frames\n"); 4368 return USBD_INVAL; 4369 } 4370 4371 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4372 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4373 KASSERT(exfer->ex_isdone); 4374 #ifdef DIAGNOSTIC 4375 exfer->ex_isdone = false; 4376 #endif 4377 4378 /* 4379 * Step 1: Initialize sitds. 4380 */ 4381 4382 frames = xfer->ux_nframes; 4383 dma_buf = &xfer->ux_dmabuf; 4384 offs = 0; 4385 4386 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4387 i++, sitd = sitd->xfer_next) { 4388 KASSERT(sitd != NULL); 4389 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4390 4391 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4392 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4393 4394 /* Set page0 index and offset - TP and T-offset are set below */ 4395 const bus_addr_t sba = DMAADDR(dma_buf, offs); 4396 sitd->sitd.sitd_buffer[0] = htole32(BUS_ADDR_LO32(sba)); 4397 sitd->sitd.sitd_buffer_hi[0] = htole32(BUS_ADDR_HI32(sba)); 4398 4399 offs += xfer->ux_frlengths[i]; 4400 4401 const bus_addr_t eba = DMAADDR(dma_buf, offs - 1); 4402 sitd->sitd.sitd_buffer[1] = 4403 htole32(EHCI_SITD_SET_BPTR(BUS_ADDR_LO32(eba))); 4404 sitd->sitd.sitd_buffer_hi[1] = htole32(BUS_ADDR_HI32(eba)); 4405 4406 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4407 4408 #if 0 4409 if (sc->sc_flags & EHCIF_FREESCALE) { 4410 // Set hub address to 0 if embedded TT is used. 4411 if (huba == sc->sc_addr) 4412 huba = 0; 4413 } 4414 #endif 4415 4416 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4417 dir = UE_GET_DIR(k) ? 1 : 0; 4418 KASSERT(sitd->sitd.sitd_endp == htole32( 4419 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4420 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4421 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4422 EHCI_SITD_SET_HUBA(huba) | 4423 EHCI_SITD_SET_DIR(dir))); 4424 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4425 4426 uint8_t sa = 0; 4427 uint8_t sb = 0; 4428 u_int temp, tlen; 4429 4430 if (dir == 0) { /* OUT */ 4431 temp = 0; 4432 tlen = xfer->ux_frlengths[i]; 4433 if (tlen <= 188) { 4434 temp |= 1; /* T-count = 1, TP = ALL */ 4435 tlen = 1; 4436 } else { 4437 tlen += 187; 4438 tlen /= 188; 4439 temp |= tlen; /* T-count = [1..6] */ 4440 temp |= 8; /* TP = Begin */ 4441 } 4442 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4443 4444 tlen += sa; 4445 4446 if (tlen >= 8) { 4447 sb = 0; 4448 } else { 4449 sb = (1 << tlen); 4450 } 4451 4452 sa = (1 << sa); 4453 sa = (sb - sa) & 0x3F; 4454 sb = 0; 4455 } else { 4456 sb = (-(4 << sa)) & 0xFE; 4457 sa = (1 << sa) & 0x3F; 4458 sa = 0x01; 4459 sb = 0xfc; 4460 } 4461 4462 sitd->sitd.sitd_sched = htole32( 4463 EHCI_SITD_SET_SMASK(sa) | 4464 EHCI_SITD_SET_CMASK(sb) 4465 ); 4466 4467 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4469 } /* End of frame */ 4470 4471 sitd = exfer->ex_sitdend; 4472 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4473 4474 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4475 sizeof(sitd->sitd.sitd_trans), 4476 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4477 4478 if (xfer->ux_length) 4479 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4480 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4481 4482 /* 4483 * Part 2: Transfer descriptors have now been set up, now they must 4484 * be scheduled into the periodic frame list. Erk. Not wanting to 4485 * complicate matters, transfer is denied if the transfer spans 4486 * more than the period frame list. 4487 */ 4488 4489 /* Start inserting frames */ 4490 if (epipe->isoc.cur_xfers > 0) { 4491 frindex = epipe->isoc.next_frame; 4492 } else { 4493 frindex = EOREAD4(sc, EHCI_FRINDEX); 4494 frindex = frindex >> 3; /* Erase microframe index */ 4495 frindex += 2; 4496 } 4497 4498 if (frindex >= sc->sc_flsize) 4499 frindex &= (sc->sc_flsize - 1); 4500 4501 /* Whats the frame interval? */ 4502 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4503 4504 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4505 j++, sitd = sitd->xfer_next) { 4506 KASSERT(sitd); 4507 4508 usb_syncmem(&sc->sc_fldma, 4509 sizeof(ehci_link_t) * frindex, 4510 sizeof(ehci_link_t), 4511 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4512 4513 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4514 if (sitd->sitd.sitd_next == 0) 4515 /* 4516 * FIXME: frindex table gets initialized to NULL 4517 * or EHCI_NULL? 4518 */ 4519 sitd->sitd.sitd_next = EHCI_NULL; 4520 4521 usb_syncmem(&sitd->dma, 4522 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4523 sizeof(ehci_sitd_t), 4524 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4525 4526 sc->sc_flist[frindex] = 4527 htole32(EHCI_LINK_SITD | sitd->physaddr); 4528 4529 usb_syncmem(&sc->sc_fldma, 4530 sizeof(ehci_link_t) * frindex, 4531 sizeof(ehci_link_t), 4532 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4533 4534 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4535 sc->sc_softsitds[frindex] = sitd; 4536 if (sitd->frame_list.next != NULL) 4537 sitd->frame_list.next->frame_list.prev = sitd; 4538 sitd->slot = frindex; 4539 sitd->frame_list.prev = NULL; 4540 4541 frindex += i; 4542 if (frindex >= sc->sc_flsize) 4543 frindex -= sc->sc_flsize; 4544 } 4545 4546 epipe->isoc.cur_xfers++; 4547 epipe->isoc.next_frame = frindex; 4548 4549 ehci_add_intr_list(sc, exfer); 4550 xfer->ux_status = USBD_IN_PROGRESS; 4551 4552 return USBD_IN_PROGRESS; 4553 } 4554 4555 Static void 4556 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4557 { 4558 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4559 4560 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4561 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4562 } 4563 4564 Static void 4565 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4566 { 4567 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4568 4569 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4570 } 4571 4572 Static void 4573 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4574 { 4575 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4576 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4577 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4578 4579 KASSERT(mutex_owned(&sc->sc_lock)); 4580 4581 epipe->isoc.cur_xfers--; 4582 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4583 4584 if (xfer->ux_length) 4585 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4586 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4587 } 4588 4589 /* -------------------------------------------------------------------------- */ 4590 4591 Static int 4592 ehci_device_isoc_init(struct usbd_xfer *xfer) 4593 { 4594 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4595 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4596 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4597 ehci_soft_itd_t *itd, *prev, *start, *stop; 4598 int i, j, k; 4599 int frames, ufrperframe; 4600 int err; 4601 4602 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4603 4604 start = NULL; 4605 prev = NULL; 4606 itd = NULL; 4607 4608 KASSERT(xfer->ux_nframes != 0); 4609 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4610 KASSERT(exfer->ex_isdone); 4611 4612 exfer->ex_type = EX_ISOC; 4613 4614 /* 4615 * Step 1: Allocate and initialize itds, how many do we need? 4616 * One per transfer if interval >= 8 microframes, less if we use 4617 * multiple microframes per frame. 4618 */ 4619 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4620 if (i > 16 || i == 0) { 4621 /* Spec page 271 says intervals > 16 are invalid */ 4622 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4623 return USBD_INVAL; 4624 } 4625 4626 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4627 frames = howmany(xfer->ux_nframes, ufrperframe); 4628 4629 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4630 itd = ehci_alloc_itd(sc); 4631 if (itd == NULL) { 4632 err = ENOMEM; 4633 goto fail; 4634 } 4635 4636 if (prev != NULL) { 4637 /* Maybe not as it's updated by the scheduling? */ 4638 prev->itd.itd_next = 4639 htole32(itd->physaddr | EHCI_LINK_ITD); 4640 4641 prev->xfer_next = itd; 4642 } else { 4643 start = itd; 4644 } 4645 4646 /* 4647 * Other special values 4648 */ 4649 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4650 itd->itd.itd_bufr[0] = htole32( 4651 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4652 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4653 4654 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4655 ? 1 : 0; 4656 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4657 itd->itd.itd_bufr[1] |= htole32( 4658 EHCI_ITD_SET_DIR(k) | 4659 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4660 4661 /* FIXME: handle invalid trans - should be done in openpipe */ 4662 itd->itd.itd_bufr[2] |= 4663 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4664 } /* End of frame */ 4665 4666 stop = itd; 4667 stop->xfer_next = NULL; 4668 4669 exfer->ex_itdstart = start; 4670 exfer->ex_itdend = stop; 4671 4672 return 0; 4673 fail: 4674 mutex_enter(&sc->sc_lock); 4675 ehci_soft_itd_t *next; 4676 for (itd = start; itd; itd = next) { 4677 next = itd->xfer_next; 4678 ehci_free_itd_locked(sc, itd); 4679 } 4680 mutex_exit(&sc->sc_lock); 4681 4682 return err; 4683 4684 } 4685 4686 Static void 4687 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4688 { 4689 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4690 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4691 4692 KASSERT(ex->ex_type == EX_ISOC); 4693 4694 ehci_free_itd_chain(sc, ex->ex_itdstart); 4695 } 4696 4697 Static usbd_status 4698 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4699 { 4700 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4701 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4702 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4703 ehci_soft_itd_t *itd, *prev; 4704 usb_dma_t *dma_buf; 4705 int i, j; 4706 int frames, uframes, ufrperframe; 4707 int trans_count, offs; 4708 int frindex; 4709 4710 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4711 4712 prev = NULL; 4713 itd = NULL; 4714 trans_count = 0; 4715 4716 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4717 4718 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4719 4720 if (sc->sc_dying) 4721 return USBD_IOERROR; 4722 4723 /* 4724 * To avoid complication, don't allow a request right now that'll span 4725 * the entire frame table. To within 4 frames, to allow some leeway 4726 * on either side of where the hc currently is. 4727 */ 4728 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4729 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4730 DPRINTF( 4731 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4732 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4733 return USBD_INVAL; 4734 } 4735 4736 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4737 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4738 KASSERT(exfer->ex_isdone); 4739 #ifdef DIAGNOSTIC 4740 exfer->ex_isdone = false; 4741 #endif 4742 4743 /* 4744 * Step 1: Re-Initialize itds 4745 */ 4746 4747 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4748 if (i > 16 || i == 0) { 4749 /* Spec page 271 says intervals > 16 are invalid */ 4750 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4751 return USBD_INVAL; 4752 } 4753 4754 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4755 frames = howmany(xfer->ux_nframes, ufrperframe); 4756 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4757 4758 if (frames == 0) { 4759 DPRINTF("frames == 0", 0, 0, 0, 0); 4760 return USBD_INVAL; 4761 } 4762 4763 dma_buf = &xfer->ux_dmabuf; 4764 offs = 0; 4765 4766 itd = exfer->ex_itdstart; 4767 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4768 int froffs = offs; 4769 4770 if (prev != NULL) { 4771 prev->itd.itd_next = 4772 htole32(itd->physaddr | EHCI_LINK_ITD); 4773 usb_syncmem(&prev->dma, 4774 prev->offs + offsetof(ehci_itd_t, itd_next), 4775 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4776 prev->xfer_next = itd; 4777 } 4778 4779 /* 4780 * Step 1.5, initialize uframes 4781 */ 4782 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4783 /* Calculate which page in the list this starts in */ 4784 int addr = DMAADDR(dma_buf, froffs); 4785 addr = EHCI_PAGE_OFFSET(addr); 4786 addr += (offs - froffs); 4787 addr = EHCI_PAGE(addr); 4788 addr /= EHCI_PAGE_SIZE; 4789 4790 /* 4791 * This gets the initial offset into the first page, 4792 * looks how far further along the current uframe 4793 * offset is. Works out how many pages that is. 4794 */ 4795 4796 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4797 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4798 EHCI_ITD_SET_PG(addr) | 4799 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4800 4801 offs += xfer->ux_frlengths[trans_count]; 4802 trans_count++; 4803 4804 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4805 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4806 break; 4807 } 4808 } 4809 4810 /* 4811 * Step 1.75, set buffer pointers. To simplify matters, all 4812 * pointers are filled out for the next 7 hardware pages in 4813 * the dma block, so no need to worry what pages to cover 4814 * and what to not. 4815 */ 4816 4817 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4818 /* 4819 * Don't try to lookup a page that's past the end 4820 * of buffer 4821 */ 4822 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4823 if (page_offs >= dma_buf->udma_block->size) 4824 break; 4825 4826 uint64_t page = DMAADDR(dma_buf, page_offs); 4827 page = EHCI_PAGE(page); 4828 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4829 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4830 } 4831 /* 4832 * Other special values 4833 */ 4834 4835 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4836 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4837 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4838 4839 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4840 ? 1 : 0; 4841 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4842 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4843 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4844 4845 /* FIXME: handle invalid trans */ 4846 itd->itd.itd_bufr[2] |= 4847 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4848 4849 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4850 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4851 4852 prev = itd; 4853 } /* End of frame */ 4854 4855 if (xfer->ux_length) 4856 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4857 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4858 4859 /* 4860 * Part 2: Transfer descriptors have now been set up, now they must 4861 * be scheduled into the period frame list. Erk. Not wanting to 4862 * complicate matters, transfer is denied if the transfer spans 4863 * more than the period frame list. 4864 */ 4865 4866 /* Start inserting frames */ 4867 if (epipe->isoc.cur_xfers > 0) { 4868 frindex = epipe->isoc.next_frame; 4869 } else { 4870 frindex = EOREAD4(sc, EHCI_FRINDEX); 4871 frindex = frindex >> 3; /* Erase microframe index */ 4872 frindex += 2; 4873 } 4874 4875 if (frindex >= sc->sc_flsize) 4876 frindex &= (sc->sc_flsize - 1); 4877 4878 /* What's the frame interval? */ 4879 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4880 if (i / USB_UFRAMES_PER_FRAME == 0) 4881 i = 1; 4882 else 4883 i /= USB_UFRAMES_PER_FRAME; 4884 4885 itd = exfer->ex_itdstart; 4886 for (j = 0; j < frames; j++) { 4887 KASSERTMSG(itd != NULL, "frame %d\n", j); 4888 4889 usb_syncmem(&sc->sc_fldma, 4890 sizeof(ehci_link_t) * frindex, 4891 sizeof(ehci_link_t), 4892 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4893 4894 itd->itd.itd_next = sc->sc_flist[frindex]; 4895 if (itd->itd.itd_next == 0) 4896 /* 4897 * FIXME: frindex table gets initialized to NULL 4898 * or EHCI_NULL? 4899 */ 4900 itd->itd.itd_next = EHCI_NULL; 4901 4902 usb_syncmem(&itd->dma, 4903 itd->offs + offsetof(ehci_itd_t, itd_next), 4904 sizeof(itd->itd.itd_next), 4905 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4906 4907 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4908 4909 usb_syncmem(&sc->sc_fldma, 4910 sizeof(ehci_link_t) * frindex, 4911 sizeof(ehci_link_t), 4912 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4913 4914 itd->frame_list.next = sc->sc_softitds[frindex]; 4915 sc->sc_softitds[frindex] = itd; 4916 if (itd->frame_list.next != NULL) 4917 itd->frame_list.next->frame_list.prev = itd; 4918 itd->slot = frindex; 4919 itd->frame_list.prev = NULL; 4920 4921 frindex += i; 4922 if (frindex >= sc->sc_flsize) 4923 frindex -= sc->sc_flsize; 4924 4925 itd = itd->xfer_next; 4926 } 4927 4928 epipe->isoc.cur_xfers++; 4929 epipe->isoc.next_frame = frindex; 4930 4931 ehci_add_intr_list(sc, exfer); 4932 xfer->ux_status = USBD_IN_PROGRESS; 4933 4934 return USBD_IN_PROGRESS; 4935 } 4936 4937 Static void 4938 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4939 { 4940 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4941 4942 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4943 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4944 } 4945 4946 Static void 4947 ehci_device_isoc_close(struct usbd_pipe *pipe) 4948 { 4949 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4950 4951 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4952 } 4953 4954 Static void 4955 ehci_device_isoc_done(struct usbd_xfer *xfer) 4956 { 4957 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4958 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4959 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4960 4961 KASSERT(mutex_owned(&sc->sc_lock)); 4962 4963 epipe->isoc.cur_xfers--; 4964 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4965 if (xfer->ux_length) 4966 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4967 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4968 } 4969
Indexes created Wed Sep 24 05:09:52 GMT 2025