ehci.c revision 1.315.2.5
1 /* $NetBSD: ehci.c,v 1.315.2.5 2025/10/01 17:23:32 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna.com.au), and 11 * Nick Hudson . 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 37 * 38 * The EHCI 1.0 spec can be found at 39 * http://www.intel.com/technology/usb/spec.htm 40 * and the USB 2.0 spec at 41 * http://www.usb.org/developers/docs/ 42 * 43 */ 44 45 /* 46 * TODO: 47 * 1) hold off explorations by companion controllers until ehci has started. 48 * 49 * 2) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 3) Command failures are not recovered correctly. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.315.2.5 2025/10/01 17:23:32 martin Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #ifdef _KERNEL_OPT 63 #include "opt_usb.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #include <sys/bus.h> 69 #include <sys/cpu.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/kmem.h> 73 #include <sys/mutex.h> 74 #include <sys/proc.h> 75 #include <sys/queue.h> 76 #include <sys/select.h> 77 #include <sys/sysctl.h> 78 #include <sys/systm.h> 79 #include <sys/reboot.h> 80 81 #include <machine/endian.h> 82 83 #include <dev/usb/usb.h> 84 #include <dev/usb/usbdi.h> 85 #include <dev/usb/usbdivar.h> 86 #include <dev/usb/usbhist.h> 87 #include <dev/usb/usb_mem.h> 88 #include <dev/usb/usb_quirks.h> 89 90 #include <dev/usb/ehcireg.h> 91 #include <dev/usb/ehcivar.h> 92 #include <dev/usb/usbroothub.h> 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 static int ehcidebug = 0; 99 100 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 101 { 102 int err; 103 const struct sysctlnode *rnode; 104 const struct sysctlnode *cnode; 105 106 err = sysctl_createv(clog, 0, NULL, &rnode, 107 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 108 SYSCTL_DESCR("ehci global controls"), 109 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 110 111 if (err) 112 goto fail; 113 114 /* control debugging printfs */ 115 err = sysctl_createv(clog, 0, &rnode, &cnode, 116 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 117 "debug", SYSCTL_DESCR("Enable debugging output"), 118 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 119 if (err) 120 goto fail; 121 122 return; 123 fail: 124 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 125 } 126 127 #endif /* EHCI_DEBUG */ 128 #endif /* USB_DEBUG */ 129 130 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 131 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 132 #define EHCIHIST_FUNC() USBHIST_FUNC() 133 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 134 135 struct ehci_pipe { 136 struct usbd_pipe pipe; 137 int nexttoggle; 138 139 ehci_soft_qh_t *sqh; 140 union { 141 /* Control pipe */ 142 struct { 143 usb_dma_t reqdma; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 u_int length; 148 } intr; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 }; 155 }; 156 157 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 158 159 Static usbd_status ehci_open(struct usbd_pipe *); 160 Static void ehci_poll(struct usbd_bus *); 161 Static void ehci_softintr(void *); 162 Static int ehci_intr1(ehci_softc_t *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 164 ex_completeq_t *); 165 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 166 ex_completeq_t *); 167 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 168 ex_completeq_t *); 169 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 170 Static void ehci_intrlist_timeout(void *); 171 Static void ehci_doorbell(void *); 172 Static void ehci_pcd(void *); 173 174 Static struct usbd_xfer * 175 ehci_allocx(struct usbd_bus *, unsigned int); 176 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 177 178 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 179 Static bool ehci_dying(struct usbd_bus *); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abortx(struct usbd_xfer *); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qh_qtd(struct ehci_qh_qtd_t *); 293 Static void ehci_dump_qtd(ehci_qtd_t *); 294 Static void ehci_dump_sqh(ehci_soft_qh_t *); 295 Static void ehci_dump_sitd(struct ehci_soft_itd *); 296 Static void ehci_dump_itds(ehci_soft_itd_t *); 297 Static void ehci_dump_itd(struct ehci_soft_itd *); 298 Static void ehci_dump_exfer(struct ehci_xfer *); 299 #endif 300 301 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 302 303 static inline void 304 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 305 { 306 307 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 308 } 309 310 static inline void 311 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 312 { 313 314 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 315 } 316 317 Static const struct usbd_bus_methods ehci_bus_methods = { 318 .ubm_open = ehci_open, 319 .ubm_softint = ehci_softintr, 320 .ubm_dopoll = ehci_poll, 321 .ubm_allocx = ehci_allocx, 322 .ubm_freex = ehci_freex, 323 .ubm_abortx = ehci_abortx, 324 .ubm_dying = ehci_dying, 325 .ubm_getlock = ehci_get_lock, 326 .ubm_rhctrl = ehci_roothub_ctrl, 327 }; 328 329 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 330 .upm_transfer = ehci_root_intr_transfer, 331 .upm_start = ehci_root_intr_start, 332 .upm_abort = ehci_root_intr_abort, 333 .upm_close = ehci_root_intr_close, 334 .upm_cleartoggle = ehci_noop, 335 .upm_done = ehci_root_intr_done, 336 }; 337 338 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 339 .upm_init = ehci_device_ctrl_init, 340 .upm_fini = ehci_device_ctrl_fini, 341 .upm_transfer = ehci_device_ctrl_transfer, 342 .upm_start = ehci_device_ctrl_start, 343 .upm_abort = ehci_device_ctrl_abort, 344 .upm_close = ehci_device_ctrl_close, 345 .upm_cleartoggle = ehci_noop, 346 .upm_done = ehci_device_ctrl_done, 347 }; 348 349 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 350 .upm_init = ehci_device_intr_init, 351 .upm_fini = ehci_device_intr_fini, 352 .upm_transfer = ehci_device_intr_transfer, 353 .upm_start = ehci_device_intr_start, 354 .upm_abort = ehci_device_intr_abort, 355 .upm_close = ehci_device_intr_close, 356 .upm_cleartoggle = ehci_device_clear_toggle, 357 .upm_done = ehci_device_intr_done, 358 }; 359 360 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 361 .upm_init = ehci_device_bulk_init, 362 .upm_fini = ehci_device_bulk_fini, 363 .upm_transfer = ehci_device_bulk_transfer, 364 .upm_start = ehci_device_bulk_start, 365 .upm_abort = ehci_device_bulk_abort, 366 .upm_close = ehci_device_bulk_close, 367 .upm_cleartoggle = ehci_device_clear_toggle, 368 .upm_done = ehci_device_bulk_done, 369 }; 370 371 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 372 .upm_init = ehci_device_isoc_init, 373 .upm_fini = ehci_device_isoc_fini, 374 .upm_transfer = ehci_device_isoc_transfer, 375 .upm_abort = ehci_device_isoc_abort, 376 .upm_close = ehci_device_isoc_close, 377 .upm_cleartoggle = ehci_noop, 378 .upm_done = ehci_device_isoc_done, 379 }; 380 381 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 382 .upm_init = ehci_device_fs_isoc_init, 383 .upm_fini = ehci_device_fs_isoc_fini, 384 .upm_transfer = ehci_device_fs_isoc_transfer, 385 .upm_abort = ehci_device_fs_isoc_abort, 386 .upm_close = ehci_device_fs_isoc_close, 387 .upm_cleartoggle = ehci_noop, 388 .upm_done = ehci_device_fs_isoc_done, 389 }; 390 391 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 392 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 393 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 394 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 395 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 396 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 397 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 398 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 399 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 400 }; 401 402 int 403 ehci_init(ehci_softc_t *sc) 404 { 405 uint32_t vers, hcr; 406 u_int i; 407 int err; 408 ehci_soft_qh_t *sqh; 409 u_int ncomp; 410 411 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 412 #ifdef EHCI_DEBUG 413 theehci = sc; 414 #endif 415 416 mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE); 417 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 418 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 419 cv_init(&sc->sc_doorbell, "ehcidb"); 420 421 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 422 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 423 424 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 425 ehci_doorbell, sc); 426 KASSERT(sc->sc_doorbell_si != NULL); 427 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 428 ehci_pcd, sc); 429 KASSERT(sc->sc_pcd_si != NULL); 430 431 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 432 433 vers = EREAD2(sc, EHCI_HCIVERSION); 434 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 435 vers >> 8, vers & 0xff); 436 437 const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS); 438 DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0); 439 sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams); 440 ncomp = EHCI_HCS_N_CC(hcsparams); 441 if (ncomp != sc->sc_ncomp) { 442 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 443 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 444 #if NOHCI == 0 || NUHCI == 0 445 aprint_error("%s: ohci or uhci probably not configured\n", 446 device_xname(sc->sc_dev)); 447 #endif 448 if (ncomp < sc->sc_ncomp) 449 sc->sc_ncomp = ncomp; 450 } 451 if (sc->sc_ncomp > 0) { 452 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 453 aprint_normal_dev(sc->sc_dev, 454 "%d companion controller%s, %d port%s%s", 455 sc->sc_ncomp, 456 sc->sc_ncomp!=1 ? "s" : "", 457 EHCI_HCS_N_PCC(hcsparams), 458 EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "", 459 sc->sc_ncomp!=1 ? " each" : ""); 460 if (sc->sc_comps[0]) { 461 aprint_normal(":"); 462 for (i = 0; i < sc->sc_ncomp; i++) 463 aprint_normal(" %s", 464 device_xname(sc->sc_comps[i])); 465 } 466 aprint_normal("\n"); 467 468 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 469 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 470 cv_init(&sc->sc_compcv, "ehciccv"); 471 sc->sc_comp_state = CO_EARLY; 472 } 473 sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams); 474 sc->sc_hasppc = EHCI_HCS_PPC(hcsparams); 475 476 const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS); 477 DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0); 478 479 if (EHCI_HCC_64BIT(hccparams)) { 480 /* MUST clear segment register if 64 bit capable. */ 481 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 482 } 483 484 if (hccparams & EHCI_HCC_IST_FULLFRAME) { 485 sc->sc_istthreshold = 0; 486 } else { 487 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams); 488 } 489 490 sc->sc_bus.ub_revision = USBREV_2_0; 491 sc->sc_bus.ub_usedma = true; 492 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 493 494 /* 495 * The bus attachment code will possibly provide a 64bit DMA 496 * tag which we now limit to the bottom 4G range as 497 * 498 * - that's as much as ehci can address in its QH, TD, iTD, and siTD 499 * structures; and 500 * - the driver doesn't currently set EHCI_CTRLDSSEGMENT to anything 501 * other than 0. 502 */ 503 bus_dma_tag_t ntag = sc->sc_bus.ub_dmatag; 504 sc->sc_dmatag = sc->sc_bus.ub_dmatag; 505 err = bus_dmatag_subregion(sc->sc_bus.ub_dmatag, 0, UINT32_MAX, 506 &ntag, 0); 507 if (err == 0) { 508 sc->sc_dmatag = ntag; 509 aprint_normal_dev(sc->sc_dev, "Using DMA subregion for control" 510 " data structures\n"); 511 } 512 513 /* Reset the controller */ 514 DPRINTF("resetting", 0, 0, 0, 0); 515 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 516 usb_delay_ms(&sc->sc_bus, 1); 517 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 518 for (i = 0; i < 100; i++) { 519 usb_delay_ms(&sc->sc_bus, 1); 520 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 521 if (!hcr) 522 break; 523 } 524 if (hcr) { 525 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 526 err = EIO; 527 goto fail1; 528 } 529 if (sc->sc_vendor_init) 530 sc->sc_vendor_init(sc); 531 532 /* XXX need proper intr scheduling */ 533 sc->sc_rand = 96; 534 535 /* frame list size at default, read back what we got and use that */ 536 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 537 case 0: sc->sc_flsize = 1024; break; 538 case 1: sc->sc_flsize = 512; break; 539 case 2: sc->sc_flsize = 256; break; 540 case 3: 541 err = EIO; 542 goto fail1; 543 } 544 err = usb_allocmem(sc->sc_dmatag, 545 sc->sc_flsize * sizeof(ehci_link_t), 546 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 547 if (err) { 548 aprint_error_dev(sc->sc_dev, "failed to allocate frame list\n"); 549 goto fail1; 550 } 551 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 552 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 553 554 for (i = 0; i < sc->sc_flsize; i++) { 555 sc->sc_flist[i] = EHCI_NULL; 556 } 557 558 const bus_addr_t flba = DMAADDR(&sc->sc_fldma, 0); 559 const uint32_t hi32 = BUS_ADDR_HI32(flba); 560 if (hi32 != 0) { 561 aprint_error_dev(sc->sc_dev, "DMA memory segment error (%08x)\n", 562 hi32); 563 goto fail2; 564 } 565 566 const uint32_t lo32 = BUS_ADDR_LO32(flba); 567 EOWRITE4(sc, EHCI_PERIODICLISTBASE, lo32); 568 569 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 570 KM_SLEEP); 571 LIST_INIT(&sc->sc_freeitds); 572 LIST_INIT(&sc->sc_freesitds); 573 TAILQ_INIT(&sc->sc_intrhead); 574 575 /* Set up the bus struct. */ 576 sc->sc_bus.ub_methods = &ehci_bus_methods; 577 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 578 579 sc->sc_eintrs = EHCI_NORMAL_INTRS; 580 581 /* 582 * Allocate the interrupt dummy QHs. These are arranged to give poll 583 * intervals that are powers of 2 times 1ms. 584 */ 585 memset(sc->sc_islots, 0, sizeof(sc->sc_islots)); 586 for (i = 0; i < EHCI_INTRQHS; i++) { 587 sqh = ehci_alloc_sqh(sc); 588 if (sqh == NULL) { 589 err = ENOMEM; 590 goto fail3; 591 } 592 sc->sc_islots[i].sqh = sqh; 593 } 594 for (i = 0; i < EHCI_INTRQHS; i++) { 595 sqh = sc->sc_islots[i].sqh; 596 if (i == 0) { 597 /* The last (1ms) QH terminates. */ 598 sqh->qh.qh_link = EHCI_NULL; 599 sqh->next = NULL; 600 } else { 601 /* Otherwise the next QH has half the poll interval */ 602 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 603 sqh->qh.qh_link = htole32(sqh->next->physaddr | 604 EHCI_LINK_QH); 605 } 606 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 607 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 608 sqh->qh.qh_curqtd = EHCI_NULL; 609 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 610 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 611 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 612 sqh->sqtd = NULL; 613 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 614 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 615 } 616 /* Point the frame list at the last level (128ms). */ 617 for (i = 0; i < sc->sc_flsize; i++) { 618 int j; 619 620 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 621 revbits[i & (EHCI_MAX_POLLRATE-1)]; 622 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 623 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 624 i)].sqh->physaddr); 625 } 626 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 627 BUS_DMASYNC_PREWRITE); 628 629 /* Allocate dummy QH that starts the async list. */ 630 sqh = ehci_alloc_sqh(sc); 631 if (sqh == NULL) { 632 err = ENOMEM; 633 goto fail3; 634 } 635 /* Fill the QH */ 636 sqh->qh.qh_endp = 637 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 638 sqh->qh.qh_link = 639 htole32(sqh->physaddr | EHCI_LINK_QH); 640 sqh->qh.qh_curqtd = EHCI_NULL; 641 sqh->next = NULL; 642 /* Fill the overlay qTD */ 643 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 644 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 645 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 646 sqh->sqtd = NULL; 647 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 648 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 649 #ifdef EHCI_DEBUG 650 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 651 ehci_dump_sqh(sqh); 652 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 653 #endif 654 655 /* Point to async list */ 656 sc->sc_async_head = sqh; 657 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 658 659 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 660 661 /* Turn on controller */ 662 EOWRITE4(sc, EHCI_USBCMD, 663 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 664 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 665 EHCI_CMD_ASE | 666 EHCI_CMD_PSE | 667 EHCI_CMD_RS); 668 669 /* Take over port ownership */ 670 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 671 672 for (i = 0; i < 100; i++) { 673 usb_delay_ms(&sc->sc_bus, 1); 674 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 675 if (!hcr) 676 break; 677 } 678 if (hcr) { 679 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 680 err = EIO; 681 goto fail4; 682 } 683 684 /* Enable interrupts */ 685 DPRINTF("enabling interrupts", 0, 0, 0, 0); 686 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 687 688 return 0; 689 690 fail4: 691 ehci_free_sqh(sc, sc->sc_async_head); 692 693 fail3: 694 for (i = 0; i < EHCI_INTRQHS; i++) { 695 sqh = sc->sc_islots[i].sqh; 696 if (sqh) 697 ehci_free_sqh(sc, sqh); 698 } 699 700 kmem_free(sc->sc_softitds, sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 701 702 fail2: 703 usb_freemem(&sc->sc_fldma); 704 705 fail1: 706 softint_disestablish(sc->sc_doorbell_si); 707 softint_disestablish(sc->sc_pcd_si); 708 mutex_destroy(&sc->sc_rhlock); 709 mutex_destroy(&sc->sc_lock); 710 mutex_destroy(&sc->sc_intr_lock); 711 712 return err; 713 } 714 715 int 716 ehci_intr(void *v) 717 { 718 ehci_softc_t *sc = v; 719 int ret = 0; 720 721 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 722 723 if (sc == NULL) 724 return 0; 725 726 mutex_spin_enter(&sc->sc_intr_lock); 727 728 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 729 goto done; 730 731 /* If we get an interrupt while polling, then just ignore it. */ 732 if (sc->sc_bus.ub_usepolling) { 733 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 734 735 if (intrs) 736 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 737 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 738 goto done; 739 } 740 741 ret = ehci_intr1(sc); 742 743 done: 744 mutex_spin_exit(&sc->sc_intr_lock); 745 return ret; 746 } 747 748 Static int 749 ehci_intr1(ehci_softc_t *sc) 750 { 751 uint32_t intrs, eintrs; 752 753 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 754 755 /* In case the interrupt occurs before initialization has completed. */ 756 if (sc == NULL) { 757 #ifdef DIAGNOSTIC 758 printf("ehci_intr1: sc == NULL\n"); 759 #endif 760 return 0; 761 } 762 763 KASSERT(mutex_owned(&sc->sc_intr_lock)); 764 765 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 766 if (!intrs) 767 return 0; 768 769 eintrs = intrs & sc->sc_eintrs; 770 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 771 EOREAD4(sc, EHCI_USBSTS), eintrs); 772 if (!eintrs) 773 return 0; 774 775 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 776 if (eintrs & EHCI_STS_IAA) { 777 DPRINTF("door bell", 0, 0, 0, 0); 778 kpreempt_disable(); 779 KASSERT(sc->sc_doorbell_si != NULL); 780 softint_schedule(sc->sc_doorbell_si); 781 kpreempt_enable(); 782 eintrs &= ~EHCI_STS_IAA; 783 } 784 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 785 DPRINTF("INT=%jd ERRINT=%jd", 786 eintrs & EHCI_STS_INT ? 1 : 0, 787 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 788 usb_schedsoftintr(&sc->sc_bus); 789 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 790 } 791 if (eintrs & EHCI_STS_HSE) { 792 printf("%s: unrecoverable error, controller halted\n", 793 device_xname(sc->sc_dev)); 794 /* XXX what else */ 795 } 796 if (eintrs & EHCI_STS_PCD) { 797 kpreempt_disable(); 798 KASSERT(sc->sc_pcd_si != NULL); 799 softint_schedule(sc->sc_pcd_si); 800 kpreempt_enable(); 801 eintrs &= ~EHCI_STS_PCD; 802 } 803 804 if (eintrs != 0) { 805 /* Block unprocessed interrupts. */ 806 sc->sc_eintrs &= ~eintrs; 807 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 808 printf("%s: blocking intrs %#x\n", 809 device_xname(sc->sc_dev), eintrs); 810 } 811 812 return 1; 813 } 814 815 Static void 816 ehci_doorbell(void *addr) 817 { 818 ehci_softc_t *sc = addr; 819 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 820 821 mutex_enter(&sc->sc_lock); 822 if (sc->sc_doorbelllwp == NULL) 823 DPRINTF("spurious doorbell interrupt", 0, 0, 0, 0); 824 sc->sc_doorbelllwp = NULL; 825 cv_broadcast(&sc->sc_doorbell); 826 mutex_exit(&sc->sc_lock); 827 } 828 829 Static void 830 ehci_pcd(void *addr) 831 { 832 ehci_softc_t *sc = addr; 833 struct usbd_xfer *xfer; 834 u_char *p; 835 int i, m; 836 837 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 838 839 mutex_enter(&sc->sc_lock); 840 xfer = sc->sc_intrxfer; 841 842 if (xfer == NULL) { 843 /* Just ignore the change. */ 844 goto done; 845 } 846 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 847 848 p = xfer->ux_buf; 849 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 850 memset(p, 0, xfer->ux_length); 851 for (i = 1; i <= m; i++) { 852 /* Pick out CHANGE bits from the status reg. */ 853 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 854 p[i/8] |= 1 << (i%8); 855 if (i % 8 == 7) 856 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 857 } 858 xfer->ux_actlen = xfer->ux_length; 859 xfer->ux_status = USBD_NORMAL_COMPLETION; 860 861 usb_transfer_complete(xfer); 862 863 done: 864 mutex_exit(&sc->sc_lock); 865 } 866 867 Static void 868 ehci_softintr(void *v) 869 { 870 struct usbd_bus *bus = v; 871 ehci_softc_t *sc = EHCI_BUS2SC(bus); 872 struct ehci_xfer *ex, *nextex; 873 874 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 875 876 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 877 878 ex_completeq_t cq; 879 TAILQ_INIT(&cq); 880 881 /* 882 * The only explanation I can think of for why EHCI is as brain dead 883 * as UHCI interrupt-wise is that Intel was involved in both. 884 * An interrupt just tells us that something is done, we have no 885 * clue what, so we need to scan through all active transfers. :-( 886 */ 887 888 /* 889 * ehci_idone will remove transfer from sc->sc_intrhead if it's 890 * complete and add to our cq list 891 * 892 */ 893 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 894 switch (ex->ex_type) { 895 case EX_CTRL: 896 case EX_BULK: 897 case EX_INTR: 898 ehci_check_qh_intr(sc, ex, &cq); 899 break; 900 case EX_ISOC: 901 ehci_check_itd_intr(sc, ex, &cq); 902 break; 903 case EX_FS_ISOC: 904 ehci_check_sitd_intr(sc, ex, &cq); 905 break; 906 default: 907 KASSERT(false); 908 } 909 910 } 911 912 /* 913 * We abuse ex_next for the interrupt and complete lists and 914 * interrupt transfers will get re-added here so use 915 * the _SAFE version of TAILQ_FOREACH. 916 */ 917 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 918 usb_transfer_complete(&ex->ex_xfer); 919 } 920 921 /* Schedule a callout to catch any dropped transactions. */ 922 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 923 !TAILQ_EMPTY(&sc->sc_intrhead)) 924 callout_reset(&sc->sc_tmo_intrlist, 925 hz, ehci_intrlist_timeout, sc); 926 } 927 928 Static void 929 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 930 { 931 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 932 uint32_t status; 933 934 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 935 936 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 937 938 if (ex->ex_type == EX_CTRL) { 939 fsqtd = ex->ex_setup; 940 lsqtd = ex->ex_status; 941 } else { 942 fsqtd = ex->ex_sqtdstart; 943 lsqtd = ex->ex_sqtdend; 944 } 945 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 946 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 947 948 /* 949 * If the last TD is still active we need to check whether there 950 * is an error somewhere in the middle, or whether there was a 951 * short packet (SPD and not ACTIVE). 952 */ 953 usb_syncmem(&lsqtd->dma, 954 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 955 sizeof(lsqtd->qtd.qtd_status), 956 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 957 status = le32toh(lsqtd->qtd.qtd_status); 958 usb_syncmem(&lsqtd->dma, 959 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 960 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 961 if (status & EHCI_QTD_ACTIVE) { 962 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 963 964 /* last qTD has already been checked */ 965 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 966 usb_syncmem(&sqtd->dma, 967 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 968 sizeof(sqtd->qtd.qtd_status), 969 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 970 status = le32toh(sqtd->qtd.qtd_status); 971 usb_syncmem(&sqtd->dma, 972 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 973 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 974 /* If there's an active QTD the xfer isn't done. */ 975 if (status & EHCI_QTD_ACTIVE) 976 break; 977 /* Any kind of error makes the xfer done. */ 978 if (status & EHCI_QTD_HALTED) 979 goto done; 980 /* Handle short packets */ 981 if (EHCI_QTD_GET_BYTES(status) != 0) { 982 /* 983 * If we get here for a control transfer then 984 * we need to let the hardware complete the 985 * status phase. That is, we're not done 986 * quite yet. 987 * 988 * Otherwise, we're done. 989 */ 990 if (ex->ex_type == EX_CTRL) { 991 break; 992 } 993 goto done; 994 } 995 } 996 DPRINTFN(10, "ex=%#jx std=%#jx still active", 997 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 998 #ifdef EHCI_DEBUG 999 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 1000 ehci_dump_sqtds(ex->ex_sqtdstart); 1001 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 1002 #endif 1003 return; 1004 } 1005 done: 1006 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1007 ehci_idone(ex, cq); 1008 } 1009 1010 Static void 1011 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1012 { 1013 ehci_soft_itd_t *itd; 1014 int i; 1015 1016 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1017 1018 KASSERT(mutex_owned(&sc->sc_lock)); 1019 1020 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1021 return; 1022 1023 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 1024 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 1025 1026 itd = ex->ex_itdend; 1027 1028 /* 1029 * check no active transfers in last itd, meaning we're finished 1030 */ 1031 1032 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1033 sizeof(itd->itd.itd_ctl), 1034 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1035 1036 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1037 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 1038 break; 1039 } 1040 1041 if (i == EHCI_ITD_NUFRAMES) { 1042 goto done; /* All 8 descriptors inactive, it's done */ 1043 } 1044 1045 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1046 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1047 1048 DPRINTFN(10, "ex %#jx itd %#jx still active", 1049 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 1050 return; 1051 done: 1052 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 1053 ehci_idone(ex, cq); 1054 } 1055 1056 void 1057 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1058 { 1059 ehci_soft_sitd_t *sitd; 1060 1061 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1062 1063 KASSERT(mutex_owned(&sc->sc_lock)); 1064 1065 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1066 return; 1067 1068 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1069 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1070 1071 sitd = ex->ex_sitdend; 1072 1073 /* 1074 * check no active transfers in last sitd, meaning we're finished 1075 */ 1076 1077 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1078 sizeof(sitd->sitd.sitd_trans), 1079 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1080 1081 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1082 1083 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1084 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1085 1086 if (active) 1087 return; 1088 1089 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1090 ehci_idone(ex, cq); 1091 } 1092 1093 Static void 1094 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1095 { 1096 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1097 struct usbd_xfer *xfer = &ex->ex_xfer; 1098 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1099 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1100 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1101 uint32_t status = 0, nstatus = 0; 1102 int actlen = 0; 1103 1104 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1105 1106 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1107 1108 /* 1109 * Try to claim this xfer for completion. If it has already 1110 * completed or aborted, drop it on the floor. 1111 */ 1112 if (!usbd_xfer_trycomplete(xfer)) 1113 return; 1114 1115 #ifdef DIAGNOSTIC 1116 #ifdef EHCI_DEBUG 1117 if (ex->ex_isdone) { 1118 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1119 ehci_dump_exfer(ex); 1120 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1121 } 1122 #endif 1123 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1124 ex->ex_type, xfer->ux_status); 1125 ex->ex_isdone = true; 1126 #endif 1127 1128 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1129 (uintptr_t)epipe, 0, 0); 1130 1131 /* The transfer is done, compute actual length and status. */ 1132 if (ex->ex_type == EX_ISOC) { 1133 /* HS isoc transfer */ 1134 1135 struct ehci_soft_itd *itd; 1136 int i, nframes, len, uframes; 1137 1138 nframes = 0; 1139 1140 #ifdef EHCI_DEBUG 1141 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1142 ehci_dump_itds(ex->ex_itdstart); 1143 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1144 #endif 1145 1146 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1147 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1148 1149 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1150 usb_syncmem(&itd->dma, 1151 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1152 sizeof(itd->itd.itd_ctl), 1153 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1154 1155 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1156 /* 1157 * XXX - driver didn't fill in the frame full 1158 * of uframes. This leads to scheduling 1159 * inefficiencies, but working around 1160 * this doubles complexity of tracking 1161 * an xfer. 1162 */ 1163 if (nframes >= xfer->ux_nframes) 1164 break; 1165 1166 status = le32toh(itd->itd.itd_ctl[i]); 1167 len = EHCI_ITD_GET_LEN(status); 1168 if (EHCI_ITD_GET_STATUS(status) != 0) 1169 len = 0; /*No valid data on error*/ 1170 1171 xfer->ux_frlengths[nframes++] = len; 1172 actlen += len; 1173 } 1174 usb_syncmem(&itd->dma, 1175 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1176 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1177 1178 if (nframes >= xfer->ux_nframes) 1179 break; 1180 } 1181 1182 xfer->ux_actlen = actlen; 1183 xfer->ux_status = USBD_NORMAL_COMPLETION; 1184 goto end; 1185 } else if (ex->ex_type == EX_FS_ISOC) { 1186 /* FS isoc transfer */ 1187 struct ehci_soft_sitd *sitd; 1188 int nframes, len; 1189 1190 nframes = 0; 1191 1192 for (sitd = ex->ex_sitdstart; sitd != NULL; 1193 sitd = sitd->xfer_next) { 1194 usb_syncmem(&sitd->dma, 1195 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1196 sizeof(sitd->sitd.sitd_trans), 1197 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1198 1199 /* 1200 * XXX - driver didn't fill in the frame full 1201 * of uframes. This leads to scheduling 1202 * inefficiencies, but working around 1203 * this doubles complexity of tracking 1204 * an xfer. 1205 */ 1206 if (nframes >= xfer->ux_nframes) 1207 break; 1208 1209 status = le32toh(sitd->sitd.sitd_trans); 1210 usb_syncmem(&sitd->dma, 1211 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1212 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1213 1214 len = EHCI_SITD_GET_LEN(status); 1215 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1216 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1217 /* No valid data on error */ 1218 len = xfer->ux_frlengths[nframes]; 1219 } 1220 1221 /* 1222 * frlengths[i]: # of bytes to send 1223 * len: # of bytes host didn't send 1224 */ 1225 xfer->ux_frlengths[nframes] -= len; 1226 /* frlengths[i]: # of bytes host sent */ 1227 actlen += xfer->ux_frlengths[nframes++]; 1228 1229 if (nframes >= xfer->ux_nframes) 1230 break; 1231 } 1232 1233 xfer->ux_actlen = actlen; 1234 xfer->ux_status = USBD_NORMAL_COMPLETION; 1235 goto end; 1236 } 1237 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1238 ex->ex_type == EX_BULK); 1239 1240 /* Continue processing xfers using queue heads */ 1241 if (ex->ex_type == EX_CTRL) { 1242 fsqtd = ex->ex_setup; 1243 lsqtd = ex->ex_status; 1244 } else { 1245 fsqtd = ex->ex_sqtdstart; 1246 lsqtd = ex->ex_sqtdend; 1247 } 1248 #ifdef EHCI_DEBUG 1249 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1250 ehci_dump_sqtds(fsqtd); 1251 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1252 #endif 1253 1254 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1255 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1256 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1257 nstatus = le32toh(sqtd->qtd.qtd_status); 1258 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1259 BUS_DMASYNC_PREREAD); 1260 if (nstatus & EHCI_QTD_ACTIVE) 1261 break; 1262 1263 status = nstatus; 1264 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1265 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1266 } 1267 1268 /* 1269 * If there are left over TDs we need to update the toggle. 1270 * The default pipe doesn't need it since control transfers 1271 * start the toggle at 0 every time. 1272 * For a short transfer we need to update the toggle for the missing 1273 * packets within the qTD. 1274 */ 1275 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1276 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1277 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1278 status, nstatus, 0, 0); 1279 #if 0 1280 ehci_dump_sqh(epipe->sqh); 1281 ehci_dump_sqtds(ex->ex_sqtdstart); 1282 #endif 1283 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1284 } 1285 1286 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1287 status, 0); 1288 xfer->ux_actlen = actlen; 1289 if (status & EHCI_QTD_HALTED) { 1290 #ifdef EHCI_DEBUG 1291 DPRINTF("halted addr=%jd endpt=0x%02jx", 1292 xfer->ux_pipe->up_dev->ud_addr, 1293 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1294 0, 0); 1295 DPRINTF("cerr=%jd pid=%jd", 1296 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1297 0, 0); 1298 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1299 status & EHCI_QTD_ACTIVE ? 1 : 0, 1300 status & EHCI_QTD_HALTED ? 1 : 0, 1301 status & EHCI_QTD_BUFERR ? 1 : 0, 1302 status & EHCI_QTD_BABBLE ? 1 : 0); 1303 1304 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1305 status & EHCI_QTD_XACTERR ? 1 : 0, 1306 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1307 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1308 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1309 1310 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1311 ehci_dump_sqh(epipe->sqh); 1312 ehci_dump_sqtds(ex->ex_sqtdstart); 1313 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1314 #endif 1315 /* low&full speed has an extra error flag */ 1316 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1317 EHCI_QH_SPEED_HIGH) 1318 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1319 else 1320 status &= EHCI_QTD_STATERRS; 1321 if (status == 0) /* no other errors means a stall */ { 1322 xfer->ux_status = USBD_STALLED; 1323 } else { 1324 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1325 } 1326 /* XXX need to reset TT on missed microframe */ 1327 if (status & EHCI_QTD_MISSEDMICRO) { 1328 printf("%s: missed microframe, TT reset not " 1329 "implemented, hub might be inoperational\n", 1330 device_xname(sc->sc_dev)); 1331 } 1332 } else { 1333 xfer->ux_status = USBD_NORMAL_COMPLETION; 1334 } 1335 1336 end: 1337 1338 ehci_del_intr_list(sc, ex); 1339 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1340 1341 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1342 } 1343 1344 Static void 1345 ehci_poll(struct usbd_bus *bus) 1346 { 1347 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1348 1349 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1350 1351 #ifdef EHCI_DEBUG 1352 static int last; 1353 int new; 1354 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1355 if (new != last) { 1356 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1357 last = new; 1358 } 1359 #endif 1360 1361 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1362 mutex_spin_enter(&sc->sc_intr_lock); 1363 ehci_intr1(sc); 1364 mutex_spin_exit(&sc->sc_intr_lock); 1365 } 1366 } 1367 1368 void 1369 ehci_childdet(device_t self, device_t child) 1370 { 1371 struct ehci_softc *sc = device_private(self); 1372 1373 KASSERT(sc->sc_child == child); 1374 sc->sc_child = NULL; 1375 } 1376 1377 int 1378 ehci_detach(struct ehci_softc *sc, int flags) 1379 { 1380 int rv = 0; 1381 1382 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1383 1384 if (sc->sc_child != NULL) { 1385 rv = config_detach(sc->sc_child, flags); 1386 if (rv != 0) 1387 return rv; 1388 } 1389 1390 if (sc->sc_ncomp > 0) { 1391 mutex_enter(&sc->sc_complock); 1392 /* XXX try to halt callout instead of waiting */ 1393 while (sc->sc_comp_state == CO_SCHED) 1394 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1395 mutex_exit(&sc->sc_complock); 1396 1397 callout_halt(&sc->sc_compcallout, NULL); 1398 callout_destroy(&sc->sc_compcallout); 1399 cv_destroy(&sc->sc_compcv); 1400 mutex_destroy(&sc->sc_complock); 1401 } 1402 1403 callout_halt(&sc->sc_tmo_intrlist, NULL); 1404 callout_destroy(&sc->sc_tmo_intrlist); 1405 1406 /* XXX free other data structures */ 1407 if (sc->sc_softitds) { 1408 kmem_free(sc->sc_softitds, 1409 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1410 } 1411 cv_destroy(&sc->sc_doorbell); 1412 1413 #if 0 1414 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1415 softint_disestablish(sc->sc_doorbell_si); 1416 softint_disestablish(sc->sc_pcd_si); 1417 mutex_destroy(&sc->sc_rhlock); 1418 mutex_destroy(&sc->sc_lock); 1419 mutex_destroy(&sc->sc_intr_lock); 1420 #endif 1421 1422 pool_cache_destroy(sc->sc_xferpool); 1423 1424 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1425 1426 return rv; 1427 } 1428 1429 int 1430 ehci_activate(device_t self, enum devact act) 1431 { 1432 struct ehci_softc *sc = device_private(self); 1433 1434 switch (act) { 1435 case DVACT_DEACTIVATE: 1436 sc->sc_dying = 1; 1437 return 0; 1438 default: 1439 return EOPNOTSUPP; 1440 } 1441 } 1442 1443 /* 1444 * Handle suspend/resume. 1445 * 1446 * Note that this power handler isn't to be registered directly; the 1447 * bus glue needs to call out to it. 1448 */ 1449 bool 1450 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1451 { 1452 ehci_softc_t *sc = device_private(dv); 1453 int i; 1454 uint32_t cmd, hcr; 1455 1456 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1457 1458 mutex_enter(&sc->sc_rhlock); 1459 1460 for (i = 1; i <= sc->sc_noport; i++) { 1461 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1462 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1463 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1464 } 1465 1466 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1467 1468 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1469 EOWRITE4(sc, EHCI_USBCMD, cmd); 1470 1471 for (i = 0; i < 100; i++) { 1472 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1473 if (hcr == 0) 1474 break; 1475 1476 usb_delay_ms(&sc->sc_bus, 1); 1477 } 1478 if (hcr != 0) 1479 printf("%s: reset timeout\n", device_xname(dv)); 1480 1481 cmd &= ~EHCI_CMD_RS; 1482 EOWRITE4(sc, EHCI_USBCMD, cmd); 1483 1484 for (i = 0; i < 100; i++) { 1485 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1486 if (hcr == EHCI_STS_HCH) 1487 break; 1488 1489 usb_delay_ms(&sc->sc_bus, 1); 1490 } 1491 if (hcr != EHCI_STS_HCH) 1492 printf("%s: config timeout\n", device_xname(dv)); 1493 1494 mutex_exit(&sc->sc_rhlock); 1495 1496 return true; 1497 } 1498 1499 bool 1500 ehci_resume(device_t dv, const pmf_qual_t *qual) 1501 { 1502 ehci_softc_t *sc = device_private(dv); 1503 int i; 1504 uint32_t cmd, hcr; 1505 1506 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1507 1508 mutex_enter(&sc->sc_rhlock); 1509 1510 /* restore things in case the bios sucks */ 1511 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1512 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1513 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1514 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1515 1516 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1517 1518 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1519 1520 hcr = 0; 1521 for (i = 1; i <= sc->sc_noport; i++) { 1522 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1523 if ((cmd & EHCI_PS_PO) == 0 && 1524 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1525 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1526 hcr = 1; 1527 } 1528 } 1529 1530 if (hcr) { 1531 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1532 1533 for (i = 1; i <= sc->sc_noport; i++) { 1534 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1535 if ((cmd & EHCI_PS_PO) == 0 && 1536 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1537 EOWRITE4(sc, EHCI_PORTSC(i), 1538 cmd & ~EHCI_PS_FPR); 1539 } 1540 } 1541 1542 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1543 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1544 1545 for (i = 0; i < 100; i++) { 1546 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1547 if (hcr != EHCI_STS_HCH) 1548 break; 1549 1550 usb_delay_ms(&sc->sc_bus, 1); 1551 } 1552 if (hcr == EHCI_STS_HCH) 1553 printf("%s: config timeout\n", device_xname(dv)); 1554 1555 mutex_exit(&sc->sc_rhlock); 1556 1557 return true; 1558 } 1559 1560 /* 1561 * Shut down the controller when the system is going down. 1562 */ 1563 bool 1564 ehci_shutdown(device_t self, int flags) 1565 { 1566 ehci_softc_t *sc = device_private(self); 1567 1568 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1569 1570 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1571 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1572 return true; 1573 } 1574 1575 Static struct usbd_xfer * 1576 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1577 { 1578 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1579 struct usbd_xfer *xfer; 1580 1581 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1582 if (xfer != NULL) { 1583 memset(xfer, 0, sizeof(struct ehci_xfer)); 1584 1585 #ifdef DIAGNOSTIC 1586 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1587 ex->ex_isdone = true; 1588 xfer->ux_state = XFER_BUSY; 1589 #endif 1590 } 1591 return xfer; 1592 } 1593 1594 Static void 1595 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1596 { 1597 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1598 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1599 1600 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1601 xfer->ux_status == USBD_NOT_STARTED, 1602 "xfer %p state %d\n", xfer, xfer->ux_state); 1603 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1604 1605 #ifdef DIAGNOSTIC 1606 xfer->ux_state = XFER_FREE; 1607 #endif 1608 1609 pool_cache_put(sc->sc_xferpool, xfer); 1610 } 1611 1612 Static bool 1613 ehci_dying(struct usbd_bus *bus) 1614 { 1615 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1616 1617 return sc->sc_dying; 1618 } 1619 1620 Static void 1621 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1622 { 1623 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1624 1625 *lock = &sc->sc_lock; 1626 } 1627 1628 Static void 1629 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1630 { 1631 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1632 1633 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1634 1635 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1636 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1637 #ifdef EHCI_DEBUG 1638 if (ehcidebug) 1639 usbd_dump_pipe(pipe); 1640 #endif 1641 epipe->nexttoggle = 0; 1642 } 1643 1644 Static void 1645 ehci_noop(struct usbd_pipe *pipe) 1646 { 1647 } 1648 1649 #ifdef EHCI_DEBUG 1650 /* 1651 * Unused function - this is meant to be called from a kernel 1652 * debugger. 1653 */ 1654 void 1655 ehci_dump(void) 1656 { 1657 ehci_softc_t *sc = theehci; 1658 int i; 1659 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1660 EOREAD4(sc, EHCI_USBCMD), 1661 EOREAD4(sc, EHCI_USBSTS), 1662 EOREAD4(sc, EHCI_USBINTR)); 1663 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1664 EOREAD4(sc, EHCI_FRINDEX), 1665 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1666 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1667 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1668 for (i = 1; i <= sc->sc_noport; i++) 1669 printf("port %d status=0x%08x\n", i, 1670 EOREAD4(sc, EHCI_PORTSC(i))); 1671 } 1672 1673 Static void 1674 ehci_dump_regs(ehci_softc_t *sc) 1675 { 1676 int i; 1677 1678 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1679 1680 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1681 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1682 EOREAD4(sc, EHCI_USBINTR), 0); 1683 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1684 "async = 0x%08jx", 1685 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1686 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1687 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1688 for (i = 1; i <= sc->sc_noport; i += 2) { 1689 if (i == sc->sc_noport) { 1690 DPRINTF("port %jd status = 0x%08jx", i, 1691 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1692 } else { 1693 DPRINTF("port %jd status = 0x%08jx port %jd " 1694 "status = 0x%08jx", 1695 i, EOREAD4(sc, EHCI_PORTSC(i)), 1696 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1697 } 1698 } 1699 } 1700 1701 #define ehci_dump_link(link, type) do { \ 1702 DPRINTF(" link 0x%08jx (T = %jd):", \ 1703 link, \ 1704 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1705 if (type) { \ 1706 DPRINTF( \ 1707 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1708 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1709 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1710 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1711 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1712 } \ 1713 } while(0) 1714 1715 Static void 1716 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1717 { 1718 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1719 int i; 1720 uint32_t stop = 0; 1721 1722 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1723 ehci_dump_sqtd(sqtd); 1724 usb_syncmem(&sqtd->dma, 1725 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1726 sizeof(sqtd->qtd), 1727 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1728 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1729 usb_syncmem(&sqtd->dma, 1730 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1731 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1732 } 1733 if (!stop) 1734 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1735 } 1736 1737 Static void 1738 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1739 { 1740 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1741 1742 usb_syncmem(&sqtd->dma, sqtd->offs, 1743 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1744 1745 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1746 0, 0); 1747 ehci_dump_qtd(&sqtd->qtd); 1748 1749 usb_syncmem(&sqtd->dma, sqtd->offs, 1750 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1751 } 1752 1753 Static void 1754 ehci_dump_qh_qtd(struct ehci_qh_qtd_t *qh_qtd) 1755 { 1756 ehci_qtd_t qtd = { 1757 .qtd_next = qh_qtd->qtd_next, 1758 .qtd_altnext = qh_qtd->qtd_altnext, 1759 .qtd_status = qh_qtd->qtd_status, 1760 }; 1761 1762 /* Manually memcpy(), because of volatile. */ 1763 for (unsigned i = 0; i < EHCI_QTD_NBUFFERS; i++) { 1764 qtd.qtd_buffer[i] = qh_qtd->qtd_buffer[i]; 1765 qtd.qtd_buffer_hi[i] = qh_qtd->qtd_buffer_hi[i]; 1766 } 1767 1768 ehci_dump_qtd(&qtd); 1769 } 1770 1771 Static void 1772 ehci_dump_qtd(ehci_qtd_t *qtd) 1773 { 1774 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1775 uint32_t s = le32toh(qtd->qtd_status); 1776 1777 DPRINTFN(10, 1778 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1779 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1780 DPRINTFN(10, 1781 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1782 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1783 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1784 DPRINTFN(10, 1785 " cerr = %jd pid = %jd stat = %jx", 1786 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1787 0); 1788 DPRINTFN(10, 1789 "active =%jd halted=%jd buferr=%jd babble=%jd", 1790 s & EHCI_QTD_ACTIVE ? 1 : 0, 1791 s & EHCI_QTD_HALTED ? 1 : 0, 1792 s & EHCI_QTD_BUFERR ? 1 : 0, 1793 s & EHCI_QTD_BABBLE ? 1 : 0); 1794 DPRINTFN(10, 1795 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1796 s & EHCI_QTD_XACTERR ? 1 : 0, 1797 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1798 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1799 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1800 DPRINTFN(10, 1801 "buffer[0] = %#jx buffer[1] = %#jx " 1802 "buffer[2] = %#jx buffer[3] = %#jx", 1803 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1804 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1805 DPRINTFN(10, 1806 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1807 } 1808 1809 Static void 1810 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1811 { 1812 ehci_qh_t *qh = &sqh->qh; 1813 ehci_link_t link; 1814 uint32_t endp, endphub; 1815 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1816 1817 usb_syncmem(&sqh->dma, sqh->offs, 1818 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1819 1820 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1821 link = le32toh(qh->qh_link); 1822 ehci_dump_link(link, true); 1823 1824 endp = le32toh(qh->qh_endp); 1825 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1826 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1827 "eps = %jd", 1828 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1829 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1830 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1831 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1832 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1833 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1834 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1835 1836 endphub = le32toh(qh->qh_endphub); 1837 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1838 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1839 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1840 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1841 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1842 EHCI_QH_GET_MULT(endphub), 0); 1843 1844 link = le32toh(qh->qh_curqtd); 1845 ehci_dump_link(link, false); 1846 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1847 ehci_dump_qh_qtd(&qh->qh_qtd); 1848 1849 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1850 BUS_DMASYNC_PREREAD); 1851 } 1852 1853 Static void 1854 ehci_dump_itds(ehci_soft_itd_t *itd) 1855 { 1856 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1857 int i; 1858 uint32_t stop = 0; 1859 1860 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1861 ehci_dump_itd(itd); 1862 usb_syncmem(&itd->dma, 1863 itd->offs + offsetof(ehci_itd_t, itd_next), 1864 sizeof(itd->itd), 1865 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1866 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1867 usb_syncmem(&itd->dma, 1868 itd->offs + offsetof(ehci_itd_t, itd_next), 1869 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1870 } 1871 if (!stop) 1872 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1873 } 1874 1875 Static void 1876 ehci_dump_itd(struct ehci_soft_itd *itd) 1877 { 1878 ehci_isoc_trans_t t; 1879 ehci_isoc_bufr_ptr_t b, b2, b3; 1880 int i; 1881 1882 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1883 1884 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1885 1886 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1887 t = le32toh(itd->itd.itd_ctl[i]); 1888 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1889 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1890 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1891 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1892 EHCI_ITD_GET_OFFS(t), 0); 1893 } 1894 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1895 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1896 DPRINTF(" %jx", 1897 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1898 1899 b = le32toh(itd->itd.itd_bufr[0]); 1900 b2 = le32toh(itd->itd.itd_bufr[1]); 1901 b3 = le32toh(itd->itd.itd_bufr[2]); 1902 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1903 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1904 DPRINTF(" maxpkt = %jx multi = %jx", 1905 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1906 } 1907 1908 Static void 1909 ehci_dump_sitd(struct ehci_soft_itd *itd) 1910 { 1911 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1912 1913 DPRINTF("SITD %#jx next = %p prev = %#jx", 1914 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1915 (uintptr_t)itd->frame_list.prev, 0); 1916 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1917 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1918 } 1919 1920 Static void 1921 ehci_dump_exfer(struct ehci_xfer *ex) 1922 { 1923 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1924 1925 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1926 ex->ex_isdone, 0); 1927 1928 switch (ex->ex_type) { 1929 case EX_CTRL: 1930 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1931 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1932 (uintptr_t)ex->ex_status, 0); 1933 break; 1934 case EX_BULK: 1935 case EX_INTR: 1936 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1937 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1938 0, 0); 1939 break; 1940 case EX_ISOC: 1941 DPRINTF(" itdstart = %#jx itdend = %#jx", 1942 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1943 break; 1944 case EX_FS_ISOC: 1945 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1946 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1947 0, 0); 1948 break; 1949 default: 1950 DPRINTF(" unknown type", 0, 0, 0, 0); 1951 } 1952 } 1953 #endif 1954 1955 Static usbd_status 1956 ehci_open(struct usbd_pipe *pipe) 1957 { 1958 struct usbd_device *dev = pipe->up_dev; 1959 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1960 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1961 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1962 uint8_t addr = dev->ud_addr; 1963 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1964 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1965 ehci_soft_qh_t *sqh; 1966 usbd_status err; 1967 int ival, speed, naks; 1968 int hshubaddr, hshubport; 1969 1970 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1971 1972 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1973 ed->bEndpointAddress, rhaddr); 1974 1975 if (dev->ud_myhsport) { 1976 /* 1977 * When directly attached FS/LS device while doing embedded 1978 * transaction translations and we are the hub, set the hub 1979 * address to 0 (us). 1980 */ 1981 if (!(sc->sc_flags & EHCIF_ETTF) 1982 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1983 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1984 } else { 1985 hshubaddr = 0; 1986 } 1987 hshubport = dev->ud_myhsport->up_portno; 1988 } else { 1989 hshubaddr = 0; 1990 hshubport = 0; 1991 } 1992 1993 if (sc->sc_dying) 1994 return USBD_IOERROR; 1995 1996 /* toggle state needed for bulk endpoints */ 1997 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1998 1999 if (addr == rhaddr) { 2000 switch (ed->bEndpointAddress) { 2001 case USB_CONTROL_ENDPOINT: 2002 pipe->up_methods = &roothub_ctrl_methods; 2003 break; 2004 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2005 pipe->up_methods = &ehci_root_intr_methods; 2006 break; 2007 default: 2008 DPRINTF("bad bEndpointAddress 0x%02jx", 2009 ed->bEndpointAddress, 0, 0, 0); 2010 return USBD_INVAL; 2011 } 2012 return USBD_NORMAL_COMPLETION; 2013 } 2014 2015 /* XXX All this stuff is only valid for async. */ 2016 switch (dev->ud_speed) { 2017 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 2018 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 2019 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 2020 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 2021 } 2022 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 2023 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 2024 0); 2025 return USBD_INVAL; 2026 } 2027 2028 /* 2029 * For interrupt transfer, nak throttling must be disabled, but for 2030 * the other transfer type, nak throttling should be enabled from the 2031 * viewpoint that avoids the memory thrashing. 2032 */ 2033 naks = (xfertype == UE_INTERRUPT) ? 0 2034 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 2035 2036 /* Allocate sqh for everything, save isoc xfers */ 2037 if (xfertype != UE_ISOCHRONOUS) { 2038 sqh = ehci_alloc_sqh(sc); 2039 if (sqh == NULL) 2040 return USBD_NOMEM; 2041 /* qh_link filled when the QH is added */ 2042 sqh->qh.qh_endp = htole32( 2043 EHCI_QH_SET_ADDR(addr) | 2044 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 2045 EHCI_QH_SET_EPS(speed) | 2046 EHCI_QH_DTC | 2047 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 2048 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 2049 EHCI_QH_CTL : 0) | 2050 EHCI_QH_SET_NRL(naks) 2051 ); 2052 sqh->qh.qh_endphub = htole32( 2053 EHCI_QH_SET_MULT(1) | 2054 (xfertype == UE_INTERRUPT ? 2055 EHCI_QH_SET_SMASK(__BIT(1)) /* Start Split Y1 */ 2056 : 0) 2057 ); 2058 if (speed != EHCI_QH_SPEED_HIGH) 2059 sqh->qh.qh_endphub |= htole32( 2060 EHCI_QH_SET_PORT(hshubport) | 2061 EHCI_QH_SET_HUBA(hshubaddr) | 2062 (xfertype == UE_INTERRUPT ? 2063 EHCI_QH_SET_CMASK(__BITS(3,5)) /* CS Y[345] */ 2064 : 0) 2065 ); 2066 sqh->qh.qh_curqtd = EHCI_NULL; 2067 /* Fill the overlay qTD */ 2068 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2069 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2070 sqh->qh.qh_qtd.qtd_status = htole32(0); 2071 2072 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2073 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2074 epipe->sqh = sqh; 2075 } else { 2076 sqh = NULL; 2077 } /*xfertype == UE_ISOC*/ 2078 2079 switch (xfertype) { 2080 case UE_CONTROL: 2081 /* we can use 64bit DMA for the reqdma buffer */ 2082 err = usb_allocmem(sc->sc_bus.ub_dmatag, 2083 sizeof(usb_device_request_t), 0, USBMALLOC_COHERENT, 2084 &epipe->ctrl.reqdma); 2085 #ifdef EHCI_DEBUG 2086 if (err) 2087 printf("ehci_open: usb_allocmem()=%d\n", err); 2088 #endif 2089 if (err) 2090 goto bad; 2091 pipe->up_methods = &ehci_device_ctrl_methods; 2092 mutex_enter(&sc->sc_lock); 2093 ehci_add_qh(sc, sqh, sc->sc_async_head); 2094 mutex_exit(&sc->sc_lock); 2095 break; 2096 case UE_BULK: 2097 pipe->up_methods = &ehci_device_bulk_methods; 2098 mutex_enter(&sc->sc_lock); 2099 ehci_add_qh(sc, sqh, sc->sc_async_head); 2100 mutex_exit(&sc->sc_lock); 2101 break; 2102 case UE_INTERRUPT: 2103 pipe->up_methods = &ehci_device_intr_methods; 2104 ival = pipe->up_interval; 2105 if (ival == USBD_DEFAULT_INTERVAL) { 2106 if (speed == EHCI_QH_SPEED_HIGH) { 2107 if (ed->bInterval > 16) { 2108 /* 2109 * illegal with high-speed, but there 2110 * were documentation bugs in the spec, 2111 * so be generous 2112 */ 2113 ival = 256; 2114 } else 2115 ival = (1 << (ed->bInterval - 1)) / 8; 2116 } else 2117 ival = ed->bInterval; 2118 } 2119 err = ehci_device_setintr(sc, sqh, ival); 2120 if (err) 2121 goto bad; 2122 break; 2123 case UE_ISOCHRONOUS: 2124 pipe->up_serialise = false; 2125 if (speed == EHCI_QH_SPEED_HIGH) 2126 pipe->up_methods = &ehci_device_isoc_methods; 2127 else 2128 pipe->up_methods = &ehci_device_fs_isoc_methods; 2129 if (ed->bInterval == 0 || ed->bInterval > 16) { 2130 printf("ehci: opening pipe with invalid bInterval\n"); 2131 err = USBD_INVAL; 2132 goto bad; 2133 } 2134 if (UGETW(ed->wMaxPacketSize) == 0) { 2135 printf("ehci: zero length endpoint open request\n"); 2136 err = USBD_INVAL; 2137 goto bad; 2138 } 2139 epipe->isoc.next_frame = 0; 2140 epipe->isoc.cur_xfers = 0; 2141 break; 2142 default: 2143 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2144 err = USBD_INVAL; 2145 goto bad; 2146 } 2147 return USBD_NORMAL_COMPLETION; 2148 2149 bad: 2150 if (sqh != NULL) { 2151 mutex_enter(&sc->sc_lock); 2152 ehci_free_sqh(sc, sqh); 2153 mutex_exit(&sc->sc_lock); 2154 } 2155 return err; 2156 } 2157 2158 /* 2159 * Add an ED to the schedule. Called with USB lock held. 2160 */ 2161 Static void 2162 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2163 { 2164 2165 KASSERT(mutex_owned(&sc->sc_lock)); 2166 2167 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2168 2169 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2170 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2171 2172 sqh->next = head->next; 2173 sqh->qh.qh_link = head->qh.qh_link; 2174 2175 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2176 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2177 2178 head->next = sqh; 2179 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2180 2181 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2182 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2183 2184 #ifdef EHCI_DEBUG 2185 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2186 ehci_dump_sqh(sqh); 2187 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2188 #endif 2189 } 2190 2191 /* 2192 * Remove an ED from the schedule. Called with USB lock held. 2193 */ 2194 Static void 2195 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2196 { 2197 ehci_soft_qh_t *p; 2198 2199 KASSERT(mutex_owned(&sc->sc_lock)); 2200 2201 /* XXX */ 2202 for (p = head; p != NULL && p->next != sqh; p = p->next) 2203 ; 2204 if (p == NULL) 2205 panic("ehci_rem_qh: ED not found"); 2206 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2207 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2208 p->next = sqh->next; 2209 p->qh.qh_link = sqh->qh.qh_link; 2210 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2211 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2212 2213 ehci_sync_hc(sc); 2214 } 2215 2216 Static void 2217 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2218 { 2219 int i; 2220 uint32_t status; 2221 2222 /* Save toggle bit and ping status. */ 2223 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2224 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2225 status = sqh->qh.qh_qtd.qtd_status & 2226 htole32(EHCI_QTD_TOGGLE_MASK | 2227 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2228 /* Set HALTED to make hw leave it alone. */ 2229 sqh->qh.qh_qtd.qtd_status = 2230 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2231 usb_syncmem(&sqh->dma, 2232 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2233 sizeof(sqh->qh.qh_qtd.qtd_status), 2234 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2235 sqh->qh.qh_curqtd = 0; 2236 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2237 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2238 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2239 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2240 sqh->sqtd = sqtd; 2241 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2242 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2243 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2244 sqh->qh.qh_qtd.qtd_status = status; 2245 usb_syncmem(&sqh->dma, 2246 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2247 sizeof(sqh->qh.qh_qtd.qtd_status), 2248 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2249 } 2250 2251 /* 2252 * Ensure that the HC has released all references to the QH. We do this 2253 * by asking for a Async Advance Doorbell interrupt and then we wait for 2254 * the interrupt. 2255 * To make this easier we first obtain exclusive use of the doorbell. 2256 * 2257 * Releases the bus lock to sleep while waiting for interrupt. 2258 */ 2259 Static void 2260 ehci_sync_hc(ehci_softc_t *sc) 2261 { 2262 unsigned delta = hz; 2263 unsigned starttime = getticks(); 2264 unsigned endtime = starttime + delta; 2265 unsigned now; 2266 2267 KASSERT(mutex_owned(&sc->sc_lock)); 2268 2269 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2270 2271 if (sc->sc_dying) { 2272 DPRINTF("dying", 0, 0, 0, 0); 2273 return; 2274 } 2275 2276 /* 2277 * Wait until any concurrent ehci_sync_hc has completed so we 2278 * have exclusive access to the doorbell. 2279 */ 2280 while (sc->sc_doorbelllwp) 2281 cv_wait(&sc->sc_doorbell, &sc->sc_lock); 2282 sc->sc_doorbelllwp = curlwp; 2283 2284 /* ask for doorbell */ 2285 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2286 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2287 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2288 2289 /* 2290 * Wait for the ehci to ring our doorbell. 2291 */ 2292 while (sc->sc_doorbelllwp == curlwp) { 2293 now = getticks(); 2294 if (now - starttime >= delta) { 2295 sc->sc_doorbelllwp = NULL; 2296 cv_broadcast(&sc->sc_doorbell); 2297 DPRINTF("doorbell timeout", 0, 0, 0, 0); 2298 #ifdef DIAGNOSTIC /* XXX DIAGNOSTIC abuse, do this differently */ 2299 printf("ehci_sync_hc: timed out\n"); 2300 #endif 2301 break; 2302 } 2303 (void)cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, 2304 endtime - now); 2305 } 2306 2307 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2308 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2309 } 2310 2311 Static void 2312 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2313 { 2314 2315 KASSERT(mutex_owned(&sc->sc_lock)); 2316 2317 for (; itd != NULL; itd = itd->xfer_next) { 2318 struct ehci_soft_itd *prev = itd->frame_list.prev; 2319 2320 /* Unlink itd from hardware chain, or frame array */ 2321 if (prev == NULL) { /* We're at the table head */ 2322 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2323 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2324 usb_syncmem(&sc->sc_fldma, 2325 sizeof(ehci_link_t) * itd->slot, 2326 sizeof(ehci_link_t), 2327 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2328 2329 if (itd->frame_list.next != NULL) 2330 itd->frame_list.next->frame_list.prev = NULL; 2331 } else { 2332 /* XXX this part is untested... */ 2333 prev->itd.itd_next = itd->itd.itd_next; 2334 usb_syncmem(&itd->dma, 2335 itd->offs + offsetof(ehci_itd_t, itd_next), 2336 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2337 2338 prev->frame_list.next = itd->frame_list.next; 2339 if (itd->frame_list.next != NULL) 2340 itd->frame_list.next->frame_list.prev = prev; 2341 } 2342 } 2343 } 2344 2345 Static void 2346 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2347 { 2348 struct ehci_soft_itd *next; 2349 2350 mutex_enter(&sc->sc_lock); 2351 next = NULL; 2352 for (; itd != NULL; itd = next) { 2353 next = itd->xfer_next; 2354 ehci_free_itd_locked(sc, itd); 2355 } 2356 mutex_exit(&sc->sc_lock); 2357 } 2358 2359 Static void 2360 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2361 { 2362 2363 KASSERT(mutex_owned(&sc->sc_lock)); 2364 2365 for (; sitd != NULL; sitd = sitd->xfer_next) { 2366 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2367 2368 /* Unlink sitd from hardware chain, or frame array */ 2369 if (prev == NULL) { /* We're at the table head */ 2370 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2371 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2372 usb_syncmem(&sc->sc_fldma, 2373 sizeof(ehci_link_t) * sitd->slot, 2374 sizeof(ehci_link_t), 2375 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2376 2377 if (sitd->frame_list.next != NULL) 2378 sitd->frame_list.next->frame_list.prev = NULL; 2379 } else { 2380 /* XXX this part is untested... */ 2381 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2382 usb_syncmem(&sitd->dma, 2383 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2384 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2385 2386 prev->frame_list.next = sitd->frame_list.next; 2387 if (sitd->frame_list.next != NULL) 2388 sitd->frame_list.next->frame_list.prev = prev; 2389 } 2390 } 2391 } 2392 2393 Static void 2394 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2395 { 2396 2397 mutex_enter(&sc->sc_lock); 2398 struct ehci_soft_sitd *next = NULL; 2399 for (; sitd != NULL; sitd = next) { 2400 next = sitd->xfer_next; 2401 ehci_free_sitd_locked(sc, sitd); 2402 } 2403 mutex_exit(&sc->sc_lock); 2404 } 2405 2406 /***********/ 2407 2408 static int 2409 ehci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req, 2410 void *buf, int buflen) 2411 { 2412 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2413 usb_hub_descriptor_t hubd; 2414 usb_port_status_t ps; 2415 uint16_t len, value, index; 2416 int l, totlen = 0; 2417 int port, i; 2418 uint32_t v; 2419 2420 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2421 2422 KASSERT(mutex_owned(&sc->sc_rhlock)); 2423 2424 if (sc->sc_dying) 2425 return -1; 2426 2427 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2428 0, 0); 2429 2430 len = UGETW(req->wLength); 2431 value = UGETW(req->wValue); 2432 index = UGETW(req->wIndex); 2433 2434 #define C(x,y) ((x) | ((y) << 8)) 2435 switch (C(req->bRequest, req->bmRequestType)) { 2436 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2437 if (len == 0) 2438 break; 2439 switch (value) { 2440 #define sd ((usb_string_descriptor_t *)buf) 2441 case C(2, UDESC_STRING): 2442 /* Product */ 2443 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2444 break; 2445 #undef sd 2446 default: 2447 /* default from usbroothub */ 2448 return buflen; 2449 } 2450 break; 2451 2452 /* Hub requests */ 2453 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2454 break; 2455 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2456 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2457 value, 0, 0); 2458 if (index < 1 || index > sc->sc_noport) { 2459 return -1; 2460 } 2461 port = EHCI_PORTSC(index); 2462 v = EOREAD4(sc, port); 2463 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2464 v &= ~EHCI_PS_CLEAR; 2465 switch (value) { 2466 case UHF_PORT_ENABLE: 2467 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2468 break; 2469 case UHF_PORT_SUSPEND: 2470 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2471 break; 2472 v &= ~EHCI_PS_SUSP; 2473 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2474 /* see USB2 spec ch. 7.1.7.7 */ 2475 usb_delay_ms(&sc->sc_bus, 20); 2476 EOWRITE4(sc, port, v); 2477 usb_delay_ms(&sc->sc_bus, 2); 2478 #ifdef DEBUG 2479 v = EOREAD4(sc, port); 2480 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2481 printf("ehci: resume failed: %x\n", v); 2482 #endif 2483 break; 2484 case UHF_PORT_POWER: 2485 if (sc->sc_hasppc) 2486 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2487 break; 2488 case UHF_PORT_TEST: 2489 DPRINTF("clear port test %jd", index, 0, 0, 0); 2490 break; 2491 case UHF_PORT_INDICATOR: 2492 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2493 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2494 break; 2495 case UHF_C_PORT_CONNECTION: 2496 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2497 break; 2498 case UHF_C_PORT_ENABLE: 2499 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2500 break; 2501 case UHF_C_PORT_SUSPEND: 2502 /* how? */ 2503 break; 2504 case UHF_C_PORT_OVER_CURRENT: 2505 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2506 break; 2507 case UHF_C_PORT_RESET: 2508 sc->sc_isreset[index] = 0; 2509 break; 2510 default: 2511 return -1; 2512 } 2513 #if 0 2514 switch(value) { 2515 case UHF_C_PORT_CONNECTION: 2516 case UHF_C_PORT_ENABLE: 2517 case UHF_C_PORT_SUSPEND: 2518 case UHF_C_PORT_OVER_CURRENT: 2519 case UHF_C_PORT_RESET: 2520 default: 2521 break; 2522 } 2523 #endif 2524 break; 2525 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2526 if (len == 0) 2527 break; 2528 if ((value & 0xff) != 0) { 2529 return -1; 2530 } 2531 totlen = uimin(buflen, sizeof(hubd)); 2532 memcpy(&hubd, buf, totlen); 2533 hubd.bNbrPorts = sc->sc_noport; 2534 v = EREAD4(sc, EHCI_HCSPARAMS); 2535 USETW(hubd.wHubCharacteristics, 2536 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2537 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2538 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2539 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2540 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2541 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2542 totlen = uimin(totlen, hubd.bDescLength); 2543 memcpy(buf, &hubd, totlen); 2544 break; 2545 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2546 if (len != 4) { 2547 return -1; 2548 } 2549 memset(buf, 0, len); /* ? XXX */ 2550 totlen = len; 2551 break; 2552 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2553 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2554 if (index < 1 || index > sc->sc_noport) { 2555 return -1; 2556 } 2557 if (len != 4) { 2558 return -1; 2559 } 2560 v = EOREAD4(sc, EHCI_PORTSC(index)); 2561 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2562 2563 i = UPS_HIGH_SPEED; 2564 if (sc->sc_flags & EHCIF_ETTF) { 2565 /* 2566 * If we are doing embedded transaction translation, 2567 * then directly attached LS/FS devices are reset by 2568 * the EHCI controller itself. PSPD is encoded 2569 * the same way as in USBSTATUS. 2570 */ 2571 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2572 } 2573 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2574 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2575 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2576 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2577 if (v & EHCI_PS_PR) i |= UPS_RESET; 2578 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2579 if (sc->sc_vendor_port_status) 2580 i = sc->sc_vendor_port_status(sc, v, i); 2581 USETW(ps.wPortStatus, i); 2582 i = 0; 2583 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2584 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2585 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2586 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2587 USETW(ps.wPortChange, i); 2588 totlen = uimin(len, sizeof(ps)); 2589 memcpy(buf, &ps, totlen); 2590 break; 2591 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2592 return -1; 2593 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2594 break; 2595 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2596 if (index < 1 || index > sc->sc_noport) { 2597 return -1; 2598 } 2599 port = EHCI_PORTSC(index); 2600 v = EOREAD4(sc, port); 2601 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2602 v &= ~EHCI_PS_CLEAR; 2603 switch(value) { 2604 case UHF_PORT_ENABLE: 2605 EOWRITE4(sc, port, v | EHCI_PS_PE); 2606 break; 2607 case UHF_PORT_SUSPEND: 2608 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2609 break; 2610 case UHF_PORT_RESET: 2611 DPRINTF("reset port %jd", index, 0, 0, 0); 2612 if (EHCI_PS_IS_LOWSPEED(v) 2613 && sc->sc_ncomp > 0 2614 && !(sc->sc_flags & EHCIF_ETTF)) { 2615 /* 2616 * Low speed device on non-ETTF controller or 2617 * unaccompanied controller, give up ownership. 2618 */ 2619 ehci_disown(sc, index, 1); 2620 break; 2621 } 2622 /* Start reset sequence. */ 2623 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2624 EOWRITE4(sc, port, v | EHCI_PS_PR); 2625 /* Wait for reset to complete. */ 2626 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2627 if (sc->sc_dying) { 2628 return -1; 2629 } 2630 /* 2631 * An embedded transaction translator will automatically 2632 * terminate the reset sequence so there's no need to 2633 * it. 2634 */ 2635 v = EOREAD4(sc, port); 2636 if (v & EHCI_PS_PR) { 2637 /* Terminate reset sequence. */ 2638 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2639 /* Wait for HC to complete reset. */ 2640 usb_delay_ms(&sc->sc_bus, 2641 EHCI_PORT_RESET_COMPLETE); 2642 if (sc->sc_dying) { 2643 return -1; 2644 } 2645 } 2646 2647 v = EOREAD4(sc, port); 2648 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2649 if (v & EHCI_PS_PR) { 2650 printf("%s: port reset timeout\n", 2651 device_xname(sc->sc_dev)); 2652 return USBD_TIMEOUT; 2653 } 2654 if (!(v & EHCI_PS_PE)) { 2655 /* Not a high speed device, give up ownership.*/ 2656 ehci_disown(sc, index, 0); 2657 break; 2658 } 2659 sc->sc_isreset[index] = 1; 2660 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2661 v, 0, 0); 2662 break; 2663 case UHF_PORT_POWER: 2664 DPRINTF("set port power %jd (has PPC = %jd)", index, 2665 sc->sc_hasppc, 0, 0); 2666 if (sc->sc_hasppc) 2667 EOWRITE4(sc, port, v | EHCI_PS_PP); 2668 break; 2669 case UHF_PORT_TEST: 2670 DPRINTF("set port test %jd", index, 0, 0, 0); 2671 break; 2672 case UHF_PORT_INDICATOR: 2673 DPRINTF("set port ind %jd", index, 0, 0, 0); 2674 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2675 break; 2676 default: 2677 return -1; 2678 } 2679 break; 2680 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2681 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2682 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2683 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2684 break; 2685 default: 2686 /* default from usbroothub */ 2687 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2688 2689 return buflen; 2690 } 2691 2692 DPRINTF("returning %jd", totlen, 0, 0, 0); 2693 2694 return totlen; 2695 } 2696 2697 Static int 2698 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2699 void *buf, int buflen) 2700 { 2701 struct ehci_softc *sc = EHCI_BUS2SC(bus); 2702 int actlen; 2703 2704 mutex_enter(&sc->sc_rhlock); 2705 actlen = ehci_roothub_ctrl_locked(bus, req, buf, buflen); 2706 mutex_exit(&sc->sc_rhlock); 2707 2708 return actlen; 2709 } 2710 2711 /* 2712 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2713 * 2714 * This pile of garbage below works around the following problem without 2715 * holding boots with no hand-over devices present, while penalising 2716 * boots where the first ehci probe hands off devices with a 5 second 2717 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2718 * for RB_SINGLE, but the same basic issue exists. 2719 * 2720 * The way ehci hand-off works, the companion controller does not get the 2721 * device until after its initial bus explore, so the reference dropped 2722 * after the first explore is not enough. 5 seconds should be enough, 2723 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2724 * 2725 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2726 * if the callback is scheduled. CO_DONE is set when the callout has 2727 * called config_pending_decr(). 2728 * 2729 * There's a mutex, a cv and a callout here, and we delay detach if the 2730 * callout has been set. 2731 */ 2732 #ifndef EHCI_DISOWN_DELAY_SECONDS 2733 #define EHCI_DISOWN_DELAY_SECONDS 5 2734 #endif 2735 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2736 2737 static void 2738 ehci_disown_callback(void *arg) 2739 { 2740 ehci_softc_t *sc = arg; 2741 2742 config_pending_decr(sc->sc_dev); 2743 2744 mutex_enter(&sc->sc_complock); 2745 KASSERT(sc->sc_comp_state == CO_SCHED); 2746 sc->sc_comp_state = CO_DONE; 2747 cv_signal(&sc->sc_compcv); 2748 mutex_exit(&sc->sc_complock); 2749 } 2750 2751 static void 2752 ehci_disown_sched_callback(ehci_softc_t *sc) 2753 { 2754 extern bool root_is_mounted; 2755 2756 mutex_enter(&sc->sc_complock); 2757 2758 if (root_is_mounted || 2759 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2760 sc->sc_comp_state != CO_EARLY) { 2761 mutex_exit(&sc->sc_complock); 2762 return; 2763 } 2764 2765 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2766 ehci_disown_callback, &sc->sc_dev); 2767 sc->sc_comp_state = CO_SCHED; 2768 2769 mutex_exit(&sc->sc_complock); 2770 2771 config_pending_incr(sc->sc_dev); 2772 aprint_normal_dev(sc->sc_dev, 2773 "delaying %s by %u seconds due to USB owner change.\n", 2774 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user", 2775 ehci_disown_delay_seconds); 2776 } 2777 2778 Static void 2779 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2780 { 2781 int port; 2782 uint32_t v; 2783 2784 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2785 2786 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2787 if (sc->sc_npcomp != 0) { 2788 int i = (index-1) / sc->sc_npcomp; 2789 if (i < sc->sc_ncomp) { 2790 ehci_disown_sched_callback(sc); 2791 #ifdef DIAGNOSTIC 2792 printf("%s: handing over %s speed device on " 2793 "port %d to %s\n", 2794 device_xname(sc->sc_dev), 2795 lowspeed ? "low" : "full", 2796 index, sc->sc_comps[i] ? 2797 device_xname(sc->sc_comps[i]) : 2798 "companion controller"); 2799 } else { 2800 printf("%s: strange port\n", 2801 device_xname(sc->sc_dev)); 2802 #endif 2803 } 2804 } else { 2805 #ifdef DIAGNOSTIC 2806 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2807 #endif 2808 } 2809 port = EHCI_PORTSC(index); 2810 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2811 EOWRITE4(sc, port, v | EHCI_PS_PO); 2812 } 2813 2814 Static usbd_status 2815 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2816 { 2817 2818 /* Pipe isn't running, start first */ 2819 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2820 } 2821 2822 Static usbd_status 2823 ehci_root_intr_start(struct usbd_xfer *xfer) 2824 { 2825 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2826 2827 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2828 2829 if (sc->sc_dying) 2830 return USBD_IOERROR; 2831 2832 KASSERT(sc->sc_intrxfer == NULL); 2833 sc->sc_intrxfer = xfer; 2834 xfer->ux_status = USBD_IN_PROGRESS; 2835 2836 return USBD_IN_PROGRESS; 2837 } 2838 2839 /* Abort a root interrupt request. */ 2840 Static void 2841 ehci_root_intr_abort(struct usbd_xfer *xfer) 2842 { 2843 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2844 2845 KASSERT(mutex_owned(&sc->sc_lock)); 2846 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2847 2848 /* If xfer has already completed, nothing to do here. */ 2849 if (sc->sc_intrxfer == NULL) 2850 return; 2851 2852 /* 2853 * Otherwise, sc->sc_intrxfer had better be this transfer. 2854 * Cancel it. 2855 */ 2856 KASSERT(sc->sc_intrxfer == xfer); 2857 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2858 xfer->ux_status = USBD_CANCELLED; 2859 usb_transfer_complete(xfer); 2860 } 2861 2862 /* Close the root pipe. */ 2863 Static void 2864 ehci_root_intr_close(struct usbd_pipe *pipe) 2865 { 2866 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2867 2868 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2869 2870 KASSERT(mutex_owned(&sc->sc_lock)); 2871 2872 /* 2873 * Caller must guarantee the xfer has completed first, by 2874 * closing the pipe only after normal completion or an abort. 2875 */ 2876 KASSERT(sc->sc_intrxfer == NULL); 2877 } 2878 2879 Static void 2880 ehci_root_intr_done(struct usbd_xfer *xfer) 2881 { 2882 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2883 2884 KASSERT(mutex_owned(&sc->sc_lock)); 2885 2886 /* Claim the xfer so it doesn't get completed again. */ 2887 KASSERT(sc->sc_intrxfer == xfer); 2888 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2889 sc->sc_intrxfer = NULL; 2890 } 2891 2892 /************************/ 2893 2894 Static ehci_soft_qh_t * 2895 ehci_alloc_sqh(ehci_softc_t *sc) 2896 { 2897 ehci_soft_qh_t *sqh; 2898 2899 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2900 2901 mutex_enter(&sc->sc_lock); 2902 if (sc->sc_freeqhs == NULL) { 2903 DPRINTF("allocating chunk", 0, 0, 0, 0); 2904 mutex_exit(&sc->sc_lock); 2905 2906 usb_dma_t dma; 2907 int err = usb_allocmem(sc->sc_dmatag, 2908 EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2909 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2910 2911 if (err) { 2912 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2913 return NULL; 2914 } 2915 2916 mutex_enter(&sc->sc_lock); 2917 for (size_t i = 0; i < EHCI_SQH_CHUNK; i++) { 2918 const int offs = i * EHCI_SQH_SIZE; 2919 const bus_addr_t baddr = DMAADDR(&dma, offs); 2920 2921 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2922 2923 sqh = KERNADDR(&dma, offs); 2924 sqh->physaddr = BUS_ADDR_LO32(baddr); 2925 sqh->dma = dma; 2926 sqh->offs = offs; 2927 2928 sqh->next = sc->sc_freeqhs; 2929 sc->sc_freeqhs = sqh; 2930 } 2931 } 2932 sqh = sc->sc_freeqhs; 2933 sc->sc_freeqhs = sqh->next; 2934 mutex_exit(&sc->sc_lock); 2935 2936 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2937 sqh->next = NULL; 2938 return sqh; 2939 } 2940 2941 Static void 2942 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2943 { 2944 KASSERT(mutex_owned(&sc->sc_lock)); 2945 2946 sqh->next = sc->sc_freeqhs; 2947 sc->sc_freeqhs = sqh; 2948 } 2949 2950 Static ehci_soft_qtd_t * 2951 ehci_alloc_sqtd(ehci_softc_t *sc) 2952 { 2953 ehci_soft_qtd_t *sqtd = NULL; 2954 2955 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2956 2957 mutex_enter(&sc->sc_lock); 2958 if (sc->sc_freeqtds == NULL) { 2959 DPRINTF("allocating chunk", 0, 0, 0, 0); 2960 mutex_exit(&sc->sc_lock); 2961 2962 usb_dma_t dma; 2963 int err = usb_allocmem(sc->sc_dmatag, 2964 EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK, 2965 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2966 2967 if (err) { 2968 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2969 return NULL; 2970 } 2971 2972 mutex_enter(&sc->sc_lock); 2973 for (size_t i = 0; i < EHCI_SQTD_CHUNK; i++) { 2974 const int offs = i * EHCI_SQTD_SIZE; 2975 const bus_addr_t baddr = DMAADDR(&dma, offs); 2976 2977 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2978 2979 sqtd = KERNADDR(&dma, offs); 2980 sqtd->physaddr = BUS_ADDR_LO32(baddr); 2981 sqtd->dma = dma; 2982 sqtd->offs = offs; 2983 2984 sqtd->nextqtd = sc->sc_freeqtds; 2985 sc->sc_freeqtds = sqtd; 2986 } 2987 } 2988 2989 sqtd = sc->sc_freeqtds; 2990 sc->sc_freeqtds = sqtd->nextqtd; 2991 mutex_exit(&sc->sc_lock); 2992 2993 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2994 sqtd->nextqtd = NULL; 2995 sqtd->xfer = NULL; 2996 2997 return sqtd; 2998 } 2999 3000 Static void 3001 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 3002 { 3003 3004 mutex_enter(&sc->sc_lock); 3005 sqtd->nextqtd = sc->sc_freeqtds; 3006 sc->sc_freeqtds = sqtd; 3007 mutex_exit(&sc->sc_lock); 3008 } 3009 3010 Static int 3011 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3012 int alen, int rd, ehci_soft_qtd_t **sp) 3013 { 3014 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3015 uint16_t flags = xfer->ux_flags; 3016 3017 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3018 3019 ASSERT_SLEEPABLE(); 3020 KASSERT(sp); 3021 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 3022 3023 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 3024 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 3025 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 3026 KM_SLEEP); 3027 exfer->ex_nsqtd = nsqtd; 3028 3029 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 3030 alen, nsqtd, flags); 3031 3032 for (size_t j = 0; j < exfer->ex_nsqtd;) { 3033 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 3034 if (cur == NULL) 3035 goto nomem; 3036 exfer->ex_sqtds[j++] = cur; 3037 3038 cur->xfer = xfer; 3039 cur->len = 0; 3040 3041 } 3042 3043 *sp = exfer->ex_sqtds[0]; 3044 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 3045 3046 return 0; 3047 3048 nomem: 3049 ehci_free_sqtds(sc, exfer); 3050 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 3051 DPRINTF("no memory", 0, 0, 0, 0); 3052 return ENOMEM; 3053 } 3054 3055 Static void 3056 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 3057 { 3058 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3059 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 3060 3061 mutex_enter(&sc->sc_lock); 3062 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 3063 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 3064 3065 if (sqtd == NULL) 3066 break; 3067 3068 sqtd->nextqtd = sc->sc_freeqtds; 3069 sc->sc_freeqtds = sqtd; 3070 } 3071 mutex_exit(&sc->sc_lock); 3072 } 3073 3074 Static void 3075 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 3076 { 3077 if (prev) { 3078 prev->nextqtd = sqtd; 3079 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3080 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3081 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 3082 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3083 } 3084 } 3085 3086 Static void 3087 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3088 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3089 { 3090 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3091 usb_dma_t *dma = &xfer->ux_dmabuf; 3092 uint16_t flags = xfer->ux_flags; 3093 ehci_soft_qtd_t *sqtd, *prev; 3094 int tog = *toggle; 3095 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3096 int len = length; 3097 3098 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3099 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 3100 len, isread, tog); 3101 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 3102 0, 0, 0); 3103 3104 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 3105 3106 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3107 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3108 EHCI_QTD_SET_CERR(3) 3109 ; 3110 3111 sqtd = prev = NULL; 3112 size_t curoffs = 0; 3113 size_t j = 0; 3114 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3115 sqtd = exfer->ex_sqtds[j++]; 3116 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3117 (uintptr_t)prev, 0); 3118 3119 /* 3120 * The EHCI hardware can handle at most 5 pages and they do 3121 * not have to be contiguous 3122 */ 3123 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3124 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3125 size_t curlen = len; 3126 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3127 /* must use multiple TDs, fill as much as possible. */ 3128 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3129 3130 /* the length must be a multiple of the max size */ 3131 curlen -= curlen % mps; 3132 } 3133 KASSERT(curlen != 0); 3134 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3135 curoffs, 0); 3136 3137 /* Fill the qTD */ 3138 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3139 sqtd->qtd.qtd_status = htole32( 3140 qtdstatus | 3141 EHCI_QTD_SET_BYTES(curlen) | 3142 EHCI_QTD_SET_TOGGLE(tog)); 3143 3144 /* Find number of pages we'll be using, insert dma addresses */ 3145 size_t pages = EHCI_NPAGES(curlen); 3146 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3147 size_t pageoffs = EHCI_PAGE(curoffs); 3148 for (size_t i = 0; i < pages; i++) { 3149 paddr_t a = EHCI_PAGE(DMAADDR(dma, 3150 pageoffs + i * EHCI_PAGE_SIZE)); 3151 sqtd->qtd.qtd_buffer[i] = htole32(BUS_ADDR_LO32(a)); 3152 sqtd->qtd.qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a)); 3153 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3154 i, pages, 3155 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3156 le32toh(sqtd->qtd.qtd_buffer[i])); 3157 } 3158 /* First buffer pointer requires a page offset to start at */ 3159 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3160 3161 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3163 3164 sqtd->len = curlen; 3165 3166 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3167 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3168 3169 ehci_append_sqtd(sqtd, prev); 3170 3171 if (howmany(curlen, mps) & 1) { 3172 tog ^= 1; 3173 } 3174 3175 curoffs += curlen; 3176 len -= curlen; 3177 } 3178 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3179 xfer, length, len, mps, exfer->ex_nsqtd, j); 3180 3181 if (!isread && 3182 (flags & USBD_FORCE_SHORT_XFER) && 3183 length % mps == 0) { 3184 /* Force a 0 length transfer at the end. */ 3185 3186 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3187 exfer->ex_nsqtd); 3188 prev = sqtd; 3189 sqtd = exfer->ex_sqtds[j++]; 3190 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3191 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3192 sqtd->qtd.qtd_status = htole32( 3193 qtdstatus | 3194 EHCI_QTD_SET_BYTES(0) | 3195 EHCI_QTD_SET_TOGGLE(tog)); 3196 3197 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3198 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3199 3200 ehci_append_sqtd(sqtd, prev); 3201 tog ^= 1; 3202 } 3203 3204 *lsqtd = sqtd; 3205 *toggle = tog; 3206 } 3207 3208 Static ehci_soft_itd_t * 3209 ehci_alloc_itd(ehci_softc_t *sc) 3210 { 3211 struct ehci_soft_itd *itd, *freeitd; 3212 3213 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3214 3215 mutex_enter(&sc->sc_lock); 3216 3217 freeitd = LIST_FIRST(&sc->sc_freeitds); 3218 if (freeitd == NULL) { 3219 DPRINTF("allocating chunk", 0, 0, 0, 0); 3220 mutex_exit(&sc->sc_lock); 3221 3222 usb_dma_t dma; 3223 int err = usb_allocmem(sc->sc_dmatag, 3224 EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3225 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3226 3227 if (err) { 3228 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3229 return NULL; 3230 } 3231 3232 mutex_enter(&sc->sc_lock); 3233 for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) { 3234 const int offs = i * EHCI_ITD_SIZE; 3235 const bus_addr_t baddr = DMAADDR(&dma, offs); 3236 3237 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3238 3239 itd = KERNADDR(&dma, offs); 3240 itd->physaddr = BUS_ADDR_LO32(baddr); 3241 itd->dma = dma; 3242 itd->offs = offs; 3243 3244 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3245 } 3246 freeitd = LIST_FIRST(&sc->sc_freeitds); 3247 } 3248 3249 itd = freeitd; 3250 LIST_REMOVE(itd, free_list); 3251 mutex_exit(&sc->sc_lock); 3252 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3253 3254 itd->frame_list.next = NULL; 3255 itd->frame_list.prev = NULL; 3256 itd->xfer_next = NULL; 3257 itd->slot = 0; 3258 3259 return itd; 3260 } 3261 3262 Static ehci_soft_sitd_t * 3263 ehci_alloc_sitd(ehci_softc_t *sc) 3264 { 3265 struct ehci_soft_sitd *sitd, *freesitd; 3266 3267 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3268 3269 mutex_enter(&sc->sc_lock); 3270 freesitd = LIST_FIRST(&sc->sc_freesitds); 3271 if (freesitd == NULL) { 3272 DPRINTF("allocating chunk", 0, 0, 0, 0); 3273 mutex_exit(&sc->sc_lock); 3274 3275 usb_dma_t dma; 3276 int err = usb_allocmem(sc->sc_dmatag, 3277 EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3278 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3279 3280 if (err) { 3281 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3282 return NULL; 3283 } 3284 3285 mutex_enter(&sc->sc_lock); 3286 for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) { 3287 const int offs = i * EHCI_SITD_SIZE; 3288 const bus_addr_t baddr = DMAADDR(&dma, offs); 3289 3290 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3291 3292 sitd = KERNADDR(&dma, offs); 3293 sitd->physaddr = BUS_ADDR_LO32(baddr); 3294 sitd->dma = dma; 3295 sitd->offs = offs; 3296 3297 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3298 } 3299 freesitd = LIST_FIRST(&sc->sc_freesitds); 3300 } 3301 3302 sitd = freesitd; 3303 LIST_REMOVE(sitd, free_list); 3304 mutex_exit(&sc->sc_lock); 3305 3306 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3307 3308 sitd->frame_list.next = NULL; 3309 sitd->frame_list.prev = NULL; 3310 sitd->xfer_next = NULL; 3311 sitd->slot = 0; 3312 3313 return sitd; 3314 } 3315 3316 /****************/ 3317 3318 /* 3319 * Close a reqular pipe. 3320 * Assumes that there are no pending transactions. 3321 */ 3322 Static void 3323 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3324 { 3325 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3326 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3327 ehci_soft_qh_t *sqh = epipe->sqh; 3328 3329 KASSERT(mutex_owned(&sc->sc_lock)); 3330 3331 ehci_rem_qh(sc, sqh, head); 3332 ehci_free_sqh(sc, epipe->sqh); 3333 } 3334 3335 /* 3336 * Arrange for the hardware to tells us that it is not still 3337 * processing the TDs by setting the QH halted bit and wait for the ehci 3338 * door bell 3339 */ 3340 Static void 3341 ehci_abortx(struct usbd_xfer *xfer) 3342 { 3343 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3344 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3345 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3346 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3347 ehci_soft_qh_t *sqh = epipe->sqh; 3348 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3349 ehci_physaddr_t cur; 3350 uint32_t qhstatus; 3351 int hit; 3352 3353 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3354 3355 KASSERT(mutex_owned(&sc->sc_lock)); 3356 ASSERT_SLEEPABLE(); 3357 3358 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3359 xfer->ux_status == USBD_TIMEOUT), 3360 "bad abort status: %d", xfer->ux_status); 3361 3362 /* 3363 * If we're dying, skip the hardware action and just notify the 3364 * software that we're done. 3365 */ 3366 if (sc->sc_dying) { 3367 goto dying; 3368 } 3369 3370 /* 3371 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3372 */ 3373 ehci_del_intr_list(sc, exfer); 3374 3375 usb_syncmem(&sqh->dma, 3376 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3377 sizeof(sqh->qh.qh_qtd.qtd_status), 3378 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3379 qhstatus = sqh->qh.qh_qtd.qtd_status; 3380 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3381 usb_syncmem(&sqh->dma, 3382 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3383 sizeof(sqh->qh.qh_qtd.qtd_status), 3384 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3385 3386 if (exfer->ex_type == EX_CTRL) { 3387 fsqtd = exfer->ex_setup; 3388 lsqtd = exfer->ex_status; 3389 } else { 3390 fsqtd = exfer->ex_sqtdstart; 3391 lsqtd = exfer->ex_sqtdend; 3392 } 3393 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3394 usb_syncmem(&sqtd->dma, 3395 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3396 sizeof(sqtd->qtd.qtd_status), 3397 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3398 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3399 usb_syncmem(&sqtd->dma, 3400 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3401 sizeof(sqtd->qtd.qtd_status), 3402 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3403 if (sqtd == lsqtd) 3404 break; 3405 } 3406 3407 /* 3408 * HC Step 2: Wait until we know hardware has finished any possible 3409 * use of the xfer. 3410 */ 3411 ehci_sync_hc(sc); 3412 3413 /* 3414 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3415 * The complication here is that the hardware may have executed 3416 * beyond the xfer we're trying to abort. So as we're scanning 3417 * the TDs of this xfer we check if the hardware points to 3418 * any of them. 3419 */ 3420 3421 usb_syncmem(&sqh->dma, 3422 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3423 sizeof(sqh->qh.qh_curqtd), 3424 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3425 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3426 hit = 0; 3427 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3428 hit |= cur == sqtd->physaddr; 3429 if (sqtd == lsqtd) 3430 break; 3431 } 3432 sqtd = sqtd->nextqtd; 3433 /* Zap curqtd register if hardware pointed inside the xfer. */ 3434 if (hit && sqtd != NULL) { 3435 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3436 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3437 usb_syncmem(&sqh->dma, 3438 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3439 sizeof(sqh->qh.qh_curqtd), 3440 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3441 sqh->qh.qh_qtd.qtd_status = qhstatus; 3442 usb_syncmem(&sqh->dma, 3443 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3444 sizeof(sqh->qh.qh_qtd.qtd_status), 3445 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3446 } else { 3447 DPRINTF("no hit", 0, 0, 0, 0); 3448 usb_syncmem(&sqh->dma, 3449 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3450 sizeof(sqh->qh.qh_curqtd), 3451 BUS_DMASYNC_PREREAD); 3452 } 3453 3454 dying: 3455 #ifdef DIAGNOSTIC 3456 exfer->ex_isdone = true; 3457 #endif 3458 DPRINTFN(14, "end", 0, 0, 0, 0); 3459 3460 KASSERT(mutex_owned(&sc->sc_lock)); 3461 } 3462 3463 Static void 3464 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3465 { 3466 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3467 ehci_isoc_trans_t trans_status; 3468 struct ehci_xfer *exfer; 3469 ehci_softc_t *sc; 3470 struct ehci_soft_itd *itd; 3471 struct ehci_soft_sitd *sitd; 3472 int i; 3473 3474 KASSERTMSG(status == USBD_CANCELLED, 3475 "invalid status for abort: %d", (int)status); 3476 3477 exfer = EHCI_XFER2EXFER(xfer); 3478 sc = EHCI_XFER2SC(xfer); 3479 3480 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3481 (uintptr_t)xfer->ux_pipe, 0, 0); 3482 3483 KASSERT(mutex_owned(&sc->sc_lock)); 3484 ASSERT_SLEEPABLE(); 3485 3486 /* No timeout or task here. */ 3487 3488 /* 3489 * The xfer cannot have been cancelled already. It is the 3490 * responsibility of the caller of usbd_abort_pipe not to try 3491 * to abort a pipe multiple times, whether concurrently or 3492 * sequentially. 3493 */ 3494 KASSERT(xfer->ux_status != USBD_CANCELLED); 3495 3496 /* If anyone else beat us, we're done. */ 3497 if (xfer->ux_status != USBD_IN_PROGRESS) 3498 return; 3499 3500 /* We beat everyone else. Claim the status. */ 3501 xfer->ux_status = status; 3502 3503 /* 3504 * If we're dying, skip the hardware action and just notify the 3505 * software that we're done. 3506 */ 3507 if (sc->sc_dying) { 3508 goto dying; 3509 } 3510 3511 /* 3512 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3513 */ 3514 ehci_del_intr_list(sc, exfer); 3515 3516 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3517 for (itd = exfer->ex_itdstart; itd != NULL; 3518 itd = itd->xfer_next) { 3519 usb_syncmem(&itd->dma, 3520 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3521 sizeof(itd->itd.itd_ctl), 3522 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3523 3524 for (i = 0; i < 8; i++) { 3525 trans_status = le32toh(itd->itd.itd_ctl[i]); 3526 trans_status &= ~EHCI_ITD_ACTIVE; 3527 itd->itd.itd_ctl[i] = htole32(trans_status); 3528 } 3529 3530 usb_syncmem(&itd->dma, 3531 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3532 sizeof(itd->itd.itd_ctl), 3533 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3534 } 3535 } else { 3536 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3537 sitd = sitd->xfer_next) { 3538 usb_syncmem(&sitd->dma, 3539 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3540 sizeof(sitd->sitd.sitd_buffer), 3541 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3542 3543 trans_status = le32toh(sitd->sitd.sitd_trans); 3544 trans_status &= ~EHCI_SITD_ACTIVE; 3545 sitd->sitd.sitd_trans = htole32(trans_status); 3546 3547 usb_syncmem(&sitd->dma, 3548 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3549 sizeof(sitd->sitd.sitd_buffer), 3550 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3551 } 3552 } 3553 3554 dying: 3555 #ifdef DIAGNOSTIC 3556 exfer->ex_isdone = true; 3557 #endif 3558 usb_transfer_complete(xfer); 3559 DPRINTFN(14, "end", 0, 0, 0, 0); 3560 3561 KASSERT(mutex_owned(&sc->sc_lock)); 3562 } 3563 3564 /************************/ 3565 3566 Static int 3567 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3568 { 3569 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3570 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3571 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3572 usb_device_request_t *req = &xfer->ux_request; 3573 ehci_soft_qtd_t *setup, *status, *next; 3574 int isread = req->bmRequestType & UT_READ; 3575 int len = xfer->ux_bufsize; 3576 int err; 3577 3578 exfer->ex_type = EX_CTRL; 3579 exfer->ex_status = NULL; 3580 exfer->ex_data = NULL; 3581 exfer->ex_setup = ehci_alloc_sqtd(sc); 3582 if (exfer->ex_setup == NULL) { 3583 err = ENOMEM; 3584 goto bad1; 3585 } 3586 exfer->ex_status = ehci_alloc_sqtd(sc); 3587 if (exfer->ex_status == NULL) { 3588 err = ENOMEM; 3589 goto bad2; 3590 } 3591 setup = exfer->ex_setup; 3592 status = exfer->ex_status; 3593 exfer->ex_nsqtd = 0; 3594 next = status; 3595 /* Set up data transaction */ 3596 if (len != 0) { 3597 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3598 &exfer->ex_data); 3599 if (err) 3600 goto bad3; 3601 next = exfer->ex_data; 3602 } 3603 3604 /* Clear toggle */ 3605 setup->qtd.qtd_status = htole32( 3606 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3607 EHCI_QTD_SET_TOGGLE(0) | 3608 EHCI_QTD_SET_BYTES(sizeof(*req)) 3609 ); 3610 3611 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3612 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3613 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3614 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3615 setup->nextqtd = next; 3616 setup->xfer = xfer; 3617 setup->len = sizeof(*req); 3618 3619 status->qtd.qtd_status = htole32( 3620 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3621 EHCI_QTD_SET_TOGGLE(1) | 3622 EHCI_QTD_IOC 3623 ); 3624 status->qtd.qtd_buffer[0] = 0; 3625 status->qtd.qtd_buffer_hi[0] = 0; 3626 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3627 status->nextqtd = NULL; 3628 status->xfer = xfer; 3629 status->len = 0; 3630 3631 return 0; 3632 bad3: 3633 ehci_free_sqtd(sc, exfer->ex_status); 3634 bad2: 3635 ehci_free_sqtd(sc, exfer->ex_setup); 3636 bad1: 3637 return err; 3638 } 3639 3640 Static void 3641 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3642 { 3643 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3644 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3645 3646 KASSERT(ex->ex_type == EX_CTRL); 3647 3648 ehci_free_sqtd(sc, ex->ex_setup); 3649 ehci_free_sqtd(sc, ex->ex_status); 3650 ehci_free_sqtds(sc, ex); 3651 if (ex->ex_nsqtd) 3652 kmem_free(ex->ex_sqtds, 3653 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3654 } 3655 3656 Static usbd_status 3657 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3658 { 3659 3660 /* Pipe isn't running, start first */ 3661 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3662 } 3663 3664 Static usbd_status 3665 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3666 { 3667 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3668 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3669 usb_device_request_t *req = &xfer->ux_request; 3670 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3671 ehci_soft_qtd_t *setup, *status, *next; 3672 ehci_soft_qh_t *sqh; 3673 3674 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3675 3676 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3677 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3678 3679 if (sc->sc_dying) 3680 return USBD_IOERROR; 3681 3682 const int isread = req->bmRequestType & UT_READ; 3683 const int len = UGETW(req->wLength); 3684 3685 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3686 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3687 UGETW(req->wIndex)); 3688 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3689 len, epipe->pipe.up_dev->ud_addr, 3690 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3691 3692 sqh = epipe->sqh; 3693 3694 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3695 "address QH %" __PRIuBIT " pipe %d\n", 3696 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3697 epipe->pipe.up_dev->ud_addr); 3698 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3699 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3700 "MPS QH %" __PRIuBIT " pipe %d\n", 3701 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3702 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3703 3704 setup = exfer->ex_setup; 3705 status = exfer->ex_status; 3706 3707 DPRINTF("setup %#jx status %#jx data %#jx", 3708 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3709 KASSERTMSG(setup != NULL && status != NULL, 3710 "Failed memory allocation, setup %p status %p", 3711 setup, status); 3712 3713 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3714 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3715 3716 /* Clear toggle */ 3717 setup->qtd.qtd_status &= ~htole32( 3718 EHCI_QTD_STATUS_MASK | 3719 EHCI_QTD_BYTES_MASK | 3720 EHCI_QTD_TOGGLE_MASK | 3721 EHCI_QTD_CERR_MASK 3722 ); 3723 setup->qtd.qtd_status |= htole32( 3724 EHCI_QTD_ACTIVE | 3725 EHCI_QTD_SET_CERR(3) | 3726 EHCI_QTD_SET_TOGGLE(0) | 3727 EHCI_QTD_SET_BYTES(sizeof(*req)) 3728 ); 3729 3730 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3731 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3732 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3733 3734 next = status; 3735 status->qtd.qtd_status &= ~htole32( 3736 EHCI_QTD_STATUS_MASK | 3737 EHCI_QTD_PID_MASK | 3738 EHCI_QTD_BYTES_MASK | 3739 EHCI_QTD_TOGGLE_MASK | 3740 EHCI_QTD_CERR_MASK 3741 ); 3742 status->qtd.qtd_status |= htole32( 3743 EHCI_QTD_ACTIVE | 3744 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3745 EHCI_QTD_SET_CERR(3) | 3746 EHCI_QTD_SET_TOGGLE(1) | 3747 EHCI_QTD_SET_BYTES(0) | 3748 EHCI_QTD_IOC 3749 ); 3750 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3751 3752 KASSERT(exfer->ex_isdone); 3753 #ifdef DIAGNOSTIC 3754 exfer->ex_isdone = false; 3755 #endif 3756 3757 /* Set up data transaction */ 3758 if (len != 0) { 3759 ehci_soft_qtd_t *end; 3760 3761 /* Start toggle at 1. */ 3762 int toggle = 1; 3763 next = exfer->ex_data; 3764 KASSERTMSG(next != NULL, "Failed memory allocation"); 3765 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3766 end->nextqtd = status; 3767 end->qtd.qtd_next = end->qtd.qtd_altnext = 3768 htole32(status->physaddr); 3769 3770 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3771 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3772 3773 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3774 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3775 } 3776 3777 setup->nextqtd = next; 3778 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3779 3780 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3781 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3782 3783 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3784 3785 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3786 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3787 3788 #ifdef EHCI_DEBUG 3789 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3790 ehci_dump_sqh(sqh); 3791 ehci_dump_sqtds(setup); 3792 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3793 #endif 3794 3795 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3796 ehci_set_qh_qtd(sqh, setup); 3797 usbd_xfer_schedule_timeout(xfer); 3798 ehci_add_intr_list(sc, exfer); 3799 xfer->ux_status = USBD_IN_PROGRESS; 3800 3801 #if 0 3802 #ifdef EHCI_DEBUG 3803 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3804 // delay(10000); 3805 ehci_dump_regs(sc); 3806 ehci_dump_sqh(sc->sc_async_head); 3807 ehci_dump_sqh(sqh); 3808 ehci_dump_sqtds(setup); 3809 #endif 3810 #endif 3811 3812 return USBD_IN_PROGRESS; 3813 } 3814 3815 Static void 3816 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3817 { 3818 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3819 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3820 usb_device_request_t *req = &xfer->ux_request; 3821 int len = UGETW(req->wLength); 3822 int rd = req->bmRequestType & UT_READ; 3823 3824 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3825 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3826 3827 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3828 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3829 3830 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3831 BUS_DMASYNC_POSTWRITE); 3832 if (len) 3833 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3834 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3835 3836 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3837 } 3838 3839 /* Abort a device control request. */ 3840 Static void 3841 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3842 { 3843 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3844 3845 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3846 usbd_xfer_abort(xfer); 3847 } 3848 3849 /* Close a device control pipe. */ 3850 Static void 3851 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3852 { 3853 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3854 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3855 3856 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3857 3858 KASSERT(mutex_owned(&sc->sc_lock)); 3859 3860 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3861 3862 ehci_close_pipe(pipe, sc->sc_async_head); 3863 3864 usb_freemem(&epipe->ctrl.reqdma); 3865 } 3866 3867 /* 3868 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3869 * qTD status, or miss signalling occasionally under heavy load. If the host 3870 * machine is too fast, we can miss transaction completion - when we scan 3871 * the active list the transaction still seems to be active. This generally 3872 * exhibits itself as a umass stall that never recovers. 3873 * 3874 * We work around this behaviour by setting up this callback after any softintr 3875 * that completes with transactions still pending, giving us another chance to 3876 * check for completion after the writeback has taken place. 3877 */ 3878 Static void 3879 ehci_intrlist_timeout(void *arg) 3880 { 3881 ehci_softc_t *sc = arg; 3882 3883 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3884 3885 usb_schedsoftintr(&sc->sc_bus); 3886 } 3887 3888 /************************/ 3889 3890 Static int 3891 ehci_device_bulk_init(struct usbd_xfer *xfer) 3892 { 3893 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3894 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3895 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3896 int endpt = ed->bEndpointAddress; 3897 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3898 int len = xfer->ux_bufsize; 3899 int err = 0; 3900 3901 exfer->ex_type = EX_BULK; 3902 exfer->ex_nsqtd = 0; 3903 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3904 &exfer->ex_sqtdstart); 3905 3906 return err; 3907 } 3908 3909 Static void 3910 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3911 { 3912 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3913 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3914 3915 KASSERT(ex->ex_type == EX_BULK); 3916 3917 ehci_free_sqtds(sc, ex); 3918 if (ex->ex_nsqtd) 3919 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3920 } 3921 3922 Static usbd_status 3923 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3924 { 3925 3926 /* Pipe isn't running, start first */ 3927 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3928 } 3929 3930 Static usbd_status 3931 ehci_device_bulk_start(struct usbd_xfer *xfer) 3932 { 3933 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3934 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3935 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3936 ehci_soft_qh_t *sqh; 3937 ehci_soft_qtd_t *end; 3938 int len, isread, endpt; 3939 3940 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3941 3942 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3943 xfer->ux_flags, 0); 3944 3945 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3946 3947 if (sc->sc_dying) 3948 return USBD_IOERROR; 3949 3950 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3951 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3952 3953 len = xfer->ux_length; 3954 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3955 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3956 sqh = epipe->sqh; 3957 3958 KASSERT(exfer->ex_isdone); 3959 #ifdef DIAGNOSTIC 3960 exfer->ex_isdone = false; 3961 #endif 3962 3963 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3964 3965 exfer->ex_sqtdend = end; 3966 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3967 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3968 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3969 3970 #ifdef EHCI_DEBUG 3971 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3972 ehci_dump_sqh(sqh); 3973 ehci_dump_sqtds(exfer->ex_sqtdstart); 3974 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3975 #endif 3976 3977 if (xfer->ux_length) 3978 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3979 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3980 3981 /* also does usb_syncmem(sqh) */ 3982 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3983 usbd_xfer_schedule_timeout(xfer); 3984 ehci_add_intr_list(sc, exfer); 3985 xfer->ux_status = USBD_IN_PROGRESS; 3986 3987 #if 0 3988 #ifdef EHCI_DEBUG 3989 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3990 // delay(10000); 3991 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3992 ehci_dump_regs(sc); 3993 #if 0 3994 printf("async_head:\n"); 3995 ehci_dump_sqh(sc->sc_async_head); 3996 #endif 3997 DPRINTF("sqh:", 0, 0, 0, 0); 3998 ehci_dump_sqh(sqh); 3999 ehci_dump_sqtds(exfer->ex_sqtdstart); 4000 #endif 4001 #endif 4002 4003 return USBD_IN_PROGRESS; 4004 } 4005 4006 Static void 4007 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4008 { 4009 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4010 4011 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 4012 usbd_xfer_abort(xfer); 4013 } 4014 4015 /* 4016 * Close a device bulk pipe. 4017 */ 4018 Static void 4019 ehci_device_bulk_close(struct usbd_pipe *pipe) 4020 { 4021 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4022 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4023 4024 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4025 4026 KASSERT(mutex_owned(&sc->sc_lock)); 4027 4028 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4029 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4030 ehci_close_pipe(pipe, sc->sc_async_head); 4031 } 4032 4033 Static void 4034 ehci_device_bulk_done(struct usbd_xfer *xfer) 4035 { 4036 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4037 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4038 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4039 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4040 4041 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4042 4043 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4044 4045 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4046 4047 if (xfer->ux_length) 4048 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4049 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4050 4051 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4052 } 4053 4054 /************************/ 4055 4056 Static usbd_status 4057 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4058 { 4059 struct ehci_soft_islot *isp; 4060 int islot, lev; 4061 4062 /* Find a poll rate that is large enough. */ 4063 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4064 if (EHCI_ILEV_IVAL(lev) <= ival) 4065 break; 4066 4067 /* Pick an interrupt slot at the right level. */ 4068 /* XXX could do better than picking at random */ 4069 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4070 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4071 4072 sqh->islot = islot; 4073 isp = &sc->sc_islots[islot]; 4074 mutex_enter(&sc->sc_lock); 4075 ehci_add_qh(sc, sqh, isp->sqh); 4076 mutex_exit(&sc->sc_lock); 4077 4078 return USBD_NORMAL_COMPLETION; 4079 } 4080 4081 Static int 4082 ehci_device_intr_init(struct usbd_xfer *xfer) 4083 { 4084 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4085 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4086 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4087 int endpt = ed->bEndpointAddress; 4088 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4089 int len = xfer->ux_bufsize; 4090 int err; 4091 4092 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4093 4094 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4095 xfer->ux_flags, 0); 4096 4097 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4098 KASSERT(len != 0); 4099 4100 exfer->ex_type = EX_INTR; 4101 exfer->ex_nsqtd = 0; 4102 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4103 &exfer->ex_sqtdstart); 4104 4105 return err; 4106 } 4107 4108 Static void 4109 ehci_device_intr_fini(struct usbd_xfer *xfer) 4110 { 4111 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4112 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4113 4114 KASSERT(ex->ex_type == EX_INTR); 4115 4116 ehci_free_sqtds(sc, ex); 4117 if (ex->ex_nsqtd) 4118 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4119 } 4120 4121 Static usbd_status 4122 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4123 { 4124 4125 /* Pipe isn't running, so start it first. */ 4126 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4127 } 4128 4129 Static usbd_status 4130 ehci_device_intr_start(struct usbd_xfer *xfer) 4131 { 4132 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4133 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4134 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4135 ehci_soft_qtd_t *end; 4136 ehci_soft_qh_t *sqh; 4137 int len, isread, endpt; 4138 4139 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4140 4141 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4142 xfer->ux_flags, 0); 4143 4144 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4145 4146 if (sc->sc_dying) 4147 return USBD_IOERROR; 4148 4149 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4150 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4151 4152 len = xfer->ux_length; 4153 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4154 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4155 sqh = epipe->sqh; 4156 4157 KASSERT(exfer->ex_isdone); 4158 #ifdef DIAGNOSTIC 4159 exfer->ex_isdone = false; 4160 #endif 4161 4162 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4163 4164 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4165 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4166 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4167 exfer->ex_sqtdend = end; 4168 4169 #ifdef EHCI_DEBUG 4170 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4171 ehci_dump_sqh(sqh); 4172 ehci_dump_sqtds(exfer->ex_sqtdstart); 4173 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4174 #endif 4175 4176 if (xfer->ux_length) 4177 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4178 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4179 4180 /* also does usb_syncmem(sqh) */ 4181 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4182 usbd_xfer_schedule_timeout(xfer); 4183 ehci_add_intr_list(sc, exfer); 4184 xfer->ux_status = USBD_IN_PROGRESS; 4185 4186 #if 0 4187 #ifdef EHCI_DEBUG 4188 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4189 // delay(10000); 4190 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4191 ehci_dump_regs(sc); 4192 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4193 ehci_dump_sqh(sqh); 4194 ehci_dump_sqtds(exfer->ex_sqtdstart); 4195 #endif 4196 #endif 4197 4198 return USBD_IN_PROGRESS; 4199 } 4200 4201 Static void 4202 ehci_device_intr_abort(struct usbd_xfer *xfer) 4203 { 4204 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4205 4206 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4207 4208 /* 4209 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4210 * async doorbell. That's dependent on the async list, wheras 4211 * intr xfers are periodic, should not use this? 4212 */ 4213 usbd_xfer_abort(xfer); 4214 } 4215 4216 Static void 4217 ehci_device_intr_close(struct usbd_pipe *pipe) 4218 { 4219 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4220 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4221 struct ehci_soft_islot *isp; 4222 4223 KASSERT(mutex_owned(&sc->sc_lock)); 4224 4225 isp = &sc->sc_islots[epipe->sqh->islot]; 4226 ehci_close_pipe(pipe, isp->sqh); 4227 } 4228 4229 Static void 4230 ehci_device_intr_done(struct usbd_xfer *xfer) 4231 { 4232 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4233 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4234 4235 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4236 4237 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4238 4239 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4240 4241 if (xfer->ux_length) { 4242 int isread, endpt; 4243 4244 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4245 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4246 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4247 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4248 } 4249 } 4250 4251 /************************/ 4252 Static int 4253 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4254 { 4255 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4256 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4257 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4258 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4259 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4260 int i, k, frames; 4261 u_int huba, dir; 4262 int err; 4263 4264 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4265 4266 start = NULL; 4267 sitd = NULL; 4268 4269 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4270 xfer->ux_flags, 0); 4271 4272 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4273 KASSERT(xfer->ux_nframes != 0); 4274 KASSERT(exfer->ex_isdone); 4275 4276 exfer->ex_type = EX_FS_ISOC; 4277 /* 4278 * Step 1: Allocate and initialize sitds. 4279 */ 4280 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4281 if (i > 16 || i == 0) { 4282 /* Spec page 271 says intervals > 16 are invalid */ 4283 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4284 return EINVAL; 4285 } 4286 4287 frames = xfer->ux_nframes; 4288 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4289 sitd = ehci_alloc_sitd(sc); 4290 if (sitd == NULL) { 4291 err = ENOMEM; 4292 goto fail; 4293 } 4294 4295 if (prev) 4296 prev->xfer_next = sitd; 4297 else 4298 start = sitd; 4299 4300 huba = dev->ud_myhsport->up_parent->ud_addr; 4301 4302 #if 0 4303 if (sc->sc_flags & EHCIF_FREESCALE) { 4304 // Set hub address to 0 if embedded TT is used. 4305 if (huba == sc->sc_addr) 4306 huba = 0; 4307 } 4308 #endif 4309 4310 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4311 dir = UE_GET_DIR(k) ? 1 : 0; 4312 sitd->sitd.sitd_endp = 4313 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4314 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4315 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4316 EHCI_SITD_SET_HUBA(huba) | 4317 EHCI_SITD_SET_DIR(dir)); 4318 4319 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4320 } /* End of frame */ 4321 4322 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4323 4324 stop = sitd; 4325 stop->xfer_next = NULL; 4326 exfer->ex_sitdstart = start; 4327 exfer->ex_sitdend = stop; 4328 4329 return 0; 4330 4331 fail: 4332 mutex_enter(&sc->sc_lock); 4333 ehci_soft_sitd_t *next; 4334 for (sitd = start; sitd; sitd = next) { 4335 next = sitd->xfer_next; 4336 ehci_free_sitd_locked(sc, sitd); 4337 } 4338 mutex_exit(&sc->sc_lock); 4339 4340 return err; 4341 } 4342 4343 Static void 4344 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4345 { 4346 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4347 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4348 4349 KASSERT(ex->ex_type == EX_FS_ISOC); 4350 4351 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4352 } 4353 4354 Static usbd_status 4355 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4356 { 4357 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4358 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4359 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4360 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4361 ehci_soft_sitd_t *sitd; 4362 usb_dma_t *dma_buf; 4363 int i, j, k, frames; 4364 int offs; 4365 int frindex; 4366 u_int dir; 4367 4368 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4369 4370 sitd = NULL; 4371 4372 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4373 xfer->ux_flags, 0); 4374 4375 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4376 4377 if (sc->sc_dying) 4378 return USBD_IOERROR; 4379 4380 /* 4381 * To avoid complication, don't allow a request right now that'll span 4382 * the entire frame table. To within 4 frames, to allow some leeway 4383 * on either side of where the hc currently is. 4384 */ 4385 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4386 xfer->ux_nframes >= sc->sc_flsize - 4) { 4387 printf("ehci: isoc descriptor requested that spans the entire" 4388 " frametable, too many frames\n"); 4389 return USBD_INVAL; 4390 } 4391 4392 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4393 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4394 KASSERT(exfer->ex_isdone); 4395 #ifdef DIAGNOSTIC 4396 exfer->ex_isdone = false; 4397 #endif 4398 4399 /* 4400 * Step 1: Initialize sitds. 4401 */ 4402 4403 frames = xfer->ux_nframes; 4404 dma_buf = &xfer->ux_dmabuf; 4405 offs = 0; 4406 4407 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4408 i++, sitd = sitd->xfer_next) { 4409 KASSERT(sitd != NULL); 4410 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4411 4412 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4413 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4414 4415 /* Set page0 index and offset - TP and T-offset are set below */ 4416 const bus_addr_t sba = DMAADDR(dma_buf, offs); 4417 sitd->sitd.sitd_buffer[0] = htole32(BUS_ADDR_LO32(sba)); 4418 sitd->sitd.sitd_buffer_hi[0] = htole32(BUS_ADDR_HI32(sba)); 4419 4420 offs += xfer->ux_frlengths[i]; 4421 4422 const bus_addr_t eba = DMAADDR(dma_buf, offs - 1); 4423 sitd->sitd.sitd_buffer[1] = 4424 htole32(EHCI_SITD_SET_BPTR(BUS_ADDR_LO32(eba))); 4425 sitd->sitd.sitd_buffer_hi[1] = htole32(BUS_ADDR_HI32(eba)); 4426 4427 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4428 4429 #if 0 4430 if (sc->sc_flags & EHCIF_FREESCALE) { 4431 // Set hub address to 0 if embedded TT is used. 4432 if (huba == sc->sc_addr) 4433 huba = 0; 4434 } 4435 #endif 4436 4437 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4438 dir = UE_GET_DIR(k) ? 1 : 0; 4439 KASSERT(sitd->sitd.sitd_endp == htole32( 4440 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4441 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4442 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4443 EHCI_SITD_SET_HUBA(huba) | 4444 EHCI_SITD_SET_DIR(dir))); 4445 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4446 4447 uint8_t sa = 0; 4448 uint8_t sb = 0; 4449 u_int temp, tlen; 4450 4451 if (dir == 0) { /* OUT */ 4452 temp = 0; 4453 tlen = xfer->ux_frlengths[i]; 4454 if (tlen <= 188) { 4455 temp |= 1; /* T-count = 1, TP = ALL */ 4456 tlen = 1; 4457 } else { 4458 tlen += 187; 4459 tlen /= 188; 4460 temp |= tlen; /* T-count = [1..6] */ 4461 temp |= 8; /* TP = Begin */ 4462 } 4463 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4464 4465 tlen += sa; 4466 4467 if (tlen >= 8) { 4468 sb = 0; 4469 } else { 4470 sb = (1 << tlen); 4471 } 4472 4473 sa = (1 << sa); 4474 sa = (sb - sa) & 0x3F; 4475 sb = 0; 4476 } else { 4477 sb = (-(4 << sa)) & 0xFE; 4478 sa = (1 << sa) & 0x3F; 4479 sa = 0x01; 4480 sb = 0xfc; 4481 } 4482 4483 sitd->sitd.sitd_sched = htole32( 4484 EHCI_SITD_SET_SMASK(sa) | 4485 EHCI_SITD_SET_CMASK(sb) 4486 ); 4487 4488 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4489 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4490 } /* End of frame */ 4491 4492 sitd = exfer->ex_sitdend; 4493 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4494 4495 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4496 sizeof(sitd->sitd.sitd_trans), 4497 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4498 4499 if (xfer->ux_length) 4500 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4502 4503 /* 4504 * Part 2: Transfer descriptors have now been set up, now they must 4505 * be scheduled into the periodic frame list. Erk. Not wanting to 4506 * complicate matters, transfer is denied if the transfer spans 4507 * more than the periodic frame list. 4508 */ 4509 4510 /* Start inserting frames */ 4511 if (epipe->isoc.cur_xfers > 0) { 4512 frindex = epipe->isoc.next_frame; 4513 } else { 4514 frindex = EOREAD4(sc, EHCI_FRINDEX); 4515 frindex = frindex >> 3; /* Erase microframe index */ 4516 frindex += 2; 4517 } 4518 4519 if (frindex >= sc->sc_flsize) 4520 frindex &= (sc->sc_flsize - 1); 4521 4522 /* What's the frame interval? */ 4523 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4524 4525 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4526 j++, sitd = sitd->xfer_next) { 4527 KASSERT(sitd); 4528 4529 usb_syncmem(&sc->sc_fldma, 4530 sizeof(ehci_link_t) * frindex, 4531 sizeof(ehci_link_t), 4532 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4533 4534 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4535 if (sitd->sitd.sitd_next == 0) 4536 /* 4537 * FIXME: frindex table gets initialized to NULL 4538 * or EHCI_NULL? 4539 */ 4540 sitd->sitd.sitd_next = EHCI_NULL; 4541 4542 usb_syncmem(&sitd->dma, 4543 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4544 sizeof(ehci_sitd_t), 4545 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4546 4547 sc->sc_flist[frindex] = 4548 htole32(EHCI_LINK_SITD | sitd->physaddr); 4549 4550 usb_syncmem(&sc->sc_fldma, 4551 sizeof(ehci_link_t) * frindex, 4552 sizeof(ehci_link_t), 4553 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4554 4555 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4556 sc->sc_softsitds[frindex] = sitd; 4557 if (sitd->frame_list.next != NULL) 4558 sitd->frame_list.next->frame_list.prev = sitd; 4559 sitd->slot = frindex; 4560 sitd->frame_list.prev = NULL; 4561 4562 frindex += i; 4563 if (frindex >= sc->sc_flsize) 4564 frindex -= sc->sc_flsize; 4565 } 4566 4567 epipe->isoc.cur_xfers++; 4568 epipe->isoc.next_frame = frindex; 4569 4570 ehci_add_intr_list(sc, exfer); 4571 xfer->ux_status = USBD_IN_PROGRESS; 4572 4573 return USBD_IN_PROGRESS; 4574 } 4575 4576 Static void 4577 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4578 { 4579 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4580 4581 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4582 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4583 } 4584 4585 Static void 4586 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4587 { 4588 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4589 4590 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4591 } 4592 4593 Static void 4594 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4595 { 4596 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4597 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4598 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4599 4600 KASSERT(mutex_owned(&sc->sc_lock)); 4601 4602 epipe->isoc.cur_xfers--; 4603 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4604 4605 if (xfer->ux_length) 4606 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4607 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4608 } 4609 4610 /* -------------------------------------------------------------------------- */ 4611 4612 Static int 4613 ehci_device_isoc_init(struct usbd_xfer *xfer) 4614 { 4615 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4616 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4617 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4618 ehci_soft_itd_t *itd, *prev, *start, *stop; 4619 int i, j, k; 4620 int frames, ufrperframe; 4621 int err; 4622 4623 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4624 4625 start = NULL; 4626 prev = NULL; 4627 itd = NULL; 4628 4629 KASSERT(xfer->ux_nframes != 0); 4630 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4631 KASSERT(exfer->ex_isdone); 4632 4633 exfer->ex_type = EX_ISOC; 4634 4635 /* 4636 * Step 1: Allocate and initialize itds, how many do we need? 4637 * One per transfer if interval >= 8 microframes, less if we use 4638 * multiple microframes per frame. 4639 */ 4640 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4641 if (i > 16 || i == 0) { 4642 /* Spec page 271 says intervals > 16 are invalid */ 4643 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4644 return EINVAL; 4645 } 4646 4647 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4648 frames = howmany(xfer->ux_nframes, ufrperframe); 4649 4650 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4651 itd = ehci_alloc_itd(sc); 4652 if (itd == NULL) { 4653 err = ENOMEM; 4654 goto fail; 4655 } 4656 4657 if (prev != NULL) { 4658 /* Maybe not as it's updated by the scheduling? */ 4659 prev->itd.itd_next = 4660 htole32(itd->physaddr | EHCI_LINK_ITD); 4661 4662 prev->xfer_next = itd; 4663 } else { 4664 start = itd; 4665 } 4666 4667 /* 4668 * Other special values 4669 */ 4670 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4671 itd->itd.itd_bufr[0] = htole32( 4672 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4673 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4674 4675 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4676 ? 1 : 0; 4677 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4678 itd->itd.itd_bufr[1] |= htole32( 4679 EHCI_ITD_SET_DIR(k) | 4680 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4681 4682 /* FIXME: handle invalid trans - should be done in openpipe */ 4683 itd->itd.itd_bufr[2] |= 4684 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4685 } /* End of frame */ 4686 4687 stop = itd; 4688 stop->xfer_next = NULL; 4689 4690 exfer->ex_itdstart = start; 4691 exfer->ex_itdend = stop; 4692 4693 return 0; 4694 fail: 4695 mutex_enter(&sc->sc_lock); 4696 ehci_soft_itd_t *next; 4697 for (itd = start; itd; itd = next) { 4698 next = itd->xfer_next; 4699 ehci_free_itd_locked(sc, itd); 4700 } 4701 mutex_exit(&sc->sc_lock); 4702 4703 return err; 4704 4705 } 4706 4707 Static void 4708 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4709 { 4710 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4711 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4712 4713 KASSERT(ex->ex_type == EX_ISOC); 4714 4715 ehci_free_itd_chain(sc, ex->ex_itdstart); 4716 } 4717 4718 Static usbd_status 4719 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4720 { 4721 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4722 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4723 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4724 ehci_soft_itd_t *itd, *prev; 4725 usb_dma_t *dma_buf; 4726 int i, j; 4727 int frames, uframes, ufrperframe; 4728 int trans_count, offs; 4729 int frindex; 4730 4731 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4732 4733 prev = NULL; 4734 itd = NULL; 4735 trans_count = 0; 4736 4737 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4738 4739 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4740 4741 if (sc->sc_dying) 4742 return USBD_IOERROR; 4743 4744 /* 4745 * To avoid complication, don't allow a request right now that'll span 4746 * the entire frame table. To within 4 frames, to allow some leeway 4747 * on either side of where the hc currently is. 4748 */ 4749 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4750 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4751 DPRINTF( 4752 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4753 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4754 return USBD_INVAL; 4755 } 4756 4757 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4758 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4759 KASSERT(exfer->ex_isdone); 4760 #ifdef DIAGNOSTIC 4761 exfer->ex_isdone = false; 4762 #endif 4763 4764 /* 4765 * Step 1: Re-Initialize itds 4766 */ 4767 4768 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4769 if (i > 16 || i == 0) { 4770 /* Spec page 271 says intervals > 16 are invalid */ 4771 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4772 return USBD_INVAL; 4773 } 4774 4775 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4776 frames = howmany(xfer->ux_nframes, ufrperframe); 4777 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4778 4779 if (frames == 0) { 4780 DPRINTF("frames == 0", 0, 0, 0, 0); 4781 return USBD_INVAL; 4782 } 4783 4784 dma_buf = &xfer->ux_dmabuf; 4785 offs = 0; 4786 4787 itd = exfer->ex_itdstart; 4788 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4789 int froffs = offs; 4790 4791 if (prev != NULL) { 4792 prev->itd.itd_next = 4793 htole32(itd->physaddr | EHCI_LINK_ITD); 4794 usb_syncmem(&prev->dma, 4795 prev->offs + offsetof(ehci_itd_t, itd_next), 4796 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4797 prev->xfer_next = itd; 4798 } 4799 4800 /* 4801 * Step 1.5, initialize uframes 4802 */ 4803 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4804 /* Calculate which page in the list this starts in */ 4805 int addr = DMAADDR(dma_buf, froffs); 4806 addr = EHCI_PAGE_OFFSET(addr); 4807 addr += (offs - froffs); 4808 addr = EHCI_PAGE(addr); 4809 addr /= EHCI_PAGE_SIZE; 4810 4811 /* 4812 * This gets the initial offset into the first page, 4813 * looks how far further along the current uframe 4814 * offset is. Works out how many pages that is. 4815 */ 4816 4817 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4818 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4819 EHCI_ITD_SET_PG(addr) | 4820 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4821 4822 offs += xfer->ux_frlengths[trans_count]; 4823 trans_count++; 4824 4825 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4826 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4827 break; 4828 } 4829 } 4830 4831 /* 4832 * Step 1.75, set buffer pointers. To simplify matters, all 4833 * pointers are filled out for the next 7 hardware pages in 4834 * the dma block, so no need to worry what pages to cover 4835 * and what to not. 4836 */ 4837 4838 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4839 /* 4840 * Don't try to lookup a page that's past the end 4841 * of buffer 4842 */ 4843 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4844 if (page_offs >= dma_buf->udma_block->size) 4845 break; 4846 4847 uint64_t page = DMAADDR(dma_buf, page_offs); 4848 page = EHCI_PAGE(page); 4849 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4850 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4851 } 4852 /* 4853 * Other special values 4854 */ 4855 4856 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4857 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4858 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4859 4860 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4861 ? 1 : 0; 4862 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4863 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4864 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4865 4866 /* FIXME: handle invalid trans */ 4867 itd->itd.itd_bufr[2] |= 4868 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4869 4870 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4871 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4872 4873 prev = itd; 4874 } /* End of frame */ 4875 4876 if (xfer->ux_length) 4877 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4879 4880 /* 4881 * Part 2: Transfer descriptors have now been set up, now they must 4882 * be scheduled into the periodic frame list. Erk. Not wanting to 4883 * complicate matters, transfer is denied if the transfer spans 4884 * more than the periodic frame list. 4885 */ 4886 4887 /* Start inserting frames */ 4888 if (epipe->isoc.cur_xfers > 0) { 4889 frindex = epipe->isoc.next_frame; 4890 } else { 4891 frindex = EOREAD4(sc, EHCI_FRINDEX); 4892 frindex = frindex >> 3; /* Erase microframe index */ 4893 frindex += 2; 4894 } 4895 4896 if (frindex >= sc->sc_flsize) 4897 frindex &= (sc->sc_flsize - 1); 4898 4899 /* What's the frame interval? */ 4900 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4901 if (i / USB_UFRAMES_PER_FRAME == 0) 4902 i = 1; 4903 else 4904 i /= USB_UFRAMES_PER_FRAME; 4905 4906 itd = exfer->ex_itdstart; 4907 for (j = 0; j < frames; j++) { 4908 KASSERTMSG(itd != NULL, "frame %d\n", j); 4909 4910 usb_syncmem(&sc->sc_fldma, 4911 sizeof(ehci_link_t) * frindex, 4912 sizeof(ehci_link_t), 4913 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4914 4915 itd->itd.itd_next = sc->sc_flist[frindex]; 4916 if (itd->itd.itd_next == 0) 4917 /* 4918 * FIXME: frindex table gets initialized to NULL 4919 * or EHCI_NULL? 4920 */ 4921 itd->itd.itd_next = EHCI_NULL; 4922 4923 usb_syncmem(&itd->dma, 4924 itd->offs + offsetof(ehci_itd_t, itd_next), 4925 sizeof(itd->itd.itd_next), 4926 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4927 4928 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4929 4930 usb_syncmem(&sc->sc_fldma, 4931 sizeof(ehci_link_t) * frindex, 4932 sizeof(ehci_link_t), 4933 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4934 4935 itd->frame_list.next = sc->sc_softitds[frindex]; 4936 sc->sc_softitds[frindex] = itd; 4937 if (itd->frame_list.next != NULL) 4938 itd->frame_list.next->frame_list.prev = itd; 4939 itd->slot = frindex; 4940 itd->frame_list.prev = NULL; 4941 4942 frindex += i; 4943 if (frindex >= sc->sc_flsize) 4944 frindex -= sc->sc_flsize; 4945 4946 itd = itd->xfer_next; 4947 } 4948 4949 epipe->isoc.cur_xfers++; 4950 epipe->isoc.next_frame = frindex; 4951 4952 ehci_add_intr_list(sc, exfer); 4953 xfer->ux_status = USBD_IN_PROGRESS; 4954 4955 return USBD_IN_PROGRESS; 4956 } 4957 4958 Static void 4959 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4960 { 4961 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4962 4963 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4964 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4965 } 4966 4967 Static void 4968 ehci_device_isoc_close(struct usbd_pipe *pipe) 4969 { 4970 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4971 4972 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4973 } 4974 4975 Static void 4976 ehci_device_isoc_done(struct usbd_xfer *xfer) 4977 { 4978 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4979 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4980 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4981 4982 KASSERT(mutex_owned(&sc->sc_lock)); 4983 4984 epipe->isoc.cur_xfers--; 4985 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4986 if (xfer->ux_length) 4987 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4988 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4989 } 4990
Indexes created Thu Oct 02 01:09:59 GMT 2025