ehci.c revision 1.323
1 /* $NetBSD: ehci.c,v 1.323 2024/02/09 22:08:36 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna23.net), and 11 * Nick Hudson . 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 37 * 38 * The EHCI 1.0 spec can be found at 39 * http://www.intel.com/technology/usb/spec.htm 40 * and the USB 2.0 spec at 41 * http://www.usb.org/developers/docs/ 42 * 43 */ 44 45 /* 46 * TODO: 47 * 1) hold off explorations by companion controllers until ehci has started. 48 * 49 * 2) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 3) Command failures are not recovered correctly. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.323 2024/02/09 22:08:36 andvar Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #ifdef _KERNEL_OPT 63 #include "opt_usb.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #include <sys/bus.h> 69 #include <sys/cpu.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/kmem.h> 73 #include <sys/mutex.h> 74 #include <sys/proc.h> 75 #include <sys/queue.h> 76 #include <sys/select.h> 77 #include <sys/sysctl.h> 78 #include <sys/systm.h> 79 #include <sys/reboot.h> 80 81 #include <machine/endian.h> 82 83 #include <dev/usb/usb.h> 84 #include <dev/usb/usbdi.h> 85 #include <dev/usb/usbdivar.h> 86 #include <dev/usb/usbhist.h> 87 #include <dev/usb/usb_mem.h> 88 #include <dev/usb/usb_quirks.h> 89 90 #include <dev/usb/ehcireg.h> 91 #include <dev/usb/ehcivar.h> 92 #include <dev/usb/usbroothub.h> 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 99 #ifndef EHCI_DEBUG_DEFAULT 100 #define EHCI_DEBUG_DEFAULT 0 101 #endif 102 103 static int ehcidebug = EHCI_DEBUG_DEFAULT; 104 105 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 106 { 107 int err; 108 const struct sysctlnode *rnode; 109 const struct sysctlnode *cnode; 110 111 err = sysctl_createv(clog, 0, NULL, &rnode, 112 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 113 SYSCTL_DESCR("ehci global controls"), 114 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 115 116 if (err) 117 goto fail; 118 119 /* control debugging printfs */ 120 err = sysctl_createv(clog, 0, &rnode, &cnode, 121 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 122 "debug", SYSCTL_DESCR("Enable debugging output"), 123 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 124 if (err) 125 goto fail; 126 127 return; 128 fail: 129 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 130 } 131 132 #endif /* EHCI_DEBUG */ 133 #endif /* USB_DEBUG */ 134 135 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 136 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 137 #define EHCIHIST_FUNC() USBHIST_FUNC() 138 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 139 140 struct ehci_pipe { 141 struct usbd_pipe pipe; 142 int nexttoggle; 143 144 ehci_soft_qh_t *sqh; 145 union { 146 /* Control pipe */ 147 struct { 148 usb_dma_t reqdma; 149 } ctrl; 150 /* Interrupt pipe */ 151 struct { 152 u_int length; 153 } intr; 154 /* Iso pipe */ 155 struct { 156 u_int next_frame; 157 u_int cur_xfers; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 163 164 Static usbd_status ehci_open(struct usbd_pipe *); 165 Static void ehci_poll(struct usbd_bus *); 166 Static void ehci_softintr(void *); 167 Static int ehci_intr1(ehci_softc_t *); 168 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 169 ex_completeq_t *); 170 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 171 ex_completeq_t *); 172 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 173 ex_completeq_t *); 174 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 175 Static void ehci_intrlist_timeout(void *); 176 Static void ehci_doorbell(void *); 177 Static void ehci_pcd(void *); 178 179 Static struct usbd_xfer * 180 ehci_allocx(struct usbd_bus *, unsigned int); 181 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 182 183 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 184 Static bool ehci_dying(struct usbd_bus *); 185 Static int ehci_roothub_ctrl(struct usbd_bus *, 186 usb_device_request_t *, void *, int); 187 188 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 189 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 190 Static void ehci_root_intr_abort(struct usbd_xfer *); 191 Static void ehci_root_intr_close(struct usbd_pipe *); 192 Static void ehci_root_intr_done(struct usbd_xfer *); 193 194 Static int ehci_device_ctrl_init(struct usbd_xfer *); 195 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 196 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 197 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 198 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 199 Static void ehci_device_ctrl_close(struct usbd_pipe *); 200 Static void ehci_device_ctrl_done(struct usbd_xfer *); 201 202 Static int ehci_device_bulk_init(struct usbd_xfer *); 203 Static void ehci_device_bulk_fini(struct usbd_xfer *); 204 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 205 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 206 Static void ehci_device_bulk_abort(struct usbd_xfer *); 207 Static void ehci_device_bulk_close(struct usbd_pipe *); 208 Static void ehci_device_bulk_done(struct usbd_xfer *); 209 210 Static int ehci_device_intr_init(struct usbd_xfer *); 211 Static void ehci_device_intr_fini(struct usbd_xfer *); 212 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 213 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 214 Static void ehci_device_intr_abort(struct usbd_xfer *); 215 Static void ehci_device_intr_close(struct usbd_pipe *); 216 Static void ehci_device_intr_done(struct usbd_xfer *); 217 218 Static int ehci_device_isoc_init(struct usbd_xfer *); 219 Static void ehci_device_isoc_fini(struct usbd_xfer *); 220 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 221 Static void ehci_device_isoc_abort(struct usbd_xfer *); 222 Static void ehci_device_isoc_close(struct usbd_pipe *); 223 Static void ehci_device_isoc_done(struct usbd_xfer *); 224 225 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 226 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 227 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 228 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 229 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 230 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 231 232 Static void ehci_device_clear_toggle(struct usbd_pipe *); 233 Static void ehci_noop(struct usbd_pipe *); 234 235 Static void ehci_disown(ehci_softc_t *, int, int); 236 237 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 238 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 239 240 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 241 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 242 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 243 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 244 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 245 246 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 247 int, int, int *, ehci_soft_qtd_t **); 248 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 249 250 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 251 Static ehci_soft_sitd_t * 252 ehci_alloc_sitd(ehci_softc_t *); 253 254 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 255 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 256 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 257 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 258 259 static inline void 260 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 261 { 262 263 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 264 } 265 266 static inline void 267 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 268 { 269 270 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 271 } 272 273 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 274 275 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 276 int); 277 278 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 279 ehci_soft_qh_t *); 280 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 281 ehci_soft_qh_t *); 282 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 283 Static void ehci_sync_hc(ehci_softc_t *); 284 285 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 286 Static void ehci_abortx(struct usbd_xfer *); 287 288 #ifdef EHCI_DEBUG 289 Static ehci_softc_t *theehci; 290 void ehci_dump(void); 291 #endif 292 293 #ifdef EHCI_DEBUG 294 Static void ehci_dump_regs(ehci_softc_t *); 295 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 296 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 297 Static void ehci_dump_qh_qtd(struct ehci_qh_qtd_t *); 298 Static void ehci_dump_qtd(ehci_qtd_t *); 299 Static void ehci_dump_sqh(ehci_soft_qh_t *); 300 Static void ehci_dump_sitd(struct ehci_soft_itd *); 301 Static void ehci_dump_itds(ehci_soft_itd_t *); 302 Static void ehci_dump_itd(struct ehci_soft_itd *); 303 Static void ehci_dump_exfer(struct ehci_xfer *); 304 #endif 305 306 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 307 308 static inline void 309 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 310 { 311 312 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 313 } 314 315 static inline void 316 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 317 { 318 319 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 320 } 321 322 Static const struct usbd_bus_methods ehci_bus_methods = { 323 .ubm_open = ehci_open, 324 .ubm_softint = ehci_softintr, 325 .ubm_dopoll = ehci_poll, 326 .ubm_allocx = ehci_allocx, 327 .ubm_freex = ehci_freex, 328 .ubm_abortx = ehci_abortx, 329 .ubm_dying = ehci_dying, 330 .ubm_getlock = ehci_get_lock, 331 .ubm_rhctrl = ehci_roothub_ctrl, 332 }; 333 334 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 335 .upm_transfer = ehci_root_intr_transfer, 336 .upm_start = ehci_root_intr_start, 337 .upm_abort = ehci_root_intr_abort, 338 .upm_close = ehci_root_intr_close, 339 .upm_cleartoggle = ehci_noop, 340 .upm_done = ehci_root_intr_done, 341 }; 342 343 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 344 .upm_init = ehci_device_ctrl_init, 345 .upm_fini = ehci_device_ctrl_fini, 346 .upm_transfer = ehci_device_ctrl_transfer, 347 .upm_start = ehci_device_ctrl_start, 348 .upm_abort = ehci_device_ctrl_abort, 349 .upm_close = ehci_device_ctrl_close, 350 .upm_cleartoggle = ehci_noop, 351 .upm_done = ehci_device_ctrl_done, 352 }; 353 354 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 355 .upm_init = ehci_device_intr_init, 356 .upm_fini = ehci_device_intr_fini, 357 .upm_transfer = ehci_device_intr_transfer, 358 .upm_start = ehci_device_intr_start, 359 .upm_abort = ehci_device_intr_abort, 360 .upm_close = ehci_device_intr_close, 361 .upm_cleartoggle = ehci_device_clear_toggle, 362 .upm_done = ehci_device_intr_done, 363 }; 364 365 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 366 .upm_init = ehci_device_bulk_init, 367 .upm_fini = ehci_device_bulk_fini, 368 .upm_transfer = ehci_device_bulk_transfer, 369 .upm_start = ehci_device_bulk_start, 370 .upm_abort = ehci_device_bulk_abort, 371 .upm_close = ehci_device_bulk_close, 372 .upm_cleartoggle = ehci_device_clear_toggle, 373 .upm_done = ehci_device_bulk_done, 374 }; 375 376 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 377 .upm_init = ehci_device_isoc_init, 378 .upm_fini = ehci_device_isoc_fini, 379 .upm_transfer = ehci_device_isoc_transfer, 380 .upm_abort = ehci_device_isoc_abort, 381 .upm_close = ehci_device_isoc_close, 382 .upm_cleartoggle = ehci_noop, 383 .upm_done = ehci_device_isoc_done, 384 }; 385 386 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 387 .upm_init = ehci_device_fs_isoc_init, 388 .upm_fini = ehci_device_fs_isoc_fini, 389 .upm_transfer = ehci_device_fs_isoc_transfer, 390 .upm_abort = ehci_device_fs_isoc_abort, 391 .upm_close = ehci_device_fs_isoc_close, 392 .upm_cleartoggle = ehci_noop, 393 .upm_done = ehci_device_fs_isoc_done, 394 }; 395 396 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 397 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 398 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 399 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 400 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 401 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 402 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 403 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 404 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 405 }; 406 407 int 408 ehci_init(ehci_softc_t *sc) 409 { 410 uint32_t vers, hcr; 411 u_int i; 412 int err; 413 ehci_soft_qh_t *sqh; 414 u_int ncomp; 415 416 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 417 #ifdef EHCI_DEBUG 418 theehci = sc; 419 #endif 420 421 mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE); 422 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 423 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 424 cv_init(&sc->sc_doorbell, "ehcidb"); 425 426 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 427 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 428 429 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 430 ehci_doorbell, sc); 431 KASSERT(sc->sc_doorbell_si != NULL); 432 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 433 ehci_pcd, sc); 434 KASSERT(sc->sc_pcd_si != NULL); 435 436 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 437 438 vers = EREAD2(sc, EHCI_HCIVERSION); 439 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 440 vers >> 8, vers & 0xff); 441 442 const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS); 443 DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0); 444 sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams); 445 ncomp = EHCI_HCS_N_CC(hcsparams); 446 if (ncomp != sc->sc_ncomp) { 447 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 448 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 449 #if NOHCI == 0 || NUHCI == 0 450 aprint_error("%s: ohci or uhci probably not configured\n", 451 device_xname(sc->sc_dev)); 452 #endif 453 if (ncomp < sc->sc_ncomp) 454 sc->sc_ncomp = ncomp; 455 } 456 if (sc->sc_ncomp > 0) { 457 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 458 aprint_normal_dev(sc->sc_dev, 459 "%d companion controller%s, %d port%s%s", 460 sc->sc_ncomp, 461 sc->sc_ncomp!=1 ? "s" : "", 462 EHCI_HCS_N_PCC(hcsparams), 463 EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "", 464 sc->sc_ncomp!=1 ? " each" : ""); 465 if (sc->sc_comps[0]) { 466 aprint_normal(":"); 467 for (i = 0; i < sc->sc_ncomp; i++) 468 aprint_normal(" %s", 469 device_xname(sc->sc_comps[i])); 470 } 471 aprint_normal("\n"); 472 473 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 474 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 475 cv_init(&sc->sc_compcv, "ehciccv"); 476 sc->sc_comp_state = CO_EARLY; 477 } 478 sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams); 479 sc->sc_hasppc = EHCI_HCS_PPC(hcsparams); 480 481 const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS); 482 DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0); 483 484 if (EHCI_HCC_64BIT(hccparams)) { 485 /* MUST clear segment register if 64 bit capable. */ 486 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 487 } 488 489 if (hccparams & EHCI_HCC_IST_FULLFRAME) { 490 sc->sc_istthreshold = 0; 491 } else { 492 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams); 493 } 494 495 sc->sc_bus.ub_revision = USBREV_2_0; 496 sc->sc_bus.ub_usedma = true; 497 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 498 499 /* 500 * The bus attachment code will possibly provide a 64bit DMA 501 * tag which we now limit to the bottom 4G range as 502 * 503 * - that's as much as ehci can address in its QH, TD, iTD, and siTD 504 * structures; and 505 * - the driver doesn't currently set EHCI_CTRLDSSEGMENT to anything 506 * other than 0. 507 */ 508 bus_dma_tag_t ntag = sc->sc_bus.ub_dmatag; 509 sc->sc_dmatag = sc->sc_bus.ub_dmatag; 510 err = bus_dmatag_subregion(sc->sc_bus.ub_dmatag, 0, UINT32_MAX, 511 &ntag, 0); 512 if (err == 0) { 513 sc->sc_dmatag = ntag; 514 aprint_normal_dev(sc->sc_dev, "Using DMA subregion for control" 515 " data structures\n"); 516 } 517 518 /* Reset the controller */ 519 DPRINTF("resetting", 0, 0, 0, 0); 520 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 521 usb_delay_ms(&sc->sc_bus, 1); 522 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 523 for (i = 0; i < 100; i++) { 524 usb_delay_ms(&sc->sc_bus, 1); 525 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 526 if (!hcr) 527 break; 528 } 529 if (hcr) { 530 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 531 err = EIO; 532 goto fail1; 533 } 534 if (sc->sc_vendor_init) 535 sc->sc_vendor_init(sc); 536 537 /* XXX need proper intr scheduling */ 538 sc->sc_rand = 96; 539 540 /* frame list size at default, read back what we got and use that */ 541 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 542 case 0: sc->sc_flsize = 1024; break; 543 case 1: sc->sc_flsize = 512; break; 544 case 2: sc->sc_flsize = 256; break; 545 case 3: 546 err = EIO; 547 goto fail1; 548 } 549 err = usb_allocmem(sc->sc_dmatag, 550 sc->sc_flsize * sizeof(ehci_link_t), 551 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 552 if (err) { 553 aprint_error_dev(sc->sc_dev, "failed to allocate frame list\n"); 554 goto fail1; 555 } 556 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 557 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 558 559 for (i = 0; i < sc->sc_flsize; i++) { 560 sc->sc_flist[i] = EHCI_NULL; 561 } 562 563 const bus_addr_t flba = DMAADDR(&sc->sc_fldma, 0); 564 const uint32_t hi32 = BUS_ADDR_HI32(flba); 565 if (hi32 != 0) { 566 aprint_error_dev(sc->sc_dev, "DMA memory segment error (%08x)\n", 567 hi32); 568 goto fail2; 569 } 570 571 const uint32_t lo32 = BUS_ADDR_LO32(flba); 572 EOWRITE4(sc, EHCI_PERIODICLISTBASE, lo32); 573 574 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 575 KM_SLEEP); 576 LIST_INIT(&sc->sc_freeitds); 577 LIST_INIT(&sc->sc_freesitds); 578 TAILQ_INIT(&sc->sc_intrhead); 579 580 /* Set up the bus struct. */ 581 sc->sc_bus.ub_methods = &ehci_bus_methods; 582 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 583 584 sc->sc_eintrs = EHCI_NORMAL_INTRS; 585 586 /* 587 * Allocate the interrupt dummy QHs. These are arranged to give poll 588 * intervals that are powers of 2 times 1ms. 589 */ 590 memset(sc->sc_islots, 0, sizeof(sc->sc_islots)); 591 for (i = 0; i < EHCI_INTRQHS; i++) { 592 sqh = ehci_alloc_sqh(sc); 593 if (sqh == NULL) { 594 err = ENOMEM; 595 goto fail3; 596 } 597 sc->sc_islots[i].sqh = sqh; 598 } 599 for (i = 0; i < EHCI_INTRQHS; i++) { 600 sqh = sc->sc_islots[i].sqh; 601 if (i == 0) { 602 /* The last (1ms) QH terminates. */ 603 sqh->qh.qh_link = EHCI_NULL; 604 sqh->next = NULL; 605 } else { 606 /* Otherwise the next QH has half the poll interval */ 607 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 608 sqh->qh.qh_link = htole32(sqh->next->physaddr | 609 EHCI_LINK_QH); 610 } 611 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 612 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 613 sqh->qh.qh_curqtd = EHCI_NULL; 614 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 615 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 616 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 617 sqh->sqtd = NULL; 618 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 619 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 620 } 621 /* Point the frame list at the last level (128ms). */ 622 for (i = 0; i < sc->sc_flsize; i++) { 623 int j; 624 625 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 626 revbits[i & (EHCI_MAX_POLLRATE-1)]; 627 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 628 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 629 i)].sqh->physaddr); 630 } 631 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 632 BUS_DMASYNC_PREWRITE); 633 634 /* Allocate dummy QH that starts the async list. */ 635 sqh = ehci_alloc_sqh(sc); 636 if (sqh == NULL) { 637 err = ENOMEM; 638 goto fail3; 639 } 640 /* Fill the QH */ 641 sqh->qh.qh_endp = 642 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 643 sqh->qh.qh_link = 644 htole32(sqh->physaddr | EHCI_LINK_QH); 645 sqh->qh.qh_curqtd = EHCI_NULL; 646 sqh->next = NULL; 647 /* Fill the overlay qTD */ 648 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 649 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 650 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 651 sqh->sqtd = NULL; 652 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 653 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 654 #ifdef EHCI_DEBUG 655 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 656 ehci_dump_sqh(sqh); 657 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 658 #endif 659 660 /* Point to async list */ 661 sc->sc_async_head = sqh; 662 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 663 664 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 665 666 /* Turn on controller */ 667 EOWRITE4(sc, EHCI_USBCMD, 668 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 669 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 670 EHCI_CMD_ASE | 671 EHCI_CMD_PSE | 672 EHCI_CMD_RS); 673 674 /* Take over port ownership */ 675 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 676 677 for (i = 0; i < 100; i++) { 678 usb_delay_ms(&sc->sc_bus, 1); 679 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 680 if (!hcr) 681 break; 682 } 683 if (hcr) { 684 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 685 err = EIO; 686 goto fail4; 687 } 688 689 /* Enable interrupts */ 690 DPRINTF("enabling interrupts", 0, 0, 0, 0); 691 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 692 693 return 0; 694 695 fail4: 696 ehci_free_sqh(sc, sc->sc_async_head); 697 698 fail3: 699 for (i = 0; i < EHCI_INTRQHS; i++) { 700 sqh = sc->sc_islots[i].sqh; 701 if (sqh) 702 ehci_free_sqh(sc, sqh); 703 } 704 705 kmem_free(sc->sc_softitds, sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 706 707 fail2: 708 usb_freemem(&sc->sc_fldma); 709 710 fail1: 711 softint_disestablish(sc->sc_doorbell_si); 712 softint_disestablish(sc->sc_pcd_si); 713 mutex_destroy(&sc->sc_rhlock); 714 mutex_destroy(&sc->sc_lock); 715 mutex_destroy(&sc->sc_intr_lock); 716 717 return err; 718 } 719 720 int 721 ehci_intr(void *v) 722 { 723 ehci_softc_t *sc = v; 724 int ret = 0; 725 726 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 727 728 if (sc == NULL) 729 return 0; 730 731 mutex_spin_enter(&sc->sc_intr_lock); 732 733 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 734 goto done; 735 736 /* If we get an interrupt while polling, then just ignore it. */ 737 if (sc->sc_bus.ub_usepolling) { 738 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 739 740 if (intrs) 741 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 742 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 743 goto done; 744 } 745 746 ret = ehci_intr1(sc); 747 748 done: 749 mutex_spin_exit(&sc->sc_intr_lock); 750 return ret; 751 } 752 753 Static int 754 ehci_intr1(ehci_softc_t *sc) 755 { 756 uint32_t intrs, eintrs; 757 758 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 759 760 /* In case the interrupt occurs before initialization has completed. */ 761 if (sc == NULL) { 762 #ifdef DIAGNOSTIC 763 printf("ehci_intr1: sc == NULL\n"); 764 #endif 765 return 0; 766 } 767 768 KASSERT(mutex_owned(&sc->sc_intr_lock)); 769 770 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 771 if (!intrs) 772 return 0; 773 774 eintrs = intrs & sc->sc_eintrs; 775 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 776 EOREAD4(sc, EHCI_USBSTS), eintrs); 777 if (!eintrs) 778 return 0; 779 780 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 781 if (eintrs & EHCI_STS_IAA) { 782 DPRINTF("door bell", 0, 0, 0, 0); 783 kpreempt_disable(); 784 KASSERT(sc->sc_doorbell_si != NULL); 785 softint_schedule(sc->sc_doorbell_si); 786 kpreempt_enable(); 787 eintrs &= ~EHCI_STS_IAA; 788 } 789 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 790 DPRINTF("INT=%jd ERRINT=%jd", 791 eintrs & EHCI_STS_INT ? 1 : 0, 792 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 793 usb_schedsoftintr(&sc->sc_bus); 794 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 795 } 796 if (eintrs & EHCI_STS_HSE) { 797 printf("%s: unrecoverable error, controller halted\n", 798 device_xname(sc->sc_dev)); 799 /* XXX what else */ 800 } 801 if (eintrs & EHCI_STS_PCD) { 802 kpreempt_disable(); 803 KASSERT(sc->sc_pcd_si != NULL); 804 softint_schedule(sc->sc_pcd_si); 805 kpreempt_enable(); 806 eintrs &= ~EHCI_STS_PCD; 807 } 808 809 if (eintrs != 0) { 810 /* Block unprocessed interrupts. */ 811 sc->sc_eintrs &= ~eintrs; 812 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 813 printf("%s: blocking intrs %#x\n", 814 device_xname(sc->sc_dev), eintrs); 815 } 816 817 return 1; 818 } 819 820 Static void 821 ehci_doorbell(void *addr) 822 { 823 ehci_softc_t *sc = addr; 824 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 825 826 mutex_enter(&sc->sc_lock); 827 if (sc->sc_doorbelllwp == NULL) 828 DPRINTF("spurious doorbell interrupt", 0, 0, 0, 0); 829 sc->sc_doorbelllwp = NULL; 830 cv_broadcast(&sc->sc_doorbell); 831 mutex_exit(&sc->sc_lock); 832 } 833 834 Static void 835 ehci_pcd(void *addr) 836 { 837 ehci_softc_t *sc = addr; 838 struct usbd_xfer *xfer; 839 u_char *p; 840 int i, m; 841 842 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 843 844 mutex_enter(&sc->sc_lock); 845 xfer = sc->sc_intrxfer; 846 847 if (xfer == NULL) { 848 /* Just ignore the change. */ 849 goto done; 850 } 851 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 852 853 p = xfer->ux_buf; 854 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 855 memset(p, 0, xfer->ux_length); 856 for (i = 1; i <= m; i++) { 857 /* Pick out CHANGE bits from the status reg. */ 858 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 859 p[i/8] |= 1 << (i%8); 860 if (i % 8 == 7) 861 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 862 } 863 xfer->ux_actlen = xfer->ux_length; 864 xfer->ux_status = USBD_NORMAL_COMPLETION; 865 866 usb_transfer_complete(xfer); 867 868 done: 869 mutex_exit(&sc->sc_lock); 870 } 871 872 Static void 873 ehci_softintr(void *v) 874 { 875 struct usbd_bus *bus = v; 876 ehci_softc_t *sc = EHCI_BUS2SC(bus); 877 struct ehci_xfer *ex, *nextex; 878 879 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 880 881 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 882 883 ex_completeq_t cq; 884 TAILQ_INIT(&cq); 885 886 /* 887 * The only explanation I can think of for why EHCI is as brain dead 888 * as UHCI interrupt-wise is that Intel was involved in both. 889 * An interrupt just tells us that something is done, we have no 890 * clue what, so we need to scan through all active transfers. :-( 891 */ 892 893 /* 894 * ehci_idone will remove transfer from sc->sc_intrhead if it's 895 * complete and add to our cq list 896 * 897 */ 898 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 899 switch (ex->ex_type) { 900 case EX_CTRL: 901 case EX_BULK: 902 case EX_INTR: 903 ehci_check_qh_intr(sc, ex, &cq); 904 break; 905 case EX_ISOC: 906 ehci_check_itd_intr(sc, ex, &cq); 907 break; 908 case EX_FS_ISOC: 909 ehci_check_sitd_intr(sc, ex, &cq); 910 break; 911 default: 912 KASSERT(false); 913 } 914 915 } 916 917 /* 918 * We abuse ex_next for the interrupt and complete lists and 919 * interrupt transfers will get re-added here so use 920 * the _SAFE version of TAILQ_FOREACH. 921 */ 922 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 923 usb_transfer_complete(&ex->ex_xfer); 924 } 925 926 /* Schedule a callout to catch any dropped transactions. */ 927 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 928 !TAILQ_EMPTY(&sc->sc_intrhead)) 929 callout_reset(&sc->sc_tmo_intrlist, 930 hz, ehci_intrlist_timeout, sc); 931 } 932 933 Static void 934 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 935 { 936 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 937 uint32_t status; 938 939 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 940 941 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 942 943 if (ex->ex_type == EX_CTRL) { 944 fsqtd = ex->ex_setup; 945 lsqtd = ex->ex_status; 946 } else { 947 fsqtd = ex->ex_sqtdstart; 948 lsqtd = ex->ex_sqtdend; 949 } 950 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 951 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 952 953 /* 954 * If the last TD is still active we need to check whether there 955 * is an error somewhere in the middle, or whether there was a 956 * short packet (SPD and not ACTIVE). 957 */ 958 usb_syncmem(&lsqtd->dma, 959 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 960 sizeof(lsqtd->qtd.qtd_status), 961 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 962 status = le32toh(lsqtd->qtd.qtd_status); 963 usb_syncmem(&lsqtd->dma, 964 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 965 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 966 if (status & EHCI_QTD_ACTIVE) { 967 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 968 969 /* last qTD has already been checked */ 970 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 971 usb_syncmem(&sqtd->dma, 972 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 973 sizeof(sqtd->qtd.qtd_status), 974 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 975 status = le32toh(sqtd->qtd.qtd_status); 976 usb_syncmem(&sqtd->dma, 977 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 978 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 979 /* If there's an active QTD the xfer isn't done. */ 980 if (status & EHCI_QTD_ACTIVE) 981 break; 982 /* Any kind of error makes the xfer done. */ 983 if (status & EHCI_QTD_HALTED) 984 goto done; 985 /* Handle short packets */ 986 if (EHCI_QTD_GET_BYTES(status) != 0) { 987 /* 988 * If we get here for a control transfer then 989 * we need to let the hardware complete the 990 * status phase. That is, we're not done 991 * quite yet. 992 * 993 * Otherwise, we're done. 994 */ 995 if (ex->ex_type == EX_CTRL) { 996 break; 997 } 998 goto done; 999 } 1000 } 1001 DPRINTFN(10, "ex=%#jx std=%#jx still active", 1002 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 1003 #ifdef EHCI_DEBUG 1004 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 1005 ehci_dump_sqtds(ex->ex_sqtdstart); 1006 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 1007 #endif 1008 return; 1009 } 1010 done: 1011 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1012 ehci_idone(ex, cq); 1013 } 1014 1015 Static void 1016 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1017 { 1018 ehci_soft_itd_t *itd; 1019 int i; 1020 1021 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1022 1023 KASSERT(mutex_owned(&sc->sc_lock)); 1024 1025 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1026 return; 1027 1028 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 1029 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 1030 1031 itd = ex->ex_itdend; 1032 1033 /* 1034 * check no active transfers in last itd, meaning we're finished 1035 */ 1036 1037 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1038 sizeof(itd->itd.itd_ctl), 1039 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1040 1041 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1042 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 1043 break; 1044 } 1045 1046 if (i == EHCI_ITD_NUFRAMES) { 1047 goto done; /* All 8 descriptors inactive, it's done */ 1048 } 1049 1050 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1051 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1052 1053 DPRINTFN(10, "ex %#jx itd %#jx still active", 1054 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 1055 return; 1056 done: 1057 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 1058 ehci_idone(ex, cq); 1059 } 1060 1061 void 1062 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1063 { 1064 ehci_soft_sitd_t *sitd; 1065 1066 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1067 1068 KASSERT(mutex_owned(&sc->sc_lock)); 1069 1070 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1071 return; 1072 1073 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1074 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1075 1076 sitd = ex->ex_sitdend; 1077 1078 /* 1079 * check no active transfers in last sitd, meaning we're finished 1080 */ 1081 1082 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1083 sizeof(sitd->sitd.sitd_trans), 1084 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1085 1086 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1087 1088 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1089 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1090 1091 if (active) 1092 return; 1093 1094 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1095 ehci_idone(ex, cq); 1096 } 1097 1098 Static void 1099 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1100 { 1101 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1102 struct usbd_xfer *xfer = &ex->ex_xfer; 1103 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1104 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1105 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1106 uint32_t status = 0, nstatus = 0; 1107 int actlen = 0; 1108 1109 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1110 1111 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1112 1113 /* 1114 * Try to claim this xfer for completion. If it has already 1115 * completed or aborted, drop it on the floor. 1116 */ 1117 if (!usbd_xfer_trycomplete(xfer)) 1118 return; 1119 1120 #ifdef DIAGNOSTIC 1121 #ifdef EHCI_DEBUG 1122 if (ex->ex_isdone) { 1123 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1124 ehci_dump_exfer(ex); 1125 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1126 } 1127 #endif 1128 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1129 ex->ex_type, xfer->ux_status); 1130 ex->ex_isdone = true; 1131 #endif 1132 1133 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1134 (uintptr_t)epipe, 0, 0); 1135 1136 /* The transfer is done, compute actual length and status. */ 1137 if (ex->ex_type == EX_ISOC) { 1138 /* HS isoc transfer */ 1139 1140 struct ehci_soft_itd *itd; 1141 int i, nframes, len, uframes; 1142 1143 nframes = 0; 1144 1145 #ifdef EHCI_DEBUG 1146 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1147 ehci_dump_itds(ex->ex_itdstart); 1148 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1149 #endif 1150 1151 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1152 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1153 1154 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1155 usb_syncmem(&itd->dma, 1156 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1157 sizeof(itd->itd.itd_ctl), 1158 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1159 1160 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1161 /* 1162 * XXX - driver didn't fill in the frame full 1163 * of uframes. This leads to scheduling 1164 * inefficiencies, but working around 1165 * this doubles complexity of tracking 1166 * an xfer. 1167 */ 1168 if (nframes >= xfer->ux_nframes) 1169 break; 1170 1171 status = le32toh(itd->itd.itd_ctl[i]); 1172 len = EHCI_ITD_GET_LEN(status); 1173 if (EHCI_ITD_GET_STATUS(status) != 0) 1174 len = 0; /*No valid data on error*/ 1175 1176 xfer->ux_frlengths[nframes++] = len; 1177 actlen += len; 1178 } 1179 usb_syncmem(&itd->dma, 1180 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1181 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1182 1183 if (nframes >= xfer->ux_nframes) 1184 break; 1185 } 1186 1187 xfer->ux_actlen = actlen; 1188 xfer->ux_status = USBD_NORMAL_COMPLETION; 1189 goto end; 1190 } else if (ex->ex_type == EX_FS_ISOC) { 1191 /* FS isoc transfer */ 1192 struct ehci_soft_sitd *sitd; 1193 int nframes, len; 1194 1195 nframes = 0; 1196 1197 for (sitd = ex->ex_sitdstart; sitd != NULL; 1198 sitd = sitd->xfer_next) { 1199 usb_syncmem(&sitd->dma, 1200 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1201 sizeof(sitd->sitd.sitd_trans), 1202 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1203 1204 /* 1205 * XXX - driver didn't fill in the frame full 1206 * of uframes. This leads to scheduling 1207 * inefficiencies, but working around 1208 * this doubles complexity of tracking 1209 * an xfer. 1210 */ 1211 if (nframes >= xfer->ux_nframes) 1212 break; 1213 1214 status = le32toh(sitd->sitd.sitd_trans); 1215 usb_syncmem(&sitd->dma, 1216 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1217 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1218 1219 len = EHCI_SITD_GET_LEN(status); 1220 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1221 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1222 /* No valid data on error */ 1223 len = xfer->ux_frlengths[nframes]; 1224 } 1225 1226 /* 1227 * frlengths[i]: # of bytes to send 1228 * len: # of bytes host didn't send 1229 */ 1230 xfer->ux_frlengths[nframes] -= len; 1231 /* frlengths[i]: # of bytes host sent */ 1232 actlen += xfer->ux_frlengths[nframes++]; 1233 1234 if (nframes >= xfer->ux_nframes) 1235 break; 1236 } 1237 1238 xfer->ux_actlen = actlen; 1239 xfer->ux_status = USBD_NORMAL_COMPLETION; 1240 goto end; 1241 } 1242 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1243 ex->ex_type == EX_BULK); 1244 1245 /* Continue processing xfers using queue heads */ 1246 if (ex->ex_type == EX_CTRL) { 1247 fsqtd = ex->ex_setup; 1248 lsqtd = ex->ex_status; 1249 } else { 1250 fsqtd = ex->ex_sqtdstart; 1251 lsqtd = ex->ex_sqtdend; 1252 } 1253 #ifdef EHCI_DEBUG 1254 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1255 ehci_dump_sqtds(fsqtd); 1256 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1257 #endif 1258 1259 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1260 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1261 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1262 nstatus = le32toh(sqtd->qtd.qtd_status); 1263 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1264 BUS_DMASYNC_PREREAD); 1265 if (nstatus & EHCI_QTD_ACTIVE) 1266 break; 1267 1268 status = nstatus; 1269 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1270 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1271 } 1272 1273 /* 1274 * If there are left over TDs we need to update the toggle. 1275 * The default pipe doesn't need it since control transfers 1276 * start the toggle at 0 every time. 1277 * For a short transfer we need to update the toggle for the missing 1278 * packets within the qTD. 1279 */ 1280 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1281 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1282 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1283 status, nstatus, 0, 0); 1284 #if 0 1285 ehci_dump_sqh(epipe->sqh); 1286 ehci_dump_sqtds(ex->ex_sqtdstart); 1287 #endif 1288 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1289 } 1290 1291 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1292 status, 0); 1293 xfer->ux_actlen = actlen; 1294 if (status & EHCI_QTD_HALTED) { 1295 #ifdef EHCI_DEBUG 1296 DPRINTF("halted addr=%jd endpt=0x%02jx", 1297 xfer->ux_pipe->up_dev->ud_addr, 1298 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1299 0, 0); 1300 DPRINTF("cerr=%jd pid=%jd", 1301 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1302 0, 0); 1303 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1304 status & EHCI_QTD_ACTIVE ? 1 : 0, 1305 status & EHCI_QTD_HALTED ? 1 : 0, 1306 status & EHCI_QTD_BUFERR ? 1 : 0, 1307 status & EHCI_QTD_BABBLE ? 1 : 0); 1308 1309 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1310 status & EHCI_QTD_XACTERR ? 1 : 0, 1311 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1312 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1313 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1314 1315 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1316 ehci_dump_sqh(epipe->sqh); 1317 ehci_dump_sqtds(ex->ex_sqtdstart); 1318 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1319 #endif 1320 /* low&full speed has an extra error flag */ 1321 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1322 EHCI_QH_SPEED_HIGH) 1323 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1324 else 1325 status &= EHCI_QTD_STATERRS; 1326 if (status == 0) /* no other errors means a stall */ { 1327 xfer->ux_status = USBD_STALLED; 1328 } else { 1329 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1330 } 1331 /* XXX need to reset TT on missed microframe */ 1332 if (status & EHCI_QTD_MISSEDMICRO) { 1333 printf("%s: missed microframe, TT reset not " 1334 "implemented, hub might be inoperational\n", 1335 device_xname(sc->sc_dev)); 1336 } 1337 } else { 1338 xfer->ux_status = USBD_NORMAL_COMPLETION; 1339 } 1340 1341 end: 1342 1343 ehci_del_intr_list(sc, ex); 1344 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1345 1346 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1347 } 1348 1349 Static void 1350 ehci_poll(struct usbd_bus *bus) 1351 { 1352 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1353 1354 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1355 1356 #ifdef EHCI_DEBUG 1357 static int last; 1358 int new; 1359 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1360 if (new != last) { 1361 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1362 last = new; 1363 } 1364 #endif 1365 1366 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1367 mutex_spin_enter(&sc->sc_intr_lock); 1368 ehci_intr1(sc); 1369 mutex_spin_exit(&sc->sc_intr_lock); 1370 } 1371 } 1372 1373 void 1374 ehci_childdet(device_t self, device_t child) 1375 { 1376 struct ehci_softc *sc = device_private(self); 1377 1378 KASSERT(sc->sc_child == child); 1379 sc->sc_child = NULL; 1380 } 1381 1382 int 1383 ehci_detach(struct ehci_softc *sc, int flags) 1384 { 1385 int rv = 0; 1386 1387 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1388 1389 if (sc->sc_child != NULL) { 1390 rv = config_detach(sc->sc_child, flags); 1391 if (rv != 0) 1392 return rv; 1393 } 1394 1395 if (sc->sc_ncomp > 0) { 1396 mutex_enter(&sc->sc_complock); 1397 /* XXX try to halt callout instead of waiting */ 1398 while (sc->sc_comp_state == CO_SCHED) 1399 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1400 mutex_exit(&sc->sc_complock); 1401 1402 callout_halt(&sc->sc_compcallout, NULL); 1403 callout_destroy(&sc->sc_compcallout); 1404 cv_destroy(&sc->sc_compcv); 1405 mutex_destroy(&sc->sc_complock); 1406 } 1407 1408 callout_halt(&sc->sc_tmo_intrlist, NULL); 1409 callout_destroy(&sc->sc_tmo_intrlist); 1410 1411 /* XXX free other data structures */ 1412 if (sc->sc_softitds) { 1413 kmem_free(sc->sc_softitds, 1414 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1415 } 1416 cv_destroy(&sc->sc_doorbell); 1417 1418 #if 0 1419 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1420 softint_disestablish(sc->sc_doorbell_si); 1421 softint_disestablish(sc->sc_pcd_si); 1422 mutex_destroy(&sc->sc_rhlock); 1423 mutex_destroy(&sc->sc_lock); 1424 mutex_destroy(&sc->sc_intr_lock); 1425 #endif 1426 1427 pool_cache_destroy(sc->sc_xferpool); 1428 1429 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1430 1431 return rv; 1432 } 1433 1434 int 1435 ehci_activate(device_t self, enum devact act) 1436 { 1437 struct ehci_softc *sc = device_private(self); 1438 1439 switch (act) { 1440 case DVACT_DEACTIVATE: 1441 sc->sc_dying = 1; 1442 return 0; 1443 default: 1444 return EOPNOTSUPP; 1445 } 1446 } 1447 1448 /* 1449 * Handle suspend/resume. 1450 * 1451 * Note that this power handler isn't to be registered directly; the 1452 * bus glue needs to call out to it. 1453 */ 1454 bool 1455 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1456 { 1457 ehci_softc_t *sc = device_private(dv); 1458 int i; 1459 uint32_t cmd, hcr; 1460 1461 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1462 1463 mutex_enter(&sc->sc_rhlock); 1464 1465 for (i = 1; i <= sc->sc_noport; i++) { 1466 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1467 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1468 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1469 } 1470 1471 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1472 1473 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1474 EOWRITE4(sc, EHCI_USBCMD, cmd); 1475 1476 for (i = 0; i < 100; i++) { 1477 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1478 if (hcr == 0) 1479 break; 1480 1481 usb_delay_ms(&sc->sc_bus, 1); 1482 } 1483 if (hcr != 0) 1484 printf("%s: reset timeout\n", device_xname(dv)); 1485 1486 cmd &= ~EHCI_CMD_RS; 1487 EOWRITE4(sc, EHCI_USBCMD, cmd); 1488 1489 for (i = 0; i < 100; i++) { 1490 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1491 if (hcr == EHCI_STS_HCH) 1492 break; 1493 1494 usb_delay_ms(&sc->sc_bus, 1); 1495 } 1496 if (hcr != EHCI_STS_HCH) 1497 printf("%s: config timeout\n", device_xname(dv)); 1498 1499 mutex_exit(&sc->sc_rhlock); 1500 1501 return true; 1502 } 1503 1504 bool 1505 ehci_resume(device_t dv, const pmf_qual_t *qual) 1506 { 1507 ehci_softc_t *sc = device_private(dv); 1508 int i; 1509 uint32_t cmd, hcr; 1510 1511 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1512 1513 mutex_enter(&sc->sc_rhlock); 1514 1515 /* restore things in case the bios sucks */ 1516 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1517 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1518 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1519 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1520 1521 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1522 1523 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1524 1525 hcr = 0; 1526 for (i = 1; i <= sc->sc_noport; i++) { 1527 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1528 if ((cmd & EHCI_PS_PO) == 0 && 1529 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1530 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1531 hcr = 1; 1532 } 1533 } 1534 1535 if (hcr) { 1536 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1537 1538 for (i = 1; i <= sc->sc_noport; i++) { 1539 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1540 if ((cmd & EHCI_PS_PO) == 0 && 1541 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1542 EOWRITE4(sc, EHCI_PORTSC(i), 1543 cmd & ~EHCI_PS_FPR); 1544 } 1545 } 1546 1547 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1548 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1549 1550 for (i = 0; i < 100; i++) { 1551 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1552 if (hcr != EHCI_STS_HCH) 1553 break; 1554 1555 usb_delay_ms(&sc->sc_bus, 1); 1556 } 1557 if (hcr == EHCI_STS_HCH) 1558 printf("%s: config timeout\n", device_xname(dv)); 1559 1560 mutex_exit(&sc->sc_rhlock); 1561 1562 return true; 1563 } 1564 1565 /* 1566 * Shut down the controller when the system is going down. 1567 */ 1568 bool 1569 ehci_shutdown(device_t self, int flags) 1570 { 1571 ehci_softc_t *sc = device_private(self); 1572 1573 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1574 1575 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1576 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1577 return true; 1578 } 1579 1580 Static struct usbd_xfer * 1581 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1582 { 1583 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1584 struct usbd_xfer *xfer; 1585 1586 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1587 if (xfer != NULL) { 1588 memset(xfer, 0, sizeof(struct ehci_xfer)); 1589 1590 #ifdef DIAGNOSTIC 1591 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1592 ex->ex_isdone = true; 1593 xfer->ux_state = XFER_BUSY; 1594 #endif 1595 } 1596 return xfer; 1597 } 1598 1599 Static void 1600 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1601 { 1602 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1603 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1604 1605 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1606 xfer->ux_status == USBD_NOT_STARTED, 1607 "xfer %p state %d\n", xfer, xfer->ux_state); 1608 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1609 1610 #ifdef DIAGNOSTIC 1611 xfer->ux_state = XFER_FREE; 1612 #endif 1613 1614 pool_cache_put(sc->sc_xferpool, xfer); 1615 } 1616 1617 Static bool 1618 ehci_dying(struct usbd_bus *bus) 1619 { 1620 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1621 1622 return sc->sc_dying; 1623 } 1624 1625 Static void 1626 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1627 { 1628 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1629 1630 *lock = &sc->sc_lock; 1631 } 1632 1633 Static void 1634 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1635 { 1636 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1637 1638 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1639 1640 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1641 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1642 #ifdef EHCI_DEBUG 1643 if (ehcidebug) 1644 usbd_dump_pipe(pipe); 1645 #endif 1646 epipe->nexttoggle = 0; 1647 } 1648 1649 Static void 1650 ehci_noop(struct usbd_pipe *pipe) 1651 { 1652 } 1653 1654 #ifdef EHCI_DEBUG 1655 /* 1656 * Unused function - this is meant to be called from a kernel 1657 * debugger. 1658 */ 1659 void 1660 ehci_dump(void) 1661 { 1662 ehci_softc_t *sc = theehci; 1663 int i; 1664 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1665 EOREAD4(sc, EHCI_USBCMD), 1666 EOREAD4(sc, EHCI_USBSTS), 1667 EOREAD4(sc, EHCI_USBINTR)); 1668 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1669 EOREAD4(sc, EHCI_FRINDEX), 1670 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1671 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1672 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1673 for (i = 1; i <= sc->sc_noport; i++) 1674 printf("port %d status=0x%08x\n", i, 1675 EOREAD4(sc, EHCI_PORTSC(i))); 1676 } 1677 1678 Static void 1679 ehci_dump_regs(ehci_softc_t *sc) 1680 { 1681 int i; 1682 1683 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1684 1685 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1686 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1687 EOREAD4(sc, EHCI_USBINTR), 0); 1688 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1689 "async = 0x%08jx", 1690 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1691 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1692 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1693 for (i = 1; i <= sc->sc_noport; i += 2) { 1694 if (i == sc->sc_noport) { 1695 DPRINTF("port %jd status = 0x%08jx", i, 1696 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1697 } else { 1698 DPRINTF("port %jd status = 0x%08jx port %jd " 1699 "status = 0x%08jx", 1700 i, EOREAD4(sc, EHCI_PORTSC(i)), 1701 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1702 } 1703 } 1704 } 1705 1706 #define ehci_dump_link(link, type) do { \ 1707 DPRINTF(" link 0x%08jx (T = %jd):", \ 1708 link, \ 1709 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1710 if (type) { \ 1711 DPRINTF( \ 1712 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1713 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1714 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1715 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1716 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1717 } \ 1718 } while(0) 1719 1720 Static void 1721 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1722 { 1723 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1724 int i; 1725 uint32_t stop = 0; 1726 1727 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1728 ehci_dump_sqtd(sqtd); 1729 usb_syncmem(&sqtd->dma, 1730 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1731 sizeof(sqtd->qtd), 1732 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1733 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1734 usb_syncmem(&sqtd->dma, 1735 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1736 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1737 } 1738 if (!stop) 1739 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1740 } 1741 1742 Static void 1743 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1744 { 1745 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1746 1747 usb_syncmem(&sqtd->dma, sqtd->offs, 1748 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1749 1750 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1751 0, 0); 1752 ehci_dump_qtd(&sqtd->qtd); 1753 1754 usb_syncmem(&sqtd->dma, sqtd->offs, 1755 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1756 } 1757 1758 Static void 1759 ehci_dump_qh_qtd(struct ehci_qh_qtd_t *qh_qtd) 1760 { 1761 ehci_qtd_t qtd = { 1762 .qtd_next = qh_qtd->qtd_next, 1763 .qtd_altnext = qh_qtd->qtd_altnext, 1764 .qtd_status = qh_qtd->qtd_status, 1765 }; 1766 1767 /* Manually memcpy(), because of volatile. */ 1768 for (unsigned i = 0; i < EHCI_QTD_NBUFFERS; i++) { 1769 qtd.qtd_buffer[i] = qh_qtd->qtd_buffer[i]; 1770 qtd.qtd_buffer_hi[i] = qh_qtd->qtd_buffer_hi[i]; 1771 } 1772 1773 ehci_dump_qtd(&qtd); 1774 } 1775 1776 Static void 1777 ehci_dump_qtd(ehci_qtd_t *qtd) 1778 { 1779 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1780 uint32_t s = le32toh(qtd->qtd_status); 1781 1782 DPRINTFN(10, 1783 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1784 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1785 DPRINTFN(10, 1786 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1787 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1788 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1789 DPRINTFN(10, 1790 " cerr = %jd pid = %jd stat = %jx", 1791 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1792 0); 1793 DPRINTFN(10, 1794 "active =%jd halted=%jd buferr=%jd babble=%jd", 1795 s & EHCI_QTD_ACTIVE ? 1 : 0, 1796 s & EHCI_QTD_HALTED ? 1 : 0, 1797 s & EHCI_QTD_BUFERR ? 1 : 0, 1798 s & EHCI_QTD_BABBLE ? 1 : 0); 1799 DPRINTFN(10, 1800 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1801 s & EHCI_QTD_XACTERR ? 1 : 0, 1802 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1803 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1804 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1805 DPRINTFN(10, 1806 "buffer[0] = %#jx buffer[1] = %#jx " 1807 "buffer[2] = %#jx buffer[3] = %#jx", 1808 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1809 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1810 DPRINTFN(10, 1811 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1812 } 1813 1814 Static void 1815 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1816 { 1817 ehci_qh_t *qh = &sqh->qh; 1818 ehci_link_t link; 1819 uint32_t endp, endphub; 1820 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1821 1822 usb_syncmem(&sqh->dma, sqh->offs, 1823 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1824 1825 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1826 link = le32toh(qh->qh_link); 1827 ehci_dump_link(link, true); 1828 1829 endp = le32toh(qh->qh_endp); 1830 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1831 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1832 "eps = %jd", 1833 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1834 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1835 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1836 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1837 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1838 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1839 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1840 1841 endphub = le32toh(qh->qh_endphub); 1842 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1843 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1844 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1845 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1846 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1847 EHCI_QH_GET_MULT(endphub), 0); 1848 1849 link = le32toh(qh->qh_curqtd); 1850 ehci_dump_link(link, false); 1851 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1852 ehci_dump_qh_qtd(&qh->qh_qtd); 1853 1854 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1855 BUS_DMASYNC_PREREAD); 1856 } 1857 1858 Static void 1859 ehci_dump_itds(ehci_soft_itd_t *itd) 1860 { 1861 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1862 int i; 1863 uint32_t stop = 0; 1864 1865 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1866 ehci_dump_itd(itd); 1867 usb_syncmem(&itd->dma, 1868 itd->offs + offsetof(ehci_itd_t, itd_next), 1869 sizeof(itd->itd), 1870 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1871 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1872 usb_syncmem(&itd->dma, 1873 itd->offs + offsetof(ehci_itd_t, itd_next), 1874 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1875 } 1876 if (!stop) 1877 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1878 } 1879 1880 Static void 1881 ehci_dump_itd(struct ehci_soft_itd *itd) 1882 { 1883 ehci_isoc_trans_t t; 1884 ehci_isoc_bufr_ptr_t b, b2, b3; 1885 int i; 1886 1887 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1888 1889 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0); 1890 1891 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1892 t = le32toh(itd->itd.itd_ctl[i]); 1893 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1894 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1895 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1896 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1897 EHCI_ITD_GET_OFFS(t), 0); 1898 } 1899 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1900 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1901 DPRINTF(" %jx", 1902 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1903 1904 b = le32toh(itd->itd.itd_bufr[0]); 1905 b2 = le32toh(itd->itd.itd_bufr[1]); 1906 b3 = le32toh(itd->itd.itd_bufr[2]); 1907 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1908 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1909 DPRINTF(" maxpkt = %jx multi = %jx", 1910 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1911 } 1912 1913 Static void 1914 ehci_dump_sitd(struct ehci_soft_itd *itd) 1915 { 1916 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1917 1918 DPRINTF("SITD %#jx next = %p prev = %#jx", 1919 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1920 (uintptr_t)itd->frame_list.prev, 0); 1921 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1922 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1923 } 1924 1925 Static void 1926 ehci_dump_exfer(struct ehci_xfer *ex) 1927 { 1928 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1929 1930 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1931 ex->ex_isdone, 0); 1932 1933 switch (ex->ex_type) { 1934 case EX_CTRL: 1935 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1936 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1937 (uintptr_t)ex->ex_status, 0); 1938 break; 1939 case EX_BULK: 1940 case EX_INTR: 1941 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1942 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1943 0, 0); 1944 break; 1945 case EX_ISOC: 1946 DPRINTF(" itdstart = %#jx itdend = %#jx", 1947 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1948 break; 1949 case EX_FS_ISOC: 1950 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1951 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1952 0, 0); 1953 break; 1954 default: 1955 DPRINTF(" unknown type", 0, 0, 0, 0); 1956 } 1957 } 1958 #endif 1959 1960 Static usbd_status 1961 ehci_open(struct usbd_pipe *pipe) 1962 { 1963 struct usbd_device *dev = pipe->up_dev; 1964 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1965 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1966 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1967 uint8_t addr = dev->ud_addr; 1968 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1969 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1970 ehci_soft_qh_t *sqh; 1971 usbd_status err; 1972 int ival, speed, naks; 1973 int hshubaddr, hshubport; 1974 1975 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1976 1977 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1978 ed->bEndpointAddress, rhaddr); 1979 1980 if (dev->ud_myhsport) { 1981 /* 1982 * When directly attached FS/LS device while doing embedded 1983 * transaction translations and we are the hub, set the hub 1984 * address to 0 (us). 1985 */ 1986 if (!(sc->sc_flags & EHCIF_ETTF) 1987 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1988 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1989 } else { 1990 hshubaddr = 0; 1991 } 1992 hshubport = dev->ud_myhsport->up_portno; 1993 } else { 1994 hshubaddr = 0; 1995 hshubport = 0; 1996 } 1997 1998 if (sc->sc_dying) 1999 return USBD_IOERROR; 2000 2001 /* toggle state needed for bulk endpoints */ 2002 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 2003 2004 if (addr == rhaddr) { 2005 switch (ed->bEndpointAddress) { 2006 case USB_CONTROL_ENDPOINT: 2007 pipe->up_methods = &roothub_ctrl_methods; 2008 break; 2009 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2010 pipe->up_methods = &ehci_root_intr_methods; 2011 break; 2012 default: 2013 DPRINTF("bad bEndpointAddress 0x%02jx", 2014 ed->bEndpointAddress, 0, 0, 0); 2015 return USBD_INVAL; 2016 } 2017 return USBD_NORMAL_COMPLETION; 2018 } 2019 2020 /* XXX All this stuff is only valid for async. */ 2021 switch (dev->ud_speed) { 2022 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 2023 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 2024 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 2025 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 2026 } 2027 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 2028 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 2029 0); 2030 return USBD_INVAL; 2031 } 2032 2033 /* 2034 * For interrupt transfer, nak throttling must be disabled, but for 2035 * the other transfer type, nak throttling should be enabled from the 2036 * viewpoint that avoids the memory thrashing. 2037 */ 2038 naks = (xfertype == UE_INTERRUPT) ? 0 2039 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 2040 2041 /* Allocate sqh for everything, save isoc xfers */ 2042 if (xfertype != UE_ISOCHRONOUS) { 2043 sqh = ehci_alloc_sqh(sc); 2044 if (sqh == NULL) 2045 return USBD_NOMEM; 2046 /* qh_link filled when the QH is added */ 2047 sqh->qh.qh_endp = htole32( 2048 EHCI_QH_SET_ADDR(addr) | 2049 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 2050 EHCI_QH_SET_EPS(speed) | 2051 EHCI_QH_DTC | 2052 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 2053 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 2054 EHCI_QH_CTL : 0) | 2055 EHCI_QH_SET_NRL(naks) 2056 ); 2057 sqh->qh.qh_endphub = htole32( 2058 EHCI_QH_SET_MULT(1) | 2059 (xfertype == UE_INTERRUPT ? 2060 EHCI_QH_SET_SMASK(__BIT(1)) /* Start Split Y1 */ 2061 : 0) 2062 ); 2063 if (speed != EHCI_QH_SPEED_HIGH) 2064 sqh->qh.qh_endphub |= htole32( 2065 EHCI_QH_SET_PORT(hshubport) | 2066 EHCI_QH_SET_HUBA(hshubaddr) | 2067 (xfertype == UE_INTERRUPT ? 2068 EHCI_QH_SET_CMASK(__BITS(3,5)) /* CS Y[345] */ 2069 : 0) 2070 ); 2071 sqh->qh.qh_curqtd = EHCI_NULL; 2072 /* Fill the overlay qTD */ 2073 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 2074 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2075 sqh->qh.qh_qtd.qtd_status = htole32(0); 2076 2077 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2078 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2079 epipe->sqh = sqh; 2080 } else { 2081 sqh = NULL; 2082 } /*xfertype == UE_ISOC*/ 2083 2084 switch (xfertype) { 2085 case UE_CONTROL: 2086 /* we can use 64bit DMA for the reqdma buffer */ 2087 err = usb_allocmem(sc->sc_bus.ub_dmatag, 2088 sizeof(usb_device_request_t), 0, USBMALLOC_COHERENT, 2089 &epipe->ctrl.reqdma); 2090 #ifdef EHCI_DEBUG 2091 if (err) 2092 printf("ehci_open: usb_allocmem()=%d\n", err); 2093 #endif 2094 if (err) 2095 goto bad; 2096 pipe->up_methods = &ehci_device_ctrl_methods; 2097 mutex_enter(&sc->sc_lock); 2098 ehci_add_qh(sc, sqh, sc->sc_async_head); 2099 mutex_exit(&sc->sc_lock); 2100 break; 2101 case UE_BULK: 2102 pipe->up_methods = &ehci_device_bulk_methods; 2103 mutex_enter(&sc->sc_lock); 2104 ehci_add_qh(sc, sqh, sc->sc_async_head); 2105 mutex_exit(&sc->sc_lock); 2106 break; 2107 case UE_INTERRUPT: 2108 pipe->up_methods = &ehci_device_intr_methods; 2109 ival = pipe->up_interval; 2110 if (ival == USBD_DEFAULT_INTERVAL) { 2111 if (speed == EHCI_QH_SPEED_HIGH) { 2112 if (ed->bInterval > 16) { 2113 /* 2114 * illegal with high-speed, but there 2115 * were documentation bugs in the spec, 2116 * so be generous 2117 */ 2118 ival = 256; 2119 } else 2120 ival = (1 << (ed->bInterval - 1)) / 8; 2121 } else 2122 ival = ed->bInterval; 2123 } 2124 err = ehci_device_setintr(sc, sqh, ival); 2125 if (err) 2126 goto bad; 2127 break; 2128 case UE_ISOCHRONOUS: 2129 pipe->up_serialise = false; 2130 if (speed == EHCI_QH_SPEED_HIGH) 2131 pipe->up_methods = &ehci_device_isoc_methods; 2132 else 2133 pipe->up_methods = &ehci_device_fs_isoc_methods; 2134 if (ed->bInterval == 0 || ed->bInterval > 16) { 2135 printf("ehci: opening pipe with invalid bInterval\n"); 2136 err = USBD_INVAL; 2137 goto bad; 2138 } 2139 if (UGETW(ed->wMaxPacketSize) == 0) { 2140 printf("ehci: zero length endpoint open request\n"); 2141 err = USBD_INVAL; 2142 goto bad; 2143 } 2144 epipe->isoc.next_frame = 0; 2145 epipe->isoc.cur_xfers = 0; 2146 break; 2147 default: 2148 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2149 err = USBD_INVAL; 2150 goto bad; 2151 } 2152 return USBD_NORMAL_COMPLETION; 2153 2154 bad: 2155 if (sqh != NULL) { 2156 mutex_enter(&sc->sc_lock); 2157 ehci_free_sqh(sc, sqh); 2158 mutex_exit(&sc->sc_lock); 2159 } 2160 return err; 2161 } 2162 2163 /* 2164 * Add an ED to the schedule. Called with USB lock held. 2165 */ 2166 Static void 2167 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2168 { 2169 2170 KASSERT(mutex_owned(&sc->sc_lock)); 2171 2172 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2173 2174 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2175 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2176 2177 sqh->next = head->next; 2178 sqh->qh.qh_link = head->qh.qh_link; 2179 2180 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2181 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2182 2183 head->next = sqh; 2184 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2185 2186 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2187 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2188 2189 #ifdef EHCI_DEBUG 2190 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2191 ehci_dump_sqh(sqh); 2192 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2193 #endif 2194 } 2195 2196 /* 2197 * Remove an ED from the schedule. Called with USB lock held. 2198 */ 2199 Static void 2200 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2201 { 2202 ehci_soft_qh_t *p; 2203 2204 KASSERT(mutex_owned(&sc->sc_lock)); 2205 2206 /* XXX */ 2207 for (p = head; p != NULL && p->next != sqh; p = p->next) 2208 ; 2209 if (p == NULL) 2210 panic("ehci_rem_qh: ED not found"); 2211 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2212 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2213 p->next = sqh->next; 2214 p->qh.qh_link = sqh->qh.qh_link; 2215 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2216 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2217 2218 ehci_sync_hc(sc); 2219 } 2220 2221 Static void 2222 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2223 { 2224 int i; 2225 uint32_t status; 2226 2227 /* Save toggle bit and ping status. */ 2228 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2229 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2230 status = sqh->qh.qh_qtd.qtd_status & 2231 htole32(EHCI_QTD_TOGGLE_MASK | 2232 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2233 /* Set HALTED to make hw leave it alone. */ 2234 sqh->qh.qh_qtd.qtd_status = 2235 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2236 usb_syncmem(&sqh->dma, 2237 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2238 sizeof(sqh->qh.qh_qtd.qtd_status), 2239 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2240 sqh->qh.qh_curqtd = 0; 2241 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2242 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2243 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2244 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2245 sqh->sqtd = sqtd; 2246 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2247 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2248 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2249 sqh->qh.qh_qtd.qtd_status = status; 2250 usb_syncmem(&sqh->dma, 2251 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2252 sizeof(sqh->qh.qh_qtd.qtd_status), 2253 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2254 } 2255 2256 /* 2257 * Ensure that the HC has released all references to the QH. We do this 2258 * by asking for a Async Advance Doorbell interrupt and then we wait for 2259 * the interrupt. 2260 * To make this easier we first obtain exclusive use of the doorbell. 2261 * 2262 * Releases the bus lock to sleep while waiting for interrupt. 2263 */ 2264 Static void 2265 ehci_sync_hc(ehci_softc_t *sc) 2266 { 2267 unsigned delta = hz; 2268 unsigned starttime = getticks(); 2269 unsigned endtime = starttime + delta; 2270 unsigned now; 2271 2272 KASSERT(mutex_owned(&sc->sc_lock)); 2273 2274 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2275 2276 if (sc->sc_dying) { 2277 DPRINTF("dying", 0, 0, 0, 0); 2278 return; 2279 } 2280 2281 /* 2282 * Wait until any concurrent ehci_sync_hc has completed so we 2283 * have exclusive access to the doorbell. 2284 */ 2285 while (sc->sc_doorbelllwp) 2286 cv_wait(&sc->sc_doorbell, &sc->sc_lock); 2287 sc->sc_doorbelllwp = curlwp; 2288 2289 /* ask for doorbell */ 2290 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2291 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2292 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2293 2294 /* 2295 * Wait for the ehci to ring our doorbell. 2296 */ 2297 while (sc->sc_doorbelllwp == curlwp) { 2298 now = getticks(); 2299 if (now - starttime >= delta) { 2300 sc->sc_doorbelllwp = NULL; 2301 cv_broadcast(&sc->sc_doorbell); 2302 DPRINTF("doorbell timeout", 0, 0, 0, 0); 2303 #ifdef DIAGNOSTIC /* XXX DIAGNOSTIC abuse, do this differently */ 2304 printf("ehci_sync_hc: timed out\n"); 2305 #endif 2306 break; 2307 } 2308 (void)cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, 2309 endtime - now); 2310 } 2311 2312 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2313 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2314 } 2315 2316 Static void 2317 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2318 { 2319 2320 KASSERT(mutex_owned(&sc->sc_lock)); 2321 2322 for (; itd != NULL; itd = itd->xfer_next) { 2323 struct ehci_soft_itd *prev = itd->frame_list.prev; 2324 2325 /* Unlink itd from hardware chain, or frame array */ 2326 if (prev == NULL) { /* We're at the table head */ 2327 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2328 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2329 usb_syncmem(&sc->sc_fldma, 2330 sizeof(ehci_link_t) * itd->slot, 2331 sizeof(ehci_link_t), 2332 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2333 2334 if (itd->frame_list.next != NULL) 2335 itd->frame_list.next->frame_list.prev = NULL; 2336 } else { 2337 /* XXX this part is untested... */ 2338 prev->itd.itd_next = itd->itd.itd_next; 2339 usb_syncmem(&itd->dma, 2340 itd->offs + offsetof(ehci_itd_t, itd_next), 2341 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2342 2343 prev->frame_list.next = itd->frame_list.next; 2344 if (itd->frame_list.next != NULL) 2345 itd->frame_list.next->frame_list.prev = prev; 2346 } 2347 } 2348 } 2349 2350 Static void 2351 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2352 { 2353 struct ehci_soft_itd *next; 2354 2355 mutex_enter(&sc->sc_lock); 2356 next = NULL; 2357 for (; itd != NULL; itd = next) { 2358 next = itd->xfer_next; 2359 ehci_free_itd_locked(sc, itd); 2360 } 2361 mutex_exit(&sc->sc_lock); 2362 } 2363 2364 Static void 2365 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2366 { 2367 2368 KASSERT(mutex_owned(&sc->sc_lock)); 2369 2370 for (; sitd != NULL; sitd = sitd->xfer_next) { 2371 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2372 2373 /* Unlink sitd from hardware chain, or frame array */ 2374 if (prev == NULL) { /* We're at the table head */ 2375 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2376 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2377 usb_syncmem(&sc->sc_fldma, 2378 sizeof(ehci_link_t) * sitd->slot, 2379 sizeof(ehci_link_t), 2380 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2381 2382 if (sitd->frame_list.next != NULL) 2383 sitd->frame_list.next->frame_list.prev = NULL; 2384 } else { 2385 /* XXX this part is untested... */ 2386 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2387 usb_syncmem(&sitd->dma, 2388 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2389 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2390 2391 prev->frame_list.next = sitd->frame_list.next; 2392 if (sitd->frame_list.next != NULL) 2393 sitd->frame_list.next->frame_list.prev = prev; 2394 } 2395 } 2396 } 2397 2398 Static void 2399 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2400 { 2401 2402 mutex_enter(&sc->sc_lock); 2403 struct ehci_soft_sitd *next = NULL; 2404 for (; sitd != NULL; sitd = next) { 2405 next = sitd->xfer_next; 2406 ehci_free_sitd_locked(sc, sitd); 2407 } 2408 mutex_exit(&sc->sc_lock); 2409 } 2410 2411 /***********/ 2412 2413 static int 2414 ehci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req, 2415 void *buf, int buflen) 2416 { 2417 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2418 usb_hub_descriptor_t hubd; 2419 usb_port_status_t ps; 2420 uint16_t len, value, index; 2421 int l, totlen = 0; 2422 int port, i; 2423 uint32_t v; 2424 2425 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2426 2427 KASSERT(mutex_owned(&sc->sc_rhlock)); 2428 2429 if (sc->sc_dying) 2430 return -1; 2431 2432 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2433 0, 0); 2434 2435 len = UGETW(req->wLength); 2436 value = UGETW(req->wValue); 2437 index = UGETW(req->wIndex); 2438 2439 #define C(x,y) ((x) | ((y) << 8)) 2440 switch (C(req->bRequest, req->bmRequestType)) { 2441 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2442 if (len == 0) 2443 break; 2444 switch (value) { 2445 #define sd ((usb_string_descriptor_t *)buf) 2446 case C(2, UDESC_STRING): 2447 /* Product */ 2448 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2449 break; 2450 #undef sd 2451 default: 2452 /* default from usbroothub */ 2453 return buflen; 2454 } 2455 break; 2456 2457 /* Hub requests */ 2458 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2459 break; 2460 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2461 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2462 value, 0, 0); 2463 if (index < 1 || index > sc->sc_noport) { 2464 return -1; 2465 } 2466 port = EHCI_PORTSC(index); 2467 v = EOREAD4(sc, port); 2468 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2469 v &= ~EHCI_PS_CLEAR; 2470 switch (value) { 2471 case UHF_PORT_ENABLE: 2472 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2473 break; 2474 case UHF_PORT_SUSPEND: 2475 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2476 break; 2477 v &= ~EHCI_PS_SUSP; 2478 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2479 /* see USB2 spec ch. 7.1.7.7 */ 2480 usb_delay_ms(&sc->sc_bus, 20); 2481 EOWRITE4(sc, port, v); 2482 usb_delay_ms(&sc->sc_bus, 2); 2483 #ifdef DEBUG 2484 v = EOREAD4(sc, port); 2485 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2486 printf("ehci: resume failed: %x\n", v); 2487 #endif 2488 break; 2489 case UHF_PORT_POWER: 2490 if (sc->sc_hasppc) 2491 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2492 break; 2493 case UHF_PORT_TEST: 2494 DPRINTF("clear port test %jd", index, 0, 0, 0); 2495 break; 2496 case UHF_PORT_INDICATOR: 2497 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2498 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2499 break; 2500 case UHF_C_PORT_CONNECTION: 2501 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2502 break; 2503 case UHF_C_PORT_ENABLE: 2504 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2505 break; 2506 case UHF_C_PORT_SUSPEND: 2507 /* how? */ 2508 break; 2509 case UHF_C_PORT_OVER_CURRENT: 2510 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2511 break; 2512 case UHF_C_PORT_RESET: 2513 sc->sc_isreset[index] = 0; 2514 break; 2515 default: 2516 return -1; 2517 } 2518 #if 0 2519 switch(value) { 2520 case UHF_C_PORT_CONNECTION: 2521 case UHF_C_PORT_ENABLE: 2522 case UHF_C_PORT_SUSPEND: 2523 case UHF_C_PORT_OVER_CURRENT: 2524 case UHF_C_PORT_RESET: 2525 default: 2526 break; 2527 } 2528 #endif 2529 break; 2530 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2531 if (len == 0) 2532 break; 2533 if ((value & 0xff) != 0) { 2534 return -1; 2535 } 2536 totlen = uimin(buflen, sizeof(hubd)); 2537 memcpy(&hubd, buf, totlen); 2538 hubd.bNbrPorts = sc->sc_noport; 2539 v = EREAD4(sc, EHCI_HCSPARAMS); 2540 USETW(hubd.wHubCharacteristics, 2541 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2542 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2543 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2544 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2545 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2546 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2547 totlen = uimin(totlen, hubd.bDescLength); 2548 memcpy(buf, &hubd, totlen); 2549 break; 2550 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2551 if (len != 4) { 2552 return -1; 2553 } 2554 memset(buf, 0, len); /* ? XXX */ 2555 totlen = len; 2556 break; 2557 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2558 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2559 if (index < 1 || index > sc->sc_noport) { 2560 return -1; 2561 } 2562 if (len != 4) { 2563 return -1; 2564 } 2565 v = EOREAD4(sc, EHCI_PORTSC(index)); 2566 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2567 2568 i = UPS_HIGH_SPEED; 2569 if (sc->sc_flags & EHCIF_ETTF) { 2570 /* 2571 * If we are doing embedded transaction translation, 2572 * then directly attached LS/FS devices are reset by 2573 * the EHCI controller itself. PSPD is encoded 2574 * the same way as in USBSTATUS. 2575 */ 2576 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2577 } 2578 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2579 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2580 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2581 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2582 if (v & EHCI_PS_PR) i |= UPS_RESET; 2583 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2584 if (sc->sc_vendor_port_status) 2585 i = sc->sc_vendor_port_status(sc, v, i); 2586 USETW(ps.wPortStatus, i); 2587 i = 0; 2588 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2589 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2590 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2591 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2592 USETW(ps.wPortChange, i); 2593 totlen = uimin(len, sizeof(ps)); 2594 memcpy(buf, &ps, totlen); 2595 break; 2596 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2597 return -1; 2598 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2599 break; 2600 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2601 if (index < 1 || index > sc->sc_noport) { 2602 return -1; 2603 } 2604 port = EHCI_PORTSC(index); 2605 v = EOREAD4(sc, port); 2606 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2607 v &= ~EHCI_PS_CLEAR; 2608 switch(value) { 2609 case UHF_PORT_ENABLE: 2610 EOWRITE4(sc, port, v | EHCI_PS_PE); 2611 break; 2612 case UHF_PORT_SUSPEND: 2613 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2614 break; 2615 case UHF_PORT_RESET: 2616 DPRINTF("reset port %jd", index, 0, 0, 0); 2617 if (EHCI_PS_IS_LOWSPEED(v) 2618 && sc->sc_ncomp > 0 2619 && !(sc->sc_flags & EHCIF_ETTF)) { 2620 /* 2621 * Low speed device on non-ETTF controller or 2622 * unaccompanied controller, give up ownership. 2623 */ 2624 ehci_disown(sc, index, 1); 2625 break; 2626 } 2627 /* Start reset sequence. */ 2628 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2629 EOWRITE4(sc, port, v | EHCI_PS_PR); 2630 /* Wait for reset to complete. */ 2631 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2632 if (sc->sc_dying) { 2633 return -1; 2634 } 2635 /* 2636 * An embedded transaction translator will automatically 2637 * terminate the reset sequence so there's no need to 2638 * it. 2639 */ 2640 v = EOREAD4(sc, port); 2641 if (v & EHCI_PS_PR) { 2642 /* Terminate reset sequence. */ 2643 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2644 /* Wait for HC to complete reset. */ 2645 usb_delay_ms(&sc->sc_bus, 2646 EHCI_PORT_RESET_COMPLETE); 2647 if (sc->sc_dying) { 2648 return -1; 2649 } 2650 } 2651 2652 v = EOREAD4(sc, port); 2653 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2654 if (v & EHCI_PS_PR) { 2655 printf("%s: port reset timeout\n", 2656 device_xname(sc->sc_dev)); 2657 return USBD_TIMEOUT; 2658 } 2659 if (!(v & EHCI_PS_PE)) { 2660 /* Not a high speed device, give up ownership.*/ 2661 ehci_disown(sc, index, 0); 2662 break; 2663 } 2664 sc->sc_isreset[index] = 1; 2665 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2666 v, 0, 0); 2667 break; 2668 case UHF_PORT_POWER: 2669 DPRINTF("set port power %jd (has PPC = %jd)", index, 2670 sc->sc_hasppc, 0, 0); 2671 if (sc->sc_hasppc) 2672 EOWRITE4(sc, port, v | EHCI_PS_PP); 2673 break; 2674 case UHF_PORT_TEST: 2675 DPRINTF("set port test %jd", index, 0, 0, 0); 2676 break; 2677 case UHF_PORT_INDICATOR: 2678 DPRINTF("set port ind %jd", index, 0, 0, 0); 2679 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2680 break; 2681 default: 2682 return -1; 2683 } 2684 break; 2685 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2686 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2687 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2688 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2689 break; 2690 default: 2691 /* default from usbroothub */ 2692 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2693 2694 return buflen; 2695 } 2696 2697 DPRINTF("returning %jd", totlen, 0, 0, 0); 2698 2699 return totlen; 2700 } 2701 2702 Static int 2703 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2704 void *buf, int buflen) 2705 { 2706 struct ehci_softc *sc = EHCI_BUS2SC(bus); 2707 int actlen; 2708 2709 mutex_enter(&sc->sc_rhlock); 2710 actlen = ehci_roothub_ctrl_locked(bus, req, buf, buflen); 2711 mutex_exit(&sc->sc_rhlock); 2712 2713 return actlen; 2714 } 2715 2716 /* 2717 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2718 * 2719 * This pile of garbage below works around the following problem without 2720 * holding boots with no hand-over devices present, while penalising 2721 * boots where the first ehci probe hands off devices with a 5 second 2722 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2723 * for RB_SINGLE, but the same basic issue exists. 2724 * 2725 * The way ehci hand-off works, the companion controller does not get the 2726 * device until after its initial bus explore, so the reference dropped 2727 * after the first explore is not enough. 5 seconds should be enough, 2728 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2729 * 2730 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2731 * if the callback is scheduled. CO_DONE is set when the callout has 2732 * called config_pending_decr(). 2733 * 2734 * There's a mutex, a cv and a callout here, and we delay detach if the 2735 * callout has been set. 2736 */ 2737 #ifndef EHCI_DISOWN_DELAY_SECONDS 2738 #define EHCI_DISOWN_DELAY_SECONDS 5 2739 #endif 2740 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2741 2742 static void 2743 ehci_disown_callback(void *arg) 2744 { 2745 ehci_softc_t *sc = arg; 2746 2747 config_pending_decr(sc->sc_dev); 2748 2749 mutex_enter(&sc->sc_complock); 2750 KASSERT(sc->sc_comp_state == CO_SCHED); 2751 sc->sc_comp_state = CO_DONE; 2752 cv_signal(&sc->sc_compcv); 2753 mutex_exit(&sc->sc_complock); 2754 } 2755 2756 static void 2757 ehci_disown_sched_callback(ehci_softc_t *sc) 2758 { 2759 extern bool root_is_mounted; 2760 2761 mutex_enter(&sc->sc_complock); 2762 2763 if (root_is_mounted || 2764 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2765 sc->sc_comp_state != CO_EARLY) { 2766 mutex_exit(&sc->sc_complock); 2767 return; 2768 } 2769 2770 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2771 ehci_disown_callback, &sc->sc_dev); 2772 sc->sc_comp_state = CO_SCHED; 2773 2774 mutex_exit(&sc->sc_complock); 2775 2776 config_pending_incr(sc->sc_dev); 2777 aprint_normal_dev(sc->sc_dev, 2778 "delaying %s by %u seconds due to USB owner change.\n", 2779 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user", 2780 ehci_disown_delay_seconds); 2781 } 2782 2783 Static void 2784 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2785 { 2786 int port; 2787 uint32_t v; 2788 2789 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2790 2791 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2792 if (sc->sc_npcomp != 0) { 2793 int i = (index-1) / sc->sc_npcomp; 2794 if (i < sc->sc_ncomp) { 2795 ehci_disown_sched_callback(sc); 2796 #ifdef DIAGNOSTIC 2797 printf("%s: handing over %s speed device on " 2798 "port %d to %s\n", 2799 device_xname(sc->sc_dev), 2800 lowspeed ? "low" : "full", 2801 index, sc->sc_comps[i] ? 2802 device_xname(sc->sc_comps[i]) : 2803 "companion controller"); 2804 } else { 2805 printf("%s: strange port\n", 2806 device_xname(sc->sc_dev)); 2807 #endif 2808 } 2809 } else { 2810 #ifdef DIAGNOSTIC 2811 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2812 #endif 2813 } 2814 port = EHCI_PORTSC(index); 2815 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2816 EOWRITE4(sc, port, v | EHCI_PS_PO); 2817 } 2818 2819 Static usbd_status 2820 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2821 { 2822 2823 /* Pipe isn't running, start first */ 2824 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2825 } 2826 2827 Static usbd_status 2828 ehci_root_intr_start(struct usbd_xfer *xfer) 2829 { 2830 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2831 2832 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2833 2834 if (sc->sc_dying) 2835 return USBD_IOERROR; 2836 2837 KASSERT(sc->sc_intrxfer == NULL); 2838 sc->sc_intrxfer = xfer; 2839 xfer->ux_status = USBD_IN_PROGRESS; 2840 2841 return USBD_IN_PROGRESS; 2842 } 2843 2844 /* Abort a root interrupt request. */ 2845 Static void 2846 ehci_root_intr_abort(struct usbd_xfer *xfer) 2847 { 2848 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2849 2850 KASSERT(mutex_owned(&sc->sc_lock)); 2851 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2852 2853 /* If xfer has already completed, nothing to do here. */ 2854 if (sc->sc_intrxfer == NULL) 2855 return; 2856 2857 /* 2858 * Otherwise, sc->sc_intrxfer had better be this transfer. 2859 * Cancel it. 2860 */ 2861 KASSERT(sc->sc_intrxfer == xfer); 2862 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2863 xfer->ux_status = USBD_CANCELLED; 2864 usb_transfer_complete(xfer); 2865 } 2866 2867 /* Close the root pipe. */ 2868 Static void 2869 ehci_root_intr_close(struct usbd_pipe *pipe) 2870 { 2871 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2872 2873 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2874 2875 KASSERT(mutex_owned(&sc->sc_lock)); 2876 2877 /* 2878 * Caller must guarantee the xfer has completed first, by 2879 * closing the pipe only after normal completion or an abort. 2880 */ 2881 KASSERT(sc->sc_intrxfer == NULL); 2882 } 2883 2884 Static void 2885 ehci_root_intr_done(struct usbd_xfer *xfer) 2886 { 2887 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2888 2889 KASSERT(mutex_owned(&sc->sc_lock)); 2890 2891 /* Claim the xfer so it doesn't get completed again. */ 2892 KASSERT(sc->sc_intrxfer == xfer); 2893 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2894 sc->sc_intrxfer = NULL; 2895 } 2896 2897 /************************/ 2898 2899 Static ehci_soft_qh_t * 2900 ehci_alloc_sqh(ehci_softc_t *sc) 2901 { 2902 ehci_soft_qh_t *sqh; 2903 2904 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2905 2906 mutex_enter(&sc->sc_lock); 2907 if (sc->sc_freeqhs == NULL) { 2908 DPRINTF("allocating chunk", 0, 0, 0, 0); 2909 mutex_exit(&sc->sc_lock); 2910 2911 usb_dma_t dma; 2912 int err = usb_allocmem(sc->sc_dmatag, 2913 EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2914 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2915 2916 if (err) { 2917 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2918 return NULL; 2919 } 2920 2921 mutex_enter(&sc->sc_lock); 2922 for (size_t i = 0; i < EHCI_SQH_CHUNK; i++) { 2923 const int offs = i * EHCI_SQH_SIZE; 2924 const bus_addr_t baddr = DMAADDR(&dma, offs); 2925 2926 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2927 2928 sqh = KERNADDR(&dma, offs); 2929 sqh->physaddr = BUS_ADDR_LO32(baddr); 2930 sqh->dma = dma; 2931 sqh->offs = offs; 2932 2933 sqh->next = sc->sc_freeqhs; 2934 sc->sc_freeqhs = sqh; 2935 } 2936 } 2937 sqh = sc->sc_freeqhs; 2938 sc->sc_freeqhs = sqh->next; 2939 mutex_exit(&sc->sc_lock); 2940 2941 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2942 sqh->next = NULL; 2943 return sqh; 2944 } 2945 2946 Static void 2947 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2948 { 2949 KASSERT(mutex_owned(&sc->sc_lock)); 2950 2951 sqh->next = sc->sc_freeqhs; 2952 sc->sc_freeqhs = sqh; 2953 } 2954 2955 Static ehci_soft_qtd_t * 2956 ehci_alloc_sqtd(ehci_softc_t *sc) 2957 { 2958 ehci_soft_qtd_t *sqtd = NULL; 2959 2960 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2961 2962 mutex_enter(&sc->sc_lock); 2963 if (sc->sc_freeqtds == NULL) { 2964 DPRINTF("allocating chunk", 0, 0, 0, 0); 2965 mutex_exit(&sc->sc_lock); 2966 2967 usb_dma_t dma; 2968 int err = usb_allocmem(sc->sc_dmatag, 2969 EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK, 2970 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 2971 2972 if (err) { 2973 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2974 return NULL; 2975 } 2976 2977 mutex_enter(&sc->sc_lock); 2978 for (size_t i = 0; i < EHCI_SQTD_CHUNK; i++) { 2979 const int offs = i * EHCI_SQTD_SIZE; 2980 const bus_addr_t baddr = DMAADDR(&dma, offs); 2981 2982 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2983 2984 sqtd = KERNADDR(&dma, offs); 2985 sqtd->physaddr = BUS_ADDR_LO32(baddr); 2986 sqtd->dma = dma; 2987 sqtd->offs = offs; 2988 2989 sqtd->nextqtd = sc->sc_freeqtds; 2990 sc->sc_freeqtds = sqtd; 2991 } 2992 } 2993 2994 sqtd = sc->sc_freeqtds; 2995 sc->sc_freeqtds = sqtd->nextqtd; 2996 mutex_exit(&sc->sc_lock); 2997 2998 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2999 sqtd->nextqtd = NULL; 3000 sqtd->xfer = NULL; 3001 3002 return sqtd; 3003 } 3004 3005 Static void 3006 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 3007 { 3008 3009 mutex_enter(&sc->sc_lock); 3010 sqtd->nextqtd = sc->sc_freeqtds; 3011 sc->sc_freeqtds = sqtd; 3012 mutex_exit(&sc->sc_lock); 3013 } 3014 3015 Static int 3016 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3017 int alen, int rd, ehci_soft_qtd_t **sp) 3018 { 3019 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3020 uint16_t flags = xfer->ux_flags; 3021 3022 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3023 3024 ASSERT_SLEEPABLE(); 3025 KASSERT(sp); 3026 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 3027 3028 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 3029 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 3030 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 3031 KM_SLEEP); 3032 exfer->ex_nsqtd = nsqtd; 3033 3034 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 3035 alen, nsqtd, flags); 3036 3037 for (size_t j = 0; j < exfer->ex_nsqtd;) { 3038 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 3039 if (cur == NULL) 3040 goto nomem; 3041 exfer->ex_sqtds[j++] = cur; 3042 3043 cur->xfer = xfer; 3044 cur->len = 0; 3045 3046 } 3047 3048 *sp = exfer->ex_sqtds[0]; 3049 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 3050 3051 return 0; 3052 3053 nomem: 3054 ehci_free_sqtds(sc, exfer); 3055 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 3056 DPRINTF("no memory", 0, 0, 0, 0); 3057 return ENOMEM; 3058 } 3059 3060 Static void 3061 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 3062 { 3063 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3064 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 3065 3066 mutex_enter(&sc->sc_lock); 3067 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 3068 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 3069 3070 if (sqtd == NULL) 3071 break; 3072 3073 sqtd->nextqtd = sc->sc_freeqtds; 3074 sc->sc_freeqtds = sqtd; 3075 } 3076 mutex_exit(&sc->sc_lock); 3077 } 3078 3079 Static void 3080 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 3081 { 3082 if (prev) { 3083 prev->nextqtd = sqtd; 3084 prev->qtd.qtd_next = htole32(sqtd->physaddr); 3085 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 3086 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 3087 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3088 } 3089 } 3090 3091 Static void 3092 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3093 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3094 { 3095 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3096 usb_dma_t *dma = &xfer->ux_dmabuf; 3097 uint16_t flags = xfer->ux_flags; 3098 ehci_soft_qtd_t *sqtd, *prev; 3099 int tog = *toggle; 3100 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3101 int len = length; 3102 3103 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3104 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 3105 len, isread, tog); 3106 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 3107 0, 0, 0); 3108 3109 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 3110 3111 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3112 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3113 EHCI_QTD_SET_CERR(3) 3114 ; 3115 3116 sqtd = prev = NULL; 3117 size_t curoffs = 0; 3118 size_t j = 0; 3119 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3120 sqtd = exfer->ex_sqtds[j++]; 3121 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3122 (uintptr_t)prev, 0); 3123 3124 /* 3125 * The EHCI hardware can handle at most 5 pages and they do 3126 * not have to be contiguous 3127 */ 3128 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3129 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3130 size_t curlen = len; 3131 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3132 /* must use multiple TDs, fill as much as possible. */ 3133 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3134 3135 /* the length must be a multiple of the max size */ 3136 curlen -= curlen % mps; 3137 } 3138 KASSERT(curlen != 0); 3139 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3140 curoffs, 0); 3141 3142 /* Fill the qTD */ 3143 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3144 sqtd->qtd.qtd_status = htole32( 3145 qtdstatus | 3146 EHCI_QTD_SET_BYTES(curlen) | 3147 EHCI_QTD_SET_TOGGLE(tog)); 3148 3149 /* Find number of pages we'll be using, insert dma addresses */ 3150 size_t pages = EHCI_NPAGES(curlen); 3151 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3152 size_t pageoffs = EHCI_PAGE(curoffs); 3153 for (size_t i = 0; i < pages; i++) { 3154 paddr_t a = EHCI_PAGE(DMAADDR(dma, 3155 pageoffs + i * EHCI_PAGE_SIZE)); 3156 sqtd->qtd.qtd_buffer[i] = htole32(BUS_ADDR_LO32(a)); 3157 sqtd->qtd.qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a)); 3158 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3159 i, pages, 3160 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 3161 le32toh(sqtd->qtd.qtd_buffer[i])); 3162 } 3163 /* First buffer pointer requires a page offset to start at */ 3164 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 3165 3166 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3168 3169 sqtd->len = curlen; 3170 3171 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3172 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3173 3174 ehci_append_sqtd(sqtd, prev); 3175 3176 if (howmany(curlen, mps) & 1) { 3177 tog ^= 1; 3178 } 3179 3180 curoffs += curlen; 3181 len -= curlen; 3182 } 3183 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3184 xfer, length, len, mps, exfer->ex_nsqtd, j); 3185 3186 if (!isread && 3187 (flags & USBD_FORCE_SHORT_XFER) && 3188 length % mps == 0) { 3189 /* Force a 0 length transfer at the end. */ 3190 3191 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3192 exfer->ex_nsqtd); 3193 prev = sqtd; 3194 sqtd = exfer->ex_sqtds[j++]; 3195 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 3196 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 3197 sqtd->qtd.qtd_status = htole32( 3198 qtdstatus | 3199 EHCI_QTD_SET_BYTES(0) | 3200 EHCI_QTD_SET_TOGGLE(tog)); 3201 3202 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 3203 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3204 3205 ehci_append_sqtd(sqtd, prev); 3206 tog ^= 1; 3207 } 3208 3209 *lsqtd = sqtd; 3210 *toggle = tog; 3211 } 3212 3213 Static ehci_soft_itd_t * 3214 ehci_alloc_itd(ehci_softc_t *sc) 3215 { 3216 struct ehci_soft_itd *itd, *freeitd; 3217 3218 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3219 3220 mutex_enter(&sc->sc_lock); 3221 3222 freeitd = LIST_FIRST(&sc->sc_freeitds); 3223 if (freeitd == NULL) { 3224 DPRINTF("allocating chunk", 0, 0, 0, 0); 3225 mutex_exit(&sc->sc_lock); 3226 3227 usb_dma_t dma; 3228 int err = usb_allocmem(sc->sc_dmatag, 3229 EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3230 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3231 3232 if (err) { 3233 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3234 return NULL; 3235 } 3236 3237 mutex_enter(&sc->sc_lock); 3238 for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) { 3239 const int offs = i * EHCI_ITD_SIZE; 3240 const bus_addr_t baddr = DMAADDR(&dma, offs); 3241 3242 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3243 3244 itd = KERNADDR(&dma, offs); 3245 itd->physaddr = BUS_ADDR_LO32(baddr); 3246 itd->dma = dma; 3247 itd->offs = offs; 3248 3249 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3250 } 3251 freeitd = LIST_FIRST(&sc->sc_freeitds); 3252 } 3253 3254 itd = freeitd; 3255 LIST_REMOVE(itd, free_list); 3256 mutex_exit(&sc->sc_lock); 3257 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3258 3259 itd->frame_list.next = NULL; 3260 itd->frame_list.prev = NULL; 3261 itd->xfer_next = NULL; 3262 itd->slot = 0; 3263 3264 return itd; 3265 } 3266 3267 Static ehci_soft_sitd_t * 3268 ehci_alloc_sitd(ehci_softc_t *sc) 3269 { 3270 struct ehci_soft_sitd *sitd, *freesitd; 3271 3272 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3273 3274 mutex_enter(&sc->sc_lock); 3275 freesitd = LIST_FIRST(&sc->sc_freesitds); 3276 if (freesitd == NULL) { 3277 DPRINTF("allocating chunk", 0, 0, 0, 0); 3278 mutex_exit(&sc->sc_lock); 3279 3280 usb_dma_t dma; 3281 int err = usb_allocmem(sc->sc_dmatag, 3282 EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3283 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3284 3285 if (err) { 3286 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3287 return NULL; 3288 } 3289 3290 mutex_enter(&sc->sc_lock); 3291 for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) { 3292 const int offs = i * EHCI_SITD_SIZE; 3293 const bus_addr_t baddr = DMAADDR(&dma, offs); 3294 3295 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3296 3297 sitd = KERNADDR(&dma, offs); 3298 sitd->physaddr = BUS_ADDR_LO32(baddr); 3299 sitd->dma = dma; 3300 sitd->offs = offs; 3301 3302 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3303 } 3304 freesitd = LIST_FIRST(&sc->sc_freesitds); 3305 } 3306 3307 sitd = freesitd; 3308 LIST_REMOVE(sitd, free_list); 3309 mutex_exit(&sc->sc_lock); 3310 3311 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3312 3313 sitd->frame_list.next = NULL; 3314 sitd->frame_list.prev = NULL; 3315 sitd->xfer_next = NULL; 3316 sitd->slot = 0; 3317 3318 return sitd; 3319 } 3320 3321 /****************/ 3322 3323 /* 3324 * Close a regular pipe. 3325 * Assumes that there are no pending transactions. 3326 */ 3327 Static void 3328 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3329 { 3330 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3331 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3332 ehci_soft_qh_t *sqh = epipe->sqh; 3333 3334 KASSERT(mutex_owned(&sc->sc_lock)); 3335 3336 ehci_rem_qh(sc, sqh, head); 3337 ehci_free_sqh(sc, epipe->sqh); 3338 } 3339 3340 /* 3341 * Arrange for the hardware to tells us that it is not still 3342 * processing the TDs by setting the QH halted bit and wait for the ehci 3343 * door bell 3344 */ 3345 Static void 3346 ehci_abortx(struct usbd_xfer *xfer) 3347 { 3348 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3349 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3350 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3351 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3352 ehci_soft_qh_t *sqh = epipe->sqh; 3353 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3354 ehci_physaddr_t cur; 3355 uint32_t qhstatus; 3356 int hit; 3357 3358 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3359 3360 KASSERT(mutex_owned(&sc->sc_lock)); 3361 ASSERT_SLEEPABLE(); 3362 3363 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3364 xfer->ux_status == USBD_TIMEOUT), 3365 "bad abort status: %d", xfer->ux_status); 3366 3367 /* 3368 * If we're dying, skip the hardware action and just notify the 3369 * software that we're done. 3370 */ 3371 if (sc->sc_dying) { 3372 goto dying; 3373 } 3374 3375 /* 3376 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3377 */ 3378 ehci_del_intr_list(sc, exfer); 3379 3380 usb_syncmem(&sqh->dma, 3381 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3382 sizeof(sqh->qh.qh_qtd.qtd_status), 3383 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3384 qhstatus = sqh->qh.qh_qtd.qtd_status; 3385 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3386 usb_syncmem(&sqh->dma, 3387 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3388 sizeof(sqh->qh.qh_qtd.qtd_status), 3389 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3390 3391 if (exfer->ex_type == EX_CTRL) { 3392 fsqtd = exfer->ex_setup; 3393 lsqtd = exfer->ex_status; 3394 } else { 3395 fsqtd = exfer->ex_sqtdstart; 3396 lsqtd = exfer->ex_sqtdend; 3397 } 3398 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3399 usb_syncmem(&sqtd->dma, 3400 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3401 sizeof(sqtd->qtd.qtd_status), 3402 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3403 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3404 usb_syncmem(&sqtd->dma, 3405 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3406 sizeof(sqtd->qtd.qtd_status), 3407 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3408 if (sqtd == lsqtd) 3409 break; 3410 } 3411 3412 /* 3413 * HC Step 2: Wait until we know hardware has finished any possible 3414 * use of the xfer. 3415 */ 3416 ehci_sync_hc(sc); 3417 3418 /* 3419 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3420 * The complication here is that the hardware may have executed 3421 * beyond the xfer we're trying to abort. So as we're scanning 3422 * the TDs of this xfer we check if the hardware points to 3423 * any of them. 3424 */ 3425 3426 usb_syncmem(&sqh->dma, 3427 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3428 sizeof(sqh->qh.qh_curqtd), 3429 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3430 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3431 hit = 0; 3432 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3433 hit |= cur == sqtd->physaddr; 3434 if (sqtd == lsqtd) 3435 break; 3436 } 3437 sqtd = sqtd->nextqtd; 3438 /* Zap curqtd register if hardware pointed inside the xfer. */ 3439 if (hit && sqtd != NULL) { 3440 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3441 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3442 usb_syncmem(&sqh->dma, 3443 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3444 sizeof(sqh->qh.qh_curqtd), 3445 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3446 sqh->qh.qh_qtd.qtd_status = qhstatus; 3447 usb_syncmem(&sqh->dma, 3448 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3449 sizeof(sqh->qh.qh_qtd.qtd_status), 3450 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3451 } else { 3452 DPRINTF("no hit", 0, 0, 0, 0); 3453 usb_syncmem(&sqh->dma, 3454 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3455 sizeof(sqh->qh.qh_curqtd), 3456 BUS_DMASYNC_PREREAD); 3457 } 3458 3459 dying: 3460 #ifdef DIAGNOSTIC 3461 exfer->ex_isdone = true; 3462 #endif 3463 DPRINTFN(14, "end", 0, 0, 0, 0); 3464 3465 KASSERT(mutex_owned(&sc->sc_lock)); 3466 } 3467 3468 Static void 3469 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3470 { 3471 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3472 ehci_isoc_trans_t trans_status; 3473 struct ehci_xfer *exfer; 3474 ehci_softc_t *sc; 3475 struct ehci_soft_itd *itd; 3476 struct ehci_soft_sitd *sitd; 3477 int i; 3478 3479 KASSERTMSG(status == USBD_CANCELLED, 3480 "invalid status for abort: %d", (int)status); 3481 3482 exfer = EHCI_XFER2EXFER(xfer); 3483 sc = EHCI_XFER2SC(xfer); 3484 3485 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3486 (uintptr_t)xfer->ux_pipe, 0, 0); 3487 3488 KASSERT(mutex_owned(&sc->sc_lock)); 3489 ASSERT_SLEEPABLE(); 3490 3491 /* No timeout or task here. */ 3492 3493 /* 3494 * The xfer cannot have been cancelled already. It is the 3495 * responsibility of the caller of usbd_abort_pipe not to try 3496 * to abort a pipe multiple times, whether concurrently or 3497 * sequentially. 3498 */ 3499 KASSERT(xfer->ux_status != USBD_CANCELLED); 3500 3501 /* If anyone else beat us, we're done. */ 3502 if (xfer->ux_status != USBD_IN_PROGRESS) 3503 return; 3504 3505 /* We beat everyone else. Claim the status. */ 3506 xfer->ux_status = status; 3507 3508 /* 3509 * If we're dying, skip the hardware action and just notify the 3510 * software that we're done. 3511 */ 3512 if (sc->sc_dying) { 3513 goto dying; 3514 } 3515 3516 /* 3517 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3518 */ 3519 ehci_del_intr_list(sc, exfer); 3520 3521 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3522 for (itd = exfer->ex_itdstart; itd != NULL; 3523 itd = itd->xfer_next) { 3524 usb_syncmem(&itd->dma, 3525 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3526 sizeof(itd->itd.itd_ctl), 3527 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3528 3529 for (i = 0; i < 8; i++) { 3530 trans_status = le32toh(itd->itd.itd_ctl[i]); 3531 trans_status &= ~EHCI_ITD_ACTIVE; 3532 itd->itd.itd_ctl[i] = htole32(trans_status); 3533 } 3534 3535 usb_syncmem(&itd->dma, 3536 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3537 sizeof(itd->itd.itd_ctl), 3538 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3539 } 3540 } else { 3541 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3542 sitd = sitd->xfer_next) { 3543 usb_syncmem(&sitd->dma, 3544 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3545 sizeof(sitd->sitd.sitd_buffer), 3546 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3547 3548 trans_status = le32toh(sitd->sitd.sitd_trans); 3549 trans_status &= ~EHCI_SITD_ACTIVE; 3550 sitd->sitd.sitd_trans = htole32(trans_status); 3551 3552 usb_syncmem(&sitd->dma, 3553 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3554 sizeof(sitd->sitd.sitd_buffer), 3555 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3556 } 3557 } 3558 3559 dying: 3560 #ifdef DIAGNOSTIC 3561 exfer->ex_isdone = true; 3562 #endif 3563 usb_transfer_complete(xfer); 3564 DPRINTFN(14, "end", 0, 0, 0, 0); 3565 3566 KASSERT(mutex_owned(&sc->sc_lock)); 3567 } 3568 3569 /************************/ 3570 3571 Static int 3572 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3573 { 3574 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3575 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3576 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3577 usb_device_request_t *req = &xfer->ux_request; 3578 ehci_soft_qtd_t *setup, *status, *next; 3579 int isread = req->bmRequestType & UT_READ; 3580 int len = xfer->ux_bufsize; 3581 int err; 3582 3583 exfer->ex_type = EX_CTRL; 3584 exfer->ex_status = NULL; 3585 exfer->ex_data = NULL; 3586 exfer->ex_setup = ehci_alloc_sqtd(sc); 3587 if (exfer->ex_setup == NULL) { 3588 err = ENOMEM; 3589 goto bad1; 3590 } 3591 exfer->ex_status = ehci_alloc_sqtd(sc); 3592 if (exfer->ex_status == NULL) { 3593 err = ENOMEM; 3594 goto bad2; 3595 } 3596 setup = exfer->ex_setup; 3597 status = exfer->ex_status; 3598 exfer->ex_nsqtd = 0; 3599 next = status; 3600 /* Set up data transaction */ 3601 if (len != 0) { 3602 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3603 &exfer->ex_data); 3604 if (err) 3605 goto bad3; 3606 next = exfer->ex_data; 3607 } 3608 3609 /* Clear toggle */ 3610 setup->qtd.qtd_status = htole32( 3611 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3612 EHCI_QTD_SET_TOGGLE(0) | 3613 EHCI_QTD_SET_BYTES(sizeof(*req)) 3614 ); 3615 3616 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3617 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3618 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3619 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3620 setup->nextqtd = next; 3621 setup->xfer = xfer; 3622 setup->len = sizeof(*req); 3623 3624 status->qtd.qtd_status = htole32( 3625 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3626 EHCI_QTD_SET_TOGGLE(1) | 3627 EHCI_QTD_IOC 3628 ); 3629 status->qtd.qtd_buffer[0] = 0; 3630 status->qtd.qtd_buffer_hi[0] = 0; 3631 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3632 status->nextqtd = NULL; 3633 status->xfer = xfer; 3634 status->len = 0; 3635 3636 return 0; 3637 bad3: 3638 ehci_free_sqtd(sc, exfer->ex_status); 3639 bad2: 3640 ehci_free_sqtd(sc, exfer->ex_setup); 3641 bad1: 3642 return err; 3643 } 3644 3645 Static void 3646 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3647 { 3648 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3649 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3650 3651 KASSERT(ex->ex_type == EX_CTRL); 3652 3653 ehci_free_sqtd(sc, ex->ex_setup); 3654 ehci_free_sqtd(sc, ex->ex_status); 3655 ehci_free_sqtds(sc, ex); 3656 if (ex->ex_nsqtd) 3657 kmem_free(ex->ex_sqtds, 3658 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3659 } 3660 3661 Static usbd_status 3662 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3663 { 3664 3665 /* Pipe isn't running, start first */ 3666 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3667 } 3668 3669 Static usbd_status 3670 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3671 { 3672 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3673 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3674 usb_device_request_t *req = &xfer->ux_request; 3675 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3676 ehci_soft_qtd_t *setup, *status, *next; 3677 ehci_soft_qh_t *sqh; 3678 3679 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3680 3681 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3682 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3683 3684 if (sc->sc_dying) 3685 return USBD_IOERROR; 3686 3687 const int isread = req->bmRequestType & UT_READ; 3688 const int len = UGETW(req->wLength); 3689 3690 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3691 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3692 UGETW(req->wIndex)); 3693 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3694 len, epipe->pipe.up_dev->ud_addr, 3695 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3696 3697 sqh = epipe->sqh; 3698 3699 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3700 "address QH %" __PRIuBIT " pipe %d\n", 3701 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3702 epipe->pipe.up_dev->ud_addr); 3703 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3704 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3705 "MPS QH %" __PRIuBIT " pipe %d\n", 3706 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3707 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3708 3709 setup = exfer->ex_setup; 3710 status = exfer->ex_status; 3711 3712 DPRINTF("setup %#jx status %#jx data %#jx", 3713 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3714 KASSERTMSG(setup != NULL && status != NULL, 3715 "Failed memory allocation, setup %p status %p", 3716 setup, status); 3717 3718 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3719 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3720 3721 /* Clear toggle */ 3722 setup->qtd.qtd_status &= ~htole32( 3723 EHCI_QTD_STATUS_MASK | 3724 EHCI_QTD_BYTES_MASK | 3725 EHCI_QTD_TOGGLE_MASK | 3726 EHCI_QTD_CERR_MASK 3727 ); 3728 setup->qtd.qtd_status |= htole32( 3729 EHCI_QTD_ACTIVE | 3730 EHCI_QTD_SET_CERR(3) | 3731 EHCI_QTD_SET_TOGGLE(0) | 3732 EHCI_QTD_SET_BYTES(sizeof(*req)) 3733 ); 3734 3735 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3736 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3737 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3738 3739 next = status; 3740 status->qtd.qtd_status &= ~htole32( 3741 EHCI_QTD_STATUS_MASK | 3742 EHCI_QTD_PID_MASK | 3743 EHCI_QTD_BYTES_MASK | 3744 EHCI_QTD_TOGGLE_MASK | 3745 EHCI_QTD_CERR_MASK 3746 ); 3747 status->qtd.qtd_status |= htole32( 3748 EHCI_QTD_ACTIVE | 3749 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3750 EHCI_QTD_SET_CERR(3) | 3751 EHCI_QTD_SET_TOGGLE(1) | 3752 EHCI_QTD_SET_BYTES(0) | 3753 EHCI_QTD_IOC 3754 ); 3755 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3756 3757 KASSERT(exfer->ex_isdone); 3758 #ifdef DIAGNOSTIC 3759 exfer->ex_isdone = false; 3760 #endif 3761 3762 /* Set up data transaction */ 3763 if (len != 0) { 3764 ehci_soft_qtd_t *end; 3765 3766 /* Start toggle at 1. */ 3767 int toggle = 1; 3768 next = exfer->ex_data; 3769 KASSERTMSG(next != NULL, "Failed memory allocation"); 3770 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3771 end->nextqtd = status; 3772 end->qtd.qtd_next = end->qtd.qtd_altnext = 3773 htole32(status->physaddr); 3774 3775 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3776 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3777 3778 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3779 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3780 } 3781 3782 setup->nextqtd = next; 3783 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3784 3785 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3786 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3787 3788 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3789 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3790 3791 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3792 3793 #ifdef EHCI_DEBUG 3794 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3795 ehci_dump_sqh(sqh); 3796 ehci_dump_sqtds(setup); 3797 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3798 #endif 3799 3800 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3801 ehci_set_qh_qtd(sqh, setup); 3802 usbd_xfer_schedule_timeout(xfer); 3803 ehci_add_intr_list(sc, exfer); 3804 xfer->ux_status = USBD_IN_PROGRESS; 3805 3806 #if 0 3807 #ifdef EHCI_DEBUG 3808 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3809 // delay(10000); 3810 ehci_dump_regs(sc); 3811 ehci_dump_sqh(sc->sc_async_head); 3812 ehci_dump_sqh(sqh); 3813 ehci_dump_sqtds(setup); 3814 #endif 3815 #endif 3816 3817 return USBD_IN_PROGRESS; 3818 } 3819 3820 Static void 3821 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3822 { 3823 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3824 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3825 usb_device_request_t *req = &xfer->ux_request; 3826 int len = UGETW(req->wLength); 3827 int rd = req->bmRequestType & UT_READ; 3828 3829 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3830 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3831 3832 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3833 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3834 3835 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3836 BUS_DMASYNC_POSTWRITE); 3837 if (len) 3838 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3839 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3840 3841 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3842 } 3843 3844 /* Abort a device control request. */ 3845 Static void 3846 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3847 { 3848 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3849 3850 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3851 usbd_xfer_abort(xfer); 3852 } 3853 3854 /* Close a device control pipe. */ 3855 Static void 3856 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3857 { 3858 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3859 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3860 3861 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3862 3863 KASSERT(mutex_owned(&sc->sc_lock)); 3864 3865 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3866 3867 ehci_close_pipe(pipe, sc->sc_async_head); 3868 3869 usb_freemem(&epipe->ctrl.reqdma); 3870 } 3871 3872 /* 3873 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3874 * qTD status, or miss signalling occasionally under heavy load. If the host 3875 * machine is too fast, we can miss transaction completion - when we scan 3876 * the active list the transaction still seems to be active. This generally 3877 * exhibits itself as a umass stall that never recovers. 3878 * 3879 * We work around this behaviour by setting up this callback after any softintr 3880 * that completes with transactions still pending, giving us another chance to 3881 * check for completion after the writeback has taken place. 3882 */ 3883 Static void 3884 ehci_intrlist_timeout(void *arg) 3885 { 3886 ehci_softc_t *sc = arg; 3887 3888 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3889 3890 usb_schedsoftintr(&sc->sc_bus); 3891 } 3892 3893 /************************/ 3894 3895 Static int 3896 ehci_device_bulk_init(struct usbd_xfer *xfer) 3897 { 3898 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3899 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3900 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3901 int endpt = ed->bEndpointAddress; 3902 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3903 int len = xfer->ux_bufsize; 3904 int err = 0; 3905 3906 exfer->ex_type = EX_BULK; 3907 exfer->ex_nsqtd = 0; 3908 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3909 &exfer->ex_sqtdstart); 3910 3911 return err; 3912 } 3913 3914 Static void 3915 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3916 { 3917 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3918 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3919 3920 KASSERT(ex->ex_type == EX_BULK); 3921 3922 ehci_free_sqtds(sc, ex); 3923 if (ex->ex_nsqtd) 3924 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3925 } 3926 3927 Static usbd_status 3928 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3929 { 3930 3931 /* Pipe isn't running, start first */ 3932 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3933 } 3934 3935 Static usbd_status 3936 ehci_device_bulk_start(struct usbd_xfer *xfer) 3937 { 3938 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3939 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3940 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3941 ehci_soft_qh_t *sqh; 3942 ehci_soft_qtd_t *end; 3943 int len, isread, endpt; 3944 3945 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3946 3947 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3948 xfer->ux_flags, 0); 3949 3950 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3951 3952 if (sc->sc_dying) 3953 return USBD_IOERROR; 3954 3955 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3956 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3957 3958 len = xfer->ux_length; 3959 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3960 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3961 sqh = epipe->sqh; 3962 3963 KASSERT(exfer->ex_isdone); 3964 #ifdef DIAGNOSTIC 3965 exfer->ex_isdone = false; 3966 #endif 3967 3968 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3969 3970 exfer->ex_sqtdend = end; 3971 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3972 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3973 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3974 3975 #ifdef EHCI_DEBUG 3976 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3977 ehci_dump_sqh(sqh); 3978 ehci_dump_sqtds(exfer->ex_sqtdstart); 3979 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3980 #endif 3981 3982 if (xfer->ux_length) 3983 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3984 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3985 3986 /* also does usb_syncmem(sqh) */ 3987 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3988 usbd_xfer_schedule_timeout(xfer); 3989 ehci_add_intr_list(sc, exfer); 3990 xfer->ux_status = USBD_IN_PROGRESS; 3991 3992 #if 0 3993 #ifdef EHCI_DEBUG 3994 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3995 // delay(10000); 3996 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3997 ehci_dump_regs(sc); 3998 #if 0 3999 printf("async_head:\n"); 4000 ehci_dump_sqh(sc->sc_async_head); 4001 #endif 4002 DPRINTF("sqh:", 0, 0, 0, 0); 4003 ehci_dump_sqh(sqh); 4004 ehci_dump_sqtds(exfer->ex_sqtdstart); 4005 #endif 4006 #endif 4007 4008 return USBD_IN_PROGRESS; 4009 } 4010 4011 Static void 4012 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4013 { 4014 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4015 4016 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 4017 usbd_xfer_abort(xfer); 4018 } 4019 4020 /* 4021 * Close a device bulk pipe. 4022 */ 4023 Static void 4024 ehci_device_bulk_close(struct usbd_pipe *pipe) 4025 { 4026 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4027 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4028 4029 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4030 4031 KASSERT(mutex_owned(&sc->sc_lock)); 4032 4033 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4034 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4035 ehci_close_pipe(pipe, sc->sc_async_head); 4036 } 4037 4038 Static void 4039 ehci_device_bulk_done(struct usbd_xfer *xfer) 4040 { 4041 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4042 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4043 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4044 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4045 4046 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4047 4048 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4049 4050 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4051 4052 if (xfer->ux_length) 4053 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4054 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4055 4056 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4057 } 4058 4059 /************************/ 4060 4061 Static usbd_status 4062 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4063 { 4064 struct ehci_soft_islot *isp; 4065 int islot, lev; 4066 4067 /* Find a poll rate that is large enough. */ 4068 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4069 if (EHCI_ILEV_IVAL(lev) <= ival) 4070 break; 4071 4072 /* Pick an interrupt slot at the right level. */ 4073 /* XXX could do better than picking at random */ 4074 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4075 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4076 4077 sqh->islot = islot; 4078 isp = &sc->sc_islots[islot]; 4079 mutex_enter(&sc->sc_lock); 4080 ehci_add_qh(sc, sqh, isp->sqh); 4081 mutex_exit(&sc->sc_lock); 4082 4083 return USBD_NORMAL_COMPLETION; 4084 } 4085 4086 Static int 4087 ehci_device_intr_init(struct usbd_xfer *xfer) 4088 { 4089 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4090 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4091 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4092 int endpt = ed->bEndpointAddress; 4093 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4094 int len = xfer->ux_bufsize; 4095 int err; 4096 4097 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4098 4099 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4100 xfer->ux_flags, 0); 4101 4102 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4103 KASSERT(len != 0); 4104 4105 exfer->ex_type = EX_INTR; 4106 exfer->ex_nsqtd = 0; 4107 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4108 &exfer->ex_sqtdstart); 4109 4110 return err; 4111 } 4112 4113 Static void 4114 ehci_device_intr_fini(struct usbd_xfer *xfer) 4115 { 4116 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4117 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4118 4119 KASSERT(ex->ex_type == EX_INTR); 4120 4121 ehci_free_sqtds(sc, ex); 4122 if (ex->ex_nsqtd) 4123 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4124 } 4125 4126 Static usbd_status 4127 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4128 { 4129 4130 /* Pipe isn't running, so start it first. */ 4131 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4132 } 4133 4134 Static usbd_status 4135 ehci_device_intr_start(struct usbd_xfer *xfer) 4136 { 4137 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4138 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4139 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4140 ehci_soft_qtd_t *end; 4141 ehci_soft_qh_t *sqh; 4142 int len, isread, endpt; 4143 4144 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4145 4146 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4147 xfer->ux_flags, 0); 4148 4149 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4150 4151 if (sc->sc_dying) 4152 return USBD_IOERROR; 4153 4154 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4155 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4156 4157 len = xfer->ux_length; 4158 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4159 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4160 sqh = epipe->sqh; 4161 4162 KASSERT(exfer->ex_isdone); 4163 #ifdef DIAGNOSTIC 4164 exfer->ex_isdone = false; 4165 #endif 4166 4167 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4168 4169 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4170 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4171 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4172 exfer->ex_sqtdend = end; 4173 4174 #ifdef EHCI_DEBUG 4175 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4176 ehci_dump_sqh(sqh); 4177 ehci_dump_sqtds(exfer->ex_sqtdstart); 4178 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4179 #endif 4180 4181 if (xfer->ux_length) 4182 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4183 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4184 4185 /* also does usb_syncmem(sqh) */ 4186 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4187 usbd_xfer_schedule_timeout(xfer); 4188 ehci_add_intr_list(sc, exfer); 4189 xfer->ux_status = USBD_IN_PROGRESS; 4190 4191 #if 0 4192 #ifdef EHCI_DEBUG 4193 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4194 // delay(10000); 4195 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4196 ehci_dump_regs(sc); 4197 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4198 ehci_dump_sqh(sqh); 4199 ehci_dump_sqtds(exfer->ex_sqtdstart); 4200 #endif 4201 #endif 4202 4203 return USBD_IN_PROGRESS; 4204 } 4205 4206 Static void 4207 ehci_device_intr_abort(struct usbd_xfer *xfer) 4208 { 4209 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4210 4211 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4212 4213 /* 4214 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4215 * async doorbell. That's dependent on the async list, wheras 4216 * intr xfers are periodic, should not use this? 4217 */ 4218 usbd_xfer_abort(xfer); 4219 } 4220 4221 Static void 4222 ehci_device_intr_close(struct usbd_pipe *pipe) 4223 { 4224 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4225 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4226 struct ehci_soft_islot *isp; 4227 4228 KASSERT(mutex_owned(&sc->sc_lock)); 4229 4230 isp = &sc->sc_islots[epipe->sqh->islot]; 4231 ehci_close_pipe(pipe, isp->sqh); 4232 } 4233 4234 Static void 4235 ehci_device_intr_done(struct usbd_xfer *xfer) 4236 { 4237 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4238 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4239 4240 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4241 4242 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4243 4244 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4245 4246 if (xfer->ux_length) { 4247 int isread, endpt; 4248 4249 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4250 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4251 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4252 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4253 } 4254 } 4255 4256 /************************/ 4257 Static int 4258 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4259 { 4260 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4261 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4262 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4263 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4264 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4265 int i, k, frames; 4266 u_int huba, dir; 4267 int err; 4268 4269 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4270 4271 start = NULL; 4272 sitd = NULL; 4273 4274 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4275 xfer->ux_flags, 0); 4276 4277 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4278 KASSERT(xfer->ux_nframes != 0); 4279 KASSERT(exfer->ex_isdone); 4280 4281 exfer->ex_type = EX_FS_ISOC; 4282 /* 4283 * Step 1: Allocate and initialize sitds. 4284 */ 4285 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4286 if (i > 16 || i == 0) { 4287 /* Spec page 271 says intervals > 16 are invalid */ 4288 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4289 return EINVAL; 4290 } 4291 4292 frames = xfer->ux_nframes; 4293 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4294 sitd = ehci_alloc_sitd(sc); 4295 if (sitd == NULL) { 4296 err = ENOMEM; 4297 goto fail; 4298 } 4299 4300 if (prev) 4301 prev->xfer_next = sitd; 4302 else 4303 start = sitd; 4304 4305 huba = dev->ud_myhsport->up_parent->ud_addr; 4306 4307 #if 0 4308 if (sc->sc_flags & EHCIF_FREESCALE) { 4309 // Set hub address to 0 if embedded TT is used. 4310 if (huba == sc->sc_addr) 4311 huba = 0; 4312 } 4313 #endif 4314 4315 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4316 dir = UE_GET_DIR(k) ? 1 : 0; 4317 sitd->sitd.sitd_endp = 4318 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4319 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4320 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4321 EHCI_SITD_SET_HUBA(huba) | 4322 EHCI_SITD_SET_DIR(dir)); 4323 4324 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4325 } /* End of frame */ 4326 4327 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4328 4329 stop = sitd; 4330 stop->xfer_next = NULL; 4331 exfer->ex_sitdstart = start; 4332 exfer->ex_sitdend = stop; 4333 4334 return 0; 4335 4336 fail: 4337 mutex_enter(&sc->sc_lock); 4338 ehci_soft_sitd_t *next; 4339 for (sitd = start; sitd; sitd = next) { 4340 next = sitd->xfer_next; 4341 ehci_free_sitd_locked(sc, sitd); 4342 } 4343 mutex_exit(&sc->sc_lock); 4344 4345 return err; 4346 } 4347 4348 Static void 4349 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4350 { 4351 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4352 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4353 4354 KASSERT(ex->ex_type == EX_FS_ISOC); 4355 4356 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4357 } 4358 4359 Static usbd_status 4360 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4361 { 4362 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4363 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4364 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4365 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4366 ehci_soft_sitd_t *sitd; 4367 usb_dma_t *dma_buf; 4368 int i, j, k, frames; 4369 int offs; 4370 int frindex; 4371 u_int dir; 4372 4373 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4374 4375 sitd = NULL; 4376 4377 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4378 xfer->ux_flags, 0); 4379 4380 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4381 4382 if (sc->sc_dying) 4383 return USBD_IOERROR; 4384 4385 /* 4386 * To avoid complication, don't allow a request right now that'll span 4387 * the entire frame table. To within 4 frames, to allow some leeway 4388 * on either side of where the hc currently is. 4389 */ 4390 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4391 xfer->ux_nframes >= sc->sc_flsize - 4) { 4392 printf("ehci: isoc descriptor requested that spans the entire" 4393 " frametable, too many frames\n"); 4394 return USBD_INVAL; 4395 } 4396 4397 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4398 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4399 KASSERT(exfer->ex_isdone); 4400 #ifdef DIAGNOSTIC 4401 exfer->ex_isdone = false; 4402 #endif 4403 4404 /* 4405 * Step 1: Initialize sitds. 4406 */ 4407 4408 frames = xfer->ux_nframes; 4409 dma_buf = &xfer->ux_dmabuf; 4410 offs = 0; 4411 4412 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4413 i++, sitd = sitd->xfer_next) { 4414 KASSERT(sitd != NULL); 4415 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4416 4417 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4418 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4419 4420 /* Set page0 index and offset - TP and T-offset are set below */ 4421 const bus_addr_t sba = DMAADDR(dma_buf, offs); 4422 sitd->sitd.sitd_buffer[0] = htole32(BUS_ADDR_LO32(sba)); 4423 sitd->sitd.sitd_buffer_hi[0] = htole32(BUS_ADDR_HI32(sba)); 4424 4425 offs += xfer->ux_frlengths[i]; 4426 4427 const bus_addr_t eba = DMAADDR(dma_buf, offs - 1); 4428 sitd->sitd.sitd_buffer[1] = 4429 htole32(EHCI_SITD_SET_BPTR(BUS_ADDR_LO32(eba))); 4430 sitd->sitd.sitd_buffer_hi[1] = htole32(BUS_ADDR_HI32(eba)); 4431 4432 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4433 4434 #if 0 4435 if (sc->sc_flags & EHCIF_FREESCALE) { 4436 // Set hub address to 0 if embedded TT is used. 4437 if (huba == sc->sc_addr) 4438 huba = 0; 4439 } 4440 #endif 4441 4442 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4443 dir = UE_GET_DIR(k) ? 1 : 0; 4444 KASSERT(sitd->sitd.sitd_endp == htole32( 4445 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4446 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4447 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4448 EHCI_SITD_SET_HUBA(huba) | 4449 EHCI_SITD_SET_DIR(dir))); 4450 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4451 4452 uint8_t sa = 0; 4453 uint8_t sb = 0; 4454 u_int temp, tlen; 4455 4456 if (dir == 0) { /* OUT */ 4457 temp = 0; 4458 tlen = xfer->ux_frlengths[i]; 4459 if (tlen <= 188) { 4460 temp |= 1; /* T-count = 1, TP = ALL */ 4461 tlen = 1; 4462 } else { 4463 tlen += 187; 4464 tlen /= 188; 4465 temp |= tlen; /* T-count = [1..6] */ 4466 temp |= 8; /* TP = Begin */ 4467 } 4468 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4469 4470 tlen += sa; 4471 4472 if (tlen >= 8) { 4473 sb = 0; 4474 } else { 4475 sb = (1 << tlen); 4476 } 4477 4478 sa = (1 << sa); 4479 sa = (sb - sa) & 0x3F; 4480 sb = 0; 4481 } else { 4482 sb = (-(4 << sa)) & 0xFE; 4483 sa = (1 << sa) & 0x3F; 4484 sa = 0x01; 4485 sb = 0xfc; 4486 } 4487 4488 sitd->sitd.sitd_sched = htole32( 4489 EHCI_SITD_SET_SMASK(sa) | 4490 EHCI_SITD_SET_CMASK(sb) 4491 ); 4492 4493 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4494 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4495 } /* End of frame */ 4496 4497 sitd = exfer->ex_sitdend; 4498 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4499 4500 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4501 sizeof(sitd->sitd.sitd_trans), 4502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4503 4504 if (xfer->ux_length) 4505 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4506 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4507 4508 /* 4509 * Part 2: Transfer descriptors have now been set up, now they must 4510 * be scheduled into the periodic frame list. Erk. Not wanting to 4511 * complicate matters, transfer is denied if the transfer spans 4512 * more than the periodic frame list. 4513 */ 4514 4515 /* Start inserting frames */ 4516 if (epipe->isoc.cur_xfers > 0) { 4517 frindex = epipe->isoc.next_frame; 4518 } else { 4519 frindex = EOREAD4(sc, EHCI_FRINDEX); 4520 frindex = frindex >> 3; /* Erase microframe index */ 4521 frindex += 2; 4522 } 4523 4524 if (frindex >= sc->sc_flsize) 4525 frindex &= (sc->sc_flsize - 1); 4526 4527 /* What's the frame interval? */ 4528 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4529 4530 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4531 j++, sitd = sitd->xfer_next) { 4532 KASSERT(sitd); 4533 4534 usb_syncmem(&sc->sc_fldma, 4535 sizeof(ehci_link_t) * frindex, 4536 sizeof(ehci_link_t), 4537 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4538 4539 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4540 if (sitd->sitd.sitd_next == 0) 4541 /* 4542 * FIXME: frindex table gets initialized to NULL 4543 * or EHCI_NULL? 4544 */ 4545 sitd->sitd.sitd_next = EHCI_NULL; 4546 4547 usb_syncmem(&sitd->dma, 4548 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4549 sizeof(ehci_sitd_t), 4550 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4551 4552 sc->sc_flist[frindex] = 4553 htole32(EHCI_LINK_SITD | sitd->physaddr); 4554 4555 usb_syncmem(&sc->sc_fldma, 4556 sizeof(ehci_link_t) * frindex, 4557 sizeof(ehci_link_t), 4558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4559 4560 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4561 sc->sc_softsitds[frindex] = sitd; 4562 if (sitd->frame_list.next != NULL) 4563 sitd->frame_list.next->frame_list.prev = sitd; 4564 sitd->slot = frindex; 4565 sitd->frame_list.prev = NULL; 4566 4567 frindex += i; 4568 if (frindex >= sc->sc_flsize) 4569 frindex -= sc->sc_flsize; 4570 } 4571 4572 epipe->isoc.cur_xfers++; 4573 epipe->isoc.next_frame = frindex; 4574 4575 ehci_add_intr_list(sc, exfer); 4576 xfer->ux_status = USBD_IN_PROGRESS; 4577 4578 return USBD_IN_PROGRESS; 4579 } 4580 4581 Static void 4582 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4583 { 4584 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4585 4586 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4587 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4588 } 4589 4590 Static void 4591 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4592 { 4593 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4594 4595 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4596 } 4597 4598 Static void 4599 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4600 { 4601 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4602 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4603 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4604 4605 KASSERT(mutex_owned(&sc->sc_lock)); 4606 4607 epipe->isoc.cur_xfers--; 4608 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4609 4610 if (xfer->ux_length) 4611 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4612 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4613 } 4614 4615 /* -------------------------------------------------------------------------- */ 4616 4617 Static int 4618 ehci_device_isoc_init(struct usbd_xfer *xfer) 4619 { 4620 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4621 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4622 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4623 ehci_soft_itd_t *itd, *prev, *start, *stop; 4624 int i, j, k; 4625 int frames, ufrperframe; 4626 int err; 4627 4628 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4629 4630 start = NULL; 4631 prev = NULL; 4632 itd = NULL; 4633 4634 KASSERT(xfer->ux_nframes != 0); 4635 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4636 KASSERT(exfer->ex_isdone); 4637 4638 exfer->ex_type = EX_ISOC; 4639 4640 /* 4641 * Step 1: Allocate and initialize itds, how many do we need? 4642 * One per transfer if interval >= 8 microframes, less if we use 4643 * multiple microframes per frame. 4644 */ 4645 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4646 if (i > 16 || i == 0) { 4647 /* Spec page 271 says intervals > 16 are invalid */ 4648 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4649 return EINVAL; 4650 } 4651 4652 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4653 frames = howmany(xfer->ux_nframes, ufrperframe); 4654 4655 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4656 itd = ehci_alloc_itd(sc); 4657 if (itd == NULL) { 4658 err = ENOMEM; 4659 goto fail; 4660 } 4661 4662 if (prev != NULL) { 4663 /* Maybe not as it's updated by the scheduling? */ 4664 prev->itd.itd_next = 4665 htole32(itd->physaddr | EHCI_LINK_ITD); 4666 4667 prev->xfer_next = itd; 4668 } else { 4669 start = itd; 4670 } 4671 4672 /* 4673 * Other special values 4674 */ 4675 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4676 itd->itd.itd_bufr[0] = htole32( 4677 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4678 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4679 4680 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4681 ? 1 : 0; 4682 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4683 itd->itd.itd_bufr[1] |= htole32( 4684 EHCI_ITD_SET_DIR(k) | 4685 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4686 4687 /* FIXME: handle invalid trans - should be done in openpipe */ 4688 itd->itd.itd_bufr[2] |= 4689 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4690 } /* End of frame */ 4691 4692 stop = itd; 4693 stop->xfer_next = NULL; 4694 4695 exfer->ex_itdstart = start; 4696 exfer->ex_itdend = stop; 4697 4698 return 0; 4699 fail: 4700 mutex_enter(&sc->sc_lock); 4701 ehci_soft_itd_t *next; 4702 for (itd = start; itd; itd = next) { 4703 next = itd->xfer_next; 4704 ehci_free_itd_locked(sc, itd); 4705 } 4706 mutex_exit(&sc->sc_lock); 4707 4708 return err; 4709 4710 } 4711 4712 Static void 4713 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4714 { 4715 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4716 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4717 4718 KASSERT(ex->ex_type == EX_ISOC); 4719 4720 ehci_free_itd_chain(sc, ex->ex_itdstart); 4721 } 4722 4723 Static usbd_status 4724 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4725 { 4726 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4727 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4728 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4729 ehci_soft_itd_t *itd, *prev; 4730 usb_dma_t *dma_buf; 4731 int i, j; 4732 int frames, uframes, ufrperframe; 4733 int trans_count, offs; 4734 int frindex; 4735 4736 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4737 4738 prev = NULL; 4739 itd = NULL; 4740 trans_count = 0; 4741 4742 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4743 4744 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4745 4746 if (sc->sc_dying) 4747 return USBD_IOERROR; 4748 4749 /* 4750 * To avoid complication, don't allow a request right now that'll span 4751 * the entire frame table. To within 4 frames, to allow some leeway 4752 * on either side of where the hc currently is. 4753 */ 4754 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4755 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4756 DPRINTF( 4757 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4758 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4759 return USBD_INVAL; 4760 } 4761 4762 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4763 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4764 KASSERT(exfer->ex_isdone); 4765 #ifdef DIAGNOSTIC 4766 exfer->ex_isdone = false; 4767 #endif 4768 4769 /* 4770 * Step 1: Re-Initialize itds 4771 */ 4772 4773 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4774 if (i > 16 || i == 0) { 4775 /* Spec page 271 says intervals > 16 are invalid */ 4776 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4777 return USBD_INVAL; 4778 } 4779 4780 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4781 frames = howmany(xfer->ux_nframes, ufrperframe); 4782 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4783 4784 if (frames == 0) { 4785 DPRINTF("frames == 0", 0, 0, 0, 0); 4786 return USBD_INVAL; 4787 } 4788 4789 dma_buf = &xfer->ux_dmabuf; 4790 offs = 0; 4791 4792 itd = exfer->ex_itdstart; 4793 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4794 int froffs = offs; 4795 4796 if (prev != NULL) { 4797 prev->itd.itd_next = 4798 htole32(itd->physaddr | EHCI_LINK_ITD); 4799 usb_syncmem(&prev->dma, 4800 prev->offs + offsetof(ehci_itd_t, itd_next), 4801 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4802 prev->xfer_next = itd; 4803 } 4804 4805 /* 4806 * Step 1.5, initialize uframes 4807 */ 4808 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4809 /* Calculate which page in the list this starts in */ 4810 int addr = DMAADDR(dma_buf, froffs); 4811 addr = EHCI_PAGE_OFFSET(addr); 4812 addr += (offs - froffs); 4813 addr = EHCI_PAGE(addr); 4814 addr /= EHCI_PAGE_SIZE; 4815 4816 /* 4817 * This gets the initial offset into the first page, 4818 * looks how far further along the current uframe 4819 * offset is. Works out how many pages that is. 4820 */ 4821 4822 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4823 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4824 EHCI_ITD_SET_PG(addr) | 4825 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4826 4827 offs += xfer->ux_frlengths[trans_count]; 4828 trans_count++; 4829 4830 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4831 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4832 break; 4833 } 4834 } 4835 4836 /* 4837 * Step 1.75, set buffer pointers. To simplify matters, all 4838 * pointers are filled out for the next 7 hardware pages in 4839 * the dma block, so no need to worry what pages to cover 4840 * and what to not. 4841 */ 4842 4843 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4844 /* 4845 * Don't try to lookup a page that's past the end 4846 * of buffer 4847 */ 4848 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4849 if (page_offs >= dma_buf->udma_block->size) 4850 break; 4851 4852 uint64_t page = DMAADDR(dma_buf, page_offs); 4853 page = EHCI_PAGE(page); 4854 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4855 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4856 } 4857 /* 4858 * Other special values 4859 */ 4860 4861 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4862 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4863 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4864 4865 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4866 ? 1 : 0; 4867 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4868 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4869 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4870 4871 /* FIXME: handle invalid trans */ 4872 itd->itd.itd_bufr[2] |= 4873 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4874 4875 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4876 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4877 4878 prev = itd; 4879 } /* End of frame */ 4880 4881 if (xfer->ux_length) 4882 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4883 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4884 4885 /* 4886 * Part 2: Transfer descriptors have now been set up, now they must 4887 * be scheduled into the periodic frame list. Erk. Not wanting to 4888 * complicate matters, transfer is denied if the transfer spans 4889 * more than the periodic frame list. 4890 */ 4891 4892 /* Start inserting frames */ 4893 if (epipe->isoc.cur_xfers > 0) { 4894 frindex = epipe->isoc.next_frame; 4895 } else { 4896 frindex = EOREAD4(sc, EHCI_FRINDEX); 4897 frindex = frindex >> 3; /* Erase microframe index */ 4898 frindex += 2; 4899 } 4900 4901 if (frindex >= sc->sc_flsize) 4902 frindex &= (sc->sc_flsize - 1); 4903 4904 /* What's the frame interval? */ 4905 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4906 if (i / USB_UFRAMES_PER_FRAME == 0) 4907 i = 1; 4908 else 4909 i /= USB_UFRAMES_PER_FRAME; 4910 4911 itd = exfer->ex_itdstart; 4912 for (j = 0; j < frames; j++) { 4913 KASSERTMSG(itd != NULL, "frame %d\n", j); 4914 4915 usb_syncmem(&sc->sc_fldma, 4916 sizeof(ehci_link_t) * frindex, 4917 sizeof(ehci_link_t), 4918 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4919 4920 itd->itd.itd_next = sc->sc_flist[frindex]; 4921 if (itd->itd.itd_next == 0) 4922 /* 4923 * FIXME: frindex table gets initialized to NULL 4924 * or EHCI_NULL? 4925 */ 4926 itd->itd.itd_next = EHCI_NULL; 4927 4928 usb_syncmem(&itd->dma, 4929 itd->offs + offsetof(ehci_itd_t, itd_next), 4930 sizeof(itd->itd.itd_next), 4931 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4932 4933 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4934 4935 usb_syncmem(&sc->sc_fldma, 4936 sizeof(ehci_link_t) * frindex, 4937 sizeof(ehci_link_t), 4938 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4939 4940 itd->frame_list.next = sc->sc_softitds[frindex]; 4941 sc->sc_softitds[frindex] = itd; 4942 if (itd->frame_list.next != NULL) 4943 itd->frame_list.next->frame_list.prev = itd; 4944 itd->slot = frindex; 4945 itd->frame_list.prev = NULL; 4946 4947 frindex += i; 4948 if (frindex >= sc->sc_flsize) 4949 frindex -= sc->sc_flsize; 4950 4951 itd = itd->xfer_next; 4952 } 4953 4954 epipe->isoc.cur_xfers++; 4955 epipe->isoc.next_frame = frindex; 4956 4957 ehci_add_intr_list(sc, exfer); 4958 xfer->ux_status = USBD_IN_PROGRESS; 4959 4960 return USBD_IN_PROGRESS; 4961 } 4962 4963 Static void 4964 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4965 { 4966 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4967 4968 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4969 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4970 } 4971 4972 Static void 4973 ehci_device_isoc_close(struct usbd_pipe *pipe) 4974 { 4975 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4976 4977 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4978 } 4979 4980 Static void 4981 ehci_device_isoc_done(struct usbd_xfer *xfer) 4982 { 4983 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4984 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4985 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4986 4987 KASSERT(mutex_owned(&sc->sc_lock)); 4988 4989 epipe->isoc.cur_xfers--; 4990 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4991 if (xfer->ux_length) 4992 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4993 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4994 } 4995
Indexes created Tue Sep 23 14:10:03 GMT 2025