ehci.c revision 1.326
1 /* $NetBSD: ehci.c,v 1.326 2024/09/23 10:07:26 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna23.net), and 11 * Nick Hudson . 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 37 * 38 * The EHCI 1.0 spec can be found at 39 * http://www.intel.com/technology/usb/spec.htm 40 * and the USB 2.0 spec at 41 * http://www.usb.org/developers/docs/ 42 * 43 */ 44 45 /* 46 * TODO: 47 * 1) hold off explorations by companion controllers until ehci has started. 48 * 49 * 2) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 3) Command failures are not recovered correctly. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.326 2024/09/23 10:07:26 skrll Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #ifdef _KERNEL_OPT 63 #include "opt_usb.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #include <sys/bus.h> 69 #include <sys/cpu.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/kmem.h> 73 #include <sys/mutex.h> 74 #include <sys/proc.h> 75 #include <sys/queue.h> 76 #include <sys/select.h> 77 #include <sys/sysctl.h> 78 #include <sys/systm.h> 79 #include <sys/reboot.h> 80 81 #include <machine/endian.h> 82 83 #include <dev/usb/usb.h> 84 #include <dev/usb/usbdi.h> 85 #include <dev/usb/usbdivar.h> 86 #include <dev/usb/usbhist.h> 87 #include <dev/usb/usb_mem.h> 88 #include <dev/usb/usb_quirks.h> 89 90 #include <dev/usb/ehcireg.h> 91 #include <dev/usb/ehcivar.h> 92 #include <dev/usb/usbroothub.h> 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 99 #ifndef EHCI_DEBUG_DEFAULT 100 #define EHCI_DEBUG_DEFAULT 0 101 #endif 102 103 static int ehcidebug = EHCI_DEBUG_DEFAULT; 104 105 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 106 { 107 int err; 108 const struct sysctlnode *rnode; 109 const struct sysctlnode *cnode; 110 111 err = sysctl_createv(clog, 0, NULL, &rnode, 112 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 113 SYSCTL_DESCR("ehci global controls"), 114 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 115 116 if (err) 117 goto fail; 118 119 /* control debugging printfs */ 120 err = sysctl_createv(clog, 0, &rnode, &cnode, 121 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 122 "debug", SYSCTL_DESCR("Enable debugging output"), 123 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 124 if (err) 125 goto fail; 126 127 return; 128 fail: 129 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 130 } 131 132 #endif /* EHCI_DEBUG */ 133 #endif /* USB_DEBUG */ 134 135 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 136 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 137 #define EHCIHIST_FUNC() USBHIST_FUNC() 138 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 139 140 struct ehci_pipe { 141 struct usbd_pipe pipe; 142 int nexttoggle; 143 144 ehci_soft_qh_t *sqh; 145 union { 146 /* Control pipe */ 147 struct { 148 usb_dma_t reqdma; 149 } ctrl; 150 /* Interrupt pipe */ 151 struct { 152 u_int length; 153 } intr; 154 /* Iso pipe */ 155 struct { 156 u_int next_frame; 157 u_int cur_xfers; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 163 164 Static usbd_status ehci_open(struct usbd_pipe *); 165 Static void ehci_poll(struct usbd_bus *); 166 Static void ehci_softintr(void *); 167 Static int ehci_intr1(ehci_softc_t *); 168 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 169 ex_completeq_t *); 170 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 171 ex_completeq_t *); 172 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 173 ex_completeq_t *); 174 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 175 Static void ehci_intrlist_timeout(void *); 176 Static void ehci_doorbell(void *); 177 Static void ehci_pcd(void *); 178 179 Static struct usbd_xfer * 180 ehci_allocx(struct usbd_bus *, unsigned int); 181 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 182 183 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 184 Static bool ehci_dying(struct usbd_bus *); 185 Static int ehci_roothub_ctrl(struct usbd_bus *, 186 usb_device_request_t *, void *, int); 187 188 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 189 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 190 Static void ehci_root_intr_abort(struct usbd_xfer *); 191 Static void ehci_root_intr_close(struct usbd_pipe *); 192 Static void ehci_root_intr_done(struct usbd_xfer *); 193 194 Static int ehci_device_ctrl_init(struct usbd_xfer *); 195 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 196 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 197 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 198 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 199 Static void ehci_device_ctrl_close(struct usbd_pipe *); 200 Static void ehci_device_ctrl_done(struct usbd_xfer *); 201 202 Static int ehci_device_bulk_init(struct usbd_xfer *); 203 Static void ehci_device_bulk_fini(struct usbd_xfer *); 204 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 205 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 206 Static void ehci_device_bulk_abort(struct usbd_xfer *); 207 Static void ehci_device_bulk_close(struct usbd_pipe *); 208 Static void ehci_device_bulk_done(struct usbd_xfer *); 209 210 Static int ehci_device_intr_init(struct usbd_xfer *); 211 Static void ehci_device_intr_fini(struct usbd_xfer *); 212 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 213 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 214 Static void ehci_device_intr_abort(struct usbd_xfer *); 215 Static void ehci_device_intr_close(struct usbd_pipe *); 216 Static void ehci_device_intr_done(struct usbd_xfer *); 217 218 Static int ehci_device_isoc_init(struct usbd_xfer *); 219 Static void ehci_device_isoc_fini(struct usbd_xfer *); 220 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 221 Static void ehci_device_isoc_abort(struct usbd_xfer *); 222 Static void ehci_device_isoc_close(struct usbd_pipe *); 223 Static void ehci_device_isoc_done(struct usbd_xfer *); 224 225 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 226 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 227 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 228 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 229 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 230 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 231 232 Static void ehci_device_clear_toggle(struct usbd_pipe *); 233 Static void ehci_noop(struct usbd_pipe *); 234 235 Static void ehci_disown(ehci_softc_t *, int, int); 236 237 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 238 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 239 240 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 241 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 242 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 243 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 244 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 245 246 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 247 int, int, int *, ehci_soft_qtd_t **); 248 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 249 250 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 251 Static ehci_soft_sitd_t * 252 ehci_alloc_sitd(ehci_softc_t *); 253 254 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 255 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 256 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 257 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 258 259 static inline void 260 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 261 { 262 263 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 264 } 265 266 static inline void 267 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 268 { 269 270 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 271 } 272 273 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 274 275 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 276 int); 277 278 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 279 ehci_soft_qh_t *); 280 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 281 ehci_soft_qh_t *); 282 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 283 Static void ehci_sync_hc(ehci_softc_t *); 284 285 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 286 Static void ehci_abortx(struct usbd_xfer *); 287 288 #ifdef EHCI_DEBUG 289 Static ehci_softc_t *theehci; 290 void ehci_dump(void); 291 #endif 292 293 #ifdef EHCI_DEBUG 294 Static void ehci_dump_regs(ehci_softc_t *); 295 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 296 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 297 Static void ehci_dump_qh_qtd(struct ehci_qh_qtd_t *); 298 Static void ehci_dump_qtd(ehci_qtd_t *); 299 Static void ehci_dump_sqh(ehci_soft_qh_t *); 300 Static void ehci_dump_sitd(struct ehci_soft_itd *); 301 Static void ehci_dump_itds(ehci_soft_itd_t *); 302 Static void ehci_dump_itd(struct ehci_soft_itd *); 303 Static void ehci_dump_exfer(struct ehci_xfer *); 304 #endif 305 306 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 307 308 static inline void 309 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 310 { 311 312 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 313 } 314 315 static inline void 316 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 317 { 318 319 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 320 } 321 322 Static const struct usbd_bus_methods ehci_bus_methods = { 323 .ubm_open = ehci_open, 324 .ubm_softint = ehci_softintr, 325 .ubm_dopoll = ehci_poll, 326 .ubm_allocx = ehci_allocx, 327 .ubm_freex = ehci_freex, 328 .ubm_abortx = ehci_abortx, 329 .ubm_dying = ehci_dying, 330 .ubm_getlock = ehci_get_lock, 331 .ubm_rhctrl = ehci_roothub_ctrl, 332 }; 333 334 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 335 .upm_transfer = ehci_root_intr_transfer, 336 .upm_start = ehci_root_intr_start, 337 .upm_abort = ehci_root_intr_abort, 338 .upm_close = ehci_root_intr_close, 339 .upm_cleartoggle = ehci_noop, 340 .upm_done = ehci_root_intr_done, 341 }; 342 343 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 344 .upm_init = ehci_device_ctrl_init, 345 .upm_fini = ehci_device_ctrl_fini, 346 .upm_transfer = ehci_device_ctrl_transfer, 347 .upm_start = ehci_device_ctrl_start, 348 .upm_abort = ehci_device_ctrl_abort, 349 .upm_close = ehci_device_ctrl_close, 350 .upm_cleartoggle = ehci_noop, 351 .upm_done = ehci_device_ctrl_done, 352 }; 353 354 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 355 .upm_init = ehci_device_intr_init, 356 .upm_fini = ehci_device_intr_fini, 357 .upm_transfer = ehci_device_intr_transfer, 358 .upm_start = ehci_device_intr_start, 359 .upm_abort = ehci_device_intr_abort, 360 .upm_close = ehci_device_intr_close, 361 .upm_cleartoggle = ehci_device_clear_toggle, 362 .upm_done = ehci_device_intr_done, 363 }; 364 365 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 366 .upm_init = ehci_device_bulk_init, 367 .upm_fini = ehci_device_bulk_fini, 368 .upm_transfer = ehci_device_bulk_transfer, 369 .upm_start = ehci_device_bulk_start, 370 .upm_abort = ehci_device_bulk_abort, 371 .upm_close = ehci_device_bulk_close, 372 .upm_cleartoggle = ehci_device_clear_toggle, 373 .upm_done = ehci_device_bulk_done, 374 }; 375 376 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 377 .upm_init = ehci_device_isoc_init, 378 .upm_fini = ehci_device_isoc_fini, 379 .upm_transfer = ehci_device_isoc_transfer, 380 .upm_abort = ehci_device_isoc_abort, 381 .upm_close = ehci_device_isoc_close, 382 .upm_cleartoggle = ehci_noop, 383 .upm_done = ehci_device_isoc_done, 384 }; 385 386 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 387 .upm_init = ehci_device_fs_isoc_init, 388 .upm_fini = ehci_device_fs_isoc_fini, 389 .upm_transfer = ehci_device_fs_isoc_transfer, 390 .upm_abort = ehci_device_fs_isoc_abort, 391 .upm_close = ehci_device_fs_isoc_close, 392 .upm_cleartoggle = ehci_noop, 393 .upm_done = ehci_device_fs_isoc_done, 394 }; 395 396 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 397 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 398 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 399 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 400 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 401 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 402 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 403 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 404 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 405 }; 406 407 int 408 ehci_init(ehci_softc_t *sc) 409 { 410 uint32_t vers, hcr; 411 u_int i; 412 int err; 413 ehci_soft_qh_t *sqh; 414 u_int ncomp; 415 416 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 417 #ifdef EHCI_DEBUG 418 theehci = sc; 419 #endif 420 421 mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE); 422 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 423 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 424 cv_init(&sc->sc_doorbell, "ehcidb"); 425 426 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 427 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 428 429 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 430 ehci_doorbell, sc); 431 KASSERT(sc->sc_doorbell_si != NULL); 432 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 433 ehci_pcd, sc); 434 KASSERT(sc->sc_pcd_si != NULL); 435 436 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 437 438 vers = EREAD2(sc, EHCI_HCIVERSION); 439 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 440 vers >> 8, vers & 0xff); 441 442 const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS); 443 DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0); 444 sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams); 445 ncomp = EHCI_HCS_N_CC(hcsparams); 446 if (ncomp != sc->sc_ncomp) { 447 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 448 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 449 #if NOHCI == 0 || NUHCI == 0 450 aprint_error("%s: ohci or uhci probably not configured\n", 451 device_xname(sc->sc_dev)); 452 #endif 453 if (ncomp < sc->sc_ncomp) 454 sc->sc_ncomp = ncomp; 455 } 456 if (sc->sc_ncomp > 0) { 457 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 458 aprint_normal_dev(sc->sc_dev, 459 "%d companion controller%s, %d port%s%s", 460 sc->sc_ncomp, 461 sc->sc_ncomp!=1 ? "s" : "", 462 EHCI_HCS_N_PCC(hcsparams), 463 EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "", 464 sc->sc_ncomp!=1 ? " each" : ""); 465 if (sc->sc_comps[0]) { 466 aprint_normal(":"); 467 for (i = 0; i < sc->sc_ncomp; i++) 468 aprint_normal(" %s", 469 device_xname(sc->sc_comps[i])); 470 } 471 aprint_normal("\n"); 472 473 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 474 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 475 cv_init(&sc->sc_compcv, "ehciccv"); 476 sc->sc_comp_state = CO_EARLY; 477 } 478 sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams); 479 sc->sc_hasppc = EHCI_HCS_PPC(hcsparams); 480 481 const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS); 482 DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0); 483 484 if (EHCI_HCC_64BIT(hccparams)) { 485 /* MUST clear segment register if 64 bit capable. */ 486 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 487 } 488 489 if (hccparams & EHCI_HCC_IST_FULLFRAME) { 490 sc->sc_istthreshold = 0; 491 } else { 492 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams); 493 } 494 495 sc->sc_bus.ub_revision = USBREV_2_0; 496 sc->sc_bus.ub_usedma = true; 497 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 498 499 /* 500 * The bus attachment code will possibly provide a 64bit DMA 501 * tag which we now limit to the bottom 4G range as 502 * 503 * - that's as much as ehci can address in its QH, TD, iTD, and siTD 504 * structures; and 505 * - the driver doesn't currently set EHCI_CTRLDSSEGMENT to anything 506 * other than 0. 507 */ 508 bus_dma_tag_t ntag = sc->sc_bus.ub_dmatag; 509 sc->sc_dmatag = sc->sc_bus.ub_dmatag; 510 err = bus_dmatag_subregion(sc->sc_bus.ub_dmatag, 0, UINT32_MAX, 511 &ntag, 0); 512 if (err == 0) { 513 sc->sc_dmatag = ntag; 514 aprint_normal_dev(sc->sc_dev, "Using DMA subregion for control" 515 " data structures\n"); 516 } 517 518 /* Reset the controller */ 519 DPRINTF("resetting", 0, 0, 0, 0); 520 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 521 usb_delay_ms(&sc->sc_bus, 1); 522 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 523 for (i = 0; i < 100; i++) { 524 usb_delay_ms(&sc->sc_bus, 1); 525 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 526 if (!hcr) 527 break; 528 } 529 if (hcr) { 530 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 531 err = EIO; 532 goto fail1; 533 } 534 if (sc->sc_vendor_init) 535 sc->sc_vendor_init(sc); 536 537 /* XXX need proper intr scheduling */ 538 sc->sc_rand = 96; 539 540 /* frame list size at default, read back what we got and use that */ 541 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 542 case 0: sc->sc_flsize = 1024; break; 543 case 1: sc->sc_flsize = 512; break; 544 case 2: sc->sc_flsize = 256; break; 545 case 3: 546 err = EIO; 547 goto fail1; 548 } 549 err = usb_allocmem(sc->sc_dmatag, 550 sc->sc_flsize * sizeof(ehci_link_t), 551 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 552 if (err) { 553 aprint_error_dev(sc->sc_dev, "failed to allocate frame list\n"); 554 goto fail1; 555 } 556 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 557 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 558 559 for (i = 0; i < sc->sc_flsize; i++) { 560 sc->sc_flist[i] = EHCI_NULL; 561 } 562 563 const bus_addr_t flba = DMAADDR(&sc->sc_fldma, 0); 564 const uint32_t hi32 = BUS_ADDR_HI32(flba); 565 if (hi32 != 0) { 566 aprint_error_dev(sc->sc_dev, "DMA memory segment error (%08x)\n", 567 hi32); 568 goto fail2; 569 } 570 571 const uint32_t lo32 = BUS_ADDR_LO32(flba); 572 EOWRITE4(sc, EHCI_PERIODICLISTBASE, lo32); 573 574 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 575 KM_SLEEP); 576 LIST_INIT(&sc->sc_freeitds); 577 LIST_INIT(&sc->sc_freesitds); 578 TAILQ_INIT(&sc->sc_intrhead); 579 580 /* Set up the bus struct. */ 581 sc->sc_bus.ub_methods = &ehci_bus_methods; 582 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 583 584 sc->sc_eintrs = EHCI_NORMAL_INTRS; 585 586 /* 587 * Allocate the interrupt dummy QHs. These are arranged to give poll 588 * intervals that are powers of 2 times 1ms. 589 */ 590 memset(sc->sc_islots, 0, sizeof(sc->sc_islots)); 591 for (i = 0; i < EHCI_INTRQHS; i++) { 592 sqh = ehci_alloc_sqh(sc); 593 if (sqh == NULL) { 594 err = ENOMEM; 595 goto fail3; 596 } 597 sc->sc_islots[i].sqh = sqh; 598 } 599 for (i = 0; i < EHCI_INTRQHS; i++) { 600 sqh = sc->sc_islots[i].sqh; 601 if (i == 0) { 602 /* The last (1ms) QH terminates. */ 603 sqh->qh->qh_link = EHCI_NULL; 604 sqh->next = NULL; 605 } else { 606 /* Otherwise the next QH has half the poll interval */ 607 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 608 sqh->qh->qh_link = htole32(sqh->next->physaddr | 609 EHCI_LINK_QH); 610 } 611 sqh->qh->qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 612 sqh->qh->qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 613 sqh->qh->qh_curqtd = EHCI_NULL; 614 615 sqh->qh->qh_qtd.qtd_next = EHCI_NULL; 616 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 617 sqh->qh->qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 618 sqh->sqtd = NULL; 619 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 620 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 621 } 622 /* Point the frame list at the last level (128ms). */ 623 for (i = 0; i < sc->sc_flsize; i++) { 624 int j; 625 626 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 627 revbits[i & (EHCI_MAX_POLLRATE-1)]; 628 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 629 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 630 i)].sqh->physaddr); 631 } 632 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 633 BUS_DMASYNC_PREWRITE); 634 635 /* Allocate dummy QH that starts the async list. */ 636 sqh = ehci_alloc_sqh(sc); 637 if (sqh == NULL) { 638 err = ENOMEM; 639 goto fail3; 640 } 641 /* Fill the QH */ 642 sqh->qh->qh_endp = 643 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 644 sqh->qh->qh_link = 645 htole32(sqh->physaddr | EHCI_LINK_QH); 646 sqh->qh->qh_curqtd = EHCI_NULL; 647 sqh->next = NULL; 648 /* Fill the overlay qTD */ 649 sqh->qh->qh_qtd.qtd_next = EHCI_NULL; 650 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 651 sqh->qh->qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 652 sqh->sqtd = NULL; 653 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 654 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 655 #ifdef EHCI_DEBUG 656 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 657 ehci_dump_sqh(sqh); 658 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 659 #endif 660 661 /* Point to async list */ 662 sc->sc_async_head = sqh; 663 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 664 665 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 666 667 /* Turn on controller */ 668 EOWRITE4(sc, EHCI_USBCMD, 669 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 670 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 671 EHCI_CMD_ASE | 672 EHCI_CMD_PSE | 673 EHCI_CMD_RS); 674 675 /* Take over port ownership */ 676 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 677 678 for (i = 0; i < 100; i++) { 679 usb_delay_ms(&sc->sc_bus, 1); 680 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 681 if (!hcr) 682 break; 683 } 684 if (hcr) { 685 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 686 err = EIO; 687 goto fail4; 688 } 689 690 /* Enable interrupts */ 691 DPRINTF("enabling interrupts", 0, 0, 0, 0); 692 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 693 694 return 0; 695 696 fail4: 697 ehci_free_sqh(sc, sc->sc_async_head); 698 699 fail3: 700 for (i = 0; i < EHCI_INTRQHS; i++) { 701 sqh = sc->sc_islots[i].sqh; 702 if (sqh) 703 ehci_free_sqh(sc, sqh); 704 } 705 706 kmem_free(sc->sc_softitds, sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 707 708 fail2: 709 usb_freemem(&sc->sc_fldma); 710 711 fail1: 712 softint_disestablish(sc->sc_doorbell_si); 713 softint_disestablish(sc->sc_pcd_si); 714 mutex_destroy(&sc->sc_rhlock); 715 mutex_destroy(&sc->sc_lock); 716 mutex_destroy(&sc->sc_intr_lock); 717 718 return err; 719 } 720 721 int 722 ehci_intr(void *v) 723 { 724 ehci_softc_t *sc = v; 725 int ret = 0; 726 727 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 728 729 if (sc == NULL) 730 return 0; 731 732 mutex_spin_enter(&sc->sc_intr_lock); 733 734 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 735 goto done; 736 737 /* If we get an interrupt while polling, then just ignore it. */ 738 if (sc->sc_bus.ub_usepolling) { 739 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 740 741 if (intrs) 742 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 743 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 744 goto done; 745 } 746 747 ret = ehci_intr1(sc); 748 749 done: 750 mutex_spin_exit(&sc->sc_intr_lock); 751 return ret; 752 } 753 754 Static int 755 ehci_intr1(ehci_softc_t *sc) 756 { 757 uint32_t intrs, eintrs; 758 759 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 760 761 /* In case the interrupt occurs before initialization has completed. */ 762 if (sc == NULL) { 763 #ifdef DIAGNOSTIC 764 printf("ehci_intr1: sc == NULL\n"); 765 #endif 766 return 0; 767 } 768 769 KASSERT(mutex_owned(&sc->sc_intr_lock)); 770 771 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 772 if (!intrs) 773 return 0; 774 775 eintrs = intrs & sc->sc_eintrs; 776 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 777 EOREAD4(sc, EHCI_USBSTS), eintrs); 778 if (!eintrs) 779 return 0; 780 781 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 782 if (eintrs & EHCI_STS_IAA) { 783 DPRINTF("door bell", 0, 0, 0, 0); 784 kpreempt_disable(); 785 KASSERT(sc->sc_doorbell_si != NULL); 786 softint_schedule(sc->sc_doorbell_si); 787 kpreempt_enable(); 788 eintrs &= ~EHCI_STS_IAA; 789 } 790 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 791 DPRINTF("INT=%jd ERRINT=%jd", 792 eintrs & EHCI_STS_INT ? 1 : 0, 793 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 794 usb_schedsoftintr(&sc->sc_bus); 795 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 796 } 797 if (eintrs & EHCI_STS_HSE) { 798 printf("%s: unrecoverable error, controller halted\n", 799 device_xname(sc->sc_dev)); 800 /* XXX what else */ 801 } 802 if (eintrs & EHCI_STS_PCD) { 803 kpreempt_disable(); 804 KASSERT(sc->sc_pcd_si != NULL); 805 softint_schedule(sc->sc_pcd_si); 806 kpreempt_enable(); 807 eintrs &= ~EHCI_STS_PCD; 808 } 809 810 if (eintrs != 0) { 811 /* Block unprocessed interrupts. */ 812 sc->sc_eintrs &= ~eintrs; 813 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 814 printf("%s: blocking intrs %#x\n", 815 device_xname(sc->sc_dev), eintrs); 816 } 817 818 return 1; 819 } 820 821 Static void 822 ehci_doorbell(void *addr) 823 { 824 ehci_softc_t *sc = addr; 825 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 826 827 mutex_enter(&sc->sc_lock); 828 if (sc->sc_doorbelllwp == NULL) 829 DPRINTF("spurious doorbell interrupt", 0, 0, 0, 0); 830 sc->sc_doorbelllwp = NULL; 831 cv_broadcast(&sc->sc_doorbell); 832 mutex_exit(&sc->sc_lock); 833 } 834 835 Static void 836 ehci_pcd(void *addr) 837 { 838 ehci_softc_t *sc = addr; 839 struct usbd_xfer *xfer; 840 u_char *p; 841 int i, m; 842 843 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 844 845 mutex_enter(&sc->sc_lock); 846 xfer = sc->sc_intrxfer; 847 848 if (xfer == NULL) { 849 /* Just ignore the change. */ 850 goto done; 851 } 852 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 853 854 p = xfer->ux_buf; 855 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 856 memset(p, 0, xfer->ux_length); 857 for (i = 1; i <= m; i++) { 858 /* Pick out CHANGE bits from the status reg. */ 859 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 860 p[i/8] |= 1 << (i%8); 861 if (i % 8 == 7) 862 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 863 } 864 xfer->ux_actlen = xfer->ux_length; 865 xfer->ux_status = USBD_NORMAL_COMPLETION; 866 867 usb_transfer_complete(xfer); 868 869 done: 870 mutex_exit(&sc->sc_lock); 871 } 872 873 Static void 874 ehci_softintr(void *v) 875 { 876 struct usbd_bus *bus = v; 877 ehci_softc_t *sc = EHCI_BUS2SC(bus); 878 struct ehci_xfer *ex, *nextex; 879 880 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 881 882 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 883 884 ex_completeq_t cq; 885 TAILQ_INIT(&cq); 886 887 /* 888 * The only explanation I can think of for why EHCI is as brain dead 889 * as UHCI interrupt-wise is that Intel was involved in both. 890 * An interrupt just tells us that something is done, we have no 891 * clue what, so we need to scan through all active transfers. :-( 892 */ 893 894 /* 895 * ehci_idone will remove transfer from sc->sc_intrhead if it's 896 * complete and add to our cq list 897 * 898 */ 899 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 900 switch (ex->ex_type) { 901 case EX_CTRL: 902 case EX_BULK: 903 case EX_INTR: 904 ehci_check_qh_intr(sc, ex, &cq); 905 break; 906 case EX_ISOC: 907 ehci_check_itd_intr(sc, ex, &cq); 908 break; 909 case EX_FS_ISOC: 910 ehci_check_sitd_intr(sc, ex, &cq); 911 break; 912 default: 913 KASSERT(false); 914 } 915 916 } 917 918 /* 919 * We abuse ex_next for the interrupt and complete lists and 920 * interrupt transfers will get re-added here so use 921 * the _SAFE version of TAILQ_FOREACH. 922 */ 923 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 924 usb_transfer_complete(&ex->ex_xfer); 925 } 926 927 /* Schedule a callout to catch any dropped transactions. */ 928 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 929 !TAILQ_EMPTY(&sc->sc_intrhead)) 930 callout_reset(&sc->sc_tmo_intrlist, 931 hz, ehci_intrlist_timeout, sc); 932 } 933 934 Static void 935 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 936 { 937 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 938 uint32_t status; 939 940 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 941 942 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 943 944 if (ex->ex_type == EX_CTRL) { 945 fsqtd = ex->ex_setup; 946 lsqtd = ex->ex_status; 947 } else { 948 fsqtd = ex->ex_sqtdstart; 949 lsqtd = ex->ex_sqtdend; 950 } 951 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 952 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 953 954 /* 955 * If the last TD is still active we need to check whether there 956 * is an error somewhere in the middle, or whether there was a 957 * short packet (SPD and not ACTIVE). 958 */ 959 usb_syncmem(&lsqtd->dma, 960 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 961 sizeof(lsqtd->qtd->qtd_status), 962 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 963 status = le32toh(lsqtd->qtd->qtd_status); 964 usb_syncmem(&lsqtd->dma, 965 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 966 sizeof(lsqtd->qtd->qtd_status), BUS_DMASYNC_PREREAD); 967 if (status & EHCI_QTD_ACTIVE) { 968 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 969 970 /* last qTD has already been checked */ 971 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 972 usb_syncmem(&sqtd->dma, 973 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 974 sizeof(sqtd->qtd->qtd_status), 975 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 976 status = le32toh(sqtd->qtd->qtd_status); 977 usb_syncmem(&sqtd->dma, 978 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 979 sizeof(sqtd->qtd->qtd_status), BUS_DMASYNC_PREREAD); 980 /* If there's an active QTD the xfer isn't done. */ 981 if (status & EHCI_QTD_ACTIVE) 982 break; 983 /* Any kind of error makes the xfer done. */ 984 if (status & EHCI_QTD_HALTED) 985 goto done; 986 /* Handle short packets */ 987 if (EHCI_QTD_GET_BYTES(status) != 0) { 988 /* 989 * If we get here for a control transfer then 990 * we need to let the hardware complete the 991 * status phase. That is, we're not done 992 * quite yet. 993 * 994 * Otherwise, we're done. 995 */ 996 if (ex->ex_type == EX_CTRL) { 997 break; 998 } 999 goto done; 1000 } 1001 } 1002 DPRINTFN(10, "ex=%#jx std=%#jx still active", 1003 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 1004 #ifdef EHCI_DEBUG 1005 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 1006 ehci_dump_sqtds(ex->ex_sqtdstart); 1007 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 1008 #endif 1009 return; 1010 } 1011 done: 1012 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1013 ehci_idone(ex, cq); 1014 } 1015 1016 Static void 1017 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1018 { 1019 ehci_soft_itd_t *itd; 1020 int i; 1021 1022 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1023 1024 KASSERT(mutex_owned(&sc->sc_lock)); 1025 1026 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1027 return; 1028 1029 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 1030 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 1031 1032 itd = ex->ex_itdend; 1033 1034 /* 1035 * check no active transfers in last itd, meaning we're finished 1036 */ 1037 1038 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1039 sizeof(itd->itd->itd_ctl), 1040 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1041 1042 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1043 if (le32toh(itd->itd->itd_ctl[i]) & EHCI_ITD_ACTIVE) 1044 break; 1045 } 1046 1047 if (i == EHCI_ITD_NUFRAMES) { 1048 goto done; /* All 8 descriptors inactive, it's done */ 1049 } 1050 1051 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1052 sizeof(itd->itd->itd_ctl), BUS_DMASYNC_PREREAD); 1053 1054 DPRINTFN(10, "ex %#jx itd %#jx still active", 1055 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 1056 return; 1057 done: 1058 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 1059 ehci_idone(ex, cq); 1060 } 1061 1062 void 1063 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1064 { 1065 ehci_soft_sitd_t *sitd; 1066 1067 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1068 1069 KASSERT(mutex_owned(&sc->sc_lock)); 1070 1071 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1072 return; 1073 1074 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1075 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1076 1077 sitd = ex->ex_sitdend; 1078 1079 /* 1080 * check no active transfers in last sitd, meaning we're finished 1081 */ 1082 1083 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1084 sizeof(sitd->sitd->sitd_trans), 1085 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1086 1087 bool active = ((le32toh(sitd->sitd->sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1088 1089 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1090 sizeof(sitd->sitd->sitd_trans), BUS_DMASYNC_PREREAD); 1091 1092 if (active) 1093 return; 1094 1095 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1096 ehci_idone(ex, cq); 1097 } 1098 1099 Static void 1100 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1101 { 1102 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1103 struct usbd_xfer *xfer = &ex->ex_xfer; 1104 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1105 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1106 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1107 uint32_t status = 0, nstatus = 0; 1108 int actlen = 0; 1109 1110 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1111 1112 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1113 1114 /* 1115 * Try to claim this xfer for completion. If it has already 1116 * completed or aborted, drop it on the floor. 1117 */ 1118 if (!usbd_xfer_trycomplete(xfer)) 1119 return; 1120 1121 #ifdef DIAGNOSTIC 1122 #ifdef EHCI_DEBUG 1123 if (ex->ex_isdone) { 1124 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1125 ehci_dump_exfer(ex); 1126 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1127 } 1128 #endif 1129 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1130 ex->ex_type, xfer->ux_status); 1131 ex->ex_isdone = true; 1132 #endif 1133 1134 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1135 (uintptr_t)epipe, 0, 0); 1136 1137 /* The transfer is done, compute actual length and status. */ 1138 if (ex->ex_type == EX_ISOC) { 1139 /* HS isoc transfer */ 1140 1141 struct ehci_soft_itd *itd; 1142 int i, nframes, len, uframes; 1143 1144 nframes = 0; 1145 1146 #ifdef EHCI_DEBUG 1147 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1148 ehci_dump_itds(ex->ex_itdstart); 1149 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1150 #endif 1151 1152 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1153 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1154 1155 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1156 usb_syncmem(&itd->dma, 1157 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1158 sizeof(itd->itd->itd_ctl), 1159 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1160 1161 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1162 /* 1163 * XXX - driver didn't fill in the frame full 1164 * of uframes. This leads to scheduling 1165 * inefficiencies, but working around 1166 * this doubles complexity of tracking 1167 * an xfer. 1168 */ 1169 if (nframes >= xfer->ux_nframes) 1170 break; 1171 1172 status = le32toh(itd->itd->itd_ctl[i]); 1173 len = EHCI_ITD_GET_LEN(status); 1174 if (EHCI_ITD_GET_STATUS(status) != 0) 1175 len = 0; /*No valid data on error*/ 1176 1177 xfer->ux_frlengths[nframes++] = len; 1178 actlen += len; 1179 } 1180 usb_syncmem(&itd->dma, 1181 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1182 sizeof(itd->itd->itd_ctl), BUS_DMASYNC_PREREAD); 1183 1184 if (nframes >= xfer->ux_nframes) 1185 break; 1186 } 1187 1188 xfer->ux_actlen = actlen; 1189 xfer->ux_status = USBD_NORMAL_COMPLETION; 1190 goto end; 1191 } else if (ex->ex_type == EX_FS_ISOC) { 1192 /* FS isoc transfer */ 1193 struct ehci_soft_sitd *sitd; 1194 int nframes, len; 1195 1196 nframes = 0; 1197 1198 for (sitd = ex->ex_sitdstart; sitd != NULL; 1199 sitd = sitd->xfer_next) { 1200 usb_syncmem(&sitd->dma, 1201 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1202 sizeof(sitd->sitd->sitd_trans), 1203 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1204 1205 /* 1206 * XXX - driver didn't fill in the frame full 1207 * of uframes. This leads to scheduling 1208 * inefficiencies, but working around 1209 * this doubles complexity of tracking 1210 * an xfer. 1211 */ 1212 if (nframes >= xfer->ux_nframes) 1213 break; 1214 1215 status = le32toh(sitd->sitd->sitd_trans); 1216 usb_syncmem(&sitd->dma, 1217 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1218 sizeof(sitd->sitd->sitd_trans), BUS_DMASYNC_PREREAD); 1219 1220 len = EHCI_SITD_GET_LEN(status); 1221 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1222 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1223 /* No valid data on error */ 1224 len = xfer->ux_frlengths[nframes]; 1225 } 1226 1227 /* 1228 * frlengths[i]: # of bytes to send 1229 * len: # of bytes host didn't send 1230 */ 1231 xfer->ux_frlengths[nframes] -= len; 1232 /* frlengths[i]: # of bytes host sent */ 1233 actlen += xfer->ux_frlengths[nframes++]; 1234 1235 if (nframes >= xfer->ux_nframes) 1236 break; 1237 } 1238 1239 xfer->ux_actlen = actlen; 1240 xfer->ux_status = USBD_NORMAL_COMPLETION; 1241 goto end; 1242 } 1243 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1244 ex->ex_type == EX_BULK); 1245 1246 /* Continue processing xfers using queue heads */ 1247 if (ex->ex_type == EX_CTRL) { 1248 fsqtd = ex->ex_setup; 1249 lsqtd = ex->ex_status; 1250 } else { 1251 fsqtd = ex->ex_sqtdstart; 1252 lsqtd = ex->ex_sqtdend; 1253 } 1254 #ifdef EHCI_DEBUG 1255 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1256 ehci_dump_sqtds(fsqtd); 1257 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1258 #endif 1259 1260 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1261 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 1262 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1263 nstatus = le32toh(sqtd->qtd->qtd_status); 1264 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 1265 BUS_DMASYNC_PREREAD); 1266 if (nstatus & EHCI_QTD_ACTIVE) 1267 break; 1268 1269 status = nstatus; 1270 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1271 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1272 } 1273 1274 /* 1275 * If there are left over TDs we need to update the toggle. 1276 * The default pipe doesn't need it since control transfers 1277 * start the toggle at 0 every time. 1278 * For a short transfer we need to update the toggle for the missing 1279 * packets within the qTD. 1280 */ 1281 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1282 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1283 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1284 status, nstatus, 0, 0); 1285 #if 0 1286 ehci_dump_sqh(epipe->sqh); 1287 ehci_dump_sqtds(ex->ex_sqtdstart); 1288 #endif 1289 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1290 } 1291 1292 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1293 status, 0); 1294 xfer->ux_actlen = actlen; 1295 if (status & EHCI_QTD_HALTED) { 1296 #ifdef EHCI_DEBUG 1297 DPRINTF("halted addr=%jd endpt=0x%02jx", 1298 xfer->ux_pipe->up_dev->ud_addr, 1299 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1300 0, 0); 1301 DPRINTF("cerr=%jd pid=%jd", 1302 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1303 0, 0); 1304 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1305 status & EHCI_QTD_ACTIVE ? 1 : 0, 1306 status & EHCI_QTD_HALTED ? 1 : 0, 1307 status & EHCI_QTD_BUFERR ? 1 : 0, 1308 status & EHCI_QTD_BABBLE ? 1 : 0); 1309 1310 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1311 status & EHCI_QTD_XACTERR ? 1 : 0, 1312 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1313 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1314 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1315 1316 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1317 ehci_dump_sqh(epipe->sqh); 1318 ehci_dump_sqtds(ex->ex_sqtdstart); 1319 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1320 #endif 1321 /* low&full speed has an extra error flag */ 1322 if (EHCI_QH_GET_EPS(epipe->sqh->qh->qh_endp) != 1323 EHCI_QH_SPEED_HIGH) 1324 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1325 else 1326 status &= EHCI_QTD_STATERRS; 1327 if (status == 0) /* no other errors means a stall */ { 1328 xfer->ux_status = USBD_STALLED; 1329 } else { 1330 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1331 } 1332 /* XXX need to reset TT on missed microframe */ 1333 if (status & EHCI_QTD_MISSEDMICRO) { 1334 printf("%s: missed microframe, TT reset not " 1335 "implemented, hub might be inoperational\n", 1336 device_xname(sc->sc_dev)); 1337 } 1338 } else { 1339 xfer->ux_status = USBD_NORMAL_COMPLETION; 1340 } 1341 1342 end: 1343 1344 ehci_del_intr_list(sc, ex); 1345 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1346 1347 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1348 } 1349 1350 Static void 1351 ehci_poll(struct usbd_bus *bus) 1352 { 1353 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1354 1355 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1356 1357 #ifdef EHCI_DEBUG 1358 static int last; 1359 int new; 1360 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1361 if (new != last) { 1362 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1363 last = new; 1364 } 1365 #endif 1366 1367 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1368 mutex_spin_enter(&sc->sc_intr_lock); 1369 ehci_intr1(sc); 1370 mutex_spin_exit(&sc->sc_intr_lock); 1371 } 1372 } 1373 1374 void 1375 ehci_childdet(device_t self, device_t child) 1376 { 1377 struct ehci_softc *sc = device_private(self); 1378 1379 KASSERT(sc->sc_child == child); 1380 sc->sc_child = NULL; 1381 } 1382 1383 int 1384 ehci_detach(struct ehci_softc *sc, int flags) 1385 { 1386 int rv = 0; 1387 1388 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1389 1390 if (sc->sc_child != NULL) { 1391 rv = config_detach(sc->sc_child, flags); 1392 if (rv != 0) 1393 return rv; 1394 } 1395 1396 if (sc->sc_ncomp > 0) { 1397 mutex_enter(&sc->sc_complock); 1398 /* XXX try to halt callout instead of waiting */ 1399 while (sc->sc_comp_state == CO_SCHED) 1400 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1401 mutex_exit(&sc->sc_complock); 1402 1403 callout_halt(&sc->sc_compcallout, NULL); 1404 callout_destroy(&sc->sc_compcallout); 1405 cv_destroy(&sc->sc_compcv); 1406 mutex_destroy(&sc->sc_complock); 1407 } 1408 1409 callout_halt(&sc->sc_tmo_intrlist, NULL); 1410 callout_destroy(&sc->sc_tmo_intrlist); 1411 1412 /* XXX free other data structures */ 1413 if (sc->sc_softitds) { 1414 kmem_free(sc->sc_softitds, 1415 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1416 } 1417 cv_destroy(&sc->sc_doorbell); 1418 1419 #if 0 1420 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1421 softint_disestablish(sc->sc_doorbell_si); 1422 softint_disestablish(sc->sc_pcd_si); 1423 mutex_destroy(&sc->sc_rhlock); 1424 mutex_destroy(&sc->sc_lock); 1425 mutex_destroy(&sc->sc_intr_lock); 1426 #endif 1427 1428 pool_cache_destroy(sc->sc_xferpool); 1429 1430 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1431 1432 return rv; 1433 } 1434 1435 int 1436 ehci_activate(device_t self, enum devact act) 1437 { 1438 struct ehci_softc *sc = device_private(self); 1439 1440 switch (act) { 1441 case DVACT_DEACTIVATE: 1442 sc->sc_dying = 1; 1443 return 0; 1444 default: 1445 return EOPNOTSUPP; 1446 } 1447 } 1448 1449 /* 1450 * Handle suspend/resume. 1451 * 1452 * Note that this power handler isn't to be registered directly; the 1453 * bus glue needs to call out to it. 1454 */ 1455 bool 1456 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1457 { 1458 ehci_softc_t *sc = device_private(dv); 1459 int i; 1460 uint32_t cmd, hcr; 1461 1462 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1463 1464 mutex_enter(&sc->sc_rhlock); 1465 1466 for (i = 1; i <= sc->sc_noport; i++) { 1467 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1468 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1469 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1470 } 1471 1472 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1473 1474 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1475 EOWRITE4(sc, EHCI_USBCMD, cmd); 1476 1477 for (i = 0; i < 100; i++) { 1478 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1479 if (hcr == 0) 1480 break; 1481 1482 usb_delay_ms(&sc->sc_bus, 1); 1483 } 1484 if (hcr != 0) 1485 printf("%s: reset timeout\n", device_xname(dv)); 1486 1487 cmd &= ~EHCI_CMD_RS; 1488 EOWRITE4(sc, EHCI_USBCMD, cmd); 1489 1490 for (i = 0; i < 100; i++) { 1491 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1492 if (hcr == EHCI_STS_HCH) 1493 break; 1494 1495 usb_delay_ms(&sc->sc_bus, 1); 1496 } 1497 if (hcr != EHCI_STS_HCH) 1498 printf("%s: config timeout\n", device_xname(dv)); 1499 1500 mutex_exit(&sc->sc_rhlock); 1501 1502 return true; 1503 } 1504 1505 bool 1506 ehci_resume(device_t dv, const pmf_qual_t *qual) 1507 { 1508 ehci_softc_t *sc = device_private(dv); 1509 int i; 1510 uint32_t cmd, hcr; 1511 1512 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1513 1514 mutex_enter(&sc->sc_rhlock); 1515 1516 /* restore things in case the bios sucks */ 1517 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1518 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1519 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1520 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1521 1522 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1523 1524 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1525 1526 hcr = 0; 1527 for (i = 1; i <= sc->sc_noport; i++) { 1528 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1529 if ((cmd & EHCI_PS_PO) == 0 && 1530 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1531 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1532 hcr = 1; 1533 } 1534 } 1535 1536 if (hcr) { 1537 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1538 1539 for (i = 1; i <= sc->sc_noport; i++) { 1540 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1541 if ((cmd & EHCI_PS_PO) == 0 && 1542 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1543 EOWRITE4(sc, EHCI_PORTSC(i), 1544 cmd & ~EHCI_PS_FPR); 1545 } 1546 } 1547 1548 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1549 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1550 1551 for (i = 0; i < 100; i++) { 1552 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1553 if (hcr != EHCI_STS_HCH) 1554 break; 1555 1556 usb_delay_ms(&sc->sc_bus, 1); 1557 } 1558 if (hcr == EHCI_STS_HCH) 1559 printf("%s: config timeout\n", device_xname(dv)); 1560 1561 mutex_exit(&sc->sc_rhlock); 1562 1563 return true; 1564 } 1565 1566 /* 1567 * Shut down the controller when the system is going down. 1568 */ 1569 bool 1570 ehci_shutdown(device_t self, int flags) 1571 { 1572 ehci_softc_t *sc = device_private(self); 1573 1574 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1575 1576 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1577 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1578 return true; 1579 } 1580 1581 Static struct usbd_xfer * 1582 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1583 { 1584 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1585 struct usbd_xfer *xfer; 1586 1587 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1588 if (xfer != NULL) { 1589 memset(xfer, 0, sizeof(*xfer)); 1590 1591 #ifdef DIAGNOSTIC 1592 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1593 ex->ex_isdone = true; 1594 xfer->ux_state = XFER_BUSY; 1595 #endif 1596 } 1597 return xfer; 1598 } 1599 1600 Static void 1601 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1602 { 1603 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1604 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1605 1606 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1607 xfer->ux_status == USBD_NOT_STARTED, 1608 "xfer %p state %d\n", xfer, xfer->ux_state); 1609 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1610 1611 #ifdef DIAGNOSTIC 1612 xfer->ux_state = XFER_FREE; 1613 #endif 1614 1615 pool_cache_put(sc->sc_xferpool, xfer); 1616 } 1617 1618 Static bool 1619 ehci_dying(struct usbd_bus *bus) 1620 { 1621 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1622 1623 return sc->sc_dying; 1624 } 1625 1626 Static void 1627 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1628 { 1629 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1630 1631 *lock = &sc->sc_lock; 1632 } 1633 1634 Static void 1635 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1636 { 1637 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1638 1639 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1640 1641 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1642 epipe->sqh->qh->qh_qtd.qtd_status, 0, 0); 1643 #ifdef EHCI_DEBUG 1644 if (ehcidebug) 1645 usbd_dump_pipe(pipe); 1646 #endif 1647 epipe->nexttoggle = 0; 1648 } 1649 1650 Static void 1651 ehci_noop(struct usbd_pipe *pipe) 1652 { 1653 } 1654 1655 #ifdef EHCI_DEBUG 1656 /* 1657 * Unused function - this is meant to be called from a kernel 1658 * debugger. 1659 */ 1660 void 1661 ehci_dump(void) 1662 { 1663 ehci_softc_t *sc = theehci; 1664 int i; 1665 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1666 EOREAD4(sc, EHCI_USBCMD), 1667 EOREAD4(sc, EHCI_USBSTS), 1668 EOREAD4(sc, EHCI_USBINTR)); 1669 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1670 EOREAD4(sc, EHCI_FRINDEX), 1671 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1672 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1673 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1674 for (i = 1; i <= sc->sc_noport; i++) 1675 printf("port %d status=0x%08x\n", i, 1676 EOREAD4(sc, EHCI_PORTSC(i))); 1677 } 1678 1679 Static void 1680 ehci_dump_regs(ehci_softc_t *sc) 1681 { 1682 int i; 1683 1684 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1685 1686 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1687 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1688 EOREAD4(sc, EHCI_USBINTR), 0); 1689 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1690 "async = 0x%08jx", 1691 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1692 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1693 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1694 for (i = 1; i <= sc->sc_noport; i += 2) { 1695 if (i == sc->sc_noport) { 1696 DPRINTF("port %jd status = 0x%08jx", i, 1697 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1698 } else { 1699 DPRINTF("port %jd status = 0x%08jx port %jd " 1700 "status = 0x%08jx", 1701 i, EOREAD4(sc, EHCI_PORTSC(i)), 1702 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1703 } 1704 } 1705 } 1706 1707 #define ehci_dump_link(link, type) do { \ 1708 DPRINTF(" link 0x%08jx (T = %jd):", \ 1709 link, \ 1710 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1711 if (type) { \ 1712 DPRINTF( \ 1713 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1714 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1715 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1716 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1717 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1718 } \ 1719 } while(0) 1720 1721 Static void 1722 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1723 { 1724 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1725 int i; 1726 uint32_t stop = 0; 1727 1728 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1729 ehci_dump_sqtd(sqtd); 1730 usb_syncmem(&sqtd->dma, 1731 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1732 sizeof(sqtd->qtd->qtd_next), 1733 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1734 stop = sqtd->qtd->qtd_next & htole32(EHCI_LINK_TERMINATE); 1735 usb_syncmem(&sqtd->dma, 1736 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1737 sizeof(sqtd->qtd->qtd_next), BUS_DMASYNC_PREREAD); 1738 } 1739 if (!stop) 1740 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1741 } 1742 1743 Static void 1744 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1745 { 1746 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1747 1748 usb_syncmem(&sqtd->dma, sqtd->offs, 1749 sizeof(*sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1750 1751 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1752 0, 0); 1753 ehci_dump_qtd(sqtd->qtd); 1754 1755 usb_syncmem(&sqtd->dma, sqtd->offs, 1756 sizeof(*sqtd->qtd), BUS_DMASYNC_PREREAD); 1757 } 1758 1759 Static void 1760 ehci_dump_qh_qtd(struct ehci_qh_qtd_t *qh_qtd) 1761 { 1762 ehci_qtd_t qtd = { 1763 .qtd_next = qh_qtd->qtd_next, 1764 .qtd_altnext = qh_qtd->qtd_altnext, 1765 .qtd_status = qh_qtd->qtd_status, 1766 }; 1767 1768 /* Manually memcpy(), because of volatile. */ 1769 for (unsigned i = 0; i < EHCI_QTD_NBUFFERS; i++) { 1770 qtd.qtd_buffer[i] = qh_qtd->qtd_buffer[i]; 1771 qtd.qtd_buffer_hi[i] = qh_qtd->qtd_buffer_hi[i]; 1772 } 1773 1774 ehci_dump_qtd(&qtd); 1775 } 1776 1777 Static void 1778 ehci_dump_qtd(ehci_qtd_t *qtd) 1779 { 1780 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1781 uint32_t s = le32toh(qtd->qtd_status); 1782 1783 DPRINTFN(10, 1784 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1785 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1786 DPRINTFN(10, 1787 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1788 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1789 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1790 DPRINTFN(10, 1791 " cerr = %jd pid = %jd stat = %jx", 1792 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1793 0); 1794 DPRINTFN(10, 1795 "active =%jd halted=%jd buferr=%jd babble=%jd", 1796 s & EHCI_QTD_ACTIVE ? 1 : 0, 1797 s & EHCI_QTD_HALTED ? 1 : 0, 1798 s & EHCI_QTD_BUFERR ? 1 : 0, 1799 s & EHCI_QTD_BABBLE ? 1 : 0); 1800 DPRINTFN(10, 1801 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1802 s & EHCI_QTD_XACTERR ? 1 : 0, 1803 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1804 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1805 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1806 DPRINTFN(10, 1807 "buffer[0] = %#jx buffer[1] = %#jx " 1808 "buffer[2] = %#jx buffer[3] = %#jx", 1809 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1810 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1811 DPRINTFN(10, 1812 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1813 } 1814 1815 Static void 1816 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1817 { 1818 ehci_qh_t *qh = sqh->qh; 1819 ehci_link_t link; 1820 uint32_t endp, endphub; 1821 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1822 1823 usb_syncmem(&sqh->dma, sqh->offs, 1824 sizeof(*sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1825 1826 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1827 link = le32toh(qh->qh_link); 1828 ehci_dump_link(link, true); 1829 1830 endp = le32toh(qh->qh_endp); 1831 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1832 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1833 "eps = %jd", 1834 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1835 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1836 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1837 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1838 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1839 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1840 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1841 1842 endphub = le32toh(qh->qh_endphub); 1843 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1844 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1845 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1846 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1847 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1848 EHCI_QH_GET_MULT(endphub), 0); 1849 1850 link = le32toh(qh->qh_curqtd); 1851 ehci_dump_link(link, false); 1852 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1853 ehci_dump_qh_qtd(&qh->qh_qtd); 1854 1855 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 1856 BUS_DMASYNC_PREREAD); 1857 } 1858 1859 Static void 1860 ehci_dump_itds(ehci_soft_itd_t *itd) 1861 { 1862 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1863 int i; 1864 uint32_t stop = 0; 1865 1866 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1867 ehci_dump_itd(itd); 1868 usb_syncmem(&itd->dma, 1869 itd->offs + offsetof(ehci_itd_t, itd_next), 1870 sizeof(itd->itd->itd_next), 1871 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1872 stop = itd->itd->itd_next & htole32(EHCI_LINK_TERMINATE); 1873 usb_syncmem(&itd->dma, 1874 itd->offs + offsetof(ehci_itd_t, itd_next), 1875 sizeof(itd->itd->itd_next), BUS_DMASYNC_PREREAD); 1876 } 1877 if (!stop) 1878 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1879 } 1880 1881 Static void 1882 ehci_dump_itd(struct ehci_soft_itd *itd) 1883 { 1884 ehci_isoc_trans_t t; 1885 ehci_isoc_bufr_ptr_t b, b2, b3; 1886 int i; 1887 1888 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1889 1890 DPRINTF("ITD: next phys = %#jx", itd->itd->itd_next, 0, 0, 0); 1891 1892 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1893 t = le32toh(itd->itd->itd_ctl[i]); 1894 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1895 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1896 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1897 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1898 EHCI_ITD_GET_OFFS(t), 0); 1899 } 1900 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1901 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1902 DPRINTF(" %jx", 1903 EHCI_ITD_GET_BPTR(le32toh(itd->itd->itd_bufr[i])), 0, 0, 0); 1904 1905 b = le32toh(itd->itd->itd_bufr[0]); 1906 b2 = le32toh(itd->itd->itd_bufr[1]); 1907 b3 = le32toh(itd->itd->itd_bufr[2]); 1908 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1909 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1910 DPRINTF(" maxpkt = %jx multi = %jx", 1911 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1912 } 1913 1914 Static void 1915 ehci_dump_sitd(struct ehci_soft_itd *itd) 1916 { 1917 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1918 1919 DPRINTF("SITD %#jx next = %p prev = %#jx", 1920 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1921 (uintptr_t)itd->frame_list.prev, 0); 1922 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1923 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1924 } 1925 1926 Static void 1927 ehci_dump_exfer(struct ehci_xfer *ex) 1928 { 1929 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1930 1931 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1932 ex->ex_isdone, 0); 1933 1934 switch (ex->ex_type) { 1935 case EX_CTRL: 1936 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1937 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1938 (uintptr_t)ex->ex_status, 0); 1939 break; 1940 case EX_BULK: 1941 case EX_INTR: 1942 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1943 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1944 0, 0); 1945 break; 1946 case EX_ISOC: 1947 DPRINTF(" itdstart = %#jx itdend = %#jx", 1948 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1949 break; 1950 case EX_FS_ISOC: 1951 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1952 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1953 0, 0); 1954 break; 1955 default: 1956 DPRINTF(" unknown type", 0, 0, 0, 0); 1957 } 1958 } 1959 #endif 1960 1961 Static usbd_status 1962 ehci_open(struct usbd_pipe *pipe) 1963 { 1964 struct usbd_device *dev = pipe->up_dev; 1965 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1966 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1967 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1968 uint8_t addr = dev->ud_addr; 1969 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1970 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1971 ehci_soft_qh_t *sqh; 1972 usbd_status err; 1973 int ival, speed, naks; 1974 int hshubaddr, hshubport; 1975 1976 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1977 1978 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1979 ed->bEndpointAddress, rhaddr); 1980 1981 if (dev->ud_myhsport) { 1982 /* 1983 * When directly attached FS/LS device while doing embedded 1984 * transaction translations and we are the hub, set the hub 1985 * address to 0 (us). 1986 */ 1987 if (!(sc->sc_flags & EHCIF_ETTF) 1988 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1989 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1990 } else { 1991 hshubaddr = 0; 1992 } 1993 hshubport = dev->ud_myhsport->up_portno; 1994 } else { 1995 hshubaddr = 0; 1996 hshubport = 0; 1997 } 1998 1999 if (sc->sc_dying) 2000 return USBD_IOERROR; 2001 2002 /* toggle state needed for bulk endpoints */ 2003 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 2004 2005 if (addr == rhaddr) { 2006 switch (ed->bEndpointAddress) { 2007 case USB_CONTROL_ENDPOINT: 2008 pipe->up_methods = &roothub_ctrl_methods; 2009 break; 2010 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2011 pipe->up_methods = &ehci_root_intr_methods; 2012 break; 2013 default: 2014 DPRINTF("bad bEndpointAddress 0x%02jx", 2015 ed->bEndpointAddress, 0, 0, 0); 2016 return USBD_INVAL; 2017 } 2018 return USBD_NORMAL_COMPLETION; 2019 } 2020 2021 /* XXX All this stuff is only valid for async. */ 2022 switch (dev->ud_speed) { 2023 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 2024 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 2025 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 2026 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 2027 } 2028 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 2029 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 2030 0); 2031 return USBD_INVAL; 2032 } 2033 2034 /* 2035 * For interrupt transfer, nak throttling must be disabled, but for 2036 * the other transfer type, nak throttling should be enabled from the 2037 * viewpoint that avoids the memory thrashing. 2038 */ 2039 naks = (xfertype == UE_INTERRUPT) ? 0 2040 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 2041 2042 /* Allocate sqh for everything, save isoc xfers */ 2043 if (xfertype != UE_ISOCHRONOUS) { 2044 sqh = ehci_alloc_sqh(sc); 2045 if (sqh == NULL) 2046 return USBD_NOMEM; 2047 /* qh_link filled when the QH is added */ 2048 sqh->qh->qh_endp = htole32( 2049 EHCI_QH_SET_ADDR(addr) | 2050 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 2051 EHCI_QH_SET_EPS(speed) | 2052 EHCI_QH_DTC | 2053 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 2054 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 2055 EHCI_QH_CTL : 0) | 2056 EHCI_QH_SET_NRL(naks) 2057 ); 2058 sqh->qh->qh_endphub = htole32( 2059 EHCI_QH_SET_MULT(1) | 2060 (xfertype == UE_INTERRUPT ? 2061 EHCI_QH_SET_SMASK(__BIT(1)) /* Start Split Y1 */ 2062 : 0) 2063 ); 2064 if (speed != EHCI_QH_SPEED_HIGH) 2065 sqh->qh->qh_endphub |= htole32( 2066 EHCI_QH_SET_PORT(hshubport) | 2067 EHCI_QH_SET_HUBA(hshubaddr) | 2068 (xfertype == UE_INTERRUPT ? 2069 EHCI_QH_SET_CMASK(__BITS(3,5)) /* CS Y[345] */ 2070 : 0) 2071 ); 2072 sqh->qh->qh_curqtd = EHCI_NULL; 2073 /* Fill the overlay qTD */ 2074 sqh->qh->qh_qtd.qtd_next = EHCI_NULL; 2075 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 2076 sqh->qh->qh_qtd.qtd_status = htole32(0); 2077 2078 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 2079 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2080 epipe->sqh = sqh; 2081 } else { 2082 sqh = NULL; 2083 } /*xfertype == UE_ISOC*/ 2084 2085 switch (xfertype) { 2086 case UE_CONTROL: 2087 /* we can use 64bit DMA for the reqdma buffer */ 2088 err = usb_allocmem(sc->sc_bus.ub_dmatag, 2089 sizeof(usb_device_request_t), 0, USBMALLOC_COHERENT, 2090 &epipe->ctrl.reqdma); 2091 #ifdef EHCI_DEBUG 2092 if (err) 2093 printf("ehci_open: usb_allocmem()=%d\n", err); 2094 #endif 2095 if (err) 2096 goto bad; 2097 pipe->up_methods = &ehci_device_ctrl_methods; 2098 mutex_enter(&sc->sc_lock); 2099 ehci_add_qh(sc, sqh, sc->sc_async_head); 2100 mutex_exit(&sc->sc_lock); 2101 break; 2102 case UE_BULK: 2103 pipe->up_methods = &ehci_device_bulk_methods; 2104 mutex_enter(&sc->sc_lock); 2105 ehci_add_qh(sc, sqh, sc->sc_async_head); 2106 mutex_exit(&sc->sc_lock); 2107 break; 2108 case UE_INTERRUPT: 2109 pipe->up_methods = &ehci_device_intr_methods; 2110 ival = pipe->up_interval; 2111 if (ival == USBD_DEFAULT_INTERVAL) { 2112 if (speed == EHCI_QH_SPEED_HIGH) { 2113 if (ed->bInterval > 16) { 2114 /* 2115 * illegal with high-speed, but there 2116 * were documentation bugs in the spec, 2117 * so be generous 2118 */ 2119 ival = 256; 2120 } else 2121 ival = (1 << (ed->bInterval - 1)) / 8; 2122 } else 2123 ival = ed->bInterval; 2124 } 2125 err = ehci_device_setintr(sc, sqh, ival); 2126 if (err) 2127 goto bad; 2128 break; 2129 case UE_ISOCHRONOUS: 2130 pipe->up_serialise = false; 2131 if (speed == EHCI_QH_SPEED_HIGH) 2132 pipe->up_methods = &ehci_device_isoc_methods; 2133 else 2134 pipe->up_methods = &ehci_device_fs_isoc_methods; 2135 if (ed->bInterval == 0 || ed->bInterval > 16) { 2136 printf("ehci: opening pipe with invalid bInterval\n"); 2137 err = USBD_INVAL; 2138 goto bad; 2139 } 2140 if (UGETW(ed->wMaxPacketSize) == 0) { 2141 printf("ehci: zero length endpoint open request\n"); 2142 err = USBD_INVAL; 2143 goto bad; 2144 } 2145 epipe->isoc.next_frame = 0; 2146 epipe->isoc.cur_xfers = 0; 2147 break; 2148 default: 2149 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2150 err = USBD_INVAL; 2151 goto bad; 2152 } 2153 return USBD_NORMAL_COMPLETION; 2154 2155 bad: 2156 if (sqh != NULL) { 2157 mutex_enter(&sc->sc_lock); 2158 ehci_free_sqh(sc, sqh); 2159 mutex_exit(&sc->sc_lock); 2160 } 2161 return err; 2162 } 2163 2164 /* 2165 * Add an ED to the schedule. Called with USB lock held. 2166 */ 2167 Static void 2168 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2169 { 2170 2171 KASSERT(mutex_owned(&sc->sc_lock)); 2172 2173 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2174 2175 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2176 sizeof(head->qh->qh_link), BUS_DMASYNC_POSTWRITE); 2177 2178 sqh->next = head->next; 2179 sqh->qh->qh_link = head->qh->qh_link; 2180 2181 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2182 sizeof(sqh->qh->qh_link), BUS_DMASYNC_PREWRITE); 2183 2184 head->next = sqh; 2185 head->qh->qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2186 2187 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2188 sizeof(head->qh->qh_link), BUS_DMASYNC_PREWRITE); 2189 2190 #ifdef EHCI_DEBUG 2191 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2192 ehci_dump_sqh(sqh); 2193 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2194 #endif 2195 } 2196 2197 /* 2198 * Remove an ED from the schedule. Called with USB lock held. 2199 */ 2200 Static void 2201 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2202 { 2203 ehci_soft_qh_t *p; 2204 2205 KASSERT(mutex_owned(&sc->sc_lock)); 2206 2207 /* XXX */ 2208 for (p = head; p != NULL && p->next != sqh; p = p->next) 2209 ; 2210 if (p == NULL) 2211 panic("ehci_rem_qh: ED not found"); 2212 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2213 sizeof(sqh->qh->qh_link), BUS_DMASYNC_POSTWRITE); 2214 p->next = sqh->next; 2215 p->qh->qh_link = sqh->qh->qh_link; 2216 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2217 sizeof(p->qh->qh_link), BUS_DMASYNC_PREWRITE); 2218 2219 ehci_sync_hc(sc); 2220 } 2221 2222 Static void 2223 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2224 { 2225 int i; 2226 uint32_t status; 2227 2228 /* Save toggle bit and ping status. */ 2229 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 2230 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2231 status = sqh->qh->qh_qtd.qtd_status & 2232 htole32(EHCI_QTD_TOGGLE_MASK | 2233 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2234 /* Set HALTED to make hw leave it alone. */ 2235 sqh->qh->qh_qtd.qtd_status = 2236 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2237 usb_syncmem(&sqh->dma, 2238 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2239 sizeof(sqh->qh->qh_qtd.qtd_status), 2240 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2241 sqh->qh->qh_curqtd = 0; 2242 sqh->qh->qh_qtd.qtd_next = htole32(sqtd->physaddr); 2243 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 2244 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2245 sqh->qh->qh_qtd.qtd_buffer[i] = 0; 2246 sqh->sqtd = sqtd; 2247 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 2248 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2249 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2250 sqh->qh->qh_qtd.qtd_status = status; 2251 usb_syncmem(&sqh->dma, 2252 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2253 sizeof(sqh->qh->qh_qtd.qtd_status), 2254 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2255 } 2256 2257 /* 2258 * Ensure that the HC has released all references to the QH. We do this 2259 * by asking for a Async Advance Doorbell interrupt and then we wait for 2260 * the interrupt. 2261 * To make this easier we first obtain exclusive use of the doorbell. 2262 * 2263 * Releases the bus lock to sleep while waiting for interrupt. 2264 */ 2265 Static void 2266 ehci_sync_hc(ehci_softc_t *sc) 2267 { 2268 unsigned delta = hz; 2269 unsigned starttime = getticks(); 2270 unsigned endtime = starttime + delta; 2271 unsigned now; 2272 2273 KASSERT(mutex_owned(&sc->sc_lock)); 2274 2275 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2276 2277 if (sc->sc_dying) { 2278 DPRINTF("dying", 0, 0, 0, 0); 2279 return; 2280 } 2281 2282 /* 2283 * Wait until any concurrent ehci_sync_hc has completed so we 2284 * have exclusive access to the doorbell. 2285 */ 2286 while (sc->sc_doorbelllwp) 2287 cv_wait(&sc->sc_doorbell, &sc->sc_lock); 2288 sc->sc_doorbelllwp = curlwp; 2289 2290 /* ask for doorbell */ 2291 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2292 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2293 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2294 2295 /* 2296 * Wait for the ehci to ring our doorbell. 2297 */ 2298 while (sc->sc_doorbelllwp == curlwp) { 2299 now = getticks(); 2300 if (now - starttime >= delta) { 2301 sc->sc_doorbelllwp = NULL; 2302 cv_broadcast(&sc->sc_doorbell); 2303 DPRINTF("doorbell timeout", 0, 0, 0, 0); 2304 #ifdef DIAGNOSTIC /* XXX DIAGNOSTIC abuse, do this differently */ 2305 printf("ehci_sync_hc: timed out\n"); 2306 #endif 2307 break; 2308 } 2309 (void)cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, 2310 endtime - now); 2311 } 2312 2313 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2314 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2315 } 2316 2317 Static void 2318 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2319 { 2320 2321 KASSERT(mutex_owned(&sc->sc_lock)); 2322 2323 for (; itd != NULL; itd = itd->xfer_next) { 2324 struct ehci_soft_itd *prev = itd->frame_list.prev; 2325 2326 /* Unlink itd from hardware chain, or frame array */ 2327 if (prev == NULL) { /* We're at the table head */ 2328 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2329 sc->sc_flist[itd->slot] = itd->itd->itd_next; 2330 usb_syncmem(&sc->sc_fldma, 2331 sizeof(ehci_link_t) * itd->slot, 2332 sizeof(ehci_link_t), 2333 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2334 2335 if (itd->frame_list.next != NULL) 2336 itd->frame_list.next->frame_list.prev = NULL; 2337 } else { 2338 /* XXX this part is untested... */ 2339 prev->itd->itd_next = itd->itd->itd_next; 2340 usb_syncmem(&itd->dma, 2341 itd->offs + offsetof(ehci_itd_t, itd_next), 2342 sizeof(itd->itd->itd_next), BUS_DMASYNC_PREWRITE); 2343 2344 prev->frame_list.next = itd->frame_list.next; 2345 if (itd->frame_list.next != NULL) 2346 itd->frame_list.next->frame_list.prev = prev; 2347 } 2348 } 2349 } 2350 2351 Static void 2352 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2353 { 2354 struct ehci_soft_itd *next; 2355 2356 mutex_enter(&sc->sc_lock); 2357 next = NULL; 2358 for (; itd != NULL; itd = next) { 2359 next = itd->xfer_next; 2360 ehci_free_itd_locked(sc, itd); 2361 } 2362 mutex_exit(&sc->sc_lock); 2363 } 2364 2365 Static void 2366 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2367 { 2368 2369 KASSERT(mutex_owned(&sc->sc_lock)); 2370 2371 for (; sitd != NULL; sitd = sitd->xfer_next) { 2372 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2373 2374 /* Unlink sitd from hardware chain, or frame array */ 2375 if (prev == NULL) { /* We're at the table head */ 2376 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2377 sc->sc_flist[sitd->slot] = sitd->sitd->sitd_next; 2378 usb_syncmem(&sc->sc_fldma, 2379 sizeof(ehci_link_t) * sitd->slot, 2380 sizeof(ehci_link_t), 2381 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2382 2383 if (sitd->frame_list.next != NULL) 2384 sitd->frame_list.next->frame_list.prev = NULL; 2385 } else { 2386 /* XXX this part is untested... */ 2387 prev->sitd->sitd_next = sitd->sitd->sitd_next; 2388 usb_syncmem(&sitd->dma, 2389 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2390 sizeof(sitd->sitd->sitd_next), BUS_DMASYNC_PREWRITE); 2391 2392 prev->frame_list.next = sitd->frame_list.next; 2393 if (sitd->frame_list.next != NULL) 2394 sitd->frame_list.next->frame_list.prev = prev; 2395 } 2396 } 2397 } 2398 2399 Static void 2400 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2401 { 2402 2403 mutex_enter(&sc->sc_lock); 2404 struct ehci_soft_sitd *next = NULL; 2405 for (; sitd != NULL; sitd = next) { 2406 next = sitd->xfer_next; 2407 ehci_free_sitd_locked(sc, sitd); 2408 } 2409 mutex_exit(&sc->sc_lock); 2410 } 2411 2412 /***********/ 2413 2414 static int 2415 ehci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req, 2416 void *buf, int buflen) 2417 { 2418 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2419 usb_hub_descriptor_t hubd; 2420 usb_port_status_t ps; 2421 uint16_t len, value, index; 2422 int l, totlen = 0; 2423 int port, i; 2424 uint32_t v; 2425 2426 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2427 2428 KASSERT(mutex_owned(&sc->sc_rhlock)); 2429 2430 if (sc->sc_dying) 2431 return -1; 2432 2433 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2434 0, 0); 2435 2436 len = UGETW(req->wLength); 2437 value = UGETW(req->wValue); 2438 index = UGETW(req->wIndex); 2439 2440 #define C(x,y) ((x) | ((y) << 8)) 2441 switch (C(req->bRequest, req->bmRequestType)) { 2442 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2443 if (len == 0) 2444 break; 2445 switch (value) { 2446 #define sd ((usb_string_descriptor_t *)buf) 2447 case C(2, UDESC_STRING): 2448 /* Product */ 2449 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2450 break; 2451 #undef sd 2452 default: 2453 /* default from usbroothub */ 2454 return buflen; 2455 } 2456 break; 2457 2458 /* Hub requests */ 2459 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2460 break; 2461 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2462 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2463 value, 0, 0); 2464 if (index < 1 || index > sc->sc_noport) { 2465 return -1; 2466 } 2467 port = EHCI_PORTSC(index); 2468 v = EOREAD4(sc, port); 2469 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2470 v &= ~EHCI_PS_CLEAR; 2471 switch (value) { 2472 case UHF_PORT_ENABLE: 2473 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2474 break; 2475 case UHF_PORT_SUSPEND: 2476 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2477 break; 2478 v &= ~EHCI_PS_SUSP; 2479 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2480 /* see USB2 spec ch. 7.1.7.7 */ 2481 usb_delay_ms(&sc->sc_bus, 20); 2482 EOWRITE4(sc, port, v); 2483 usb_delay_ms(&sc->sc_bus, 2); 2484 #ifdef DEBUG 2485 v = EOREAD4(sc, port); 2486 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2487 printf("ehci: resume failed: %x\n", v); 2488 #endif 2489 break; 2490 case UHF_PORT_POWER: 2491 if (sc->sc_hasppc) 2492 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2493 break; 2494 case UHF_PORT_TEST: 2495 DPRINTF("clear port test %jd", index, 0, 0, 0); 2496 break; 2497 case UHF_PORT_INDICATOR: 2498 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2499 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2500 break; 2501 case UHF_C_PORT_CONNECTION: 2502 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2503 break; 2504 case UHF_C_PORT_ENABLE: 2505 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2506 break; 2507 case UHF_C_PORT_SUSPEND: 2508 /* how? */ 2509 break; 2510 case UHF_C_PORT_OVER_CURRENT: 2511 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2512 break; 2513 case UHF_C_PORT_RESET: 2514 sc->sc_isreset[index] = 0; 2515 break; 2516 default: 2517 return -1; 2518 } 2519 #if 0 2520 switch(value) { 2521 case UHF_C_PORT_CONNECTION: 2522 case UHF_C_PORT_ENABLE: 2523 case UHF_C_PORT_SUSPEND: 2524 case UHF_C_PORT_OVER_CURRENT: 2525 case UHF_C_PORT_RESET: 2526 default: 2527 break; 2528 } 2529 #endif 2530 break; 2531 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2532 if (len == 0) 2533 break; 2534 if ((value & 0xff) != 0) { 2535 return -1; 2536 } 2537 totlen = uimin(buflen, sizeof(hubd)); 2538 memcpy(&hubd, buf, totlen); 2539 hubd.bNbrPorts = sc->sc_noport; 2540 v = EREAD4(sc, EHCI_HCSPARAMS); 2541 USETW(hubd.wHubCharacteristics, 2542 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2543 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2544 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2545 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2546 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2547 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2548 totlen = uimin(totlen, hubd.bDescLength); 2549 memcpy(buf, &hubd, totlen); 2550 break; 2551 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2552 if (len != 4) { 2553 return -1; 2554 } 2555 memset(buf, 0, len); /* ? XXX */ 2556 totlen = len; 2557 break; 2558 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2559 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2560 if (index < 1 || index > sc->sc_noport) { 2561 return -1; 2562 } 2563 if (len != 4) { 2564 return -1; 2565 } 2566 v = EOREAD4(sc, EHCI_PORTSC(index)); 2567 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2568 2569 i = UPS_HIGH_SPEED; 2570 if (sc->sc_flags & EHCIF_ETTF) { 2571 /* 2572 * If we are doing embedded transaction translation, 2573 * then directly attached LS/FS devices are reset by 2574 * the EHCI controller itself. PSPD is encoded 2575 * the same way as in USBSTATUS. 2576 */ 2577 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2578 } 2579 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2580 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2581 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2582 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2583 if (v & EHCI_PS_PR) i |= UPS_RESET; 2584 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2585 if (sc->sc_vendor_port_status) 2586 i = sc->sc_vendor_port_status(sc, v, i); 2587 USETW(ps.wPortStatus, i); 2588 i = 0; 2589 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2590 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2591 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2592 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2593 USETW(ps.wPortChange, i); 2594 totlen = uimin(len, sizeof(ps)); 2595 memcpy(buf, &ps, totlen); 2596 break; 2597 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2598 return -1; 2599 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2600 break; 2601 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2602 if (index < 1 || index > sc->sc_noport) { 2603 return -1; 2604 } 2605 port = EHCI_PORTSC(index); 2606 v = EOREAD4(sc, port); 2607 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2608 v &= ~EHCI_PS_CLEAR; 2609 switch(value) { 2610 case UHF_PORT_ENABLE: 2611 EOWRITE4(sc, port, v | EHCI_PS_PE); 2612 break; 2613 case UHF_PORT_SUSPEND: 2614 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2615 break; 2616 case UHF_PORT_RESET: 2617 DPRINTF("reset port %jd", index, 0, 0, 0); 2618 if (EHCI_PS_IS_LOWSPEED(v) 2619 && sc->sc_ncomp > 0 2620 && !(sc->sc_flags & EHCIF_ETTF)) { 2621 /* 2622 * Low speed device on non-ETTF controller or 2623 * unaccompanied controller, give up ownership. 2624 */ 2625 ehci_disown(sc, index, 1); 2626 break; 2627 } 2628 /* Start reset sequence. */ 2629 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2630 EOWRITE4(sc, port, v | EHCI_PS_PR); 2631 /* Wait for reset to complete. */ 2632 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2633 if (sc->sc_dying) { 2634 return -1; 2635 } 2636 /* 2637 * An embedded transaction translator will automatically 2638 * terminate the reset sequence so there's no need to 2639 * it. 2640 */ 2641 v = EOREAD4(sc, port); 2642 if (v & EHCI_PS_PR) { 2643 /* Terminate reset sequence. */ 2644 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2645 /* Wait for HC to complete reset. */ 2646 usb_delay_ms(&sc->sc_bus, 2647 EHCI_PORT_RESET_COMPLETE); 2648 if (sc->sc_dying) { 2649 return -1; 2650 } 2651 } 2652 2653 v = EOREAD4(sc, port); 2654 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2655 if (v & EHCI_PS_PR) { 2656 printf("%s: port reset timeout\n", 2657 device_xname(sc->sc_dev)); 2658 return USBD_TIMEOUT; 2659 } 2660 if (!(v & EHCI_PS_PE)) { 2661 /* Not a high speed device, give up ownership.*/ 2662 ehci_disown(sc, index, 0); 2663 break; 2664 } 2665 sc->sc_isreset[index] = 1; 2666 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2667 v, 0, 0); 2668 break; 2669 case UHF_PORT_POWER: 2670 DPRINTF("set port power %jd (has PPC = %jd)", index, 2671 sc->sc_hasppc, 0, 0); 2672 if (sc->sc_hasppc) 2673 EOWRITE4(sc, port, v | EHCI_PS_PP); 2674 break; 2675 case UHF_PORT_TEST: 2676 DPRINTF("set port test %jd", index, 0, 0, 0); 2677 break; 2678 case UHF_PORT_INDICATOR: 2679 DPRINTF("set port ind %jd", index, 0, 0, 0); 2680 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2681 break; 2682 default: 2683 return -1; 2684 } 2685 break; 2686 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2687 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2688 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2689 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2690 break; 2691 default: 2692 /* default from usbroothub */ 2693 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2694 2695 return buflen; 2696 } 2697 2698 DPRINTF("returning %jd", totlen, 0, 0, 0); 2699 2700 return totlen; 2701 } 2702 2703 Static int 2704 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2705 void *buf, int buflen) 2706 { 2707 struct ehci_softc *sc = EHCI_BUS2SC(bus); 2708 int actlen; 2709 2710 mutex_enter(&sc->sc_rhlock); 2711 actlen = ehci_roothub_ctrl_locked(bus, req, buf, buflen); 2712 mutex_exit(&sc->sc_rhlock); 2713 2714 return actlen; 2715 } 2716 2717 /* 2718 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2719 * 2720 * This pile of garbage below works around the following problem without 2721 * holding boots with no hand-over devices present, while penalising 2722 * boots where the first ehci probe hands off devices with a 5 second 2723 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2724 * for RB_SINGLE, but the same basic issue exists. 2725 * 2726 * The way ehci hand-off works, the companion controller does not get the 2727 * device until after its initial bus explore, so the reference dropped 2728 * after the first explore is not enough. 5 seconds should be enough, 2729 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2730 * 2731 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2732 * if the callback is scheduled. CO_DONE is set when the callout has 2733 * called config_pending_decr(). 2734 * 2735 * There's a mutex, a cv and a callout here, and we delay detach if the 2736 * callout has been set. 2737 */ 2738 #ifndef EHCI_DISOWN_DELAY_SECONDS 2739 #define EHCI_DISOWN_DELAY_SECONDS 5 2740 #endif 2741 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2742 2743 static void 2744 ehci_disown_callback(void *arg) 2745 { 2746 ehci_softc_t *sc = arg; 2747 2748 config_pending_decr(sc->sc_dev); 2749 2750 mutex_enter(&sc->sc_complock); 2751 KASSERT(sc->sc_comp_state == CO_SCHED); 2752 sc->sc_comp_state = CO_DONE; 2753 cv_signal(&sc->sc_compcv); 2754 mutex_exit(&sc->sc_complock); 2755 } 2756 2757 static void 2758 ehci_disown_sched_callback(ehci_softc_t *sc) 2759 { 2760 extern bool root_is_mounted; 2761 2762 mutex_enter(&sc->sc_complock); 2763 2764 if (root_is_mounted || 2765 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2766 sc->sc_comp_state != CO_EARLY) { 2767 mutex_exit(&sc->sc_complock); 2768 return; 2769 } 2770 2771 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2772 ehci_disown_callback, &sc->sc_dev); 2773 sc->sc_comp_state = CO_SCHED; 2774 2775 mutex_exit(&sc->sc_complock); 2776 2777 config_pending_incr(sc->sc_dev); 2778 aprint_normal_dev(sc->sc_dev, 2779 "delaying %s by %u seconds due to USB owner change.\n", 2780 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user", 2781 ehci_disown_delay_seconds); 2782 } 2783 2784 Static void 2785 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2786 { 2787 int port; 2788 uint32_t v; 2789 2790 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2791 2792 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2793 if (sc->sc_npcomp != 0) { 2794 int i = (index-1) / sc->sc_npcomp; 2795 if (i < sc->sc_ncomp) { 2796 ehci_disown_sched_callback(sc); 2797 #ifdef DIAGNOSTIC 2798 printf("%s: handing over %s speed device on " 2799 "port %d to %s\n", 2800 device_xname(sc->sc_dev), 2801 lowspeed ? "low" : "full", 2802 index, sc->sc_comps[i] ? 2803 device_xname(sc->sc_comps[i]) : 2804 "companion controller"); 2805 } else { 2806 printf("%s: strange port\n", 2807 device_xname(sc->sc_dev)); 2808 #endif 2809 } 2810 } else { 2811 #ifdef DIAGNOSTIC 2812 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2813 #endif 2814 } 2815 port = EHCI_PORTSC(index); 2816 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2817 EOWRITE4(sc, port, v | EHCI_PS_PO); 2818 } 2819 2820 Static usbd_status 2821 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2822 { 2823 2824 /* Pipe isn't running, start first */ 2825 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2826 } 2827 2828 Static usbd_status 2829 ehci_root_intr_start(struct usbd_xfer *xfer) 2830 { 2831 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2832 2833 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2834 2835 if (sc->sc_dying) 2836 return USBD_IOERROR; 2837 2838 KASSERT(sc->sc_intrxfer == NULL); 2839 sc->sc_intrxfer = xfer; 2840 xfer->ux_status = USBD_IN_PROGRESS; 2841 2842 return USBD_IN_PROGRESS; 2843 } 2844 2845 /* Abort a root interrupt request. */ 2846 Static void 2847 ehci_root_intr_abort(struct usbd_xfer *xfer) 2848 { 2849 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2850 2851 KASSERT(mutex_owned(&sc->sc_lock)); 2852 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2853 2854 /* If xfer has already completed, nothing to do here. */ 2855 if (sc->sc_intrxfer == NULL) 2856 return; 2857 2858 /* 2859 * Otherwise, sc->sc_intrxfer had better be this transfer. 2860 * Cancel it. 2861 */ 2862 KASSERT(sc->sc_intrxfer == xfer); 2863 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2864 xfer->ux_status = USBD_CANCELLED; 2865 usb_transfer_complete(xfer); 2866 } 2867 2868 /* Close the root pipe. */ 2869 Static void 2870 ehci_root_intr_close(struct usbd_pipe *pipe) 2871 { 2872 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2873 2874 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2875 2876 KASSERT(mutex_owned(&sc->sc_lock)); 2877 2878 /* 2879 * Caller must guarantee the xfer has completed first, by 2880 * closing the pipe only after normal completion or an abort. 2881 */ 2882 KASSERT(sc->sc_intrxfer == NULL); 2883 } 2884 2885 Static void 2886 ehci_root_intr_done(struct usbd_xfer *xfer) 2887 { 2888 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2889 2890 KASSERT(mutex_owned(&sc->sc_lock)); 2891 2892 /* Claim the xfer so it doesn't get completed again. */ 2893 KASSERT(sc->sc_intrxfer == xfer); 2894 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2895 sc->sc_intrxfer = NULL; 2896 } 2897 2898 /************************/ 2899 2900 Static ehci_soft_qh_t * 2901 ehci_alloc_sqh(ehci_softc_t *sc) 2902 { 2903 ehci_soft_qh_t *sqh; 2904 2905 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2906 2907 mutex_enter(&sc->sc_lock); 2908 if (sc->sc_freeqhs == NULL) { 2909 DPRINTF("allocating chunk", 0, 0, 0, 0); 2910 mutex_exit(&sc->sc_lock); 2911 2912 /* 2913 * We can avoid USBMALLOC_COHERENT as the QHs are each on a 2914 * cacheline. 2915 */ 2916 usb_dma_t dma; 2917 int err = usb_allocmem(sc->sc_dmatag, 2918 EHCI_QH_SIZE * EHCI_QH_CHUNK, 2919 EHCI_PAGE_SIZE, 0, &dma); 2920 2921 if (err) { 2922 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2923 return NULL; 2924 } 2925 2926 ehci_soft_qh_t *sqhs = 2927 kmem_zalloc(sizeof(*sqh) * EHCI_QH_CHUNK, KM_SLEEP); 2928 2929 mutex_enter(&sc->sc_lock); 2930 for (size_t i = 0; i < EHCI_QH_CHUNK; i++) { 2931 const int offs = i * EHCI_QH_SIZE; 2932 const bus_addr_t baddr = DMAADDR(&dma, offs); 2933 2934 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2935 2936 sqh = &sqhs[i]; 2937 sqh->qh = KERNADDR(&dma, offs); 2938 sqh->physaddr = BUS_ADDR_LO32(baddr); 2939 sqh->dma = dma; 2940 sqh->offs = offs; 2941 2942 sqh->next = sc->sc_freeqhs; 2943 sc->sc_freeqhs = sqh; 2944 } 2945 } 2946 sqh = sc->sc_freeqhs; 2947 sc->sc_freeqhs = sqh->next; 2948 mutex_exit(&sc->sc_lock); 2949 2950 memset(sqh->qh, 0, sizeof(*sqh->qh)); 2951 sqh->next = NULL; 2952 return sqh; 2953 } 2954 2955 Static void 2956 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2957 { 2958 KASSERT(mutex_owned(&sc->sc_lock)); 2959 2960 sqh->next = sc->sc_freeqhs; 2961 sc->sc_freeqhs = sqh; 2962 } 2963 2964 Static ehci_soft_qtd_t * 2965 ehci_alloc_sqtd(ehci_softc_t *sc) 2966 { 2967 ehci_soft_qtd_t *sqtd = NULL; 2968 2969 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2970 2971 mutex_enter(&sc->sc_lock); 2972 if (sc->sc_freeqtds == NULL) { 2973 DPRINTF("allocating chunk", 0, 0, 0, 0); 2974 mutex_exit(&sc->sc_lock); 2975 2976 usb_dma_t dma; 2977 /* 2978 * We can avoid USBMALLOC_COHERENT as the QTDs are each on a 2979 * cacheline. 2980 */ 2981 int err = usb_allocmem(sc->sc_dmatag, 2982 EHCI_QTD_SIZE * EHCI_QTD_CHUNK, 2983 EHCI_PAGE_SIZE, 0, &dma); 2984 2985 if (err) { 2986 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2987 return NULL; 2988 } 2989 2990 ehci_soft_qtd_t *sqtds = 2991 kmem_zalloc(sizeof(*sqtd) * EHCI_QTD_CHUNK, KM_SLEEP); 2992 2993 mutex_enter(&sc->sc_lock); 2994 for (size_t i = 0; i < EHCI_QTD_CHUNK; i++) { 2995 const int offs = i * EHCI_QTD_SIZE; 2996 const bus_addr_t baddr = DMAADDR(&dma, offs); 2997 2998 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2999 3000 sqtd = &sqtds[i]; 3001 sqtd->qtd = KERNADDR(&dma, offs); 3002 sqtd->physaddr = BUS_ADDR_LO32(baddr); 3003 sqtd->dma = dma; 3004 sqtd->offs = offs; 3005 3006 sqtd->nextqtd = sc->sc_freeqtds; 3007 sc->sc_freeqtds = sqtd; 3008 } 3009 } 3010 3011 sqtd = sc->sc_freeqtds; 3012 sc->sc_freeqtds = sqtd->nextqtd; 3013 mutex_exit(&sc->sc_lock); 3014 3015 memset(sqtd->qtd, 0, sizeof(*sqtd->qtd)); 3016 sqtd->nextqtd = NULL; 3017 sqtd->xfer = NULL; 3018 3019 return sqtd; 3020 } 3021 3022 Static void 3023 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 3024 { 3025 3026 mutex_enter(&sc->sc_lock); 3027 sqtd->nextqtd = sc->sc_freeqtds; 3028 sc->sc_freeqtds = sqtd; 3029 mutex_exit(&sc->sc_lock); 3030 } 3031 3032 Static int 3033 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3034 int alen, int rd, ehci_soft_qtd_t **sp) 3035 { 3036 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3037 uint16_t flags = xfer->ux_flags; 3038 3039 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3040 3041 ASSERT_SLEEPABLE(); 3042 KASSERT(sp); 3043 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 3044 3045 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 3046 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 3047 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 3048 KM_SLEEP); 3049 exfer->ex_nsqtd = nsqtd; 3050 3051 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 3052 alen, nsqtd, flags); 3053 3054 for (size_t j = 0; j < exfer->ex_nsqtd;) { 3055 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 3056 if (cur == NULL) 3057 goto nomem; 3058 exfer->ex_sqtds[j++] = cur; 3059 3060 cur->xfer = xfer; 3061 cur->len = 0; 3062 3063 } 3064 3065 *sp = exfer->ex_sqtds[0]; 3066 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 3067 3068 return 0; 3069 3070 nomem: 3071 ehci_free_sqtds(sc, exfer); 3072 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 3073 DPRINTF("no memory", 0, 0, 0, 0); 3074 return ENOMEM; 3075 } 3076 3077 Static void 3078 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 3079 { 3080 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3081 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 3082 3083 mutex_enter(&sc->sc_lock); 3084 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 3085 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 3086 3087 if (sqtd == NULL) 3088 break; 3089 3090 sqtd->nextqtd = sc->sc_freeqtds; 3091 sc->sc_freeqtds = sqtd; 3092 } 3093 mutex_exit(&sc->sc_lock); 3094 } 3095 3096 Static void 3097 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 3098 { 3099 if (prev) { 3100 prev->nextqtd = sqtd; 3101 prev->qtd->qtd_next = htole32(sqtd->physaddr); 3102 prev->qtd->qtd_altnext = prev->qtd->qtd_next; 3103 usb_syncmem(&prev->dma, prev->offs, sizeof(*prev->qtd), 3104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3105 } 3106 } 3107 3108 Static void 3109 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3110 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3111 { 3112 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3113 usb_dma_t *dma = &xfer->ux_dmabuf; 3114 uint16_t flags = xfer->ux_flags; 3115 ehci_soft_qtd_t *sqtd, *prev; 3116 int tog = *toggle; 3117 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3118 int len = length; 3119 3120 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3121 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 3122 len, isread, tog); 3123 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 3124 0, 0, 0); 3125 3126 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 3127 3128 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3129 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3130 EHCI_QTD_SET_CERR(3) 3131 ; 3132 3133 sqtd = prev = NULL; 3134 size_t curoffs = 0; 3135 size_t j = 0; 3136 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3137 sqtd = exfer->ex_sqtds[j++]; 3138 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3139 (uintptr_t)prev, 0); 3140 3141 /* 3142 * The EHCI hardware can handle at most 5 pages and they do 3143 * not have to be contiguous 3144 */ 3145 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3146 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3147 size_t curlen = len; 3148 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3149 /* must use multiple TDs, fill as much as possible. */ 3150 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3151 3152 /* the length must be a multiple of the max size */ 3153 curlen -= curlen % mps; 3154 } 3155 KASSERT(curlen != 0); 3156 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3157 curoffs, 0); 3158 3159 /* Fill the qTD */ 3160 sqtd->qtd->qtd_next = sqtd->qtd->qtd_altnext = EHCI_NULL; 3161 sqtd->qtd->qtd_status = htole32( 3162 qtdstatus | 3163 EHCI_QTD_SET_BYTES(curlen) | 3164 EHCI_QTD_SET_TOGGLE(tog)); 3165 3166 /* Find number of pages we'll be using, insert dma addresses */ 3167 size_t pages = EHCI_NPAGES(curlen); 3168 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3169 size_t pageoffs = EHCI_PAGE(curoffs); 3170 for (size_t i = 0; i < pages; i++) { 3171 paddr_t a = EHCI_PAGE(DMAADDR(dma, 3172 pageoffs + i * EHCI_PAGE_SIZE)); 3173 sqtd->qtd->qtd_buffer[i] = htole32(BUS_ADDR_LO32(a)); 3174 sqtd->qtd->qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a)); 3175 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3176 i, pages, 3177 le32toh(sqtd->qtd->qtd_buffer_hi[i]), 3178 le32toh(sqtd->qtd->qtd_buffer[i])); 3179 } 3180 /* First buffer pointer requires a page offset to start at */ 3181 sqtd->qtd->qtd_buffer[0] |= htole32(va_offs); 3182 3183 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 3184 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3185 3186 sqtd->len = curlen; 3187 3188 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3189 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3190 3191 ehci_append_sqtd(sqtd, prev); 3192 3193 if (howmany(curlen, mps) & 1) { 3194 tog ^= 1; 3195 } 3196 3197 curoffs += curlen; 3198 len -= curlen; 3199 } 3200 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3201 xfer, length, len, mps, exfer->ex_nsqtd, j); 3202 3203 if (!isread && 3204 (flags & USBD_FORCE_SHORT_XFER) && 3205 length % mps == 0) { 3206 /* Force a 0 length transfer at the end. */ 3207 3208 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3209 exfer->ex_nsqtd); 3210 prev = sqtd; 3211 sqtd = exfer->ex_sqtds[j++]; 3212 memset(sqtd->qtd, 0, sizeof(*sqtd->qtd)); 3213 sqtd->qtd->qtd_next = sqtd->qtd->qtd_altnext = EHCI_NULL; 3214 sqtd->qtd->qtd_status = htole32( 3215 qtdstatus | 3216 EHCI_QTD_SET_BYTES(0) | 3217 EHCI_QTD_SET_TOGGLE(tog)); 3218 3219 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 3220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3221 3222 ehci_append_sqtd(sqtd, prev); 3223 tog ^= 1; 3224 } 3225 3226 *lsqtd = sqtd; 3227 *toggle = tog; 3228 } 3229 3230 Static ehci_soft_itd_t * 3231 ehci_alloc_itd(ehci_softc_t *sc) 3232 { 3233 struct ehci_soft_itd *itd, *freeitd; 3234 3235 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3236 3237 mutex_enter(&sc->sc_lock); 3238 3239 freeitd = LIST_FIRST(&sc->sc_freeitds); 3240 if (freeitd == NULL) { 3241 DPRINTF("allocating chunk", 0, 0, 0, 0); 3242 mutex_exit(&sc->sc_lock); 3243 3244 usb_dma_t dma; 3245 /* 3246 * We can avoid USBMALLOC_COHERENT as the ITDs are each on a 3247 * cacheline. 3248 */ 3249 int err = usb_allocmem(sc->sc_dmatag, 3250 EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3251 EHCI_PAGE_SIZE, 0, &dma); 3252 3253 if (err) { 3254 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3255 return NULL; 3256 } 3257 3258 struct ehci_soft_itd *itds = 3259 kmem_alloc(sizeof(*itd) * EHCI_ITD_CHUNK, KM_SLEEP); 3260 3261 mutex_enter(&sc->sc_lock); 3262 for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) { 3263 const int offs = i * EHCI_ITD_SIZE; 3264 const bus_addr_t baddr = DMAADDR(&dma, offs); 3265 3266 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3267 3268 itd = &itds[i]; 3269 itd->itd = KERNADDR(&dma, offs); 3270 itd->physaddr = BUS_ADDR_LO32(baddr); 3271 itd->dma = dma; 3272 itd->offs = offs; 3273 3274 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3275 } 3276 freeitd = LIST_FIRST(&sc->sc_freeitds); 3277 } 3278 3279 itd = freeitd; 3280 LIST_REMOVE(itd, free_list); 3281 mutex_exit(&sc->sc_lock); 3282 memset(itd->itd, 0, sizeof(*itd->itd)); 3283 3284 itd->frame_list.next = NULL; 3285 itd->frame_list.prev = NULL; 3286 itd->xfer_next = NULL; 3287 itd->slot = 0; 3288 3289 return itd; 3290 } 3291 3292 Static ehci_soft_sitd_t * 3293 ehci_alloc_sitd(ehci_softc_t *sc) 3294 { 3295 struct ehci_soft_sitd *sitd, *freesitd; 3296 3297 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3298 3299 mutex_enter(&sc->sc_lock); 3300 freesitd = LIST_FIRST(&sc->sc_freesitds); 3301 if (freesitd == NULL) { 3302 DPRINTF("allocating chunk", 0, 0, 0, 0); 3303 mutex_exit(&sc->sc_lock); 3304 3305 usb_dma_t dma; 3306 3307 /* 3308 * We can avoid USBMALLOC_COHERENT as the SITDs are each on a 3309 * cacheline. 3310 */ 3311 int err = usb_allocmem(sc->sc_dmatag, 3312 EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3313 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3314 3315 if (err) { 3316 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3317 return NULL; 3318 } 3319 struct ehci_soft_sitd *sitds = 3320 kmem_alloc(sizeof(*sitd) * EHCI_SITD_CHUNK, KM_SLEEP); 3321 3322 mutex_enter(&sc->sc_lock); 3323 for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) { 3324 const int offs = i * EHCI_SITD_SIZE; 3325 const bus_addr_t baddr = DMAADDR(&dma, offs); 3326 3327 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3328 3329 sitd = &sitds[i]; 3330 sitd->itd = KERNADDR(&dma, offs); 3331 sitd->physaddr = BUS_ADDR_LO32(baddr); 3332 sitd->dma = dma; 3333 sitd->offs = offs; 3334 3335 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3336 } 3337 freesitd = LIST_FIRST(&sc->sc_freesitds); 3338 } 3339 3340 sitd = freesitd; 3341 LIST_REMOVE(sitd, free_list); 3342 mutex_exit(&sc->sc_lock); 3343 3344 memset(sitd->sitd, 0, sizeof(*sitd->sitd)); 3345 3346 sitd->frame_list.next = NULL; 3347 sitd->frame_list.prev = NULL; 3348 sitd->xfer_next = NULL; 3349 sitd->slot = 0; 3350 3351 return sitd; 3352 } 3353 3354 /****************/ 3355 3356 /* 3357 * Close a regular pipe. 3358 * Assumes that there are no pending transactions. 3359 */ 3360 Static void 3361 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3362 { 3363 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3364 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3365 ehci_soft_qh_t *sqh = epipe->sqh; 3366 3367 KASSERT(mutex_owned(&sc->sc_lock)); 3368 3369 ehci_rem_qh(sc, sqh, head); 3370 ehci_free_sqh(sc, epipe->sqh); 3371 } 3372 3373 /* 3374 * Arrange for the hardware to tells us that it is not still 3375 * processing the TDs by setting the QH halted bit and wait for the ehci 3376 * door bell 3377 */ 3378 Static void 3379 ehci_abortx(struct usbd_xfer *xfer) 3380 { 3381 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3382 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3383 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3384 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3385 ehci_soft_qh_t *sqh = epipe->sqh; 3386 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3387 ehci_physaddr_t cur; 3388 uint32_t qhstatus; 3389 int hit; 3390 3391 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3392 3393 KASSERT(mutex_owned(&sc->sc_lock)); 3394 ASSERT_SLEEPABLE(); 3395 3396 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3397 xfer->ux_status == USBD_TIMEOUT), 3398 "bad abort status: %d", xfer->ux_status); 3399 3400 /* 3401 * If we're dying, skip the hardware action and just notify the 3402 * software that we're done. 3403 */ 3404 if (sc->sc_dying) { 3405 goto dying; 3406 } 3407 3408 /* 3409 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3410 */ 3411 ehci_del_intr_list(sc, exfer); 3412 3413 usb_syncmem(&sqh->dma, 3414 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3415 sizeof(sqh->qh->qh_qtd.qtd_status), 3416 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3417 qhstatus = sqh->qh->qh_qtd.qtd_status; 3418 sqh->qh->qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3419 usb_syncmem(&sqh->dma, 3420 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3421 sizeof(sqh->qh->qh_qtd.qtd_status), 3422 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3423 3424 if (exfer->ex_type == EX_CTRL) { 3425 fsqtd = exfer->ex_setup; 3426 lsqtd = exfer->ex_status; 3427 } else { 3428 fsqtd = exfer->ex_sqtdstart; 3429 lsqtd = exfer->ex_sqtdend; 3430 } 3431 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3432 usb_syncmem(&sqtd->dma, 3433 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3434 sizeof(sqtd->qtd->qtd_status), 3435 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3436 sqtd->qtd->qtd_status |= htole32(EHCI_QTD_HALTED); 3437 usb_syncmem(&sqtd->dma, 3438 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3439 sizeof(sqtd->qtd->qtd_status), 3440 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3441 if (sqtd == lsqtd) 3442 break; 3443 } 3444 3445 /* 3446 * HC Step 2: Wait until we know hardware has finished any possible 3447 * use of the xfer. 3448 */ 3449 ehci_sync_hc(sc); 3450 3451 /* 3452 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3453 * The complication here is that the hardware may have executed 3454 * beyond the xfer we're trying to abort. So as we're scanning 3455 * the TDs of this xfer we check if the hardware points to 3456 * any of them. 3457 */ 3458 3459 usb_syncmem(&sqh->dma, 3460 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3461 sizeof(sqh->qh->qh_curqtd), 3462 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3463 cur = EHCI_LINK_ADDR(le32toh(sqh->qh->qh_curqtd)); 3464 hit = 0; 3465 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3466 hit |= cur == sqtd->physaddr; 3467 if (sqtd == lsqtd) 3468 break; 3469 } 3470 sqtd = sqtd->nextqtd; 3471 /* Zap curqtd register if hardware pointed inside the xfer. */ 3472 if (hit && sqtd != NULL) { 3473 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3474 sqh->qh->qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3475 usb_syncmem(&sqh->dma, 3476 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3477 sizeof(sqh->qh->qh_curqtd), 3478 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3479 sqh->qh->qh_qtd.qtd_status = qhstatus; 3480 usb_syncmem(&sqh->dma, 3481 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3482 sizeof(sqh->qh->qh_qtd.qtd_status), 3483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3484 } else { 3485 DPRINTF("no hit", 0, 0, 0, 0); 3486 usb_syncmem(&sqh->dma, 3487 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3488 sizeof(sqh->qh->qh_curqtd), 3489 BUS_DMASYNC_PREREAD); 3490 } 3491 3492 dying: 3493 #ifdef DIAGNOSTIC 3494 exfer->ex_isdone = true; 3495 #endif 3496 DPRINTFN(14, "end", 0, 0, 0, 0); 3497 3498 KASSERT(mutex_owned(&sc->sc_lock)); 3499 } 3500 3501 Static void 3502 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3503 { 3504 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3505 ehci_isoc_trans_t trans_status; 3506 struct ehci_xfer *exfer; 3507 ehci_softc_t *sc; 3508 struct ehci_soft_itd *itd; 3509 struct ehci_soft_sitd *sitd; 3510 int i; 3511 3512 KASSERTMSG(status == USBD_CANCELLED, 3513 "invalid status for abort: %d", (int)status); 3514 3515 exfer = EHCI_XFER2EXFER(xfer); 3516 sc = EHCI_XFER2SC(xfer); 3517 3518 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3519 (uintptr_t)xfer->ux_pipe, 0, 0); 3520 3521 KASSERT(mutex_owned(&sc->sc_lock)); 3522 ASSERT_SLEEPABLE(); 3523 3524 /* No timeout or task here. */ 3525 3526 /* 3527 * The xfer cannot have been cancelled already. It is the 3528 * responsibility of the caller of usbd_abort_pipe not to try 3529 * to abort a pipe multiple times, whether concurrently or 3530 * sequentially. 3531 */ 3532 KASSERT(xfer->ux_status != USBD_CANCELLED); 3533 3534 /* If anyone else beat us, we're done. */ 3535 if (xfer->ux_status != USBD_IN_PROGRESS) 3536 return; 3537 3538 /* We beat everyone else. Claim the status. */ 3539 xfer->ux_status = status; 3540 3541 /* 3542 * If we're dying, skip the hardware action and just notify the 3543 * software that we're done. 3544 */ 3545 if (sc->sc_dying) { 3546 goto dying; 3547 } 3548 3549 /* 3550 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3551 */ 3552 ehci_del_intr_list(sc, exfer); 3553 3554 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3555 for (itd = exfer->ex_itdstart; itd != NULL; 3556 itd = itd->xfer_next) { 3557 usb_syncmem(&itd->dma, 3558 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3559 sizeof(itd->itd->itd_ctl), 3560 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3561 3562 for (i = 0; i < 8; i++) { 3563 trans_status = le32toh(itd->itd->itd_ctl[i]); 3564 trans_status &= ~EHCI_ITD_ACTIVE; 3565 itd->itd->itd_ctl[i] = htole32(trans_status); 3566 } 3567 3568 usb_syncmem(&itd->dma, 3569 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3570 sizeof(itd->itd->itd_ctl), 3571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3572 } 3573 } else { 3574 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3575 sitd = sitd->xfer_next) { 3576 usb_syncmem(&sitd->dma, 3577 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3578 sizeof(sitd->sitd->sitd_buffer), 3579 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3580 3581 trans_status = le32toh(sitd->sitd->sitd_trans); 3582 trans_status &= ~EHCI_SITD_ACTIVE; 3583 sitd->sitd->sitd_trans = htole32(trans_status); 3584 3585 usb_syncmem(&sitd->dma, 3586 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3587 sizeof(sitd->sitd->sitd_buffer), 3588 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3589 } 3590 } 3591 3592 dying: 3593 #ifdef DIAGNOSTIC 3594 exfer->ex_isdone = true; 3595 #endif 3596 usb_transfer_complete(xfer); 3597 DPRINTFN(14, "end", 0, 0, 0, 0); 3598 3599 KASSERT(mutex_owned(&sc->sc_lock)); 3600 } 3601 3602 /************************/ 3603 3604 Static int 3605 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3606 { 3607 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3608 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3609 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3610 usb_device_request_t *req = &xfer->ux_request; 3611 ehci_soft_qtd_t *setup, *status, *next; 3612 int isread = req->bmRequestType & UT_READ; 3613 int len = xfer->ux_bufsize; 3614 int err; 3615 3616 exfer->ex_type = EX_CTRL; 3617 exfer->ex_status = NULL; 3618 exfer->ex_data = NULL; 3619 exfer->ex_setup = ehci_alloc_sqtd(sc); 3620 if (exfer->ex_setup == NULL) { 3621 err = ENOMEM; 3622 goto bad1; 3623 } 3624 exfer->ex_status = ehci_alloc_sqtd(sc); 3625 if (exfer->ex_status == NULL) { 3626 err = ENOMEM; 3627 goto bad2; 3628 } 3629 setup = exfer->ex_setup; 3630 status = exfer->ex_status; 3631 exfer->ex_nsqtd = 0; 3632 next = status; 3633 /* Set up data transaction */ 3634 if (len != 0) { 3635 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3636 &exfer->ex_data); 3637 if (err) 3638 goto bad3; 3639 next = exfer->ex_data; 3640 } 3641 3642 /* Clear toggle */ 3643 setup->qtd->qtd_status = htole32( 3644 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3645 EHCI_QTD_SET_TOGGLE(0) | 3646 EHCI_QTD_SET_BYTES(sizeof(*req)) 3647 ); 3648 3649 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3650 setup->qtd->qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3651 setup->qtd->qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3652 setup->qtd->qtd_next = setup->qtd->qtd_altnext = htole32(next->physaddr); 3653 setup->nextqtd = next; 3654 setup->xfer = xfer; 3655 setup->len = sizeof(*req); 3656 3657 status->qtd->qtd_status = htole32( 3658 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3659 EHCI_QTD_SET_TOGGLE(1) | 3660 EHCI_QTD_IOC 3661 ); 3662 status->qtd->qtd_buffer[0] = 0; 3663 status->qtd->qtd_buffer_hi[0] = 0; 3664 status->qtd->qtd_next = status->qtd->qtd_altnext = EHCI_NULL; 3665 status->nextqtd = NULL; 3666 status->xfer = xfer; 3667 status->len = 0; 3668 3669 return 0; 3670 bad3: 3671 ehci_free_sqtd(sc, exfer->ex_status); 3672 bad2: 3673 ehci_free_sqtd(sc, exfer->ex_setup); 3674 bad1: 3675 return err; 3676 } 3677 3678 Static void 3679 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3680 { 3681 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3682 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3683 3684 KASSERT(ex->ex_type == EX_CTRL); 3685 3686 ehci_free_sqtd(sc, ex->ex_setup); 3687 ehci_free_sqtd(sc, ex->ex_status); 3688 ehci_free_sqtds(sc, ex); 3689 if (ex->ex_nsqtd) 3690 kmem_free(ex->ex_sqtds, 3691 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3692 } 3693 3694 Static usbd_status 3695 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3696 { 3697 3698 /* Pipe isn't running, start first */ 3699 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3700 } 3701 3702 Static usbd_status 3703 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3704 { 3705 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3706 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3707 usb_device_request_t *req = &xfer->ux_request; 3708 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3709 ehci_soft_qtd_t *setup, *status, *next; 3710 ehci_soft_qh_t *sqh; 3711 3712 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3713 3714 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3715 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3716 3717 if (sc->sc_dying) 3718 return USBD_IOERROR; 3719 3720 const int isread = req->bmRequestType & UT_READ; 3721 const int len = UGETW(req->wLength); 3722 3723 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3724 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3725 UGETW(req->wIndex)); 3726 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3727 len, epipe->pipe.up_dev->ud_addr, 3728 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3729 3730 sqh = epipe->sqh; 3731 3732 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh->qh_endp)) == epipe->pipe.up_dev->ud_addr, 3733 "address QH %" __PRIuBIT " pipe %d\n", 3734 EHCI_QH_GET_ADDR(le32toh(sqh->qh->qh_endp)), 3735 epipe->pipe.up_dev->ud_addr); 3736 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh->qh_endp)) == 3737 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3738 "MPS QH %" __PRIuBIT " pipe %d\n", 3739 EHCI_QH_GET_MPL(le32toh(sqh->qh->qh_endp)), 3740 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3741 3742 setup = exfer->ex_setup; 3743 status = exfer->ex_status; 3744 3745 DPRINTF("setup %#jx status %#jx data %#jx", 3746 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3747 KASSERTMSG(setup != NULL && status != NULL, 3748 "Failed memory allocation, setup %p status %p", 3749 setup, status); 3750 3751 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3752 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3753 3754 /* Clear toggle */ 3755 setup->qtd->qtd_status &= ~htole32( 3756 EHCI_QTD_STATUS_MASK | 3757 EHCI_QTD_BYTES_MASK | 3758 EHCI_QTD_TOGGLE_MASK | 3759 EHCI_QTD_CERR_MASK 3760 ); 3761 setup->qtd->qtd_status |= htole32( 3762 EHCI_QTD_ACTIVE | 3763 EHCI_QTD_SET_CERR(3) | 3764 EHCI_QTD_SET_TOGGLE(0) | 3765 EHCI_QTD_SET_BYTES(sizeof(*req)) 3766 ); 3767 3768 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3769 setup->qtd->qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3770 setup->qtd->qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3771 3772 next = status; 3773 status->qtd->qtd_status &= ~htole32( 3774 EHCI_QTD_STATUS_MASK | 3775 EHCI_QTD_PID_MASK | 3776 EHCI_QTD_BYTES_MASK | 3777 EHCI_QTD_TOGGLE_MASK | 3778 EHCI_QTD_CERR_MASK 3779 ); 3780 status->qtd->qtd_status |= htole32( 3781 EHCI_QTD_ACTIVE | 3782 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3783 EHCI_QTD_SET_CERR(3) | 3784 EHCI_QTD_SET_TOGGLE(1) | 3785 EHCI_QTD_SET_BYTES(0) | 3786 EHCI_QTD_IOC 3787 ); 3788 KASSERT(status->qtd->qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3789 3790 KASSERT(exfer->ex_isdone); 3791 #ifdef DIAGNOSTIC 3792 exfer->ex_isdone = false; 3793 #endif 3794 3795 /* Set up data transaction */ 3796 if (len != 0) { 3797 ehci_soft_qtd_t *end; 3798 3799 /* Start toggle at 1. */ 3800 int toggle = 1; 3801 next = exfer->ex_data; 3802 KASSERTMSG(next != NULL, "Failed memory allocation"); 3803 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3804 end->nextqtd = status; 3805 end->qtd->qtd_next = end->qtd->qtd_altnext = 3806 htole32(status->physaddr); 3807 3808 usb_syncmem(&end->dma, end->offs, sizeof(*end->qtd), 3809 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3810 3811 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3812 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3813 } 3814 3815 setup->nextqtd = next; 3816 setup->qtd->qtd_next = setup->qtd->qtd_altnext = htole32(next->physaddr); 3817 3818 usb_syncmem(&setup->dma, setup->offs, sizeof(*setup->qtd), 3819 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3820 3821 usb_syncmem(&status->dma, status->offs, sizeof(*status->qtd), 3822 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3823 3824 KASSERT(status->qtd->qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3825 3826 #ifdef EHCI_DEBUG 3827 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3828 ehci_dump_sqh(sqh); 3829 ehci_dump_sqtds(setup); 3830 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3831 #endif 3832 3833 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3834 ehci_set_qh_qtd(sqh, setup); 3835 ehci_add_intr_list(sc, exfer); 3836 xfer->ux_status = USBD_IN_PROGRESS; 3837 usbd_xfer_schedule_timeout(xfer); 3838 3839 #if 0 3840 #ifdef EHCI_DEBUG 3841 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3842 // delay(10000); 3843 ehci_dump_regs(sc); 3844 ehci_dump_sqh(sc->sc_async_head); 3845 ehci_dump_sqh(sqh); 3846 ehci_dump_sqtds(setup); 3847 #endif 3848 #endif 3849 3850 return USBD_IN_PROGRESS; 3851 } 3852 3853 Static void 3854 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3855 { 3856 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3857 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3858 usb_device_request_t *req = &xfer->ux_request; 3859 int len = UGETW(req->wLength); 3860 int rd = req->bmRequestType & UT_READ; 3861 3862 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3863 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3864 3865 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3866 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3867 3868 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3869 BUS_DMASYNC_POSTWRITE); 3870 if (len) 3871 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3872 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3873 3874 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3875 } 3876 3877 /* Abort a device control request. */ 3878 Static void 3879 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3880 { 3881 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3882 3883 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3884 usbd_xfer_abort(xfer); 3885 } 3886 3887 /* Close a device control pipe. */ 3888 Static void 3889 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3890 { 3891 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3892 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3893 3894 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3895 3896 KASSERT(mutex_owned(&sc->sc_lock)); 3897 3898 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3899 3900 ehci_close_pipe(pipe, sc->sc_async_head); 3901 3902 usb_freemem(&epipe->ctrl.reqdma); 3903 } 3904 3905 /* 3906 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3907 * qTD status, or miss signalling occasionally under heavy load. If the host 3908 * machine is too fast, we can miss transaction completion - when we scan 3909 * the active list the transaction still seems to be active. This generally 3910 * exhibits itself as a umass stall that never recovers. 3911 * 3912 * We work around this behaviour by setting up this callback after any softintr 3913 * that completes with transactions still pending, giving us another chance to 3914 * check for completion after the writeback has taken place. 3915 */ 3916 Static void 3917 ehci_intrlist_timeout(void *arg) 3918 { 3919 ehci_softc_t *sc = arg; 3920 3921 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3922 3923 usb_schedsoftintr(&sc->sc_bus); 3924 } 3925 3926 /************************/ 3927 3928 Static int 3929 ehci_device_bulk_init(struct usbd_xfer *xfer) 3930 { 3931 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3932 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3933 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3934 int endpt = ed->bEndpointAddress; 3935 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3936 int len = xfer->ux_bufsize; 3937 int err = 0; 3938 3939 exfer->ex_type = EX_BULK; 3940 exfer->ex_nsqtd = 0; 3941 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3942 &exfer->ex_sqtdstart); 3943 3944 return err; 3945 } 3946 3947 Static void 3948 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3949 { 3950 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3951 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3952 3953 KASSERT(ex->ex_type == EX_BULK); 3954 3955 ehci_free_sqtds(sc, ex); 3956 if (ex->ex_nsqtd) 3957 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3958 } 3959 3960 Static usbd_status 3961 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3962 { 3963 3964 /* Pipe isn't running, start first */ 3965 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3966 } 3967 3968 Static usbd_status 3969 ehci_device_bulk_start(struct usbd_xfer *xfer) 3970 { 3971 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3972 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3973 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3974 ehci_soft_qh_t *sqh; 3975 ehci_soft_qtd_t *end; 3976 int len, isread, endpt; 3977 3978 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3979 3980 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3981 xfer->ux_flags, 0); 3982 3983 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3984 3985 if (sc->sc_dying) 3986 return USBD_IOERROR; 3987 3988 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3989 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3990 3991 len = xfer->ux_length; 3992 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3993 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3994 sqh = epipe->sqh; 3995 3996 KASSERT(exfer->ex_isdone); 3997 #ifdef DIAGNOSTIC 3998 exfer->ex_isdone = false; 3999 #endif 4000 4001 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4002 4003 exfer->ex_sqtdend = end; 4004 end->qtd->qtd_status |= htole32(EHCI_QTD_IOC); 4005 usb_syncmem(&end->dma, end->offs, sizeof(*end->qtd), 4006 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4007 4008 #ifdef EHCI_DEBUG 4009 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4010 ehci_dump_sqh(sqh); 4011 ehci_dump_sqtds(exfer->ex_sqtdstart); 4012 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4013 #endif 4014 4015 if (xfer->ux_length) 4016 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4017 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4018 4019 /* also does usb_syncmem(sqh) */ 4020 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4021 ehci_add_intr_list(sc, exfer); 4022 xfer->ux_status = USBD_IN_PROGRESS; 4023 usbd_xfer_schedule_timeout(xfer); 4024 4025 #if 0 4026 #ifdef EHCI_DEBUG 4027 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4028 // delay(10000); 4029 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4030 ehci_dump_regs(sc); 4031 #if 0 4032 printf("async_head:\n"); 4033 ehci_dump_sqh(sc->sc_async_head); 4034 #endif 4035 DPRINTF("sqh:", 0, 0, 0, 0); 4036 ehci_dump_sqh(sqh); 4037 ehci_dump_sqtds(exfer->ex_sqtdstart); 4038 #endif 4039 #endif 4040 4041 return USBD_IN_PROGRESS; 4042 } 4043 4044 Static void 4045 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4046 { 4047 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4048 4049 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 4050 usbd_xfer_abort(xfer); 4051 } 4052 4053 /* 4054 * Close a device bulk pipe. 4055 */ 4056 Static void 4057 ehci_device_bulk_close(struct usbd_pipe *pipe) 4058 { 4059 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4060 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4061 4062 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4063 4064 KASSERT(mutex_owned(&sc->sc_lock)); 4065 4066 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4067 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4068 ehci_close_pipe(pipe, sc->sc_async_head); 4069 } 4070 4071 Static void 4072 ehci_device_bulk_done(struct usbd_xfer *xfer) 4073 { 4074 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4075 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4076 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4077 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4078 4079 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4080 4081 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4082 4083 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4084 4085 if (xfer->ux_length) 4086 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4087 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4088 4089 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4090 } 4091 4092 /************************/ 4093 4094 Static usbd_status 4095 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4096 { 4097 struct ehci_soft_islot *isp; 4098 int islot, lev; 4099 4100 /* Find a poll rate that is large enough. */ 4101 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4102 if (EHCI_ILEV_IVAL(lev) <= ival) 4103 break; 4104 4105 /* Pick an interrupt slot at the right level. */ 4106 /* XXX could do better than picking at random */ 4107 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4108 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4109 4110 sqh->islot = islot; 4111 isp = &sc->sc_islots[islot]; 4112 mutex_enter(&sc->sc_lock); 4113 ehci_add_qh(sc, sqh, isp->sqh); 4114 mutex_exit(&sc->sc_lock); 4115 4116 return USBD_NORMAL_COMPLETION; 4117 } 4118 4119 Static int 4120 ehci_device_intr_init(struct usbd_xfer *xfer) 4121 { 4122 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4123 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4124 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4125 int endpt = ed->bEndpointAddress; 4126 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4127 int len = xfer->ux_bufsize; 4128 int err; 4129 4130 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4131 4132 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4133 xfer->ux_flags, 0); 4134 4135 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4136 KASSERT(len != 0); 4137 4138 exfer->ex_type = EX_INTR; 4139 exfer->ex_nsqtd = 0; 4140 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4141 &exfer->ex_sqtdstart); 4142 4143 return err; 4144 } 4145 4146 Static void 4147 ehci_device_intr_fini(struct usbd_xfer *xfer) 4148 { 4149 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4150 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4151 4152 KASSERT(ex->ex_type == EX_INTR); 4153 4154 ehci_free_sqtds(sc, ex); 4155 if (ex->ex_nsqtd) 4156 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4157 } 4158 4159 Static usbd_status 4160 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4161 { 4162 4163 /* Pipe isn't running, so start it first. */ 4164 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4165 } 4166 4167 Static usbd_status 4168 ehci_device_intr_start(struct usbd_xfer *xfer) 4169 { 4170 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4171 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4172 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4173 ehci_soft_qtd_t *end; 4174 ehci_soft_qh_t *sqh; 4175 int len, isread, endpt; 4176 4177 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4178 4179 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4180 xfer->ux_flags, 0); 4181 4182 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4183 4184 if (sc->sc_dying) 4185 return USBD_IOERROR; 4186 4187 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4188 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4189 4190 len = xfer->ux_length; 4191 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4192 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4193 sqh = epipe->sqh; 4194 4195 KASSERT(exfer->ex_isdone); 4196 #ifdef DIAGNOSTIC 4197 exfer->ex_isdone = false; 4198 #endif 4199 4200 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4201 4202 end->qtd->qtd_status |= htole32(EHCI_QTD_IOC); 4203 usb_syncmem(&end->dma, end->offs, sizeof(*end->qtd), 4204 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4205 exfer->ex_sqtdend = end; 4206 4207 #ifdef EHCI_DEBUG 4208 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4209 ehci_dump_sqh(sqh); 4210 ehci_dump_sqtds(exfer->ex_sqtdstart); 4211 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4212 #endif 4213 4214 if (xfer->ux_length) 4215 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4216 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4217 4218 /* also does usb_syncmem(sqh) */ 4219 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4220 ehci_add_intr_list(sc, exfer); 4221 xfer->ux_status = USBD_IN_PROGRESS; 4222 usbd_xfer_schedule_timeout(xfer); 4223 4224 #if 0 4225 #ifdef EHCI_DEBUG 4226 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4227 // delay(10000); 4228 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4229 ehci_dump_regs(sc); 4230 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4231 ehci_dump_sqh(sqh); 4232 ehci_dump_sqtds(exfer->ex_sqtdstart); 4233 #endif 4234 #endif 4235 4236 return USBD_IN_PROGRESS; 4237 } 4238 4239 Static void 4240 ehci_device_intr_abort(struct usbd_xfer *xfer) 4241 { 4242 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4243 4244 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4245 4246 /* 4247 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4248 * async doorbell. That's dependent on the async list, whereas 4249 * intr xfers are periodic, should not use this? 4250 */ 4251 usbd_xfer_abort(xfer); 4252 } 4253 4254 Static void 4255 ehci_device_intr_close(struct usbd_pipe *pipe) 4256 { 4257 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4258 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4259 struct ehci_soft_islot *isp; 4260 4261 KASSERT(mutex_owned(&sc->sc_lock)); 4262 4263 isp = &sc->sc_islots[epipe->sqh->islot]; 4264 ehci_close_pipe(pipe, isp->sqh); 4265 } 4266 4267 Static void 4268 ehci_device_intr_done(struct usbd_xfer *xfer) 4269 { 4270 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4271 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4272 4273 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4274 4275 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4276 4277 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4278 4279 if (xfer->ux_length) { 4280 int isread, endpt; 4281 4282 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4283 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4284 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4285 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4286 } 4287 } 4288 4289 /************************/ 4290 Static int 4291 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4292 { 4293 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4294 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4295 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4296 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4297 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4298 int i, k, frames; 4299 u_int huba, dir; 4300 int err; 4301 4302 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4303 4304 start = NULL; 4305 sitd = NULL; 4306 4307 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4308 xfer->ux_flags, 0); 4309 4310 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4311 KASSERT(xfer->ux_nframes != 0); 4312 KASSERT(exfer->ex_isdone); 4313 4314 exfer->ex_type = EX_FS_ISOC; 4315 /* 4316 * Step 1: Allocate and initialize sitds. 4317 */ 4318 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4319 if (i > 16 || i == 0) { 4320 /* Spec page 271 says intervals > 16 are invalid */ 4321 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4322 return EINVAL; 4323 } 4324 4325 frames = xfer->ux_nframes; 4326 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4327 sitd = ehci_alloc_sitd(sc); 4328 if (sitd == NULL) { 4329 err = ENOMEM; 4330 goto fail; 4331 } 4332 4333 if (prev) 4334 prev->xfer_next = sitd; 4335 else 4336 start = sitd; 4337 4338 huba = dev->ud_myhsport->up_parent->ud_addr; 4339 4340 #if 0 4341 if (sc->sc_flags & EHCIF_FREESCALE) { 4342 // Set hub address to 0 if embedded TT is used. 4343 if (huba == sc->sc_addr) 4344 huba = 0; 4345 } 4346 #endif 4347 4348 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4349 dir = UE_GET_DIR(k) ? 1 : 0; 4350 sitd->sitd->sitd_endp = 4351 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4352 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4353 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4354 EHCI_SITD_SET_HUBA(huba) | 4355 EHCI_SITD_SET_DIR(dir)); 4356 4357 sitd->sitd->sitd_back = htole32(EHCI_LINK_TERMINATE); 4358 } /* End of frame */ 4359 4360 sitd->sitd->sitd_trans |= htole32(EHCI_SITD_IOC); 4361 4362 stop = sitd; 4363 stop->xfer_next = NULL; 4364 exfer->ex_sitdstart = start; 4365 exfer->ex_sitdend = stop; 4366 4367 return 0; 4368 4369 fail: 4370 mutex_enter(&sc->sc_lock); 4371 ehci_soft_sitd_t *next; 4372 for (sitd = start; sitd; sitd = next) { 4373 next = sitd->xfer_next; 4374 ehci_free_sitd_locked(sc, sitd); 4375 } 4376 mutex_exit(&sc->sc_lock); 4377 4378 return err; 4379 } 4380 4381 Static void 4382 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4383 { 4384 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4385 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4386 4387 KASSERT(ex->ex_type == EX_FS_ISOC); 4388 4389 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4390 } 4391 4392 Static usbd_status 4393 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4394 { 4395 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4396 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4397 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4398 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4399 ehci_soft_sitd_t *sitd; 4400 usb_dma_t *dma_buf; 4401 int i, j, k, frames; 4402 int offs; 4403 int frindex; 4404 u_int dir; 4405 4406 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4407 4408 sitd = NULL; 4409 4410 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4411 xfer->ux_flags, 0); 4412 4413 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4414 4415 if (sc->sc_dying) 4416 return USBD_IOERROR; 4417 4418 /* 4419 * To avoid complication, don't allow a request right now that'll span 4420 * the entire frame table. To within 4 frames, to allow some leeway 4421 * on either side of where the hc currently is. 4422 */ 4423 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4424 xfer->ux_nframes >= sc->sc_flsize - 4) { 4425 printf("ehci: isoc descriptor requested that spans the entire" 4426 " frametable, too many frames\n"); 4427 return USBD_INVAL; 4428 } 4429 4430 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4431 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4432 KASSERT(exfer->ex_isdone); 4433 #ifdef DIAGNOSTIC 4434 exfer->ex_isdone = false; 4435 #endif 4436 4437 /* 4438 * Step 1: Initialize sitds. 4439 */ 4440 4441 frames = xfer->ux_nframes; 4442 dma_buf = &xfer->ux_dmabuf; 4443 offs = 0; 4444 4445 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4446 i++, sitd = sitd->xfer_next) { 4447 KASSERT(sitd != NULL); 4448 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4449 4450 sitd->sitd->sitd_trans = htole32(EHCI_SITD_ACTIVE | 4451 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4452 4453 /* Set page0 index and offset - TP and T-offset are set below */ 4454 const bus_addr_t sba = DMAADDR(dma_buf, offs); 4455 sitd->sitd->sitd_buffer[0] = htole32(BUS_ADDR_LO32(sba)); 4456 sitd->sitd->sitd_buffer_hi[0] = htole32(BUS_ADDR_HI32(sba)); 4457 4458 offs += xfer->ux_frlengths[i]; 4459 4460 const bus_addr_t eba = DMAADDR(dma_buf, offs - 1); 4461 sitd->sitd->sitd_buffer[1] = 4462 htole32(EHCI_SITD_SET_BPTR(BUS_ADDR_LO32(eba))); 4463 sitd->sitd->sitd_buffer_hi[1] = htole32(BUS_ADDR_HI32(eba)); 4464 4465 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4466 4467 #if 0 4468 if (sc->sc_flags & EHCIF_FREESCALE) { 4469 // Set hub address to 0 if embedded TT is used. 4470 if (huba == sc->sc_addr) 4471 huba = 0; 4472 } 4473 #endif 4474 4475 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4476 dir = UE_GET_DIR(k) ? 1 : 0; 4477 KASSERT(sitd->sitd->sitd_endp == htole32( 4478 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4479 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4480 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4481 EHCI_SITD_SET_HUBA(huba) | 4482 EHCI_SITD_SET_DIR(dir))); 4483 KASSERT(sitd->sitd->sitd_back == htole32(EHCI_LINK_TERMINATE)); 4484 4485 uint8_t sa = 0; 4486 uint8_t sb = 0; 4487 u_int temp, tlen; 4488 4489 if (dir == 0) { /* OUT */ 4490 temp = 0; 4491 tlen = xfer->ux_frlengths[i]; 4492 if (tlen <= 188) { 4493 temp |= 1; /* T-count = 1, TP = ALL */ 4494 tlen = 1; 4495 } else { 4496 tlen += 187; 4497 tlen /= 188; 4498 temp |= tlen; /* T-count = [1..6] */ 4499 temp |= 8; /* TP = Begin */ 4500 } 4501 sitd->sitd->sitd_buffer[1] |= htole32(temp); 4502 4503 tlen += sa; 4504 4505 if (tlen >= 8) { 4506 sb = 0; 4507 } else { 4508 sb = (1 << tlen); 4509 } 4510 4511 sa = (1 << sa); 4512 sa = (sb - sa) & 0x3F; 4513 sb = 0; 4514 } else { 4515 sb = (-(4 << sa)) & 0xFE; 4516 sa = (1 << sa) & 0x3F; 4517 sa = 0x01; 4518 sb = 0xfc; 4519 } 4520 4521 sitd->sitd->sitd_sched = htole32( 4522 EHCI_SITD_SET_SMASK(sa) | 4523 EHCI_SITD_SET_CMASK(sb) 4524 ); 4525 4526 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4528 } /* End of frame */ 4529 4530 sitd = exfer->ex_sitdend; 4531 sitd->sitd->sitd_trans |= htole32(EHCI_SITD_IOC); 4532 4533 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4534 sizeof(sitd->sitd->sitd_trans), 4535 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4536 4537 if (xfer->ux_length) 4538 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4539 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4540 4541 /* 4542 * Part 2: Transfer descriptors have now been set up, now they must 4543 * be scheduled into the periodic frame list. Erk. Not wanting to 4544 * complicate matters, transfer is denied if the transfer spans 4545 * more than the periodic frame list. 4546 */ 4547 4548 /* Start inserting frames */ 4549 if (epipe->isoc.cur_xfers > 0) { 4550 frindex = epipe->isoc.next_frame; 4551 } else { 4552 frindex = EOREAD4(sc, EHCI_FRINDEX); 4553 frindex = frindex >> 3; /* Erase microframe index */ 4554 frindex += 2; 4555 } 4556 4557 if (frindex >= sc->sc_flsize) 4558 frindex &= (sc->sc_flsize - 1); 4559 4560 /* What's the frame interval? */ 4561 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4562 4563 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4564 j++, sitd = sitd->xfer_next) { 4565 KASSERT(sitd); 4566 4567 usb_syncmem(&sc->sc_fldma, 4568 sizeof(ehci_link_t) * frindex, 4569 sizeof(ehci_link_t), 4570 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4571 4572 sitd->sitd->sitd_next = sc->sc_flist[frindex]; 4573 if (sitd->sitd->sitd_next == 0) 4574 /* 4575 * FIXME: frindex table gets initialized to NULL 4576 * or EHCI_NULL? 4577 */ 4578 sitd->sitd->sitd_next = EHCI_NULL; 4579 4580 usb_syncmem(&sitd->dma, 4581 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4582 sizeof(ehci_sitd_t), 4583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4584 4585 sc->sc_flist[frindex] = 4586 htole32(EHCI_LINK_SITD | sitd->physaddr); 4587 4588 usb_syncmem(&sc->sc_fldma, 4589 sizeof(ehci_link_t) * frindex, 4590 sizeof(ehci_link_t), 4591 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4592 4593 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4594 sc->sc_softsitds[frindex] = sitd; 4595 if (sitd->frame_list.next != NULL) 4596 sitd->frame_list.next->frame_list.prev = sitd; 4597 sitd->slot = frindex; 4598 sitd->frame_list.prev = NULL; 4599 4600 frindex += i; 4601 if (frindex >= sc->sc_flsize) 4602 frindex -= sc->sc_flsize; 4603 } 4604 4605 epipe->isoc.cur_xfers++; 4606 epipe->isoc.next_frame = frindex; 4607 4608 ehci_add_intr_list(sc, exfer); 4609 xfer->ux_status = USBD_IN_PROGRESS; 4610 4611 return USBD_IN_PROGRESS; 4612 } 4613 4614 Static void 4615 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4616 { 4617 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4618 4619 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4620 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4621 } 4622 4623 Static void 4624 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4625 { 4626 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4627 4628 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4629 } 4630 4631 Static void 4632 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4633 { 4634 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4635 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4636 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4637 4638 KASSERT(mutex_owned(&sc->sc_lock)); 4639 4640 epipe->isoc.cur_xfers--; 4641 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4642 4643 if (xfer->ux_length) 4644 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4645 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4646 } 4647 4648 /* -------------------------------------------------------------------------- */ 4649 4650 Static int 4651 ehci_device_isoc_init(struct usbd_xfer *xfer) 4652 { 4653 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4654 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4655 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4656 ehci_soft_itd_t *itd, *prev, *start, *stop; 4657 int i, j, k; 4658 int frames, ufrperframe; 4659 int err; 4660 4661 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4662 4663 start = NULL; 4664 prev = NULL; 4665 itd = NULL; 4666 4667 KASSERT(xfer->ux_nframes != 0); 4668 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4669 KASSERT(exfer->ex_isdone); 4670 4671 exfer->ex_type = EX_ISOC; 4672 4673 /* 4674 * Step 1: Allocate and initialize itds, how many do we need? 4675 * One per transfer if interval >= 8 microframes, less if we use 4676 * multiple microframes per frame. 4677 */ 4678 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4679 if (i > 16 || i == 0) { 4680 /* Spec page 271 says intervals > 16 are invalid */ 4681 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4682 return EINVAL; 4683 } 4684 4685 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4686 frames = howmany(xfer->ux_nframes, ufrperframe); 4687 4688 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4689 itd = ehci_alloc_itd(sc); 4690 if (itd == NULL) { 4691 err = ENOMEM; 4692 goto fail; 4693 } 4694 4695 if (prev != NULL) { 4696 /* Maybe not as it's updated by the scheduling? */ 4697 prev->itd->itd_next = 4698 htole32(itd->physaddr | EHCI_LINK_ITD); 4699 4700 prev->xfer_next = itd; 4701 } else { 4702 start = itd; 4703 } 4704 4705 /* 4706 * Other special values 4707 */ 4708 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4709 itd->itd->itd_bufr[0] = htole32( 4710 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4711 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4712 4713 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4714 ? 1 : 0; 4715 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4716 itd->itd->itd_bufr[1] |= htole32( 4717 EHCI_ITD_SET_DIR(k) | 4718 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4719 4720 /* FIXME: handle invalid trans - should be done in openpipe */ 4721 itd->itd->itd_bufr[2] |= 4722 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4723 } /* End of frame */ 4724 4725 stop = itd; 4726 stop->xfer_next = NULL; 4727 4728 exfer->ex_itdstart = start; 4729 exfer->ex_itdend = stop; 4730 4731 return 0; 4732 fail: 4733 mutex_enter(&sc->sc_lock); 4734 ehci_soft_itd_t *next; 4735 for (itd = start; itd; itd = next) { 4736 next = itd->xfer_next; 4737 ehci_free_itd_locked(sc, itd); 4738 } 4739 mutex_exit(&sc->sc_lock); 4740 4741 return err; 4742 4743 } 4744 4745 Static void 4746 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4747 { 4748 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4749 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4750 4751 KASSERT(ex->ex_type == EX_ISOC); 4752 4753 ehci_free_itd_chain(sc, ex->ex_itdstart); 4754 } 4755 4756 Static usbd_status 4757 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4758 { 4759 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4760 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4761 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4762 ehci_soft_itd_t *itd, *prev; 4763 usb_dma_t *dma_buf; 4764 int i, j; 4765 int frames, uframes, ufrperframe; 4766 int trans_count, offs; 4767 int frindex; 4768 4769 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4770 4771 prev = NULL; 4772 itd = NULL; 4773 trans_count = 0; 4774 4775 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4776 4777 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4778 4779 if (sc->sc_dying) 4780 return USBD_IOERROR; 4781 4782 /* 4783 * To avoid complication, don't allow a request right now that'll span 4784 * the entire frame table. To within 4 frames, to allow some leeway 4785 * on either side of where the hc currently is. 4786 */ 4787 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4788 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4789 DPRINTF( 4790 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4791 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4792 return USBD_INVAL; 4793 } 4794 4795 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4796 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4797 KASSERT(exfer->ex_isdone); 4798 #ifdef DIAGNOSTIC 4799 exfer->ex_isdone = false; 4800 #endif 4801 4802 /* 4803 * Step 1: Re-Initialize itds 4804 */ 4805 4806 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4807 if (i > 16 || i == 0) { 4808 /* Spec page 271 says intervals > 16 are invalid */ 4809 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4810 return USBD_INVAL; 4811 } 4812 4813 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4814 frames = howmany(xfer->ux_nframes, ufrperframe); 4815 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4816 4817 if (frames == 0) { 4818 DPRINTF("frames == 0", 0, 0, 0, 0); 4819 return USBD_INVAL; 4820 } 4821 4822 dma_buf = &xfer->ux_dmabuf; 4823 offs = 0; 4824 4825 itd = exfer->ex_itdstart; 4826 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4827 int froffs = offs; 4828 4829 if (prev != NULL) { 4830 prev->itd->itd_next = 4831 htole32(itd->physaddr | EHCI_LINK_ITD); 4832 usb_syncmem(&prev->dma, 4833 prev->offs + offsetof(ehci_itd_t, itd_next), 4834 sizeof(prev->itd->itd_next), BUS_DMASYNC_POSTWRITE); 4835 prev->xfer_next = itd; 4836 } 4837 4838 /* 4839 * Step 1.5, initialize uframes 4840 */ 4841 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4842 /* Calculate which page in the list this starts in */ 4843 int addr = DMAADDR(dma_buf, froffs); 4844 addr = EHCI_PAGE_OFFSET(addr); 4845 addr += (offs - froffs); 4846 addr = EHCI_PAGE(addr); 4847 addr /= EHCI_PAGE_SIZE; 4848 4849 /* 4850 * This gets the initial offset into the first page, 4851 * looks how far further along the current uframe 4852 * offset is. Works out how many pages that is. 4853 */ 4854 4855 itd->itd->itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4856 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4857 EHCI_ITD_SET_PG(addr) | 4858 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4859 4860 offs += xfer->ux_frlengths[trans_count]; 4861 trans_count++; 4862 4863 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4864 itd->itd->itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4865 break; 4866 } 4867 } 4868 4869 /* 4870 * Step 1.75, set buffer pointers. To simplify matters, all 4871 * pointers are filled out for the next 7 hardware pages in 4872 * the dma block, so no need to worry what pages to cover 4873 * and what to not. 4874 */ 4875 4876 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4877 /* 4878 * Don't try to lookup a page that's past the end 4879 * of buffer 4880 */ 4881 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4882 if (page_offs >= dma_buf->udma_block->size) 4883 break; 4884 4885 uint64_t page = DMAADDR(dma_buf, page_offs); 4886 page = EHCI_PAGE(page); 4887 itd->itd->itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4888 itd->itd->itd_bufr_hi[j] = htole32(page >> 32); 4889 } 4890 /* 4891 * Other special values 4892 */ 4893 4894 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4895 itd->itd->itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4896 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4897 4898 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4899 ? 1 : 0; 4900 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4901 itd->itd->itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4902 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4903 4904 /* FIXME: handle invalid trans */ 4905 itd->itd->itd_bufr[2] |= 4906 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4907 4908 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4909 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4910 4911 prev = itd; 4912 } /* End of frame */ 4913 4914 if (xfer->ux_length) 4915 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4917 4918 /* 4919 * Part 2: Transfer descriptors have now been set up, now they must 4920 * be scheduled into the periodic frame list. Erk. Not wanting to 4921 * complicate matters, transfer is denied if the transfer spans 4922 * more than the periodic frame list. 4923 */ 4924 4925 /* Start inserting frames */ 4926 if (epipe->isoc.cur_xfers > 0) { 4927 frindex = epipe->isoc.next_frame; 4928 } else { 4929 frindex = EOREAD4(sc, EHCI_FRINDEX); 4930 frindex = frindex >> 3; /* Erase microframe index */ 4931 frindex += 2; 4932 } 4933 4934 if (frindex >= sc->sc_flsize) 4935 frindex &= (sc->sc_flsize - 1); 4936 4937 /* What's the frame interval? */ 4938 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4939 if (i / USB_UFRAMES_PER_FRAME == 0) 4940 i = 1; 4941 else 4942 i /= USB_UFRAMES_PER_FRAME; 4943 4944 itd = exfer->ex_itdstart; 4945 for (j = 0; j < frames; j++) { 4946 KASSERTMSG(itd != NULL, "frame %d\n", j); 4947 4948 usb_syncmem(&sc->sc_fldma, 4949 sizeof(ehci_link_t) * frindex, 4950 sizeof(ehci_link_t), 4951 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4952 4953 itd->itd->itd_next = sc->sc_flist[frindex]; 4954 if (itd->itd->itd_next == 0) 4955 /* 4956 * FIXME: frindex table gets initialized to NULL 4957 * or EHCI_NULL? 4958 */ 4959 itd->itd->itd_next = EHCI_NULL; 4960 4961 usb_syncmem(&itd->dma, 4962 itd->offs + offsetof(ehci_itd_t, itd_next), 4963 sizeof(itd->itd->itd_next), 4964 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4965 4966 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4967 4968 usb_syncmem(&sc->sc_fldma, 4969 sizeof(ehci_link_t) * frindex, 4970 sizeof(ehci_link_t), 4971 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4972 4973 itd->frame_list.next = sc->sc_softitds[frindex]; 4974 sc->sc_softitds[frindex] = itd; 4975 if (itd->frame_list.next != NULL) 4976 itd->frame_list.next->frame_list.prev = itd; 4977 itd->slot = frindex; 4978 itd->frame_list.prev = NULL; 4979 4980 frindex += i; 4981 if (frindex >= sc->sc_flsize) 4982 frindex -= sc->sc_flsize; 4983 4984 itd = itd->xfer_next; 4985 } 4986 4987 epipe->isoc.cur_xfers++; 4988 epipe->isoc.next_frame = frindex; 4989 4990 ehci_add_intr_list(sc, exfer); 4991 xfer->ux_status = USBD_IN_PROGRESS; 4992 4993 return USBD_IN_PROGRESS; 4994 } 4995 4996 Static void 4997 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4998 { 4999 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 5000 5001 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 5002 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5003 } 5004 5005 Static void 5006 ehci_device_isoc_close(struct usbd_pipe *pipe) 5007 { 5008 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 5009 5010 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 5011 } 5012 5013 Static void 5014 ehci_device_isoc_done(struct usbd_xfer *xfer) 5015 { 5016 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5017 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5018 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5019 5020 KASSERT(mutex_owned(&sc->sc_lock)); 5021 5022 epipe->isoc.cur_xfers--; 5023 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5024 if (xfer->ux_length) 5025 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5026 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5027 } 5028
Indexes created Tue Sep 23 01:09:51 GMT 2025