ehci.c revision 1.327
1 /* $NetBSD: ehci.c,v 1.327 2024/09/23 16:28:06 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna23.net), and 11 * Nick Hudson . 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 37 * 38 * The EHCI 1.0 spec can be found at 39 * http://www.intel.com/technology/usb/spec.htm 40 * and the USB 2.0 spec at 41 * http://www.usb.org/developers/docs/ 42 * 43 */ 44 45 /* 46 * TODO: 47 * 1) hold off explorations by companion controllers until ehci has started. 48 * 49 * 2) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 3) Command failures are not recovered correctly. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.327 2024/09/23 16:28:06 skrll Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #ifdef _KERNEL_OPT 63 #include "opt_usb.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #include <sys/bus.h> 69 #include <sys/cpu.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/kmem.h> 73 #include <sys/mutex.h> 74 #include <sys/proc.h> 75 #include <sys/queue.h> 76 #include <sys/select.h> 77 #include <sys/sysctl.h> 78 #include <sys/systm.h> 79 #include <sys/reboot.h> 80 81 #include <machine/endian.h> 82 83 #include <dev/usb/usb.h> 84 #include <dev/usb/usbdi.h> 85 #include <dev/usb/usbdivar.h> 86 #include <dev/usb/usbhist.h> 87 #include <dev/usb/usb_mem.h> 88 #include <dev/usb/usb_quirks.h> 89 90 #include <dev/usb/ehcireg.h> 91 #include <dev/usb/ehcivar.h> 92 #include <dev/usb/usbroothub.h> 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 99 #ifndef EHCI_DEBUG_DEFAULT 100 #define EHCI_DEBUG_DEFAULT 0 101 #endif 102 103 static int ehcidebug = EHCI_DEBUG_DEFAULT; 104 105 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 106 { 107 int err; 108 const struct sysctlnode *rnode; 109 const struct sysctlnode *cnode; 110 111 err = sysctl_createv(clog, 0, NULL, &rnode, 112 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 113 SYSCTL_DESCR("ehci global controls"), 114 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 115 116 if (err) 117 goto fail; 118 119 /* control debugging printfs */ 120 err = sysctl_createv(clog, 0, &rnode, &cnode, 121 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 122 "debug", SYSCTL_DESCR("Enable debugging output"), 123 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 124 if (err) 125 goto fail; 126 127 return; 128 fail: 129 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 130 } 131 132 #endif /* EHCI_DEBUG */ 133 #endif /* USB_DEBUG */ 134 135 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 136 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 137 #define EHCIHIST_FUNC() USBHIST_FUNC() 138 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 139 140 struct ehci_pipe { 141 struct usbd_pipe pipe; 142 int nexttoggle; 143 144 ehci_soft_qh_t *sqh; 145 union { 146 /* Control pipe */ 147 struct { 148 usb_dma_t reqdma; 149 } ctrl; 150 /* Interrupt pipe */ 151 struct { 152 u_int length; 153 } intr; 154 /* Iso pipe */ 155 struct { 156 u_int next_frame; 157 u_int cur_xfers; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 163 164 Static usbd_status ehci_open(struct usbd_pipe *); 165 Static void ehci_poll(struct usbd_bus *); 166 Static void ehci_softintr(void *); 167 Static int ehci_intr1(ehci_softc_t *); 168 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 169 ex_completeq_t *); 170 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 171 ex_completeq_t *); 172 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 173 ex_completeq_t *); 174 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 175 Static void ehci_intrlist_timeout(void *); 176 Static void ehci_doorbell(void *); 177 Static void ehci_pcd(void *); 178 179 Static struct usbd_xfer * 180 ehci_allocx(struct usbd_bus *, unsigned int); 181 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 182 183 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 184 Static bool ehci_dying(struct usbd_bus *); 185 Static int ehci_roothub_ctrl(struct usbd_bus *, 186 usb_device_request_t *, void *, int); 187 188 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 189 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 190 Static void ehci_root_intr_abort(struct usbd_xfer *); 191 Static void ehci_root_intr_close(struct usbd_pipe *); 192 Static void ehci_root_intr_done(struct usbd_xfer *); 193 194 Static int ehci_device_ctrl_init(struct usbd_xfer *); 195 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 196 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 197 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 198 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 199 Static void ehci_device_ctrl_close(struct usbd_pipe *); 200 Static void ehci_device_ctrl_done(struct usbd_xfer *); 201 202 Static int ehci_device_bulk_init(struct usbd_xfer *); 203 Static void ehci_device_bulk_fini(struct usbd_xfer *); 204 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 205 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 206 Static void ehci_device_bulk_abort(struct usbd_xfer *); 207 Static void ehci_device_bulk_close(struct usbd_pipe *); 208 Static void ehci_device_bulk_done(struct usbd_xfer *); 209 210 Static int ehci_device_intr_init(struct usbd_xfer *); 211 Static void ehci_device_intr_fini(struct usbd_xfer *); 212 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 213 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 214 Static void ehci_device_intr_abort(struct usbd_xfer *); 215 Static void ehci_device_intr_close(struct usbd_pipe *); 216 Static void ehci_device_intr_done(struct usbd_xfer *); 217 218 Static int ehci_device_isoc_init(struct usbd_xfer *); 219 Static void ehci_device_isoc_fini(struct usbd_xfer *); 220 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 221 Static void ehci_device_isoc_abort(struct usbd_xfer *); 222 Static void ehci_device_isoc_close(struct usbd_pipe *); 223 Static void ehci_device_isoc_done(struct usbd_xfer *); 224 225 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 226 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 227 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 228 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 229 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 230 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 231 232 Static void ehci_device_clear_toggle(struct usbd_pipe *); 233 Static void ehci_noop(struct usbd_pipe *); 234 235 Static void ehci_disown(ehci_softc_t *, int, int); 236 237 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 238 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 239 240 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 241 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 242 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 243 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 244 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 245 246 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 247 int, int, int *, ehci_soft_qtd_t **); 248 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 249 250 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 251 Static ehci_soft_sitd_t * 252 ehci_alloc_sitd(ehci_softc_t *); 253 254 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 255 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 256 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 257 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 258 259 static inline void 260 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 261 { 262 263 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 264 } 265 266 static inline void 267 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 268 { 269 270 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 271 } 272 273 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 274 275 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 276 int); 277 278 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 279 ehci_soft_qh_t *); 280 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 281 ehci_soft_qh_t *); 282 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 283 Static void ehci_sync_hc(ehci_softc_t *); 284 285 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 286 Static void ehci_abortx(struct usbd_xfer *); 287 288 #ifdef EHCI_DEBUG 289 Static ehci_softc_t *theehci; 290 void ehci_dump(void); 291 #endif 292 293 #ifdef EHCI_DEBUG 294 Static void ehci_dump_regs(ehci_softc_t *); 295 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 296 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 297 Static void ehci_dump_qh_qtd(struct ehci_qh_qtd_t *); 298 Static void ehci_dump_qtd(ehci_qtd_t *); 299 Static void ehci_dump_sqh(ehci_soft_qh_t *); 300 Static void ehci_dump_sitd(struct ehci_soft_itd *); 301 Static void ehci_dump_itds(ehci_soft_itd_t *); 302 Static void ehci_dump_itd(struct ehci_soft_itd *); 303 Static void ehci_dump_exfer(struct ehci_xfer *); 304 #endif 305 306 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 307 308 static inline void 309 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 310 { 311 312 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 313 } 314 315 static inline void 316 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 317 { 318 319 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 320 } 321 322 Static const struct usbd_bus_methods ehci_bus_methods = { 323 .ubm_open = ehci_open, 324 .ubm_softint = ehci_softintr, 325 .ubm_dopoll = ehci_poll, 326 .ubm_allocx = ehci_allocx, 327 .ubm_freex = ehci_freex, 328 .ubm_abortx = ehci_abortx, 329 .ubm_dying = ehci_dying, 330 .ubm_getlock = ehci_get_lock, 331 .ubm_rhctrl = ehci_roothub_ctrl, 332 }; 333 334 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 335 .upm_transfer = ehci_root_intr_transfer, 336 .upm_start = ehci_root_intr_start, 337 .upm_abort = ehci_root_intr_abort, 338 .upm_close = ehci_root_intr_close, 339 .upm_cleartoggle = ehci_noop, 340 .upm_done = ehci_root_intr_done, 341 }; 342 343 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 344 .upm_init = ehci_device_ctrl_init, 345 .upm_fini = ehci_device_ctrl_fini, 346 .upm_transfer = ehci_device_ctrl_transfer, 347 .upm_start = ehci_device_ctrl_start, 348 .upm_abort = ehci_device_ctrl_abort, 349 .upm_close = ehci_device_ctrl_close, 350 .upm_cleartoggle = ehci_noop, 351 .upm_done = ehci_device_ctrl_done, 352 }; 353 354 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 355 .upm_init = ehci_device_intr_init, 356 .upm_fini = ehci_device_intr_fini, 357 .upm_transfer = ehci_device_intr_transfer, 358 .upm_start = ehci_device_intr_start, 359 .upm_abort = ehci_device_intr_abort, 360 .upm_close = ehci_device_intr_close, 361 .upm_cleartoggle = ehci_device_clear_toggle, 362 .upm_done = ehci_device_intr_done, 363 }; 364 365 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 366 .upm_init = ehci_device_bulk_init, 367 .upm_fini = ehci_device_bulk_fini, 368 .upm_transfer = ehci_device_bulk_transfer, 369 .upm_start = ehci_device_bulk_start, 370 .upm_abort = ehci_device_bulk_abort, 371 .upm_close = ehci_device_bulk_close, 372 .upm_cleartoggle = ehci_device_clear_toggle, 373 .upm_done = ehci_device_bulk_done, 374 }; 375 376 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 377 .upm_init = ehci_device_isoc_init, 378 .upm_fini = ehci_device_isoc_fini, 379 .upm_transfer = ehci_device_isoc_transfer, 380 .upm_abort = ehci_device_isoc_abort, 381 .upm_close = ehci_device_isoc_close, 382 .upm_cleartoggle = ehci_noop, 383 .upm_done = ehci_device_isoc_done, 384 }; 385 386 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 387 .upm_init = ehci_device_fs_isoc_init, 388 .upm_fini = ehci_device_fs_isoc_fini, 389 .upm_transfer = ehci_device_fs_isoc_transfer, 390 .upm_abort = ehci_device_fs_isoc_abort, 391 .upm_close = ehci_device_fs_isoc_close, 392 .upm_cleartoggle = ehci_noop, 393 .upm_done = ehci_device_fs_isoc_done, 394 }; 395 396 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 397 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 398 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 399 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 400 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 401 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 402 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 403 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 404 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 405 }; 406 407 int 408 ehci_init(ehci_softc_t *sc) 409 { 410 uint32_t vers, hcr; 411 u_int i; 412 int err; 413 ehci_soft_qh_t *sqh; 414 u_int ncomp; 415 416 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 417 #ifdef EHCI_DEBUG 418 theehci = sc; 419 #endif 420 421 mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE); 422 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 423 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 424 cv_init(&sc->sc_doorbell, "ehcidb"); 425 426 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 427 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 428 429 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 430 ehci_doorbell, sc); 431 KASSERT(sc->sc_doorbell_si != NULL); 432 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 433 ehci_pcd, sc); 434 KASSERT(sc->sc_pcd_si != NULL); 435 436 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 437 438 vers = EREAD2(sc, EHCI_HCIVERSION); 439 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 440 vers >> 8, vers & 0xff); 441 442 const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS); 443 DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0); 444 sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams); 445 ncomp = EHCI_HCS_N_CC(hcsparams); 446 if (ncomp != sc->sc_ncomp) { 447 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 448 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 449 #if NOHCI == 0 || NUHCI == 0 450 aprint_error("%s: ohci or uhci probably not configured\n", 451 device_xname(sc->sc_dev)); 452 #endif 453 if (ncomp < sc->sc_ncomp) 454 sc->sc_ncomp = ncomp; 455 } 456 if (sc->sc_ncomp > 0) { 457 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 458 aprint_normal_dev(sc->sc_dev, 459 "%d companion controller%s, %d port%s%s", 460 sc->sc_ncomp, 461 sc->sc_ncomp!=1 ? "s" : "", 462 EHCI_HCS_N_PCC(hcsparams), 463 EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "", 464 sc->sc_ncomp!=1 ? " each" : ""); 465 if (sc->sc_comps[0]) { 466 aprint_normal(":"); 467 for (i = 0; i < sc->sc_ncomp; i++) 468 aprint_normal(" %s", 469 device_xname(sc->sc_comps[i])); 470 } 471 aprint_normal("\n"); 472 473 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 474 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 475 cv_init(&sc->sc_compcv, "ehciccv"); 476 sc->sc_comp_state = CO_EARLY; 477 } 478 sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams); 479 sc->sc_hasppc = EHCI_HCS_PPC(hcsparams); 480 481 const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS); 482 DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0); 483 484 if (EHCI_HCC_64BIT(hccparams)) { 485 /* MUST clear segment register if 64 bit capable. */ 486 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 487 } 488 489 if (hccparams & EHCI_HCC_IST_FULLFRAME) { 490 sc->sc_istthreshold = 0; 491 } else { 492 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams); 493 } 494 495 sc->sc_bus.ub_revision = USBREV_2_0; 496 sc->sc_bus.ub_usedma = true; 497 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 498 499 /* 500 * The bus attachment code will possibly provide a 64bit DMA 501 * tag which we now limit to the bottom 4G range as 502 * 503 * - that's as much as ehci can address in its QH, TD, iTD, and siTD 504 * structures; and 505 * - the driver doesn't currently set EHCI_CTRLDSSEGMENT to anything 506 * other than 0. 507 */ 508 bus_dma_tag_t ntag = sc->sc_bus.ub_dmatag; 509 sc->sc_dmatag = sc->sc_bus.ub_dmatag; 510 err = bus_dmatag_subregion(sc->sc_bus.ub_dmatag, 0, UINT32_MAX, 511 &ntag, 0); 512 if (err == 0) { 513 sc->sc_dmatag = ntag; 514 aprint_normal_dev(sc->sc_dev, "Using DMA subregion for control" 515 " data structures\n"); 516 } 517 518 /* Reset the controller */ 519 DPRINTF("resetting", 0, 0, 0, 0); 520 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 521 usb_delay_ms(&sc->sc_bus, 1); 522 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 523 for (i = 0; i < 100; i++) { 524 usb_delay_ms(&sc->sc_bus, 1); 525 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 526 if (!hcr) 527 break; 528 } 529 if (hcr) { 530 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 531 err = EIO; 532 goto fail1; 533 } 534 if (sc->sc_vendor_init) 535 sc->sc_vendor_init(sc); 536 537 /* XXX need proper intr scheduling */ 538 sc->sc_rand = 96; 539 540 /* frame list size at default, read back what we got and use that */ 541 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 542 case 0: sc->sc_flsize = 1024; break; 543 case 1: sc->sc_flsize = 512; break; 544 case 2: sc->sc_flsize = 256; break; 545 case 3: 546 err = EIO; 547 goto fail1; 548 } 549 err = usb_allocmem(sc->sc_dmatag, 550 sc->sc_flsize * sizeof(ehci_link_t), 551 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 552 if (err) { 553 aprint_error_dev(sc->sc_dev, "failed to allocate frame list\n"); 554 goto fail1; 555 } 556 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 557 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 558 559 for (i = 0; i < sc->sc_flsize; i++) { 560 sc->sc_flist[i] = EHCI_NULL; 561 } 562 563 const bus_addr_t flba = DMAADDR(&sc->sc_fldma, 0); 564 const uint32_t hi32 = BUS_ADDR_HI32(flba); 565 if (hi32 != 0) { 566 aprint_error_dev(sc->sc_dev, "DMA memory segment error (%08x)\n", 567 hi32); 568 goto fail2; 569 } 570 571 const uint32_t lo32 = BUS_ADDR_LO32(flba); 572 EOWRITE4(sc, EHCI_PERIODICLISTBASE, lo32); 573 574 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 575 KM_SLEEP); 576 LIST_INIT(&sc->sc_freeitds); 577 LIST_INIT(&sc->sc_freesitds); 578 TAILQ_INIT(&sc->sc_intrhead); 579 580 /* Set up the bus struct. */ 581 sc->sc_bus.ub_methods = &ehci_bus_methods; 582 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 583 584 sc->sc_eintrs = EHCI_NORMAL_INTRS; 585 586 /* 587 * Allocate the interrupt dummy QHs. These are arranged to give poll 588 * intervals that are powers of 2 times 1ms. 589 */ 590 memset(sc->sc_islots, 0, sizeof(sc->sc_islots)); 591 for (i = 0; i < EHCI_INTRQHS; i++) { 592 sqh = ehci_alloc_sqh(sc); 593 if (sqh == NULL) { 594 err = ENOMEM; 595 goto fail3; 596 } 597 sc->sc_islots[i].sqh = sqh; 598 } 599 for (i = 0; i < EHCI_INTRQHS; i++) { 600 sqh = sc->sc_islots[i].sqh; 601 if (i == 0) { 602 /* The last (1ms) QH terminates. */ 603 sqh->qh->qh_link = EHCI_NULL; 604 sqh->next = NULL; 605 } else { 606 /* Otherwise the next QH has half the poll interval */ 607 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 608 sqh->qh->qh_link = htole32(sqh->next->physaddr | 609 EHCI_LINK_QH); 610 } 611 sqh->qh->qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 612 sqh->qh->qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 613 sqh->qh->qh_curqtd = EHCI_NULL; 614 615 sqh->qh->qh_qtd.qtd_next = EHCI_NULL; 616 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 617 sqh->qh->qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 618 619 ehci_qtd_t *qh_qtd = &sqh->qh->qh_qtd; 620 for (unsigned n = 0; n < EHCI_QTD_NBUFFERS; n++) { 621 qh_qtd->qtd_buffer[n] = 0; 622 qh_qtd->qtd_buffer_hi[n] = 0; 623 } 624 625 sqh->sqtd = NULL; 626 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 627 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 628 } 629 /* Point the frame list at the last level (128ms). */ 630 for (i = 0; i < sc->sc_flsize; i++) { 631 int j; 632 633 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 634 revbits[i & (EHCI_MAX_POLLRATE-1)]; 635 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 636 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 637 i)].sqh->physaddr); 638 } 639 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 640 BUS_DMASYNC_PREWRITE); 641 642 /* Allocate dummy QH that starts the async list. */ 643 sqh = ehci_alloc_sqh(sc); 644 if (sqh == NULL) { 645 err = ENOMEM; 646 goto fail3; 647 } 648 /* Fill the QH */ 649 sqh->qh->qh_endp = 650 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 651 sqh->qh->qh_link = 652 htole32(sqh->physaddr | EHCI_LINK_QH); 653 sqh->qh->qh_curqtd = EHCI_NULL; 654 sqh->next = NULL; 655 /* Fill the overlay qTD */ 656 sqh->qh->qh_qtd.qtd_next = EHCI_NULL; 657 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 658 sqh->qh->qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 659 660 ehci_qtd_t *qh_qtd = &sqh->qh->qh_qtd; 661 for (unsigned n = 0; n < EHCI_QTD_NBUFFERS; n++) { 662 qh_qtd->qtd_buffer[n] = 0; 663 qh_qtd->qtd_buffer_hi[n] = 0; 664 } 665 666 sqh->sqtd = NULL; 667 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 668 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 669 #ifdef EHCI_DEBUG 670 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 671 ehci_dump_sqh(sqh); 672 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 673 #endif 674 675 /* Point to async list */ 676 sc->sc_async_head = sqh; 677 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 678 679 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 680 681 /* Turn on controller */ 682 EOWRITE4(sc, EHCI_USBCMD, 683 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 684 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 685 EHCI_CMD_ASE | 686 EHCI_CMD_PSE | 687 EHCI_CMD_RS); 688 689 /* Take over port ownership */ 690 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 691 692 for (i = 0; i < 100; i++) { 693 usb_delay_ms(&sc->sc_bus, 1); 694 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 695 if (!hcr) 696 break; 697 } 698 if (hcr) { 699 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 700 err = EIO; 701 goto fail4; 702 } 703 704 /* Enable interrupts */ 705 DPRINTF("enabling interrupts", 0, 0, 0, 0); 706 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 707 708 return 0; 709 710 fail4: 711 ehci_free_sqh(sc, sc->sc_async_head); 712 713 fail3: 714 for (i = 0; i < EHCI_INTRQHS; i++) { 715 sqh = sc->sc_islots[i].sqh; 716 if (sqh) 717 ehci_free_sqh(sc, sqh); 718 } 719 720 kmem_free(sc->sc_softitds, sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 721 722 fail2: 723 usb_freemem(&sc->sc_fldma); 724 725 fail1: 726 softint_disestablish(sc->sc_doorbell_si); 727 softint_disestablish(sc->sc_pcd_si); 728 mutex_destroy(&sc->sc_rhlock); 729 mutex_destroy(&sc->sc_lock); 730 mutex_destroy(&sc->sc_intr_lock); 731 732 return err; 733 } 734 735 int 736 ehci_intr(void *v) 737 { 738 ehci_softc_t *sc = v; 739 int ret = 0; 740 741 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 742 743 if (sc == NULL) 744 return 0; 745 746 mutex_spin_enter(&sc->sc_intr_lock); 747 748 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 749 goto done; 750 751 /* If we get an interrupt while polling, then just ignore it. */ 752 if (sc->sc_bus.ub_usepolling) { 753 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 754 755 if (intrs) 756 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 757 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 758 goto done; 759 } 760 761 ret = ehci_intr1(sc); 762 763 done: 764 mutex_spin_exit(&sc->sc_intr_lock); 765 return ret; 766 } 767 768 Static int 769 ehci_intr1(ehci_softc_t *sc) 770 { 771 uint32_t intrs, eintrs; 772 773 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 774 775 /* In case the interrupt occurs before initialization has completed. */ 776 if (sc == NULL) { 777 #ifdef DIAGNOSTIC 778 printf("ehci_intr1: sc == NULL\n"); 779 #endif 780 return 0; 781 } 782 783 KASSERT(mutex_owned(&sc->sc_intr_lock)); 784 785 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 786 if (!intrs) 787 return 0; 788 789 eintrs = intrs & sc->sc_eintrs; 790 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 791 EOREAD4(sc, EHCI_USBSTS), eintrs); 792 if (!eintrs) 793 return 0; 794 795 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 796 if (eintrs & EHCI_STS_IAA) { 797 DPRINTF("door bell", 0, 0, 0, 0); 798 kpreempt_disable(); 799 KASSERT(sc->sc_doorbell_si != NULL); 800 softint_schedule(sc->sc_doorbell_si); 801 kpreempt_enable(); 802 eintrs &= ~EHCI_STS_IAA; 803 } 804 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 805 DPRINTF("INT=%jd ERRINT=%jd", 806 eintrs & EHCI_STS_INT ? 1 : 0, 807 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 808 usb_schedsoftintr(&sc->sc_bus); 809 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 810 } 811 if (eintrs & EHCI_STS_HSE) { 812 printf("%s: unrecoverable error, controller halted\n", 813 device_xname(sc->sc_dev)); 814 /* XXX what else */ 815 } 816 if (eintrs & EHCI_STS_PCD) { 817 kpreempt_disable(); 818 KASSERT(sc->sc_pcd_si != NULL); 819 softint_schedule(sc->sc_pcd_si); 820 kpreempt_enable(); 821 eintrs &= ~EHCI_STS_PCD; 822 } 823 824 if (eintrs != 0) { 825 /* Block unprocessed interrupts. */ 826 sc->sc_eintrs &= ~eintrs; 827 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 828 printf("%s: blocking intrs %#x\n", 829 device_xname(sc->sc_dev), eintrs); 830 } 831 832 return 1; 833 } 834 835 Static void 836 ehci_doorbell(void *addr) 837 { 838 ehci_softc_t *sc = addr; 839 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 840 841 mutex_enter(&sc->sc_lock); 842 if (sc->sc_doorbelllwp == NULL) 843 DPRINTF("spurious doorbell interrupt", 0, 0, 0, 0); 844 sc->sc_doorbelllwp = NULL; 845 cv_broadcast(&sc->sc_doorbell); 846 mutex_exit(&sc->sc_lock); 847 } 848 849 Static void 850 ehci_pcd(void *addr) 851 { 852 ehci_softc_t *sc = addr; 853 struct usbd_xfer *xfer; 854 u_char *p; 855 int i, m; 856 857 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 858 859 mutex_enter(&sc->sc_lock); 860 xfer = sc->sc_intrxfer; 861 862 if (xfer == NULL) { 863 /* Just ignore the change. */ 864 goto done; 865 } 866 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 867 868 p = xfer->ux_buf; 869 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 870 memset(p, 0, xfer->ux_length); 871 for (i = 1; i <= m; i++) { 872 /* Pick out CHANGE bits from the status reg. */ 873 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 874 p[i/8] |= 1 << (i%8); 875 if (i % 8 == 7) 876 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 877 } 878 xfer->ux_actlen = xfer->ux_length; 879 xfer->ux_status = USBD_NORMAL_COMPLETION; 880 881 usb_transfer_complete(xfer); 882 883 done: 884 mutex_exit(&sc->sc_lock); 885 } 886 887 Static void 888 ehci_softintr(void *v) 889 { 890 struct usbd_bus *bus = v; 891 ehci_softc_t *sc = EHCI_BUS2SC(bus); 892 struct ehci_xfer *ex, *nextex; 893 894 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 895 896 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 897 898 ex_completeq_t cq; 899 TAILQ_INIT(&cq); 900 901 /* 902 * The only explanation I can think of for why EHCI is as brain dead 903 * as UHCI interrupt-wise is that Intel was involved in both. 904 * An interrupt just tells us that something is done, we have no 905 * clue what, so we need to scan through all active transfers. :-( 906 */ 907 908 /* 909 * ehci_idone will remove transfer from sc->sc_intrhead if it's 910 * complete and add to our cq list 911 * 912 */ 913 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 914 switch (ex->ex_type) { 915 case EX_CTRL: 916 case EX_BULK: 917 case EX_INTR: 918 ehci_check_qh_intr(sc, ex, &cq); 919 break; 920 case EX_ISOC: 921 ehci_check_itd_intr(sc, ex, &cq); 922 break; 923 case EX_FS_ISOC: 924 ehci_check_sitd_intr(sc, ex, &cq); 925 break; 926 default: 927 KASSERT(false); 928 } 929 930 } 931 932 /* 933 * We abuse ex_next for the interrupt and complete lists and 934 * interrupt transfers will get re-added here so use 935 * the _SAFE version of TAILQ_FOREACH. 936 */ 937 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 938 usb_transfer_complete(&ex->ex_xfer); 939 } 940 941 /* Schedule a callout to catch any dropped transactions. */ 942 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 943 !TAILQ_EMPTY(&sc->sc_intrhead)) 944 callout_reset(&sc->sc_tmo_intrlist, 945 hz, ehci_intrlist_timeout, sc); 946 } 947 948 Static void 949 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 950 { 951 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 952 uint32_t status; 953 954 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 955 956 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 957 958 if (ex->ex_type == EX_CTRL) { 959 fsqtd = ex->ex_setup; 960 lsqtd = ex->ex_status; 961 } else { 962 fsqtd = ex->ex_sqtdstart; 963 lsqtd = ex->ex_sqtdend; 964 } 965 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 966 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 967 968 /* 969 * If the last TD is still active we need to check whether there 970 * is an error somewhere in the middle, or whether there was a 971 * short packet (SPD and not ACTIVE). 972 */ 973 usb_syncmem(&lsqtd->dma, 974 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 975 sizeof(lsqtd->qtd->qtd_status), 976 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 977 status = le32toh(lsqtd->qtd->qtd_status); 978 usb_syncmem(&lsqtd->dma, 979 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 980 sizeof(lsqtd->qtd->qtd_status), BUS_DMASYNC_PREREAD); 981 if (status & EHCI_QTD_ACTIVE) { 982 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 983 984 /* last qTD has already been checked */ 985 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 986 usb_syncmem(&sqtd->dma, 987 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 988 sizeof(sqtd->qtd->qtd_status), 989 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 990 status = le32toh(sqtd->qtd->qtd_status); 991 usb_syncmem(&sqtd->dma, 992 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 993 sizeof(sqtd->qtd->qtd_status), BUS_DMASYNC_PREREAD); 994 /* If there's an active QTD the xfer isn't done. */ 995 if (status & EHCI_QTD_ACTIVE) 996 break; 997 /* Any kind of error makes the xfer done. */ 998 if (status & EHCI_QTD_HALTED) 999 goto done; 1000 /* Handle short packets */ 1001 if (EHCI_QTD_GET_BYTES(status) != 0) { 1002 /* 1003 * If we get here for a control transfer then 1004 * we need to let the hardware complete the 1005 * status phase. That is, we're not done 1006 * quite yet. 1007 * 1008 * Otherwise, we're done. 1009 */ 1010 if (ex->ex_type == EX_CTRL) { 1011 break; 1012 } 1013 goto done; 1014 } 1015 } 1016 DPRINTFN(10, "ex=%#jx std=%#jx still active", 1017 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 1018 #ifdef EHCI_DEBUG 1019 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 1020 ehci_dump_sqtds(ex->ex_sqtdstart); 1021 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 1022 #endif 1023 return; 1024 } 1025 done: 1026 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1027 ehci_idone(ex, cq); 1028 } 1029 1030 Static void 1031 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1032 { 1033 ehci_soft_itd_t *itd; 1034 int i; 1035 1036 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1037 1038 KASSERT(mutex_owned(&sc->sc_lock)); 1039 1040 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1041 return; 1042 1043 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 1044 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 1045 1046 itd = ex->ex_itdend; 1047 1048 /* 1049 * check no active transfers in last itd, meaning we're finished 1050 */ 1051 1052 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1053 sizeof(itd->itd->itd_ctl), 1054 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1055 1056 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1057 if (le32toh(itd->itd->itd_ctl[i]) & EHCI_ITD_ACTIVE) 1058 break; 1059 } 1060 1061 if (i == EHCI_ITD_NUFRAMES) { 1062 goto done; /* All 8 descriptors inactive, it's done */ 1063 } 1064 1065 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1066 sizeof(itd->itd->itd_ctl), BUS_DMASYNC_PREREAD); 1067 1068 DPRINTFN(10, "ex %#jx itd %#jx still active", 1069 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 1070 return; 1071 done: 1072 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 1073 ehci_idone(ex, cq); 1074 } 1075 1076 void 1077 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1078 { 1079 ehci_soft_sitd_t *sitd; 1080 1081 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1082 1083 KASSERT(mutex_owned(&sc->sc_lock)); 1084 1085 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1086 return; 1087 1088 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1089 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1090 1091 sitd = ex->ex_sitdend; 1092 1093 /* 1094 * check no active transfers in last sitd, meaning we're finished 1095 */ 1096 1097 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1098 sizeof(sitd->sitd->sitd_trans), 1099 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1100 1101 bool active = ((le32toh(sitd->sitd->sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1102 1103 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1104 sizeof(sitd->sitd->sitd_trans), BUS_DMASYNC_PREREAD); 1105 1106 if (active) 1107 return; 1108 1109 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1110 ehci_idone(ex, cq); 1111 } 1112 1113 Static void 1114 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1115 { 1116 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1117 struct usbd_xfer *xfer = &ex->ex_xfer; 1118 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1119 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1120 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1121 uint32_t status = 0, nstatus = 0; 1122 int actlen = 0; 1123 1124 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1125 1126 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1127 1128 /* 1129 * Try to claim this xfer for completion. If it has already 1130 * completed or aborted, drop it on the floor. 1131 */ 1132 if (!usbd_xfer_trycomplete(xfer)) 1133 return; 1134 1135 #ifdef DIAGNOSTIC 1136 #ifdef EHCI_DEBUG 1137 if (ex->ex_isdone) { 1138 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1139 ehci_dump_exfer(ex); 1140 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1141 } 1142 #endif 1143 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1144 ex->ex_type, xfer->ux_status); 1145 ex->ex_isdone = true; 1146 #endif 1147 1148 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1149 (uintptr_t)epipe, 0, 0); 1150 1151 /* The transfer is done, compute actual length and status. */ 1152 if (ex->ex_type == EX_ISOC) { 1153 /* HS isoc transfer */ 1154 1155 struct ehci_soft_itd *itd; 1156 int i, nframes, len, uframes; 1157 1158 nframes = 0; 1159 1160 #ifdef EHCI_DEBUG 1161 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1162 ehci_dump_itds(ex->ex_itdstart); 1163 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1164 #endif 1165 1166 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1167 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1168 1169 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1170 usb_syncmem(&itd->dma, 1171 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1172 sizeof(itd->itd->itd_ctl), 1173 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1174 1175 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1176 /* 1177 * XXX - driver didn't fill in the frame full 1178 * of uframes. This leads to scheduling 1179 * inefficiencies, but working around 1180 * this doubles complexity of tracking 1181 * an xfer. 1182 */ 1183 if (nframes >= xfer->ux_nframes) 1184 break; 1185 1186 status = le32toh(itd->itd->itd_ctl[i]); 1187 len = EHCI_ITD_GET_LEN(status); 1188 if (EHCI_ITD_GET_STATUS(status) != 0) 1189 len = 0; /*No valid data on error*/ 1190 1191 xfer->ux_frlengths[nframes++] = len; 1192 actlen += len; 1193 } 1194 usb_syncmem(&itd->dma, 1195 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1196 sizeof(itd->itd->itd_ctl), BUS_DMASYNC_PREREAD); 1197 1198 if (nframes >= xfer->ux_nframes) 1199 break; 1200 } 1201 1202 xfer->ux_actlen = actlen; 1203 xfer->ux_status = USBD_NORMAL_COMPLETION; 1204 goto end; 1205 } else if (ex->ex_type == EX_FS_ISOC) { 1206 /* FS isoc transfer */ 1207 struct ehci_soft_sitd *sitd; 1208 int nframes, len; 1209 1210 nframes = 0; 1211 1212 for (sitd = ex->ex_sitdstart; sitd != NULL; 1213 sitd = sitd->xfer_next) { 1214 usb_syncmem(&sitd->dma, 1215 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1216 sizeof(sitd->sitd->sitd_trans), 1217 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1218 1219 /* 1220 * XXX - driver didn't fill in the frame full 1221 * of uframes. This leads to scheduling 1222 * inefficiencies, but working around 1223 * this doubles complexity of tracking 1224 * an xfer. 1225 */ 1226 if (nframes >= xfer->ux_nframes) 1227 break; 1228 1229 status = le32toh(sitd->sitd->sitd_trans); 1230 usb_syncmem(&sitd->dma, 1231 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1232 sizeof(sitd->sitd->sitd_trans), BUS_DMASYNC_PREREAD); 1233 1234 len = EHCI_SITD_GET_LEN(status); 1235 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1236 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1237 /* No valid data on error */ 1238 len = xfer->ux_frlengths[nframes]; 1239 } 1240 1241 /* 1242 * frlengths[i]: # of bytes to send 1243 * len: # of bytes host didn't send 1244 */ 1245 xfer->ux_frlengths[nframes] -= len; 1246 /* frlengths[i]: # of bytes host sent */ 1247 actlen += xfer->ux_frlengths[nframes++]; 1248 1249 if (nframes >= xfer->ux_nframes) 1250 break; 1251 } 1252 1253 xfer->ux_actlen = actlen; 1254 xfer->ux_status = USBD_NORMAL_COMPLETION; 1255 goto end; 1256 } 1257 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1258 ex->ex_type == EX_BULK); 1259 1260 /* Continue processing xfers using queue heads */ 1261 if (ex->ex_type == EX_CTRL) { 1262 fsqtd = ex->ex_setup; 1263 lsqtd = ex->ex_status; 1264 } else { 1265 fsqtd = ex->ex_sqtdstart; 1266 lsqtd = ex->ex_sqtdend; 1267 } 1268 #ifdef EHCI_DEBUG 1269 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1270 ehci_dump_sqtds(fsqtd); 1271 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1272 #endif 1273 1274 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1275 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 1276 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1277 nstatus = le32toh(sqtd->qtd->qtd_status); 1278 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 1279 BUS_DMASYNC_PREREAD); 1280 if (nstatus & EHCI_QTD_ACTIVE) 1281 break; 1282 1283 status = nstatus; 1284 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1285 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1286 } 1287 1288 /* 1289 * If there are left over TDs we need to update the toggle. 1290 * The default pipe doesn't need it since control transfers 1291 * start the toggle at 0 every time. 1292 * For a short transfer we need to update the toggle for the missing 1293 * packets within the qTD. 1294 */ 1295 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1296 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1297 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1298 status, nstatus, 0, 0); 1299 #if 0 1300 ehci_dump_sqh(epipe->sqh); 1301 ehci_dump_sqtds(ex->ex_sqtdstart); 1302 #endif 1303 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1304 } 1305 1306 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1307 status, 0); 1308 xfer->ux_actlen = actlen; 1309 if (status & EHCI_QTD_HALTED) { 1310 #ifdef EHCI_DEBUG 1311 DPRINTF("halted addr=%jd endpt=0x%02jx", 1312 xfer->ux_pipe->up_dev->ud_addr, 1313 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1314 0, 0); 1315 DPRINTF("cerr=%jd pid=%jd", 1316 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1317 0, 0); 1318 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1319 status & EHCI_QTD_ACTIVE ? 1 : 0, 1320 status & EHCI_QTD_HALTED ? 1 : 0, 1321 status & EHCI_QTD_BUFERR ? 1 : 0, 1322 status & EHCI_QTD_BABBLE ? 1 : 0); 1323 1324 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1325 status & EHCI_QTD_XACTERR ? 1 : 0, 1326 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1327 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1328 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1329 1330 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1331 ehci_dump_sqh(epipe->sqh); 1332 ehci_dump_sqtds(ex->ex_sqtdstart); 1333 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1334 #endif 1335 /* low&full speed has an extra error flag */ 1336 if (EHCI_QH_GET_EPS(epipe->sqh->qh->qh_endp) != 1337 EHCI_QH_SPEED_HIGH) 1338 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1339 else 1340 status &= EHCI_QTD_STATERRS; 1341 if (status == 0) /* no other errors means a stall */ { 1342 xfer->ux_status = USBD_STALLED; 1343 } else { 1344 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1345 } 1346 /* XXX need to reset TT on missed microframe */ 1347 if (status & EHCI_QTD_MISSEDMICRO) { 1348 printf("%s: missed microframe, TT reset not " 1349 "implemented, hub might be inoperational\n", 1350 device_xname(sc->sc_dev)); 1351 } 1352 } else { 1353 xfer->ux_status = USBD_NORMAL_COMPLETION; 1354 } 1355 1356 end: 1357 1358 ehci_del_intr_list(sc, ex); 1359 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1360 1361 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1362 } 1363 1364 Static void 1365 ehci_poll(struct usbd_bus *bus) 1366 { 1367 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1368 1369 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1370 1371 #ifdef EHCI_DEBUG 1372 static int last; 1373 int new; 1374 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1375 if (new != last) { 1376 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1377 last = new; 1378 } 1379 #endif 1380 1381 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1382 mutex_spin_enter(&sc->sc_intr_lock); 1383 ehci_intr1(sc); 1384 mutex_spin_exit(&sc->sc_intr_lock); 1385 } 1386 } 1387 1388 void 1389 ehci_childdet(device_t self, device_t child) 1390 { 1391 struct ehci_softc *sc = device_private(self); 1392 1393 KASSERT(sc->sc_child == child); 1394 sc->sc_child = NULL; 1395 } 1396 1397 int 1398 ehci_detach(struct ehci_softc *sc, int flags) 1399 { 1400 int rv = 0; 1401 1402 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1403 1404 if (sc->sc_child != NULL) { 1405 rv = config_detach(sc->sc_child, flags); 1406 if (rv != 0) 1407 return rv; 1408 } 1409 1410 if (sc->sc_ncomp > 0) { 1411 mutex_enter(&sc->sc_complock); 1412 /* XXX try to halt callout instead of waiting */ 1413 while (sc->sc_comp_state == CO_SCHED) 1414 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1415 mutex_exit(&sc->sc_complock); 1416 1417 callout_halt(&sc->sc_compcallout, NULL); 1418 callout_destroy(&sc->sc_compcallout); 1419 cv_destroy(&sc->sc_compcv); 1420 mutex_destroy(&sc->sc_complock); 1421 } 1422 1423 callout_halt(&sc->sc_tmo_intrlist, NULL); 1424 callout_destroy(&sc->sc_tmo_intrlist); 1425 1426 /* XXX free other data structures */ 1427 if (sc->sc_softitds) { 1428 kmem_free(sc->sc_softitds, 1429 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1430 } 1431 cv_destroy(&sc->sc_doorbell); 1432 1433 #if 0 1434 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1435 softint_disestablish(sc->sc_doorbell_si); 1436 softint_disestablish(sc->sc_pcd_si); 1437 mutex_destroy(&sc->sc_rhlock); 1438 mutex_destroy(&sc->sc_lock); 1439 mutex_destroy(&sc->sc_intr_lock); 1440 #endif 1441 1442 pool_cache_destroy(sc->sc_xferpool); 1443 1444 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1445 1446 return rv; 1447 } 1448 1449 int 1450 ehci_activate(device_t self, enum devact act) 1451 { 1452 struct ehci_softc *sc = device_private(self); 1453 1454 switch (act) { 1455 case DVACT_DEACTIVATE: 1456 sc->sc_dying = 1; 1457 return 0; 1458 default: 1459 return EOPNOTSUPP; 1460 } 1461 } 1462 1463 /* 1464 * Handle suspend/resume. 1465 * 1466 * Note that this power handler isn't to be registered directly; the 1467 * bus glue needs to call out to it. 1468 */ 1469 bool 1470 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1471 { 1472 ehci_softc_t *sc = device_private(dv); 1473 int i; 1474 uint32_t cmd, hcr; 1475 1476 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1477 1478 mutex_enter(&sc->sc_rhlock); 1479 1480 for (i = 1; i <= sc->sc_noport; i++) { 1481 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1482 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1483 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1484 } 1485 1486 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1487 1488 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1489 EOWRITE4(sc, EHCI_USBCMD, cmd); 1490 1491 for (i = 0; i < 100; i++) { 1492 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1493 if (hcr == 0) 1494 break; 1495 1496 usb_delay_ms(&sc->sc_bus, 1); 1497 } 1498 if (hcr != 0) 1499 printf("%s: reset timeout\n", device_xname(dv)); 1500 1501 cmd &= ~EHCI_CMD_RS; 1502 EOWRITE4(sc, EHCI_USBCMD, cmd); 1503 1504 for (i = 0; i < 100; i++) { 1505 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1506 if (hcr == EHCI_STS_HCH) 1507 break; 1508 1509 usb_delay_ms(&sc->sc_bus, 1); 1510 } 1511 if (hcr != EHCI_STS_HCH) 1512 printf("%s: config timeout\n", device_xname(dv)); 1513 1514 mutex_exit(&sc->sc_rhlock); 1515 1516 return true; 1517 } 1518 1519 bool 1520 ehci_resume(device_t dv, const pmf_qual_t *qual) 1521 { 1522 ehci_softc_t *sc = device_private(dv); 1523 int i; 1524 uint32_t cmd, hcr; 1525 1526 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1527 1528 mutex_enter(&sc->sc_rhlock); 1529 1530 /* restore things in case the bios sucks */ 1531 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1532 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1533 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1534 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1535 1536 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1537 1538 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1539 1540 hcr = 0; 1541 for (i = 1; i <= sc->sc_noport; i++) { 1542 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1543 if ((cmd & EHCI_PS_PO) == 0 && 1544 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1545 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1546 hcr = 1; 1547 } 1548 } 1549 1550 if (hcr) { 1551 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1552 1553 for (i = 1; i <= sc->sc_noport; i++) { 1554 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1555 if ((cmd & EHCI_PS_PO) == 0 && 1556 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1557 EOWRITE4(sc, EHCI_PORTSC(i), 1558 cmd & ~EHCI_PS_FPR); 1559 } 1560 } 1561 1562 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1563 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1564 1565 for (i = 0; i < 100; i++) { 1566 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1567 if (hcr != EHCI_STS_HCH) 1568 break; 1569 1570 usb_delay_ms(&sc->sc_bus, 1); 1571 } 1572 if (hcr == EHCI_STS_HCH) 1573 printf("%s: config timeout\n", device_xname(dv)); 1574 1575 mutex_exit(&sc->sc_rhlock); 1576 1577 return true; 1578 } 1579 1580 /* 1581 * Shut down the controller when the system is going down. 1582 */ 1583 bool 1584 ehci_shutdown(device_t self, int flags) 1585 { 1586 ehci_softc_t *sc = device_private(self); 1587 1588 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1589 1590 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1591 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1592 return true; 1593 } 1594 1595 Static struct usbd_xfer * 1596 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1597 { 1598 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1599 struct usbd_xfer *xfer; 1600 1601 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1602 if (xfer != NULL) { 1603 memset(xfer, 0, sizeof(*xfer)); 1604 1605 #ifdef DIAGNOSTIC 1606 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1607 ex->ex_isdone = true; 1608 xfer->ux_state = XFER_BUSY; 1609 #endif 1610 } 1611 return xfer; 1612 } 1613 1614 Static void 1615 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1616 { 1617 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1618 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1619 1620 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1621 xfer->ux_status == USBD_NOT_STARTED, 1622 "xfer %p state %d\n", xfer, xfer->ux_state); 1623 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1624 1625 #ifdef DIAGNOSTIC 1626 xfer->ux_state = XFER_FREE; 1627 #endif 1628 1629 pool_cache_put(sc->sc_xferpool, xfer); 1630 } 1631 1632 Static bool 1633 ehci_dying(struct usbd_bus *bus) 1634 { 1635 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1636 1637 return sc->sc_dying; 1638 } 1639 1640 Static void 1641 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1642 { 1643 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1644 1645 *lock = &sc->sc_lock; 1646 } 1647 1648 Static void 1649 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1650 { 1651 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1652 1653 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1654 1655 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1656 epipe->sqh->qh->qh_qtd.qtd_status, 0, 0); 1657 #ifdef EHCI_DEBUG 1658 if (ehcidebug) 1659 usbd_dump_pipe(pipe); 1660 #endif 1661 epipe->nexttoggle = 0; 1662 } 1663 1664 Static void 1665 ehci_noop(struct usbd_pipe *pipe) 1666 { 1667 } 1668 1669 #ifdef EHCI_DEBUG 1670 /* 1671 * Unused function - this is meant to be called from a kernel 1672 * debugger. 1673 */ 1674 void 1675 ehci_dump(void) 1676 { 1677 ehci_softc_t *sc = theehci; 1678 int i; 1679 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1680 EOREAD4(sc, EHCI_USBCMD), 1681 EOREAD4(sc, EHCI_USBSTS), 1682 EOREAD4(sc, EHCI_USBINTR)); 1683 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1684 EOREAD4(sc, EHCI_FRINDEX), 1685 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1686 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1687 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1688 for (i = 1; i <= sc->sc_noport; i++) 1689 printf("port %d status=0x%08x\n", i, 1690 EOREAD4(sc, EHCI_PORTSC(i))); 1691 } 1692 1693 Static void 1694 ehci_dump_regs(ehci_softc_t *sc) 1695 { 1696 int i; 1697 1698 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1699 1700 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1701 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1702 EOREAD4(sc, EHCI_USBINTR), 0); 1703 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1704 "async = 0x%08jx", 1705 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1706 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1707 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1708 for (i = 1; i <= sc->sc_noport; i += 2) { 1709 if (i == sc->sc_noport) { 1710 DPRINTF("port %jd status = 0x%08jx", i, 1711 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1712 } else { 1713 DPRINTF("port %jd status = 0x%08jx port %jd " 1714 "status = 0x%08jx", 1715 i, EOREAD4(sc, EHCI_PORTSC(i)), 1716 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1717 } 1718 } 1719 } 1720 1721 #define ehci_dump_link(link, type) do { \ 1722 DPRINTF(" link 0x%08jx (T = %jd):", \ 1723 link, \ 1724 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1725 if (type) { \ 1726 DPRINTF( \ 1727 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1728 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1729 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1730 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1731 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1732 } \ 1733 } while(0) 1734 1735 Static void 1736 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1737 { 1738 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1739 int i; 1740 uint32_t stop = 0; 1741 1742 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1743 ehci_dump_sqtd(sqtd); 1744 usb_syncmem(&sqtd->dma, 1745 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1746 sizeof(sqtd->qtd->qtd_next), 1747 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1748 stop = sqtd->qtd->qtd_next & htole32(EHCI_LINK_TERMINATE); 1749 usb_syncmem(&sqtd->dma, 1750 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1751 sizeof(sqtd->qtd->qtd_next), BUS_DMASYNC_PREREAD); 1752 } 1753 if (!stop) 1754 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1755 } 1756 1757 Static void 1758 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1759 { 1760 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1761 1762 usb_syncmem(&sqtd->dma, sqtd->offs, 1763 sizeof(*sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1764 1765 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1766 0, 0); 1767 ehci_dump_qtd(sqtd->qtd); 1768 1769 usb_syncmem(&sqtd->dma, sqtd->offs, 1770 sizeof(*sqtd->qtd), BUS_DMASYNC_PREREAD); 1771 } 1772 1773 Static void 1774 ehci_dump_qh_qtd(struct ehci_qh_qtd_t *qh_qtd) 1775 { 1776 ehci_qtd_t qtd = { 1777 .qtd_next = qh_qtd->qtd_next, 1778 .qtd_altnext = qh_qtd->qtd_altnext, 1779 .qtd_status = qh_qtd->qtd_status, 1780 }; 1781 1782 /* Manually memcpy(), because of volatile. */ 1783 for (unsigned i = 0; i < EHCI_QTD_NBUFFERS; i++) { 1784 qtd.qtd_buffer[i] = qh_qtd->qtd_buffer[i]; 1785 qtd.qtd_buffer_hi[i] = qh_qtd->qtd_buffer_hi[i]; 1786 } 1787 1788 ehci_dump_qtd(&qtd); 1789 } 1790 1791 Static void 1792 ehci_dump_qtd(ehci_qtd_t *qtd) 1793 { 1794 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1795 uint32_t s = le32toh(qtd->qtd_status); 1796 1797 DPRINTFN(10, 1798 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1799 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1800 DPRINTFN(10, 1801 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1802 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1803 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1804 DPRINTFN(10, 1805 " cerr = %jd pid = %jd stat = %jx", 1806 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1807 0); 1808 DPRINTFN(10, 1809 "active =%jd halted=%jd buferr=%jd babble=%jd", 1810 s & EHCI_QTD_ACTIVE ? 1 : 0, 1811 s & EHCI_QTD_HALTED ? 1 : 0, 1812 s & EHCI_QTD_BUFERR ? 1 : 0, 1813 s & EHCI_QTD_BABBLE ? 1 : 0); 1814 DPRINTFN(10, 1815 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1816 s & EHCI_QTD_XACTERR ? 1 : 0, 1817 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1818 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1819 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1820 DPRINTFN(10, 1821 "buffer[0] = %#jx buffer[1] = %#jx " 1822 "buffer[2] = %#jx buffer[3] = %#jx", 1823 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1824 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1825 DPRINTFN(10, 1826 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1827 } 1828 1829 Static void 1830 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1831 { 1832 ehci_qh_t *qh = sqh->qh; 1833 ehci_link_t link; 1834 uint32_t endp, endphub; 1835 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1836 1837 usb_syncmem(&sqh->dma, sqh->offs, 1838 sizeof(*sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1839 1840 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1841 link = le32toh(qh->qh_link); 1842 ehci_dump_link(link, true); 1843 1844 endp = le32toh(qh->qh_endp); 1845 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1846 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1847 "eps = %jd", 1848 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1849 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1850 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1851 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1852 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1853 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1854 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1855 1856 endphub = le32toh(qh->qh_endphub); 1857 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1858 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1859 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1860 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1861 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1862 EHCI_QH_GET_MULT(endphub), 0); 1863 1864 link = le32toh(qh->qh_curqtd); 1865 ehci_dump_link(link, false); 1866 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1867 ehci_dump_qh_qtd(&qh->qh_qtd); 1868 1869 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 1870 BUS_DMASYNC_PREREAD); 1871 } 1872 1873 Static void 1874 ehci_dump_itds(ehci_soft_itd_t *itd) 1875 { 1876 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1877 int i; 1878 uint32_t stop = 0; 1879 1880 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1881 ehci_dump_itd(itd); 1882 usb_syncmem(&itd->dma, 1883 itd->offs + offsetof(ehci_itd_t, itd_next), 1884 sizeof(itd->itd->itd_next), 1885 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1886 stop = itd->itd->itd_next & htole32(EHCI_LINK_TERMINATE); 1887 usb_syncmem(&itd->dma, 1888 itd->offs + offsetof(ehci_itd_t, itd_next), 1889 sizeof(itd->itd->itd_next), BUS_DMASYNC_PREREAD); 1890 } 1891 if (!stop) 1892 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1893 } 1894 1895 Static void 1896 ehci_dump_itd(struct ehci_soft_itd *itd) 1897 { 1898 ehci_isoc_trans_t t; 1899 ehci_isoc_bufr_ptr_t b, b2, b3; 1900 int i; 1901 1902 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1903 1904 DPRINTF("ITD: next phys = %#jx", itd->itd->itd_next, 0, 0, 0); 1905 1906 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1907 t = le32toh(itd->itd->itd_ctl[i]); 1908 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1909 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1910 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1911 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1912 EHCI_ITD_GET_OFFS(t), 0); 1913 } 1914 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1915 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1916 DPRINTF(" %jx", 1917 EHCI_ITD_GET_BPTR(le32toh(itd->itd->itd_bufr[i])), 0, 0, 0); 1918 1919 b = le32toh(itd->itd->itd_bufr[0]); 1920 b2 = le32toh(itd->itd->itd_bufr[1]); 1921 b3 = le32toh(itd->itd->itd_bufr[2]); 1922 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1923 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1924 DPRINTF(" maxpkt = %jx multi = %jx", 1925 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1926 } 1927 1928 Static void 1929 ehci_dump_sitd(struct ehci_soft_itd *itd) 1930 { 1931 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1932 1933 DPRINTF("SITD %#jx next = %p prev = %#jx", 1934 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1935 (uintptr_t)itd->frame_list.prev, 0); 1936 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1937 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1938 } 1939 1940 Static void 1941 ehci_dump_exfer(struct ehci_xfer *ex) 1942 { 1943 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1944 1945 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1946 ex->ex_isdone, 0); 1947 1948 switch (ex->ex_type) { 1949 case EX_CTRL: 1950 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1951 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1952 (uintptr_t)ex->ex_status, 0); 1953 break; 1954 case EX_BULK: 1955 case EX_INTR: 1956 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1957 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1958 0, 0); 1959 break; 1960 case EX_ISOC: 1961 DPRINTF(" itdstart = %#jx itdend = %#jx", 1962 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1963 break; 1964 case EX_FS_ISOC: 1965 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1966 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1967 0, 0); 1968 break; 1969 default: 1970 DPRINTF(" unknown type", 0, 0, 0, 0); 1971 } 1972 } 1973 #endif 1974 1975 Static usbd_status 1976 ehci_open(struct usbd_pipe *pipe) 1977 { 1978 struct usbd_device *dev = pipe->up_dev; 1979 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1980 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1981 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1982 uint8_t addr = dev->ud_addr; 1983 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1984 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1985 ehci_soft_qh_t *sqh; 1986 usbd_status err; 1987 int ival, speed, naks; 1988 int hshubaddr, hshubport; 1989 1990 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1991 1992 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1993 ed->bEndpointAddress, rhaddr); 1994 1995 if (dev->ud_myhsport) { 1996 /* 1997 * When directly attached FS/LS device while doing embedded 1998 * transaction translations and we are the hub, set the hub 1999 * address to 0 (us). 2000 */ 2001 if (!(sc->sc_flags & EHCIF_ETTF) 2002 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 2003 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 2004 } else { 2005 hshubaddr = 0; 2006 } 2007 hshubport = dev->ud_myhsport->up_portno; 2008 } else { 2009 hshubaddr = 0; 2010 hshubport = 0; 2011 } 2012 2013 if (sc->sc_dying) 2014 return USBD_IOERROR; 2015 2016 /* toggle state needed for bulk endpoints */ 2017 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 2018 2019 if (addr == rhaddr) { 2020 switch (ed->bEndpointAddress) { 2021 case USB_CONTROL_ENDPOINT: 2022 pipe->up_methods = &roothub_ctrl_methods; 2023 break; 2024 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2025 pipe->up_methods = &ehci_root_intr_methods; 2026 break; 2027 default: 2028 DPRINTF("bad bEndpointAddress 0x%02jx", 2029 ed->bEndpointAddress, 0, 0, 0); 2030 return USBD_INVAL; 2031 } 2032 return USBD_NORMAL_COMPLETION; 2033 } 2034 2035 /* XXX All this stuff is only valid for async. */ 2036 switch (dev->ud_speed) { 2037 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 2038 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 2039 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 2040 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 2041 } 2042 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 2043 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 2044 0); 2045 return USBD_INVAL; 2046 } 2047 2048 /* 2049 * For interrupt transfer, nak throttling must be disabled, but for 2050 * the other transfer type, nak throttling should be enabled from the 2051 * viewpoint that avoids the memory thrashing. 2052 */ 2053 naks = (xfertype == UE_INTERRUPT) ? 0 2054 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 2055 2056 /* Allocate sqh for everything, save isoc xfers */ 2057 if (xfertype != UE_ISOCHRONOUS) { 2058 sqh = ehci_alloc_sqh(sc); 2059 if (sqh == NULL) 2060 return USBD_NOMEM; 2061 /* qh_link filled when the QH is added */ 2062 sqh->qh->qh_endp = htole32( 2063 EHCI_QH_SET_ADDR(addr) | 2064 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 2065 EHCI_QH_SET_EPS(speed) | 2066 EHCI_QH_DTC | 2067 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 2068 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 2069 EHCI_QH_CTL : 0) | 2070 EHCI_QH_SET_NRL(naks) 2071 ); 2072 sqh->qh->qh_endphub = htole32( 2073 EHCI_QH_SET_MULT(1) | 2074 (xfertype == UE_INTERRUPT ? 2075 EHCI_QH_SET_SMASK(__BIT(1)) /* Start Split Y1 */ 2076 : 0) 2077 ); 2078 if (speed != EHCI_QH_SPEED_HIGH) 2079 sqh->qh->qh_endphub |= htole32( 2080 EHCI_QH_SET_PORT(hshubport) | 2081 EHCI_QH_SET_HUBA(hshubaddr) | 2082 (xfertype == UE_INTERRUPT ? 2083 EHCI_QH_SET_CMASK(__BITS(3,5)) /* CS Y[345] */ 2084 : 0) 2085 ); 2086 sqh->qh->qh_curqtd = EHCI_NULL; 2087 /* Fill the overlay qTD */ 2088 sqh->qh->qh_qtd.qtd_next = EHCI_NULL; 2089 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 2090 sqh->qh->qh_qtd.qtd_status = htole32(0); 2091 2092 ehci_qtd_t *qh_qtd = &sqh->qh->qh_qtd; 2093 for (unsigned n = 0; n < EHCI_QTD_NBUFFERS; n++) { 2094 qh_qtd->qtd_buffer[n] = 0; 2095 qh_qtd->qtd_buffer_hi[n] = 0; 2096 } 2097 2098 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 2099 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2100 epipe->sqh = sqh; 2101 } else { 2102 sqh = NULL; 2103 } /*xfertype == UE_ISOC*/ 2104 2105 switch (xfertype) { 2106 case UE_CONTROL: 2107 /* we can use 64bit DMA for the reqdma buffer */ 2108 err = usb_allocmem(sc->sc_bus.ub_dmatag, 2109 sizeof(usb_device_request_t), 0, USBMALLOC_COHERENT, 2110 &epipe->ctrl.reqdma); 2111 #ifdef EHCI_DEBUG 2112 if (err) 2113 printf("ehci_open: usb_allocmem()=%d\n", err); 2114 #endif 2115 if (err) 2116 goto bad; 2117 pipe->up_methods = &ehci_device_ctrl_methods; 2118 mutex_enter(&sc->sc_lock); 2119 ehci_add_qh(sc, sqh, sc->sc_async_head); 2120 mutex_exit(&sc->sc_lock); 2121 break; 2122 case UE_BULK: 2123 pipe->up_methods = &ehci_device_bulk_methods; 2124 mutex_enter(&sc->sc_lock); 2125 ehci_add_qh(sc, sqh, sc->sc_async_head); 2126 mutex_exit(&sc->sc_lock); 2127 break; 2128 case UE_INTERRUPT: 2129 pipe->up_methods = &ehci_device_intr_methods; 2130 ival = pipe->up_interval; 2131 if (ival == USBD_DEFAULT_INTERVAL) { 2132 if (speed == EHCI_QH_SPEED_HIGH) { 2133 if (ed->bInterval > 16) { 2134 /* 2135 * illegal with high-speed, but there 2136 * were documentation bugs in the spec, 2137 * so be generous 2138 */ 2139 ival = 256; 2140 } else 2141 ival = (1 << (ed->bInterval - 1)) / 8; 2142 } else 2143 ival = ed->bInterval; 2144 } 2145 err = ehci_device_setintr(sc, sqh, ival); 2146 if (err) 2147 goto bad; 2148 break; 2149 case UE_ISOCHRONOUS: 2150 pipe->up_serialise = false; 2151 if (speed == EHCI_QH_SPEED_HIGH) 2152 pipe->up_methods = &ehci_device_isoc_methods; 2153 else 2154 pipe->up_methods = &ehci_device_fs_isoc_methods; 2155 if (ed->bInterval == 0 || ed->bInterval > 16) { 2156 printf("ehci: opening pipe with invalid bInterval\n"); 2157 err = USBD_INVAL; 2158 goto bad; 2159 } 2160 if (UGETW(ed->wMaxPacketSize) == 0) { 2161 printf("ehci: zero length endpoint open request\n"); 2162 err = USBD_INVAL; 2163 goto bad; 2164 } 2165 epipe->isoc.next_frame = 0; 2166 epipe->isoc.cur_xfers = 0; 2167 break; 2168 default: 2169 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2170 err = USBD_INVAL; 2171 goto bad; 2172 } 2173 return USBD_NORMAL_COMPLETION; 2174 2175 bad: 2176 if (sqh != NULL) { 2177 mutex_enter(&sc->sc_lock); 2178 ehci_free_sqh(sc, sqh); 2179 mutex_exit(&sc->sc_lock); 2180 } 2181 return err; 2182 } 2183 2184 /* 2185 * Add an ED to the schedule. Called with USB lock held. 2186 */ 2187 Static void 2188 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2189 { 2190 2191 KASSERT(mutex_owned(&sc->sc_lock)); 2192 2193 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2194 2195 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2196 sizeof(head->qh->qh_link), BUS_DMASYNC_POSTWRITE); 2197 2198 sqh->next = head->next; 2199 sqh->qh->qh_link = head->qh->qh_link; 2200 2201 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2202 sizeof(sqh->qh->qh_link), BUS_DMASYNC_PREWRITE); 2203 2204 head->next = sqh; 2205 head->qh->qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2206 2207 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2208 sizeof(head->qh->qh_link), BUS_DMASYNC_PREWRITE); 2209 2210 #ifdef EHCI_DEBUG 2211 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2212 ehci_dump_sqh(sqh); 2213 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2214 #endif 2215 } 2216 2217 /* 2218 * Remove an ED from the schedule. Called with USB lock held. 2219 */ 2220 Static void 2221 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2222 { 2223 ehci_soft_qh_t *p; 2224 2225 KASSERT(mutex_owned(&sc->sc_lock)); 2226 2227 /* XXX */ 2228 for (p = head; p != NULL && p->next != sqh; p = p->next) 2229 ; 2230 if (p == NULL) 2231 panic("ehci_rem_qh: ED not found"); 2232 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2233 sizeof(sqh->qh->qh_link), BUS_DMASYNC_POSTWRITE); 2234 p->next = sqh->next; 2235 p->qh->qh_link = sqh->qh->qh_link; 2236 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2237 sizeof(p->qh->qh_link), BUS_DMASYNC_PREWRITE); 2238 2239 ehci_sync_hc(sc); 2240 } 2241 2242 Static void 2243 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2244 { 2245 uint32_t status; 2246 2247 /* Save toggle bit and ping status. */ 2248 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 2249 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2250 status = sqh->qh->qh_qtd.qtd_status & 2251 htole32(EHCI_QTD_TOGGLE_MASK | 2252 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2253 /* Set HALTED to make hw leave it alone. */ 2254 sqh->qh->qh_qtd.qtd_status = 2255 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2256 usb_syncmem(&sqh->dma, 2257 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2258 sizeof(sqh->qh->qh_qtd.qtd_status), 2259 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2260 sqh->qh->qh_curqtd = 0; 2261 sqh->qh->qh_qtd.qtd_next = htole32(sqtd->physaddr); 2262 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 2263 for (unsigned n = 0; n < EHCI_QTD_NBUFFERS; n++) { 2264 sqh->qh->qh_qtd.qtd_buffer[n] = 0; 2265 sqh->qh->qh_qtd.qtd_buffer_hi[n] = 0; 2266 } 2267 2268 sqh->sqtd = sqtd; 2269 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 2270 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2271 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2272 sqh->qh->qh_qtd.qtd_status = status; 2273 usb_syncmem(&sqh->dma, 2274 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2275 sizeof(sqh->qh->qh_qtd.qtd_status), 2276 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2277 } 2278 2279 /* 2280 * Ensure that the HC has released all references to the QH. We do this 2281 * by asking for a Async Advance Doorbell interrupt and then we wait for 2282 * the interrupt. 2283 * To make this easier we first obtain exclusive use of the doorbell. 2284 * 2285 * Releases the bus lock to sleep while waiting for interrupt. 2286 */ 2287 Static void 2288 ehci_sync_hc(ehci_softc_t *sc) 2289 { 2290 unsigned delta = hz; 2291 unsigned starttime = getticks(); 2292 unsigned endtime = starttime + delta; 2293 unsigned now; 2294 2295 KASSERT(mutex_owned(&sc->sc_lock)); 2296 2297 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2298 2299 if (sc->sc_dying) { 2300 DPRINTF("dying", 0, 0, 0, 0); 2301 return; 2302 } 2303 2304 /* 2305 * Wait until any concurrent ehci_sync_hc has completed so we 2306 * have exclusive access to the doorbell. 2307 */ 2308 while (sc->sc_doorbelllwp) 2309 cv_wait(&sc->sc_doorbell, &sc->sc_lock); 2310 sc->sc_doorbelllwp = curlwp; 2311 2312 /* ask for doorbell */ 2313 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2314 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2315 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2316 2317 /* 2318 * Wait for the ehci to ring our doorbell. 2319 */ 2320 while (sc->sc_doorbelllwp == curlwp) { 2321 now = getticks(); 2322 if (now - starttime >= delta) { 2323 sc->sc_doorbelllwp = NULL; 2324 cv_broadcast(&sc->sc_doorbell); 2325 DPRINTF("doorbell timeout", 0, 0, 0, 0); 2326 #ifdef DIAGNOSTIC /* XXX DIAGNOSTIC abuse, do this differently */ 2327 printf("ehci_sync_hc: timed out\n"); 2328 #endif 2329 break; 2330 } 2331 (void)cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, 2332 endtime - now); 2333 } 2334 2335 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2336 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2337 } 2338 2339 Static void 2340 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2341 { 2342 2343 KASSERT(mutex_owned(&sc->sc_lock)); 2344 2345 for (; itd != NULL; itd = itd->xfer_next) { 2346 struct ehci_soft_itd *prev = itd->frame_list.prev; 2347 2348 /* Unlink itd from hardware chain, or frame array */ 2349 if (prev == NULL) { /* We're at the table head */ 2350 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2351 sc->sc_flist[itd->slot] = itd->itd->itd_next; 2352 usb_syncmem(&sc->sc_fldma, 2353 sizeof(ehci_link_t) * itd->slot, 2354 sizeof(ehci_link_t), 2355 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2356 2357 if (itd->frame_list.next != NULL) 2358 itd->frame_list.next->frame_list.prev = NULL; 2359 } else { 2360 /* XXX this part is untested... */ 2361 prev->itd->itd_next = itd->itd->itd_next; 2362 usb_syncmem(&itd->dma, 2363 itd->offs + offsetof(ehci_itd_t, itd_next), 2364 sizeof(itd->itd->itd_next), BUS_DMASYNC_PREWRITE); 2365 2366 prev->frame_list.next = itd->frame_list.next; 2367 if (itd->frame_list.next != NULL) 2368 itd->frame_list.next->frame_list.prev = prev; 2369 } 2370 } 2371 } 2372 2373 Static void 2374 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2375 { 2376 struct ehci_soft_itd *next; 2377 2378 mutex_enter(&sc->sc_lock); 2379 next = NULL; 2380 for (; itd != NULL; itd = next) { 2381 next = itd->xfer_next; 2382 ehci_free_itd_locked(sc, itd); 2383 } 2384 mutex_exit(&sc->sc_lock); 2385 } 2386 2387 Static void 2388 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2389 { 2390 2391 KASSERT(mutex_owned(&sc->sc_lock)); 2392 2393 for (; sitd != NULL; sitd = sitd->xfer_next) { 2394 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2395 2396 /* Unlink sitd from hardware chain, or frame array */ 2397 if (prev == NULL) { /* We're at the table head */ 2398 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2399 sc->sc_flist[sitd->slot] = sitd->sitd->sitd_next; 2400 usb_syncmem(&sc->sc_fldma, 2401 sizeof(ehci_link_t) * sitd->slot, 2402 sizeof(ehci_link_t), 2403 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2404 2405 if (sitd->frame_list.next != NULL) 2406 sitd->frame_list.next->frame_list.prev = NULL; 2407 } else { 2408 /* XXX this part is untested... */ 2409 prev->sitd->sitd_next = sitd->sitd->sitd_next; 2410 usb_syncmem(&sitd->dma, 2411 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2412 sizeof(sitd->sitd->sitd_next), BUS_DMASYNC_PREWRITE); 2413 2414 prev->frame_list.next = sitd->frame_list.next; 2415 if (sitd->frame_list.next != NULL) 2416 sitd->frame_list.next->frame_list.prev = prev; 2417 } 2418 } 2419 } 2420 2421 Static void 2422 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2423 { 2424 2425 mutex_enter(&sc->sc_lock); 2426 struct ehci_soft_sitd *next = NULL; 2427 for (; sitd != NULL; sitd = next) { 2428 next = sitd->xfer_next; 2429 ehci_free_sitd_locked(sc, sitd); 2430 } 2431 mutex_exit(&sc->sc_lock); 2432 } 2433 2434 /***********/ 2435 2436 static int 2437 ehci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req, 2438 void *buf, int buflen) 2439 { 2440 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2441 usb_hub_descriptor_t hubd; 2442 usb_port_status_t ps; 2443 uint16_t len, value, index; 2444 int l, totlen = 0; 2445 int port, i; 2446 uint32_t v; 2447 2448 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2449 2450 KASSERT(mutex_owned(&sc->sc_rhlock)); 2451 2452 if (sc->sc_dying) 2453 return -1; 2454 2455 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2456 0, 0); 2457 2458 len = UGETW(req->wLength); 2459 value = UGETW(req->wValue); 2460 index = UGETW(req->wIndex); 2461 2462 #define C(x,y) ((x) | ((y) << 8)) 2463 switch (C(req->bRequest, req->bmRequestType)) { 2464 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2465 if (len == 0) 2466 break; 2467 switch (value) { 2468 #define sd ((usb_string_descriptor_t *)buf) 2469 case C(2, UDESC_STRING): 2470 /* Product */ 2471 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2472 break; 2473 #undef sd 2474 default: 2475 /* default from usbroothub */ 2476 return buflen; 2477 } 2478 break; 2479 2480 /* Hub requests */ 2481 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2482 break; 2483 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2484 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2485 value, 0, 0); 2486 if (index < 1 || index > sc->sc_noport) { 2487 return -1; 2488 } 2489 port = EHCI_PORTSC(index); 2490 v = EOREAD4(sc, port); 2491 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2492 v &= ~EHCI_PS_CLEAR; 2493 switch (value) { 2494 case UHF_PORT_ENABLE: 2495 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2496 break; 2497 case UHF_PORT_SUSPEND: 2498 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2499 break; 2500 v &= ~EHCI_PS_SUSP; 2501 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2502 /* see USB2 spec ch. 7.1.7.7 */ 2503 usb_delay_ms(&sc->sc_bus, 20); 2504 EOWRITE4(sc, port, v); 2505 usb_delay_ms(&sc->sc_bus, 2); 2506 #ifdef DEBUG 2507 v = EOREAD4(sc, port); 2508 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2509 printf("ehci: resume failed: %x\n", v); 2510 #endif 2511 break; 2512 case UHF_PORT_POWER: 2513 if (sc->sc_hasppc) 2514 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2515 break; 2516 case UHF_PORT_TEST: 2517 DPRINTF("clear port test %jd", index, 0, 0, 0); 2518 break; 2519 case UHF_PORT_INDICATOR: 2520 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2521 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2522 break; 2523 case UHF_C_PORT_CONNECTION: 2524 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2525 break; 2526 case UHF_C_PORT_ENABLE: 2527 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2528 break; 2529 case UHF_C_PORT_SUSPEND: 2530 /* how? */ 2531 break; 2532 case UHF_C_PORT_OVER_CURRENT: 2533 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2534 break; 2535 case UHF_C_PORT_RESET: 2536 sc->sc_isreset[index] = 0; 2537 break; 2538 default: 2539 return -1; 2540 } 2541 #if 0 2542 switch(value) { 2543 case UHF_C_PORT_CONNECTION: 2544 case UHF_C_PORT_ENABLE: 2545 case UHF_C_PORT_SUSPEND: 2546 case UHF_C_PORT_OVER_CURRENT: 2547 case UHF_C_PORT_RESET: 2548 default: 2549 break; 2550 } 2551 #endif 2552 break; 2553 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2554 if (len == 0) 2555 break; 2556 if ((value & 0xff) != 0) { 2557 return -1; 2558 } 2559 totlen = uimin(buflen, sizeof(hubd)); 2560 memcpy(&hubd, buf, totlen); 2561 hubd.bNbrPorts = sc->sc_noport; 2562 v = EREAD4(sc, EHCI_HCSPARAMS); 2563 USETW(hubd.wHubCharacteristics, 2564 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2565 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2566 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2567 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2568 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2569 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2570 totlen = uimin(totlen, hubd.bDescLength); 2571 memcpy(buf, &hubd, totlen); 2572 break; 2573 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2574 if (len != 4) { 2575 return -1; 2576 } 2577 memset(buf, 0, len); /* ? XXX */ 2578 totlen = len; 2579 break; 2580 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2581 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2582 if (index < 1 || index > sc->sc_noport) { 2583 return -1; 2584 } 2585 if (len != 4) { 2586 return -1; 2587 } 2588 v = EOREAD4(sc, EHCI_PORTSC(index)); 2589 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2590 2591 i = UPS_HIGH_SPEED; 2592 if (sc->sc_flags & EHCIF_ETTF) { 2593 /* 2594 * If we are doing embedded transaction translation, 2595 * then directly attached LS/FS devices are reset by 2596 * the EHCI controller itself. PSPD is encoded 2597 * the same way as in USBSTATUS. 2598 */ 2599 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2600 } 2601 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2602 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2603 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2604 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2605 if (v & EHCI_PS_PR) i |= UPS_RESET; 2606 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2607 if (sc->sc_vendor_port_status) 2608 i = sc->sc_vendor_port_status(sc, v, i); 2609 USETW(ps.wPortStatus, i); 2610 i = 0; 2611 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2612 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2613 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2614 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2615 USETW(ps.wPortChange, i); 2616 totlen = uimin(len, sizeof(ps)); 2617 memcpy(buf, &ps, totlen); 2618 break; 2619 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2620 return -1; 2621 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2622 break; 2623 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2624 if (index < 1 || index > sc->sc_noport) { 2625 return -1; 2626 } 2627 port = EHCI_PORTSC(index); 2628 v = EOREAD4(sc, port); 2629 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2630 v &= ~EHCI_PS_CLEAR; 2631 switch(value) { 2632 case UHF_PORT_ENABLE: 2633 EOWRITE4(sc, port, v | EHCI_PS_PE); 2634 break; 2635 case UHF_PORT_SUSPEND: 2636 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2637 break; 2638 case UHF_PORT_RESET: 2639 DPRINTF("reset port %jd", index, 0, 0, 0); 2640 if (EHCI_PS_IS_LOWSPEED(v) 2641 && sc->sc_ncomp > 0 2642 && !(sc->sc_flags & EHCIF_ETTF)) { 2643 /* 2644 * Low speed device on non-ETTF controller or 2645 * unaccompanied controller, give up ownership. 2646 */ 2647 ehci_disown(sc, index, 1); 2648 break; 2649 } 2650 /* Start reset sequence. */ 2651 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2652 EOWRITE4(sc, port, v | EHCI_PS_PR); 2653 /* Wait for reset to complete. */ 2654 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2655 if (sc->sc_dying) { 2656 return -1; 2657 } 2658 /* 2659 * An embedded transaction translator will automatically 2660 * terminate the reset sequence so there's no need to 2661 * it. 2662 */ 2663 v = EOREAD4(sc, port); 2664 if (v & EHCI_PS_PR) { 2665 /* Terminate reset sequence. */ 2666 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2667 /* Wait for HC to complete reset. */ 2668 usb_delay_ms(&sc->sc_bus, 2669 EHCI_PORT_RESET_COMPLETE); 2670 if (sc->sc_dying) { 2671 return -1; 2672 } 2673 } 2674 2675 v = EOREAD4(sc, port); 2676 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2677 if (v & EHCI_PS_PR) { 2678 printf("%s: port reset timeout\n", 2679 device_xname(sc->sc_dev)); 2680 return USBD_TIMEOUT; 2681 } 2682 if (!(v & EHCI_PS_PE)) { 2683 /* Not a high speed device, give up ownership.*/ 2684 ehci_disown(sc, index, 0); 2685 break; 2686 } 2687 sc->sc_isreset[index] = 1; 2688 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2689 v, 0, 0); 2690 break; 2691 case UHF_PORT_POWER: 2692 DPRINTF("set port power %jd (has PPC = %jd)", index, 2693 sc->sc_hasppc, 0, 0); 2694 if (sc->sc_hasppc) 2695 EOWRITE4(sc, port, v | EHCI_PS_PP); 2696 break; 2697 case UHF_PORT_TEST: 2698 DPRINTF("set port test %jd", index, 0, 0, 0); 2699 break; 2700 case UHF_PORT_INDICATOR: 2701 DPRINTF("set port ind %jd", index, 0, 0, 0); 2702 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2703 break; 2704 default: 2705 return -1; 2706 } 2707 break; 2708 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2709 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2710 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2711 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2712 break; 2713 default: 2714 /* default from usbroothub */ 2715 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2716 2717 return buflen; 2718 } 2719 2720 DPRINTF("returning %jd", totlen, 0, 0, 0); 2721 2722 return totlen; 2723 } 2724 2725 Static int 2726 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2727 void *buf, int buflen) 2728 { 2729 struct ehci_softc *sc = EHCI_BUS2SC(bus); 2730 int actlen; 2731 2732 mutex_enter(&sc->sc_rhlock); 2733 actlen = ehci_roothub_ctrl_locked(bus, req, buf, buflen); 2734 mutex_exit(&sc->sc_rhlock); 2735 2736 return actlen; 2737 } 2738 2739 /* 2740 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2741 * 2742 * This pile of garbage below works around the following problem without 2743 * holding boots with no hand-over devices present, while penalising 2744 * boots where the first ehci probe hands off devices with a 5 second 2745 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2746 * for RB_SINGLE, but the same basic issue exists. 2747 * 2748 * The way ehci hand-off works, the companion controller does not get the 2749 * device until after its initial bus explore, so the reference dropped 2750 * after the first explore is not enough. 5 seconds should be enough, 2751 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2752 * 2753 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2754 * if the callback is scheduled. CO_DONE is set when the callout has 2755 * called config_pending_decr(). 2756 * 2757 * There's a mutex, a cv and a callout here, and we delay detach if the 2758 * callout has been set. 2759 */ 2760 #ifndef EHCI_DISOWN_DELAY_SECONDS 2761 #define EHCI_DISOWN_DELAY_SECONDS 5 2762 #endif 2763 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2764 2765 static void 2766 ehci_disown_callback(void *arg) 2767 { 2768 ehci_softc_t *sc = arg; 2769 2770 config_pending_decr(sc->sc_dev); 2771 2772 mutex_enter(&sc->sc_complock); 2773 KASSERT(sc->sc_comp_state == CO_SCHED); 2774 sc->sc_comp_state = CO_DONE; 2775 cv_signal(&sc->sc_compcv); 2776 mutex_exit(&sc->sc_complock); 2777 } 2778 2779 static void 2780 ehci_disown_sched_callback(ehci_softc_t *sc) 2781 { 2782 extern bool root_is_mounted; 2783 2784 mutex_enter(&sc->sc_complock); 2785 2786 if (root_is_mounted || 2787 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2788 sc->sc_comp_state != CO_EARLY) { 2789 mutex_exit(&sc->sc_complock); 2790 return; 2791 } 2792 2793 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2794 ehci_disown_callback, &sc->sc_dev); 2795 sc->sc_comp_state = CO_SCHED; 2796 2797 mutex_exit(&sc->sc_complock); 2798 2799 config_pending_incr(sc->sc_dev); 2800 aprint_normal_dev(sc->sc_dev, 2801 "delaying %s by %u seconds due to USB owner change.\n", 2802 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user", 2803 ehci_disown_delay_seconds); 2804 } 2805 2806 Static void 2807 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2808 { 2809 int port; 2810 uint32_t v; 2811 2812 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2813 2814 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2815 if (sc->sc_npcomp != 0) { 2816 int i = (index-1) / sc->sc_npcomp; 2817 if (i < sc->sc_ncomp) { 2818 ehci_disown_sched_callback(sc); 2819 #ifdef DIAGNOSTIC 2820 printf("%s: handing over %s speed device on " 2821 "port %d to %s\n", 2822 device_xname(sc->sc_dev), 2823 lowspeed ? "low" : "full", 2824 index, sc->sc_comps[i] ? 2825 device_xname(sc->sc_comps[i]) : 2826 "companion controller"); 2827 } else { 2828 printf("%s: strange port\n", 2829 device_xname(sc->sc_dev)); 2830 #endif 2831 } 2832 } else { 2833 #ifdef DIAGNOSTIC 2834 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2835 #endif 2836 } 2837 port = EHCI_PORTSC(index); 2838 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2839 EOWRITE4(sc, port, v | EHCI_PS_PO); 2840 } 2841 2842 Static usbd_status 2843 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2844 { 2845 2846 /* Pipe isn't running, start first */ 2847 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2848 } 2849 2850 Static usbd_status 2851 ehci_root_intr_start(struct usbd_xfer *xfer) 2852 { 2853 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2854 2855 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2856 2857 if (sc->sc_dying) 2858 return USBD_IOERROR; 2859 2860 KASSERT(sc->sc_intrxfer == NULL); 2861 sc->sc_intrxfer = xfer; 2862 xfer->ux_status = USBD_IN_PROGRESS; 2863 2864 return USBD_IN_PROGRESS; 2865 } 2866 2867 /* Abort a root interrupt request. */ 2868 Static void 2869 ehci_root_intr_abort(struct usbd_xfer *xfer) 2870 { 2871 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2872 2873 KASSERT(mutex_owned(&sc->sc_lock)); 2874 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2875 2876 /* If xfer has already completed, nothing to do here. */ 2877 if (sc->sc_intrxfer == NULL) 2878 return; 2879 2880 /* 2881 * Otherwise, sc->sc_intrxfer had better be this transfer. 2882 * Cancel it. 2883 */ 2884 KASSERT(sc->sc_intrxfer == xfer); 2885 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2886 xfer->ux_status = USBD_CANCELLED; 2887 usb_transfer_complete(xfer); 2888 } 2889 2890 /* Close the root pipe. */ 2891 Static void 2892 ehci_root_intr_close(struct usbd_pipe *pipe) 2893 { 2894 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2895 2896 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2897 2898 KASSERT(mutex_owned(&sc->sc_lock)); 2899 2900 /* 2901 * Caller must guarantee the xfer has completed first, by 2902 * closing the pipe only after normal completion or an abort. 2903 */ 2904 KASSERT(sc->sc_intrxfer == NULL); 2905 } 2906 2907 Static void 2908 ehci_root_intr_done(struct usbd_xfer *xfer) 2909 { 2910 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2911 2912 KASSERT(mutex_owned(&sc->sc_lock)); 2913 2914 /* Claim the xfer so it doesn't get completed again. */ 2915 KASSERT(sc->sc_intrxfer == xfer); 2916 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2917 sc->sc_intrxfer = NULL; 2918 } 2919 2920 /************************/ 2921 2922 Static ehci_soft_qh_t * 2923 ehci_alloc_sqh(ehci_softc_t *sc) 2924 { 2925 ehci_soft_qh_t *sqh; 2926 2927 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2928 2929 mutex_enter(&sc->sc_lock); 2930 if (sc->sc_freeqhs == NULL) { 2931 DPRINTF("allocating chunk", 0, 0, 0, 0); 2932 mutex_exit(&sc->sc_lock); 2933 2934 /* 2935 * We can avoid USBMALLOC_COHERENT as the QHs are each on a 2936 * cacheline. 2937 */ 2938 usb_dma_t dma; 2939 int err = usb_allocmem(sc->sc_dmatag, 2940 EHCI_QH_SIZE * EHCI_QH_CHUNK, 2941 EHCI_PAGE_SIZE, 0, &dma); 2942 2943 if (err) { 2944 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2945 return NULL; 2946 } 2947 2948 ehci_soft_qh_t *sqhs = 2949 kmem_zalloc(sizeof(*sqh) * EHCI_QH_CHUNK, KM_SLEEP); 2950 2951 mutex_enter(&sc->sc_lock); 2952 for (size_t i = 0; i < EHCI_QH_CHUNK; i++) { 2953 const int offs = i * EHCI_QH_SIZE; 2954 const bus_addr_t baddr = DMAADDR(&dma, offs); 2955 2956 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2957 2958 sqh = &sqhs[i]; 2959 sqh->qh = KERNADDR(&dma, offs); 2960 sqh->physaddr = BUS_ADDR_LO32(baddr); 2961 sqh->dma = dma; 2962 sqh->offs = offs; 2963 2964 sqh->next = sc->sc_freeqhs; 2965 sc->sc_freeqhs = sqh; 2966 } 2967 } 2968 sqh = sc->sc_freeqhs; 2969 sc->sc_freeqhs = sqh->next; 2970 mutex_exit(&sc->sc_lock); 2971 2972 memset(sqh->qh, 0, sizeof(*sqh->qh)); 2973 sqh->next = NULL; 2974 2975 return sqh; 2976 } 2977 2978 Static void 2979 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2980 { 2981 KASSERT(mutex_owned(&sc->sc_lock)); 2982 2983 sqh->next = sc->sc_freeqhs; 2984 sc->sc_freeqhs = sqh; 2985 } 2986 2987 Static ehci_soft_qtd_t * 2988 ehci_alloc_sqtd(ehci_softc_t *sc) 2989 { 2990 ehci_soft_qtd_t *sqtd = NULL; 2991 2992 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2993 2994 mutex_enter(&sc->sc_lock); 2995 if (sc->sc_freeqtds == NULL) { 2996 DPRINTF("allocating chunk", 0, 0, 0, 0); 2997 mutex_exit(&sc->sc_lock); 2998 2999 usb_dma_t dma; 3000 /* 3001 * We can avoid USBMALLOC_COHERENT as the QTDs are each on a 3002 * cacheline. 3003 */ 3004 int err = usb_allocmem(sc->sc_dmatag, 3005 EHCI_QTD_SIZE * EHCI_QTD_CHUNK, 3006 EHCI_PAGE_SIZE, 0, &dma); 3007 3008 if (err) { 3009 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3010 return NULL; 3011 } 3012 3013 ehci_soft_qtd_t *sqtds = 3014 kmem_zalloc(sizeof(*sqtd) * EHCI_QTD_CHUNK, KM_SLEEP); 3015 3016 mutex_enter(&sc->sc_lock); 3017 for (size_t i = 0; i < EHCI_QTD_CHUNK; i++) { 3018 const int offs = i * EHCI_QTD_SIZE; 3019 const bus_addr_t baddr = DMAADDR(&dma, offs); 3020 3021 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3022 3023 sqtd = &sqtds[i]; 3024 sqtd->qtd = KERNADDR(&dma, offs); 3025 sqtd->physaddr = BUS_ADDR_LO32(baddr); 3026 sqtd->dma = dma; 3027 sqtd->offs = offs; 3028 3029 sqtd->nextqtd = sc->sc_freeqtds; 3030 sc->sc_freeqtds = sqtd; 3031 } 3032 } 3033 3034 sqtd = sc->sc_freeqtds; 3035 sc->sc_freeqtds = sqtd->nextqtd; 3036 mutex_exit(&sc->sc_lock); 3037 3038 memset(sqtd->qtd, 0, sizeof(*sqtd->qtd)); 3039 sqtd->nextqtd = NULL; 3040 sqtd->xfer = NULL; 3041 3042 return sqtd; 3043 } 3044 3045 Static void 3046 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 3047 { 3048 3049 mutex_enter(&sc->sc_lock); 3050 sqtd->nextqtd = sc->sc_freeqtds; 3051 sc->sc_freeqtds = sqtd; 3052 mutex_exit(&sc->sc_lock); 3053 } 3054 3055 Static int 3056 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3057 int alen, int rd, ehci_soft_qtd_t **sp) 3058 { 3059 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3060 uint16_t flags = xfer->ux_flags; 3061 3062 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3063 3064 ASSERT_SLEEPABLE(); 3065 KASSERT(sp); 3066 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 3067 3068 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 3069 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 3070 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 3071 KM_SLEEP); 3072 exfer->ex_nsqtd = nsqtd; 3073 3074 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 3075 alen, nsqtd, flags); 3076 3077 for (size_t j = 0; j < exfer->ex_nsqtd;) { 3078 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 3079 if (cur == NULL) 3080 goto nomem; 3081 exfer->ex_sqtds[j++] = cur; 3082 3083 cur->xfer = xfer; 3084 cur->len = 0; 3085 3086 } 3087 3088 *sp = exfer->ex_sqtds[0]; 3089 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 3090 3091 return 0; 3092 3093 nomem: 3094 ehci_free_sqtds(sc, exfer); 3095 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 3096 DPRINTF("no memory", 0, 0, 0, 0); 3097 return ENOMEM; 3098 } 3099 3100 Static void 3101 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 3102 { 3103 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3104 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 3105 3106 mutex_enter(&sc->sc_lock); 3107 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 3108 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 3109 3110 if (sqtd == NULL) 3111 break; 3112 3113 sqtd->nextqtd = sc->sc_freeqtds; 3114 sc->sc_freeqtds = sqtd; 3115 } 3116 mutex_exit(&sc->sc_lock); 3117 } 3118 3119 Static void 3120 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 3121 { 3122 if (prev) { 3123 prev->nextqtd = sqtd; 3124 prev->qtd->qtd_next = htole32(sqtd->physaddr); 3125 prev->qtd->qtd_altnext = prev->qtd->qtd_next; 3126 usb_syncmem(&prev->dma, prev->offs, sizeof(*prev->qtd), 3127 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3128 } 3129 } 3130 3131 Static void 3132 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3133 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3134 { 3135 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3136 usb_dma_t *dma = &xfer->ux_dmabuf; 3137 uint16_t flags = xfer->ux_flags; 3138 ehci_soft_qtd_t *sqtd, *prev; 3139 int tog = *toggle; 3140 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3141 int len = length; 3142 3143 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3144 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 3145 len, isread, tog); 3146 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 3147 0, 0, 0); 3148 3149 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 3150 3151 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3152 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3153 EHCI_QTD_SET_CERR(3) 3154 ; 3155 3156 sqtd = prev = NULL; 3157 size_t curoffs = 0; 3158 size_t j = 0; 3159 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3160 sqtd = exfer->ex_sqtds[j++]; 3161 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3162 (uintptr_t)prev, 0); 3163 3164 /* 3165 * The EHCI hardware can handle at most 5 pages and they do 3166 * not have to be contiguous 3167 */ 3168 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3169 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3170 size_t curlen = len; 3171 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3172 /* must use multiple TDs, fill as much as possible. */ 3173 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3174 3175 /* the length must be a multiple of the max size */ 3176 curlen -= curlen % mps; 3177 } 3178 KASSERT(curlen != 0); 3179 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3180 curoffs, 0); 3181 3182 /* Fill the qTD */ 3183 sqtd->qtd->qtd_next = sqtd->qtd->qtd_altnext = EHCI_NULL; 3184 sqtd->qtd->qtd_status = htole32( 3185 qtdstatus | 3186 EHCI_QTD_SET_BYTES(curlen) | 3187 EHCI_QTD_SET_TOGGLE(tog)); 3188 3189 /* Find number of pages we'll be using, insert dma addresses */ 3190 size_t pages = EHCI_NPAGES(curlen); 3191 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3192 size_t pageoffs = EHCI_PAGE(curoffs); 3193 for (size_t i = 0; i < pages; i++) { 3194 paddr_t a = EHCI_PAGE(DMAADDR(dma, 3195 pageoffs + i * EHCI_PAGE_SIZE)); 3196 sqtd->qtd->qtd_buffer[i] = htole32(BUS_ADDR_LO32(a)); 3197 sqtd->qtd->qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a)); 3198 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3199 i, pages, 3200 le32toh(sqtd->qtd->qtd_buffer_hi[i]), 3201 le32toh(sqtd->qtd->qtd_buffer[i])); 3202 } 3203 /* First buffer pointer requires a page offset to start at */ 3204 sqtd->qtd->qtd_buffer[0] |= htole32(va_offs); 3205 3206 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 3207 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3208 3209 sqtd->len = curlen; 3210 3211 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3212 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3213 3214 ehci_append_sqtd(sqtd, prev); 3215 3216 if (howmany(curlen, mps) & 1) { 3217 tog ^= 1; 3218 } 3219 3220 curoffs += curlen; 3221 len -= curlen; 3222 } 3223 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3224 xfer, length, len, mps, exfer->ex_nsqtd, j); 3225 3226 if (!isread && 3227 (flags & USBD_FORCE_SHORT_XFER) && 3228 length % mps == 0) { 3229 /* Force a 0 length transfer at the end. */ 3230 3231 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3232 exfer->ex_nsqtd); 3233 prev = sqtd; 3234 sqtd = exfer->ex_sqtds[j++]; 3235 memset(sqtd->qtd, 0, sizeof(*sqtd->qtd)); 3236 sqtd->qtd->qtd_next = sqtd->qtd->qtd_altnext = EHCI_NULL; 3237 sqtd->qtd->qtd_status = htole32( 3238 qtdstatus | 3239 EHCI_QTD_SET_BYTES(0) | 3240 EHCI_QTD_SET_TOGGLE(tog)); 3241 3242 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 3243 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3244 3245 ehci_append_sqtd(sqtd, prev); 3246 tog ^= 1; 3247 } 3248 3249 *lsqtd = sqtd; 3250 *toggle = tog; 3251 } 3252 3253 Static ehci_soft_itd_t * 3254 ehci_alloc_itd(ehci_softc_t *sc) 3255 { 3256 struct ehci_soft_itd *itd, *freeitd; 3257 3258 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3259 3260 mutex_enter(&sc->sc_lock); 3261 3262 freeitd = LIST_FIRST(&sc->sc_freeitds); 3263 if (freeitd == NULL) { 3264 DPRINTF("allocating chunk", 0, 0, 0, 0); 3265 mutex_exit(&sc->sc_lock); 3266 3267 usb_dma_t dma; 3268 /* 3269 * We can avoid USBMALLOC_COHERENT as the ITDs are each on a 3270 * cacheline. 3271 */ 3272 int err = usb_allocmem(sc->sc_dmatag, 3273 EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3274 EHCI_PAGE_SIZE, 0, &dma); 3275 3276 if (err) { 3277 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3278 return NULL; 3279 } 3280 3281 struct ehci_soft_itd *itds = 3282 kmem_alloc(sizeof(*itd) * EHCI_ITD_CHUNK, KM_SLEEP); 3283 3284 mutex_enter(&sc->sc_lock); 3285 for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) { 3286 const int offs = i * EHCI_ITD_SIZE; 3287 const bus_addr_t baddr = DMAADDR(&dma, offs); 3288 3289 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3290 3291 itd = &itds[i]; 3292 itd->itd = KERNADDR(&dma, offs); 3293 itd->physaddr = BUS_ADDR_LO32(baddr); 3294 itd->dma = dma; 3295 itd->offs = offs; 3296 3297 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3298 } 3299 freeitd = LIST_FIRST(&sc->sc_freeitds); 3300 } 3301 3302 itd = freeitd; 3303 LIST_REMOVE(itd, free_list); 3304 mutex_exit(&sc->sc_lock); 3305 3306 memset(itd->itd, 0, sizeof(*itd->itd)); 3307 itd->frame_list.next = NULL; 3308 itd->frame_list.prev = NULL; 3309 itd->xfer_next = NULL; 3310 itd->slot = 0; 3311 3312 return itd; 3313 } 3314 3315 Static ehci_soft_sitd_t * 3316 ehci_alloc_sitd(ehci_softc_t *sc) 3317 { 3318 struct ehci_soft_sitd *sitd, *freesitd; 3319 3320 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3321 3322 mutex_enter(&sc->sc_lock); 3323 freesitd = LIST_FIRST(&sc->sc_freesitds); 3324 if (freesitd == NULL) { 3325 DPRINTF("allocating chunk", 0, 0, 0, 0); 3326 mutex_exit(&sc->sc_lock); 3327 3328 usb_dma_t dma; 3329 3330 /* 3331 * We can avoid USBMALLOC_COHERENT as the SITDs are each on a 3332 * cacheline. 3333 */ 3334 int err = usb_allocmem(sc->sc_dmatag, 3335 EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3336 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3337 3338 if (err) { 3339 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3340 return NULL; 3341 } 3342 struct ehci_soft_sitd *sitds = 3343 kmem_alloc(sizeof(*sitd) * EHCI_SITD_CHUNK, KM_SLEEP); 3344 3345 mutex_enter(&sc->sc_lock); 3346 for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) { 3347 const int offs = i * EHCI_SITD_SIZE; 3348 const bus_addr_t baddr = DMAADDR(&dma, offs); 3349 3350 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3351 3352 sitd = &sitds[i]; 3353 sitd->itd = KERNADDR(&dma, offs); 3354 sitd->physaddr = BUS_ADDR_LO32(baddr); 3355 sitd->dma = dma; 3356 sitd->offs = offs; 3357 3358 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3359 } 3360 freesitd = LIST_FIRST(&sc->sc_freesitds); 3361 } 3362 3363 sitd = freesitd; 3364 LIST_REMOVE(sitd, free_list); 3365 mutex_exit(&sc->sc_lock); 3366 3367 memset(sitd->sitd, 0, sizeof(*sitd->sitd)); 3368 sitd->frame_list.next = NULL; 3369 sitd->frame_list.prev = NULL; 3370 sitd->xfer_next = NULL; 3371 sitd->slot = 0; 3372 3373 return sitd; 3374 } 3375 3376 /****************/ 3377 3378 /* 3379 * Close a regular pipe. 3380 * Assumes that there are no pending transactions. 3381 */ 3382 Static void 3383 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3384 { 3385 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3386 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3387 ehci_soft_qh_t *sqh = epipe->sqh; 3388 3389 KASSERT(mutex_owned(&sc->sc_lock)); 3390 3391 ehci_rem_qh(sc, sqh, head); 3392 ehci_free_sqh(sc, epipe->sqh); 3393 } 3394 3395 /* 3396 * Arrange for the hardware to tells us that it is not still 3397 * processing the TDs by setting the QH halted bit and wait for the ehci 3398 * door bell 3399 */ 3400 Static void 3401 ehci_abortx(struct usbd_xfer *xfer) 3402 { 3403 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3404 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3405 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3406 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3407 ehci_soft_qh_t *sqh = epipe->sqh; 3408 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3409 ehci_physaddr_t cur; 3410 uint32_t qhstatus; 3411 int hit; 3412 3413 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3414 3415 KASSERT(mutex_owned(&sc->sc_lock)); 3416 ASSERT_SLEEPABLE(); 3417 3418 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3419 xfer->ux_status == USBD_TIMEOUT), 3420 "bad abort status: %d", xfer->ux_status); 3421 3422 /* 3423 * If we're dying, skip the hardware action and just notify the 3424 * software that we're done. 3425 */ 3426 if (sc->sc_dying) { 3427 goto dying; 3428 } 3429 3430 /* 3431 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3432 */ 3433 ehci_del_intr_list(sc, exfer); 3434 3435 usb_syncmem(&sqh->dma, 3436 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3437 sizeof(sqh->qh->qh_qtd.qtd_status), 3438 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3439 qhstatus = sqh->qh->qh_qtd.qtd_status; 3440 sqh->qh->qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3441 usb_syncmem(&sqh->dma, 3442 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3443 sizeof(sqh->qh->qh_qtd.qtd_status), 3444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3445 3446 if (exfer->ex_type == EX_CTRL) { 3447 fsqtd = exfer->ex_setup; 3448 lsqtd = exfer->ex_status; 3449 } else { 3450 fsqtd = exfer->ex_sqtdstart; 3451 lsqtd = exfer->ex_sqtdend; 3452 } 3453 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3454 usb_syncmem(&sqtd->dma, 3455 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3456 sizeof(sqtd->qtd->qtd_status), 3457 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3458 sqtd->qtd->qtd_status |= htole32(EHCI_QTD_HALTED); 3459 usb_syncmem(&sqtd->dma, 3460 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3461 sizeof(sqtd->qtd->qtd_status), 3462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3463 if (sqtd == lsqtd) 3464 break; 3465 } 3466 3467 /* 3468 * HC Step 2: Wait until we know hardware has finished any possible 3469 * use of the xfer. 3470 */ 3471 ehci_sync_hc(sc); 3472 3473 /* 3474 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3475 * The complication here is that the hardware may have executed 3476 * beyond the xfer we're trying to abort. So as we're scanning 3477 * the TDs of this xfer we check if the hardware points to 3478 * any of them. 3479 */ 3480 3481 usb_syncmem(&sqh->dma, 3482 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3483 sizeof(sqh->qh->qh_curqtd), 3484 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3485 cur = EHCI_LINK_ADDR(le32toh(sqh->qh->qh_curqtd)); 3486 hit = 0; 3487 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3488 hit |= cur == sqtd->physaddr; 3489 if (sqtd == lsqtd) 3490 break; 3491 } 3492 sqtd = sqtd->nextqtd; 3493 /* Zap curqtd register if hardware pointed inside the xfer. */ 3494 if (hit && sqtd != NULL) { 3495 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3496 sqh->qh->qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3497 usb_syncmem(&sqh->dma, 3498 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3499 sizeof(sqh->qh->qh_curqtd), 3500 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3501 sqh->qh->qh_qtd.qtd_status = qhstatus; 3502 usb_syncmem(&sqh->dma, 3503 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3504 sizeof(sqh->qh->qh_qtd.qtd_status), 3505 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3506 } else { 3507 DPRINTF("no hit", 0, 0, 0, 0); 3508 usb_syncmem(&sqh->dma, 3509 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3510 sizeof(sqh->qh->qh_curqtd), 3511 BUS_DMASYNC_PREREAD); 3512 } 3513 3514 dying: 3515 #ifdef DIAGNOSTIC 3516 exfer->ex_isdone = true; 3517 #endif 3518 DPRINTFN(14, "end", 0, 0, 0, 0); 3519 3520 KASSERT(mutex_owned(&sc->sc_lock)); 3521 } 3522 3523 Static void 3524 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3525 { 3526 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3527 ehci_isoc_trans_t trans_status; 3528 struct ehci_xfer *exfer; 3529 ehci_softc_t *sc; 3530 struct ehci_soft_itd *itd; 3531 struct ehci_soft_sitd *sitd; 3532 int i; 3533 3534 KASSERTMSG(status == USBD_CANCELLED, 3535 "invalid status for abort: %d", (int)status); 3536 3537 exfer = EHCI_XFER2EXFER(xfer); 3538 sc = EHCI_XFER2SC(xfer); 3539 3540 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3541 (uintptr_t)xfer->ux_pipe, 0, 0); 3542 3543 KASSERT(mutex_owned(&sc->sc_lock)); 3544 ASSERT_SLEEPABLE(); 3545 3546 /* No timeout or task here. */ 3547 3548 /* 3549 * The xfer cannot have been cancelled already. It is the 3550 * responsibility of the caller of usbd_abort_pipe not to try 3551 * to abort a pipe multiple times, whether concurrently or 3552 * sequentially. 3553 */ 3554 KASSERT(xfer->ux_status != USBD_CANCELLED); 3555 3556 /* If anyone else beat us, we're done. */ 3557 if (xfer->ux_status != USBD_IN_PROGRESS) 3558 return; 3559 3560 /* We beat everyone else. Claim the status. */ 3561 xfer->ux_status = status; 3562 3563 /* 3564 * If we're dying, skip the hardware action and just notify the 3565 * software that we're done. 3566 */ 3567 if (sc->sc_dying) { 3568 goto dying; 3569 } 3570 3571 /* 3572 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3573 */ 3574 ehci_del_intr_list(sc, exfer); 3575 3576 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3577 for (itd = exfer->ex_itdstart; itd != NULL; 3578 itd = itd->xfer_next) { 3579 usb_syncmem(&itd->dma, 3580 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3581 sizeof(itd->itd->itd_ctl), 3582 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3583 3584 for (i = 0; i < 8; i++) { 3585 trans_status = le32toh(itd->itd->itd_ctl[i]); 3586 trans_status &= ~EHCI_ITD_ACTIVE; 3587 itd->itd->itd_ctl[i] = htole32(trans_status); 3588 } 3589 3590 usb_syncmem(&itd->dma, 3591 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3592 sizeof(itd->itd->itd_ctl), 3593 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3594 } 3595 } else { 3596 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3597 sitd = sitd->xfer_next) { 3598 usb_syncmem(&sitd->dma, 3599 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3600 sizeof(sitd->sitd->sitd_buffer), 3601 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3602 3603 trans_status = le32toh(sitd->sitd->sitd_trans); 3604 trans_status &= ~EHCI_SITD_ACTIVE; 3605 sitd->sitd->sitd_trans = htole32(trans_status); 3606 3607 usb_syncmem(&sitd->dma, 3608 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3609 sizeof(sitd->sitd->sitd_buffer), 3610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3611 } 3612 } 3613 3614 dying: 3615 #ifdef DIAGNOSTIC 3616 exfer->ex_isdone = true; 3617 #endif 3618 usb_transfer_complete(xfer); 3619 DPRINTFN(14, "end", 0, 0, 0, 0); 3620 3621 KASSERT(mutex_owned(&sc->sc_lock)); 3622 } 3623 3624 /************************/ 3625 3626 Static int 3627 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3628 { 3629 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3630 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3631 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3632 usb_device_request_t *req = &xfer->ux_request; 3633 ehci_soft_qtd_t *setup, *status, *next; 3634 int isread = req->bmRequestType & UT_READ; 3635 int len = xfer->ux_bufsize; 3636 int err; 3637 3638 exfer->ex_type = EX_CTRL; 3639 exfer->ex_status = NULL; 3640 exfer->ex_data = NULL; 3641 exfer->ex_setup = ehci_alloc_sqtd(sc); 3642 if (exfer->ex_setup == NULL) { 3643 err = ENOMEM; 3644 goto bad1; 3645 } 3646 exfer->ex_status = ehci_alloc_sqtd(sc); 3647 if (exfer->ex_status == NULL) { 3648 err = ENOMEM; 3649 goto bad2; 3650 } 3651 setup = exfer->ex_setup; 3652 status = exfer->ex_status; 3653 exfer->ex_nsqtd = 0; 3654 next = status; 3655 /* Set up data transaction */ 3656 if (len != 0) { 3657 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3658 &exfer->ex_data); 3659 if (err) 3660 goto bad3; 3661 next = exfer->ex_data; 3662 } 3663 3664 /* Clear toggle */ 3665 setup->qtd->qtd_status = htole32( 3666 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3667 EHCI_QTD_SET_TOGGLE(0) | 3668 EHCI_QTD_SET_BYTES(sizeof(*req)) 3669 ); 3670 3671 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3672 setup->qtd->qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3673 setup->qtd->qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3674 setup->qtd->qtd_next = setup->qtd->qtd_altnext = htole32(next->physaddr); 3675 setup->nextqtd = next; 3676 setup->xfer = xfer; 3677 setup->len = sizeof(*req); 3678 3679 status->qtd->qtd_status = htole32( 3680 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3681 EHCI_QTD_SET_TOGGLE(1) | 3682 EHCI_QTD_IOC 3683 ); 3684 status->qtd->qtd_buffer[0] = 0; 3685 status->qtd->qtd_buffer_hi[0] = 0; 3686 status->qtd->qtd_next = status->qtd->qtd_altnext = EHCI_NULL; 3687 status->nextqtd = NULL; 3688 status->xfer = xfer; 3689 status->len = 0; 3690 3691 return 0; 3692 bad3: 3693 ehci_free_sqtd(sc, exfer->ex_status); 3694 bad2: 3695 ehci_free_sqtd(sc, exfer->ex_setup); 3696 bad1: 3697 return err; 3698 } 3699 3700 Static void 3701 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3702 { 3703 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3704 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3705 3706 KASSERT(ex->ex_type == EX_CTRL); 3707 3708 ehci_free_sqtd(sc, ex->ex_setup); 3709 ehci_free_sqtd(sc, ex->ex_status); 3710 ehci_free_sqtds(sc, ex); 3711 if (ex->ex_nsqtd) 3712 kmem_free(ex->ex_sqtds, 3713 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3714 } 3715 3716 Static usbd_status 3717 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3718 { 3719 3720 /* Pipe isn't running, start first */ 3721 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3722 } 3723 3724 Static usbd_status 3725 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3726 { 3727 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3728 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3729 usb_device_request_t *req = &xfer->ux_request; 3730 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3731 ehci_soft_qtd_t *setup, *status, *next; 3732 ehci_soft_qh_t *sqh; 3733 3734 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3735 3736 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3737 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3738 3739 if (sc->sc_dying) 3740 return USBD_IOERROR; 3741 3742 const int isread = req->bmRequestType & UT_READ; 3743 const int len = UGETW(req->wLength); 3744 3745 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3746 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3747 UGETW(req->wIndex)); 3748 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3749 len, epipe->pipe.up_dev->ud_addr, 3750 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3751 3752 sqh = epipe->sqh; 3753 3754 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh->qh_endp)) == epipe->pipe.up_dev->ud_addr, 3755 "address QH %" __PRIuBIT " pipe %d\n", 3756 EHCI_QH_GET_ADDR(le32toh(sqh->qh->qh_endp)), 3757 epipe->pipe.up_dev->ud_addr); 3758 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh->qh_endp)) == 3759 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3760 "MPS QH %" __PRIuBIT " pipe %d\n", 3761 EHCI_QH_GET_MPL(le32toh(sqh->qh->qh_endp)), 3762 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3763 3764 setup = exfer->ex_setup; 3765 status = exfer->ex_status; 3766 3767 DPRINTF("setup %#jx status %#jx data %#jx", 3768 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3769 KASSERTMSG(setup != NULL && status != NULL, 3770 "Failed memory allocation, setup %p status %p", 3771 setup, status); 3772 3773 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3774 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3775 3776 /* Clear toggle */ 3777 setup->qtd->qtd_status &= ~htole32( 3778 EHCI_QTD_STATUS_MASK | 3779 EHCI_QTD_BYTES_MASK | 3780 EHCI_QTD_TOGGLE_MASK | 3781 EHCI_QTD_CERR_MASK 3782 ); 3783 setup->qtd->qtd_status |= htole32( 3784 EHCI_QTD_ACTIVE | 3785 EHCI_QTD_SET_CERR(3) | 3786 EHCI_QTD_SET_TOGGLE(0) | 3787 EHCI_QTD_SET_BYTES(sizeof(*req)) 3788 ); 3789 3790 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3791 setup->qtd->qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3792 setup->qtd->qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3793 3794 next = status; 3795 status->qtd->qtd_status &= ~htole32( 3796 EHCI_QTD_STATUS_MASK | 3797 EHCI_QTD_PID_MASK | 3798 EHCI_QTD_BYTES_MASK | 3799 EHCI_QTD_TOGGLE_MASK | 3800 EHCI_QTD_CERR_MASK 3801 ); 3802 status->qtd->qtd_status |= htole32( 3803 EHCI_QTD_ACTIVE | 3804 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3805 EHCI_QTD_SET_CERR(3) | 3806 EHCI_QTD_SET_TOGGLE(1) | 3807 EHCI_QTD_SET_BYTES(0) | 3808 EHCI_QTD_IOC 3809 ); 3810 KASSERT(status->qtd->qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3811 3812 KASSERT(exfer->ex_isdone); 3813 #ifdef DIAGNOSTIC 3814 exfer->ex_isdone = false; 3815 #endif 3816 3817 /* Set up data transaction */ 3818 if (len != 0) { 3819 ehci_soft_qtd_t *end; 3820 3821 /* Start toggle at 1. */ 3822 int toggle = 1; 3823 next = exfer->ex_data; 3824 KASSERTMSG(next != NULL, "Failed memory allocation"); 3825 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3826 end->nextqtd = status; 3827 end->qtd->qtd_next = end->qtd->qtd_altnext = 3828 htole32(status->physaddr); 3829 3830 usb_syncmem(&end->dma, end->offs, sizeof(*end->qtd), 3831 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3832 3833 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3834 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3835 } 3836 3837 setup->nextqtd = next; 3838 setup->qtd->qtd_next = setup->qtd->qtd_altnext = htole32(next->physaddr); 3839 3840 usb_syncmem(&setup->dma, setup->offs, sizeof(*setup->qtd), 3841 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3842 3843 usb_syncmem(&status->dma, status->offs, sizeof(*status->qtd), 3844 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3845 3846 KASSERT(status->qtd->qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3847 3848 #ifdef EHCI_DEBUG 3849 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3850 ehci_dump_sqh(sqh); 3851 ehci_dump_sqtds(setup); 3852 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3853 #endif 3854 3855 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3856 ehci_set_qh_qtd(sqh, setup); 3857 ehci_add_intr_list(sc, exfer); 3858 xfer->ux_status = USBD_IN_PROGRESS; 3859 usbd_xfer_schedule_timeout(xfer); 3860 3861 #if 0 3862 #ifdef EHCI_DEBUG 3863 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3864 // delay(10000); 3865 ehci_dump_regs(sc); 3866 ehci_dump_sqh(sc->sc_async_head); 3867 ehci_dump_sqh(sqh); 3868 ehci_dump_sqtds(setup); 3869 #endif 3870 #endif 3871 3872 return USBD_IN_PROGRESS; 3873 } 3874 3875 Static void 3876 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3877 { 3878 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3879 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3880 usb_device_request_t *req = &xfer->ux_request; 3881 int len = UGETW(req->wLength); 3882 int rd = req->bmRequestType & UT_READ; 3883 3884 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3885 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3886 3887 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3888 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3889 3890 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3891 BUS_DMASYNC_POSTWRITE); 3892 if (len) 3893 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3894 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3895 3896 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3897 } 3898 3899 /* Abort a device control request. */ 3900 Static void 3901 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3902 { 3903 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3904 3905 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3906 usbd_xfer_abort(xfer); 3907 } 3908 3909 /* Close a device control pipe. */ 3910 Static void 3911 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3912 { 3913 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3914 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3915 3916 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3917 3918 KASSERT(mutex_owned(&sc->sc_lock)); 3919 3920 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3921 3922 ehci_close_pipe(pipe, sc->sc_async_head); 3923 3924 usb_freemem(&epipe->ctrl.reqdma); 3925 } 3926 3927 /* 3928 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3929 * qTD status, or miss signalling occasionally under heavy load. If the host 3930 * machine is too fast, we can miss transaction completion - when we scan 3931 * the active list the transaction still seems to be active. This generally 3932 * exhibits itself as a umass stall that never recovers. 3933 * 3934 * We work around this behaviour by setting up this callback after any softintr 3935 * that completes with transactions still pending, giving us another chance to 3936 * check for completion after the writeback has taken place. 3937 */ 3938 Static void 3939 ehci_intrlist_timeout(void *arg) 3940 { 3941 ehci_softc_t *sc = arg; 3942 3943 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3944 3945 usb_schedsoftintr(&sc->sc_bus); 3946 } 3947 3948 /************************/ 3949 3950 Static int 3951 ehci_device_bulk_init(struct usbd_xfer *xfer) 3952 { 3953 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3954 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3955 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3956 int endpt = ed->bEndpointAddress; 3957 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3958 int len = xfer->ux_bufsize; 3959 int err = 0; 3960 3961 exfer->ex_type = EX_BULK; 3962 exfer->ex_nsqtd = 0; 3963 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3964 &exfer->ex_sqtdstart); 3965 3966 return err; 3967 } 3968 3969 Static void 3970 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3971 { 3972 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3973 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3974 3975 KASSERT(ex->ex_type == EX_BULK); 3976 3977 ehci_free_sqtds(sc, ex); 3978 if (ex->ex_nsqtd) 3979 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3980 } 3981 3982 Static usbd_status 3983 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3984 { 3985 3986 /* Pipe isn't running, start first */ 3987 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3988 } 3989 3990 Static usbd_status 3991 ehci_device_bulk_start(struct usbd_xfer *xfer) 3992 { 3993 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3994 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3995 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3996 ehci_soft_qh_t *sqh; 3997 ehci_soft_qtd_t *end; 3998 int len, isread, endpt; 3999 4000 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4001 4002 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4003 xfer->ux_flags, 0); 4004 4005 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4006 4007 if (sc->sc_dying) 4008 return USBD_IOERROR; 4009 4010 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4011 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4012 4013 len = xfer->ux_length; 4014 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4015 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4016 sqh = epipe->sqh; 4017 4018 KASSERT(exfer->ex_isdone); 4019 #ifdef DIAGNOSTIC 4020 exfer->ex_isdone = false; 4021 #endif 4022 4023 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4024 4025 exfer->ex_sqtdend = end; 4026 end->qtd->qtd_status |= htole32(EHCI_QTD_IOC); 4027 usb_syncmem(&end->dma, end->offs, sizeof(*end->qtd), 4028 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4029 4030 #ifdef EHCI_DEBUG 4031 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4032 ehci_dump_sqh(sqh); 4033 ehci_dump_sqtds(exfer->ex_sqtdstart); 4034 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4035 #endif 4036 4037 if (xfer->ux_length) 4038 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4039 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4040 4041 /* also does usb_syncmem(sqh) */ 4042 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4043 ehci_add_intr_list(sc, exfer); 4044 xfer->ux_status = USBD_IN_PROGRESS; 4045 usbd_xfer_schedule_timeout(xfer); 4046 4047 #if 0 4048 #ifdef EHCI_DEBUG 4049 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4050 // delay(10000); 4051 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4052 ehci_dump_regs(sc); 4053 #if 0 4054 printf("async_head:\n"); 4055 ehci_dump_sqh(sc->sc_async_head); 4056 #endif 4057 DPRINTF("sqh:", 0, 0, 0, 0); 4058 ehci_dump_sqh(sqh); 4059 ehci_dump_sqtds(exfer->ex_sqtdstart); 4060 #endif 4061 #endif 4062 4063 return USBD_IN_PROGRESS; 4064 } 4065 4066 Static void 4067 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4068 { 4069 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4070 4071 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 4072 usbd_xfer_abort(xfer); 4073 } 4074 4075 /* 4076 * Close a device bulk pipe. 4077 */ 4078 Static void 4079 ehci_device_bulk_close(struct usbd_pipe *pipe) 4080 { 4081 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4082 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4083 4084 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4085 4086 KASSERT(mutex_owned(&sc->sc_lock)); 4087 4088 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4089 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4090 ehci_close_pipe(pipe, sc->sc_async_head); 4091 } 4092 4093 Static void 4094 ehci_device_bulk_done(struct usbd_xfer *xfer) 4095 { 4096 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4097 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4098 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4099 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4100 4101 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4102 4103 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4104 4105 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4106 4107 if (xfer->ux_length) 4108 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4109 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4110 4111 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4112 } 4113 4114 /************************/ 4115 4116 Static usbd_status 4117 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4118 { 4119 struct ehci_soft_islot *isp; 4120 int islot, lev; 4121 4122 /* Find a poll rate that is large enough. */ 4123 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4124 if (EHCI_ILEV_IVAL(lev) <= ival) 4125 break; 4126 4127 /* Pick an interrupt slot at the right level. */ 4128 /* XXX could do better than picking at random */ 4129 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4130 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4131 4132 sqh->islot = islot; 4133 isp = &sc->sc_islots[islot]; 4134 mutex_enter(&sc->sc_lock); 4135 ehci_add_qh(sc, sqh, isp->sqh); 4136 mutex_exit(&sc->sc_lock); 4137 4138 return USBD_NORMAL_COMPLETION; 4139 } 4140 4141 Static int 4142 ehci_device_intr_init(struct usbd_xfer *xfer) 4143 { 4144 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4145 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4146 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4147 int endpt = ed->bEndpointAddress; 4148 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4149 int len = xfer->ux_bufsize; 4150 int err; 4151 4152 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4153 4154 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4155 xfer->ux_flags, 0); 4156 4157 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4158 KASSERT(len != 0); 4159 4160 exfer->ex_type = EX_INTR; 4161 exfer->ex_nsqtd = 0; 4162 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4163 &exfer->ex_sqtdstart); 4164 4165 return err; 4166 } 4167 4168 Static void 4169 ehci_device_intr_fini(struct usbd_xfer *xfer) 4170 { 4171 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4172 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4173 4174 KASSERT(ex->ex_type == EX_INTR); 4175 4176 ehci_free_sqtds(sc, ex); 4177 if (ex->ex_nsqtd) 4178 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4179 } 4180 4181 Static usbd_status 4182 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4183 { 4184 4185 /* Pipe isn't running, so start it first. */ 4186 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4187 } 4188 4189 Static usbd_status 4190 ehci_device_intr_start(struct usbd_xfer *xfer) 4191 { 4192 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4193 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4194 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4195 ehci_soft_qtd_t *end; 4196 ehci_soft_qh_t *sqh; 4197 int len, isread, endpt; 4198 4199 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4200 4201 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4202 xfer->ux_flags, 0); 4203 4204 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4205 4206 if (sc->sc_dying) 4207 return USBD_IOERROR; 4208 4209 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4210 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4211 4212 len = xfer->ux_length; 4213 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4214 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4215 sqh = epipe->sqh; 4216 4217 KASSERT(exfer->ex_isdone); 4218 #ifdef DIAGNOSTIC 4219 exfer->ex_isdone = false; 4220 #endif 4221 4222 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4223 4224 end->qtd->qtd_status |= htole32(EHCI_QTD_IOC); 4225 usb_syncmem(&end->dma, end->offs, sizeof(*end->qtd), 4226 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4227 exfer->ex_sqtdend = end; 4228 4229 #ifdef EHCI_DEBUG 4230 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4231 ehci_dump_sqh(sqh); 4232 ehci_dump_sqtds(exfer->ex_sqtdstart); 4233 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4234 #endif 4235 4236 if (xfer->ux_length) 4237 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4238 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4239 4240 /* also does usb_syncmem(sqh) */ 4241 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4242 ehci_add_intr_list(sc, exfer); 4243 xfer->ux_status = USBD_IN_PROGRESS; 4244 usbd_xfer_schedule_timeout(xfer); 4245 4246 #if 0 4247 #ifdef EHCI_DEBUG 4248 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4249 // delay(10000); 4250 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4251 ehci_dump_regs(sc); 4252 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4253 ehci_dump_sqh(sqh); 4254 ehci_dump_sqtds(exfer->ex_sqtdstart); 4255 #endif 4256 #endif 4257 4258 return USBD_IN_PROGRESS; 4259 } 4260 4261 Static void 4262 ehci_device_intr_abort(struct usbd_xfer *xfer) 4263 { 4264 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4265 4266 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4267 4268 /* 4269 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4270 * async doorbell. That's dependent on the async list, whereas 4271 * intr xfers are periodic, should not use this? 4272 */ 4273 usbd_xfer_abort(xfer); 4274 } 4275 4276 Static void 4277 ehci_device_intr_close(struct usbd_pipe *pipe) 4278 { 4279 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4280 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4281 struct ehci_soft_islot *isp; 4282 4283 KASSERT(mutex_owned(&sc->sc_lock)); 4284 4285 isp = &sc->sc_islots[epipe->sqh->islot]; 4286 ehci_close_pipe(pipe, isp->sqh); 4287 } 4288 4289 Static void 4290 ehci_device_intr_done(struct usbd_xfer *xfer) 4291 { 4292 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4293 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4294 4295 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4296 4297 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4298 4299 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4300 4301 if (xfer->ux_length) { 4302 int isread, endpt; 4303 4304 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4305 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4306 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4307 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4308 } 4309 } 4310 4311 /************************/ 4312 Static int 4313 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4314 { 4315 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4316 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4317 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4318 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4319 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4320 int i, k, frames; 4321 u_int huba, dir; 4322 int err; 4323 4324 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4325 4326 start = NULL; 4327 sitd = NULL; 4328 4329 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4330 xfer->ux_flags, 0); 4331 4332 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4333 KASSERT(xfer->ux_nframes != 0); 4334 KASSERT(exfer->ex_isdone); 4335 4336 exfer->ex_type = EX_FS_ISOC; 4337 /* 4338 * Step 1: Allocate and initialize sitds. 4339 */ 4340 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4341 if (i > 16 || i == 0) { 4342 /* Spec page 271 says intervals > 16 are invalid */ 4343 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4344 return EINVAL; 4345 } 4346 4347 frames = xfer->ux_nframes; 4348 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4349 sitd = ehci_alloc_sitd(sc); 4350 if (sitd == NULL) { 4351 err = ENOMEM; 4352 goto fail; 4353 } 4354 4355 if (prev) 4356 prev->xfer_next = sitd; 4357 else 4358 start = sitd; 4359 4360 huba = dev->ud_myhsport->up_parent->ud_addr; 4361 4362 #if 0 4363 if (sc->sc_flags & EHCIF_FREESCALE) { 4364 // Set hub address to 0 if embedded TT is used. 4365 if (huba == sc->sc_addr) 4366 huba = 0; 4367 } 4368 #endif 4369 4370 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4371 dir = UE_GET_DIR(k) ? 1 : 0; 4372 sitd->sitd->sitd_endp = 4373 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4374 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4375 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4376 EHCI_SITD_SET_HUBA(huba) | 4377 EHCI_SITD_SET_DIR(dir)); 4378 4379 sitd->sitd->sitd_back = htole32(EHCI_LINK_TERMINATE); 4380 } /* End of frame */ 4381 4382 sitd->sitd->sitd_trans |= htole32(EHCI_SITD_IOC); 4383 4384 stop = sitd; 4385 stop->xfer_next = NULL; 4386 exfer->ex_sitdstart = start; 4387 exfer->ex_sitdend = stop; 4388 4389 return 0; 4390 4391 fail: 4392 mutex_enter(&sc->sc_lock); 4393 ehci_soft_sitd_t *next; 4394 for (sitd = start; sitd; sitd = next) { 4395 next = sitd->xfer_next; 4396 ehci_free_sitd_locked(sc, sitd); 4397 } 4398 mutex_exit(&sc->sc_lock); 4399 4400 return err; 4401 } 4402 4403 Static void 4404 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4405 { 4406 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4407 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4408 4409 KASSERT(ex->ex_type == EX_FS_ISOC); 4410 4411 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4412 } 4413 4414 Static usbd_status 4415 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4416 { 4417 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4418 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4419 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4420 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4421 ehci_soft_sitd_t *sitd; 4422 usb_dma_t *dma_buf; 4423 int i, j, k, frames; 4424 int offs; 4425 int frindex; 4426 u_int dir; 4427 4428 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4429 4430 sitd = NULL; 4431 4432 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4433 xfer->ux_flags, 0); 4434 4435 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4436 4437 if (sc->sc_dying) 4438 return USBD_IOERROR; 4439 4440 /* 4441 * To avoid complication, don't allow a request right now that'll span 4442 * the entire frame table. To within 4 frames, to allow some leeway 4443 * on either side of where the hc currently is. 4444 */ 4445 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4446 xfer->ux_nframes >= sc->sc_flsize - 4) { 4447 printf("ehci: isoc descriptor requested that spans the entire" 4448 " frametable, too many frames\n"); 4449 return USBD_INVAL; 4450 } 4451 4452 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4453 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4454 KASSERT(exfer->ex_isdone); 4455 #ifdef DIAGNOSTIC 4456 exfer->ex_isdone = false; 4457 #endif 4458 4459 /* 4460 * Step 1: Initialize sitds. 4461 */ 4462 4463 frames = xfer->ux_nframes; 4464 dma_buf = &xfer->ux_dmabuf; 4465 offs = 0; 4466 4467 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4468 i++, sitd = sitd->xfer_next) { 4469 KASSERT(sitd != NULL); 4470 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4471 4472 sitd->sitd->sitd_trans = htole32(EHCI_SITD_ACTIVE | 4473 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4474 4475 /* Set page0 index and offset - TP and T-offset are set below */ 4476 const bus_addr_t sba = DMAADDR(dma_buf, offs); 4477 sitd->sitd->sitd_buffer[0] = htole32(BUS_ADDR_LO32(sba)); 4478 sitd->sitd->sitd_buffer_hi[0] = htole32(BUS_ADDR_HI32(sba)); 4479 4480 offs += xfer->ux_frlengths[i]; 4481 4482 const bus_addr_t eba = DMAADDR(dma_buf, offs - 1); 4483 sitd->sitd->sitd_buffer[1] = 4484 htole32(EHCI_SITD_SET_BPTR(BUS_ADDR_LO32(eba))); 4485 sitd->sitd->sitd_buffer_hi[1] = htole32(BUS_ADDR_HI32(eba)); 4486 4487 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4488 4489 #if 0 4490 if (sc->sc_flags & EHCIF_FREESCALE) { 4491 // Set hub address to 0 if embedded TT is used. 4492 if (huba == sc->sc_addr) 4493 huba = 0; 4494 } 4495 #endif 4496 4497 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4498 dir = UE_GET_DIR(k) ? 1 : 0; 4499 KASSERT(sitd->sitd->sitd_endp == htole32( 4500 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4501 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4502 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4503 EHCI_SITD_SET_HUBA(huba) | 4504 EHCI_SITD_SET_DIR(dir))); 4505 KASSERT(sitd->sitd->sitd_back == htole32(EHCI_LINK_TERMINATE)); 4506 4507 uint8_t sa = 0; 4508 uint8_t sb = 0; 4509 u_int temp, tlen; 4510 4511 if (dir == 0) { /* OUT */ 4512 temp = 0; 4513 tlen = xfer->ux_frlengths[i]; 4514 if (tlen <= 188) { 4515 temp |= 1; /* T-count = 1, TP = ALL */ 4516 tlen = 1; 4517 } else { 4518 tlen += 187; 4519 tlen /= 188; 4520 temp |= tlen; /* T-count = [1..6] */ 4521 temp |= 8; /* TP = Begin */ 4522 } 4523 sitd->sitd->sitd_buffer[1] |= htole32(temp); 4524 4525 tlen += sa; 4526 4527 if (tlen >= 8) { 4528 sb = 0; 4529 } else { 4530 sb = (1 << tlen); 4531 } 4532 4533 sa = (1 << sa); 4534 sa = (sb - sa) & 0x3F; 4535 sb = 0; 4536 } else { 4537 sb = (-(4 << sa)) & 0xFE; 4538 sa = (1 << sa) & 0x3F; 4539 sa = 0x01; 4540 sb = 0xfc; 4541 } 4542 4543 sitd->sitd->sitd_sched = htole32( 4544 EHCI_SITD_SET_SMASK(sa) | 4545 EHCI_SITD_SET_CMASK(sb) 4546 ); 4547 4548 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4550 } /* End of frame */ 4551 4552 sitd = exfer->ex_sitdend; 4553 sitd->sitd->sitd_trans |= htole32(EHCI_SITD_IOC); 4554 4555 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4556 sizeof(sitd->sitd->sitd_trans), 4557 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4558 4559 if (xfer->ux_length) 4560 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4561 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4562 4563 /* 4564 * Part 2: Transfer descriptors have now been set up, now they must 4565 * be scheduled into the periodic frame list. Erk. Not wanting to 4566 * complicate matters, transfer is denied if the transfer spans 4567 * more than the periodic frame list. 4568 */ 4569 4570 /* Start inserting frames */ 4571 if (epipe->isoc.cur_xfers > 0) { 4572 frindex = epipe->isoc.next_frame; 4573 } else { 4574 frindex = EOREAD4(sc, EHCI_FRINDEX); 4575 frindex = frindex >> 3; /* Erase microframe index */ 4576 frindex += 2; 4577 } 4578 4579 if (frindex >= sc->sc_flsize) 4580 frindex &= (sc->sc_flsize - 1); 4581 4582 /* What's the frame interval? */ 4583 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4584 4585 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4586 j++, sitd = sitd->xfer_next) { 4587 KASSERT(sitd); 4588 4589 usb_syncmem(&sc->sc_fldma, 4590 sizeof(ehci_link_t) * frindex, 4591 sizeof(ehci_link_t), 4592 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4593 4594 sitd->sitd->sitd_next = sc->sc_flist[frindex]; 4595 if (sitd->sitd->sitd_next == 0) 4596 /* 4597 * FIXME: frindex table gets initialized to NULL 4598 * or EHCI_NULL? 4599 */ 4600 sitd->sitd->sitd_next = EHCI_NULL; 4601 4602 usb_syncmem(&sitd->dma, 4603 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4604 sizeof(ehci_sitd_t), 4605 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4606 4607 sc->sc_flist[frindex] = 4608 htole32(EHCI_LINK_SITD | sitd->physaddr); 4609 4610 usb_syncmem(&sc->sc_fldma, 4611 sizeof(ehci_link_t) * frindex, 4612 sizeof(ehci_link_t), 4613 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4614 4615 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4616 sc->sc_softsitds[frindex] = sitd; 4617 if (sitd->frame_list.next != NULL) 4618 sitd->frame_list.next->frame_list.prev = sitd; 4619 sitd->slot = frindex; 4620 sitd->frame_list.prev = NULL; 4621 4622 frindex += i; 4623 if (frindex >= sc->sc_flsize) 4624 frindex -= sc->sc_flsize; 4625 } 4626 4627 epipe->isoc.cur_xfers++; 4628 epipe->isoc.next_frame = frindex; 4629 4630 ehci_add_intr_list(sc, exfer); 4631 xfer->ux_status = USBD_IN_PROGRESS; 4632 4633 return USBD_IN_PROGRESS; 4634 } 4635 4636 Static void 4637 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4638 { 4639 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4640 4641 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4642 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4643 } 4644 4645 Static void 4646 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4647 { 4648 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4649 4650 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4651 } 4652 4653 Static void 4654 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4655 { 4656 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4657 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4658 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4659 4660 KASSERT(mutex_owned(&sc->sc_lock)); 4661 4662 epipe->isoc.cur_xfers--; 4663 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4664 4665 if (xfer->ux_length) 4666 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4667 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4668 } 4669 4670 /* -------------------------------------------------------------------------- */ 4671 4672 Static int 4673 ehci_device_isoc_init(struct usbd_xfer *xfer) 4674 { 4675 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4676 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4677 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4678 ehci_soft_itd_t *itd, *prev, *start, *stop; 4679 int i, j, k; 4680 int frames, ufrperframe; 4681 int err; 4682 4683 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4684 4685 start = NULL; 4686 prev = NULL; 4687 itd = NULL; 4688 4689 KASSERT(xfer->ux_nframes != 0); 4690 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4691 KASSERT(exfer->ex_isdone); 4692 4693 exfer->ex_type = EX_ISOC; 4694 4695 /* 4696 * Step 1: Allocate and initialize itds, how many do we need? 4697 * One per transfer if interval >= 8 microframes, less if we use 4698 * multiple microframes per frame. 4699 */ 4700 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4701 if (i > 16 || i == 0) { 4702 /* Spec page 271 says intervals > 16 are invalid */ 4703 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4704 return EINVAL; 4705 } 4706 4707 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4708 frames = howmany(xfer->ux_nframes, ufrperframe); 4709 4710 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4711 itd = ehci_alloc_itd(sc); 4712 if (itd == NULL) { 4713 err = ENOMEM; 4714 goto fail; 4715 } 4716 4717 if (prev != NULL) { 4718 /* Maybe not as it's updated by the scheduling? */ 4719 prev->itd->itd_next = 4720 htole32(itd->physaddr | EHCI_LINK_ITD); 4721 4722 prev->xfer_next = itd; 4723 } else { 4724 start = itd; 4725 } 4726 4727 /* 4728 * Other special values 4729 */ 4730 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4731 itd->itd->itd_bufr[0] = htole32( 4732 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4733 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4734 4735 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4736 ? 1 : 0; 4737 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4738 itd->itd->itd_bufr[1] |= htole32( 4739 EHCI_ITD_SET_DIR(k) | 4740 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4741 4742 /* FIXME: handle invalid trans - should be done in openpipe */ 4743 itd->itd->itd_bufr[2] |= 4744 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4745 } /* End of frame */ 4746 4747 stop = itd; 4748 stop->xfer_next = NULL; 4749 4750 exfer->ex_itdstart = start; 4751 exfer->ex_itdend = stop; 4752 4753 return 0; 4754 fail: 4755 mutex_enter(&sc->sc_lock); 4756 ehci_soft_itd_t *next; 4757 for (itd = start; itd; itd = next) { 4758 next = itd->xfer_next; 4759 ehci_free_itd_locked(sc, itd); 4760 } 4761 mutex_exit(&sc->sc_lock); 4762 4763 return err; 4764 4765 } 4766 4767 Static void 4768 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4769 { 4770 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4771 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4772 4773 KASSERT(ex->ex_type == EX_ISOC); 4774 4775 ehci_free_itd_chain(sc, ex->ex_itdstart); 4776 } 4777 4778 Static usbd_status 4779 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4780 { 4781 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4782 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4783 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4784 ehci_soft_itd_t *itd, *prev; 4785 usb_dma_t *dma_buf; 4786 int i, j; 4787 int frames, uframes, ufrperframe; 4788 int trans_count, offs; 4789 int frindex; 4790 4791 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4792 4793 prev = NULL; 4794 itd = NULL; 4795 trans_count = 0; 4796 4797 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4798 4799 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4800 4801 if (sc->sc_dying) 4802 return USBD_IOERROR; 4803 4804 /* 4805 * To avoid complication, don't allow a request right now that'll span 4806 * the entire frame table. To within 4 frames, to allow some leeway 4807 * on either side of where the hc currently is. 4808 */ 4809 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4810 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4811 DPRINTF( 4812 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4813 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4814 return USBD_INVAL; 4815 } 4816 4817 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4818 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4819 KASSERT(exfer->ex_isdone); 4820 #ifdef DIAGNOSTIC 4821 exfer->ex_isdone = false; 4822 #endif 4823 4824 /* 4825 * Step 1: Re-Initialize itds 4826 */ 4827 4828 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4829 if (i > 16 || i == 0) { 4830 /* Spec page 271 says intervals > 16 are invalid */ 4831 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4832 return USBD_INVAL; 4833 } 4834 4835 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4836 frames = howmany(xfer->ux_nframes, ufrperframe); 4837 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4838 4839 if (frames == 0) { 4840 DPRINTF("frames == 0", 0, 0, 0, 0); 4841 return USBD_INVAL; 4842 } 4843 4844 dma_buf = &xfer->ux_dmabuf; 4845 offs = 0; 4846 4847 itd = exfer->ex_itdstart; 4848 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4849 int froffs = offs; 4850 4851 if (prev != NULL) { 4852 prev->itd->itd_next = 4853 htole32(itd->physaddr | EHCI_LINK_ITD); 4854 usb_syncmem(&prev->dma, 4855 prev->offs + offsetof(ehci_itd_t, itd_next), 4856 sizeof(prev->itd->itd_next), BUS_DMASYNC_POSTWRITE); 4857 prev->xfer_next = itd; 4858 } 4859 4860 /* 4861 * Step 1.5, initialize uframes 4862 */ 4863 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4864 /* Calculate which page in the list this starts in */ 4865 int addr = DMAADDR(dma_buf, froffs); 4866 addr = EHCI_PAGE_OFFSET(addr); 4867 addr += (offs - froffs); 4868 addr = EHCI_PAGE(addr); 4869 addr /= EHCI_PAGE_SIZE; 4870 4871 /* 4872 * This gets the initial offset into the first page, 4873 * looks how far further along the current uframe 4874 * offset is. Works out how many pages that is. 4875 */ 4876 4877 itd->itd->itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4878 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4879 EHCI_ITD_SET_PG(addr) | 4880 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4881 4882 offs += xfer->ux_frlengths[trans_count]; 4883 trans_count++; 4884 4885 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4886 itd->itd->itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4887 break; 4888 } 4889 } 4890 4891 /* 4892 * Step 1.75, set buffer pointers. To simplify matters, all 4893 * pointers are filled out for the next 7 hardware pages in 4894 * the dma block, so no need to worry what pages to cover 4895 * and what to not. 4896 */ 4897 4898 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4899 /* 4900 * Don't try to lookup a page that's past the end 4901 * of buffer 4902 */ 4903 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4904 if (page_offs >= dma_buf->udma_block->size) 4905 break; 4906 4907 uint64_t page = DMAADDR(dma_buf, page_offs); 4908 page = EHCI_PAGE(page); 4909 itd->itd->itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4910 itd->itd->itd_bufr_hi[j] = htole32(page >> 32); 4911 } 4912 /* 4913 * Other special values 4914 */ 4915 4916 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4917 itd->itd->itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4918 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4919 4920 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4921 ? 1 : 0; 4922 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4923 itd->itd->itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4924 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4925 4926 /* FIXME: handle invalid trans */ 4927 itd->itd->itd_bufr[2] |= 4928 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4929 4930 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4931 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4932 4933 prev = itd; 4934 } /* End of frame */ 4935 4936 if (xfer->ux_length) 4937 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4938 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4939 4940 /* 4941 * Part 2: Transfer descriptors have now been set up, now they must 4942 * be scheduled into the periodic frame list. Erk. Not wanting to 4943 * complicate matters, transfer is denied if the transfer spans 4944 * more than the periodic frame list. 4945 */ 4946 4947 /* Start inserting frames */ 4948 if (epipe->isoc.cur_xfers > 0) { 4949 frindex = epipe->isoc.next_frame; 4950 } else { 4951 frindex = EOREAD4(sc, EHCI_FRINDEX); 4952 frindex = frindex >> 3; /* Erase microframe index */ 4953 frindex += 2; 4954 } 4955 4956 if (frindex >= sc->sc_flsize) 4957 frindex &= (sc->sc_flsize - 1); 4958 4959 /* What's the frame interval? */ 4960 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4961 if (i / USB_UFRAMES_PER_FRAME == 0) 4962 i = 1; 4963 else 4964 i /= USB_UFRAMES_PER_FRAME; 4965 4966 itd = exfer->ex_itdstart; 4967 for (j = 0; j < frames; j++) { 4968 KASSERTMSG(itd != NULL, "frame %d\n", j); 4969 4970 usb_syncmem(&sc->sc_fldma, 4971 sizeof(ehci_link_t) * frindex, 4972 sizeof(ehci_link_t), 4973 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4974 4975 itd->itd->itd_next = sc->sc_flist[frindex]; 4976 if (itd->itd->itd_next == 0) 4977 /* 4978 * FIXME: frindex table gets initialized to NULL 4979 * or EHCI_NULL? 4980 */ 4981 itd->itd->itd_next = EHCI_NULL; 4982 4983 usb_syncmem(&itd->dma, 4984 itd->offs + offsetof(ehci_itd_t, itd_next), 4985 sizeof(itd->itd->itd_next), 4986 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4987 4988 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4989 4990 usb_syncmem(&sc->sc_fldma, 4991 sizeof(ehci_link_t) * frindex, 4992 sizeof(ehci_link_t), 4993 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4994 4995 itd->frame_list.next = sc->sc_softitds[frindex]; 4996 sc->sc_softitds[frindex] = itd; 4997 if (itd->frame_list.next != NULL) 4998 itd->frame_list.next->frame_list.prev = itd; 4999 itd->slot = frindex; 5000 itd->frame_list.prev = NULL; 5001 5002 frindex += i; 5003 if (frindex >= sc->sc_flsize) 5004 frindex -= sc->sc_flsize; 5005 5006 itd = itd->xfer_next; 5007 } 5008 5009 epipe->isoc.cur_xfers++; 5010 epipe->isoc.next_frame = frindex; 5011 5012 ehci_add_intr_list(sc, exfer); 5013 xfer->ux_status = USBD_IN_PROGRESS; 5014 5015 return USBD_IN_PROGRESS; 5016 } 5017 5018 Static void 5019 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5020 { 5021 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 5022 5023 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 5024 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5025 } 5026 5027 Static void 5028 ehci_device_isoc_close(struct usbd_pipe *pipe) 5029 { 5030 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 5031 5032 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 5033 } 5034 5035 Static void 5036 ehci_device_isoc_done(struct usbd_xfer *xfer) 5037 { 5038 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5039 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5040 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5041 5042 KASSERT(mutex_owned(&sc->sc_lock)); 5043 5044 epipe->isoc.cur_xfers--; 5045 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5046 if (xfer->ux_length) 5047 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5048 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 5049 } 5050
Indexes created Mon Sep 22 13:09:51 GMT 2025