ehci.c revision 1.331
1 /* $NetBSD: ehci.c,v 1.331 2025/02/16 18:24:41 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna23.net), and 11 * Nick Hudson . 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 37 * 38 * The EHCI 1.0 spec can be found at 39 * http://www.intel.com/technology/usb/spec.htm 40 * and the USB 2.0 spec at 41 * http://www.usb.org/developers/docs/ 42 * 43 */ 44 45 /* 46 * TODO: 47 * 1) hold off explorations by companion controllers until ehci has started. 48 * 49 * 2) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 3) Command failures are not recovered correctly. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.331 2025/02/16 18:24:41 jakllsch Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #ifdef _KERNEL_OPT 63 #include "opt_usb.h" 64 #endif 65 66 #include <sys/param.h> 67 68 #include <sys/bus.h> 69 #include <sys/cpu.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/kmem.h> 73 #include <sys/mutex.h> 74 #include <sys/proc.h> 75 #include <sys/queue.h> 76 #include <sys/select.h> 77 #include <sys/sysctl.h> 78 #include <sys/systm.h> 79 #include <sys/reboot.h> 80 81 #include <machine/endian.h> 82 83 #include <dev/usb/usb.h> 84 #include <dev/usb/usbdi.h> 85 #include <dev/usb/usbdivar.h> 86 #include <dev/usb/usbhist.h> 87 #include <dev/usb/usb_mem.h> 88 #include <dev/usb/usb_quirks.h> 89 90 #include <dev/usb/ehcireg.h> 91 #include <dev/usb/ehcivar.h> 92 #include <dev/usb/usbroothub.h> 93 94 #ifdef USB_DEBUG 95 #ifndef EHCI_DEBUG 96 #define ehcidebug 0 97 #else 98 99 #ifndef EHCI_DEBUG_DEFAULT 100 #define EHCI_DEBUG_DEFAULT 0 101 #endif 102 103 static int ehcidebug = EHCI_DEBUG_DEFAULT; 104 105 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 106 { 107 int err; 108 const struct sysctlnode *rnode; 109 const struct sysctlnode *cnode; 110 111 err = sysctl_createv(clog, 0, NULL, &rnode, 112 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 113 SYSCTL_DESCR("ehci global controls"), 114 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 115 116 if (err) 117 goto fail; 118 119 /* control debugging printfs */ 120 err = sysctl_createv(clog, 0, &rnode, &cnode, 121 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 122 "debug", SYSCTL_DESCR("Enable debugging output"), 123 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 124 if (err) 125 goto fail; 126 127 return; 128 fail: 129 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 130 } 131 132 #endif /* EHCI_DEBUG */ 133 #endif /* USB_DEBUG */ 134 135 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 136 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 137 #define EHCIHIST_FUNC() USBHIST_FUNC() 138 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 139 140 struct ehci_pipe { 141 struct usbd_pipe pipe; 142 int nexttoggle; 143 144 ehci_soft_qh_t *sqh; 145 union { 146 /* Control pipe */ 147 struct { 148 usb_dma_t reqdma; 149 } ctrl; 150 /* Interrupt pipe */ 151 struct { 152 u_int length; 153 } intr; 154 /* Iso pipe */ 155 struct { 156 u_int next_frame; 157 u_int cur_xfers; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 163 164 Static usbd_status ehci_open(struct usbd_pipe *); 165 Static void ehci_poll(struct usbd_bus *); 166 Static void ehci_softintr(void *); 167 Static int ehci_intr1(ehci_softc_t *); 168 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 169 ex_completeq_t *); 170 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 171 ex_completeq_t *); 172 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 173 ex_completeq_t *); 174 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 175 Static void ehci_intrlist_timeout(void *); 176 Static void ehci_doorbell(void *); 177 Static void ehci_pcd(void *); 178 179 Static struct usbd_xfer * 180 ehci_allocx(struct usbd_bus *, unsigned int); 181 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 182 183 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 184 Static bool ehci_dying(struct usbd_bus *); 185 Static int ehci_roothub_ctrl(struct usbd_bus *, 186 usb_device_request_t *, void *, int); 187 188 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 189 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 190 Static void ehci_root_intr_abort(struct usbd_xfer *); 191 Static void ehci_root_intr_close(struct usbd_pipe *); 192 Static void ehci_root_intr_done(struct usbd_xfer *); 193 194 Static int ehci_device_ctrl_init(struct usbd_xfer *); 195 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 196 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 197 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 198 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 199 Static void ehci_device_ctrl_close(struct usbd_pipe *); 200 Static void ehci_device_ctrl_done(struct usbd_xfer *); 201 202 Static int ehci_device_bulk_init(struct usbd_xfer *); 203 Static void ehci_device_bulk_fini(struct usbd_xfer *); 204 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 205 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 206 Static void ehci_device_bulk_abort(struct usbd_xfer *); 207 Static void ehci_device_bulk_close(struct usbd_pipe *); 208 Static void ehci_device_bulk_done(struct usbd_xfer *); 209 210 Static int ehci_device_intr_init(struct usbd_xfer *); 211 Static void ehci_device_intr_fini(struct usbd_xfer *); 212 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 213 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 214 Static void ehci_device_intr_abort(struct usbd_xfer *); 215 Static void ehci_device_intr_close(struct usbd_pipe *); 216 Static void ehci_device_intr_done(struct usbd_xfer *); 217 218 Static int ehci_device_isoc_init(struct usbd_xfer *); 219 Static void ehci_device_isoc_fini(struct usbd_xfer *); 220 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 221 Static void ehci_device_isoc_abort(struct usbd_xfer *); 222 Static void ehci_device_isoc_close(struct usbd_pipe *); 223 Static void ehci_device_isoc_done(struct usbd_xfer *); 224 225 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 226 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 227 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 228 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 229 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 230 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 231 232 Static void ehci_device_clear_toggle(struct usbd_pipe *); 233 Static void ehci_noop(struct usbd_pipe *); 234 235 Static void ehci_disown(ehci_softc_t *, int, int); 236 237 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 238 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 239 240 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 241 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 242 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 243 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 244 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 245 246 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 247 int, int, int *, ehci_soft_qtd_t **); 248 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 249 250 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 251 Static ehci_soft_sitd_t * 252 ehci_alloc_sitd(ehci_softc_t *); 253 254 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 255 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 256 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 257 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 258 259 static inline void 260 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 261 { 262 263 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 264 } 265 266 static inline void 267 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 268 { 269 270 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 271 } 272 273 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 274 275 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 276 int); 277 278 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 279 ehci_soft_qh_t *); 280 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 281 ehci_soft_qh_t *); 282 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 283 Static void ehci_sync_hc(ehci_softc_t *); 284 285 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 286 Static void ehci_abortx(struct usbd_xfer *); 287 288 #ifdef EHCI_DEBUG 289 Static ehci_softc_t *theehci; 290 void ehci_dump(void); 291 #endif 292 293 #ifdef EHCI_DEBUG 294 Static void ehci_dump_regs(ehci_softc_t *); 295 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 296 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 297 Static void ehci_dump_qtd(ehci_qtd_t *); 298 Static void ehci_dump_sqh(ehci_soft_qh_t *); 299 Static void ehci_dump_sitd(struct ehci_soft_itd *); 300 Static void ehci_dump_itds(ehci_soft_itd_t *); 301 Static void ehci_dump_itd(struct ehci_soft_itd *); 302 Static void ehci_dump_exfer(struct ehci_xfer *); 303 #endif 304 305 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 306 307 static inline void 308 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 309 { 310 311 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 312 } 313 314 static inline void 315 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 316 { 317 318 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 319 } 320 321 Static const struct usbd_bus_methods ehci_bus_methods = { 322 .ubm_open = ehci_open, 323 .ubm_softint = ehci_softintr, 324 .ubm_dopoll = ehci_poll, 325 .ubm_allocx = ehci_allocx, 326 .ubm_freex = ehci_freex, 327 .ubm_abortx = ehci_abortx, 328 .ubm_dying = ehci_dying, 329 .ubm_getlock = ehci_get_lock, 330 .ubm_rhctrl = ehci_roothub_ctrl, 331 }; 332 333 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 334 .upm_transfer = ehci_root_intr_transfer, 335 .upm_start = ehci_root_intr_start, 336 .upm_abort = ehci_root_intr_abort, 337 .upm_close = ehci_root_intr_close, 338 .upm_cleartoggle = ehci_noop, 339 .upm_done = ehci_root_intr_done, 340 }; 341 342 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 343 .upm_init = ehci_device_ctrl_init, 344 .upm_fini = ehci_device_ctrl_fini, 345 .upm_transfer = ehci_device_ctrl_transfer, 346 .upm_start = ehci_device_ctrl_start, 347 .upm_abort = ehci_device_ctrl_abort, 348 .upm_close = ehci_device_ctrl_close, 349 .upm_cleartoggle = ehci_noop, 350 .upm_done = ehci_device_ctrl_done, 351 }; 352 353 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 354 .upm_init = ehci_device_intr_init, 355 .upm_fini = ehci_device_intr_fini, 356 .upm_transfer = ehci_device_intr_transfer, 357 .upm_start = ehci_device_intr_start, 358 .upm_abort = ehci_device_intr_abort, 359 .upm_close = ehci_device_intr_close, 360 .upm_cleartoggle = ehci_device_clear_toggle, 361 .upm_done = ehci_device_intr_done, 362 }; 363 364 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 365 .upm_init = ehci_device_bulk_init, 366 .upm_fini = ehci_device_bulk_fini, 367 .upm_transfer = ehci_device_bulk_transfer, 368 .upm_start = ehci_device_bulk_start, 369 .upm_abort = ehci_device_bulk_abort, 370 .upm_close = ehci_device_bulk_close, 371 .upm_cleartoggle = ehci_device_clear_toggle, 372 .upm_done = ehci_device_bulk_done, 373 }; 374 375 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 376 .upm_init = ehci_device_isoc_init, 377 .upm_fini = ehci_device_isoc_fini, 378 .upm_transfer = ehci_device_isoc_transfer, 379 .upm_abort = ehci_device_isoc_abort, 380 .upm_close = ehci_device_isoc_close, 381 .upm_cleartoggle = ehci_noop, 382 .upm_done = ehci_device_isoc_done, 383 }; 384 385 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 386 .upm_init = ehci_device_fs_isoc_init, 387 .upm_fini = ehci_device_fs_isoc_fini, 388 .upm_transfer = ehci_device_fs_isoc_transfer, 389 .upm_abort = ehci_device_fs_isoc_abort, 390 .upm_close = ehci_device_fs_isoc_close, 391 .upm_cleartoggle = ehci_noop, 392 .upm_done = ehci_device_fs_isoc_done, 393 }; 394 395 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 396 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 397 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 398 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 399 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 400 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 401 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 402 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 403 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 404 }; 405 406 int 407 ehci_init(ehci_softc_t *sc) 408 { 409 uint32_t vers, hcr; 410 u_int i; 411 int err; 412 ehci_soft_qh_t *sqh; 413 u_int ncomp; 414 415 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 416 #ifdef EHCI_DEBUG 417 theehci = sc; 418 #endif 419 420 mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE); 421 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 422 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 423 cv_init(&sc->sc_doorbell, "ehcidb"); 424 425 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 426 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 427 428 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 429 ehci_doorbell, sc); 430 KASSERT(sc->sc_doorbell_si != NULL); 431 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 432 ehci_pcd, sc); 433 KASSERT(sc->sc_pcd_si != NULL); 434 435 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 436 437 vers = EREAD2(sc, EHCI_HCIVERSION); 438 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 439 vers >> 8, vers & 0xff); 440 441 const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS); 442 DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0); 443 sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams); 444 ncomp = EHCI_HCS_N_CC(hcsparams); 445 if (ncomp != sc->sc_ncomp) { 446 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 447 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 448 #if NOHCI == 0 || NUHCI == 0 449 aprint_error("%s: ohci or uhci probably not configured\n", 450 device_xname(sc->sc_dev)); 451 #endif 452 if (ncomp < sc->sc_ncomp) 453 sc->sc_ncomp = ncomp; 454 } 455 if (sc->sc_ncomp > 0) { 456 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 457 aprint_normal_dev(sc->sc_dev, 458 "%d companion controller%s, %d port%s%s", 459 sc->sc_ncomp, 460 sc->sc_ncomp!=1 ? "s" : "", 461 EHCI_HCS_N_PCC(hcsparams), 462 EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "", 463 sc->sc_ncomp!=1 ? " each" : ""); 464 if (sc->sc_comps[0]) { 465 aprint_normal(":"); 466 for (i = 0; i < sc->sc_ncomp; i++) 467 aprint_normal(" %s", 468 device_xname(sc->sc_comps[i])); 469 } 470 aprint_normal("\n"); 471 472 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB); 473 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE); 474 cv_init(&sc->sc_compcv, "ehciccv"); 475 sc->sc_comp_state = CO_EARLY; 476 } 477 sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams); 478 sc->sc_hasppc = EHCI_HCS_PPC(hcsparams); 479 480 const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS); 481 DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0); 482 483 if (EHCI_HCC_64BIT(hccparams)) { 484 /* MUST clear segment register if 64 bit capable. */ 485 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 486 } 487 488 if (hccparams & EHCI_HCC_IST_FULLFRAME) { 489 sc->sc_istthreshold = 0; 490 } else { 491 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams); 492 } 493 494 sc->sc_bus.ub_revision = USBREV_2_0; 495 sc->sc_bus.ub_usedma = true; 496 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 497 498 /* 499 * The bus attachment code will possibly provide a 64bit DMA 500 * tag which we now limit to the bottom 4G range as 501 * 502 * - that's as much as ehci can address in its QH, TD, iTD, and siTD 503 * structures; and 504 * - the driver doesn't currently set EHCI_CTRLDSSEGMENT to anything 505 * other than 0. 506 */ 507 bus_dma_tag_t ntag = sc->sc_bus.ub_dmatag; 508 sc->sc_dmatag = sc->sc_bus.ub_dmatag; 509 err = bus_dmatag_subregion(sc->sc_bus.ub_dmatag, 0, UINT32_MAX, 510 &ntag, 0); 511 if (err == 0) { 512 sc->sc_dmatag = ntag; 513 aprint_normal_dev(sc->sc_dev, "Using DMA subregion for control" 514 " data structures\n"); 515 } 516 517 /* Reset the controller */ 518 DPRINTF("resetting", 0, 0, 0, 0); 519 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 520 usb_delay_ms(&sc->sc_bus, 1); 521 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 522 for (i = 0; i < 100; i++) { 523 usb_delay_ms(&sc->sc_bus, 1); 524 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 525 if (!hcr) 526 break; 527 } 528 if (hcr) { 529 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 530 err = EIO; 531 goto fail1; 532 } 533 if (sc->sc_vendor_init) 534 sc->sc_vendor_init(sc); 535 536 /* XXX need proper intr scheduling */ 537 sc->sc_rand = 96; 538 539 /* frame list size at default, read back what we got and use that */ 540 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 541 case 0: sc->sc_flsize = 1024; break; 542 case 1: sc->sc_flsize = 512; break; 543 case 2: sc->sc_flsize = 256; break; 544 case 3: 545 err = EIO; 546 goto fail1; 547 } 548 err = usb_allocmem(sc->sc_dmatag, 549 sc->sc_flsize * sizeof(ehci_link_t), 550 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma); 551 if (err) { 552 aprint_error_dev(sc->sc_dev, "failed to allocate frame list\n"); 553 goto fail1; 554 } 555 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0); 556 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 557 558 for (i = 0; i < sc->sc_flsize; i++) { 559 sc->sc_flist[i] = EHCI_NULL; 560 } 561 562 const bus_addr_t flba = DMAADDR(&sc->sc_fldma, 0); 563 const uint32_t hi32 = BUS_ADDR_HI32(flba); 564 if (hi32 != 0) { 565 aprint_error_dev(sc->sc_dev, "DMA memory segment error (%08x)\n", 566 hi32); 567 goto fail2; 568 } 569 570 const uint32_t lo32 = BUS_ADDR_LO32(flba); 571 EOWRITE4(sc, EHCI_PERIODICLISTBASE, lo32); 572 573 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 574 KM_SLEEP); 575 LIST_INIT(&sc->sc_freeitds); 576 LIST_INIT(&sc->sc_freesitds); 577 TAILQ_INIT(&sc->sc_intrhead); 578 579 /* Set up the bus struct. */ 580 sc->sc_bus.ub_methods = &ehci_bus_methods; 581 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe); 582 583 sc->sc_eintrs = EHCI_NORMAL_INTRS; 584 585 /* 586 * Allocate the interrupt dummy QHs. These are arranged to give poll 587 * intervals that are powers of 2 times 1ms. 588 */ 589 memset(sc->sc_islots, 0, sizeof(sc->sc_islots)); 590 for (i = 0; i < EHCI_INTRQHS; i++) { 591 sqh = ehci_alloc_sqh(sc); 592 if (sqh == NULL) { 593 err = ENOMEM; 594 goto fail3; 595 } 596 sc->sc_islots[i].sqh = sqh; 597 } 598 for (i = 0; i < EHCI_INTRQHS; i++) { 599 sqh = sc->sc_islots[i].sqh; 600 if (i == 0) { 601 /* The last (1ms) QH terminates. */ 602 sqh->qh->qh_link = EHCI_NULL; 603 sqh->next = NULL; 604 } else { 605 /* Otherwise the next QH has half the poll interval */ 606 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 607 sqh->qh->qh_link = htole32(sqh->next->physaddr | 608 EHCI_LINK_QH); 609 } 610 sqh->qh->qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 611 sqh->qh->qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 612 sqh->qh->qh_curqtd = EHCI_NULL; 613 614 sqh->qh->qh_qtd.qtd_next = EHCI_NULL; 615 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 616 sqh->qh->qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 617 618 ehci_qtd_t *qh_qtd = &sqh->qh->qh_qtd; 619 for (unsigned n = 0; n < EHCI_QTD_NBUFFERS; n++) { 620 qh_qtd->qtd_buffer[n] = 0; 621 qh_qtd->qtd_buffer_hi[n] = 0; 622 } 623 624 sqh->sqtd = NULL; 625 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 626 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 627 } 628 /* Point the frame list at the last level (128ms). */ 629 for (i = 0; i < sc->sc_flsize; i++) { 630 int j; 631 632 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 633 revbits[i & (EHCI_MAX_POLLRATE-1)]; 634 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 635 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 636 i)].sqh->physaddr); 637 } 638 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 639 BUS_DMASYNC_PREWRITE); 640 641 /* Allocate dummy QH that starts the async list. */ 642 sqh = ehci_alloc_sqh(sc); 643 if (sqh == NULL) { 644 err = ENOMEM; 645 goto fail3; 646 } 647 /* Fill the QH */ 648 sqh->qh->qh_endp = 649 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 650 sqh->qh->qh_link = 651 htole32(sqh->physaddr | EHCI_LINK_QH); 652 sqh->qh->qh_curqtd = EHCI_NULL; 653 sqh->next = NULL; 654 /* Fill the overlay qTD */ 655 sqh->qh->qh_qtd.qtd_next = EHCI_NULL; 656 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 657 sqh->qh->qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 658 659 ehci_qtd_t *qh_qtd = &sqh->qh->qh_qtd; 660 for (unsigned n = 0; n < EHCI_QTD_NBUFFERS; n++) { 661 qh_qtd->qtd_buffer[n] = 0; 662 qh_qtd->qtd_buffer_hi[n] = 0; 663 } 664 665 sqh->sqtd = NULL; 666 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 667 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 668 #ifdef EHCI_DEBUG 669 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 670 ehci_dump_sqh(sqh); 671 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 672 #endif 673 674 /* Point to async list */ 675 sc->sc_async_head = sqh; 676 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 677 678 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 679 680 /* Turn on controller */ 681 EOWRITE4(sc, EHCI_USBCMD, 682 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 683 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 684 EHCI_CMD_ASE | 685 EHCI_CMD_PSE | 686 EHCI_CMD_RS); 687 688 /* Take over port ownership */ 689 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 690 691 for (i = 0; i < 100; i++) { 692 usb_delay_ms(&sc->sc_bus, 1); 693 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 694 if (!hcr) 695 break; 696 } 697 if (hcr) { 698 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 699 err = EIO; 700 goto fail4; 701 } 702 703 /* Enable interrupts */ 704 DPRINTF("enabling interrupts", 0, 0, 0, 0); 705 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 706 707 return 0; 708 709 fail4: 710 ehci_free_sqh(sc, sc->sc_async_head); 711 712 fail3: 713 for (i = 0; i < EHCI_INTRQHS; i++) { 714 sqh = sc->sc_islots[i].sqh; 715 if (sqh) 716 ehci_free_sqh(sc, sqh); 717 } 718 719 kmem_free(sc->sc_softitds, sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 720 721 fail2: 722 usb_freemem(&sc->sc_fldma); 723 724 fail1: 725 softint_disestablish(sc->sc_doorbell_si); 726 softint_disestablish(sc->sc_pcd_si); 727 mutex_destroy(&sc->sc_rhlock); 728 mutex_destroy(&sc->sc_lock); 729 mutex_destroy(&sc->sc_intr_lock); 730 731 return err; 732 } 733 734 int 735 ehci_intr(void *v) 736 { 737 ehci_softc_t *sc = v; 738 int ret = 0; 739 740 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 741 742 if (sc == NULL) 743 return 0; 744 745 mutex_spin_enter(&sc->sc_intr_lock); 746 747 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 748 goto done; 749 750 /* If we get an interrupt while polling, then just ignore it. */ 751 if (sc->sc_bus.ub_usepolling) { 752 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 753 754 if (intrs) 755 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 756 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 757 goto done; 758 } 759 760 ret = ehci_intr1(sc); 761 762 done: 763 mutex_spin_exit(&sc->sc_intr_lock); 764 return ret; 765 } 766 767 Static int 768 ehci_intr1(ehci_softc_t *sc) 769 { 770 uint32_t intrs, eintrs; 771 772 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 773 774 /* In case the interrupt occurs before initialization has completed. */ 775 if (sc == NULL) { 776 #ifdef DIAGNOSTIC 777 printf("ehci_intr1: sc == NULL\n"); 778 #endif 779 return 0; 780 } 781 782 KASSERT(mutex_owned(&sc->sc_intr_lock)); 783 784 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 785 if (!intrs) 786 return 0; 787 788 eintrs = intrs & sc->sc_eintrs; 789 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs, 790 EOREAD4(sc, EHCI_USBSTS), eintrs); 791 if (!eintrs) 792 return 0; 793 794 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 795 if (eintrs & EHCI_STS_IAA) { 796 DPRINTF("door bell", 0, 0, 0, 0); 797 kpreempt_disable(); 798 KASSERT(sc->sc_doorbell_si != NULL); 799 softint_schedule(sc->sc_doorbell_si); 800 kpreempt_enable(); 801 eintrs &= ~EHCI_STS_IAA; 802 } 803 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 804 DPRINTF("INT=%jd ERRINT=%jd", 805 eintrs & EHCI_STS_INT ? 1 : 0, 806 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 807 usb_schedsoftintr(&sc->sc_bus); 808 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 809 } 810 if (eintrs & EHCI_STS_HSE) { 811 printf("%s: unrecoverable error, controller halted\n", 812 device_xname(sc->sc_dev)); 813 /* XXX what else */ 814 } 815 if (eintrs & EHCI_STS_PCD) { 816 kpreempt_disable(); 817 KASSERT(sc->sc_pcd_si != NULL); 818 softint_schedule(sc->sc_pcd_si); 819 kpreempt_enable(); 820 eintrs &= ~EHCI_STS_PCD; 821 } 822 823 if (eintrs != 0) { 824 /* Block unprocessed interrupts. */ 825 sc->sc_eintrs &= ~eintrs; 826 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 827 printf("%s: blocking intrs %#x\n", 828 device_xname(sc->sc_dev), eintrs); 829 } 830 831 return 1; 832 } 833 834 Static void 835 ehci_doorbell(void *addr) 836 { 837 ehci_softc_t *sc = addr; 838 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 839 840 mutex_enter(&sc->sc_lock); 841 if (sc->sc_doorbelllwp == NULL) 842 DPRINTF("spurious doorbell interrupt", 0, 0, 0, 0); 843 sc->sc_doorbelllwp = NULL; 844 cv_broadcast(&sc->sc_doorbell); 845 mutex_exit(&sc->sc_lock); 846 } 847 848 Static void 849 ehci_pcd(void *addr) 850 { 851 ehci_softc_t *sc = addr; 852 struct usbd_xfer *xfer; 853 u_char *p; 854 int i, m; 855 856 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 857 858 mutex_enter(&sc->sc_lock); 859 xfer = sc->sc_intrxfer; 860 861 if (xfer == NULL) { 862 /* Just ignore the change. */ 863 goto done; 864 } 865 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 866 867 p = xfer->ux_buf; 868 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 869 memset(p, 0, xfer->ux_length); 870 for (i = 1; i <= m; i++) { 871 /* Pick out CHANGE bits from the status reg. */ 872 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 873 p[i/8] |= 1 << (i%8); 874 if (i % 8 == 7) 875 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0); 876 } 877 xfer->ux_actlen = xfer->ux_length; 878 xfer->ux_status = USBD_NORMAL_COMPLETION; 879 880 usb_transfer_complete(xfer); 881 882 done: 883 mutex_exit(&sc->sc_lock); 884 } 885 886 Static void 887 ehci_softintr(void *v) 888 { 889 struct usbd_bus *bus = v; 890 ehci_softc_t *sc = EHCI_BUS2SC(bus); 891 struct ehci_xfer *ex, *nextex; 892 893 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 894 895 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 896 897 ex_completeq_t cq; 898 TAILQ_INIT(&cq); 899 900 /* 901 * The only explanation I can think of for why EHCI is as brain dead 902 * as UHCI interrupt-wise is that Intel was involved in both. 903 * An interrupt just tells us that something is done, we have no 904 * clue what, so we need to scan through all active transfers. :-( 905 */ 906 907 /* 908 * ehci_idone will remove transfer from sc->sc_intrhead if it's 909 * complete and add to our cq list 910 * 911 */ 912 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 913 switch (ex->ex_type) { 914 case EX_CTRL: 915 case EX_BULK: 916 case EX_INTR: 917 ehci_check_qh_intr(sc, ex, &cq); 918 break; 919 case EX_ISOC: 920 ehci_check_itd_intr(sc, ex, &cq); 921 break; 922 case EX_FS_ISOC: 923 ehci_check_sitd_intr(sc, ex, &cq); 924 break; 925 default: 926 KASSERT(false); 927 } 928 929 } 930 931 /* 932 * We abuse ex_next for the interrupt and complete lists and 933 * interrupt transfers will get re-added here so use 934 * the _SAFE version of TAILQ_FOREACH. 935 */ 936 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 937 usb_transfer_complete(&ex->ex_xfer); 938 } 939 940 /* Schedule a callout to catch any dropped transactions. */ 941 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 942 !TAILQ_EMPTY(&sc->sc_intrhead)) 943 callout_reset(&sc->sc_tmo_intrlist, 944 hz, ehci_intrlist_timeout, sc); 945 } 946 947 Static void 948 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 949 { 950 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 951 uint32_t status; 952 953 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 954 955 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 956 957 if (ex->ex_type == EX_CTRL) { 958 fsqtd = ex->ex_setup; 959 lsqtd = ex->ex_status; 960 } else { 961 fsqtd = ex->ex_sqtdstart; 962 lsqtd = ex->ex_sqtdend; 963 } 964 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 965 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 966 967 /* 968 * If the last TD is still active we need to check whether there 969 * is an error somewhere in the middle, or whether there was a 970 * short packet (SPD and not ACTIVE). 971 */ 972 usb_syncmem(&lsqtd->dma, 973 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 974 sizeof(lsqtd->qtd->qtd_status), 975 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 976 status = le32toh(lsqtd->qtd->qtd_status); 977 usb_syncmem(&lsqtd->dma, 978 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 979 sizeof(lsqtd->qtd->qtd_status), BUS_DMASYNC_PREREAD); 980 if (status & EHCI_QTD_ACTIVE) { 981 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0); 982 983 /* last qTD has already been checked */ 984 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 985 usb_syncmem(&sqtd->dma, 986 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 987 sizeof(sqtd->qtd->qtd_status), 988 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 989 status = le32toh(sqtd->qtd->qtd_status); 990 usb_syncmem(&sqtd->dma, 991 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 992 sizeof(sqtd->qtd->qtd_status), BUS_DMASYNC_PREREAD); 993 /* If there's an active QTD the xfer isn't done. */ 994 if (status & EHCI_QTD_ACTIVE) 995 break; 996 /* Any kind of error makes the xfer done. */ 997 if (status & EHCI_QTD_HALTED) 998 goto done; 999 /* Handle short packets */ 1000 if (EHCI_QTD_GET_BYTES(status) != 0) { 1001 /* 1002 * If we get here for a control transfer then 1003 * we need to let the hardware complete the 1004 * status phase. That is, we're not done 1005 * quite yet. 1006 * 1007 * Otherwise, we're done. 1008 */ 1009 if (ex->ex_type == EX_CTRL) { 1010 break; 1011 } 1012 goto done; 1013 } 1014 } 1015 DPRINTFN(10, "ex=%#jx std=%#jx still active", 1016 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0); 1017 #ifdef EHCI_DEBUG 1018 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 1019 ehci_dump_sqtds(ex->ex_sqtdstart); 1020 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 1021 #endif 1022 return; 1023 } 1024 done: 1025 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1026 ehci_idone(ex, cq); 1027 } 1028 1029 Static void 1030 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1031 { 1032 ehci_soft_itd_t *itd; 1033 int i; 1034 1035 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1036 1037 KASSERT(mutex_owned(&sc->sc_lock)); 1038 1039 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1040 return; 1041 1042 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 1043 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 1044 1045 itd = ex->ex_itdend; 1046 1047 /* 1048 * check no active transfers in last itd, meaning we're finished 1049 */ 1050 1051 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1052 sizeof(itd->itd->itd_ctl), 1053 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1054 1055 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1056 if (le32toh(itd->itd->itd_ctl[i]) & EHCI_ITD_ACTIVE) 1057 break; 1058 } 1059 1060 if (i == EHCI_ITD_NUFRAMES) { 1061 goto done; /* All 8 descriptors inactive, it's done */ 1062 } 1063 1064 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 1065 sizeof(itd->itd->itd_ctl), BUS_DMASYNC_PREREAD); 1066 1067 DPRINTFN(10, "ex %#jx itd %#jx still active", 1068 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0); 1069 return; 1070 done: 1071 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0); 1072 ehci_idone(ex, cq); 1073 } 1074 1075 void 1076 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 1077 { 1078 ehci_soft_sitd_t *sitd; 1079 1080 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1081 1082 KASSERT(mutex_owned(&sc->sc_lock)); 1083 1084 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1085 return; 1086 1087 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1088 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1089 1090 sitd = ex->ex_sitdend; 1091 1092 /* 1093 * check no active transfers in last sitd, meaning we're finished 1094 */ 1095 1096 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1097 sizeof(sitd->sitd->sitd_trans), 1098 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1099 1100 bool active = ((le32toh(sitd->sitd->sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1101 1102 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1103 sizeof(sitd->sitd->sitd_trans), BUS_DMASYNC_PREREAD); 1104 1105 if (active) 1106 return; 1107 1108 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1109 ehci_idone(ex, cq); 1110 } 1111 1112 Static void 1113 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1114 { 1115 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1116 struct usbd_xfer *xfer = &ex->ex_xfer; 1117 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1118 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1119 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1120 uint32_t status = 0, nstatus = 0; 1121 int actlen = 0; 1122 1123 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1124 1125 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0); 1126 1127 /* 1128 * Try to claim this xfer for completion. If it has already 1129 * completed or aborted, drop it on the floor. 1130 */ 1131 if (!usbd_xfer_trycomplete(xfer)) 1132 return; 1133 1134 #ifdef DIAGNOSTIC 1135 #ifdef EHCI_DEBUG 1136 if (ex->ex_isdone) { 1137 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1138 ehci_dump_exfer(ex); 1139 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1140 } 1141 #endif 1142 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1143 ex->ex_type, xfer->ux_status); 1144 ex->ex_isdone = true; 1145 #endif 1146 1147 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer, 1148 (uintptr_t)epipe, 0, 0); 1149 1150 /* The transfer is done, compute actual length and status. */ 1151 if (ex->ex_type == EX_ISOC) { 1152 /* HS isoc transfer */ 1153 1154 struct ehci_soft_itd *itd; 1155 int i, nframes, len, uframes; 1156 1157 nframes = 0; 1158 1159 #ifdef EHCI_DEBUG 1160 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1161 ehci_dump_itds(ex->ex_itdstart); 1162 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1163 #endif 1164 1165 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1166 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1167 1168 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1169 usb_syncmem(&itd->dma, 1170 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1171 sizeof(itd->itd->itd_ctl), 1172 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1173 1174 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1175 /* 1176 * XXX - driver didn't fill in the frame full 1177 * of uframes. This leads to scheduling 1178 * inefficiencies, but working around 1179 * this doubles complexity of tracking 1180 * an xfer. 1181 */ 1182 if (nframes >= xfer->ux_nframes) 1183 break; 1184 1185 status = le32toh(itd->itd->itd_ctl[i]); 1186 len = EHCI_ITD_GET_LEN(status); 1187 if (EHCI_ITD_GET_STATUS(status) != 0) 1188 len = 0; /*No valid data on error*/ 1189 1190 xfer->ux_frlengths[nframes++] = len; 1191 actlen += len; 1192 } 1193 usb_syncmem(&itd->dma, 1194 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1195 sizeof(itd->itd->itd_ctl), BUS_DMASYNC_PREREAD); 1196 1197 if (nframes >= xfer->ux_nframes) 1198 break; 1199 } 1200 1201 xfer->ux_actlen = actlen; 1202 xfer->ux_status = USBD_NORMAL_COMPLETION; 1203 goto end; 1204 } else if (ex->ex_type == EX_FS_ISOC) { 1205 /* FS isoc transfer */ 1206 struct ehci_soft_sitd *sitd; 1207 int nframes, len; 1208 1209 nframes = 0; 1210 1211 for (sitd = ex->ex_sitdstart; sitd != NULL; 1212 sitd = sitd->xfer_next) { 1213 usb_syncmem(&sitd->dma, 1214 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1215 sizeof(sitd->sitd->sitd_trans), 1216 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1217 1218 /* 1219 * XXX - driver didn't fill in the frame full 1220 * of uframes. This leads to scheduling 1221 * inefficiencies, but working around 1222 * this doubles complexity of tracking 1223 * an xfer. 1224 */ 1225 if (nframes >= xfer->ux_nframes) 1226 break; 1227 1228 status = le32toh(sitd->sitd->sitd_trans); 1229 usb_syncmem(&sitd->dma, 1230 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1231 sizeof(sitd->sitd->sitd_trans), BUS_DMASYNC_PREREAD); 1232 1233 len = EHCI_SITD_GET_LEN(status); 1234 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1235 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1236 /* No valid data on error */ 1237 len = xfer->ux_frlengths[nframes]; 1238 } 1239 1240 /* 1241 * frlengths[i]: # of bytes to send 1242 * len: # of bytes host didn't send 1243 */ 1244 xfer->ux_frlengths[nframes] -= len; 1245 /* frlengths[i]: # of bytes host sent */ 1246 actlen += xfer->ux_frlengths[nframes++]; 1247 1248 if (nframes >= xfer->ux_nframes) 1249 break; 1250 } 1251 1252 xfer->ux_actlen = actlen; 1253 xfer->ux_status = USBD_NORMAL_COMPLETION; 1254 goto end; 1255 } 1256 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1257 ex->ex_type == EX_BULK); 1258 1259 /* Continue processing xfers using queue heads */ 1260 if (ex->ex_type == EX_CTRL) { 1261 fsqtd = ex->ex_setup; 1262 lsqtd = ex->ex_status; 1263 } else { 1264 fsqtd = ex->ex_sqtdstart; 1265 lsqtd = ex->ex_sqtdend; 1266 } 1267 #ifdef EHCI_DEBUG 1268 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1269 ehci_dump_sqtds(fsqtd); 1270 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1271 #endif 1272 1273 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1274 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 1275 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1276 nstatus = le32toh(sqtd->qtd->qtd_status); 1277 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 1278 BUS_DMASYNC_PREREAD); 1279 if (nstatus & EHCI_QTD_ACTIVE) 1280 break; 1281 1282 status = nstatus; 1283 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1284 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1285 } 1286 1287 /* 1288 * If there are left over TDs we need to update the toggle. 1289 * The default pipe doesn't need it since control transfers 1290 * start the toggle at 0 every time. 1291 * For a short transfer we need to update the toggle for the missing 1292 * packets within the qTD. 1293 */ 1294 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1295 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1296 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx", 1297 status, nstatus, 0, 0); 1298 #if 0 1299 ehci_dump_sqh(epipe->sqh); 1300 ehci_dump_sqtds(ex->ex_sqtdstart); 1301 #endif 1302 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1303 } 1304 1305 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen, 1306 status, 0); 1307 xfer->ux_actlen = actlen; 1308 if (status & EHCI_QTD_HALTED) { 1309 #ifdef EHCI_DEBUG 1310 DPRINTF("halted addr=%jd endpt=0x%02jx", 1311 xfer->ux_pipe->up_dev->ud_addr, 1312 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1313 0, 0); 1314 DPRINTF("cerr=%jd pid=%jd", 1315 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1316 0, 0); 1317 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd", 1318 status & EHCI_QTD_ACTIVE ? 1 : 0, 1319 status & EHCI_QTD_HALTED ? 1 : 0, 1320 status & EHCI_QTD_BUFERR ? 1 : 0, 1321 status & EHCI_QTD_BABBLE ? 1 : 0); 1322 1323 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd", 1324 status & EHCI_QTD_XACTERR ? 1 : 0, 1325 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1326 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1327 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1328 1329 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1330 ehci_dump_sqh(epipe->sqh); 1331 ehci_dump_sqtds(ex->ex_sqtdstart); 1332 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1333 #endif 1334 /* low&full speed has an extra error flag */ 1335 if (EHCI_QH_GET_EPS(epipe->sqh->qh->qh_endp) != 1336 EHCI_QH_SPEED_HIGH) 1337 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1338 else 1339 status &= EHCI_QTD_STATERRS; 1340 if (status == 0) /* no other errors means a stall */ { 1341 xfer->ux_status = USBD_STALLED; 1342 } else { 1343 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1344 } 1345 /* XXX need to reset TT on missed microframe */ 1346 if (status & EHCI_QTD_MISSEDMICRO) { 1347 printf("%s: missed microframe, TT reset not " 1348 "implemented, hub might be inoperational\n", 1349 device_xname(sc->sc_dev)); 1350 } 1351 } else { 1352 xfer->ux_status = USBD_NORMAL_COMPLETION; 1353 } 1354 1355 end: 1356 1357 ehci_del_intr_list(sc, ex); 1358 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1359 1360 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0); 1361 } 1362 1363 Static void 1364 ehci_poll(struct usbd_bus *bus) 1365 { 1366 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1367 1368 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1369 1370 #ifdef EHCI_DEBUG 1371 static int last; 1372 int new; 1373 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1374 if (new != last) { 1375 DPRINTF("intrs=0x%04jx", new, 0, 0, 0); 1376 last = new; 1377 } 1378 #endif 1379 1380 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1381 mutex_spin_enter(&sc->sc_intr_lock); 1382 ehci_intr1(sc); 1383 mutex_spin_exit(&sc->sc_intr_lock); 1384 } 1385 } 1386 1387 void 1388 ehci_childdet(device_t self, device_t child) 1389 { 1390 struct ehci_softc *sc = device_private(self); 1391 1392 KASSERT(sc->sc_child == child); 1393 sc->sc_child = NULL; 1394 } 1395 1396 int 1397 ehci_detach(struct ehci_softc *sc, int flags) 1398 { 1399 int rv = 0; 1400 1401 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1402 1403 if (sc->sc_child != NULL) { 1404 rv = config_detach(sc->sc_child, flags); 1405 if (rv != 0) 1406 return rv; 1407 } 1408 1409 if (sc->sc_ncomp > 0) { 1410 mutex_enter(&sc->sc_complock); 1411 /* XXX try to halt callout instead of waiting */ 1412 while (sc->sc_comp_state == CO_SCHED) 1413 cv_wait(&sc->sc_compcv, &sc->sc_complock); 1414 mutex_exit(&sc->sc_complock); 1415 1416 callout_halt(&sc->sc_compcallout, NULL); 1417 callout_destroy(&sc->sc_compcallout); 1418 cv_destroy(&sc->sc_compcv); 1419 mutex_destroy(&sc->sc_complock); 1420 } 1421 1422 callout_halt(&sc->sc_tmo_intrlist, NULL); 1423 callout_destroy(&sc->sc_tmo_intrlist); 1424 1425 /* XXX free other data structures */ 1426 if (sc->sc_softitds) { 1427 kmem_free(sc->sc_softitds, 1428 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1429 } 1430 cv_destroy(&sc->sc_doorbell); 1431 1432 #if 0 1433 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1434 softint_disestablish(sc->sc_doorbell_si); 1435 softint_disestablish(sc->sc_pcd_si); 1436 mutex_destroy(&sc->sc_rhlock); 1437 mutex_destroy(&sc->sc_lock); 1438 mutex_destroy(&sc->sc_intr_lock); 1439 #endif 1440 1441 pool_cache_destroy(sc->sc_xferpool); 1442 1443 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1444 1445 return rv; 1446 } 1447 1448 int 1449 ehci_activate(device_t self, enum devact act) 1450 { 1451 struct ehci_softc *sc = device_private(self); 1452 1453 switch (act) { 1454 case DVACT_DEACTIVATE: 1455 sc->sc_dying = 1; 1456 return 0; 1457 default: 1458 return EOPNOTSUPP; 1459 } 1460 } 1461 1462 /* 1463 * Handle suspend/resume. 1464 * 1465 * Note that this power handler isn't to be registered directly; the 1466 * bus glue needs to call out to it. 1467 */ 1468 bool 1469 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1470 { 1471 ehci_softc_t *sc = device_private(dv); 1472 int i; 1473 uint32_t cmd, hcr; 1474 1475 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1476 1477 mutex_enter(&sc->sc_rhlock); 1478 1479 for (i = 1; i <= sc->sc_noport; i++) { 1480 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1481 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1482 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1483 } 1484 1485 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1486 1487 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1488 EOWRITE4(sc, EHCI_USBCMD, cmd); 1489 1490 for (i = 0; i < 100; i++) { 1491 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1492 if (hcr == 0) 1493 break; 1494 1495 usb_delay_ms(&sc->sc_bus, 1); 1496 } 1497 if (hcr != 0) 1498 printf("%s: reset timeout\n", device_xname(dv)); 1499 1500 cmd &= ~EHCI_CMD_RS; 1501 EOWRITE4(sc, EHCI_USBCMD, cmd); 1502 1503 for (i = 0; i < 100; i++) { 1504 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1505 if (hcr == EHCI_STS_HCH) 1506 break; 1507 1508 usb_delay_ms(&sc->sc_bus, 1); 1509 } 1510 if (hcr != EHCI_STS_HCH) 1511 printf("%s: config timeout\n", device_xname(dv)); 1512 1513 mutex_exit(&sc->sc_rhlock); 1514 1515 return true; 1516 } 1517 1518 bool 1519 ehci_resume(device_t dv, const pmf_qual_t *qual) 1520 { 1521 ehci_softc_t *sc = device_private(dv); 1522 int i; 1523 uint32_t cmd, hcr; 1524 1525 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1526 1527 mutex_enter(&sc->sc_rhlock); 1528 1529 /* restore things in case the bios sucks */ 1530 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1531 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1532 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1533 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1534 1535 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1536 1537 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1538 1539 hcr = 0; 1540 for (i = 1; i <= sc->sc_noport; i++) { 1541 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1542 if ((cmd & EHCI_PS_PO) == 0 && 1543 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1544 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1545 hcr = 1; 1546 } 1547 } 1548 1549 if (hcr) { 1550 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1551 1552 for (i = 1; i <= sc->sc_noport; i++) { 1553 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1554 if ((cmd & EHCI_PS_PO) == 0 && 1555 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1556 EOWRITE4(sc, EHCI_PORTSC(i), 1557 cmd & ~EHCI_PS_FPR); 1558 } 1559 } 1560 1561 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1562 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1563 1564 for (i = 0; i < 100; i++) { 1565 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1566 if (hcr != EHCI_STS_HCH) 1567 break; 1568 1569 usb_delay_ms(&sc->sc_bus, 1); 1570 } 1571 if (hcr == EHCI_STS_HCH) 1572 printf("%s: config timeout\n", device_xname(dv)); 1573 1574 mutex_exit(&sc->sc_rhlock); 1575 1576 return true; 1577 } 1578 1579 /* 1580 * Shut down the controller when the system is going down. 1581 */ 1582 bool 1583 ehci_shutdown(device_t self, int flags) 1584 { 1585 ehci_softc_t *sc = device_private(self); 1586 1587 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1588 1589 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1590 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1591 return true; 1592 } 1593 1594 Static struct usbd_xfer * 1595 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1596 { 1597 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1598 struct usbd_xfer *xfer; 1599 1600 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1601 if (xfer != NULL) { 1602 memset(xfer, 0, sizeof(*xfer)); 1603 1604 #ifdef DIAGNOSTIC 1605 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1606 ex->ex_isdone = true; 1607 xfer->ux_state = XFER_BUSY; 1608 #endif 1609 } 1610 return xfer; 1611 } 1612 1613 Static void 1614 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1615 { 1616 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1617 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1618 1619 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1620 xfer->ux_status == USBD_NOT_STARTED, 1621 "xfer %p state %d\n", xfer, xfer->ux_state); 1622 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED); 1623 1624 #ifdef DIAGNOSTIC 1625 xfer->ux_state = XFER_FREE; 1626 #endif 1627 1628 pool_cache_put(sc->sc_xferpool, xfer); 1629 } 1630 1631 Static bool 1632 ehci_dying(struct usbd_bus *bus) 1633 { 1634 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1635 1636 return sc->sc_dying; 1637 } 1638 1639 Static void 1640 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1641 { 1642 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1643 1644 *lock = &sc->sc_lock; 1645 } 1646 1647 Static void 1648 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1649 { 1650 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1651 1652 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1653 1654 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe, 1655 epipe->sqh->qh->qh_qtd.qtd_status, 0, 0); 1656 #ifdef EHCI_DEBUG 1657 if (ehcidebug) 1658 usbd_dump_pipe(pipe); 1659 #endif 1660 epipe->nexttoggle = 0; 1661 } 1662 1663 Static void 1664 ehci_noop(struct usbd_pipe *pipe) 1665 { 1666 } 1667 1668 #ifdef EHCI_DEBUG 1669 /* 1670 * Unused function - this is meant to be called from a kernel 1671 * debugger. 1672 */ 1673 void 1674 ehci_dump(void) 1675 { 1676 ehci_softc_t *sc = theehci; 1677 int i; 1678 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1679 EOREAD4(sc, EHCI_USBCMD), 1680 EOREAD4(sc, EHCI_USBSTS), 1681 EOREAD4(sc, EHCI_USBINTR)); 1682 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1683 EOREAD4(sc, EHCI_FRINDEX), 1684 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1685 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1686 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1687 for (i = 1; i <= sc->sc_noport; i++) 1688 printf("port %d status=0x%08x\n", i, 1689 EOREAD4(sc, EHCI_PORTSC(i))); 1690 } 1691 1692 Static void 1693 ehci_dump_regs(ehci_softc_t *sc) 1694 { 1695 int i; 1696 1697 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1698 1699 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx", 1700 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1701 EOREAD4(sc, EHCI_USBINTR), 0); 1702 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx " 1703 "async = 0x%08jx", 1704 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1705 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1706 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1707 for (i = 1; i <= sc->sc_noport; i += 2) { 1708 if (i == sc->sc_noport) { 1709 DPRINTF("port %jd status = 0x%08jx", i, 1710 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1711 } else { 1712 DPRINTF("port %jd status = 0x%08jx port %jd " 1713 "status = 0x%08jx", 1714 i, EOREAD4(sc, EHCI_PORTSC(i)), 1715 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1716 } 1717 } 1718 } 1719 1720 #define ehci_dump_link(link, type) do { \ 1721 DPRINTF(" link 0x%08jx (T = %jd):", \ 1722 link, \ 1723 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1724 if (type) { \ 1725 DPRINTF( \ 1726 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\ 1727 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1728 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1729 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1730 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1731 } \ 1732 } while(0) 1733 1734 Static void 1735 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1736 { 1737 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1738 int i; 1739 uint32_t stop = 0; 1740 1741 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1742 ehci_dump_sqtd(sqtd); 1743 usb_syncmem(&sqtd->dma, 1744 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1745 sizeof(sqtd->qtd->qtd_next), 1746 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1747 stop = sqtd->qtd->qtd_next & htole32(EHCI_LINK_TERMINATE); 1748 usb_syncmem(&sqtd->dma, 1749 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1750 sizeof(sqtd->qtd->qtd_next), BUS_DMASYNC_PREREAD); 1751 } 1752 if (!stop) 1753 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1754 } 1755 1756 Static void 1757 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1758 { 1759 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1760 1761 usb_syncmem(&sqtd->dma, sqtd->offs, 1762 sizeof(*sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1763 1764 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr, 1765 0, 0); 1766 ehci_dump_qtd(sqtd->qtd); 1767 1768 usb_syncmem(&sqtd->dma, sqtd->offs, 1769 sizeof(*sqtd->qtd), BUS_DMASYNC_PREREAD); 1770 } 1771 1772 1773 Static void 1774 ehci_dump_qtd(ehci_qtd_t *qtd) 1775 { 1776 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1777 uint32_t s = le32toh(qtd->qtd_status); 1778 1779 DPRINTFN(10, 1780 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx", 1781 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1782 DPRINTFN(10, 1783 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx", 1784 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1785 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1786 DPRINTFN(10, 1787 " cerr = %jd pid = %jd stat = %jx", 1788 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1789 0); 1790 DPRINTFN(10, 1791 "active =%jd halted=%jd buferr=%jd babble=%jd", 1792 s & EHCI_QTD_ACTIVE ? 1 : 0, 1793 s & EHCI_QTD_HALTED ? 1 : 0, 1794 s & EHCI_QTD_BUFERR ? 1 : 0, 1795 s & EHCI_QTD_BABBLE ? 1 : 0); 1796 DPRINTFN(10, 1797 "xacterr=%jd missed=%jd split =%jd ping =%jd", 1798 s & EHCI_QTD_XACTERR ? 1 : 0, 1799 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1800 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1801 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1802 DPRINTFN(10, 1803 "buffer[0] = %#jx buffer[1] = %#jx " 1804 "buffer[2] = %#jx buffer[3] = %#jx", 1805 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1806 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1807 DPRINTFN(10, 1808 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1809 } 1810 1811 Static void 1812 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1813 { 1814 ehci_qh_t *qh = sqh->qh; 1815 ehci_link_t link; 1816 uint32_t endp, endphub; 1817 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1818 1819 usb_syncmem(&sqh->dma, sqh->offs, 1820 sizeof(*sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1821 1822 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0); 1823 link = le32toh(qh->qh_link); 1824 ehci_dump_link(link, true); 1825 1826 endp = le32toh(qh->qh_endp); 1827 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0); 1828 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd " 1829 "eps = %jd", 1830 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1831 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1832 DPRINTFN(10, " dtc = %jd hrecl = %jd", 1833 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1834 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)", 1835 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1836 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1837 1838 endphub = le32toh(qh->qh_endphub); 1839 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0); 1840 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx", 1841 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1842 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd", 1843 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1844 EHCI_QH_GET_MULT(endphub), 0); 1845 1846 link = le32toh(qh->qh_curqtd); 1847 ehci_dump_link(link, false); 1848 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1849 ehci_dump_qtd(&qh->qh_qtd); 1850 1851 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 1852 BUS_DMASYNC_PREREAD); 1853 } 1854 1855 Static void 1856 ehci_dump_itds(ehci_soft_itd_t *itd) 1857 { 1858 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1859 int i; 1860 uint32_t stop = 0; 1861 1862 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1863 ehci_dump_itd(itd); 1864 usb_syncmem(&itd->dma, 1865 itd->offs + offsetof(ehci_itd_t, itd_next), 1866 sizeof(itd->itd->itd_next), 1867 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1868 stop = itd->itd->itd_next & htole32(EHCI_LINK_TERMINATE); 1869 usb_syncmem(&itd->dma, 1870 itd->offs + offsetof(ehci_itd_t, itd_next), 1871 sizeof(itd->itd->itd_next), BUS_DMASYNC_PREREAD); 1872 } 1873 if (!stop) 1874 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1875 } 1876 1877 Static void 1878 ehci_dump_itd(struct ehci_soft_itd *itd) 1879 { 1880 ehci_isoc_trans_t t; 1881 ehci_isoc_bufr_ptr_t b, b2, b3; 1882 int i; 1883 1884 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1885 1886 DPRINTF("ITD: next phys = %#jx", itd->itd->itd_next, 0, 0, 0); 1887 1888 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1889 t = le32toh(itd->itd->itd_ctl[i]); 1890 DPRINTF("ITDctl %jd: stat = %jx len = %jx", 1891 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1892 DPRINTF(" ioc = %jx pg = %jx offs = %jx", 1893 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1894 EHCI_ITD_GET_OFFS(t), 0); 1895 } 1896 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1897 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1898 DPRINTF(" %jx", 1899 EHCI_ITD_GET_BPTR(le32toh(itd->itd->itd_bufr[i])), 0, 0, 0); 1900 1901 b = le32toh(itd->itd->itd_bufr[0]); 1902 b2 = le32toh(itd->itd->itd_bufr[1]); 1903 b3 = le32toh(itd->itd->itd_bufr[2]); 1904 DPRINTF(" ep = %jx daddr = %jx dir = %jd", 1905 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1906 DPRINTF(" maxpkt = %jx multi = %jx", 1907 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1908 } 1909 1910 Static void 1911 ehci_dump_sitd(struct ehci_soft_itd *itd) 1912 { 1913 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1914 1915 DPRINTF("SITD %#jx next = %p prev = %#jx", 1916 (uintptr_t)itd, (uintptr_t)itd->frame_list.next, 1917 (uintptr_t)itd->frame_list.prev, 0); 1918 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd", 1919 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0); 1920 } 1921 1922 Static void 1923 ehci_dump_exfer(struct ehci_xfer *ex) 1924 { 1925 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1926 1927 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type, 1928 ex->ex_isdone, 0); 1929 1930 switch (ex->ex_type) { 1931 case EX_CTRL: 1932 DPRINTF(" setup = %#jx data = %#jx status = %#jx", 1933 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data, 1934 (uintptr_t)ex->ex_status, 0); 1935 break; 1936 case EX_BULK: 1937 case EX_INTR: 1938 DPRINTF(" qtdstart = %#jx qtdend = %#jx", 1939 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend, 1940 0, 0); 1941 break; 1942 case EX_ISOC: 1943 DPRINTF(" itdstart = %#jx itdend = %#jx", 1944 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0); 1945 break; 1946 case EX_FS_ISOC: 1947 DPRINTF(" sitdstart = %#jx sitdend = %#jx", 1948 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend, 1949 0, 0); 1950 break; 1951 default: 1952 DPRINTF(" unknown type", 0, 0, 0, 0); 1953 } 1954 } 1955 #endif 1956 1957 Static usbd_status 1958 ehci_open(struct usbd_pipe *pipe) 1959 { 1960 struct usbd_device *dev = pipe->up_dev; 1961 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1962 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1963 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1964 uint8_t addr = dev->ud_addr; 1965 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1966 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1967 ehci_soft_qh_t *sqh; 1968 usbd_status err; 1969 int ival, speed, naks; 1970 int hshubaddr, hshubport; 1971 1972 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1973 1974 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr, 1975 ed->bEndpointAddress, rhaddr); 1976 1977 if (dev->ud_myhsport) { 1978 /* 1979 * When directly attached FS/LS device while doing embedded 1980 * transaction translations and we are the hub, set the hub 1981 * address to 0 (us). 1982 */ 1983 if (!(sc->sc_flags & EHCIF_ETTF) 1984 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1985 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1986 } else { 1987 hshubaddr = 0; 1988 } 1989 hshubport = dev->ud_myhsport->up_portno; 1990 } else { 1991 hshubaddr = 0; 1992 hshubport = 0; 1993 } 1994 1995 if (sc->sc_dying) 1996 return USBD_IOERROR; 1997 1998 /* toggle state needed for bulk endpoints */ 1999 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 2000 2001 if (addr == rhaddr) { 2002 switch (ed->bEndpointAddress) { 2003 case USB_CONTROL_ENDPOINT: 2004 pipe->up_methods = &roothub_ctrl_methods; 2005 break; 2006 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2007 pipe->up_methods = &ehci_root_intr_methods; 2008 break; 2009 default: 2010 DPRINTF("bad bEndpointAddress 0x%02jx", 2011 ed->bEndpointAddress, 0, 0, 0); 2012 return USBD_INVAL; 2013 } 2014 return USBD_NORMAL_COMPLETION; 2015 } 2016 2017 /* XXX All this stuff is only valid for async. */ 2018 switch (dev->ud_speed) { 2019 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 2020 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 2021 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 2022 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 2023 } 2024 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 2025 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0, 2026 0); 2027 return USBD_INVAL; 2028 } 2029 2030 /* 2031 * For interrupt transfer, nak throttling must be disabled, but for 2032 * the other transfer type, nak throttling should be enabled from the 2033 * viewpoint that avoids the memory thrashing. 2034 */ 2035 naks = (xfertype == UE_INTERRUPT) ? 0 2036 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 2037 2038 /* Allocate sqh for everything, save isoc xfers */ 2039 if (xfertype != UE_ISOCHRONOUS) { 2040 sqh = ehci_alloc_sqh(sc); 2041 if (sqh == NULL) 2042 return USBD_NOMEM; 2043 /* qh_link filled when the QH is added */ 2044 sqh->qh->qh_endp = htole32( 2045 EHCI_QH_SET_ADDR(addr) | 2046 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 2047 EHCI_QH_SET_EPS(speed) | 2048 EHCI_QH_DTC | 2049 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 2050 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 2051 EHCI_QH_CTL : 0) | 2052 EHCI_QH_SET_NRL(naks) 2053 ); 2054 sqh->qh->qh_endphub = htole32( 2055 EHCI_QH_SET_MULT(1) | 2056 (xfertype == UE_INTERRUPT ? 2057 EHCI_QH_SET_SMASK(__BIT(1)) /* Start Split Y1 */ 2058 : 0) 2059 ); 2060 if (speed != EHCI_QH_SPEED_HIGH) 2061 sqh->qh->qh_endphub |= htole32( 2062 EHCI_QH_SET_PORT(hshubport) | 2063 EHCI_QH_SET_HUBA(hshubaddr) | 2064 (xfertype == UE_INTERRUPT ? 2065 EHCI_QH_SET_CMASK(__BITS(3,5)) /* CS Y[345] */ 2066 : 0) 2067 ); 2068 sqh->qh->qh_curqtd = EHCI_NULL; 2069 /* Fill the overlay qTD */ 2070 sqh->qh->qh_qtd.qtd_next = EHCI_NULL; 2071 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 2072 sqh->qh->qh_qtd.qtd_status = htole32(0); 2073 2074 ehci_qtd_t *qh_qtd = &sqh->qh->qh_qtd; 2075 for (unsigned n = 0; n < EHCI_QTD_NBUFFERS; n++) { 2076 qh_qtd->qtd_buffer[n] = 0; 2077 qh_qtd->qtd_buffer_hi[n] = 0; 2078 } 2079 2080 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 2081 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2082 epipe->sqh = sqh; 2083 } else { 2084 sqh = NULL; 2085 } /*xfertype == UE_ISOC*/ 2086 2087 switch (xfertype) { 2088 case UE_CONTROL: 2089 /* we can use 64bit DMA for the reqdma buffer */ 2090 err = usb_allocmem(sc->sc_bus.ub_dmatag, 2091 sizeof(usb_device_request_t), 0, USBMALLOC_COHERENT, 2092 &epipe->ctrl.reqdma); 2093 #ifdef EHCI_DEBUG 2094 if (err) 2095 printf("ehci_open: usb_allocmem()=%d\n", err); 2096 #endif 2097 if (err) 2098 goto bad; 2099 pipe->up_methods = &ehci_device_ctrl_methods; 2100 mutex_enter(&sc->sc_lock); 2101 ehci_add_qh(sc, sqh, sc->sc_async_head); 2102 mutex_exit(&sc->sc_lock); 2103 break; 2104 case UE_BULK: 2105 pipe->up_methods = &ehci_device_bulk_methods; 2106 mutex_enter(&sc->sc_lock); 2107 ehci_add_qh(sc, sqh, sc->sc_async_head); 2108 mutex_exit(&sc->sc_lock); 2109 break; 2110 case UE_INTERRUPT: 2111 pipe->up_methods = &ehci_device_intr_methods; 2112 ival = pipe->up_interval; 2113 if (ival == USBD_DEFAULT_INTERVAL) { 2114 if (speed == EHCI_QH_SPEED_HIGH) { 2115 if (ed->bInterval > 16) { 2116 /* 2117 * illegal with high-speed, but there 2118 * were documentation bugs in the spec, 2119 * so be generous 2120 */ 2121 ival = 256; 2122 } else 2123 ival = (1 << (ed->bInterval - 1)) / 8; 2124 } else 2125 ival = ed->bInterval; 2126 } 2127 err = ehci_device_setintr(sc, sqh, ival); 2128 if (err) 2129 goto bad; 2130 break; 2131 case UE_ISOCHRONOUS: 2132 pipe->up_serialise = false; 2133 if (speed == EHCI_QH_SPEED_HIGH) 2134 pipe->up_methods = &ehci_device_isoc_methods; 2135 else 2136 pipe->up_methods = &ehci_device_fs_isoc_methods; 2137 if (ed->bInterval == 0 || ed->bInterval > 16) { 2138 printf("ehci: opening pipe with invalid bInterval\n"); 2139 err = USBD_INVAL; 2140 goto bad; 2141 } 2142 if (UGETW(ed->wMaxPacketSize) == 0) { 2143 printf("ehci: zero length endpoint open request\n"); 2144 err = USBD_INVAL; 2145 goto bad; 2146 } 2147 epipe->isoc.next_frame = 0; 2148 epipe->isoc.cur_xfers = 0; 2149 break; 2150 default: 2151 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0); 2152 err = USBD_INVAL; 2153 goto bad; 2154 } 2155 return USBD_NORMAL_COMPLETION; 2156 2157 bad: 2158 if (sqh != NULL) { 2159 mutex_enter(&sc->sc_lock); 2160 ehci_free_sqh(sc, sqh); 2161 mutex_exit(&sc->sc_lock); 2162 } 2163 return err; 2164 } 2165 2166 /* 2167 * Add an ED to the schedule. Called with USB lock held. 2168 */ 2169 Static void 2170 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2171 { 2172 2173 KASSERT(mutex_owned(&sc->sc_lock)); 2174 2175 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2176 2177 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2178 sizeof(head->qh->qh_link), BUS_DMASYNC_POSTWRITE); 2179 2180 sqh->next = head->next; 2181 sqh->qh->qh_link = head->qh->qh_link; 2182 2183 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2184 sizeof(sqh->qh->qh_link), BUS_DMASYNC_PREWRITE); 2185 2186 head->next = sqh; 2187 head->qh->qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2188 2189 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2190 sizeof(head->qh->qh_link), BUS_DMASYNC_PREWRITE); 2191 2192 #ifdef EHCI_DEBUG 2193 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2194 ehci_dump_sqh(sqh); 2195 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2196 #endif 2197 } 2198 2199 /* 2200 * Remove an ED from the schedule. Called with USB lock held. 2201 */ 2202 Static void 2203 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2204 { 2205 ehci_soft_qh_t *p; 2206 2207 KASSERT(mutex_owned(&sc->sc_lock)); 2208 2209 /* XXX */ 2210 for (p = head; p != NULL && p->next != sqh; p = p->next) 2211 ; 2212 if (p == NULL) 2213 panic("ehci_rem_qh: ED not found"); 2214 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2215 sizeof(sqh->qh->qh_link), BUS_DMASYNC_POSTWRITE); 2216 p->next = sqh->next; 2217 p->qh->qh_link = sqh->qh->qh_link; 2218 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2219 sizeof(p->qh->qh_link), BUS_DMASYNC_PREWRITE); 2220 2221 ehci_sync_hc(sc); 2222 } 2223 2224 Static void 2225 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2226 { 2227 uint32_t status; 2228 2229 /* Save toggle bit and ping status. */ 2230 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 2231 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2232 status = sqh->qh->qh_qtd.qtd_status & 2233 htole32(EHCI_QTD_TOGGLE_MASK | 2234 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2235 /* Set HALTED to make hw leave it alone. */ 2236 sqh->qh->qh_qtd.qtd_status = 2237 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2238 usb_syncmem(&sqh->dma, 2239 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2240 sizeof(sqh->qh->qh_qtd.qtd_status), 2241 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2242 sqh->qh->qh_curqtd = 0; 2243 sqh->qh->qh_qtd.qtd_next = htole32(sqtd->physaddr); 2244 sqh->qh->qh_qtd.qtd_altnext = EHCI_NULL; 2245 for (unsigned n = 0; n < EHCI_QTD_NBUFFERS; n++) { 2246 sqh->qh->qh_qtd.qtd_buffer[n] = 0; 2247 sqh->qh->qh_qtd.qtd_buffer_hi[n] = 0; 2248 } 2249 2250 sqh->sqtd = sqtd; 2251 usb_syncmem(&sqh->dma, sqh->offs, sizeof(*sqh->qh), 2252 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2253 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2254 sqh->qh->qh_qtd.qtd_status = status; 2255 usb_syncmem(&sqh->dma, 2256 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2257 sizeof(sqh->qh->qh_qtd.qtd_status), 2258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2259 } 2260 2261 /* 2262 * Ensure that the HC has released all references to the QH. We do this 2263 * by asking for a Async Advance Doorbell interrupt and then we wait for 2264 * the interrupt. 2265 * To make this easier we first obtain exclusive use of the doorbell. 2266 * 2267 * Releases the bus lock to sleep while waiting for interrupt. 2268 */ 2269 Static void 2270 ehci_sync_hc(ehci_softc_t *sc) 2271 { 2272 unsigned delta = hz; 2273 unsigned starttime = getticks(); 2274 unsigned endtime = starttime + delta; 2275 unsigned now; 2276 2277 KASSERT(mutex_owned(&sc->sc_lock)); 2278 2279 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2280 2281 if (sc->sc_dying) { 2282 DPRINTF("dying", 0, 0, 0, 0); 2283 return; 2284 } 2285 2286 /* 2287 * Wait until any concurrent ehci_sync_hc has completed so we 2288 * have exclusive access to the doorbell. 2289 */ 2290 while (sc->sc_doorbelllwp) 2291 cv_wait(&sc->sc_doorbell, &sc->sc_lock); 2292 sc->sc_doorbelllwp = curlwp; 2293 2294 /* ask for doorbell */ 2295 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2296 DPRINTF("cmd = 0x%08jx sts = 0x%08jx", 2297 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2298 2299 /* 2300 * Wait for the ehci to ring our doorbell. 2301 */ 2302 while (sc->sc_doorbelllwp == curlwp) { 2303 now = getticks(); 2304 if (now - starttime >= delta) { 2305 sc->sc_doorbelllwp = NULL; 2306 cv_broadcast(&sc->sc_doorbell); 2307 DPRINTF("doorbell timeout", 0, 0, 0, 0); 2308 #ifdef DIAGNOSTIC /* XXX DIAGNOSTIC abuse, do this differently */ 2309 printf("ehci_sync_hc: timed out\n"); 2310 #endif 2311 break; 2312 } 2313 (void)cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, 2314 endtime - now); 2315 } 2316 2317 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done", 2318 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2319 } 2320 2321 Static void 2322 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2323 { 2324 2325 KASSERT(mutex_owned(&sc->sc_lock)); 2326 2327 for (; itd != NULL; itd = itd->xfer_next) { 2328 struct ehci_soft_itd *prev = itd->frame_list.prev; 2329 2330 /* Unlink itd from hardware chain, or frame array */ 2331 if (prev == NULL) { /* We're at the table head */ 2332 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2333 sc->sc_flist[itd->slot] = itd->itd->itd_next; 2334 usb_syncmem(&sc->sc_fldma, 2335 sizeof(ehci_link_t) * itd->slot, 2336 sizeof(ehci_link_t), 2337 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2338 2339 if (itd->frame_list.next != NULL) 2340 itd->frame_list.next->frame_list.prev = NULL; 2341 } else { 2342 /* XXX this part is untested... */ 2343 prev->itd->itd_next = itd->itd->itd_next; 2344 usb_syncmem(&itd->dma, 2345 itd->offs + offsetof(ehci_itd_t, itd_next), 2346 sizeof(itd->itd->itd_next), BUS_DMASYNC_PREWRITE); 2347 2348 prev->frame_list.next = itd->frame_list.next; 2349 if (itd->frame_list.next != NULL) 2350 itd->frame_list.next->frame_list.prev = prev; 2351 } 2352 } 2353 } 2354 2355 Static void 2356 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2357 { 2358 struct ehci_soft_itd *next; 2359 2360 mutex_enter(&sc->sc_lock); 2361 next = NULL; 2362 for (; itd != NULL; itd = next) { 2363 next = itd->xfer_next; 2364 ehci_free_itd_locked(sc, itd); 2365 } 2366 mutex_exit(&sc->sc_lock); 2367 } 2368 2369 Static void 2370 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2371 { 2372 2373 KASSERT(mutex_owned(&sc->sc_lock)); 2374 2375 for (; sitd != NULL; sitd = sitd->xfer_next) { 2376 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2377 2378 /* Unlink sitd from hardware chain, or frame array */ 2379 if (prev == NULL) { /* We're at the table head */ 2380 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2381 sc->sc_flist[sitd->slot] = sitd->sitd->sitd_next; 2382 usb_syncmem(&sc->sc_fldma, 2383 sizeof(ehci_link_t) * sitd->slot, 2384 sizeof(ehci_link_t), 2385 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2386 2387 if (sitd->frame_list.next != NULL) 2388 sitd->frame_list.next->frame_list.prev = NULL; 2389 } else { 2390 /* XXX this part is untested... */ 2391 prev->sitd->sitd_next = sitd->sitd->sitd_next; 2392 usb_syncmem(&sitd->dma, 2393 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2394 sizeof(sitd->sitd->sitd_next), BUS_DMASYNC_PREWRITE); 2395 2396 prev->frame_list.next = sitd->frame_list.next; 2397 if (sitd->frame_list.next != NULL) 2398 sitd->frame_list.next->frame_list.prev = prev; 2399 } 2400 } 2401 } 2402 2403 Static void 2404 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2405 { 2406 2407 mutex_enter(&sc->sc_lock); 2408 struct ehci_soft_sitd *next = NULL; 2409 for (; sitd != NULL; sitd = next) { 2410 next = sitd->xfer_next; 2411 ehci_free_sitd_locked(sc, sitd); 2412 } 2413 mutex_exit(&sc->sc_lock); 2414 } 2415 2416 /***********/ 2417 2418 static int 2419 ehci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req, 2420 void *buf, int buflen) 2421 { 2422 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2423 usb_hub_descriptor_t hubd; 2424 usb_port_status_t ps; 2425 uint16_t len, value, index; 2426 int l, totlen = 0; 2427 int port, i; 2428 uint32_t v; 2429 2430 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2431 2432 KASSERT(mutex_owned(&sc->sc_rhlock)); 2433 2434 if (sc->sc_dying) 2435 return -1; 2436 2437 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest, 2438 0, 0); 2439 2440 len = UGETW(req->wLength); 2441 value = UGETW(req->wValue); 2442 index = UGETW(req->wIndex); 2443 2444 #define C(x,y) ((x) | ((y) << 8)) 2445 switch (C(req->bRequest, req->bmRequestType)) { 2446 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2447 if (len == 0) 2448 break; 2449 switch (value) { 2450 #define sd ((usb_string_descriptor_t *)buf) 2451 case C(2, UDESC_STRING): 2452 /* Product */ 2453 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2454 break; 2455 #undef sd 2456 default: 2457 /* default from usbroothub */ 2458 return buflen; 2459 } 2460 break; 2461 2462 /* Hub requests */ 2463 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2464 break; 2465 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2466 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 2467 value, 0, 0); 2468 if (index < 1 || index > sc->sc_noport) { 2469 return -1; 2470 } 2471 port = EHCI_PORTSC(index); 2472 v = EOREAD4(sc, port); 2473 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2474 v &= ~EHCI_PS_CLEAR; 2475 switch (value) { 2476 case UHF_PORT_ENABLE: 2477 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2478 break; 2479 case UHF_PORT_SUSPEND: 2480 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2481 break; 2482 v &= ~EHCI_PS_SUSP; 2483 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2484 /* see USB2 spec ch. 7.1.7.7 */ 2485 usb_delay_ms(&sc->sc_bus, 20); 2486 EOWRITE4(sc, port, v); 2487 usb_delay_ms(&sc->sc_bus, 2); 2488 #ifdef DEBUG 2489 v = EOREAD4(sc, port); 2490 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2491 printf("ehci: resume failed: %x\n", v); 2492 #endif 2493 break; 2494 case UHF_PORT_POWER: 2495 if (sc->sc_hasppc) 2496 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2497 break; 2498 case UHF_PORT_TEST: 2499 DPRINTF("clear port test %jd", index, 0, 0, 0); 2500 break; 2501 case UHF_PORT_INDICATOR: 2502 DPRINTF("clear port ind %jd", index, 0, 0, 0); 2503 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2504 break; 2505 case UHF_C_PORT_CONNECTION: 2506 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2507 break; 2508 case UHF_C_PORT_ENABLE: 2509 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2510 break; 2511 case UHF_C_PORT_SUSPEND: 2512 /* how? */ 2513 break; 2514 case UHF_C_PORT_OVER_CURRENT: 2515 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2516 break; 2517 case UHF_C_PORT_RESET: 2518 sc->sc_isreset[index] = 0; 2519 break; 2520 default: 2521 return -1; 2522 } 2523 #if 0 2524 switch(value) { 2525 case UHF_C_PORT_CONNECTION: 2526 case UHF_C_PORT_ENABLE: 2527 case UHF_C_PORT_SUSPEND: 2528 case UHF_C_PORT_OVER_CURRENT: 2529 case UHF_C_PORT_RESET: 2530 default: 2531 break; 2532 } 2533 #endif 2534 break; 2535 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2536 if (len == 0) 2537 break; 2538 if ((value & 0xff) != 0) { 2539 return -1; 2540 } 2541 totlen = uimin(buflen, sizeof(hubd)); 2542 memcpy(&hubd, buf, totlen); 2543 hubd.bNbrPorts = sc->sc_noport; 2544 v = EREAD4(sc, EHCI_HCSPARAMS); 2545 USETW(hubd.wHubCharacteristics, 2546 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2547 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2548 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2549 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2550 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2551 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2552 totlen = uimin(totlen, hubd.bDescLength); 2553 memcpy(buf, &hubd, totlen); 2554 break; 2555 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2556 if (len != 4) { 2557 return -1; 2558 } 2559 memset(buf, 0, len); /* ? XXX */ 2560 totlen = len; 2561 break; 2562 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2563 DPRINTF("get port status i=%jd", index, 0, 0, 0); 2564 if (index < 1 || index > sc->sc_noport) { 2565 return -1; 2566 } 2567 if (len != 4) { 2568 return -1; 2569 } 2570 v = EOREAD4(sc, EHCI_PORTSC(index)); 2571 DPRINTF("port status=0x%04jx", v, 0, 0, 0); 2572 2573 i = UPS_HIGH_SPEED; 2574 if (sc->sc_flags & EHCIF_ETTF) { 2575 /* 2576 * If we are doing embedded transaction translation, 2577 * then directly attached LS/FS devices are reset by 2578 * the EHCI controller itself. PSPD is encoded 2579 * the same way as in USBSTATUS. 2580 */ 2581 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2582 } 2583 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2584 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2585 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2586 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2587 if (v & EHCI_PS_PR) i |= UPS_RESET; 2588 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2589 if (sc->sc_vendor_port_status) 2590 i = sc->sc_vendor_port_status(sc, v, i); 2591 USETW(ps.wPortStatus, i); 2592 i = 0; 2593 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2594 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2595 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2596 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2597 USETW(ps.wPortChange, i); 2598 totlen = uimin(len, sizeof(ps)); 2599 memcpy(buf, &ps, totlen); 2600 break; 2601 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2602 return -1; 2603 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2604 break; 2605 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2606 if (index < 1 || index > sc->sc_noport) { 2607 return -1; 2608 } 2609 port = EHCI_PORTSC(index); 2610 v = EOREAD4(sc, port); 2611 DPRINTF("portsc=0x%08jx", v, 0, 0, 0); 2612 v &= ~EHCI_PS_CLEAR; 2613 switch(value) { 2614 case UHF_PORT_ENABLE: 2615 EOWRITE4(sc, port, v | EHCI_PS_PE); 2616 break; 2617 case UHF_PORT_SUSPEND: 2618 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2619 break; 2620 case UHF_PORT_RESET: 2621 DPRINTF("reset port %jd", index, 0, 0, 0); 2622 if (EHCI_PS_IS_LOWSPEED(v) 2623 && sc->sc_ncomp > 0 2624 && !(sc->sc_flags & EHCIF_ETTF)) { 2625 /* 2626 * Low speed device on non-ETTF controller or 2627 * unaccompanied controller, give up ownership. 2628 */ 2629 ehci_disown(sc, index, 1); 2630 break; 2631 } 2632 /* Start reset sequence. */ 2633 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2634 EOWRITE4(sc, port, v | EHCI_PS_PR); 2635 /* Wait for reset to complete. */ 2636 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2637 if (sc->sc_dying) { 2638 return -1; 2639 } 2640 /* 2641 * An embedded transaction translator will automatically 2642 * terminate the reset sequence so there's no need to 2643 * it. 2644 */ 2645 v = EOREAD4(sc, port); 2646 if (v & EHCI_PS_PR) { 2647 /* Terminate reset sequence. */ 2648 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2649 /* Wait for HC to complete reset. */ 2650 usb_delay_ms(&sc->sc_bus, 2651 EHCI_PORT_RESET_COMPLETE); 2652 if (sc->sc_dying) { 2653 return -1; 2654 } 2655 } 2656 2657 v = EOREAD4(sc, port); 2658 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0); 2659 if (v & EHCI_PS_PR) { 2660 printf("%s: port reset timeout\n", 2661 device_xname(sc->sc_dev)); 2662 return USBD_TIMEOUT; 2663 } 2664 if (!(v & EHCI_PS_PE)) { 2665 /* Not a high speed device, give up ownership.*/ 2666 ehci_disown(sc, index, 0); 2667 break; 2668 } 2669 sc->sc_isreset[index] = 1; 2670 DPRINTF("ehci port %jd reset, status = 0x%08jx", index, 2671 v, 0, 0); 2672 break; 2673 case UHF_PORT_POWER: 2674 DPRINTF("set port power %jd (has PPC = %jd)", index, 2675 sc->sc_hasppc, 0, 0); 2676 if (sc->sc_hasppc) 2677 EOWRITE4(sc, port, v | EHCI_PS_PP); 2678 break; 2679 case UHF_PORT_TEST: 2680 DPRINTF("set port test %jd", index, 0, 0, 0); 2681 break; 2682 case UHF_PORT_INDICATOR: 2683 DPRINTF("set port ind %jd", index, 0, 0, 0); 2684 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2685 break; 2686 default: 2687 return -1; 2688 } 2689 break; 2690 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2691 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2692 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2693 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2694 break; 2695 default: 2696 /* default from usbroothub */ 2697 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0); 2698 2699 return buflen; 2700 } 2701 2702 DPRINTF("returning %jd", totlen, 0, 0, 0); 2703 2704 return totlen; 2705 } 2706 2707 Static int 2708 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2709 void *buf, int buflen) 2710 { 2711 struct ehci_softc *sc = EHCI_BUS2SC(bus); 2712 int actlen; 2713 2714 mutex_enter(&sc->sc_rhlock); 2715 actlen = ehci_roothub_ctrl_locked(bus, req, buf, buflen); 2716 mutex_exit(&sc->sc_rhlock); 2717 2718 return actlen; 2719 } 2720 2721 /* 2722 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE. 2723 * 2724 * This pile of garbage below works around the following problem without 2725 * holding boots with no hand-over devices present, while penalising 2726 * boots where the first ehci probe hands off devices with a 5 second 2727 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem 2728 * for RB_SINGLE, but the same basic issue exists. 2729 * 2730 * The way ehci hand-off works, the companion controller does not get the 2731 * device until after its initial bus explore, so the reference dropped 2732 * after the first explore is not enough. 5 seconds should be enough, 2733 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value. 2734 * 2735 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set 2736 * if the callback is scheduled. CO_DONE is set when the callout has 2737 * called config_pending_decr(). 2738 * 2739 * There's a mutex, a cv and a callout here, and we delay detach if the 2740 * callout has been set. 2741 */ 2742 #ifndef EHCI_DISOWN_DELAY_SECONDS 2743 #define EHCI_DISOWN_DELAY_SECONDS 5 2744 #endif 2745 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS; 2746 2747 static void 2748 ehci_disown_callback(void *arg) 2749 { 2750 ehci_softc_t *sc = arg; 2751 2752 config_pending_decr(sc->sc_dev); 2753 2754 mutex_enter(&sc->sc_complock); 2755 KASSERT(sc->sc_comp_state == CO_SCHED); 2756 sc->sc_comp_state = CO_DONE; 2757 cv_signal(&sc->sc_compcv); 2758 mutex_exit(&sc->sc_complock); 2759 } 2760 2761 static void 2762 ehci_disown_sched_callback(ehci_softc_t *sc) 2763 { 2764 extern bool root_is_mounted; 2765 2766 mutex_enter(&sc->sc_complock); 2767 2768 if (root_is_mounted || 2769 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 || 2770 sc->sc_comp_state != CO_EARLY) { 2771 mutex_exit(&sc->sc_complock); 2772 return; 2773 } 2774 2775 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz, 2776 ehci_disown_callback, &sc->sc_dev); 2777 sc->sc_comp_state = CO_SCHED; 2778 2779 mutex_exit(&sc->sc_complock); 2780 2781 config_pending_incr(sc->sc_dev); 2782 aprint_normal_dev(sc->sc_dev, 2783 "delaying %s by %u seconds due to USB owner change.\n", 2784 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user", 2785 ehci_disown_delay_seconds); 2786 } 2787 2788 Static void 2789 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2790 { 2791 int port; 2792 uint32_t v; 2793 2794 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2795 2796 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0); 2797 if (sc->sc_npcomp != 0) { 2798 int i = (index-1) / sc->sc_npcomp; 2799 if (i < sc->sc_ncomp) { 2800 ehci_disown_sched_callback(sc); 2801 #ifdef DIAGNOSTIC 2802 printf("%s: handing over %s speed device on " 2803 "port %d to %s\n", 2804 device_xname(sc->sc_dev), 2805 lowspeed ? "low" : "full", 2806 index, sc->sc_comps[i] ? 2807 device_xname(sc->sc_comps[i]) : 2808 "companion controller"); 2809 } else { 2810 printf("%s: strange port\n", 2811 device_xname(sc->sc_dev)); 2812 #endif 2813 } 2814 } else { 2815 #ifdef DIAGNOSTIC 2816 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2817 #endif 2818 } 2819 port = EHCI_PORTSC(index); 2820 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2821 EOWRITE4(sc, port, v | EHCI_PS_PO); 2822 } 2823 2824 Static usbd_status 2825 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2826 { 2827 2828 /* Pipe isn't running, start first */ 2829 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2830 } 2831 2832 Static usbd_status 2833 ehci_root_intr_start(struct usbd_xfer *xfer) 2834 { 2835 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2836 2837 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2838 2839 if (sc->sc_dying) 2840 return USBD_IOERROR; 2841 2842 KASSERT(sc->sc_intrxfer == NULL); 2843 sc->sc_intrxfer = xfer; 2844 xfer->ux_status = USBD_IN_PROGRESS; 2845 2846 return USBD_IN_PROGRESS; 2847 } 2848 2849 /* Abort a root interrupt request. */ 2850 Static void 2851 ehci_root_intr_abort(struct usbd_xfer *xfer) 2852 { 2853 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2854 2855 KASSERT(mutex_owned(&sc->sc_lock)); 2856 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2857 2858 /* If xfer has already completed, nothing to do here. */ 2859 if (sc->sc_intrxfer == NULL) 2860 return; 2861 2862 /* 2863 * Otherwise, sc->sc_intrxfer had better be this transfer. 2864 * Cancel it. 2865 */ 2866 KASSERT(sc->sc_intrxfer == xfer); 2867 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2868 xfer->ux_status = USBD_CANCELLED; 2869 usb_transfer_complete(xfer); 2870 } 2871 2872 /* Close the root pipe. */ 2873 Static void 2874 ehci_root_intr_close(struct usbd_pipe *pipe) 2875 { 2876 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe); 2877 2878 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2879 2880 KASSERT(mutex_owned(&sc->sc_lock)); 2881 2882 /* 2883 * Caller must guarantee the xfer has completed first, by 2884 * closing the pipe only after normal completion or an abort. 2885 */ 2886 KASSERT(sc->sc_intrxfer == NULL); 2887 } 2888 2889 Static void 2890 ehci_root_intr_done(struct usbd_xfer *xfer) 2891 { 2892 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 2893 2894 KASSERT(mutex_owned(&sc->sc_lock)); 2895 2896 /* Claim the xfer so it doesn't get completed again. */ 2897 KASSERT(sc->sc_intrxfer == xfer); 2898 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 2899 sc->sc_intrxfer = NULL; 2900 } 2901 2902 /************************/ 2903 2904 Static ehci_soft_qh_t * 2905 ehci_alloc_sqh(ehci_softc_t *sc) 2906 { 2907 ehci_soft_qh_t *sqh; 2908 2909 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2910 2911 mutex_enter(&sc->sc_lock); 2912 if (sc->sc_freeqhs == NULL) { 2913 DPRINTF("allocating chunk", 0, 0, 0, 0); 2914 mutex_exit(&sc->sc_lock); 2915 2916 /* 2917 * We can avoid USBMALLOC_COHERENT as the QHs are each on a 2918 * cacheline. 2919 */ 2920 usb_dma_t dma; 2921 int err = usb_allocmem(sc->sc_dmatag, 2922 EHCI_QH_SIZE * EHCI_QH_CHUNK, 2923 EHCI_PAGE_SIZE, 0, &dma); 2924 2925 if (err) { 2926 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2927 return NULL; 2928 } 2929 2930 ehci_soft_qh_t *sqhs = 2931 kmem_zalloc(sizeof(*sqh) * EHCI_QH_CHUNK, KM_SLEEP); 2932 2933 mutex_enter(&sc->sc_lock); 2934 for (size_t i = 0; i < EHCI_QH_CHUNK; i++) { 2935 const int offs = i * EHCI_QH_SIZE; 2936 const bus_addr_t baddr = DMAADDR(&dma, offs); 2937 2938 KASSERT(BUS_ADDR_HI32(baddr) == 0); 2939 2940 sqh = &sqhs[i]; 2941 sqh->qh = KERNADDR(&dma, offs); 2942 sqh->physaddr = BUS_ADDR_LO32(baddr); 2943 sqh->dma = dma; 2944 sqh->offs = offs; 2945 2946 sqh->next = sc->sc_freeqhs; 2947 sc->sc_freeqhs = sqh; 2948 } 2949 } 2950 sqh = sc->sc_freeqhs; 2951 sc->sc_freeqhs = sqh->next; 2952 mutex_exit(&sc->sc_lock); 2953 2954 memset(sqh->qh, 0, sizeof(*sqh->qh)); 2955 sqh->next = NULL; 2956 2957 return sqh; 2958 } 2959 2960 Static void 2961 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2962 { 2963 KASSERT(mutex_owned(&sc->sc_lock)); 2964 2965 sqh->next = sc->sc_freeqhs; 2966 sc->sc_freeqhs = sqh; 2967 } 2968 2969 Static ehci_soft_qtd_t * 2970 ehci_alloc_sqtd(ehci_softc_t *sc) 2971 { 2972 ehci_soft_qtd_t *sqtd = NULL; 2973 2974 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2975 2976 mutex_enter(&sc->sc_lock); 2977 if (sc->sc_freeqtds == NULL) { 2978 DPRINTF("allocating chunk", 0, 0, 0, 0); 2979 mutex_exit(&sc->sc_lock); 2980 2981 usb_dma_t dma; 2982 /* 2983 * We can avoid USBMALLOC_COHERENT as the QTDs are each on a 2984 * cacheline. 2985 */ 2986 int err = usb_allocmem(sc->sc_dmatag, 2987 EHCI_QTD_SIZE * EHCI_QTD_CHUNK, 2988 EHCI_PAGE_SIZE, 0, &dma); 2989 2990 if (err) { 2991 DPRINTF("alloc returned %jd", err, 0, 0, 0); 2992 return NULL; 2993 } 2994 2995 ehci_soft_qtd_t *sqtds = 2996 kmem_zalloc(sizeof(*sqtd) * EHCI_QTD_CHUNK, KM_SLEEP); 2997 2998 mutex_enter(&sc->sc_lock); 2999 for (size_t i = 0; i < EHCI_QTD_CHUNK; i++) { 3000 const int offs = i * EHCI_QTD_SIZE; 3001 const bus_addr_t baddr = DMAADDR(&dma, offs); 3002 3003 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3004 3005 sqtd = &sqtds[i]; 3006 sqtd->qtd = KERNADDR(&dma, offs); 3007 sqtd->physaddr = BUS_ADDR_LO32(baddr); 3008 sqtd->dma = dma; 3009 sqtd->offs = offs; 3010 3011 sqtd->nextqtd = sc->sc_freeqtds; 3012 sc->sc_freeqtds = sqtd; 3013 } 3014 } 3015 3016 sqtd = sc->sc_freeqtds; 3017 sc->sc_freeqtds = sqtd->nextqtd; 3018 mutex_exit(&sc->sc_lock); 3019 3020 memset(sqtd->qtd, 0, sizeof(*sqtd->qtd)); 3021 sqtd->nextqtd = NULL; 3022 sqtd->xfer = NULL; 3023 3024 return sqtd; 3025 } 3026 3027 Static void 3028 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 3029 { 3030 3031 mutex_enter(&sc->sc_lock); 3032 sqtd->nextqtd = sc->sc_freeqtds; 3033 sc->sc_freeqtds = sqtd; 3034 mutex_exit(&sc->sc_lock); 3035 } 3036 3037 Static int 3038 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3039 int alen, int rd, ehci_soft_qtd_t **sp) 3040 { 3041 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3042 uint16_t flags = xfer->ux_flags; 3043 3044 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3045 3046 ASSERT_SLEEPABLE(); 3047 KASSERT(sp); 3048 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 3049 3050 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 3051 nsqtd += howmany(alen, EHCI_PAGE_SIZE); 3052 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 3053 KM_SLEEP); 3054 exfer->ex_nsqtd = nsqtd; 3055 3056 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer, 3057 alen, nsqtd, flags); 3058 3059 for (size_t j = 0; j < exfer->ex_nsqtd;) { 3060 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 3061 if (cur == NULL) 3062 goto nomem; 3063 exfer->ex_sqtds[j++] = cur; 3064 3065 cur->xfer = xfer; 3066 cur->len = 0; 3067 3068 } 3069 3070 *sp = exfer->ex_sqtds[0]; 3071 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0); 3072 3073 return 0; 3074 3075 nomem: 3076 ehci_free_sqtds(sc, exfer); 3077 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 3078 DPRINTF("no memory", 0, 0, 0, 0); 3079 return ENOMEM; 3080 } 3081 3082 Static void 3083 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 3084 { 3085 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3086 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0); 3087 3088 mutex_enter(&sc->sc_lock); 3089 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 3090 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 3091 3092 if (sqtd == NULL) 3093 break; 3094 3095 sqtd->nextqtd = sc->sc_freeqtds; 3096 sc->sc_freeqtds = sqtd; 3097 } 3098 mutex_exit(&sc->sc_lock); 3099 } 3100 3101 Static void 3102 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 3103 { 3104 if (prev) { 3105 prev->nextqtd = sqtd; 3106 prev->qtd->qtd_next = htole32(sqtd->physaddr); 3107 prev->qtd->qtd_altnext = prev->qtd->qtd_next; 3108 usb_syncmem(&prev->dma, prev->offs, sizeof(*prev->qtd), 3109 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3110 } 3111 } 3112 3113 Static void 3114 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 3115 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 3116 { 3117 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3118 usb_dma_t *dma = &xfer->ux_dmabuf; 3119 uint16_t flags = xfer->ux_flags; 3120 ehci_soft_qtd_t *sqtd, *prev; 3121 int tog = *toggle; 3122 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 3123 int len = length; 3124 3125 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3126 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 3127 len, isread, tog); 3128 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0), 3129 0, 0, 0); 3130 3131 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 3132 3133 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 3134 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3135 EHCI_QTD_SET_CERR(3) 3136 ; 3137 3138 sqtd = prev = NULL; 3139 size_t curoffs = 0; 3140 size_t j = 0; 3141 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 3142 sqtd = exfer->ex_sqtds[j++]; 3143 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd, 3144 (uintptr_t)prev, 0); 3145 3146 /* 3147 * The EHCI hardware can handle at most 5 pages and they do 3148 * not have to be contiguous 3149 */ 3150 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 3151 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 3152 size_t curlen = len; 3153 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 3154 /* must use multiple TDs, fill as much as possible. */ 3155 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 3156 3157 /* the length must be a multiple of the max size */ 3158 curlen -= curlen % mps; 3159 } 3160 KASSERT(curlen != 0); 3161 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen, 3162 curoffs, 0); 3163 3164 /* Fill the qTD */ 3165 sqtd->qtd->qtd_next = sqtd->qtd->qtd_altnext = EHCI_NULL; 3166 sqtd->qtd->qtd_status = htole32( 3167 qtdstatus | 3168 EHCI_QTD_SET_BYTES(curlen) | 3169 EHCI_QTD_SET_TOGGLE(tog)); 3170 3171 /* Find number of pages we'll be using, insert dma addresses */ 3172 size_t pages = EHCI_NPAGES(curlen); 3173 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3174 size_t pageoffs = EHCI_PAGE(curoffs); 3175 for (size_t i = 0; i < pages; i++) { 3176 paddr_t a = EHCI_PAGE(DMAADDR(dma, 3177 pageoffs + i * EHCI_PAGE_SIZE)); 3178 sqtd->qtd->qtd_buffer[i] = htole32(BUS_ADDR_LO32(a)); 3179 sqtd->qtd->qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a)); 3180 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx", 3181 i, pages, 3182 le32toh(sqtd->qtd->qtd_buffer_hi[i]), 3183 le32toh(sqtd->qtd->qtd_buffer[i])); 3184 } 3185 /* First buffer pointer requires a page offset to start at */ 3186 sqtd->qtd->qtd_buffer[0] |= htole32(va_offs); 3187 3188 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 3189 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3190 3191 sqtd->len = curlen; 3192 3193 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va, 3194 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 3195 3196 ehci_append_sqtd(sqtd, prev); 3197 3198 if (howmany(curlen, mps) & 1) { 3199 tog ^= 1; 3200 } 3201 3202 curoffs += curlen; 3203 len -= curlen; 3204 } 3205 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 3206 xfer, length, len, mps, exfer->ex_nsqtd, j); 3207 3208 if (!isread && 3209 (flags & USBD_FORCE_SHORT_XFER) && 3210 length % mps == 0) { 3211 /* Force a 0 length transfer at the end. */ 3212 3213 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 3214 exfer->ex_nsqtd); 3215 prev = sqtd; 3216 sqtd = exfer->ex_sqtds[j++]; 3217 memset(sqtd->qtd, 0, sizeof(*sqtd->qtd)); 3218 sqtd->qtd->qtd_next = sqtd->qtd->qtd_altnext = EHCI_NULL; 3219 sqtd->qtd->qtd_status = htole32( 3220 qtdstatus | 3221 EHCI_QTD_SET_BYTES(0) | 3222 EHCI_QTD_SET_TOGGLE(tog)); 3223 3224 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(*sqtd->qtd), 3225 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3226 3227 ehci_append_sqtd(sqtd, prev); 3228 tog ^= 1; 3229 } 3230 3231 *lsqtd = sqtd; 3232 *toggle = tog; 3233 } 3234 3235 Static ehci_soft_itd_t * 3236 ehci_alloc_itd(ehci_softc_t *sc) 3237 { 3238 struct ehci_soft_itd *itd, *freeitd; 3239 3240 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3241 3242 mutex_enter(&sc->sc_lock); 3243 3244 freeitd = LIST_FIRST(&sc->sc_freeitds); 3245 if (freeitd == NULL) { 3246 DPRINTF("allocating chunk", 0, 0, 0, 0); 3247 mutex_exit(&sc->sc_lock); 3248 3249 usb_dma_t dma; 3250 /* 3251 * We can avoid USBMALLOC_COHERENT as the ITDs are each on a 3252 * cacheline. 3253 */ 3254 int err = usb_allocmem(sc->sc_dmatag, 3255 EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3256 EHCI_PAGE_SIZE, 0, &dma); 3257 3258 if (err) { 3259 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3260 return NULL; 3261 } 3262 3263 struct ehci_soft_itd *itds = 3264 kmem_alloc(sizeof(*itd) * EHCI_ITD_CHUNK, KM_SLEEP); 3265 3266 mutex_enter(&sc->sc_lock); 3267 for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) { 3268 const int offs = i * EHCI_ITD_SIZE; 3269 const bus_addr_t baddr = DMAADDR(&dma, offs); 3270 3271 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3272 3273 itd = &itds[i]; 3274 itd->itd = KERNADDR(&dma, offs); 3275 itd->physaddr = BUS_ADDR_LO32(baddr); 3276 itd->dma = dma; 3277 itd->offs = offs; 3278 3279 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3280 } 3281 freeitd = LIST_FIRST(&sc->sc_freeitds); 3282 } 3283 3284 itd = freeitd; 3285 LIST_REMOVE(itd, free_list); 3286 mutex_exit(&sc->sc_lock); 3287 3288 memset(itd->itd, 0, sizeof(*itd->itd)); 3289 itd->frame_list.next = NULL; 3290 itd->frame_list.prev = NULL; 3291 itd->xfer_next = NULL; 3292 itd->slot = 0; 3293 3294 return itd; 3295 } 3296 3297 Static ehci_soft_sitd_t * 3298 ehci_alloc_sitd(ehci_softc_t *sc) 3299 { 3300 struct ehci_soft_sitd *sitd, *freesitd; 3301 3302 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3303 3304 mutex_enter(&sc->sc_lock); 3305 freesitd = LIST_FIRST(&sc->sc_freesitds); 3306 if (freesitd == NULL) { 3307 DPRINTF("allocating chunk", 0, 0, 0, 0); 3308 mutex_exit(&sc->sc_lock); 3309 3310 usb_dma_t dma; 3311 3312 /* 3313 * We can avoid USBMALLOC_COHERENT as the SITDs are each on a 3314 * cacheline. 3315 */ 3316 int err = usb_allocmem(sc->sc_dmatag, 3317 EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3318 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma); 3319 3320 if (err) { 3321 DPRINTF("alloc returned %jd", err, 0, 0, 0); 3322 return NULL; 3323 } 3324 struct ehci_soft_sitd *sitds = 3325 kmem_alloc(sizeof(*sitd) * EHCI_SITD_CHUNK, KM_SLEEP); 3326 3327 mutex_enter(&sc->sc_lock); 3328 for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) { 3329 const int offs = i * EHCI_SITD_SIZE; 3330 const bus_addr_t baddr = DMAADDR(&dma, offs); 3331 3332 KASSERT(BUS_ADDR_HI32(baddr) == 0); 3333 3334 sitd = &sitds[i]; 3335 sitd->itd = KERNADDR(&dma, offs); 3336 sitd->physaddr = BUS_ADDR_LO32(baddr); 3337 sitd->dma = dma; 3338 sitd->offs = offs; 3339 3340 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3341 } 3342 freesitd = LIST_FIRST(&sc->sc_freesitds); 3343 } 3344 3345 sitd = freesitd; 3346 LIST_REMOVE(sitd, free_list); 3347 mutex_exit(&sc->sc_lock); 3348 3349 memset(sitd->sitd, 0, sizeof(*sitd->sitd)); 3350 sitd->frame_list.next = NULL; 3351 sitd->frame_list.prev = NULL; 3352 sitd->xfer_next = NULL; 3353 sitd->slot = 0; 3354 3355 return sitd; 3356 } 3357 3358 /****************/ 3359 3360 /* 3361 * Close a regular pipe. 3362 * Assumes that there are no pending transactions. 3363 */ 3364 Static void 3365 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3366 { 3367 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3368 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3369 ehci_soft_qh_t *sqh = epipe->sqh; 3370 3371 KASSERT(mutex_owned(&sc->sc_lock)); 3372 3373 ehci_rem_qh(sc, sqh, head); 3374 ehci_free_sqh(sc, epipe->sqh); 3375 } 3376 3377 /* 3378 * Arrange for the hardware to tells us that it is not still 3379 * processing the TDs by setting the QH halted bit and wait for the ehci 3380 * door bell 3381 */ 3382 Static void 3383 ehci_abortx(struct usbd_xfer *xfer) 3384 { 3385 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3386 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3387 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3388 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3389 ehci_soft_qh_t *sqh = epipe->sqh; 3390 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3391 ehci_physaddr_t cur; 3392 uint32_t qhstatus; 3393 int hit; 3394 3395 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0); 3396 3397 KASSERT(mutex_owned(&sc->sc_lock)); 3398 ASSERT_SLEEPABLE(); 3399 3400 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 3401 xfer->ux_status == USBD_TIMEOUT), 3402 "bad abort status: %d", xfer->ux_status); 3403 3404 /* 3405 * If we're dying, skip the hardware action and just notify the 3406 * software that we're done. 3407 */ 3408 if (sc->sc_dying) { 3409 goto dying; 3410 } 3411 3412 /* 3413 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3414 */ 3415 ehci_del_intr_list(sc, exfer); 3416 3417 usb_syncmem(&sqh->dma, 3418 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3419 sizeof(sqh->qh->qh_qtd.qtd_status), 3420 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3421 qhstatus = sqh->qh->qh_qtd.qtd_status; 3422 sqh->qh->qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3423 usb_syncmem(&sqh->dma, 3424 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3425 sizeof(sqh->qh->qh_qtd.qtd_status), 3426 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3427 3428 if (exfer->ex_type == EX_CTRL) { 3429 fsqtd = exfer->ex_setup; 3430 lsqtd = exfer->ex_status; 3431 } else { 3432 fsqtd = exfer->ex_sqtdstart; 3433 lsqtd = exfer->ex_sqtdend; 3434 } 3435 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3436 usb_syncmem(&sqtd->dma, 3437 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3438 sizeof(sqtd->qtd->qtd_status), 3439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3440 sqtd->qtd->qtd_status |= htole32(EHCI_QTD_HALTED); 3441 usb_syncmem(&sqtd->dma, 3442 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3443 sizeof(sqtd->qtd->qtd_status), 3444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3445 if (sqtd == lsqtd) 3446 break; 3447 } 3448 3449 /* 3450 * HC Step 2: Wait until we know hardware has finished any possible 3451 * use of the xfer. 3452 */ 3453 ehci_sync_hc(sc); 3454 3455 /* 3456 * HC Step 3: Remove any vestiges of the xfer from the hardware. 3457 * The complication here is that the hardware may have executed 3458 * beyond the xfer we're trying to abort. So as we're scanning 3459 * the TDs of this xfer we check if the hardware points to 3460 * any of them. 3461 */ 3462 3463 usb_syncmem(&sqh->dma, 3464 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3465 sizeof(sqh->qh->qh_curqtd), 3466 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3467 cur = EHCI_LINK_ADDR(le32toh(sqh->qh->qh_curqtd)); 3468 hit = 0; 3469 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3470 hit |= cur == sqtd->physaddr; 3471 if (sqtd == lsqtd) 3472 break; 3473 } 3474 sqtd = sqtd->nextqtd; 3475 /* Zap curqtd register if hardware pointed inside the xfer. */ 3476 if (hit && sqtd != NULL) { 3477 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0); 3478 sqh->qh->qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3479 usb_syncmem(&sqh->dma, 3480 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3481 sizeof(sqh->qh->qh_curqtd), 3482 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3483 sqh->qh->qh_qtd.qtd_status = qhstatus; 3484 usb_syncmem(&sqh->dma, 3485 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3486 sizeof(sqh->qh->qh_qtd.qtd_status), 3487 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3488 } else { 3489 DPRINTF("no hit", 0, 0, 0, 0); 3490 usb_syncmem(&sqh->dma, 3491 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3492 sizeof(sqh->qh->qh_curqtd), 3493 BUS_DMASYNC_PREREAD); 3494 } 3495 3496 dying: 3497 #ifdef DIAGNOSTIC 3498 exfer->ex_isdone = true; 3499 #endif 3500 DPRINTFN(14, "end", 0, 0, 0, 0); 3501 3502 KASSERT(mutex_owned(&sc->sc_lock)); 3503 } 3504 3505 Static void 3506 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3507 { 3508 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3509 ehci_isoc_trans_t trans_status; 3510 struct ehci_xfer *exfer; 3511 ehci_softc_t *sc; 3512 struct ehci_soft_itd *itd; 3513 struct ehci_soft_sitd *sitd; 3514 int i; 3515 3516 KASSERTMSG(status == USBD_CANCELLED, 3517 "invalid status for abort: %d", (int)status); 3518 3519 exfer = EHCI_XFER2EXFER(xfer); 3520 sc = EHCI_XFER2SC(xfer); 3521 3522 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer, 3523 (uintptr_t)xfer->ux_pipe, 0, 0); 3524 3525 KASSERT(mutex_owned(&sc->sc_lock)); 3526 ASSERT_SLEEPABLE(); 3527 3528 /* No timeout or task here. */ 3529 3530 /* 3531 * The xfer cannot have been cancelled already. It is the 3532 * responsibility of the caller of usbd_abort_pipe not to try 3533 * to abort a pipe multiple times, whether concurrently or 3534 * sequentially. 3535 */ 3536 KASSERT(xfer->ux_status != USBD_CANCELLED); 3537 3538 /* If anyone else beat us, we're done. */ 3539 if (xfer->ux_status != USBD_IN_PROGRESS) 3540 return; 3541 3542 /* We beat everyone else. Claim the status. */ 3543 xfer->ux_status = status; 3544 3545 /* 3546 * If we're dying, skip the hardware action and just notify the 3547 * software that we're done. 3548 */ 3549 if (sc->sc_dying) { 3550 goto dying; 3551 } 3552 3553 /* 3554 * HC Step 1: Make interrupt routine and hardware ignore xfer. 3555 */ 3556 ehci_del_intr_list(sc, exfer); 3557 3558 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3559 for (itd = exfer->ex_itdstart; itd != NULL; 3560 itd = itd->xfer_next) { 3561 usb_syncmem(&itd->dma, 3562 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3563 sizeof(itd->itd->itd_ctl), 3564 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3565 3566 for (i = 0; i < 8; i++) { 3567 trans_status = le32toh(itd->itd->itd_ctl[i]); 3568 trans_status &= ~EHCI_ITD_ACTIVE; 3569 itd->itd->itd_ctl[i] = htole32(trans_status); 3570 } 3571 3572 usb_syncmem(&itd->dma, 3573 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3574 sizeof(itd->itd->itd_ctl), 3575 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3576 } 3577 } else { 3578 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3579 sitd = sitd->xfer_next) { 3580 usb_syncmem(&sitd->dma, 3581 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3582 sizeof(sitd->sitd->sitd_buffer), 3583 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3584 3585 trans_status = le32toh(sitd->sitd->sitd_trans); 3586 trans_status &= ~EHCI_SITD_ACTIVE; 3587 sitd->sitd->sitd_trans = htole32(trans_status); 3588 3589 usb_syncmem(&sitd->dma, 3590 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3591 sizeof(sitd->sitd->sitd_buffer), 3592 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3593 } 3594 } 3595 3596 dying: 3597 #ifdef DIAGNOSTIC 3598 exfer->ex_isdone = true; 3599 #endif 3600 usb_transfer_complete(xfer); 3601 DPRINTFN(14, "end", 0, 0, 0, 0); 3602 3603 KASSERT(mutex_owned(&sc->sc_lock)); 3604 } 3605 3606 /************************/ 3607 3608 Static int 3609 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3610 { 3611 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3612 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3613 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3614 usb_device_request_t *req = &xfer->ux_request; 3615 ehci_soft_qtd_t *setup, *status, *next; 3616 int isread = req->bmRequestType & UT_READ; 3617 int len = xfer->ux_bufsize; 3618 int err; 3619 3620 exfer->ex_type = EX_CTRL; 3621 exfer->ex_status = NULL; 3622 exfer->ex_data = NULL; 3623 exfer->ex_setup = ehci_alloc_sqtd(sc); 3624 if (exfer->ex_setup == NULL) { 3625 err = ENOMEM; 3626 goto bad1; 3627 } 3628 exfer->ex_status = ehci_alloc_sqtd(sc); 3629 if (exfer->ex_status == NULL) { 3630 err = ENOMEM; 3631 goto bad2; 3632 } 3633 setup = exfer->ex_setup; 3634 status = exfer->ex_status; 3635 exfer->ex_nsqtd = 0; 3636 next = status; 3637 /* Set up data transaction */ 3638 if (len != 0) { 3639 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3640 &exfer->ex_data); 3641 if (err) 3642 goto bad3; 3643 next = exfer->ex_data; 3644 } 3645 3646 /* Clear toggle */ 3647 setup->qtd->qtd_status = htole32( 3648 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3649 EHCI_QTD_SET_TOGGLE(0) | 3650 EHCI_QTD_SET_BYTES(sizeof(*req)) 3651 ); 3652 3653 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3654 setup->qtd->qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3655 setup->qtd->qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3656 setup->qtd->qtd_next = setup->qtd->qtd_altnext = htole32(next->physaddr); 3657 setup->nextqtd = next; 3658 setup->xfer = xfer; 3659 setup->len = sizeof(*req); 3660 3661 status->qtd->qtd_status = htole32( 3662 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3663 EHCI_QTD_SET_TOGGLE(1) | 3664 EHCI_QTD_IOC 3665 ); 3666 status->qtd->qtd_buffer[0] = 0; 3667 status->qtd->qtd_buffer_hi[0] = 0; 3668 status->qtd->qtd_next = status->qtd->qtd_altnext = EHCI_NULL; 3669 status->nextqtd = NULL; 3670 status->xfer = xfer; 3671 status->len = 0; 3672 3673 return 0; 3674 bad3: 3675 ehci_free_sqtd(sc, exfer->ex_status); 3676 bad2: 3677 ehci_free_sqtd(sc, exfer->ex_setup); 3678 bad1: 3679 return err; 3680 } 3681 3682 Static void 3683 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3684 { 3685 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3686 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3687 3688 KASSERT(ex->ex_type == EX_CTRL); 3689 3690 ehci_free_sqtd(sc, ex->ex_setup); 3691 ehci_free_sqtd(sc, ex->ex_status); 3692 ehci_free_sqtds(sc, ex); 3693 if (ex->ex_nsqtd) 3694 kmem_free(ex->ex_sqtds, 3695 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3696 } 3697 3698 Static usbd_status 3699 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3700 { 3701 3702 /* Pipe isn't running, start first */ 3703 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3704 } 3705 3706 Static usbd_status 3707 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3708 { 3709 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3710 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3711 usb_device_request_t *req = &xfer->ux_request; 3712 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3713 ehci_soft_qtd_t *setup, *status, *next; 3714 ehci_soft_qh_t *sqh; 3715 3716 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3717 3718 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3719 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3720 3721 if (sc->sc_dying) 3722 return USBD_IOERROR; 3723 3724 const int isread = req->bmRequestType & UT_READ; 3725 const int len = UGETW(req->wLength); 3726 3727 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 3728 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3729 UGETW(req->wIndex)); 3730 DPRINTF("len=%jd, addr=%jd, endpt=%jd", 3731 len, epipe->pipe.up_dev->ud_addr, 3732 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3733 3734 sqh = epipe->sqh; 3735 3736 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh->qh_endp)) == epipe->pipe.up_dev->ud_addr, 3737 "address QH %" __PRIuBIT " pipe %d\n", 3738 EHCI_QH_GET_ADDR(le32toh(sqh->qh->qh_endp)), 3739 epipe->pipe.up_dev->ud_addr); 3740 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh->qh_endp)) == 3741 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3742 "MPS QH %" __PRIuBIT " pipe %d\n", 3743 EHCI_QH_GET_MPL(le32toh(sqh->qh->qh_endp)), 3744 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3745 3746 setup = exfer->ex_setup; 3747 status = exfer->ex_status; 3748 3749 DPRINTF("setup %#jx status %#jx data %#jx", 3750 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0); 3751 KASSERTMSG(setup != NULL && status != NULL, 3752 "Failed memory allocation, setup %p status %p", 3753 setup, status); 3754 3755 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3756 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3757 3758 /* Clear toggle */ 3759 setup->qtd->qtd_status &= ~htole32( 3760 EHCI_QTD_STATUS_MASK | 3761 EHCI_QTD_BYTES_MASK | 3762 EHCI_QTD_TOGGLE_MASK | 3763 EHCI_QTD_CERR_MASK 3764 ); 3765 setup->qtd->qtd_status |= htole32( 3766 EHCI_QTD_ACTIVE | 3767 EHCI_QTD_SET_CERR(3) | 3768 EHCI_QTD_SET_TOGGLE(0) | 3769 EHCI_QTD_SET_BYTES(sizeof(*req)) 3770 ); 3771 3772 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0); 3773 setup->qtd->qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba)); 3774 setup->qtd->qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba)); 3775 3776 next = status; 3777 status->qtd->qtd_status &= ~htole32( 3778 EHCI_QTD_STATUS_MASK | 3779 EHCI_QTD_PID_MASK | 3780 EHCI_QTD_BYTES_MASK | 3781 EHCI_QTD_TOGGLE_MASK | 3782 EHCI_QTD_CERR_MASK 3783 ); 3784 status->qtd->qtd_status |= htole32( 3785 EHCI_QTD_ACTIVE | 3786 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3787 EHCI_QTD_SET_CERR(3) | 3788 EHCI_QTD_SET_TOGGLE(1) | 3789 EHCI_QTD_SET_BYTES(0) | 3790 EHCI_QTD_IOC 3791 ); 3792 KASSERT(status->qtd->qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3793 3794 KASSERT(exfer->ex_isdone); 3795 #ifdef DIAGNOSTIC 3796 exfer->ex_isdone = false; 3797 #endif 3798 3799 /* Set up data transaction */ 3800 if (len != 0) { 3801 ehci_soft_qtd_t *end; 3802 3803 /* Start toggle at 1. */ 3804 int toggle = 1; 3805 next = exfer->ex_data; 3806 KASSERTMSG(next != NULL, "Failed memory allocation"); 3807 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3808 end->nextqtd = status; 3809 end->qtd->qtd_next = end->qtd->qtd_altnext = 3810 htole32(status->physaddr); 3811 3812 usb_syncmem(&end->dma, end->offs, sizeof(*end->qtd), 3813 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3814 3815 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3816 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3817 } 3818 3819 setup->nextqtd = next; 3820 setup->qtd->qtd_next = setup->qtd->qtd_altnext = htole32(next->physaddr); 3821 3822 usb_syncmem(&setup->dma, setup->offs, sizeof(*setup->qtd), 3823 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3824 3825 usb_syncmem(&status->dma, status->offs, sizeof(*status->qtd), 3826 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3827 3828 KASSERT(status->qtd->qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3829 3830 #ifdef EHCI_DEBUG 3831 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3832 ehci_dump_sqh(sqh); 3833 ehci_dump_sqtds(setup); 3834 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3835 #endif 3836 3837 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3838 ehci_set_qh_qtd(sqh, setup); 3839 ehci_add_intr_list(sc, exfer); 3840 xfer->ux_status = USBD_IN_PROGRESS; 3841 usbd_xfer_schedule_timeout(xfer); 3842 3843 #if 0 3844 #ifdef EHCI_DEBUG 3845 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3846 // delay(10000); 3847 ehci_dump_regs(sc); 3848 ehci_dump_sqh(sc->sc_async_head); 3849 ehci_dump_sqh(sqh); 3850 ehci_dump_sqtds(setup); 3851 #endif 3852 #endif 3853 3854 return USBD_IN_PROGRESS; 3855 } 3856 3857 Static void 3858 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3859 { 3860 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3861 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3862 usb_device_request_t *req = &xfer->ux_request; 3863 int len = UGETW(req->wLength); 3864 int rd = req->bmRequestType & UT_READ; 3865 3866 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3867 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3868 3869 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3870 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3871 3872 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3873 BUS_DMASYNC_POSTWRITE); 3874 if (len) 3875 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3876 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3877 3878 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3879 } 3880 3881 /* Abort a device control request. */ 3882 Static void 3883 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3884 { 3885 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3886 3887 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3888 usbd_xfer_abort(xfer); 3889 } 3890 3891 /* Close a device control pipe. */ 3892 Static void 3893 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3894 { 3895 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3896 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe); 3897 3898 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3899 3900 KASSERT(mutex_owned(&sc->sc_lock)); 3901 3902 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3903 3904 ehci_close_pipe(pipe, sc->sc_async_head); 3905 3906 usb_freemem(&epipe->ctrl.reqdma); 3907 } 3908 3909 /* 3910 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3911 * qTD status, or miss signalling occasionally under heavy load. If the host 3912 * machine is too fast, we can miss transaction completion - when we scan 3913 * the active list the transaction still seems to be active. This generally 3914 * exhibits itself as a umass stall that never recovers. 3915 * 3916 * We work around this behaviour by setting up this callback after any softintr 3917 * that completes with transactions still pending, giving us another chance to 3918 * check for completion after the writeback has taken place. 3919 */ 3920 Static void 3921 ehci_intrlist_timeout(void *arg) 3922 { 3923 ehci_softc_t *sc = arg; 3924 3925 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3926 3927 usb_schedsoftintr(&sc->sc_bus); 3928 } 3929 3930 /************************/ 3931 3932 Static int 3933 ehci_device_bulk_init(struct usbd_xfer *xfer) 3934 { 3935 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3936 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3937 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3938 int endpt = ed->bEndpointAddress; 3939 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3940 int len = xfer->ux_bufsize; 3941 int err = 0; 3942 3943 exfer->ex_type = EX_BULK; 3944 exfer->ex_nsqtd = 0; 3945 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3946 &exfer->ex_sqtdstart); 3947 3948 return err; 3949 } 3950 3951 Static void 3952 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3953 { 3954 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3955 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3956 3957 KASSERT(ex->ex_type == EX_BULK); 3958 3959 ehci_free_sqtds(sc, ex); 3960 if (ex->ex_nsqtd) 3961 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3962 } 3963 3964 Static usbd_status 3965 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3966 { 3967 3968 /* Pipe isn't running, start first */ 3969 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3970 } 3971 3972 Static usbd_status 3973 ehci_device_bulk_start(struct usbd_xfer *xfer) 3974 { 3975 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3976 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3977 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3978 ehci_soft_qh_t *sqh; 3979 ehci_soft_qtd_t *end; 3980 int len, isread, endpt; 3981 3982 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3983 3984 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3985 xfer->ux_flags, 0); 3986 3987 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3988 3989 if (sc->sc_dying) 3990 return USBD_IOERROR; 3991 3992 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3993 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3994 3995 len = xfer->ux_length; 3996 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3997 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3998 sqh = epipe->sqh; 3999 4000 KASSERT(exfer->ex_isdone); 4001 #ifdef DIAGNOSTIC 4002 exfer->ex_isdone = false; 4003 #endif 4004 4005 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4006 4007 exfer->ex_sqtdend = end; 4008 end->qtd->qtd_status |= htole32(EHCI_QTD_IOC); 4009 usb_syncmem(&end->dma, end->offs, sizeof(*end->qtd), 4010 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4011 4012 #ifdef EHCI_DEBUG 4013 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4014 ehci_dump_sqh(sqh); 4015 ehci_dump_sqtds(exfer->ex_sqtdstart); 4016 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4017 #endif 4018 4019 if (xfer->ux_length) 4020 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4021 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4022 4023 /* also does usb_syncmem(sqh) */ 4024 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4025 ehci_add_intr_list(sc, exfer); 4026 xfer->ux_status = USBD_IN_PROGRESS; 4027 usbd_xfer_schedule_timeout(xfer); 4028 4029 #if 0 4030 #ifdef EHCI_DEBUG 4031 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4032 // delay(10000); 4033 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4034 ehci_dump_regs(sc); 4035 #if 0 4036 printf("async_head:\n"); 4037 ehci_dump_sqh(sc->sc_async_head); 4038 #endif 4039 DPRINTF("sqh:", 0, 0, 0, 0); 4040 ehci_dump_sqh(sqh); 4041 ehci_dump_sqtds(exfer->ex_sqtdstart); 4042 #endif 4043 #endif 4044 4045 return USBD_IN_PROGRESS; 4046 } 4047 4048 Static void 4049 ehci_device_bulk_abort(struct usbd_xfer *xfer) 4050 { 4051 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4052 4053 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 4054 usbd_xfer_abort(xfer); 4055 } 4056 4057 /* 4058 * Close a device bulk pipe. 4059 */ 4060 Static void 4061 ehci_device_bulk_close(struct usbd_pipe *pipe) 4062 { 4063 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4064 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4065 4066 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4067 4068 KASSERT(mutex_owned(&sc->sc_lock)); 4069 4070 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 4071 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4072 ehci_close_pipe(pipe, sc->sc_async_head); 4073 } 4074 4075 Static void 4076 ehci_device_bulk_done(struct usbd_xfer *xfer) 4077 { 4078 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4079 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4080 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4081 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4082 4083 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4084 4085 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4086 4087 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4088 4089 if (xfer->ux_length) 4090 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4091 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4092 4093 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 4094 } 4095 4096 /************************/ 4097 4098 Static usbd_status 4099 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4100 { 4101 struct ehci_soft_islot *isp; 4102 int islot, lev; 4103 4104 /* Find a poll rate that is large enough. */ 4105 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4106 if (EHCI_ILEV_IVAL(lev) <= ival) 4107 break; 4108 4109 /* Pick an interrupt slot at the right level. */ 4110 /* XXX could do better than picking at random */ 4111 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4112 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4113 4114 sqh->islot = islot; 4115 isp = &sc->sc_islots[islot]; 4116 mutex_enter(&sc->sc_lock); 4117 ehci_add_qh(sc, sqh, isp->sqh); 4118 mutex_exit(&sc->sc_lock); 4119 4120 return USBD_NORMAL_COMPLETION; 4121 } 4122 4123 Static int 4124 ehci_device_intr_init(struct usbd_xfer *xfer) 4125 { 4126 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4127 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4128 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 4129 int endpt = ed->bEndpointAddress; 4130 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4131 int len = xfer->ux_bufsize; 4132 int err; 4133 4134 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4135 4136 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4137 xfer->ux_flags, 0); 4138 4139 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4140 KASSERT(len != 0); 4141 4142 exfer->ex_type = EX_INTR; 4143 exfer->ex_nsqtd = 0; 4144 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4145 &exfer->ex_sqtdstart); 4146 4147 return err; 4148 } 4149 4150 Static void 4151 ehci_device_intr_fini(struct usbd_xfer *xfer) 4152 { 4153 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4154 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4155 4156 KASSERT(ex->ex_type == EX_INTR); 4157 4158 ehci_free_sqtds(sc, ex); 4159 if (ex->ex_nsqtd) 4160 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4161 } 4162 4163 Static usbd_status 4164 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4165 { 4166 4167 /* Pipe isn't running, so start it first. */ 4168 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4169 } 4170 4171 Static usbd_status 4172 ehci_device_intr_start(struct usbd_xfer *xfer) 4173 { 4174 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4175 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4176 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4177 ehci_soft_qtd_t *end; 4178 ehci_soft_qh_t *sqh; 4179 int len, isread, endpt; 4180 4181 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4182 4183 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 4184 xfer->ux_flags, 0); 4185 4186 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4187 4188 if (sc->sc_dying) 4189 return USBD_IOERROR; 4190 4191 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4192 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4193 4194 len = xfer->ux_length; 4195 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4196 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4197 sqh = epipe->sqh; 4198 4199 KASSERT(exfer->ex_isdone); 4200 #ifdef DIAGNOSTIC 4201 exfer->ex_isdone = false; 4202 #endif 4203 4204 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4205 4206 end->qtd->qtd_status |= htole32(EHCI_QTD_IOC); 4207 usb_syncmem(&end->dma, end->offs, sizeof(*end->qtd), 4208 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4209 exfer->ex_sqtdend = end; 4210 4211 #ifdef EHCI_DEBUG 4212 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4213 ehci_dump_sqh(sqh); 4214 ehci_dump_sqtds(exfer->ex_sqtdstart); 4215 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4216 #endif 4217 4218 if (xfer->ux_length) 4219 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4220 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4221 4222 /* also does usb_syncmem(sqh) */ 4223 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4224 ehci_add_intr_list(sc, exfer); 4225 xfer->ux_status = USBD_IN_PROGRESS; 4226 usbd_xfer_schedule_timeout(xfer); 4227 4228 #if 0 4229 #ifdef EHCI_DEBUG 4230 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4231 // delay(10000); 4232 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4233 ehci_dump_regs(sc); 4234 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4235 ehci_dump_sqh(sqh); 4236 ehci_dump_sqtds(exfer->ex_sqtdstart); 4237 #endif 4238 #endif 4239 4240 return USBD_IN_PROGRESS; 4241 } 4242 4243 Static void 4244 ehci_device_intr_abort(struct usbd_xfer *xfer) 4245 { 4246 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4247 4248 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 4249 4250 /* 4251 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4252 * async doorbell. That's dependent on the async list, whereas 4253 * intr xfers are periodic, should not use this? 4254 */ 4255 usbd_xfer_abort(xfer); 4256 } 4257 4258 Static void 4259 ehci_device_intr_close(struct usbd_pipe *pipe) 4260 { 4261 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4262 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4263 struct ehci_soft_islot *isp; 4264 4265 KASSERT(mutex_owned(&sc->sc_lock)); 4266 4267 isp = &sc->sc_islots[epipe->sqh->islot]; 4268 ehci_close_pipe(pipe, isp->sqh); 4269 } 4270 4271 Static void 4272 ehci_device_intr_done(struct usbd_xfer *xfer) 4273 { 4274 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4275 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4276 4277 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4278 4279 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0); 4280 4281 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4282 4283 if (xfer->ux_length) { 4284 int isread, endpt; 4285 4286 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4287 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4288 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4289 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4290 } 4291 } 4292 4293 /************************/ 4294 Static int 4295 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4296 { 4297 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4298 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4299 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4300 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4301 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4302 int i, k, frames; 4303 u_int huba, dir; 4304 int err; 4305 4306 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4307 4308 start = NULL; 4309 sitd = NULL; 4310 4311 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4312 xfer->ux_flags, 0); 4313 4314 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4315 KASSERT(xfer->ux_nframes != 0); 4316 KASSERT(exfer->ex_isdone); 4317 4318 exfer->ex_type = EX_FS_ISOC; 4319 /* 4320 * Step 1: Allocate and initialize sitds. 4321 */ 4322 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4323 if (i > 16 || i == 0) { 4324 /* Spec page 271 says intervals > 16 are invalid */ 4325 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4326 return EINVAL; 4327 } 4328 4329 frames = xfer->ux_nframes; 4330 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4331 sitd = ehci_alloc_sitd(sc); 4332 if (sitd == NULL) { 4333 err = ENOMEM; 4334 goto fail; 4335 } 4336 4337 if (prev) 4338 prev->xfer_next = sitd; 4339 else 4340 start = sitd; 4341 4342 huba = dev->ud_myhsport->up_parent->ud_addr; 4343 4344 #if 0 4345 if (sc->sc_flags & EHCIF_FREESCALE) { 4346 // Set hub address to 0 if embedded TT is used. 4347 if (huba == sc->sc_addr) 4348 huba = 0; 4349 } 4350 #endif 4351 4352 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4353 dir = UE_GET_DIR(k) ? 1 : 0; 4354 sitd->sitd->sitd_endp = 4355 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4356 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4357 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4358 EHCI_SITD_SET_HUBA(huba) | 4359 EHCI_SITD_SET_DIR(dir)); 4360 4361 sitd->sitd->sitd_back = htole32(EHCI_LINK_TERMINATE); 4362 } /* End of frame */ 4363 4364 sitd->sitd->sitd_trans |= htole32(EHCI_SITD_IOC); 4365 4366 stop = sitd; 4367 stop->xfer_next = NULL; 4368 exfer->ex_sitdstart = start; 4369 exfer->ex_sitdend = stop; 4370 4371 return 0; 4372 4373 fail: 4374 mutex_enter(&sc->sc_lock); 4375 ehci_soft_sitd_t *next; 4376 for (sitd = start; sitd; sitd = next) { 4377 next = sitd->xfer_next; 4378 ehci_free_sitd_locked(sc, sitd); 4379 } 4380 mutex_exit(&sc->sc_lock); 4381 4382 return err; 4383 } 4384 4385 Static void 4386 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4387 { 4388 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4389 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4390 4391 KASSERT(ex->ex_type == EX_FS_ISOC); 4392 4393 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4394 } 4395 4396 Static usbd_status 4397 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4398 { 4399 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4400 const bool isread = usbd_xfer_isread(xfer); 4401 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4402 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4403 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4404 ehci_soft_sitd_t *sitd; 4405 usb_dma_t *dma_buf; 4406 int i, j, k, frames; 4407 int offs; 4408 int frindex; 4409 u_int dir; 4410 4411 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4412 4413 sitd = NULL; 4414 4415 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length, 4416 xfer->ux_flags, 0); 4417 4418 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4419 4420 if (sc->sc_dying) 4421 return USBD_IOERROR; 4422 4423 /* 4424 * To avoid complication, don't allow a request right now that'll span 4425 * the entire frame table. To within 4 frames, to allow some leeway 4426 * on either side of where the hc currently is. 4427 */ 4428 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4429 xfer->ux_nframes >= sc->sc_flsize - 4) { 4430 printf("ehci: isoc descriptor requested that spans the entire" 4431 " frametable, too many frames\n"); 4432 return USBD_INVAL; 4433 } 4434 4435 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4436 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4437 KASSERT(exfer->ex_isdone); 4438 #ifdef DIAGNOSTIC 4439 exfer->ex_isdone = false; 4440 #endif 4441 4442 /* 4443 * Step 1: Initialize sitds. 4444 */ 4445 4446 frames = xfer->ux_nframes; 4447 dma_buf = &xfer->ux_dmabuf; 4448 offs = 0; 4449 4450 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4451 i++, sitd = sitd->xfer_next) { 4452 KASSERT(sitd != NULL); 4453 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4454 4455 sitd->sitd->sitd_trans = htole32(EHCI_SITD_ACTIVE | 4456 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4457 4458 /* Set page0 index and offset - TP and T-offset are set below */ 4459 const bus_addr_t sba = DMAADDR(dma_buf, offs); 4460 sitd->sitd->sitd_buffer[0] = htole32(BUS_ADDR_LO32(sba)); 4461 sitd->sitd->sitd_buffer_hi[0] = htole32(BUS_ADDR_HI32(sba)); 4462 4463 offs += xfer->ux_frlengths[i]; 4464 4465 const bus_addr_t eba = DMAADDR(dma_buf, offs - 1); 4466 sitd->sitd->sitd_buffer[1] = 4467 htole32(EHCI_SITD_SET_BPTR(BUS_ADDR_LO32(eba))); 4468 sitd->sitd->sitd_buffer_hi[1] = htole32(BUS_ADDR_HI32(eba)); 4469 4470 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4471 4472 #if 0 4473 if (sc->sc_flags & EHCIF_FREESCALE) { 4474 // Set hub address to 0 if embedded TT is used. 4475 if (huba == sc->sc_addr) 4476 huba = 0; 4477 } 4478 #endif 4479 4480 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4481 dir = UE_GET_DIR(k) ? 1 : 0; 4482 KASSERT(sitd->sitd->sitd_endp == htole32( 4483 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4484 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4485 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4486 EHCI_SITD_SET_HUBA(huba) | 4487 EHCI_SITD_SET_DIR(dir))); 4488 KASSERT(sitd->sitd->sitd_back == htole32(EHCI_LINK_TERMINATE)); 4489 4490 uint8_t sa = 0; 4491 uint8_t sb = 0; 4492 u_int temp, tlen; 4493 4494 if (dir == 0) { /* OUT */ 4495 temp = 0; 4496 tlen = xfer->ux_frlengths[i]; 4497 if (tlen <= 188) { 4498 temp |= 1; /* T-count = 1, TP = ALL */ 4499 tlen = 1; 4500 } else { 4501 tlen += 187; 4502 tlen /= 188; 4503 temp |= tlen; /* T-count = [1..6] */ 4504 temp |= 8; /* TP = Begin */ 4505 } 4506 sitd->sitd->sitd_buffer[1] |= htole32(temp); 4507 4508 tlen += sa; 4509 4510 if (tlen >= 8) { 4511 sb = 0; 4512 } else { 4513 sb = (1 << tlen); 4514 } 4515 4516 sa = (1 << sa); 4517 sa = (sb - sa) & 0x3F; 4518 sb = 0; 4519 } else { 4520 sb = (-(4 << sa)) & 0xFE; 4521 sa = (1 << sa) & 0x3F; 4522 sa = 0x01; 4523 sb = 0xfc; 4524 } 4525 4526 sitd->sitd->sitd_sched = htole32( 4527 EHCI_SITD_SET_SMASK(sa) | 4528 EHCI_SITD_SET_CMASK(sb) 4529 ); 4530 4531 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4532 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4533 } /* End of frame */ 4534 4535 sitd = exfer->ex_sitdend; 4536 sitd->sitd->sitd_trans |= htole32(EHCI_SITD_IOC); 4537 4538 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4539 sizeof(sitd->sitd->sitd_trans), 4540 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4541 4542 if (xfer->ux_length) 4543 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4544 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4545 4546 /* 4547 * Part 2: Transfer descriptors have now been set up, now they must 4548 * be scheduled into the periodic frame list. Erk. Not wanting to 4549 * complicate matters, transfer is denied if the transfer spans 4550 * more than the periodic frame list. 4551 */ 4552 4553 /* Start inserting frames */ 4554 if (epipe->isoc.cur_xfers > 0) { 4555 frindex = epipe->isoc.next_frame; 4556 } else { 4557 frindex = EOREAD4(sc, EHCI_FRINDEX); 4558 frindex = frindex >> 3; /* Erase microframe index */ 4559 frindex += 2; 4560 } 4561 4562 if (frindex >= sc->sc_flsize) 4563 frindex &= (sc->sc_flsize - 1); 4564 4565 /* What's the frame interval? */ 4566 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4567 4568 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4569 j++, sitd = sitd->xfer_next) { 4570 KASSERT(sitd); 4571 4572 usb_syncmem(&sc->sc_fldma, 4573 sizeof(ehci_link_t) * frindex, 4574 sizeof(ehci_link_t), 4575 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4576 4577 sitd->sitd->sitd_next = sc->sc_flist[frindex]; 4578 if (sitd->sitd->sitd_next == 0) 4579 /* 4580 * FIXME: frindex table gets initialized to NULL 4581 * or EHCI_NULL? 4582 */ 4583 sitd->sitd->sitd_next = EHCI_NULL; 4584 4585 usb_syncmem(&sitd->dma, 4586 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4587 sizeof(ehci_sitd_t), 4588 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4589 4590 sc->sc_flist[frindex] = 4591 htole32(EHCI_LINK_SITD | sitd->physaddr); 4592 4593 usb_syncmem(&sc->sc_fldma, 4594 sizeof(ehci_link_t) * frindex, 4595 sizeof(ehci_link_t), 4596 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4597 4598 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4599 sc->sc_softsitds[frindex] = sitd; 4600 if (sitd->frame_list.next != NULL) 4601 sitd->frame_list.next->frame_list.prev = sitd; 4602 sitd->slot = frindex; 4603 sitd->frame_list.prev = NULL; 4604 4605 frindex += i; 4606 if (frindex >= sc->sc_flsize) 4607 frindex -= sc->sc_flsize; 4608 } 4609 4610 epipe->isoc.cur_xfers++; 4611 epipe->isoc.next_frame = frindex; 4612 4613 ehci_add_intr_list(sc, exfer); 4614 xfer->ux_status = USBD_IN_PROGRESS; 4615 4616 return USBD_IN_PROGRESS; 4617 } 4618 4619 Static void 4620 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4621 { 4622 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4623 4624 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 4625 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4626 } 4627 4628 Static void 4629 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4630 { 4631 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4632 4633 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4634 } 4635 4636 Static void 4637 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4638 { 4639 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4640 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4641 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4642 const bool isread = usbd_xfer_isread(xfer); 4643 4644 KASSERT(mutex_owned(&sc->sc_lock)); 4645 4646 epipe->isoc.cur_xfers--; 4647 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4648 4649 if (xfer->ux_length) 4650 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4651 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4652 } 4653 4654 /* -------------------------------------------------------------------------- */ 4655 4656 Static int 4657 ehci_device_isoc_init(struct usbd_xfer *xfer) 4658 { 4659 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4660 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4661 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4662 ehci_soft_itd_t *itd, *prev, *start, *stop; 4663 int i, j, k; 4664 int frames, ufrperframe; 4665 int err; 4666 4667 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4668 4669 start = NULL; 4670 prev = NULL; 4671 itd = NULL; 4672 4673 KASSERT(xfer->ux_nframes != 0); 4674 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4675 KASSERT(exfer->ex_isdone); 4676 4677 exfer->ex_type = EX_ISOC; 4678 4679 /* 4680 * Step 1: Allocate and initialize itds, how many do we need? 4681 * One per transfer if interval >= 8 microframes, less if we use 4682 * multiple microframes per frame. 4683 */ 4684 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4685 if (i > 16 || i == 0) { 4686 /* Spec page 271 says intervals > 16 are invalid */ 4687 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4688 return EINVAL; 4689 } 4690 4691 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4692 frames = howmany(xfer->ux_nframes, ufrperframe); 4693 4694 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4695 itd = ehci_alloc_itd(sc); 4696 if (itd == NULL) { 4697 err = ENOMEM; 4698 goto fail; 4699 } 4700 4701 if (prev != NULL) { 4702 /* Maybe not as it's updated by the scheduling? */ 4703 prev->itd->itd_next = 4704 htole32(itd->physaddr | EHCI_LINK_ITD); 4705 4706 prev->xfer_next = itd; 4707 } else { 4708 start = itd; 4709 } 4710 4711 /* 4712 * Other special values 4713 */ 4714 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4715 itd->itd->itd_bufr[0] = htole32( 4716 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4717 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4718 4719 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4720 ? 1 : 0; 4721 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4722 itd->itd->itd_bufr[1] |= htole32( 4723 EHCI_ITD_SET_DIR(k) | 4724 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4725 4726 /* FIXME: handle invalid trans - should be done in openpipe */ 4727 itd->itd->itd_bufr[2] |= 4728 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4729 } /* End of frame */ 4730 4731 stop = itd; 4732 stop->xfer_next = NULL; 4733 4734 exfer->ex_itdstart = start; 4735 exfer->ex_itdend = stop; 4736 4737 return 0; 4738 fail: 4739 mutex_enter(&sc->sc_lock); 4740 ehci_soft_itd_t *next; 4741 for (itd = start; itd; itd = next) { 4742 next = itd->xfer_next; 4743 ehci_free_itd_locked(sc, itd); 4744 } 4745 mutex_exit(&sc->sc_lock); 4746 4747 return err; 4748 4749 } 4750 4751 Static void 4752 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4753 { 4754 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4755 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4756 4757 KASSERT(ex->ex_type == EX_ISOC); 4758 4759 ehci_free_itd_chain(sc, ex->ex_itdstart); 4760 } 4761 4762 Static usbd_status 4763 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4764 { 4765 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4766 const bool isread = usbd_xfer_isread(xfer); 4767 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4768 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4769 ehci_soft_itd_t *itd, *prev; 4770 usb_dma_t *dma_buf; 4771 int i, j; 4772 int frames, uframes, ufrperframe; 4773 int trans_count, offs; 4774 int frindex; 4775 4776 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4777 4778 prev = NULL; 4779 itd = NULL; 4780 trans_count = 0; 4781 4782 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0); 4783 4784 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4785 4786 if (sc->sc_dying) 4787 return USBD_IOERROR; 4788 4789 /* 4790 * To avoid complication, don't allow a request right now that'll span 4791 * the entire frame table. To within 4 frames, to allow some leeway 4792 * on either side of where the hc currently is. 4793 */ 4794 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4795 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4796 DPRINTF( 4797 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4798 printf("ehci: isoc descriptor requested that spans the entire" 4799 " frametable, too many frames\n"); 4800 return USBD_INVAL; 4801 } 4802 4803 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4804 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4805 KASSERT(exfer->ex_isdone); 4806 #ifdef DIAGNOSTIC 4807 exfer->ex_isdone = false; 4808 #endif 4809 4810 /* 4811 * Step 1: Re-Initialize itds 4812 */ 4813 4814 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4815 if (i > 16 || i == 0) { 4816 /* Spec page 271 says intervals > 16 are invalid */ 4817 DPRINTF("bInterval %jd invalid", i, 0, 0, 0); 4818 return USBD_INVAL; 4819 } 4820 4821 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4822 frames = howmany(xfer->ux_nframes, ufrperframe); 4823 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4824 4825 if (frames == 0) { 4826 DPRINTF("frames == 0", 0, 0, 0, 0); 4827 return USBD_INVAL; 4828 } 4829 4830 dma_buf = &xfer->ux_dmabuf; 4831 offs = 0; 4832 4833 itd = exfer->ex_itdstart; 4834 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4835 int froffs = offs; 4836 4837 if (prev != NULL) { 4838 prev->itd->itd_next = 4839 htole32(itd->physaddr | EHCI_LINK_ITD); 4840 usb_syncmem(&prev->dma, 4841 prev->offs + offsetof(ehci_itd_t, itd_next), 4842 sizeof(prev->itd->itd_next), BUS_DMASYNC_POSTWRITE); 4843 prev->xfer_next = itd; 4844 } 4845 4846 /* 4847 * Step 1.5, initialize uframes 4848 */ 4849 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4850 /* Calculate which page in the list this starts in */ 4851 int addr = DMAADDR(dma_buf, froffs); 4852 addr = EHCI_PAGE_OFFSET(addr); 4853 addr += (offs - froffs); 4854 addr = EHCI_PAGE(addr); 4855 addr /= EHCI_PAGE_SIZE; 4856 4857 /* 4858 * This gets the initial offset into the first page, 4859 * looks how far further along the current uframe 4860 * offset is. Works out how many pages that is. 4861 */ 4862 4863 itd->itd->itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4864 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4865 EHCI_ITD_SET_PG(addr) | 4866 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4867 4868 offs += xfer->ux_frlengths[trans_count]; 4869 trans_count++; 4870 4871 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4872 itd->itd->itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4873 break; 4874 } 4875 } 4876 4877 /* 4878 * Step 1.75, set buffer pointers. To simplify matters, all 4879 * pointers are filled out for the next 7 hardware pages in 4880 * the dma block, so no need to worry what pages to cover 4881 * and what to not. 4882 */ 4883 4884 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4885 /* 4886 * Don't try to lookup a page that's past the end 4887 * of buffer 4888 */ 4889 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4890 if (page_offs >= dma_buf->udma_block->size) 4891 break; 4892 4893 uint64_t page = DMAADDR(dma_buf, page_offs); 4894 page = EHCI_PAGE(page); 4895 itd->itd->itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4896 itd->itd->itd_bufr_hi[j] = htole32(page >> 32); 4897 } 4898 /* 4899 * Other special values 4900 */ 4901 4902 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4903 itd->itd->itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4904 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4905 4906 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4907 ? 1 : 0; 4908 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4909 itd->itd->itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4910 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4911 4912 /* FIXME: handle invalid trans */ 4913 itd->itd->itd_bufr[2] |= 4914 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4915 4916 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4917 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4918 4919 prev = itd; 4920 } /* End of frame */ 4921 4922 if (xfer->ux_length) 4923 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length, 4924 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4925 4926 /* 4927 * Part 2: Transfer descriptors have now been set up, now they must 4928 * be scheduled into the periodic frame list. Erk. Not wanting to 4929 * complicate matters, transfer is denied if the transfer spans 4930 * more than the periodic frame list. 4931 */ 4932 4933 /* Start inserting frames */ 4934 if (epipe->isoc.cur_xfers > 0) { 4935 frindex = epipe->isoc.next_frame; 4936 } else { 4937 frindex = EOREAD4(sc, EHCI_FRINDEX); 4938 frindex = frindex >> 3; /* Erase microframe index */ 4939 frindex += 2; 4940 } 4941 4942 if (frindex >= sc->sc_flsize) 4943 frindex &= (sc->sc_flsize - 1); 4944 4945 /* What's the frame interval? */ 4946 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4947 if (i / USB_UFRAMES_PER_FRAME == 0) 4948 i = 1; 4949 else 4950 i /= USB_UFRAMES_PER_FRAME; 4951 4952 itd = exfer->ex_itdstart; 4953 for (j = 0; j < frames; j++) { 4954 KASSERTMSG(itd != NULL, "frame %d\n", j); 4955 4956 usb_syncmem(&sc->sc_fldma, 4957 sizeof(ehci_link_t) * frindex, 4958 sizeof(ehci_link_t), 4959 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4960 4961 itd->itd->itd_next = sc->sc_flist[frindex]; 4962 if (itd->itd->itd_next == 0) 4963 /* 4964 * FIXME: frindex table gets initialized to NULL 4965 * or EHCI_NULL? 4966 */ 4967 itd->itd->itd_next = EHCI_NULL; 4968 4969 usb_syncmem(&itd->dma, 4970 itd->offs + offsetof(ehci_itd_t, itd_next), 4971 sizeof(itd->itd->itd_next), 4972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4973 4974 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4975 4976 usb_syncmem(&sc->sc_fldma, 4977 sizeof(ehci_link_t) * frindex, 4978 sizeof(ehci_link_t), 4979 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4980 4981 itd->frame_list.next = sc->sc_softitds[frindex]; 4982 sc->sc_softitds[frindex] = itd; 4983 if (itd->frame_list.next != NULL) 4984 itd->frame_list.next->frame_list.prev = itd; 4985 itd->slot = frindex; 4986 itd->frame_list.prev = NULL; 4987 4988 frindex += i; 4989 if (frindex >= sc->sc_flsize) 4990 frindex -= sc->sc_flsize; 4991 4992 itd = itd->xfer_next; 4993 } 4994 4995 epipe->isoc.cur_xfers++; 4996 epipe->isoc.next_frame = frindex; 4997 4998 ehci_add_intr_list(sc, exfer); 4999 xfer->ux_status = USBD_IN_PROGRESS; 5000 5001 return USBD_IN_PROGRESS; 5002 } 5003 5004 Static void 5005 ehci_device_isoc_abort(struct usbd_xfer *xfer) 5006 { 5007 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 5008 5009 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0); 5010 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 5011 } 5012 5013 Static void 5014 ehci_device_isoc_close(struct usbd_pipe *pipe) 5015 { 5016 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 5017 5018 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 5019 } 5020 5021 Static void 5022 ehci_device_isoc_done(struct usbd_xfer *xfer) 5023 { 5024 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 5025 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 5026 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 5027 const bool isread = usbd_xfer_isread(xfer); 5028 5029 KASSERT(mutex_owned(&sc->sc_lock)); 5030 5031 epipe->isoc.cur_xfers--; 5032 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 5033 5034 if (xfer->ux_length) 5035 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 5036 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 5037 } 5038
Indexes created Tue Sep 23 07:09:52 GMT 2025