ehci.c revision 1.91.2.10
1 /* $NetBSD: ehci.c,v 1.91.2.10 2008/09/28 16:06:39 jdc Exp $ */ 2 3 /* 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 41 * 42 * The EHCI 1.0 spec can be found at 43 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 44 * and the USB 2.0 spec at 45 * http://www.usb.org/developers/docs/usb_20.zip 46 * 47 */ 48 49 /* 50 * TODO: 51 * 1) hold off explorations by companion controllers until ehci has started. 52 * 53 * 2) The EHCI driver lacks support for interrupt isochronous transfers, so 54 * devices using them don't work. 55 * Interrupt transfers are not difficult, it's just not done. 56 * 57 * 3) The meaty part to implement is the support for USB 2.0 hubs. 58 * They are quite complicated since the need to be able to do 59 * "transaction translation", i.e., converting to/from USB 2 and USB 1. 60 * So the hub driver needs to handle and schedule these things, to 61 * assign place in frame where different devices get to go. See chapter 62 * on hubs in USB 2.0 for details. 63 * 64 * 4) command failures are not recovered correctly 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.91.2.10 2008/09/28 16:06:39 jdc Exp $"); 69 70 #include "ohci.h" 71 #include "uhci.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/select.h> 79 #include <sys/proc.h> 80 #include <sys/queue.h> 81 82 #include <machine/bus.h> 83 #include <machine/endian.h> 84 85 #include <dev/usb/usb.h> 86 #include <dev/usb/usbdi.h> 87 #include <dev/usb/usbdivar.h> 88 #include <dev/usb/usb_mem.h> 89 #include <dev/usb/usb_quirks.h> 90 91 #include <dev/usb/ehcireg.h> 92 #include <dev/usb/ehcivar.h> 93 94 #ifdef EHCI_DEBUG 95 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 96 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 97 int ehcidebug = 0; 98 #ifndef __NetBSD__ 99 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 100 #endif 101 #else 102 #define DPRINTF(x) 103 #define DPRINTFN(n,x) 104 #endif 105 106 struct ehci_pipe { 107 struct usbd_pipe pipe; 108 int nexttoggle; 109 110 ehci_soft_qh_t *sqh; 111 union { 112 ehci_soft_qtd_t *qtd; 113 /* ehci_soft_itd_t *itd; */ 114 } tail; 115 union { 116 /* Control pipe */ 117 struct { 118 usb_dma_t reqdma; 119 u_int length; 120 /*ehci_soft_qtd_t *setup, *data, *stat;*/ 121 } ctl; 122 /* Interrupt pipe */ 123 struct { 124 u_int length; 125 } intr; 126 /* Bulk pipe */ 127 struct { 128 u_int length; 129 } bulk; 130 /* Iso pipe */ 131 /* XXX */ 132 } u; 133 }; 134 135 Static void ehci_shutdown(void *); 136 Static void ehci_power(int, void *); 137 138 Static usbd_status ehci_open(usbd_pipe_handle); 139 Static void ehci_poll(struct usbd_bus *); 140 Static void ehci_softintr(void *); 141 Static int ehci_intr1(ehci_softc_t *); 142 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 143 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 144 Static void ehci_idone(struct ehci_xfer *); 145 Static void ehci_timeout(void *); 146 Static void ehci_timeout_task(void *); 147 Static void ehci_intrlist_timeout(void *); 148 149 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 150 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 151 152 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 153 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 154 155 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 156 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 157 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 158 Static void ehci_root_ctrl_close(usbd_pipe_handle); 159 Static void ehci_root_ctrl_done(usbd_xfer_handle); 160 161 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 162 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 163 Static void ehci_root_intr_abort(usbd_xfer_handle); 164 Static void ehci_root_intr_close(usbd_pipe_handle); 165 Static void ehci_root_intr_done(usbd_xfer_handle); 166 167 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 168 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 169 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 170 Static void ehci_device_ctrl_close(usbd_pipe_handle); 171 Static void ehci_device_ctrl_done(usbd_xfer_handle); 172 173 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 174 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 175 Static void ehci_device_bulk_abort(usbd_xfer_handle); 176 Static void ehci_device_bulk_close(usbd_pipe_handle); 177 Static void ehci_device_bulk_done(usbd_xfer_handle); 178 179 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 181 Static void ehci_device_intr_abort(usbd_xfer_handle); 182 Static void ehci_device_intr_close(usbd_pipe_handle); 183 Static void ehci_device_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 187 Static void ehci_device_isoc_abort(usbd_xfer_handle); 188 Static void ehci_device_isoc_close(usbd_pipe_handle); 189 Static void ehci_device_isoc_done(usbd_xfer_handle); 190 191 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 192 Static void ehci_noop(usbd_pipe_handle pipe); 193 194 Static int ehci_str(usb_string_descriptor_t *, int, char *); 195 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 196 Static void ehci_pcd_able(ehci_softc_t *, int); 197 Static void ehci_pcd_enable(void *); 198 Static void ehci_disown(ehci_softc_t *, int, int); 199 200 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 201 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 202 203 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 204 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 205 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 206 ehci_softc_t *, int, int, usbd_xfer_handle, 207 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 208 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 209 ehci_soft_qtd_t *); 210 211 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 212 213 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 214 int ival); 215 216 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 217 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 218 ehci_soft_qh_t *); 219 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 220 Static void ehci_sync_hc(ehci_softc_t *); 221 222 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 223 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 224 225 #ifdef EHCI_DEBUG 226 Static void ehci_dump_regs(ehci_softc_t *); 227 Static void ehci_dump(void); 228 Static ehci_softc_t *theehci; 229 Static void ehci_dump_link(ehci_link_t, int); 230 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 231 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 232 Static void ehci_dump_qtd(ehci_qtd_t *); 233 Static void ehci_dump_sqh(ehci_soft_qh_t *); 234 #ifdef DIAGNOSTIC 235 Static void ehci_dump_exfer(struct ehci_xfer *); 236 #endif 237 #endif 238 239 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 240 241 #define EHCI_INTR_ENDPT 1 242 243 #define ehci_add_intr_list(sc, ex) \ 244 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 245 #define ehci_del_intr_list(ex) \ 246 do { \ 247 LIST_REMOVE((ex), inext); \ 248 (ex)->inext.le_prev = NULL; \ 249 } while (0) 250 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 251 252 Static struct usbd_bus_methods ehci_bus_methods = { 253 ehci_open, 254 ehci_softintr, 255 ehci_poll, 256 ehci_allocm, 257 ehci_freem, 258 ehci_allocx, 259 ehci_freex, 260 }; 261 262 Static struct usbd_pipe_methods ehci_root_ctrl_methods = { 263 ehci_root_ctrl_transfer, 264 ehci_root_ctrl_start, 265 ehci_root_ctrl_abort, 266 ehci_root_ctrl_close, 267 ehci_noop, 268 ehci_root_ctrl_done, 269 }; 270 271 Static struct usbd_pipe_methods ehci_root_intr_methods = { 272 ehci_root_intr_transfer, 273 ehci_root_intr_start, 274 ehci_root_intr_abort, 275 ehci_root_intr_close, 276 ehci_noop, 277 ehci_root_intr_done, 278 }; 279 280 Static struct usbd_pipe_methods ehci_device_ctrl_methods = { 281 ehci_device_ctrl_transfer, 282 ehci_device_ctrl_start, 283 ehci_device_ctrl_abort, 284 ehci_device_ctrl_close, 285 ehci_noop, 286 ehci_device_ctrl_done, 287 }; 288 289 Static struct usbd_pipe_methods ehci_device_intr_methods = { 290 ehci_device_intr_transfer, 291 ehci_device_intr_start, 292 ehci_device_intr_abort, 293 ehci_device_intr_close, 294 ehci_device_clear_toggle, 295 ehci_device_intr_done, 296 }; 297 298 Static struct usbd_pipe_methods ehci_device_bulk_methods = { 299 ehci_device_bulk_transfer, 300 ehci_device_bulk_start, 301 ehci_device_bulk_abort, 302 ehci_device_bulk_close, 303 ehci_device_clear_toggle, 304 ehci_device_bulk_done, 305 }; 306 307 Static struct usbd_pipe_methods ehci_device_isoc_methods = { 308 ehci_device_isoc_transfer, 309 ehci_device_isoc_start, 310 ehci_device_isoc_abort, 311 ehci_device_isoc_close, 312 ehci_noop, 313 ehci_device_isoc_done, 314 }; 315 316 static uint8_t revbits[EHCI_MAX_POLLRATE] = { 317 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 318 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 319 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 320 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 321 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 322 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 323 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 324 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 325 }; 326 327 usbd_status 328 ehci_init(ehci_softc_t *sc) 329 { 330 u_int32_t version, sparams, cparams, hcr; 331 u_int i; 332 usbd_status err; 333 ehci_soft_qh_t *sqh; 334 u_int ncomp; 335 336 DPRINTF(("ehci_init: start\n")); 337 #ifdef EHCI_DEBUG 338 theehci = sc; 339 #endif 340 341 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 342 343 version = EREAD2(sc, EHCI_HCIVERSION); 344 aprint_normal("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 345 version >> 8, version & 0xff); 346 347 sparams = EREAD4(sc, EHCI_HCSPARAMS); 348 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 349 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 350 ncomp = EHCI_HCS_N_CC(sparams); 351 if (ncomp != sc->sc_ncomp) { 352 aprint_error("%s: wrong number of companions (%d != %d)\n", 353 USBDEVNAME(sc->sc_bus.bdev), 354 ncomp, sc->sc_ncomp); 355 #if NOHCI == 0 || NUHCI == 0 356 aprint_error("%s: ohci or uhci probably not configured\n", 357 USBDEVNAME(sc->sc_bus.bdev)); 358 #endif 359 if (ncomp < sc->sc_ncomp) 360 sc->sc_ncomp = ncomp; 361 } 362 if (sc->sc_ncomp > 0) { 363 aprint_normal("%s: companion controller%s, %d port%s each:", 364 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 365 EHCI_HCS_N_PCC(sparams), 366 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 367 for (i = 0; i < sc->sc_ncomp; i++) 368 aprint_normal(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 369 aprint_normal("\n"); 370 } 371 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 372 cparams = EREAD4(sc, EHCI_HCCPARAMS); 373 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 374 375 if (EHCI_HCC_64BIT(cparams)) { 376 /* MUST clear segment register if 64 bit capable. */ 377 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 378 } 379 380 sc->sc_bus.usbrev = USBREV_2_0; 381 382 usb_setup_reserve(sc, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 383 USB_MEM_RESERVE); 384 385 /* Reset the controller */ 386 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 387 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 388 usb_delay_ms(&sc->sc_bus, 1); 389 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 390 for (i = 0; i < 100; i++) { 391 usb_delay_ms(&sc->sc_bus, 1); 392 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 393 if (!hcr) 394 break; 395 } 396 if (hcr) { 397 aprint_error("%s: reset timeout\n", 398 USBDEVNAME(sc->sc_bus.bdev)); 399 return (USBD_IOERROR); 400 } 401 402 /* XXX need proper intr scheduling */ 403 sc->sc_rand = 96; 404 405 /* frame list size at default, read back what we got and use that */ 406 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 407 case 0: sc->sc_flsize = 1024; break; 408 case 1: sc->sc_flsize = 512; break; 409 case 2: sc->sc_flsize = 256; break; 410 case 3: return (USBD_IOERROR); 411 } 412 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 413 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 414 if (err) 415 return (err); 416 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 417 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 418 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 419 420 /* Set up the bus struct. */ 421 sc->sc_bus.methods = &ehci_bus_methods; 422 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 423 424 sc->sc_powerhook = powerhook_establish(ehci_power, sc); 425 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 426 427 sc->sc_eintrs = EHCI_NORMAL_INTRS; 428 429 /* 430 * Allocate the interrupt dummy QHs. These are arranged to give poll 431 * intervals that are powers of 2 times 1ms. 432 */ 433 for (i = 0; i < EHCI_INTRQHS; i++) { 434 sqh = ehci_alloc_sqh(sc); 435 if (sqh == NULL) { 436 err = USBD_NOMEM; 437 goto bad1; 438 } 439 sc->sc_islots[i].sqh = sqh; 440 } 441 for (i = 0; i < EHCI_INTRQHS; i++) { 442 sqh = sc->sc_islots[i].sqh; 443 if (i == 0) { 444 /* The last (1ms) QH terminates. */ 445 sqh->qh.qh_link = EHCI_NULL; 446 sqh->next = NULL; 447 } else { 448 /* Otherwise the next QH has half the poll interval */ 449 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 450 sqh->qh.qh_link = htole32(sqh->next->physaddr | 451 EHCI_LINK_QH); 452 } 453 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 454 sqh->qh.qh_curqtd = EHCI_NULL; 455 sqh->next = NULL; 456 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 457 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 458 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 459 sqh->sqtd = NULL; 460 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 461 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 462 } 463 /* Point the frame list at the last level (128ms). */ 464 for (i = 0; i < sc->sc_flsize; i++) { 465 int j; 466 467 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 468 revbits[i & (EHCI_MAX_POLLRATE-1)]; 469 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 470 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 471 i)].sqh->physaddr); 472 } 473 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 474 BUS_DMASYNC_PREWRITE); 475 476 /* Allocate dummy QH that starts the async list. */ 477 sqh = ehci_alloc_sqh(sc); 478 if (sqh == NULL) { 479 err = USBD_NOMEM; 480 goto bad1; 481 } 482 /* Fill the QH */ 483 sqh->qh.qh_endp = 484 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 485 sqh->qh.qh_link = 486 htole32(sqh->physaddr | EHCI_LINK_QH); 487 sqh->qh.qh_curqtd = EHCI_NULL; 488 sqh->next = NULL; 489 /* Fill the overlay qTD */ 490 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 491 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 492 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 493 sqh->sqtd = NULL; 494 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 495 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 496 #ifdef EHCI_DEBUG 497 if (ehcidebug) { 498 ehci_dump_sqh(sqh); 499 } 500 #endif 501 502 /* Point to async list */ 503 sc->sc_async_head = sqh; 504 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 505 506 usb_callout_init(sc->sc_tmo_pcd); 507 usb_callout_init(sc->sc_tmo_intrlist); 508 509 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 510 511 /* Enable interrupts */ 512 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 513 514 /* Turn on controller */ 515 EOWRITE4(sc, EHCI_USBCMD, 516 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 517 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 518 EHCI_CMD_ASE | 519 EHCI_CMD_PSE | 520 EHCI_CMD_RS); 521 522 /* Take over port ownership */ 523 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 524 525 for (i = 0; i < 100; i++) { 526 usb_delay_ms(&sc->sc_bus, 1); 527 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 528 if (!hcr) 529 break; 530 } 531 if (hcr) { 532 aprint_error("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 533 return (USBD_IOERROR); 534 } 535 536 return (USBD_NORMAL_COMPLETION); 537 538 #if 0 539 bad2: 540 ehci_free_sqh(sc, sc->sc_async_head); 541 #endif 542 bad1: 543 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 544 return (err); 545 } 546 547 int 548 ehci_intr(void *v) 549 { 550 ehci_softc_t *sc = v; 551 552 if (sc == NULL || sc->sc_dying) 553 return (0); 554 555 /* If we get an interrupt while polling, then just ignore it. */ 556 if (sc->sc_bus.use_polling) { 557 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 558 559 if (intrs) 560 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 561 #ifdef DIAGNOSTIC 562 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 563 #endif 564 return (0); 565 } 566 567 return (ehci_intr1(sc)); 568 } 569 570 Static int 571 ehci_intr1(ehci_softc_t *sc) 572 { 573 u_int32_t intrs, eintrs; 574 575 DPRINTFN(20,("ehci_intr1: enter\n")); 576 577 /* In case the interrupt occurs before initialization has completed. */ 578 if (sc == NULL) { 579 #ifdef DIAGNOSTIC 580 printf("ehci_intr1: sc == NULL\n"); 581 #endif 582 return (0); 583 } 584 585 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 586 if (!intrs) 587 return (0); 588 589 eintrs = intrs & sc->sc_eintrs; 590 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 591 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 592 (u_int)eintrs)); 593 if (!eintrs) 594 return (0); 595 596 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 597 sc->sc_bus.intr_context++; 598 sc->sc_bus.no_intrs++; 599 if (eintrs & EHCI_STS_IAA) { 600 DPRINTF(("ehci_intr1: door bell\n")); 601 wakeup(&sc->sc_async_head); 602 eintrs &= ~EHCI_STS_IAA; 603 } 604 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 605 DPRINTFN(5,("ehci_intr1: %s %s\n", 606 eintrs & EHCI_STS_INT ? "INT" : "", 607 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 608 usb_schedsoftintr(&sc->sc_bus); 609 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 610 } 611 if (eintrs & EHCI_STS_HSE) { 612 printf("%s: unrecoverable error, controller halted\n", 613 USBDEVNAME(sc->sc_bus.bdev)); 614 /* XXX what else */ 615 } 616 if (eintrs & EHCI_STS_PCD) { 617 ehci_pcd(sc, sc->sc_intrxfer); 618 /* 619 * Disable PCD interrupt for now, because it will be 620 * on until the port has been reset. 621 */ 622 ehci_pcd_able(sc, 0); 623 /* Do not allow RHSC interrupts > 1 per second */ 624 usb_callout(sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc); 625 eintrs &= ~EHCI_STS_PCD; 626 } 627 628 sc->sc_bus.intr_context--; 629 630 if (eintrs != 0) { 631 /* Block unprocessed interrupts. */ 632 sc->sc_eintrs &= ~eintrs; 633 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 634 printf("%s: blocking intrs 0x%x\n", 635 USBDEVNAME(sc->sc_bus.bdev), eintrs); 636 } 637 638 return (1); 639 } 640 641 void 642 ehci_pcd_able(ehci_softc_t *sc, int on) 643 { 644 DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on)); 645 if (on) 646 sc->sc_eintrs |= EHCI_STS_PCD; 647 else 648 sc->sc_eintrs &= ~EHCI_STS_PCD; 649 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 650 } 651 652 void 653 ehci_pcd_enable(void *v_sc) 654 { 655 ehci_softc_t *sc = v_sc; 656 657 ehci_pcd_able(sc, 1); 658 } 659 660 void 661 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 662 { 663 usbd_pipe_handle pipe; 664 u_char *p; 665 int i, m; 666 667 if (xfer == NULL) { 668 /* Just ignore the change. */ 669 return; 670 } 671 672 pipe = xfer->pipe; 673 674 p = KERNADDR(&xfer->dmabuf, 0); 675 m = min(sc->sc_noport, xfer->length * 8 - 1); 676 memset(p, 0, xfer->length); 677 for (i = 1; i <= m; i++) { 678 /* Pick out CHANGE bits from the status reg. */ 679 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 680 p[i/8] |= 1 << (i%8); 681 } 682 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 683 xfer->actlen = xfer->length; 684 xfer->status = USBD_NORMAL_COMPLETION; 685 686 usb_transfer_complete(xfer); 687 } 688 689 void 690 ehci_softintr(void *v) 691 { 692 ehci_softc_t *sc = v; 693 struct ehci_xfer *ex, *nextex; 694 695 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 696 sc->sc_bus.intr_context)); 697 698 sc->sc_bus.intr_context++; 699 700 /* 701 * The only explanation I can think of for why EHCI is as brain dead 702 * as UHCI interrupt-wise is that Intel was involved in both. 703 * An interrupt just tells us that something is done, we have no 704 * clue what, so we need to scan through all active transfers. :-( 705 */ 706 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 707 nextex = LIST_NEXT(ex, inext); 708 ehci_check_intr(sc, ex); 709 } 710 711 /* Schedule a callout to catch any dropped transactions. */ 712 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 713 !LIST_EMPTY(&sc->sc_intrhead)) 714 usb_callout(sc->sc_tmo_intrlist, hz, 715 ehci_intrlist_timeout, sc); 716 717 #ifdef USB_USE_SOFTINTR 718 if (sc->sc_softwake) { 719 sc->sc_softwake = 0; 720 wakeup(&sc->sc_softwake); 721 } 722 #endif /* USB_USE_SOFTINTR */ 723 724 sc->sc_bus.intr_context--; 725 } 726 727 /* Check for an interrupt. */ 728 void 729 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 730 { 731 ehci_soft_qtd_t *sqtd, *lsqtd; 732 u_int32_t status; 733 734 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 735 736 if (ex->sqtdstart == NULL) { 737 printf("ehci_check_intr: sqtdstart=NULL\n"); 738 return; 739 } 740 lsqtd = ex->sqtdend; 741 #ifdef DIAGNOSTIC 742 if (lsqtd == NULL) { 743 printf("ehci_check_intr: lsqtd==0\n"); 744 return; 745 } 746 #endif 747 /* 748 * If the last TD is still active we need to check whether there 749 * is a an error somewhere in the middle, or whether there was a 750 * short packet (SPD and not ACTIVE). 751 */ 752 usb_syncmem(&lsqtd->dma, 753 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 754 sizeof(lsqtd->qtd.qtd_status), 755 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 756 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 757 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 758 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 759 usb_syncmem(&sqtd->dma, 760 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 761 sizeof(sqtd->qtd.qtd_status), 762 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 763 status = le32toh(sqtd->qtd.qtd_status); 764 usb_syncmem(&sqtd->dma, 765 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 766 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 767 /* If there's an active QTD the xfer isn't done. */ 768 if (status & EHCI_QTD_ACTIVE) 769 break; 770 /* Any kind of error makes the xfer done. */ 771 if (status & EHCI_QTD_HALTED) 772 goto done; 773 /* We want short packets, and it is short: it's done */ 774 if (EHCI_QTD_GET_BYTES(status) != 0) 775 goto done; 776 } 777 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 778 ex, ex->sqtdstart)); 779 usb_syncmem(&lsqtd->dma, 780 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 781 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 782 return; 783 } 784 done: 785 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 786 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 787 ehci_idone(ex); 788 } 789 790 void 791 ehci_idone(struct ehci_xfer *ex) 792 { 793 usbd_xfer_handle xfer = &ex->xfer; 794 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 795 ehci_soft_qtd_t *sqtd, *lsqtd; 796 u_int32_t status = 0, nstatus = 0; 797 int actlen; 798 uint pkts_left; 799 800 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 801 #ifdef DIAGNOSTIC 802 { 803 int s = splhigh(); 804 if (ex->isdone) { 805 splx(s); 806 #ifdef EHCI_DEBUG 807 printf("ehci_idone: ex is done!\n "); 808 ehci_dump_exfer(ex); 809 #else 810 printf("ehci_idone: ex=%p is done!\n", ex); 811 #endif 812 return; 813 } 814 ex->isdone = 1; 815 splx(s); 816 } 817 #endif 818 819 if (xfer->status == USBD_CANCELLED || 820 xfer->status == USBD_TIMEOUT) { 821 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 822 return; 823 } 824 825 #ifdef EHCI_DEBUG 826 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 827 if (ehcidebug > 10) 828 ehci_dump_sqtds(ex->sqtdstart); 829 #endif 830 831 /* The transfer is done, compute actual length and status. */ 832 lsqtd = ex->sqtdend; 833 actlen = 0; 834 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) { 835 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 836 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 837 nstatus = le32toh(sqtd->qtd.qtd_status); 838 if (nstatus & EHCI_QTD_ACTIVE) 839 break; 840 841 status = nstatus; 842 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 843 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 844 } 845 846 /* 847 * If there are left over TDs we need to update the toggle. 848 * The default pipe doesn't need it since control transfers 849 * start the toggle at 0 every time. 850 */ 851 if (sqtd != lsqtd->nextqtd && 852 xfer->pipe->device->default_pipe != xfer->pipe) { 853 printf("ehci_idone: need toggle update status=%08x nstatus=%08x\n", status, nstatus); 854 #if 0 855 ehci_dump_sqh(epipe->sqh); 856 ehci_dump_sqtds(ex->sqtdstart); 857 #endif 858 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 859 } 860 861 /* 862 * For a short transfer we need to update the toggle for the missing 863 * packets within the qTD. 864 */ 865 pkts_left = EHCI_QTD_GET_BYTES(status) / 866 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 867 epipe->nexttoggle ^= pkts_left % 2; 868 869 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 870 xfer->length, actlen, status)); 871 xfer->actlen = actlen; 872 if (status & EHCI_QTD_HALTED) { 873 #ifdef EHCI_DEBUG 874 char sbuf[128]; 875 876 bitmask_snprintf((u_int32_t)status, 877 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 878 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 879 880 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 881 "status 0x%s\n", 882 xfer->pipe->device->address, 883 xfer->pipe->endpoint->edesc->bEndpointAddress, 884 sbuf)); 885 if (ehcidebug > 2) { 886 ehci_dump_sqh(epipe->sqh); 887 ehci_dump_sqtds(ex->sqtdstart); 888 } 889 #endif 890 /* low&full speed has an extra error flag */ 891 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 892 EHCI_QH_SPEED_HIGH) 893 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 894 else 895 status &= EHCI_QTD_STATERRS; 896 if (status == 0) /* no other errors means a stall */ 897 xfer->status = USBD_STALLED; 898 else 899 xfer->status = USBD_IOERROR; /* more info XXX */ 900 /* XXX need to reset TT on missed microframe */ 901 if (status & EHCI_QTD_MISSEDMICRO) { 902 ehci_softc_t *sc = (ehci_softc_t *) 903 xfer->pipe->device->bus; 904 905 printf("%s: missed microframe, TT reset not " 906 "implemented, hub might be inoperational\n", 907 USBDEVNAME(sc->sc_bus.bdev)); 908 } 909 } else { 910 xfer->status = USBD_NORMAL_COMPLETION; 911 } 912 913 usb_transfer_complete(xfer); 914 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 915 } 916 917 /* 918 * Wait here until controller claims to have an interrupt. 919 * Then call ehci_intr and return. Use timeout to avoid waiting 920 * too long. 921 */ 922 void 923 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 924 { 925 int timo = xfer->timeout; 926 int usecs; 927 u_int32_t intrs; 928 929 xfer->status = USBD_IN_PROGRESS; 930 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 931 usb_delay_ms(&sc->sc_bus, 1); 932 if (sc->sc_dying) 933 break; 934 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 935 sc->sc_eintrs; 936 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 937 #ifdef EHCI_DEBUG 938 if (ehcidebug > 15) 939 ehci_dump_regs(sc); 940 #endif 941 if (intrs) { 942 ehci_intr1(sc); 943 if (xfer->status != USBD_IN_PROGRESS) 944 return; 945 } 946 } 947 948 /* Timeout */ 949 DPRINTF(("ehci_waitintr: timeout\n")); 950 xfer->status = USBD_TIMEOUT; 951 usb_transfer_complete(xfer); 952 /* XXX should free TD */ 953 } 954 955 void 956 ehci_poll(struct usbd_bus *bus) 957 { 958 ehci_softc_t *sc = (ehci_softc_t *)bus; 959 #ifdef EHCI_DEBUG 960 static int last; 961 int new; 962 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 963 if (new != last) { 964 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 965 last = new; 966 } 967 #endif 968 969 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 970 ehci_intr1(sc); 971 } 972 973 int 974 ehci_detach(struct ehci_softc *sc, int flags) 975 { 976 int rv = 0; 977 978 if (sc->sc_child != NULL) 979 rv = config_detach(sc->sc_child, flags); 980 981 if (rv != 0) 982 return (rv); 983 984 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 985 usb_uncallout(sc->sc_tmo_pcd, ehci_pcd_enable, sc); 986 987 if (sc->sc_powerhook != NULL) 988 powerhook_disestablish(sc->sc_powerhook); 989 if (sc->sc_shutdownhook != NULL) 990 shutdownhook_disestablish(sc->sc_shutdownhook); 991 992 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 993 994 /* XXX free other data structures XXX */ 995 996 return (rv); 997 } 998 999 1000 int 1001 ehci_activate(device_ptr_t self, enum devact act) 1002 { 1003 struct ehci_softc *sc = (struct ehci_softc *)self; 1004 int rv = 0; 1005 1006 switch (act) { 1007 case DVACT_ACTIVATE: 1008 return (EOPNOTSUPP); 1009 1010 case DVACT_DEACTIVATE: 1011 if (sc->sc_child != NULL) 1012 rv = config_deactivate(sc->sc_child); 1013 sc->sc_dying = 1; 1014 break; 1015 } 1016 return (rv); 1017 } 1018 1019 /* 1020 * Handle suspend/resume. 1021 * 1022 * We need to switch to polling mode here, because this routine is 1023 * called from an interrupt context. This is all right since we 1024 * are almost suspended anyway. 1025 */ 1026 void 1027 ehci_power(int why, void *v) 1028 { 1029 ehci_softc_t *sc = v; 1030 u_int32_t cmd, hcr; 1031 int s, i; 1032 1033 #ifdef EHCI_DEBUG 1034 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1035 if (ehcidebug > 0) 1036 ehci_dump_regs(sc); 1037 #endif 1038 1039 s = splhardusb(); 1040 switch (why) { 1041 case PWR_SUSPEND: 1042 case PWR_STANDBY: 1043 sc->sc_bus.use_polling++; 1044 1045 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1046 1047 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1048 EOWRITE4(sc, EHCI_USBCMD, cmd); 1049 1050 for (i = 0; i < 100; i++) { 1051 hcr = EOREAD4(sc, EHCI_USBSTS) & 1052 (EHCI_STS_ASS | EHCI_STS_PSS); 1053 if (hcr == 0) 1054 break; 1055 1056 usb_delay_ms(&sc->sc_bus, 1); 1057 } 1058 if (hcr != 0) { 1059 printf("%s: reset timeout\n", 1060 USBDEVNAME(sc->sc_bus.bdev)); 1061 } 1062 1063 cmd &= ~EHCI_CMD_RS; 1064 EOWRITE4(sc, EHCI_USBCMD, cmd); 1065 1066 for (i = 0; i < 100; i++) { 1067 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1068 if (hcr == EHCI_STS_HCH) 1069 break; 1070 1071 usb_delay_ms(&sc->sc_bus, 1); 1072 } 1073 if (hcr != EHCI_STS_HCH) { 1074 printf("%s: config timeout\n", 1075 USBDEVNAME(sc->sc_bus.bdev)); 1076 } 1077 1078 sc->sc_bus.use_polling--; 1079 break; 1080 1081 case PWR_RESUME: 1082 sc->sc_bus.use_polling++; 1083 1084 /* restore things in case the bios sucks */ 1085 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1086 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1087 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1088 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1089 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1090 1091 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1092 1093 for (i = 0; i < 100; i++) { 1094 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1095 if (hcr != EHCI_STS_HCH) 1096 break; 1097 1098 usb_delay_ms(&sc->sc_bus, 1); 1099 } 1100 if (hcr == EHCI_STS_HCH) { 1101 printf("%s: config timeout\n", 1102 USBDEVNAME(sc->sc_bus.bdev)); 1103 } 1104 1105 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1106 1107 sc->sc_bus.use_polling--; 1108 break; 1109 case PWR_SOFTSUSPEND: 1110 case PWR_SOFTSTANDBY: 1111 case PWR_SOFTRESUME: 1112 break; 1113 } 1114 splx(s); 1115 1116 #ifdef EHCI_DEBUG 1117 DPRINTF(("ehci_power: sc=%p\n", sc)); 1118 if (ehcidebug > 0) 1119 ehci_dump_regs(sc); 1120 #endif 1121 } 1122 1123 /* 1124 * Shut down the controller when the system is going down. 1125 */ 1126 void 1127 ehci_shutdown(void *v) 1128 { 1129 ehci_softc_t *sc = v; 1130 1131 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1132 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1133 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1134 } 1135 1136 usbd_status 1137 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1138 { 1139 struct ehci_softc *sc = (struct ehci_softc *)bus; 1140 usbd_status err; 1141 1142 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1143 if (err == USBD_NOMEM) 1144 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1145 #ifdef EHCI_DEBUG 1146 if (err) 1147 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1148 #endif 1149 return (err); 1150 } 1151 1152 void 1153 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1154 { 1155 struct ehci_softc *sc = (struct ehci_softc *)bus; 1156 1157 if (dma->block->flags & USB_DMA_RESERVE) { 1158 usb_reserve_freem(&((struct ehci_softc *)bus)->sc_dma_reserve, 1159 dma); 1160 return; 1161 } 1162 usb_freemem(&sc->sc_bus, dma); 1163 } 1164 1165 usbd_xfer_handle 1166 ehci_allocx(struct usbd_bus *bus) 1167 { 1168 struct ehci_softc *sc = (struct ehci_softc *)bus; 1169 usbd_xfer_handle xfer; 1170 1171 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1172 if (xfer != NULL) { 1173 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1174 #ifdef DIAGNOSTIC 1175 if (xfer->busy_free != XFER_FREE) { 1176 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1177 xfer->busy_free); 1178 } 1179 #endif 1180 } else { 1181 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1182 } 1183 if (xfer != NULL) { 1184 memset(xfer, 0, sizeof(struct ehci_xfer)); 1185 #ifdef DIAGNOSTIC 1186 EXFER(xfer)->isdone = 1; 1187 xfer->busy_free = XFER_BUSY; 1188 #endif 1189 } 1190 return (xfer); 1191 } 1192 1193 void 1194 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1195 { 1196 struct ehci_softc *sc = (struct ehci_softc *)bus; 1197 1198 #ifdef DIAGNOSTIC 1199 if (xfer->busy_free != XFER_BUSY) { 1200 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1201 xfer->busy_free); 1202 return; 1203 } 1204 xfer->busy_free = XFER_FREE; 1205 if (!EXFER(xfer)->isdone) { 1206 printf("ehci_freex: !isdone\n"); 1207 return; 1208 } 1209 #endif 1210 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1211 } 1212 1213 Static void 1214 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1215 { 1216 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1217 1218 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1219 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1220 #ifdef USB_DEBUG 1221 if (ehcidebug) 1222 usbd_dump_pipe(pipe); 1223 #endif 1224 epipe->nexttoggle = 0; 1225 } 1226 1227 Static void 1228 ehci_noop(usbd_pipe_handle pipe) 1229 { 1230 } 1231 1232 #ifdef EHCI_DEBUG 1233 void 1234 ehci_dump_regs(ehci_softc_t *sc) 1235 { 1236 int i; 1237 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1238 EOREAD4(sc, EHCI_USBCMD), 1239 EOREAD4(sc, EHCI_USBSTS), 1240 EOREAD4(sc, EHCI_USBINTR)); 1241 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1242 EOREAD4(sc, EHCI_FRINDEX), 1243 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1244 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1245 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1246 for (i = 1; i <= sc->sc_noport; i++) 1247 printf("port %d status=0x%08x\n", i, 1248 EOREAD4(sc, EHCI_PORTSC(i))); 1249 } 1250 1251 /* 1252 * Unused function - this is meant to be called from a kernel 1253 * debugger. 1254 */ 1255 void 1256 ehci_dump() 1257 { 1258 ehci_dump_regs(theehci); 1259 } 1260 1261 void 1262 ehci_dump_link(ehci_link_t link, int type) 1263 { 1264 link = le32toh(link); 1265 printf("0x%08x", link); 1266 if (link & EHCI_LINK_TERMINATE) 1267 printf("<T>"); 1268 else { 1269 printf("<"); 1270 if (type) { 1271 switch (EHCI_LINK_TYPE(link)) { 1272 case EHCI_LINK_ITD: printf("ITD"); break; 1273 case EHCI_LINK_QH: printf("QH"); break; 1274 case EHCI_LINK_SITD: printf("SITD"); break; 1275 case EHCI_LINK_FSTN: printf("FSTN"); break; 1276 } 1277 } 1278 printf(">"); 1279 } 1280 } 1281 1282 void 1283 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1284 { 1285 int i; 1286 u_int32_t stop; 1287 1288 stop = 0; 1289 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1290 ehci_dump_sqtd(sqtd); 1291 usb_syncmem(&sqtd->dma, 1292 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1293 sizeof(sqtd->qtd), 1294 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1295 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1296 usb_syncmem(&sqtd->dma, 1297 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1298 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1299 } 1300 if (sqtd) 1301 printf("dump aborted, too many TDs\n"); 1302 } 1303 1304 void 1305 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1306 { 1307 usb_syncmem(&sqtd->dma, sqtd->offs, 1308 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1309 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1310 ehci_dump_qtd(&sqtd->qtd); 1311 usb_syncmem(&sqtd->dma, sqtd->offs, 1312 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1313 } 1314 1315 void 1316 ehci_dump_qtd(ehci_qtd_t *qtd) 1317 { 1318 u_int32_t s; 1319 char sbuf[128]; 1320 1321 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1322 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1323 printf("\n"); 1324 s = le32toh(qtd->qtd_status); 1325 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1326 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1327 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1328 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1329 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1330 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1331 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1332 EHCI_QTD_GET_PID(s), sbuf); 1333 for (s = 0; s < 5; s++) 1334 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1335 } 1336 1337 void 1338 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1339 { 1340 ehci_qh_t *qh = &sqh->qh; 1341 u_int32_t endp, endphub; 1342 1343 usb_syncmem(&sqh->dma, sqh->offs, 1344 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1345 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1346 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1347 endp = le32toh(qh->qh_endp); 1348 printf(" endp=0x%08x\n", endp); 1349 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1350 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1351 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1352 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1353 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1354 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1355 EHCI_QH_GET_NRL(endp)); 1356 endphub = le32toh(qh->qh_endphub); 1357 printf(" endphub=0x%08x\n", endphub); 1358 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1359 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1360 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1361 EHCI_QH_GET_MULT(endphub)); 1362 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1363 printf("Overlay qTD:\n"); 1364 ehci_dump_qtd(&qh->qh_qtd); 1365 usb_syncmem(&sqh->dma, sqh->offs, 1366 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1367 } 1368 1369 #ifdef DIAGNOSTIC 1370 Static void 1371 ehci_dump_exfer(struct ehci_xfer *ex) 1372 { 1373 printf("ehci_dump_exfer: ex=%p\n", ex); 1374 } 1375 #endif 1376 #endif 1377 1378 usbd_status 1379 ehci_open(usbd_pipe_handle pipe) 1380 { 1381 usbd_device_handle dev = pipe->device; 1382 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1383 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1384 u_int8_t addr = dev->address; 1385 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1386 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1387 ehci_soft_qh_t *sqh; 1388 usbd_status err; 1389 int s; 1390 int ival, speed, naks; 1391 int hshubaddr, hshubport; 1392 1393 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1394 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1395 1396 if (dev->myhsport) { 1397 hshubaddr = dev->myhsport->parent->address; 1398 hshubport = dev->myhsport->portno; 1399 } else { 1400 hshubaddr = 0; 1401 hshubport = 0; 1402 } 1403 1404 if (sc->sc_dying) 1405 return (USBD_IOERROR); 1406 1407 epipe->nexttoggle = 0; 1408 1409 if (addr == sc->sc_addr) { 1410 switch (ed->bEndpointAddress) { 1411 case USB_CONTROL_ENDPOINT: 1412 pipe->methods = &ehci_root_ctrl_methods; 1413 break; 1414 case UE_DIR_IN | EHCI_INTR_ENDPT: 1415 pipe->methods = &ehci_root_intr_methods; 1416 break; 1417 default: 1418 return (USBD_INVAL); 1419 } 1420 return (USBD_NORMAL_COMPLETION); 1421 } 1422 1423 /* XXX All this stuff is only valid for async. */ 1424 switch (dev->speed) { 1425 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1426 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1427 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1428 default: panic("ehci_open: bad device speed %d", dev->speed); 1429 } 1430 if (speed != EHCI_QH_SPEED_HIGH) { 1431 printf("%s: *** WARNING: opening low/full speed device, this " 1432 "may not work yet.\n", 1433 USBDEVNAME(sc->sc_bus.bdev)); 1434 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1435 hshubaddr, hshubport)); 1436 #if 0 1437 if (xfertype != UE_CONTROL) 1438 return USBD_INVAL; 1439 #endif 1440 } 1441 1442 naks = 8; /* XXX */ 1443 sqh = ehci_alloc_sqh(sc); 1444 if (sqh == NULL) 1445 goto bad0; 1446 /* qh_link filled when the QH is added */ 1447 sqh->qh.qh_endp = htole32( 1448 EHCI_QH_SET_ADDR(addr) | 1449 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1450 EHCI_QH_SET_EPS(speed) | 1451 EHCI_QH_DTC | 1452 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1453 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1454 EHCI_QH_CTL : 0) | 1455 EHCI_QH_SET_NRL(naks) 1456 ); 1457 sqh->qh.qh_endphub = htole32( 1458 EHCI_QH_SET_MULT(1) | 1459 EHCI_QH_SET_HUBA(hshubaddr) | 1460 EHCI_QH_SET_PORT(hshubport) | 1461 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1462 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1463 ); 1464 sqh->qh.qh_curqtd = EHCI_NULL; 1465 /* Fill the overlay qTD */ 1466 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1467 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1468 sqh->qh.qh_qtd.qtd_status = htole32(0); 1469 1470 usb_syncmem(&sqh->dma, sqh->offs, 1471 sizeof(sqh->qh), BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1472 epipe->sqh = sqh; 1473 1474 switch (xfertype) { 1475 case UE_CONTROL: 1476 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1477 0, &epipe->u.ctl.reqdma); 1478 #ifdef EHCI_DEBUG 1479 if (err) 1480 printf("ehci_open: usb_allocmem()=%d\n", err); 1481 #endif 1482 if (err) 1483 goto bad1; 1484 pipe->methods = &ehci_device_ctrl_methods; 1485 s = splusb(); 1486 ehci_add_qh(sqh, sc->sc_async_head); 1487 splx(s); 1488 break; 1489 case UE_BULK: 1490 pipe->methods = &ehci_device_bulk_methods; 1491 s = splusb(); 1492 ehci_add_qh(sqh, sc->sc_async_head); 1493 splx(s); 1494 break; 1495 case UE_INTERRUPT: 1496 pipe->methods = &ehci_device_intr_methods; 1497 ival = pipe->interval; 1498 if (ival == USBD_DEFAULT_INTERVAL) 1499 ival = ed->bInterval; 1500 return (ehci_device_setintr(sc, sqh, ival)); 1501 case UE_ISOCHRONOUS: 1502 pipe->methods = &ehci_device_isoc_methods; 1503 return (USBD_INVAL); 1504 default: 1505 return (USBD_INVAL); 1506 } 1507 return (USBD_NORMAL_COMPLETION); 1508 1509 bad1: 1510 ehci_free_sqh(sc, sqh); 1511 bad0: 1512 return (USBD_NOMEM); 1513 } 1514 1515 /* 1516 * Add an ED to the schedule. Called at splusb(). 1517 */ 1518 void 1519 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1520 { 1521 SPLUSBCHECK; 1522 1523 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1524 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1525 sqh->next = head->next; 1526 sqh->qh.qh_link = head->qh.qh_link; 1527 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1528 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1529 head->next = sqh; 1530 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1531 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1532 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1533 1534 #ifdef EHCI_DEBUG 1535 if (ehcidebug > 5) { 1536 printf("ehci_add_qh:\n"); 1537 ehci_dump_sqh(sqh); 1538 } 1539 #endif 1540 } 1541 1542 /* 1543 * Remove an ED from the schedule. Called at splusb(). 1544 */ 1545 void 1546 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1547 { 1548 ehci_soft_qh_t *p; 1549 1550 SPLUSBCHECK; 1551 /* XXX */ 1552 for (p = head; p != NULL && p->next != sqh; p = p->next) 1553 ; 1554 if (p == NULL) 1555 panic("ehci_rem_qh: ED not found"); 1556 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1557 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1558 p->next = sqh->next; 1559 p->qh.qh_link = sqh->qh.qh_link; 1560 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1561 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1562 1563 ehci_sync_hc(sc); 1564 } 1565 1566 void 1567 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1568 { 1569 int i; 1570 u_int32_t status; 1571 1572 /* Save toggle bit and ping status. */ 1573 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1574 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1575 status = sqh->qh.qh_qtd.qtd_status & 1576 htole32(EHCI_QTD_TOGGLE_MASK | 1577 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1578 /* Set HALTED to make hw leave it alone. */ 1579 sqh->qh.qh_qtd.qtd_status = 1580 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1581 usb_syncmem(&sqh->dma, 1582 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1583 sizeof(sqh->qh.qh_qtd.qtd_status), 1584 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1585 sqh->qh.qh_curqtd = 0; 1586 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1587 sqh->qh.qh_qtd.qtd_altnext = 0; 1588 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1589 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1590 sqh->sqtd = sqtd; 1591 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1592 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1593 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1594 sqh->qh.qh_qtd.qtd_status = status; 1595 usb_syncmem(&sqh->dma, 1596 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1597 sizeof(sqh->qh.qh_qtd.qtd_status), 1598 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1599 } 1600 1601 /* 1602 * Ensure that the HC has released all references to the QH. We do this 1603 * by asking for a Async Advance Doorbell interrupt and then we wait for 1604 * the interrupt. 1605 * To make this easier we first obtain exclusive use of the doorbell. 1606 */ 1607 void 1608 ehci_sync_hc(ehci_softc_t *sc) 1609 { 1610 int s, error; 1611 1612 if (sc->sc_dying) { 1613 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1614 return; 1615 } 1616 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1617 usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); /* get doorbell */ 1618 s = splhardusb(); 1619 /* ask for doorbell */ 1620 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1621 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1622 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1623 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1624 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1625 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1626 splx(s); 1627 usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); /* release doorbell */ 1628 #ifdef DIAGNOSTIC 1629 if (error) 1630 printf("ehci_sync_hc: tsleep() = %d\n", error); 1631 #endif 1632 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1633 } 1634 1635 /***********/ 1636 1637 /* 1638 * Data structures and routines to emulate the root hub. 1639 */ 1640 Static usb_device_descriptor_t ehci_devd = { 1641 USB_DEVICE_DESCRIPTOR_SIZE, 1642 UDESC_DEVICE, /* type */ 1643 {0x00, 0x02}, /* USB version */ 1644 UDCLASS_HUB, /* class */ 1645 UDSUBCLASS_HUB, /* subclass */ 1646 UDPROTO_HSHUBSTT, /* protocol */ 1647 64, /* max packet */ 1648 {0},{0},{0x00,0x01}, /* device id */ 1649 1,2,0, /* string indicies */ 1650 1 /* # of configurations */ 1651 }; 1652 1653 Static usb_device_qualifier_t ehci_odevd = { 1654 USB_DEVICE_DESCRIPTOR_SIZE, 1655 UDESC_DEVICE_QUALIFIER, /* type */ 1656 {0x00, 0x02}, /* USB version */ 1657 UDCLASS_HUB, /* class */ 1658 UDSUBCLASS_HUB, /* subclass */ 1659 UDPROTO_FSHUB, /* protocol */ 1660 64, /* max packet */ 1661 1, /* # of configurations */ 1662 0 1663 }; 1664 1665 Static usb_config_descriptor_t ehci_confd = { 1666 USB_CONFIG_DESCRIPTOR_SIZE, 1667 UDESC_CONFIG, 1668 {USB_CONFIG_DESCRIPTOR_SIZE + 1669 USB_INTERFACE_DESCRIPTOR_SIZE + 1670 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1671 1, 1672 1, 1673 0, 1674 UC_SELF_POWERED, 1675 0 /* max power */ 1676 }; 1677 1678 Static usb_interface_descriptor_t ehci_ifcd = { 1679 USB_INTERFACE_DESCRIPTOR_SIZE, 1680 UDESC_INTERFACE, 1681 0, 1682 0, 1683 1, 1684 UICLASS_HUB, 1685 UISUBCLASS_HUB, 1686 UIPROTO_HSHUBSTT, 1687 0 1688 }; 1689 1690 Static usb_endpoint_descriptor_t ehci_endpd = { 1691 USB_ENDPOINT_DESCRIPTOR_SIZE, 1692 UDESC_ENDPOINT, 1693 UE_DIR_IN | EHCI_INTR_ENDPT, 1694 UE_INTERRUPT, 1695 {8, 0}, /* max packet */ 1696 255 1697 }; 1698 1699 Static usb_hub_descriptor_t ehci_hubd = { 1700 USB_HUB_DESCRIPTOR_SIZE, 1701 UDESC_HUB, 1702 0, 1703 {0,0}, 1704 0, 1705 0, 1706 {0}, 1707 }; 1708 1709 Static int 1710 ehci_str(usb_string_descriptor_t *p, int l, char *s) 1711 { 1712 int i; 1713 1714 if (l == 0) 1715 return (0); 1716 p->bLength = 2 * strlen(s) + 2; 1717 if (l == 1) 1718 return (1); 1719 p->bDescriptorType = UDESC_STRING; 1720 l -= 2; 1721 for (i = 0; s[i] && l > 1; i++, l -= 2) 1722 USETW2(p->bString[i], 0, s[i]); 1723 return (2*i+2); 1724 } 1725 1726 /* 1727 * Simulate a hardware hub by handling all the necessary requests. 1728 */ 1729 Static usbd_status 1730 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1731 { 1732 usbd_status err; 1733 1734 /* Insert last in queue. */ 1735 err = usb_insert_transfer(xfer); 1736 if (err) 1737 return (err); 1738 1739 /* Pipe isn't running, start first */ 1740 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1741 } 1742 1743 Static usbd_status 1744 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1745 { 1746 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1747 usb_device_request_t *req; 1748 void *buf = NULL; 1749 int port, i; 1750 int s, len, value, index, l, totlen = 0; 1751 usb_port_status_t ps; 1752 usb_hub_descriptor_t hubd; 1753 usbd_status err; 1754 u_int32_t v; 1755 1756 if (sc->sc_dying) 1757 return (USBD_IOERROR); 1758 1759 #ifdef DIAGNOSTIC 1760 if (!(xfer->rqflags & URQ_REQUEST)) 1761 /* XXX panic */ 1762 return (USBD_INVAL); 1763 #endif 1764 req = &xfer->request; 1765 1766 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1767 req->bmRequestType, req->bRequest)); 1768 1769 len = UGETW(req->wLength); 1770 value = UGETW(req->wValue); 1771 index = UGETW(req->wIndex); 1772 1773 if (len != 0) 1774 buf = KERNADDR(&xfer->dmabuf, 0); 1775 1776 #define C(x,y) ((x) | ((y) << 8)) 1777 switch(C(req->bRequest, req->bmRequestType)) { 1778 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1779 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1780 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1781 /* 1782 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1783 * for the integrated root hub. 1784 */ 1785 break; 1786 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1787 if (len > 0) { 1788 *(u_int8_t *)buf = sc->sc_conf; 1789 totlen = 1; 1790 } 1791 break; 1792 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1793 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1794 switch(value >> 8) { 1795 case UDESC_DEVICE: 1796 if ((value & 0xff) != 0) { 1797 err = USBD_IOERROR; 1798 goto ret; 1799 } 1800 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1801 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1802 memcpy(buf, &ehci_devd, l); 1803 break; 1804 /* 1805 * We can't really operate at another speed, but the spec says 1806 * we need this descriptor. 1807 */ 1808 case UDESC_DEVICE_QUALIFIER: 1809 if ((value & 0xff) != 0) { 1810 err = USBD_IOERROR; 1811 goto ret; 1812 } 1813 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1814 memcpy(buf, &ehci_odevd, l); 1815 break; 1816 /* 1817 * We can't really operate at another speed, but the spec says 1818 * we need this descriptor. 1819 */ 1820 case UDESC_OTHER_SPEED_CONFIGURATION: 1821 case UDESC_CONFIG: 1822 if ((value & 0xff) != 0) { 1823 err = USBD_IOERROR; 1824 goto ret; 1825 } 1826 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1827 memcpy(buf, &ehci_confd, l); 1828 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1829 value >> 8; 1830 buf = (char *)buf + l; 1831 len -= l; 1832 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1833 totlen += l; 1834 memcpy(buf, &ehci_ifcd, l); 1835 buf = (char *)buf + l; 1836 len -= l; 1837 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1838 totlen += l; 1839 memcpy(buf, &ehci_endpd, l); 1840 break; 1841 case UDESC_STRING: 1842 if (len == 0) 1843 break; 1844 *(u_int8_t *)buf = 0; 1845 totlen = 1; 1846 switch (value & 0xff) { 1847 case 0: /* Language table */ 1848 totlen = ehci_str(buf, len, "\001"); 1849 break; 1850 case 1: /* Vendor */ 1851 totlen = ehci_str(buf, len, sc->sc_vendor); 1852 break; 1853 case 2: /* Product */ 1854 totlen = ehci_str(buf, len, "EHCI root hub"); 1855 break; 1856 } 1857 break; 1858 default: 1859 err = USBD_IOERROR; 1860 goto ret; 1861 } 1862 break; 1863 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1864 if (len > 0) { 1865 *(u_int8_t *)buf = 0; 1866 totlen = 1; 1867 } 1868 break; 1869 case C(UR_GET_STATUS, UT_READ_DEVICE): 1870 if (len > 1) { 1871 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1872 totlen = 2; 1873 } 1874 break; 1875 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1876 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1877 if (len > 1) { 1878 USETW(((usb_status_t *)buf)->wStatus, 0); 1879 totlen = 2; 1880 } 1881 break; 1882 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1883 if (value >= USB_MAX_DEVICES) { 1884 err = USBD_IOERROR; 1885 goto ret; 1886 } 1887 sc->sc_addr = value; 1888 break; 1889 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1890 if (value != 0 && value != 1) { 1891 err = USBD_IOERROR; 1892 goto ret; 1893 } 1894 sc->sc_conf = value; 1895 break; 1896 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1897 break; 1898 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1899 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1900 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1901 err = USBD_IOERROR; 1902 goto ret; 1903 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1904 break; 1905 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1906 break; 1907 /* Hub requests */ 1908 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1909 break; 1910 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1911 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 1912 "port=%d feature=%d\n", 1913 index, value)); 1914 if (index < 1 || index > sc->sc_noport) { 1915 err = USBD_IOERROR; 1916 goto ret; 1917 } 1918 port = EHCI_PORTSC(index); 1919 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1920 switch(value) { 1921 case UHF_PORT_ENABLE: 1922 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1923 break; 1924 case UHF_PORT_SUSPEND: 1925 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1926 break; 1927 case UHF_PORT_POWER: 1928 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1929 break; 1930 case UHF_PORT_TEST: 1931 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 1932 "%d\n", index)); 1933 break; 1934 case UHF_PORT_INDICATOR: 1935 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 1936 "%d\n", index)); 1937 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1938 break; 1939 case UHF_C_PORT_CONNECTION: 1940 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1941 break; 1942 case UHF_C_PORT_ENABLE: 1943 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1944 break; 1945 case UHF_C_PORT_SUSPEND: 1946 /* how? */ 1947 break; 1948 case UHF_C_PORT_OVER_CURRENT: 1949 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1950 break; 1951 case UHF_C_PORT_RESET: 1952 sc->sc_isreset = 0; 1953 break; 1954 default: 1955 err = USBD_IOERROR; 1956 goto ret; 1957 } 1958 #if 0 1959 switch(value) { 1960 case UHF_C_PORT_CONNECTION: 1961 case UHF_C_PORT_ENABLE: 1962 case UHF_C_PORT_SUSPEND: 1963 case UHF_C_PORT_OVER_CURRENT: 1964 case UHF_C_PORT_RESET: 1965 /* Enable RHSC interrupt if condition is cleared. */ 1966 if ((OREAD4(sc, port) >> 16) == 0) 1967 ehci_pcd_able(sc, 1); 1968 break; 1969 default: 1970 break; 1971 } 1972 #endif 1973 break; 1974 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1975 if ((value & 0xff) != 0) { 1976 err = USBD_IOERROR; 1977 goto ret; 1978 } 1979 hubd = ehci_hubd; 1980 hubd.bNbrPorts = sc->sc_noport; 1981 v = EOREAD4(sc, EHCI_HCSPARAMS); 1982 USETW(hubd.wHubCharacteristics, 1983 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 1984 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 1985 ? UHD_PORT_IND : 0); 1986 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 1987 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1988 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 1989 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1990 l = min(len, hubd.bDescLength); 1991 totlen = l; 1992 memcpy(buf, &hubd, l); 1993 break; 1994 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1995 if (len != 4) { 1996 err = USBD_IOERROR; 1997 goto ret; 1998 } 1999 memset(buf, 0, len); /* ? XXX */ 2000 totlen = len; 2001 break; 2002 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2003 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2004 index)); 2005 if (index < 1 || index > sc->sc_noport) { 2006 err = USBD_IOERROR; 2007 goto ret; 2008 } 2009 if (len != 4) { 2010 err = USBD_IOERROR; 2011 goto ret; 2012 } 2013 v = EOREAD4(sc, EHCI_PORTSC(index)); 2014 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2015 v)); 2016 i = UPS_HIGH_SPEED; 2017 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2018 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2019 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2020 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2021 if (v & EHCI_PS_PR) i |= UPS_RESET; 2022 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2023 USETW(ps.wPortStatus, i); 2024 i = 0; 2025 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2026 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2027 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2028 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2029 USETW(ps.wPortChange, i); 2030 l = min(len, sizeof ps); 2031 memcpy(buf, &ps, l); 2032 totlen = l; 2033 break; 2034 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2035 err = USBD_IOERROR; 2036 goto ret; 2037 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2038 break; 2039 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2040 if (index < 1 || index > sc->sc_noport) { 2041 err = USBD_IOERROR; 2042 goto ret; 2043 } 2044 port = EHCI_PORTSC(index); 2045 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2046 switch(value) { 2047 case UHF_PORT_ENABLE: 2048 EOWRITE4(sc, port, v | EHCI_PS_PE); 2049 break; 2050 case UHF_PORT_SUSPEND: 2051 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2052 break; 2053 case UHF_PORT_RESET: 2054 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2055 index)); 2056 if (EHCI_PS_IS_LOWSPEED(v)) { 2057 /* Low speed device, give up ownership. */ 2058 ehci_disown(sc, index, 1); 2059 break; 2060 } 2061 /* Start reset sequence. */ 2062 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2063 EOWRITE4(sc, port, v | EHCI_PS_PR); 2064 /* Wait for reset to complete. */ 2065 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2066 if (sc->sc_dying) { 2067 err = USBD_IOERROR; 2068 goto ret; 2069 } 2070 /* Terminate reset sequence. */ 2071 EOWRITE4(sc, port, v); 2072 /* Wait for HC to complete reset. */ 2073 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2074 if (sc->sc_dying) { 2075 err = USBD_IOERROR; 2076 goto ret; 2077 } 2078 v = EOREAD4(sc, port); 2079 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2080 if (v & EHCI_PS_PR) { 2081 printf("%s: port reset timeout\n", 2082 USBDEVNAME(sc->sc_bus.bdev)); 2083 return (USBD_TIMEOUT); 2084 } 2085 if (!(v & EHCI_PS_PE)) { 2086 /* Not a high speed device, give up ownership.*/ 2087 ehci_disown(sc, index, 0); 2088 break; 2089 } 2090 sc->sc_isreset = 1; 2091 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2092 index, v)); 2093 break; 2094 case UHF_PORT_POWER: 2095 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2096 "%d\n", index)); 2097 EOWRITE4(sc, port, v | EHCI_PS_PP); 2098 break; 2099 case UHF_PORT_TEST: 2100 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2101 "%d\n", index)); 2102 break; 2103 case UHF_PORT_INDICATOR: 2104 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2105 "%d\n", index)); 2106 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2107 break; 2108 default: 2109 err = USBD_IOERROR; 2110 goto ret; 2111 } 2112 break; 2113 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2114 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2115 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2116 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2117 break; 2118 default: 2119 err = USBD_IOERROR; 2120 goto ret; 2121 } 2122 xfer->actlen = totlen; 2123 err = USBD_NORMAL_COMPLETION; 2124 ret: 2125 xfer->status = err; 2126 s = splusb(); 2127 usb_transfer_complete(xfer); 2128 splx(s); 2129 return (USBD_IN_PROGRESS); 2130 } 2131 2132 void 2133 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2134 { 2135 int port; 2136 u_int32_t v; 2137 2138 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2139 #ifdef DIAGNOSTIC 2140 if (sc->sc_npcomp != 0) { 2141 int i = (index-1) / sc->sc_npcomp; 2142 if (i >= sc->sc_ncomp) 2143 printf("%s: strange port\n", 2144 USBDEVNAME(sc->sc_bus.bdev)); 2145 else 2146 printf("%s: handing over %s speed device on " 2147 "port %d to %s\n", 2148 USBDEVNAME(sc->sc_bus.bdev), 2149 lowspeed ? "low" : "full", 2150 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 2151 } else { 2152 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 2153 } 2154 #endif 2155 port = EHCI_PORTSC(index); 2156 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2157 EOWRITE4(sc, port, v | EHCI_PS_PO); 2158 } 2159 2160 /* Abort a root control request. */ 2161 Static void 2162 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2163 { 2164 /* Nothing to do, all transfers are synchronous. */ 2165 } 2166 2167 /* Close the root pipe. */ 2168 Static void 2169 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2170 { 2171 DPRINTF(("ehci_root_ctrl_close\n")); 2172 /* Nothing to do. */ 2173 } 2174 2175 void 2176 ehci_root_intr_done(usbd_xfer_handle xfer) 2177 { 2178 xfer->hcpriv = NULL; 2179 } 2180 2181 Static usbd_status 2182 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2183 { 2184 usbd_status err; 2185 2186 /* Insert last in queue. */ 2187 err = usb_insert_transfer(xfer); 2188 if (err) 2189 return (err); 2190 2191 /* Pipe isn't running, start first */ 2192 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2193 } 2194 2195 Static usbd_status 2196 ehci_root_intr_start(usbd_xfer_handle xfer) 2197 { 2198 usbd_pipe_handle pipe = xfer->pipe; 2199 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2200 2201 if (sc->sc_dying) 2202 return (USBD_IOERROR); 2203 2204 sc->sc_intrxfer = xfer; 2205 2206 return (USBD_IN_PROGRESS); 2207 } 2208 2209 /* Abort a root interrupt request. */ 2210 Static void 2211 ehci_root_intr_abort(usbd_xfer_handle xfer) 2212 { 2213 int s; 2214 2215 if (xfer->pipe->intrxfer == xfer) { 2216 DPRINTF(("ehci_root_intr_abort: remove\n")); 2217 xfer->pipe->intrxfer = NULL; 2218 } 2219 xfer->status = USBD_CANCELLED; 2220 s = splusb(); 2221 usb_transfer_complete(xfer); 2222 splx(s); 2223 } 2224 2225 /* Close the root pipe. */ 2226 Static void 2227 ehci_root_intr_close(usbd_pipe_handle pipe) 2228 { 2229 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2230 2231 DPRINTF(("ehci_root_intr_close\n")); 2232 2233 sc->sc_intrxfer = NULL; 2234 } 2235 2236 void 2237 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2238 { 2239 xfer->hcpriv = NULL; 2240 } 2241 2242 /************************/ 2243 2244 ehci_soft_qh_t * 2245 ehci_alloc_sqh(ehci_softc_t *sc) 2246 { 2247 ehci_soft_qh_t *sqh; 2248 usbd_status err; 2249 int i, offs; 2250 usb_dma_t dma; 2251 2252 if (sc->sc_freeqhs == NULL) { 2253 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2254 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2255 EHCI_PAGE_SIZE, &dma); 2256 #ifdef EHCI_DEBUG 2257 if (err) 2258 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2259 #endif 2260 if (err) 2261 return (NULL); 2262 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2263 offs = i * EHCI_SQH_SIZE; 2264 sqh = KERNADDR(&dma, offs); 2265 sqh->physaddr = DMAADDR(&dma, offs); 2266 sqh->dma = dma; 2267 sqh->offs = offs; 2268 sqh->next = sc->sc_freeqhs; 2269 sc->sc_freeqhs = sqh; 2270 } 2271 } 2272 sqh = sc->sc_freeqhs; 2273 sc->sc_freeqhs = sqh->next; 2274 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2275 sqh->next = NULL; 2276 return (sqh); 2277 } 2278 2279 void 2280 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2281 { 2282 sqh->next = sc->sc_freeqhs; 2283 sc->sc_freeqhs = sqh; 2284 } 2285 2286 ehci_soft_qtd_t * 2287 ehci_alloc_sqtd(ehci_softc_t *sc) 2288 { 2289 ehci_soft_qtd_t *sqtd; 2290 usbd_status err; 2291 int i, offs; 2292 usb_dma_t dma; 2293 int s; 2294 2295 if (sc->sc_freeqtds == NULL) { 2296 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2297 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2298 EHCI_PAGE_SIZE, &dma); 2299 #ifdef EHCI_DEBUG 2300 if (err) 2301 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2302 #endif 2303 if (err) 2304 return (NULL); 2305 s = splusb(); 2306 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2307 offs = i * EHCI_SQTD_SIZE; 2308 sqtd = KERNADDR(&dma, offs); 2309 sqtd->physaddr = DMAADDR(&dma, offs); 2310 sqtd->dma = dma; 2311 sqtd->offs = offs; 2312 sqtd->nextqtd = sc->sc_freeqtds; 2313 sc->sc_freeqtds = sqtd; 2314 } 2315 splx(s); 2316 } 2317 2318 s = splusb(); 2319 sqtd = sc->sc_freeqtds; 2320 sc->sc_freeqtds = sqtd->nextqtd; 2321 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2322 sqtd->nextqtd = NULL; 2323 sqtd->xfer = NULL; 2324 splx(s); 2325 2326 return (sqtd); 2327 } 2328 2329 void 2330 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2331 { 2332 int s; 2333 2334 s = splusb(); 2335 sqtd->nextqtd = sc->sc_freeqtds; 2336 sc->sc_freeqtds = sqtd; 2337 splx(s); 2338 } 2339 2340 usbd_status 2341 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2342 int alen, int rd, usbd_xfer_handle xfer, 2343 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2344 { 2345 ehci_soft_qtd_t *next, *cur; 2346 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2347 u_int32_t qtdstatus; 2348 int len, curlen, mps; 2349 int i, tog; 2350 usb_dma_t *dma = &xfer->dmabuf; 2351 u_int16_t flags = xfer->flags; 2352 2353 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2354 2355 len = alen; 2356 dataphys = DMAADDR(dma, 0); 2357 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2358 qtdstatus = EHCI_QTD_ACTIVE | 2359 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2360 EHCI_QTD_SET_CERR(3) 2361 /* IOC set below */ 2362 /* BYTES set below */ 2363 ; 2364 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2365 tog = epipe->nexttoggle; 2366 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2367 2368 cur = ehci_alloc_sqtd(sc); 2369 *sp = cur; 2370 if (cur == NULL) 2371 goto nomem; 2372 2373 usb_syncmem(dma, 0, alen, 2374 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2375 for (;;) { 2376 dataphyspage = EHCI_PAGE(dataphys); 2377 /* The EHCI hardware can handle at most 5 pages. */ 2378 if (dataphyslastpage - dataphyspage < 2379 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2380 /* we can handle it in this QTD */ 2381 curlen = len; 2382 } else { 2383 /* must use multiple TDs, fill as much as possible. */ 2384 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2385 EHCI_PAGE_OFFSET(dataphys); 2386 #ifdef DIAGNOSTIC 2387 if (curlen > len) { 2388 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2389 "len=0x%x offs=0x%x\n", curlen, len, 2390 EHCI_PAGE_OFFSET(dataphys)); 2391 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2392 dataphyslastpage, dataphyspage, 2393 dataphys); 2394 curlen = len; 2395 } 2396 #endif 2397 /* the length must be a multiple of the max size */ 2398 curlen -= curlen % mps; 2399 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2400 "curlen=%d\n", curlen)); 2401 #ifdef DIAGNOSTIC 2402 if (curlen == 0) 2403 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2404 #endif 2405 } 2406 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2407 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2408 dataphys, dataphyslastpage, 2409 len, curlen)); 2410 len -= curlen; 2411 2412 /* 2413 * Allocate another transfer if there's more data left, 2414 * or if force last short transfer flag is set and we're 2415 * allocating a multiple of the max packet size. 2416 */ 2417 if (len != 0 || 2418 ((curlen % mps) == 0 && !rd && curlen != 0 && 2419 (flags & USBD_FORCE_SHORT_XFER))) { 2420 next = ehci_alloc_sqtd(sc); 2421 if (next == NULL) 2422 goto nomem; 2423 nextphys = htole32(next->physaddr); 2424 } else { 2425 next = NULL; 2426 nextphys = EHCI_NULL; 2427 } 2428 2429 for (i = 0; i * EHCI_PAGE_SIZE < 2430 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2431 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2432 if (i != 0) /* use offset only in first buffer */ 2433 a = EHCI_PAGE(a); 2434 cur->qtd.qtd_buffer[i] = htole32(a); 2435 cur->qtd.qtd_buffer_hi[i] = 0; 2436 #ifdef DIAGNOSTIC 2437 if (i >= EHCI_QTD_NBUFFERS) { 2438 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2439 goto nomem; 2440 } 2441 #endif 2442 } 2443 cur->nextqtd = next; 2444 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2445 cur->qtd.qtd_status = 2446 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2447 cur->xfer = xfer; 2448 cur->len = curlen; 2449 2450 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2451 dataphys, dataphys + curlen)); 2452 /* adjust the toggle based on the number of packets in this 2453 qtd */ 2454 if (((curlen + mps - 1) / mps) & 1) { 2455 tog ^= 1; 2456 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2457 } 2458 if (next == NULL) 2459 break; 2460 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2461 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2462 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2463 dataphys += curlen; 2464 cur = next; 2465 } 2466 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2467 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2469 *ep = cur; 2470 epipe->nexttoggle = tog; 2471 2472 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2473 *sp, *ep)); 2474 2475 return (USBD_NORMAL_COMPLETION); 2476 2477 nomem: 2478 /* XXX free chain */ 2479 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2480 return (USBD_NOMEM); 2481 } 2482 2483 Static void 2484 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2485 ehci_soft_qtd_t *sqtdend) 2486 { 2487 ehci_soft_qtd_t *p; 2488 int i; 2489 2490 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2491 sqtd, sqtdend)); 2492 2493 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2494 p = sqtd->nextqtd; 2495 ehci_free_sqtd(sc, sqtd); 2496 } 2497 } 2498 2499 /****************/ 2500 2501 /* 2502 * Close a reqular pipe. 2503 * Assumes that there are no pending transactions. 2504 */ 2505 void 2506 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2507 { 2508 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2509 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2510 ehci_soft_qh_t *sqh = epipe->sqh; 2511 int s; 2512 2513 s = splusb(); 2514 ehci_rem_qh(sc, sqh, head); 2515 splx(s); 2516 ehci_free_sqh(sc, epipe->sqh); 2517 } 2518 2519 /* 2520 * Abort a device request. 2521 * If this routine is called at splusb() it guarantees that the request 2522 * will be removed from the hardware scheduling and that the callback 2523 * for it will be called with USBD_CANCELLED status. 2524 * It's impossible to guarantee that the requested transfer will not 2525 * have happened since the hardware runs concurrently. 2526 * If the transaction has already happened we rely on the ordinary 2527 * interrupt processing to process it. 2528 * XXX This is most probably wrong. 2529 */ 2530 void 2531 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2532 { 2533 #define exfer EXFER(xfer) 2534 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2535 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2536 ehci_soft_qh_t *sqh = epipe->sqh; 2537 ehci_soft_qtd_t *sqtd; 2538 ehci_physaddr_t cur; 2539 u_int32_t qhstatus; 2540 int s; 2541 int hit; 2542 int wake; 2543 2544 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2545 2546 if (sc->sc_dying) { 2547 /* If we're dying, just do the software part. */ 2548 s = splusb(); 2549 xfer->status = status; /* make software ignore it */ 2550 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2551 usb_transfer_complete(xfer); 2552 splx(s); 2553 return; 2554 } 2555 2556 if (xfer->device->bus->intr_context || !curproc) 2557 panic("ehci_abort_xfer: not in process context"); 2558 2559 /* 2560 * If an abort is already in progress then just wait for it to 2561 * complete and return. 2562 */ 2563 if (xfer->hcflags & UXFER_ABORTING) { 2564 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2565 #ifdef DIAGNOSTIC 2566 if (status == USBD_TIMEOUT) 2567 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2568 #endif 2569 /* Override the status which might be USBD_TIMEOUT. */ 2570 xfer->status = status; 2571 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2572 xfer->hcflags |= UXFER_ABORTWAIT; 2573 while (xfer->hcflags & UXFER_ABORTING) 2574 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2575 return; 2576 } 2577 xfer->hcflags |= UXFER_ABORTING; 2578 2579 /* 2580 * Step 1: Make interrupt routine and hardware ignore xfer. 2581 */ 2582 s = splusb(); 2583 xfer->status = status; /* make software ignore it */ 2584 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2585 2586 usb_syncmem(&sqh->dma, 2587 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2588 sizeof(sqh->qh.qh_qtd.qtd_status), 2589 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2590 qhstatus = sqh->qh.qh_qtd.qtd_status; 2591 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2592 usb_syncmem(&sqh->dma, 2593 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2594 sizeof(sqh->qh.qh_qtd.qtd_status), 2595 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2596 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2597 usb_syncmem(&sqtd->dma, 2598 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2599 sizeof(sqtd->qtd.qtd_status), 2600 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2601 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2602 usb_syncmem(&sqtd->dma, 2603 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2604 sizeof(sqtd->qtd.qtd_status), 2605 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2606 if (sqtd == exfer->sqtdend) 2607 break; 2608 } 2609 splx(s); 2610 2611 /* 2612 * Step 2: Wait until we know hardware has finished any possible 2613 * use of the xfer. Also make sure the soft interrupt routine 2614 * has run. 2615 */ 2616 ehci_sync_hc(sc); 2617 s = splusb(); 2618 #ifdef USB_USE_SOFTINTR 2619 sc->sc_softwake = 1; 2620 #endif /* USB_USE_SOFTINTR */ 2621 usb_schedsoftintr(&sc->sc_bus); 2622 #ifdef USB_USE_SOFTINTR 2623 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2624 #endif /* USB_USE_SOFTINTR */ 2625 splx(s); 2626 2627 /* 2628 * Step 3: Remove any vestiges of the xfer from the hardware. 2629 * The complication here is that the hardware may have executed 2630 * beyond the xfer we're trying to abort. So as we're scanning 2631 * the TDs of this xfer we check if the hardware points to 2632 * any of them. 2633 */ 2634 s = splusb(); /* XXX why? */ 2635 2636 usb_syncmem(&sqh->dma, 2637 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2638 sizeof(sqh->qh.qh_curqtd), 2639 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2640 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2641 hit = 0; 2642 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2643 hit |= cur == sqtd->physaddr; 2644 if (sqtd == exfer->sqtdend) 2645 break; 2646 } 2647 sqtd = sqtd->nextqtd; 2648 /* Zap curqtd register if hardware pointed inside the xfer. */ 2649 if (hit && sqtd != NULL) { 2650 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2651 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2652 usb_syncmem(&sqh->dma, 2653 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2654 sizeof(sqh->qh.qh_curqtd), 2655 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2656 sqh->qh.qh_qtd.qtd_status = qhstatus; 2657 usb_syncmem(&sqh->dma, 2658 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2659 sizeof(sqh->qh.qh_qtd.qtd_status), 2660 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2661 } else { 2662 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2663 } 2664 2665 /* 2666 * Step 4: Execute callback. 2667 */ 2668 #ifdef DIAGNOSTIC 2669 exfer->isdone = 1; 2670 #endif 2671 wake = xfer->hcflags & UXFER_ABORTWAIT; 2672 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2673 usb_transfer_complete(xfer); 2674 if (wake) 2675 wakeup(&xfer->hcflags); 2676 2677 splx(s); 2678 #undef exfer 2679 } 2680 2681 void 2682 ehci_timeout(void *addr) 2683 { 2684 struct ehci_xfer *exfer = addr; 2685 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2686 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2687 2688 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2689 #ifdef USB_DEBUG 2690 if (ehcidebug > 1) 2691 usbd_dump_pipe(exfer->xfer.pipe); 2692 #endif 2693 2694 if (sc->sc_dying) { 2695 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2696 return; 2697 } 2698 2699 /* Execute the abort in a process context. */ 2700 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 2701 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 2702 } 2703 2704 void 2705 ehci_timeout_task(void *addr) 2706 { 2707 usbd_xfer_handle xfer = addr; 2708 int s; 2709 2710 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 2711 2712 s = splusb(); 2713 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2714 splx(s); 2715 } 2716 2717 /************************/ 2718 2719 Static usbd_status 2720 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 2721 { 2722 usbd_status err; 2723 2724 /* Insert last in queue. */ 2725 err = usb_insert_transfer(xfer); 2726 if (err) 2727 return (err); 2728 2729 /* Pipe isn't running, start first */ 2730 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2731 } 2732 2733 Static usbd_status 2734 ehci_device_ctrl_start(usbd_xfer_handle xfer) 2735 { 2736 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2737 usbd_status err; 2738 2739 if (sc->sc_dying) 2740 return (USBD_IOERROR); 2741 2742 #ifdef DIAGNOSTIC 2743 if (!(xfer->rqflags & URQ_REQUEST)) { 2744 /* XXX panic */ 2745 printf("ehci_device_ctrl_transfer: not a request\n"); 2746 return (USBD_INVAL); 2747 } 2748 #endif 2749 2750 err = ehci_device_request(xfer); 2751 if (err) 2752 return (err); 2753 2754 if (sc->sc_bus.use_polling) 2755 ehci_waitintr(sc, xfer); 2756 return (USBD_IN_PROGRESS); 2757 } 2758 2759 void 2760 ehci_device_ctrl_done(usbd_xfer_handle xfer) 2761 { 2762 struct ehci_xfer *ex = EXFER(xfer); 2763 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2764 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2765 usb_device_request_t *req = &xfer->request; 2766 int len = UGETW(req->wLength); 2767 int rd = req->bmRequestType & UT_READ; 2768 2769 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 2770 2771 #ifdef DIAGNOSTIC 2772 if (!(xfer->rqflags & URQ_REQUEST)) { 2773 panic("ehci_ctrl_done: not a request"); 2774 } 2775 #endif 2776 2777 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 2778 ehci_del_intr_list(ex); /* remove from active list */ 2779 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 2780 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 2781 BUS_DMASYNC_POSTWRITE); 2782 if (len) 2783 usb_syncmem(&xfer->dmabuf, 0, len, 2784 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2785 } 2786 2787 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 2788 } 2789 2790 /* Abort a device control request. */ 2791 Static void 2792 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 2793 { 2794 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 2795 ehci_abort_xfer(xfer, USBD_CANCELLED); 2796 } 2797 2798 /* Close a device control pipe. */ 2799 Static void 2800 ehci_device_ctrl_close(usbd_pipe_handle pipe) 2801 { 2802 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2803 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 2804 2805 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 2806 ehci_close_pipe(pipe, sc->sc_async_head); 2807 } 2808 2809 usbd_status 2810 ehci_device_request(usbd_xfer_handle xfer) 2811 { 2812 #define exfer EXFER(xfer) 2813 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2814 usb_device_request_t *req = &xfer->request; 2815 usbd_device_handle dev = epipe->pipe.device; 2816 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 2817 int addr = dev->address; 2818 ehci_soft_qtd_t *setup, *stat, *next; 2819 ehci_soft_qh_t *sqh; 2820 int isread; 2821 int len; 2822 usbd_status err; 2823 int s; 2824 2825 isread = req->bmRequestType & UT_READ; 2826 len = UGETW(req->wLength); 2827 2828 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 2829 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2830 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2831 UGETW(req->wIndex), len, addr, 2832 epipe->pipe.endpoint->edesc->bEndpointAddress)); 2833 2834 setup = ehci_alloc_sqtd(sc); 2835 if (setup == NULL) { 2836 err = USBD_NOMEM; 2837 goto bad1; 2838 } 2839 stat = ehci_alloc_sqtd(sc); 2840 if (stat == NULL) { 2841 err = USBD_NOMEM; 2842 goto bad2; 2843 } 2844 2845 sqh = epipe->sqh; 2846 epipe->u.ctl.length = len; 2847 2848 /* Update device address and length since they may have changed 2849 during the setup of the control pipe in usbd_new_device(). */ 2850 /* XXX This only needs to be done once, but it's too early in open. */ 2851 /* XXXX Should not touch ED here! */ 2852 sqh->qh.qh_endp = 2853 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 2854 htole32( 2855 EHCI_QH_SET_ADDR(addr) | 2856 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 2857 ); 2858 2859 /* Set up data transaction */ 2860 if (len != 0) { 2861 ehci_soft_qtd_t *end; 2862 2863 /* Start toggle at 1. */ 2864 epipe->nexttoggle = 1; 2865 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 2866 &next, &end); 2867 if (err) 2868 goto bad3; 2869 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 2870 end->nextqtd = stat; 2871 end->qtd.qtd_next = 2872 end->qtd.qtd_altnext = htole32(stat->physaddr); 2873 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 2874 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2875 } else { 2876 next = stat; 2877 } 2878 2879 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 2880 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2881 2882 /* Clear toggle */ 2883 setup->qtd.qtd_status = htole32( 2884 EHCI_QTD_ACTIVE | 2885 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2886 EHCI_QTD_SET_CERR(3) | 2887 EHCI_QTD_SET_TOGGLE(0) | 2888 EHCI_QTD_SET_BYTES(sizeof *req) 2889 ); 2890 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2891 setup->qtd.qtd_buffer_hi[0] = 0; 2892 setup->nextqtd = next; 2893 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2894 setup->xfer = xfer; 2895 setup->len = sizeof *req; 2896 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 2897 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2898 2899 stat->qtd.qtd_status = htole32( 2900 EHCI_QTD_ACTIVE | 2901 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2902 EHCI_QTD_SET_CERR(3) | 2903 EHCI_QTD_SET_TOGGLE(1) | 2904 EHCI_QTD_IOC 2905 ); 2906 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2907 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 2908 stat->nextqtd = NULL; 2909 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 2910 stat->xfer = xfer; 2911 stat->len = 0; 2912 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 2913 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2914 2915 #ifdef EHCI_DEBUG 2916 if (ehcidebug > 5) { 2917 DPRINTF(("ehci_device_request:\n")); 2918 ehci_dump_sqh(sqh); 2919 ehci_dump_sqtds(setup); 2920 } 2921 #endif 2922 2923 exfer->sqtdstart = setup; 2924 exfer->sqtdend = stat; 2925 #ifdef DIAGNOSTIC 2926 if (!exfer->isdone) { 2927 printf("ehci_device_request: not done, exfer=%p\n", exfer); 2928 } 2929 exfer->isdone = 0; 2930 #endif 2931 2932 /* Insert qTD in QH list. */ 2933 s = splusb(); 2934 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 2935 if (xfer->timeout && !sc->sc_bus.use_polling) { 2936 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2937 ehci_timeout, xfer); 2938 } 2939 ehci_add_intr_list(sc, exfer); 2940 xfer->status = USBD_IN_PROGRESS; 2941 splx(s); 2942 2943 #ifdef EHCI_DEBUG 2944 if (ehcidebug > 10) { 2945 DPRINTF(("ehci_device_request: status=%x\n", 2946 EOREAD4(sc, EHCI_USBSTS))); 2947 delay(10000); 2948 ehci_dump_regs(sc); 2949 ehci_dump_sqh(sc->sc_async_head); 2950 ehci_dump_sqh(sqh); 2951 ehci_dump_sqtds(setup); 2952 } 2953 #endif 2954 2955 return (USBD_NORMAL_COMPLETION); 2956 2957 bad3: 2958 ehci_free_sqtd(sc, stat); 2959 bad2: 2960 ehci_free_sqtd(sc, setup); 2961 bad1: 2962 DPRINTFN(-1,("ehci_device_request: no memory\n")); 2963 xfer->status = err; 2964 usb_transfer_complete(xfer); 2965 return (err); 2966 #undef exfer 2967 } 2968 2969 /* 2970 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 2971 * qTD status, or miss signalling occasionally under heavy load. If the host 2972 * machine is too fast, we we can miss transaction completion - when we scan 2973 * the active list the transaction still seems to be active. This generally 2974 * exhibits itself as a umass stall that never recovers. 2975 * 2976 * We work around this behaviour by setting up this callback after any softintr 2977 * that completes with transactions still pending, giving us another chance to 2978 * check for completion after the writeback has taken place. 2979 */ 2980 void 2981 ehci_intrlist_timeout(void *arg) 2982 { 2983 ehci_softc_t *sc = arg; 2984 int s = splusb(); 2985 2986 DPRINTF(("ehci_intrlist_timeout\n")); 2987 usb_schedsoftintr(&sc->sc_bus); 2988 2989 splx(s); 2990 } 2991 2992 /************************/ 2993 2994 Static usbd_status 2995 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 2996 { 2997 usbd_status err; 2998 2999 /* Insert last in queue. */ 3000 err = usb_insert_transfer(xfer); 3001 if (err) 3002 return (err); 3003 3004 /* Pipe isn't running, start first */ 3005 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3006 } 3007 3008 usbd_status 3009 ehci_device_bulk_start(usbd_xfer_handle xfer) 3010 { 3011 #define exfer EXFER(xfer) 3012 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3013 usbd_device_handle dev = epipe->pipe.device; 3014 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3015 ehci_soft_qtd_t *data, *dataend; 3016 ehci_soft_qh_t *sqh; 3017 usbd_status err; 3018 int len, isread, endpt; 3019 int s; 3020 3021 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3022 xfer, xfer->length, xfer->flags)); 3023 3024 if (sc->sc_dying) 3025 return (USBD_IOERROR); 3026 3027 #ifdef DIAGNOSTIC 3028 if (xfer->rqflags & URQ_REQUEST) 3029 panic("ehci_device_bulk_start: a request"); 3030 #endif 3031 3032 len = xfer->length; 3033 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3034 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3035 sqh = epipe->sqh; 3036 3037 epipe->u.bulk.length = len; 3038 3039 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3040 &dataend); 3041 if (err) { 3042 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3043 xfer->status = err; 3044 usb_transfer_complete(xfer); 3045 return (err); 3046 } 3047 3048 #ifdef EHCI_DEBUG 3049 if (ehcidebug > 5) { 3050 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3051 ehci_dump_sqh(sqh); 3052 ehci_dump_sqtds(data); 3053 } 3054 #endif 3055 3056 /* Set up interrupt info. */ 3057 exfer->sqtdstart = data; 3058 exfer->sqtdend = dataend; 3059 #ifdef DIAGNOSTIC 3060 if (!exfer->isdone) { 3061 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3062 } 3063 exfer->isdone = 0; 3064 #endif 3065 3066 s = splusb(); 3067 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3068 if (xfer->timeout && !sc->sc_bus.use_polling) { 3069 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3070 ehci_timeout, xfer); 3071 } 3072 ehci_add_intr_list(sc, exfer); 3073 xfer->status = USBD_IN_PROGRESS; 3074 splx(s); 3075 3076 #ifdef EHCI_DEBUG 3077 if (ehcidebug > 10) { 3078 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3079 delay(10000); 3080 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3081 ehci_dump_regs(sc); 3082 #if 0 3083 printf("async_head:\n"); 3084 ehci_dump_sqh(sc->sc_async_head); 3085 #endif 3086 printf("sqh:\n"); 3087 ehci_dump_sqh(sqh); 3088 ehci_dump_sqtds(data); 3089 } 3090 #endif 3091 3092 if (sc->sc_bus.use_polling) 3093 ehci_waitintr(sc, xfer); 3094 3095 return (USBD_IN_PROGRESS); 3096 #undef exfer 3097 } 3098 3099 Static void 3100 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3101 { 3102 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3103 ehci_abort_xfer(xfer, USBD_CANCELLED); 3104 } 3105 3106 /* 3107 * Close a device bulk pipe. 3108 */ 3109 Static void 3110 ehci_device_bulk_close(usbd_pipe_handle pipe) 3111 { 3112 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3113 3114 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3115 ehci_close_pipe(pipe, sc->sc_async_head); 3116 } 3117 3118 void 3119 ehci_device_bulk_done(usbd_xfer_handle xfer) 3120 { 3121 struct ehci_xfer *ex = EXFER(xfer); 3122 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3123 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3124 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3125 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3126 3127 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3128 xfer, xfer->actlen)); 3129 3130 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3131 ehci_del_intr_list(ex); /* remove from active list */ 3132 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3133 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3134 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3135 } 3136 3137 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3138 } 3139 3140 /************************/ 3141 3142 Static usbd_status 3143 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3144 { 3145 struct ehci_soft_islot *isp; 3146 int islot, lev; 3147 3148 /* Find a poll rate that is large enough. */ 3149 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3150 if (EHCI_ILEV_IVAL(lev) <= ival) 3151 break; 3152 3153 /* Pick an interrupt slot at the right level. */ 3154 /* XXX could do better than picking at random */ 3155 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3156 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3157 3158 sqh->islot = islot; 3159 isp = &sc->sc_islots[islot]; 3160 ehci_add_qh(sqh, isp->sqh); 3161 3162 return (USBD_NORMAL_COMPLETION); 3163 } 3164 3165 Static usbd_status 3166 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3167 { 3168 usbd_status err; 3169 3170 /* Insert last in queue. */ 3171 err = usb_insert_transfer(xfer); 3172 if (err) 3173 return (err); 3174 3175 /* 3176 * Pipe isn't running (otherwise err would be USBD_INPROG), 3177 * so start it first. 3178 */ 3179 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3180 } 3181 3182 Static usbd_status 3183 ehci_device_intr_start(usbd_xfer_handle xfer) 3184 { 3185 #define exfer EXFER(xfer) 3186 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3187 usbd_device_handle dev = xfer->pipe->device; 3188 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3189 ehci_soft_qtd_t *data, *dataend; 3190 ehci_soft_qh_t *sqh; 3191 usbd_status err; 3192 int len, isread, endpt; 3193 int s; 3194 3195 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3196 xfer, xfer->length, xfer->flags)); 3197 3198 if (sc->sc_dying) 3199 return (USBD_IOERROR); 3200 3201 #ifdef DIAGNOSTIC 3202 if (xfer->rqflags & URQ_REQUEST) 3203 panic("ehci_device_intr_start: a request"); 3204 #endif 3205 3206 len = xfer->length; 3207 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3208 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3209 sqh = epipe->sqh; 3210 3211 epipe->u.intr.length = len; 3212 3213 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3214 &dataend); 3215 if (err) { 3216 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3217 xfer->status = err; 3218 usb_transfer_complete(xfer); 3219 return (err); 3220 } 3221 3222 #ifdef EHCI_DEBUG 3223 if (ehcidebug > 5) { 3224 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3225 ehci_dump_sqh(sqh); 3226 ehci_dump_sqtds(data); 3227 } 3228 #endif 3229 3230 /* Set up interrupt info. */ 3231 exfer->sqtdstart = data; 3232 exfer->sqtdend = dataend; 3233 #ifdef DIAGNOSTIC 3234 if (!exfer->isdone) { 3235 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3236 } 3237 exfer->isdone = 0; 3238 #endif 3239 3240 s = splusb(); 3241 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3242 if (xfer->timeout && !sc->sc_bus.use_polling) { 3243 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3244 ehci_timeout, xfer); 3245 } 3246 ehci_add_intr_list(sc, exfer); 3247 xfer->status = USBD_IN_PROGRESS; 3248 splx(s); 3249 3250 #ifdef EHCI_DEBUG 3251 if (ehcidebug > 10) { 3252 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3253 delay(10000); 3254 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3255 ehci_dump_regs(sc); 3256 printf("sqh:\n"); 3257 ehci_dump_sqh(sqh); 3258 ehci_dump_sqtds(data); 3259 } 3260 #endif 3261 3262 if (sc->sc_bus.use_polling) 3263 ehci_waitintr(sc, xfer); 3264 3265 return (USBD_IN_PROGRESS); 3266 #undef exfer 3267 } 3268 3269 Static void 3270 ehci_device_intr_abort(usbd_xfer_handle xfer) 3271 { 3272 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3273 if (xfer->pipe->intrxfer == xfer) { 3274 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3275 xfer->pipe->intrxfer = NULL; 3276 } 3277 ehci_abort_xfer(xfer, USBD_CANCELLED); 3278 } 3279 3280 Static void 3281 ehci_device_intr_close(usbd_pipe_handle pipe) 3282 { 3283 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3284 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3285 struct ehci_soft_islot *isp; 3286 3287 isp = &sc->sc_islots[epipe->sqh->islot]; 3288 ehci_close_pipe(pipe, isp->sqh); 3289 } 3290 3291 Static void 3292 ehci_device_intr_done(usbd_xfer_handle xfer) 3293 { 3294 #define exfer EXFER(xfer) 3295 struct ehci_xfer *ex = EXFER(xfer); 3296 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3297 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3298 ehci_soft_qtd_t *data, *dataend; 3299 ehci_soft_qh_t *sqh; 3300 usbd_status err; 3301 int len, isread, endpt, s; 3302 3303 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3304 xfer, xfer->actlen)); 3305 3306 if (xfer->pipe->repeat) { 3307 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3308 3309 len = epipe->u.intr.length; 3310 xfer->length = len; 3311 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3312 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3313 usb_syncmem(&xfer->dmabuf, 0, len, 3314 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3315 sqh = epipe->sqh; 3316 3317 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3318 &data, &dataend); 3319 if (err) { 3320 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3321 xfer->status = err; 3322 return; 3323 } 3324 3325 /* Set up interrupt info. */ 3326 exfer->sqtdstart = data; 3327 exfer->sqtdend = dataend; 3328 #ifdef DIAGNOSTIC 3329 if (!exfer->isdone) { 3330 printf("ehci_device_intr_done: not done, ex=%p\n", 3331 exfer); 3332 } 3333 exfer->isdone = 0; 3334 #endif 3335 3336 s = splusb(); 3337 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3338 if (xfer->timeout && !sc->sc_bus.use_polling) { 3339 usb_callout(xfer->timeout_handle, 3340 mstohz(xfer->timeout), ehci_timeout, xfer); 3341 } 3342 splx(s); 3343 3344 xfer->status = USBD_IN_PROGRESS; 3345 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3346 ehci_del_intr_list(ex); /* remove from active list */ 3347 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3348 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3349 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3350 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3351 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3352 } 3353 #undef exfer 3354 } 3355 3356 /************************/ 3357 3358 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; } 3359 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle xfer) { return USBD_IOERROR; } 3360 Static void ehci_device_isoc_abort(usbd_xfer_handle xfer) { } 3361 Static void ehci_device_isoc_close(usbd_pipe_handle pipe) { } 3362 Static void ehci_device_isoc_done(usbd_xfer_handle xfer) { } 3363
Indexes created Thu Oct 02 01:09:59 GMT 2025