ehci.c revision 1.91.2.9
1 /* $NetBSD: ehci.c,v 1.91.2.9 2006/08/11 04:22:21 riz Exp $ */ 2 3 /* 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 41 * 42 * The EHCI 1.0 spec can be found at 43 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 44 * and the USB 2.0 spec at 45 * http://www.usb.org/developers/docs/usb_20.zip 46 * 47 */ 48 49 /* 50 * TODO: 51 * 1) hold off explorations by companion controllers until ehci has started. 52 * 53 * 2) The EHCI driver lacks support for interrupt isochronous transfers, so 54 * devices using them don't work. 55 * Interrupt transfers are not difficult, it's just not done. 56 * 57 * 3) The meaty part to implement is the support for USB 2.0 hubs. 58 * They are quite complicated since the need to be able to do 59 * "transaction translation", i.e., converting to/from USB 2 and USB 1. 60 * So the hub driver needs to handle and schedule these things, to 61 * assign place in frame where different devices get to go. See chapter 62 * on hubs in USB 2.0 for details. 63 * 64 * 4) command failures are not recovered correctly 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.91.2.9 2006/08/11 04:22:21 riz Exp $"); 69 70 #include "ohci.h" 71 #include "uhci.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/select.h> 79 #include <sys/proc.h> 80 #include <sys/queue.h> 81 82 #include <machine/bus.h> 83 #include <machine/endian.h> 84 85 #include <dev/usb/usb.h> 86 #include <dev/usb/usbdi.h> 87 #include <dev/usb/usbdivar.h> 88 #include <dev/usb/usb_mem.h> 89 #include <dev/usb/usb_quirks.h> 90 91 #include <dev/usb/ehcireg.h> 92 #include <dev/usb/ehcivar.h> 93 94 #ifdef EHCI_DEBUG 95 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 96 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 97 int ehcidebug = 0; 98 #ifndef __NetBSD__ 99 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 100 #endif 101 #else 102 #define DPRINTF(x) 103 #define DPRINTFN(n,x) 104 #endif 105 106 struct ehci_pipe { 107 struct usbd_pipe pipe; 108 int nexttoggle; 109 110 ehci_soft_qh_t *sqh; 111 union { 112 ehci_soft_qtd_t *qtd; 113 /* ehci_soft_itd_t *itd; */ 114 } tail; 115 union { 116 /* Control pipe */ 117 struct { 118 usb_dma_t reqdma; 119 u_int length; 120 /*ehci_soft_qtd_t *setup, *data, *stat;*/ 121 } ctl; 122 /* Interrupt pipe */ 123 struct { 124 u_int length; 125 } intr; 126 /* Bulk pipe */ 127 struct { 128 u_int length; 129 } bulk; 130 /* Iso pipe */ 131 /* XXX */ 132 } u; 133 }; 134 135 Static void ehci_shutdown(void *); 136 Static void ehci_power(int, void *); 137 138 Static usbd_status ehci_open(usbd_pipe_handle); 139 Static void ehci_poll(struct usbd_bus *); 140 Static void ehci_softintr(void *); 141 Static int ehci_intr1(ehci_softc_t *); 142 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 143 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 144 Static void ehci_idone(struct ehci_xfer *); 145 Static void ehci_timeout(void *); 146 Static void ehci_timeout_task(void *); 147 Static void ehci_intrlist_timeout(void *); 148 149 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 150 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 151 152 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 153 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 154 155 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 156 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 157 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 158 Static void ehci_root_ctrl_close(usbd_pipe_handle); 159 Static void ehci_root_ctrl_done(usbd_xfer_handle); 160 161 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 162 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 163 Static void ehci_root_intr_abort(usbd_xfer_handle); 164 Static void ehci_root_intr_close(usbd_pipe_handle); 165 Static void ehci_root_intr_done(usbd_xfer_handle); 166 167 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 168 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 169 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 170 Static void ehci_device_ctrl_close(usbd_pipe_handle); 171 Static void ehci_device_ctrl_done(usbd_xfer_handle); 172 173 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 174 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 175 Static void ehci_device_bulk_abort(usbd_xfer_handle); 176 Static void ehci_device_bulk_close(usbd_pipe_handle); 177 Static void ehci_device_bulk_done(usbd_xfer_handle); 178 179 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 181 Static void ehci_device_intr_abort(usbd_xfer_handle); 182 Static void ehci_device_intr_close(usbd_pipe_handle); 183 Static void ehci_device_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 187 Static void ehci_device_isoc_abort(usbd_xfer_handle); 188 Static void ehci_device_isoc_close(usbd_pipe_handle); 189 Static void ehci_device_isoc_done(usbd_xfer_handle); 190 191 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 192 Static void ehci_noop(usbd_pipe_handle pipe); 193 194 Static int ehci_str(usb_string_descriptor_t *, int, char *); 195 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 196 Static void ehci_pcd_able(ehci_softc_t *, int); 197 Static void ehci_pcd_enable(void *); 198 Static void ehci_disown(ehci_softc_t *, int, int); 199 200 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 201 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 202 203 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 204 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 205 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 206 ehci_softc_t *, int, int, usbd_xfer_handle, 207 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 208 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 209 ehci_soft_qtd_t *); 210 211 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 212 213 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 214 int ival); 215 216 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 217 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 218 ehci_soft_qh_t *); 219 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 220 Static void ehci_sync_hc(ehci_softc_t *); 221 222 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 223 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 224 225 #ifdef EHCI_DEBUG 226 Static void ehci_dump_regs(ehci_softc_t *); 227 Static void ehci_dump(void); 228 Static ehci_softc_t *theehci; 229 Static void ehci_dump_link(ehci_link_t, int); 230 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 231 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 232 Static void ehci_dump_qtd(ehci_qtd_t *); 233 Static void ehci_dump_sqh(ehci_soft_qh_t *); 234 #ifdef DIAGNOSTIC 235 Static void ehci_dump_exfer(struct ehci_xfer *); 236 #endif 237 #endif 238 239 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 240 241 #define EHCI_INTR_ENDPT 1 242 243 #define ehci_add_intr_list(sc, ex) \ 244 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 245 #define ehci_del_intr_list(ex) \ 246 do { \ 247 LIST_REMOVE((ex), inext); \ 248 (ex)->inext.le_prev = NULL; \ 249 } while (0) 250 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 251 252 Static struct usbd_bus_methods ehci_bus_methods = { 253 ehci_open, 254 ehci_softintr, 255 ehci_poll, 256 ehci_allocm, 257 ehci_freem, 258 ehci_allocx, 259 ehci_freex, 260 }; 261 262 Static struct usbd_pipe_methods ehci_root_ctrl_methods = { 263 ehci_root_ctrl_transfer, 264 ehci_root_ctrl_start, 265 ehci_root_ctrl_abort, 266 ehci_root_ctrl_close, 267 ehci_noop, 268 ehci_root_ctrl_done, 269 }; 270 271 Static struct usbd_pipe_methods ehci_root_intr_methods = { 272 ehci_root_intr_transfer, 273 ehci_root_intr_start, 274 ehci_root_intr_abort, 275 ehci_root_intr_close, 276 ehci_noop, 277 ehci_root_intr_done, 278 }; 279 280 Static struct usbd_pipe_methods ehci_device_ctrl_methods = { 281 ehci_device_ctrl_transfer, 282 ehci_device_ctrl_start, 283 ehci_device_ctrl_abort, 284 ehci_device_ctrl_close, 285 ehci_noop, 286 ehci_device_ctrl_done, 287 }; 288 289 Static struct usbd_pipe_methods ehci_device_intr_methods = { 290 ehci_device_intr_transfer, 291 ehci_device_intr_start, 292 ehci_device_intr_abort, 293 ehci_device_intr_close, 294 ehci_device_clear_toggle, 295 ehci_device_intr_done, 296 }; 297 298 Static struct usbd_pipe_methods ehci_device_bulk_methods = { 299 ehci_device_bulk_transfer, 300 ehci_device_bulk_start, 301 ehci_device_bulk_abort, 302 ehci_device_bulk_close, 303 ehci_device_clear_toggle, 304 ehci_device_bulk_done, 305 }; 306 307 Static struct usbd_pipe_methods ehci_device_isoc_methods = { 308 ehci_device_isoc_transfer, 309 ehci_device_isoc_start, 310 ehci_device_isoc_abort, 311 ehci_device_isoc_close, 312 ehci_noop, 313 ehci_device_isoc_done, 314 }; 315 316 static uint8_t revbits[EHCI_MAX_POLLRATE] = { 317 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 318 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 319 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 320 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 321 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 322 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 323 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 324 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 325 }; 326 327 usbd_status 328 ehci_init(ehci_softc_t *sc) 329 { 330 u_int32_t version, sparams, cparams, hcr; 331 u_int i; 332 usbd_status err; 333 ehci_soft_qh_t *sqh; 334 u_int ncomp; 335 336 DPRINTF(("ehci_init: start\n")); 337 #ifdef EHCI_DEBUG 338 theehci = sc; 339 #endif 340 341 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 342 343 version = EREAD2(sc, EHCI_HCIVERSION); 344 aprint_normal("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 345 version >> 8, version & 0xff); 346 347 sparams = EREAD4(sc, EHCI_HCSPARAMS); 348 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 349 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 350 ncomp = EHCI_HCS_N_CC(sparams); 351 if (ncomp != sc->sc_ncomp) { 352 aprint_error("%s: wrong number of companions (%d != %d)\n", 353 USBDEVNAME(sc->sc_bus.bdev), 354 ncomp, sc->sc_ncomp); 355 #if NOHCI == 0 || NUHCI == 0 356 aprint_error("%s: ohci or uhci probably not configured\n", 357 USBDEVNAME(sc->sc_bus.bdev)); 358 #endif 359 if (ncomp < sc->sc_ncomp) 360 sc->sc_ncomp = ncomp; 361 } 362 if (sc->sc_ncomp > 0) { 363 aprint_normal("%s: companion controller%s, %d port%s each:", 364 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 365 EHCI_HCS_N_PCC(sparams), 366 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 367 for (i = 0; i < sc->sc_ncomp; i++) 368 aprint_normal(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 369 aprint_normal("\n"); 370 } 371 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 372 cparams = EREAD4(sc, EHCI_HCCPARAMS); 373 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 374 375 if (EHCI_HCC_64BIT(cparams)) { 376 /* MUST clear segment register if 64 bit capable. */ 377 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 378 } 379 380 sc->sc_bus.usbrev = USBREV_2_0; 381 382 usb_setup_reserve(sc, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 383 USB_MEM_RESERVE); 384 385 /* Reset the controller */ 386 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 387 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 388 usb_delay_ms(&sc->sc_bus, 1); 389 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 390 for (i = 0; i < 100; i++) { 391 usb_delay_ms(&sc->sc_bus, 1); 392 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 393 if (!hcr) 394 break; 395 } 396 if (hcr) { 397 aprint_error("%s: reset timeout\n", 398 USBDEVNAME(sc->sc_bus.bdev)); 399 return (USBD_IOERROR); 400 } 401 402 /* XXX need proper intr scheduling */ 403 sc->sc_rand = 96; 404 405 /* frame list size at default, read back what we got and use that */ 406 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 407 case 0: sc->sc_flsize = 1024; break; 408 case 1: sc->sc_flsize = 512; break; 409 case 2: sc->sc_flsize = 256; break; 410 case 3: return (USBD_IOERROR); 411 } 412 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 413 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 414 if (err) 415 return (err); 416 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 417 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 418 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 419 420 /* Set up the bus struct. */ 421 sc->sc_bus.methods = &ehci_bus_methods; 422 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 423 424 sc->sc_powerhook = powerhook_establish(ehci_power, sc); 425 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 426 427 sc->sc_eintrs = EHCI_NORMAL_INTRS; 428 429 /* 430 * Allocate the interrupt dummy QHs. These are arranged to give poll 431 * intervals that are powers of 2 times 1ms. 432 */ 433 for (i = 0; i < EHCI_INTRQHS; i++) { 434 sqh = ehci_alloc_sqh(sc); 435 if (sqh == NULL) { 436 err = USBD_NOMEM; 437 goto bad1; 438 } 439 sc->sc_islots[i].sqh = sqh; 440 } 441 for (i = 0; i < EHCI_INTRQHS; i++) { 442 sqh = sc->sc_islots[i].sqh; 443 if (i == 0) { 444 /* The last (1ms) QH terminates. */ 445 sqh->qh.qh_link = EHCI_NULL; 446 sqh->next = NULL; 447 } else { 448 /* Otherwise the next QH has half the poll interval */ 449 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 450 sqh->qh.qh_link = htole32(sqh->next->physaddr | 451 EHCI_LINK_QH); 452 } 453 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 454 sqh->qh.qh_curqtd = EHCI_NULL; 455 sqh->next = NULL; 456 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 457 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 458 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 459 sqh->sqtd = NULL; 460 } 461 /* Point the frame list at the last level (128ms). */ 462 for (i = 0; i < sc->sc_flsize; i++) { 463 int j; 464 465 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 466 revbits[i & (EHCI_MAX_POLLRATE-1)]; 467 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 468 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 469 i)].sqh->physaddr); 470 } 471 472 /* Allocate dummy QH that starts the async list. */ 473 sqh = ehci_alloc_sqh(sc); 474 if (sqh == NULL) { 475 err = USBD_NOMEM; 476 goto bad1; 477 } 478 /* Fill the QH */ 479 sqh->qh.qh_endp = 480 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 481 sqh->qh.qh_link = 482 htole32(sqh->physaddr | EHCI_LINK_QH); 483 sqh->qh.qh_curqtd = EHCI_NULL; 484 sqh->next = NULL; 485 /* Fill the overlay qTD */ 486 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 487 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 488 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 489 sqh->sqtd = NULL; 490 #ifdef EHCI_DEBUG 491 if (ehcidebug) { 492 ehci_dump_sqh(sqh); 493 } 494 #endif 495 496 /* Point to async list */ 497 sc->sc_async_head = sqh; 498 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 499 500 usb_callout_init(sc->sc_tmo_pcd); 501 usb_callout_init(sc->sc_tmo_intrlist); 502 503 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 504 505 /* Enable interrupts */ 506 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 507 508 /* Turn on controller */ 509 EOWRITE4(sc, EHCI_USBCMD, 510 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 511 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 512 EHCI_CMD_ASE | 513 EHCI_CMD_PSE | 514 EHCI_CMD_RS); 515 516 /* Take over port ownership */ 517 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 518 519 for (i = 0; i < 100; i++) { 520 usb_delay_ms(&sc->sc_bus, 1); 521 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 522 if (!hcr) 523 break; 524 } 525 if (hcr) { 526 aprint_error("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 527 return (USBD_IOERROR); 528 } 529 530 return (USBD_NORMAL_COMPLETION); 531 532 #if 0 533 bad2: 534 ehci_free_sqh(sc, sc->sc_async_head); 535 #endif 536 bad1: 537 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 538 return (err); 539 } 540 541 int 542 ehci_intr(void *v) 543 { 544 ehci_softc_t *sc = v; 545 546 if (sc == NULL || sc->sc_dying) 547 return (0); 548 549 /* If we get an interrupt while polling, then just ignore it. */ 550 if (sc->sc_bus.use_polling) { 551 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 552 553 if (intrs) 554 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 555 #ifdef DIAGNOSTIC 556 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 557 #endif 558 return (0); 559 } 560 561 return (ehci_intr1(sc)); 562 } 563 564 Static int 565 ehci_intr1(ehci_softc_t *sc) 566 { 567 u_int32_t intrs, eintrs; 568 569 DPRINTFN(20,("ehci_intr1: enter\n")); 570 571 /* In case the interrupt occurs before initialization has completed. */ 572 if (sc == NULL) { 573 #ifdef DIAGNOSTIC 574 printf("ehci_intr1: sc == NULL\n"); 575 #endif 576 return (0); 577 } 578 579 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 580 if (!intrs) 581 return (0); 582 583 eintrs = intrs & sc->sc_eintrs; 584 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 585 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 586 (u_int)eintrs)); 587 if (!eintrs) 588 return (0); 589 590 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 591 sc->sc_bus.intr_context++; 592 sc->sc_bus.no_intrs++; 593 if (eintrs & EHCI_STS_IAA) { 594 DPRINTF(("ehci_intr1: door bell\n")); 595 wakeup(&sc->sc_async_head); 596 eintrs &= ~EHCI_STS_IAA; 597 } 598 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 599 DPRINTFN(5,("ehci_intr1: %s %s\n", 600 eintrs & EHCI_STS_INT ? "INT" : "", 601 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 602 usb_schedsoftintr(&sc->sc_bus); 603 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 604 } 605 if (eintrs & EHCI_STS_HSE) { 606 printf("%s: unrecoverable error, controller halted\n", 607 USBDEVNAME(sc->sc_bus.bdev)); 608 /* XXX what else */ 609 } 610 if (eintrs & EHCI_STS_PCD) { 611 ehci_pcd(sc, sc->sc_intrxfer); 612 /* 613 * Disable PCD interrupt for now, because it will be 614 * on until the port has been reset. 615 */ 616 ehci_pcd_able(sc, 0); 617 /* Do not allow RHSC interrupts > 1 per second */ 618 usb_callout(sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc); 619 eintrs &= ~EHCI_STS_PCD; 620 } 621 622 sc->sc_bus.intr_context--; 623 624 if (eintrs != 0) { 625 /* Block unprocessed interrupts. */ 626 sc->sc_eintrs &= ~eintrs; 627 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 628 printf("%s: blocking intrs 0x%x\n", 629 USBDEVNAME(sc->sc_bus.bdev), eintrs); 630 } 631 632 return (1); 633 } 634 635 void 636 ehci_pcd_able(ehci_softc_t *sc, int on) 637 { 638 DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on)); 639 if (on) 640 sc->sc_eintrs |= EHCI_STS_PCD; 641 else 642 sc->sc_eintrs &= ~EHCI_STS_PCD; 643 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 644 } 645 646 void 647 ehci_pcd_enable(void *v_sc) 648 { 649 ehci_softc_t *sc = v_sc; 650 651 ehci_pcd_able(sc, 1); 652 } 653 654 void 655 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 656 { 657 usbd_pipe_handle pipe; 658 u_char *p; 659 int i, m; 660 661 if (xfer == NULL) { 662 /* Just ignore the change. */ 663 return; 664 } 665 666 pipe = xfer->pipe; 667 668 p = KERNADDR(&xfer->dmabuf, 0); 669 m = min(sc->sc_noport, xfer->length * 8 - 1); 670 memset(p, 0, xfer->length); 671 for (i = 1; i <= m; i++) { 672 /* Pick out CHANGE bits from the status reg. */ 673 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 674 p[i/8] |= 1 << (i%8); 675 } 676 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 677 xfer->actlen = xfer->length; 678 xfer->status = USBD_NORMAL_COMPLETION; 679 680 usb_transfer_complete(xfer); 681 } 682 683 void 684 ehci_softintr(void *v) 685 { 686 ehci_softc_t *sc = v; 687 struct ehci_xfer *ex, *nextex; 688 689 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 690 sc->sc_bus.intr_context)); 691 692 sc->sc_bus.intr_context++; 693 694 /* 695 * The only explanation I can think of for why EHCI is as brain dead 696 * as UHCI interrupt-wise is that Intel was involved in both. 697 * An interrupt just tells us that something is done, we have no 698 * clue what, so we need to scan through all active transfers. :-( 699 */ 700 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 701 nextex = LIST_NEXT(ex, inext); 702 ehci_check_intr(sc, ex); 703 } 704 705 /* Schedule a callout to catch any dropped transactions. */ 706 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 707 !LIST_EMPTY(&sc->sc_intrhead)) 708 usb_callout(sc->sc_tmo_intrlist, hz, 709 ehci_intrlist_timeout, sc); 710 711 #ifdef USB_USE_SOFTINTR 712 if (sc->sc_softwake) { 713 sc->sc_softwake = 0; 714 wakeup(&sc->sc_softwake); 715 } 716 #endif /* USB_USE_SOFTINTR */ 717 718 sc->sc_bus.intr_context--; 719 } 720 721 /* Check for an interrupt. */ 722 void 723 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 724 { 725 ehci_soft_qtd_t *sqtd, *lsqtd; 726 u_int32_t status; 727 728 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 729 730 if (ex->sqtdstart == NULL) { 731 printf("ehci_check_intr: sqtdstart=NULL\n"); 732 return; 733 } 734 lsqtd = ex->sqtdend; 735 #ifdef DIAGNOSTIC 736 if (lsqtd == NULL) { 737 printf("ehci_check_intr: lsqtd==0\n"); 738 return; 739 } 740 #endif 741 /* 742 * If the last TD is still active we need to check whether there 743 * is a an error somewhere in the middle, or whether there was a 744 * short packet (SPD and not ACTIVE). 745 */ 746 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 747 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 748 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 749 status = le32toh(sqtd->qtd.qtd_status); 750 /* If there's an active QTD the xfer isn't done. */ 751 if (status & EHCI_QTD_ACTIVE) 752 break; 753 /* Any kind of error makes the xfer done. */ 754 if (status & EHCI_QTD_HALTED) 755 goto done; 756 /* We want short packets, and it is short: it's done */ 757 if (EHCI_QTD_GET_BYTES(status) != 0) 758 goto done; 759 } 760 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 761 ex, ex->sqtdstart)); 762 return; 763 } 764 done: 765 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 766 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 767 ehci_idone(ex); 768 } 769 770 void 771 ehci_idone(struct ehci_xfer *ex) 772 { 773 usbd_xfer_handle xfer = &ex->xfer; 774 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 775 ehci_soft_qtd_t *sqtd, *lsqtd; 776 u_int32_t status = 0, nstatus = 0; 777 int actlen; 778 uint pkts_left; 779 780 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 781 #ifdef DIAGNOSTIC 782 { 783 int s = splhigh(); 784 if (ex->isdone) { 785 splx(s); 786 #ifdef EHCI_DEBUG 787 printf("ehci_idone: ex is done!\n "); 788 ehci_dump_exfer(ex); 789 #else 790 printf("ehci_idone: ex=%p is done!\n", ex); 791 #endif 792 return; 793 } 794 ex->isdone = 1; 795 splx(s); 796 } 797 #endif 798 799 if (xfer->status == USBD_CANCELLED || 800 xfer->status == USBD_TIMEOUT) { 801 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 802 return; 803 } 804 805 #ifdef EHCI_DEBUG 806 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 807 if (ehcidebug > 10) 808 ehci_dump_sqtds(ex->sqtdstart); 809 #endif 810 811 /* The transfer is done, compute actual length and status. */ 812 lsqtd = ex->sqtdend; 813 actlen = 0; 814 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) { 815 nstatus = le32toh(sqtd->qtd.qtd_status); 816 if (nstatus & EHCI_QTD_ACTIVE) 817 break; 818 819 status = nstatus; 820 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 821 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 822 } 823 824 /* 825 * If there are left over TDs we need to update the toggle. 826 * The default pipe doesn't need it since control transfers 827 * start the toggle at 0 every time. 828 */ 829 if (sqtd != lsqtd->nextqtd && 830 xfer->pipe->device->default_pipe != xfer->pipe) { 831 printf("ehci_idone: need toggle update status=%08x nstatus=%08x\n", status, nstatus); 832 #if 0 833 ehci_dump_sqh(epipe->sqh); 834 ehci_dump_sqtds(ex->sqtdstart); 835 #endif 836 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 837 } 838 839 /* 840 * For a short transfer we need to update the toggle for the missing 841 * packets within the qTD. 842 */ 843 pkts_left = EHCI_QTD_GET_BYTES(status) / 844 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 845 epipe->nexttoggle ^= pkts_left % 2; 846 847 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 848 xfer->length, actlen, status)); 849 xfer->actlen = actlen; 850 if (status & EHCI_QTD_HALTED) { 851 #ifdef EHCI_DEBUG 852 char sbuf[128]; 853 854 bitmask_snprintf((u_int32_t)status, 855 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 856 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 857 858 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 859 "status 0x%s\n", 860 xfer->pipe->device->address, 861 xfer->pipe->endpoint->edesc->bEndpointAddress, 862 sbuf)); 863 if (ehcidebug > 2) { 864 ehci_dump_sqh(epipe->sqh); 865 ehci_dump_sqtds(ex->sqtdstart); 866 } 867 #endif 868 /* low&full speed has an extra error flag */ 869 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 870 EHCI_QH_SPEED_HIGH) 871 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 872 else 873 status &= EHCI_QTD_STATERRS; 874 if (status == 0) /* no other errors means a stall */ 875 xfer->status = USBD_STALLED; 876 else 877 xfer->status = USBD_IOERROR; /* more info XXX */ 878 /* XXX need to reset TT on missed microframe */ 879 if (status & EHCI_QTD_MISSEDMICRO) { 880 ehci_softc_t *sc = (ehci_softc_t *) 881 xfer->pipe->device->bus; 882 883 printf("%s: missed microframe, TT reset not " 884 "implemented, hub might be inoperational\n", 885 USBDEVNAME(sc->sc_bus.bdev)); 886 } 887 } else { 888 xfer->status = USBD_NORMAL_COMPLETION; 889 } 890 891 usb_transfer_complete(xfer); 892 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 893 } 894 895 /* 896 * Wait here until controller claims to have an interrupt. 897 * Then call ehci_intr and return. Use timeout to avoid waiting 898 * too long. 899 */ 900 void 901 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 902 { 903 int timo = xfer->timeout; 904 int usecs; 905 u_int32_t intrs; 906 907 xfer->status = USBD_IN_PROGRESS; 908 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 909 usb_delay_ms(&sc->sc_bus, 1); 910 if (sc->sc_dying) 911 break; 912 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 913 sc->sc_eintrs; 914 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 915 #ifdef EHCI_DEBUG 916 if (ehcidebug > 15) 917 ehci_dump_regs(sc); 918 #endif 919 if (intrs) { 920 ehci_intr1(sc); 921 if (xfer->status != USBD_IN_PROGRESS) 922 return; 923 } 924 } 925 926 /* Timeout */ 927 DPRINTF(("ehci_waitintr: timeout\n")); 928 xfer->status = USBD_TIMEOUT; 929 usb_transfer_complete(xfer); 930 /* XXX should free TD */ 931 } 932 933 void 934 ehci_poll(struct usbd_bus *bus) 935 { 936 ehci_softc_t *sc = (ehci_softc_t *)bus; 937 #ifdef EHCI_DEBUG 938 static int last; 939 int new; 940 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 941 if (new != last) { 942 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 943 last = new; 944 } 945 #endif 946 947 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 948 ehci_intr1(sc); 949 } 950 951 int 952 ehci_detach(struct ehci_softc *sc, int flags) 953 { 954 int rv = 0; 955 956 if (sc->sc_child != NULL) 957 rv = config_detach(sc->sc_child, flags); 958 959 if (rv != 0) 960 return (rv); 961 962 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 963 usb_uncallout(sc->sc_tmo_pcd, ehci_pcd_enable, sc); 964 965 if (sc->sc_powerhook != NULL) 966 powerhook_disestablish(sc->sc_powerhook); 967 if (sc->sc_shutdownhook != NULL) 968 shutdownhook_disestablish(sc->sc_shutdownhook); 969 970 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 971 972 /* XXX free other data structures XXX */ 973 974 return (rv); 975 } 976 977 978 int 979 ehci_activate(device_ptr_t self, enum devact act) 980 { 981 struct ehci_softc *sc = (struct ehci_softc *)self; 982 int rv = 0; 983 984 switch (act) { 985 case DVACT_ACTIVATE: 986 return (EOPNOTSUPP); 987 988 case DVACT_DEACTIVATE: 989 if (sc->sc_child != NULL) 990 rv = config_deactivate(sc->sc_child); 991 sc->sc_dying = 1; 992 break; 993 } 994 return (rv); 995 } 996 997 /* 998 * Handle suspend/resume. 999 * 1000 * We need to switch to polling mode here, because this routine is 1001 * called from an interrupt context. This is all right since we 1002 * are almost suspended anyway. 1003 */ 1004 void 1005 ehci_power(int why, void *v) 1006 { 1007 ehci_softc_t *sc = v; 1008 u_int32_t cmd, hcr; 1009 int s, i; 1010 1011 #ifdef EHCI_DEBUG 1012 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1013 if (ehcidebug > 0) 1014 ehci_dump_regs(sc); 1015 #endif 1016 1017 s = splhardusb(); 1018 switch (why) { 1019 case PWR_SUSPEND: 1020 case PWR_STANDBY: 1021 sc->sc_bus.use_polling++; 1022 1023 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1024 1025 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1026 EOWRITE4(sc, EHCI_USBCMD, cmd); 1027 1028 for (i = 0; i < 100; i++) { 1029 hcr = EOREAD4(sc, EHCI_USBSTS) & 1030 (EHCI_STS_ASS | EHCI_STS_PSS); 1031 if (hcr == 0) 1032 break; 1033 1034 usb_delay_ms(&sc->sc_bus, 1); 1035 } 1036 if (hcr != 0) { 1037 printf("%s: reset timeout\n", 1038 USBDEVNAME(sc->sc_bus.bdev)); 1039 } 1040 1041 cmd &= ~EHCI_CMD_RS; 1042 EOWRITE4(sc, EHCI_USBCMD, cmd); 1043 1044 for (i = 0; i < 100; i++) { 1045 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1046 if (hcr == EHCI_STS_HCH) 1047 break; 1048 1049 usb_delay_ms(&sc->sc_bus, 1); 1050 } 1051 if (hcr != EHCI_STS_HCH) { 1052 printf("%s: config timeout\n", 1053 USBDEVNAME(sc->sc_bus.bdev)); 1054 } 1055 1056 sc->sc_bus.use_polling--; 1057 break; 1058 1059 case PWR_RESUME: 1060 sc->sc_bus.use_polling++; 1061 1062 /* restore things in case the bios sucks */ 1063 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1064 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1065 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1066 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1067 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1068 1069 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1070 1071 for (i = 0; i < 100; i++) { 1072 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1073 if (hcr != EHCI_STS_HCH) 1074 break; 1075 1076 usb_delay_ms(&sc->sc_bus, 1); 1077 } 1078 if (hcr == EHCI_STS_HCH) { 1079 printf("%s: config timeout\n", 1080 USBDEVNAME(sc->sc_bus.bdev)); 1081 } 1082 1083 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1084 1085 sc->sc_bus.use_polling--; 1086 break; 1087 case PWR_SOFTSUSPEND: 1088 case PWR_SOFTSTANDBY: 1089 case PWR_SOFTRESUME: 1090 break; 1091 } 1092 splx(s); 1093 1094 #ifdef EHCI_DEBUG 1095 DPRINTF(("ehci_power: sc=%p\n", sc)); 1096 if (ehcidebug > 0) 1097 ehci_dump_regs(sc); 1098 #endif 1099 } 1100 1101 /* 1102 * Shut down the controller when the system is going down. 1103 */ 1104 void 1105 ehci_shutdown(void *v) 1106 { 1107 ehci_softc_t *sc = v; 1108 1109 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1110 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1111 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1112 } 1113 1114 usbd_status 1115 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1116 { 1117 struct ehci_softc *sc = (struct ehci_softc *)bus; 1118 usbd_status err; 1119 1120 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1121 if (err == USBD_NOMEM) 1122 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1123 #ifdef EHCI_DEBUG 1124 if (err) 1125 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1126 #endif 1127 return (err); 1128 } 1129 1130 void 1131 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1132 { 1133 struct ehci_softc *sc = (struct ehci_softc *)bus; 1134 1135 if (dma->block->flags & USB_DMA_RESERVE) { 1136 usb_reserve_freem(&((struct ehci_softc *)bus)->sc_dma_reserve, 1137 dma); 1138 return; 1139 } 1140 usb_freemem(&sc->sc_bus, dma); 1141 } 1142 1143 usbd_xfer_handle 1144 ehci_allocx(struct usbd_bus *bus) 1145 { 1146 struct ehci_softc *sc = (struct ehci_softc *)bus; 1147 usbd_xfer_handle xfer; 1148 1149 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1150 if (xfer != NULL) { 1151 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1152 #ifdef DIAGNOSTIC 1153 if (xfer->busy_free != XFER_FREE) { 1154 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1155 xfer->busy_free); 1156 } 1157 #endif 1158 } else { 1159 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1160 } 1161 if (xfer != NULL) { 1162 memset(xfer, 0, sizeof(struct ehci_xfer)); 1163 #ifdef DIAGNOSTIC 1164 EXFER(xfer)->isdone = 1; 1165 xfer->busy_free = XFER_BUSY; 1166 #endif 1167 } 1168 return (xfer); 1169 } 1170 1171 void 1172 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1173 { 1174 struct ehci_softc *sc = (struct ehci_softc *)bus; 1175 1176 #ifdef DIAGNOSTIC 1177 if (xfer->busy_free != XFER_BUSY) { 1178 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1179 xfer->busy_free); 1180 return; 1181 } 1182 xfer->busy_free = XFER_FREE; 1183 if (!EXFER(xfer)->isdone) { 1184 printf("ehci_freex: !isdone\n"); 1185 return; 1186 } 1187 #endif 1188 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1189 } 1190 1191 Static void 1192 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1193 { 1194 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1195 1196 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1197 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1198 #ifdef USB_DEBUG 1199 if (ehcidebug) 1200 usbd_dump_pipe(pipe); 1201 #endif 1202 epipe->nexttoggle = 0; 1203 } 1204 1205 Static void 1206 ehci_noop(usbd_pipe_handle pipe) 1207 { 1208 } 1209 1210 #ifdef EHCI_DEBUG 1211 void 1212 ehci_dump_regs(ehci_softc_t *sc) 1213 { 1214 int i; 1215 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1216 EOREAD4(sc, EHCI_USBCMD), 1217 EOREAD4(sc, EHCI_USBSTS), 1218 EOREAD4(sc, EHCI_USBINTR)); 1219 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1220 EOREAD4(sc, EHCI_FRINDEX), 1221 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1222 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1223 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1224 for (i = 1; i <= sc->sc_noport; i++) 1225 printf("port %d status=0x%08x\n", i, 1226 EOREAD4(sc, EHCI_PORTSC(i))); 1227 } 1228 1229 /* 1230 * Unused function - this is meant to be called from a kernel 1231 * debugger. 1232 */ 1233 void 1234 ehci_dump() 1235 { 1236 ehci_dump_regs(theehci); 1237 } 1238 1239 void 1240 ehci_dump_link(ehci_link_t link, int type) 1241 { 1242 link = le32toh(link); 1243 printf("0x%08x", link); 1244 if (link & EHCI_LINK_TERMINATE) 1245 printf("<T>"); 1246 else { 1247 printf("<"); 1248 if (type) { 1249 switch (EHCI_LINK_TYPE(link)) { 1250 case EHCI_LINK_ITD: printf("ITD"); break; 1251 case EHCI_LINK_QH: printf("QH"); break; 1252 case EHCI_LINK_SITD: printf("SITD"); break; 1253 case EHCI_LINK_FSTN: printf("FSTN"); break; 1254 } 1255 } 1256 printf(">"); 1257 } 1258 } 1259 1260 void 1261 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1262 { 1263 int i; 1264 u_int32_t stop; 1265 1266 stop = 0; 1267 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1268 ehci_dump_sqtd(sqtd); 1269 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1270 } 1271 if (sqtd) 1272 printf("dump aborted, too many TDs\n"); 1273 } 1274 1275 void 1276 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1277 { 1278 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1279 ehci_dump_qtd(&sqtd->qtd); 1280 } 1281 1282 void 1283 ehci_dump_qtd(ehci_qtd_t *qtd) 1284 { 1285 u_int32_t s; 1286 char sbuf[128]; 1287 1288 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1289 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1290 printf("\n"); 1291 s = le32toh(qtd->qtd_status); 1292 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1293 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1294 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1295 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1296 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1297 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1298 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1299 EHCI_QTD_GET_PID(s), sbuf); 1300 for (s = 0; s < 5; s++) 1301 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1302 } 1303 1304 void 1305 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1306 { 1307 ehci_qh_t *qh = &sqh->qh; 1308 u_int32_t endp, endphub; 1309 1310 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1311 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1312 endp = le32toh(qh->qh_endp); 1313 printf(" endp=0x%08x\n", endp); 1314 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1315 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1316 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1317 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1318 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1319 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1320 EHCI_QH_GET_NRL(endp)); 1321 endphub = le32toh(qh->qh_endphub); 1322 printf(" endphub=0x%08x\n", endphub); 1323 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1324 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1325 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1326 EHCI_QH_GET_MULT(endphub)); 1327 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1328 printf("Overlay qTD:\n"); 1329 ehci_dump_qtd(&qh->qh_qtd); 1330 } 1331 1332 #ifdef DIAGNOSTIC 1333 Static void 1334 ehci_dump_exfer(struct ehci_xfer *ex) 1335 { 1336 printf("ehci_dump_exfer: ex=%p\n", ex); 1337 } 1338 #endif 1339 #endif 1340 1341 usbd_status 1342 ehci_open(usbd_pipe_handle pipe) 1343 { 1344 usbd_device_handle dev = pipe->device; 1345 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1346 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1347 u_int8_t addr = dev->address; 1348 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1349 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1350 ehci_soft_qh_t *sqh; 1351 usbd_status err; 1352 int s; 1353 int ival, speed, naks; 1354 int hshubaddr, hshubport; 1355 1356 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1357 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1358 1359 if (dev->myhsport) { 1360 hshubaddr = dev->myhsport->parent->address; 1361 hshubport = dev->myhsport->portno; 1362 } else { 1363 hshubaddr = 0; 1364 hshubport = 0; 1365 } 1366 1367 if (sc->sc_dying) 1368 return (USBD_IOERROR); 1369 1370 epipe->nexttoggle = 0; 1371 1372 if (addr == sc->sc_addr) { 1373 switch (ed->bEndpointAddress) { 1374 case USB_CONTROL_ENDPOINT: 1375 pipe->methods = &ehci_root_ctrl_methods; 1376 break; 1377 case UE_DIR_IN | EHCI_INTR_ENDPT: 1378 pipe->methods = &ehci_root_intr_methods; 1379 break; 1380 default: 1381 return (USBD_INVAL); 1382 } 1383 return (USBD_NORMAL_COMPLETION); 1384 } 1385 1386 /* XXX All this stuff is only valid for async. */ 1387 switch (dev->speed) { 1388 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1389 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1390 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1391 default: panic("ehci_open: bad device speed %d", dev->speed); 1392 } 1393 if (speed != EHCI_QH_SPEED_HIGH) { 1394 printf("%s: *** WARNING: opening low/full speed device, this " 1395 "may not work yet.\n", 1396 USBDEVNAME(sc->sc_bus.bdev)); 1397 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1398 hshubaddr, hshubport)); 1399 #if 0 1400 if (xfertype != UE_CONTROL) 1401 return USBD_INVAL; 1402 #endif 1403 } 1404 1405 naks = 8; /* XXX */ 1406 sqh = ehci_alloc_sqh(sc); 1407 if (sqh == NULL) 1408 goto bad0; 1409 /* qh_link filled when the QH is added */ 1410 sqh->qh.qh_endp = htole32( 1411 EHCI_QH_SET_ADDR(addr) | 1412 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1413 EHCI_QH_SET_EPS(speed) | 1414 EHCI_QH_DTC | 1415 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1416 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1417 EHCI_QH_CTL : 0) | 1418 EHCI_QH_SET_NRL(naks) 1419 ); 1420 sqh->qh.qh_endphub = htole32( 1421 EHCI_QH_SET_MULT(1) | 1422 EHCI_QH_SET_HUBA(hshubaddr) | 1423 EHCI_QH_SET_PORT(hshubport) | 1424 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1425 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1426 ); 1427 sqh->qh.qh_curqtd = EHCI_NULL; 1428 /* Fill the overlay qTD */ 1429 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1430 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1431 sqh->qh.qh_qtd.qtd_status = htole32(0); 1432 1433 epipe->sqh = sqh; 1434 1435 switch (xfertype) { 1436 case UE_CONTROL: 1437 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1438 0, &epipe->u.ctl.reqdma); 1439 #ifdef EHCI_DEBUG 1440 if (err) 1441 printf("ehci_open: usb_allocmem()=%d\n", err); 1442 #endif 1443 if (err) 1444 goto bad1; 1445 pipe->methods = &ehci_device_ctrl_methods; 1446 s = splusb(); 1447 ehci_add_qh(sqh, sc->sc_async_head); 1448 splx(s); 1449 break; 1450 case UE_BULK: 1451 pipe->methods = &ehci_device_bulk_methods; 1452 s = splusb(); 1453 ehci_add_qh(sqh, sc->sc_async_head); 1454 splx(s); 1455 break; 1456 case UE_INTERRUPT: 1457 pipe->methods = &ehci_device_intr_methods; 1458 ival = pipe->interval; 1459 if (ival == USBD_DEFAULT_INTERVAL) 1460 ival = ed->bInterval; 1461 return (ehci_device_setintr(sc, sqh, ival)); 1462 case UE_ISOCHRONOUS: 1463 pipe->methods = &ehci_device_isoc_methods; 1464 return (USBD_INVAL); 1465 default: 1466 return (USBD_INVAL); 1467 } 1468 return (USBD_NORMAL_COMPLETION); 1469 1470 bad1: 1471 ehci_free_sqh(sc, sqh); 1472 bad0: 1473 return (USBD_NOMEM); 1474 } 1475 1476 /* 1477 * Add an ED to the schedule. Called at splusb(). 1478 */ 1479 void 1480 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1481 { 1482 SPLUSBCHECK; 1483 1484 sqh->next = head->next; 1485 sqh->qh.qh_link = head->qh.qh_link; 1486 head->next = sqh; 1487 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1488 1489 #ifdef EHCI_DEBUG 1490 if (ehcidebug > 5) { 1491 printf("ehci_add_qh:\n"); 1492 ehci_dump_sqh(sqh); 1493 } 1494 #endif 1495 } 1496 1497 /* 1498 * Remove an ED from the schedule. Called at splusb(). 1499 */ 1500 void 1501 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1502 { 1503 ehci_soft_qh_t *p; 1504 1505 SPLUSBCHECK; 1506 /* XXX */ 1507 for (p = head; p != NULL && p->next != sqh; p = p->next) 1508 ; 1509 if (p == NULL) 1510 panic("ehci_rem_qh: ED not found"); 1511 p->next = sqh->next; 1512 p->qh.qh_link = sqh->qh.qh_link; 1513 1514 ehci_sync_hc(sc); 1515 } 1516 1517 void 1518 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1519 { 1520 int i; 1521 u_int32_t status; 1522 1523 /* Save toggle bit and ping status. */ 1524 status = sqh->qh.qh_qtd.qtd_status & 1525 htole32(EHCI_QTD_TOGGLE_MASK | 1526 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1527 /* Set HALTED to make hw leave it alone. */ 1528 sqh->qh.qh_qtd.qtd_status = 1529 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1530 sqh->qh.qh_curqtd = 0; 1531 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1532 sqh->qh.qh_qtd.qtd_altnext = 0; 1533 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1534 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1535 sqh->sqtd = sqtd; 1536 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1537 sqh->qh.qh_qtd.qtd_status = status; 1538 } 1539 1540 /* 1541 * Ensure that the HC has released all references to the QH. We do this 1542 * by asking for a Async Advance Doorbell interrupt and then we wait for 1543 * the interrupt. 1544 * To make this easier we first obtain exclusive use of the doorbell. 1545 */ 1546 void 1547 ehci_sync_hc(ehci_softc_t *sc) 1548 { 1549 int s, error; 1550 1551 if (sc->sc_dying) { 1552 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1553 return; 1554 } 1555 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1556 usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); /* get doorbell */ 1557 s = splhardusb(); 1558 /* ask for doorbell */ 1559 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1560 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1561 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1562 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1563 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1564 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1565 splx(s); 1566 usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); /* release doorbell */ 1567 #ifdef DIAGNOSTIC 1568 if (error) 1569 printf("ehci_sync_hc: tsleep() = %d\n", error); 1570 #endif 1571 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1572 } 1573 1574 /***********/ 1575 1576 /* 1577 * Data structures and routines to emulate the root hub. 1578 */ 1579 Static usb_device_descriptor_t ehci_devd = { 1580 USB_DEVICE_DESCRIPTOR_SIZE, 1581 UDESC_DEVICE, /* type */ 1582 {0x00, 0x02}, /* USB version */ 1583 UDCLASS_HUB, /* class */ 1584 UDSUBCLASS_HUB, /* subclass */ 1585 UDPROTO_HSHUBSTT, /* protocol */ 1586 64, /* max packet */ 1587 {0},{0},{0x00,0x01}, /* device id */ 1588 1,2,0, /* string indicies */ 1589 1 /* # of configurations */ 1590 }; 1591 1592 Static usb_device_qualifier_t ehci_odevd = { 1593 USB_DEVICE_DESCRIPTOR_SIZE, 1594 UDESC_DEVICE_QUALIFIER, /* type */ 1595 {0x00, 0x02}, /* USB version */ 1596 UDCLASS_HUB, /* class */ 1597 UDSUBCLASS_HUB, /* subclass */ 1598 UDPROTO_FSHUB, /* protocol */ 1599 64, /* max packet */ 1600 1, /* # of configurations */ 1601 0 1602 }; 1603 1604 Static usb_config_descriptor_t ehci_confd = { 1605 USB_CONFIG_DESCRIPTOR_SIZE, 1606 UDESC_CONFIG, 1607 {USB_CONFIG_DESCRIPTOR_SIZE + 1608 USB_INTERFACE_DESCRIPTOR_SIZE + 1609 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1610 1, 1611 1, 1612 0, 1613 UC_SELF_POWERED, 1614 0 /* max power */ 1615 }; 1616 1617 Static usb_interface_descriptor_t ehci_ifcd = { 1618 USB_INTERFACE_DESCRIPTOR_SIZE, 1619 UDESC_INTERFACE, 1620 0, 1621 0, 1622 1, 1623 UICLASS_HUB, 1624 UISUBCLASS_HUB, 1625 UIPROTO_HSHUBSTT, 1626 0 1627 }; 1628 1629 Static usb_endpoint_descriptor_t ehci_endpd = { 1630 USB_ENDPOINT_DESCRIPTOR_SIZE, 1631 UDESC_ENDPOINT, 1632 UE_DIR_IN | EHCI_INTR_ENDPT, 1633 UE_INTERRUPT, 1634 {8, 0}, /* max packet */ 1635 255 1636 }; 1637 1638 Static usb_hub_descriptor_t ehci_hubd = { 1639 USB_HUB_DESCRIPTOR_SIZE, 1640 UDESC_HUB, 1641 0, 1642 {0,0}, 1643 0, 1644 0, 1645 {0}, 1646 }; 1647 1648 Static int 1649 ehci_str(usb_string_descriptor_t *p, int l, char *s) 1650 { 1651 int i; 1652 1653 if (l == 0) 1654 return (0); 1655 p->bLength = 2 * strlen(s) + 2; 1656 if (l == 1) 1657 return (1); 1658 p->bDescriptorType = UDESC_STRING; 1659 l -= 2; 1660 for (i = 0; s[i] && l > 1; i++, l -= 2) 1661 USETW2(p->bString[i], 0, s[i]); 1662 return (2*i+2); 1663 } 1664 1665 /* 1666 * Simulate a hardware hub by handling all the necessary requests. 1667 */ 1668 Static usbd_status 1669 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1670 { 1671 usbd_status err; 1672 1673 /* Insert last in queue. */ 1674 err = usb_insert_transfer(xfer); 1675 if (err) 1676 return (err); 1677 1678 /* Pipe isn't running, start first */ 1679 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1680 } 1681 1682 Static usbd_status 1683 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1684 { 1685 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1686 usb_device_request_t *req; 1687 void *buf = NULL; 1688 int port, i; 1689 int s, len, value, index, l, totlen = 0; 1690 usb_port_status_t ps; 1691 usb_hub_descriptor_t hubd; 1692 usbd_status err; 1693 u_int32_t v; 1694 1695 if (sc->sc_dying) 1696 return (USBD_IOERROR); 1697 1698 #ifdef DIAGNOSTIC 1699 if (!(xfer->rqflags & URQ_REQUEST)) 1700 /* XXX panic */ 1701 return (USBD_INVAL); 1702 #endif 1703 req = &xfer->request; 1704 1705 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1706 req->bmRequestType, req->bRequest)); 1707 1708 len = UGETW(req->wLength); 1709 value = UGETW(req->wValue); 1710 index = UGETW(req->wIndex); 1711 1712 if (len != 0) 1713 buf = KERNADDR(&xfer->dmabuf, 0); 1714 1715 #define C(x,y) ((x) | ((y) << 8)) 1716 switch(C(req->bRequest, req->bmRequestType)) { 1717 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1718 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1719 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1720 /* 1721 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1722 * for the integrated root hub. 1723 */ 1724 break; 1725 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1726 if (len > 0) { 1727 *(u_int8_t *)buf = sc->sc_conf; 1728 totlen = 1; 1729 } 1730 break; 1731 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1732 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1733 switch(value >> 8) { 1734 case UDESC_DEVICE: 1735 if ((value & 0xff) != 0) { 1736 err = USBD_IOERROR; 1737 goto ret; 1738 } 1739 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1740 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1741 memcpy(buf, &ehci_devd, l); 1742 break; 1743 /* 1744 * We can't really operate at another speed, but the spec says 1745 * we need this descriptor. 1746 */ 1747 case UDESC_DEVICE_QUALIFIER: 1748 if ((value & 0xff) != 0) { 1749 err = USBD_IOERROR; 1750 goto ret; 1751 } 1752 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1753 memcpy(buf, &ehci_odevd, l); 1754 break; 1755 /* 1756 * We can't really operate at another speed, but the spec says 1757 * we need this descriptor. 1758 */ 1759 case UDESC_OTHER_SPEED_CONFIGURATION: 1760 case UDESC_CONFIG: 1761 if ((value & 0xff) != 0) { 1762 err = USBD_IOERROR; 1763 goto ret; 1764 } 1765 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1766 memcpy(buf, &ehci_confd, l); 1767 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1768 value >> 8; 1769 buf = (char *)buf + l; 1770 len -= l; 1771 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1772 totlen += l; 1773 memcpy(buf, &ehci_ifcd, l); 1774 buf = (char *)buf + l; 1775 len -= l; 1776 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1777 totlen += l; 1778 memcpy(buf, &ehci_endpd, l); 1779 break; 1780 case UDESC_STRING: 1781 if (len == 0) 1782 break; 1783 *(u_int8_t *)buf = 0; 1784 totlen = 1; 1785 switch (value & 0xff) { 1786 case 0: /* Language table */ 1787 totlen = ehci_str(buf, len, "\001"); 1788 break; 1789 case 1: /* Vendor */ 1790 totlen = ehci_str(buf, len, sc->sc_vendor); 1791 break; 1792 case 2: /* Product */ 1793 totlen = ehci_str(buf, len, "EHCI root hub"); 1794 break; 1795 } 1796 break; 1797 default: 1798 err = USBD_IOERROR; 1799 goto ret; 1800 } 1801 break; 1802 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1803 if (len > 0) { 1804 *(u_int8_t *)buf = 0; 1805 totlen = 1; 1806 } 1807 break; 1808 case C(UR_GET_STATUS, UT_READ_DEVICE): 1809 if (len > 1) { 1810 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1811 totlen = 2; 1812 } 1813 break; 1814 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1815 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1816 if (len > 1) { 1817 USETW(((usb_status_t *)buf)->wStatus, 0); 1818 totlen = 2; 1819 } 1820 break; 1821 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1822 if (value >= USB_MAX_DEVICES) { 1823 err = USBD_IOERROR; 1824 goto ret; 1825 } 1826 sc->sc_addr = value; 1827 break; 1828 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1829 if (value != 0 && value != 1) { 1830 err = USBD_IOERROR; 1831 goto ret; 1832 } 1833 sc->sc_conf = value; 1834 break; 1835 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1836 break; 1837 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1838 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1839 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1840 err = USBD_IOERROR; 1841 goto ret; 1842 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1843 break; 1844 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1845 break; 1846 /* Hub requests */ 1847 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1848 break; 1849 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1850 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 1851 "port=%d feature=%d\n", 1852 index, value)); 1853 if (index < 1 || index > sc->sc_noport) { 1854 err = USBD_IOERROR; 1855 goto ret; 1856 } 1857 port = EHCI_PORTSC(index); 1858 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1859 switch(value) { 1860 case UHF_PORT_ENABLE: 1861 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1862 break; 1863 case UHF_PORT_SUSPEND: 1864 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1865 break; 1866 case UHF_PORT_POWER: 1867 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1868 break; 1869 case UHF_PORT_TEST: 1870 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 1871 "%d\n", index)); 1872 break; 1873 case UHF_PORT_INDICATOR: 1874 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 1875 "%d\n", index)); 1876 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1877 break; 1878 case UHF_C_PORT_CONNECTION: 1879 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1880 break; 1881 case UHF_C_PORT_ENABLE: 1882 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1883 break; 1884 case UHF_C_PORT_SUSPEND: 1885 /* how? */ 1886 break; 1887 case UHF_C_PORT_OVER_CURRENT: 1888 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1889 break; 1890 case UHF_C_PORT_RESET: 1891 sc->sc_isreset = 0; 1892 break; 1893 default: 1894 err = USBD_IOERROR; 1895 goto ret; 1896 } 1897 #if 0 1898 switch(value) { 1899 case UHF_C_PORT_CONNECTION: 1900 case UHF_C_PORT_ENABLE: 1901 case UHF_C_PORT_SUSPEND: 1902 case UHF_C_PORT_OVER_CURRENT: 1903 case UHF_C_PORT_RESET: 1904 /* Enable RHSC interrupt if condition is cleared. */ 1905 if ((OREAD4(sc, port) >> 16) == 0) 1906 ehci_pcd_able(sc, 1); 1907 break; 1908 default: 1909 break; 1910 } 1911 #endif 1912 break; 1913 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1914 if ((value & 0xff) != 0) { 1915 err = USBD_IOERROR; 1916 goto ret; 1917 } 1918 hubd = ehci_hubd; 1919 hubd.bNbrPorts = sc->sc_noport; 1920 v = EOREAD4(sc, EHCI_HCSPARAMS); 1921 USETW(hubd.wHubCharacteristics, 1922 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 1923 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 1924 ? UHD_PORT_IND : 0); 1925 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 1926 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1927 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 1928 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1929 l = min(len, hubd.bDescLength); 1930 totlen = l; 1931 memcpy(buf, &hubd, l); 1932 break; 1933 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1934 if (len != 4) { 1935 err = USBD_IOERROR; 1936 goto ret; 1937 } 1938 memset(buf, 0, len); /* ? XXX */ 1939 totlen = len; 1940 break; 1941 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1942 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 1943 index)); 1944 if (index < 1 || index > sc->sc_noport) { 1945 err = USBD_IOERROR; 1946 goto ret; 1947 } 1948 if (len != 4) { 1949 err = USBD_IOERROR; 1950 goto ret; 1951 } 1952 v = EOREAD4(sc, EHCI_PORTSC(index)); 1953 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 1954 v)); 1955 i = UPS_HIGH_SPEED; 1956 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 1957 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 1958 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 1959 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 1960 if (v & EHCI_PS_PR) i |= UPS_RESET; 1961 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 1962 USETW(ps.wPortStatus, i); 1963 i = 0; 1964 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 1965 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 1966 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 1967 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 1968 USETW(ps.wPortChange, i); 1969 l = min(len, sizeof ps); 1970 memcpy(buf, &ps, l); 1971 totlen = l; 1972 break; 1973 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1974 err = USBD_IOERROR; 1975 goto ret; 1976 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1977 break; 1978 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1979 if (index < 1 || index > sc->sc_noport) { 1980 err = USBD_IOERROR; 1981 goto ret; 1982 } 1983 port = EHCI_PORTSC(index); 1984 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1985 switch(value) { 1986 case UHF_PORT_ENABLE: 1987 EOWRITE4(sc, port, v | EHCI_PS_PE); 1988 break; 1989 case UHF_PORT_SUSPEND: 1990 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 1991 break; 1992 case UHF_PORT_RESET: 1993 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 1994 index)); 1995 if (EHCI_PS_IS_LOWSPEED(v)) { 1996 /* Low speed device, give up ownership. */ 1997 ehci_disown(sc, index, 1); 1998 break; 1999 } 2000 /* Start reset sequence. */ 2001 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2002 EOWRITE4(sc, port, v | EHCI_PS_PR); 2003 /* Wait for reset to complete. */ 2004 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2005 if (sc->sc_dying) { 2006 err = USBD_IOERROR; 2007 goto ret; 2008 } 2009 /* Terminate reset sequence. */ 2010 EOWRITE4(sc, port, v); 2011 /* Wait for HC to complete reset. */ 2012 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2013 if (sc->sc_dying) { 2014 err = USBD_IOERROR; 2015 goto ret; 2016 } 2017 v = EOREAD4(sc, port); 2018 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2019 if (v & EHCI_PS_PR) { 2020 printf("%s: port reset timeout\n", 2021 USBDEVNAME(sc->sc_bus.bdev)); 2022 return (USBD_TIMEOUT); 2023 } 2024 if (!(v & EHCI_PS_PE)) { 2025 /* Not a high speed device, give up ownership.*/ 2026 ehci_disown(sc, index, 0); 2027 break; 2028 } 2029 sc->sc_isreset = 1; 2030 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2031 index, v)); 2032 break; 2033 case UHF_PORT_POWER: 2034 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2035 "%d\n", index)); 2036 EOWRITE4(sc, port, v | EHCI_PS_PP); 2037 break; 2038 case UHF_PORT_TEST: 2039 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2040 "%d\n", index)); 2041 break; 2042 case UHF_PORT_INDICATOR: 2043 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2044 "%d\n", index)); 2045 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2046 break; 2047 default: 2048 err = USBD_IOERROR; 2049 goto ret; 2050 } 2051 break; 2052 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2053 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2054 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2055 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2056 break; 2057 default: 2058 err = USBD_IOERROR; 2059 goto ret; 2060 } 2061 xfer->actlen = totlen; 2062 err = USBD_NORMAL_COMPLETION; 2063 ret: 2064 xfer->status = err; 2065 s = splusb(); 2066 usb_transfer_complete(xfer); 2067 splx(s); 2068 return (USBD_IN_PROGRESS); 2069 } 2070 2071 void 2072 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2073 { 2074 int port; 2075 u_int32_t v; 2076 2077 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2078 #ifdef DIAGNOSTIC 2079 if (sc->sc_npcomp != 0) { 2080 int i = (index-1) / sc->sc_npcomp; 2081 if (i >= sc->sc_ncomp) 2082 printf("%s: strange port\n", 2083 USBDEVNAME(sc->sc_bus.bdev)); 2084 else 2085 printf("%s: handing over %s speed device on " 2086 "port %d to %s\n", 2087 USBDEVNAME(sc->sc_bus.bdev), 2088 lowspeed ? "low" : "full", 2089 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 2090 } else { 2091 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 2092 } 2093 #endif 2094 port = EHCI_PORTSC(index); 2095 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2096 EOWRITE4(sc, port, v | EHCI_PS_PO); 2097 } 2098 2099 /* Abort a root control request. */ 2100 Static void 2101 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2102 { 2103 /* Nothing to do, all transfers are synchronous. */ 2104 } 2105 2106 /* Close the root pipe. */ 2107 Static void 2108 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2109 { 2110 DPRINTF(("ehci_root_ctrl_close\n")); 2111 /* Nothing to do. */ 2112 } 2113 2114 void 2115 ehci_root_intr_done(usbd_xfer_handle xfer) 2116 { 2117 xfer->hcpriv = NULL; 2118 } 2119 2120 Static usbd_status 2121 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2122 { 2123 usbd_status err; 2124 2125 /* Insert last in queue. */ 2126 err = usb_insert_transfer(xfer); 2127 if (err) 2128 return (err); 2129 2130 /* Pipe isn't running, start first */ 2131 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2132 } 2133 2134 Static usbd_status 2135 ehci_root_intr_start(usbd_xfer_handle xfer) 2136 { 2137 usbd_pipe_handle pipe = xfer->pipe; 2138 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2139 2140 if (sc->sc_dying) 2141 return (USBD_IOERROR); 2142 2143 sc->sc_intrxfer = xfer; 2144 2145 return (USBD_IN_PROGRESS); 2146 } 2147 2148 /* Abort a root interrupt request. */ 2149 Static void 2150 ehci_root_intr_abort(usbd_xfer_handle xfer) 2151 { 2152 int s; 2153 2154 if (xfer->pipe->intrxfer == xfer) { 2155 DPRINTF(("ehci_root_intr_abort: remove\n")); 2156 xfer->pipe->intrxfer = NULL; 2157 } 2158 xfer->status = USBD_CANCELLED; 2159 s = splusb(); 2160 usb_transfer_complete(xfer); 2161 splx(s); 2162 } 2163 2164 /* Close the root pipe. */ 2165 Static void 2166 ehci_root_intr_close(usbd_pipe_handle pipe) 2167 { 2168 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2169 2170 DPRINTF(("ehci_root_intr_close\n")); 2171 2172 sc->sc_intrxfer = NULL; 2173 } 2174 2175 void 2176 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2177 { 2178 xfer->hcpriv = NULL; 2179 } 2180 2181 /************************/ 2182 2183 ehci_soft_qh_t * 2184 ehci_alloc_sqh(ehci_softc_t *sc) 2185 { 2186 ehci_soft_qh_t *sqh; 2187 usbd_status err; 2188 int i, offs; 2189 usb_dma_t dma; 2190 2191 if (sc->sc_freeqhs == NULL) { 2192 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2193 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2194 EHCI_PAGE_SIZE, &dma); 2195 #ifdef EHCI_DEBUG 2196 if (err) 2197 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2198 #endif 2199 if (err) 2200 return (NULL); 2201 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2202 offs = i * EHCI_SQH_SIZE; 2203 sqh = KERNADDR(&dma, offs); 2204 sqh->physaddr = DMAADDR(&dma, offs); 2205 sqh->next = sc->sc_freeqhs; 2206 sc->sc_freeqhs = sqh; 2207 } 2208 } 2209 sqh = sc->sc_freeqhs; 2210 sc->sc_freeqhs = sqh->next; 2211 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2212 sqh->next = NULL; 2213 return (sqh); 2214 } 2215 2216 void 2217 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2218 { 2219 sqh->next = sc->sc_freeqhs; 2220 sc->sc_freeqhs = sqh; 2221 } 2222 2223 ehci_soft_qtd_t * 2224 ehci_alloc_sqtd(ehci_softc_t *sc) 2225 { 2226 ehci_soft_qtd_t *sqtd; 2227 usbd_status err; 2228 int i, offs; 2229 usb_dma_t dma; 2230 int s; 2231 2232 if (sc->sc_freeqtds == NULL) { 2233 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2234 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2235 EHCI_PAGE_SIZE, &dma); 2236 #ifdef EHCI_DEBUG 2237 if (err) 2238 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2239 #endif 2240 if (err) 2241 return (NULL); 2242 s = splusb(); 2243 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2244 offs = i * EHCI_SQTD_SIZE; 2245 sqtd = KERNADDR(&dma, offs); 2246 sqtd->physaddr = DMAADDR(&dma, offs); 2247 sqtd->nextqtd = sc->sc_freeqtds; 2248 sc->sc_freeqtds = sqtd; 2249 } 2250 splx(s); 2251 } 2252 2253 s = splusb(); 2254 sqtd = sc->sc_freeqtds; 2255 sc->sc_freeqtds = sqtd->nextqtd; 2256 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2257 sqtd->nextqtd = NULL; 2258 sqtd->xfer = NULL; 2259 splx(s); 2260 2261 return (sqtd); 2262 } 2263 2264 void 2265 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2266 { 2267 int s; 2268 2269 s = splusb(); 2270 sqtd->nextqtd = sc->sc_freeqtds; 2271 sc->sc_freeqtds = sqtd; 2272 splx(s); 2273 } 2274 2275 usbd_status 2276 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2277 int alen, int rd, usbd_xfer_handle xfer, 2278 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2279 { 2280 ehci_soft_qtd_t *next, *cur; 2281 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2282 u_int32_t qtdstatus; 2283 int len, curlen, mps; 2284 int i, tog; 2285 usb_dma_t *dma = &xfer->dmabuf; 2286 u_int16_t flags = xfer->flags; 2287 2288 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2289 2290 len = alen; 2291 dataphys = DMAADDR(dma, 0); 2292 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2293 qtdstatus = EHCI_QTD_ACTIVE | 2294 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2295 EHCI_QTD_SET_CERR(3) 2296 /* IOC set below */ 2297 /* BYTES set below */ 2298 ; 2299 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2300 tog = epipe->nexttoggle; 2301 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2302 2303 cur = ehci_alloc_sqtd(sc); 2304 *sp = cur; 2305 if (cur == NULL) 2306 goto nomem; 2307 for (;;) { 2308 dataphyspage = EHCI_PAGE(dataphys); 2309 /* The EHCI hardware can handle at most 5 pages. */ 2310 if (dataphyslastpage - dataphyspage < 2311 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2312 /* we can handle it in this QTD */ 2313 curlen = len; 2314 } else { 2315 /* must use multiple TDs, fill as much as possible. */ 2316 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2317 EHCI_PAGE_OFFSET(dataphys); 2318 #ifdef DIAGNOSTIC 2319 if (curlen > len) { 2320 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2321 "len=0x%x offs=0x%x\n", curlen, len, 2322 EHCI_PAGE_OFFSET(dataphys)); 2323 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2324 dataphyslastpage, dataphyspage, 2325 dataphys); 2326 curlen = len; 2327 } 2328 #endif 2329 /* the length must be a multiple of the max size */ 2330 curlen -= curlen % mps; 2331 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2332 "curlen=%d\n", curlen)); 2333 #ifdef DIAGNOSTIC 2334 if (curlen == 0) 2335 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2336 #endif 2337 } 2338 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2339 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2340 dataphys, dataphyslastpage, 2341 len, curlen)); 2342 len -= curlen; 2343 2344 /* 2345 * Allocate another transfer if there's more data left, 2346 * or if force last short transfer flag is set and we're 2347 * allocating a multiple of the max packet size. 2348 */ 2349 if (len != 0 || 2350 ((curlen % mps) == 0 && !rd && curlen != 0 && 2351 (flags & USBD_FORCE_SHORT_XFER))) { 2352 next = ehci_alloc_sqtd(sc); 2353 if (next == NULL) 2354 goto nomem; 2355 nextphys = htole32(next->physaddr); 2356 } else { 2357 next = NULL; 2358 nextphys = EHCI_NULL; 2359 } 2360 2361 for (i = 0; i * EHCI_PAGE_SIZE < 2362 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2363 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2364 if (i != 0) /* use offset only in first buffer */ 2365 a = EHCI_PAGE(a); 2366 cur->qtd.qtd_buffer[i] = htole32(a); 2367 cur->qtd.qtd_buffer_hi[i] = 0; 2368 #ifdef DIAGNOSTIC 2369 if (i >= EHCI_QTD_NBUFFERS) { 2370 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2371 goto nomem; 2372 } 2373 #endif 2374 } 2375 cur->nextqtd = next; 2376 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2377 cur->qtd.qtd_status = 2378 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2379 cur->xfer = xfer; 2380 cur->len = curlen; 2381 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2382 dataphys, dataphys + curlen)); 2383 /* adjust the toggle based on the number of packets in this 2384 qtd */ 2385 if (((curlen + mps - 1) / mps) & 1) { 2386 tog ^= 1; 2387 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2388 } 2389 if (next == NULL) 2390 break; 2391 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2392 dataphys += curlen; 2393 cur = next; 2394 } 2395 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2396 *ep = cur; 2397 epipe->nexttoggle = tog; 2398 2399 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2400 *sp, *ep)); 2401 2402 return (USBD_NORMAL_COMPLETION); 2403 2404 nomem: 2405 /* XXX free chain */ 2406 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2407 return (USBD_NOMEM); 2408 } 2409 2410 Static void 2411 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2412 ehci_soft_qtd_t *sqtdend) 2413 { 2414 ehci_soft_qtd_t *p; 2415 int i; 2416 2417 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2418 sqtd, sqtdend)); 2419 2420 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2421 p = sqtd->nextqtd; 2422 ehci_free_sqtd(sc, sqtd); 2423 } 2424 } 2425 2426 /****************/ 2427 2428 /* 2429 * Close a reqular pipe. 2430 * Assumes that there are no pending transactions. 2431 */ 2432 void 2433 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2434 { 2435 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2436 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2437 ehci_soft_qh_t *sqh = epipe->sqh; 2438 int s; 2439 2440 s = splusb(); 2441 ehci_rem_qh(sc, sqh, head); 2442 splx(s); 2443 ehci_free_sqh(sc, epipe->sqh); 2444 } 2445 2446 /* 2447 * Abort a device request. 2448 * If this routine is called at splusb() it guarantees that the request 2449 * will be removed from the hardware scheduling and that the callback 2450 * for it will be called with USBD_CANCELLED status. 2451 * It's impossible to guarantee that the requested transfer will not 2452 * have happened since the hardware runs concurrently. 2453 * If the transaction has already happened we rely on the ordinary 2454 * interrupt processing to process it. 2455 * XXX This is most probably wrong. 2456 */ 2457 void 2458 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2459 { 2460 #define exfer EXFER(xfer) 2461 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2462 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2463 ehci_soft_qh_t *sqh = epipe->sqh; 2464 ehci_soft_qtd_t *sqtd; 2465 ehci_physaddr_t cur; 2466 u_int32_t qhstatus; 2467 int s; 2468 int hit; 2469 int wake; 2470 2471 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2472 2473 if (sc->sc_dying) { 2474 /* If we're dying, just do the software part. */ 2475 s = splusb(); 2476 xfer->status = status; /* make software ignore it */ 2477 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2478 usb_transfer_complete(xfer); 2479 splx(s); 2480 return; 2481 } 2482 2483 if (xfer->device->bus->intr_context || !curproc) 2484 panic("ehci_abort_xfer: not in process context"); 2485 2486 /* 2487 * If an abort is already in progress then just wait for it to 2488 * complete and return. 2489 */ 2490 if (xfer->hcflags & UXFER_ABORTING) { 2491 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2492 #ifdef DIAGNOSTIC 2493 if (status == USBD_TIMEOUT) 2494 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2495 #endif 2496 /* Override the status which might be USBD_TIMEOUT. */ 2497 xfer->status = status; 2498 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2499 xfer->hcflags |= UXFER_ABORTWAIT; 2500 while (xfer->hcflags & UXFER_ABORTING) 2501 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2502 return; 2503 } 2504 xfer->hcflags |= UXFER_ABORTING; 2505 2506 /* 2507 * Step 1: Make interrupt routine and hardware ignore xfer. 2508 */ 2509 s = splusb(); 2510 xfer->status = status; /* make software ignore it */ 2511 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2512 qhstatus = sqh->qh.qh_qtd.qtd_status; 2513 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2514 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2515 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2516 if (sqtd == exfer->sqtdend) 2517 break; 2518 } 2519 splx(s); 2520 2521 /* 2522 * Step 2: Wait until we know hardware has finished any possible 2523 * use of the xfer. Also make sure the soft interrupt routine 2524 * has run. 2525 */ 2526 ehci_sync_hc(sc); 2527 s = splusb(); 2528 #ifdef USB_USE_SOFTINTR 2529 sc->sc_softwake = 1; 2530 #endif /* USB_USE_SOFTINTR */ 2531 usb_schedsoftintr(&sc->sc_bus); 2532 #ifdef USB_USE_SOFTINTR 2533 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2534 #endif /* USB_USE_SOFTINTR */ 2535 splx(s); 2536 2537 /* 2538 * Step 3: Remove any vestiges of the xfer from the hardware. 2539 * The complication here is that the hardware may have executed 2540 * beyond the xfer we're trying to abort. So as we're scanning 2541 * the TDs of this xfer we check if the hardware points to 2542 * any of them. 2543 */ 2544 s = splusb(); /* XXX why? */ 2545 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2546 hit = 0; 2547 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2548 hit |= cur == sqtd->physaddr; 2549 if (sqtd == exfer->sqtdend) 2550 break; 2551 } 2552 sqtd = sqtd->nextqtd; 2553 /* Zap curqtd register if hardware pointed inside the xfer. */ 2554 if (hit && sqtd != NULL) { 2555 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2556 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2557 sqh->qh.qh_qtd.qtd_status = qhstatus; 2558 } else { 2559 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2560 } 2561 2562 /* 2563 * Step 4: Execute callback. 2564 */ 2565 #ifdef DIAGNOSTIC 2566 exfer->isdone = 1; 2567 #endif 2568 wake = xfer->hcflags & UXFER_ABORTWAIT; 2569 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2570 usb_transfer_complete(xfer); 2571 if (wake) 2572 wakeup(&xfer->hcflags); 2573 2574 splx(s); 2575 #undef exfer 2576 } 2577 2578 void 2579 ehci_timeout(void *addr) 2580 { 2581 struct ehci_xfer *exfer = addr; 2582 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2583 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2584 2585 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2586 #ifdef USB_DEBUG 2587 if (ehcidebug > 1) 2588 usbd_dump_pipe(exfer->xfer.pipe); 2589 #endif 2590 2591 if (sc->sc_dying) { 2592 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2593 return; 2594 } 2595 2596 /* Execute the abort in a process context. */ 2597 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 2598 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 2599 } 2600 2601 void 2602 ehci_timeout_task(void *addr) 2603 { 2604 usbd_xfer_handle xfer = addr; 2605 int s; 2606 2607 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 2608 2609 s = splusb(); 2610 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2611 splx(s); 2612 } 2613 2614 /************************/ 2615 2616 Static usbd_status 2617 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 2618 { 2619 usbd_status err; 2620 2621 /* Insert last in queue. */ 2622 err = usb_insert_transfer(xfer); 2623 if (err) 2624 return (err); 2625 2626 /* Pipe isn't running, start first */ 2627 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2628 } 2629 2630 Static usbd_status 2631 ehci_device_ctrl_start(usbd_xfer_handle xfer) 2632 { 2633 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2634 usbd_status err; 2635 2636 if (sc->sc_dying) 2637 return (USBD_IOERROR); 2638 2639 #ifdef DIAGNOSTIC 2640 if (!(xfer->rqflags & URQ_REQUEST)) { 2641 /* XXX panic */ 2642 printf("ehci_device_ctrl_transfer: not a request\n"); 2643 return (USBD_INVAL); 2644 } 2645 #endif 2646 2647 err = ehci_device_request(xfer); 2648 if (err) 2649 return (err); 2650 2651 if (sc->sc_bus.use_polling) 2652 ehci_waitintr(sc, xfer); 2653 return (USBD_IN_PROGRESS); 2654 } 2655 2656 void 2657 ehci_device_ctrl_done(usbd_xfer_handle xfer) 2658 { 2659 struct ehci_xfer *ex = EXFER(xfer); 2660 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2661 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 2662 2663 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 2664 2665 #ifdef DIAGNOSTIC 2666 if (!(xfer->rqflags & URQ_REQUEST)) { 2667 panic("ehci_ctrl_done: not a request"); 2668 } 2669 #endif 2670 2671 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 2672 ehci_del_intr_list(ex); /* remove from active list */ 2673 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 2674 } 2675 2676 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 2677 } 2678 2679 /* Abort a device control request. */ 2680 Static void 2681 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 2682 { 2683 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 2684 ehci_abort_xfer(xfer, USBD_CANCELLED); 2685 } 2686 2687 /* Close a device control pipe. */ 2688 Static void 2689 ehci_device_ctrl_close(usbd_pipe_handle pipe) 2690 { 2691 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2692 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 2693 2694 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 2695 ehci_close_pipe(pipe, sc->sc_async_head); 2696 } 2697 2698 usbd_status 2699 ehci_device_request(usbd_xfer_handle xfer) 2700 { 2701 #define exfer EXFER(xfer) 2702 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2703 usb_device_request_t *req = &xfer->request; 2704 usbd_device_handle dev = epipe->pipe.device; 2705 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 2706 int addr = dev->address; 2707 ehci_soft_qtd_t *setup, *stat, *next; 2708 ehci_soft_qh_t *sqh; 2709 int isread; 2710 int len; 2711 usbd_status err; 2712 int s; 2713 2714 isread = req->bmRequestType & UT_READ; 2715 len = UGETW(req->wLength); 2716 2717 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 2718 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2719 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2720 UGETW(req->wIndex), len, addr, 2721 epipe->pipe.endpoint->edesc->bEndpointAddress)); 2722 2723 setup = ehci_alloc_sqtd(sc); 2724 if (setup == NULL) { 2725 err = USBD_NOMEM; 2726 goto bad1; 2727 } 2728 stat = ehci_alloc_sqtd(sc); 2729 if (stat == NULL) { 2730 err = USBD_NOMEM; 2731 goto bad2; 2732 } 2733 2734 sqh = epipe->sqh; 2735 epipe->u.ctl.length = len; 2736 2737 /* Update device address and length since they may have changed 2738 during the setup of the control pipe in usbd_new_device(). */ 2739 /* XXX This only needs to be done once, but it's too early in open. */ 2740 /* XXXX Should not touch ED here! */ 2741 sqh->qh.qh_endp = 2742 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 2743 htole32( 2744 EHCI_QH_SET_ADDR(addr) | 2745 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 2746 ); 2747 2748 /* Set up data transaction */ 2749 if (len != 0) { 2750 ehci_soft_qtd_t *end; 2751 2752 /* Start toggle at 1. */ 2753 epipe->nexttoggle = 1; 2754 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 2755 &next, &end); 2756 if (err) 2757 goto bad3; 2758 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 2759 end->nextqtd = stat; 2760 end->qtd.qtd_next = 2761 end->qtd.qtd_altnext = htole32(stat->physaddr); 2762 } else { 2763 next = stat; 2764 } 2765 2766 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 2767 2768 /* Clear toggle */ 2769 setup->qtd.qtd_status = htole32( 2770 EHCI_QTD_ACTIVE | 2771 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2772 EHCI_QTD_SET_CERR(3) | 2773 EHCI_QTD_SET_TOGGLE(0) | 2774 EHCI_QTD_SET_BYTES(sizeof *req) 2775 ); 2776 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2777 setup->qtd.qtd_buffer_hi[0] = 0; 2778 setup->nextqtd = next; 2779 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2780 setup->xfer = xfer; 2781 setup->len = sizeof *req; 2782 2783 stat->qtd.qtd_status = htole32( 2784 EHCI_QTD_ACTIVE | 2785 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2786 EHCI_QTD_SET_CERR(3) | 2787 EHCI_QTD_SET_TOGGLE(1) | 2788 EHCI_QTD_IOC 2789 ); 2790 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2791 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 2792 stat->nextqtd = NULL; 2793 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 2794 stat->xfer = xfer; 2795 stat->len = 0; 2796 2797 #ifdef EHCI_DEBUG 2798 if (ehcidebug > 5) { 2799 DPRINTF(("ehci_device_request:\n")); 2800 ehci_dump_sqh(sqh); 2801 ehci_dump_sqtds(setup); 2802 } 2803 #endif 2804 2805 exfer->sqtdstart = setup; 2806 exfer->sqtdend = stat; 2807 #ifdef DIAGNOSTIC 2808 if (!exfer->isdone) { 2809 printf("ehci_device_request: not done, exfer=%p\n", exfer); 2810 } 2811 exfer->isdone = 0; 2812 #endif 2813 2814 /* Insert qTD in QH list. */ 2815 s = splusb(); 2816 ehci_set_qh_qtd(sqh, setup); 2817 if (xfer->timeout && !sc->sc_bus.use_polling) { 2818 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2819 ehci_timeout, xfer); 2820 } 2821 ehci_add_intr_list(sc, exfer); 2822 xfer->status = USBD_IN_PROGRESS; 2823 splx(s); 2824 2825 #ifdef EHCI_DEBUG 2826 if (ehcidebug > 10) { 2827 DPRINTF(("ehci_device_request: status=%x\n", 2828 EOREAD4(sc, EHCI_USBSTS))); 2829 delay(10000); 2830 ehci_dump_regs(sc); 2831 ehci_dump_sqh(sc->sc_async_head); 2832 ehci_dump_sqh(sqh); 2833 ehci_dump_sqtds(setup); 2834 } 2835 #endif 2836 2837 return (USBD_NORMAL_COMPLETION); 2838 2839 bad3: 2840 ehci_free_sqtd(sc, stat); 2841 bad2: 2842 ehci_free_sqtd(sc, setup); 2843 bad1: 2844 DPRINTFN(-1,("ehci_device_request: no memory\n")); 2845 xfer->status = err; 2846 usb_transfer_complete(xfer); 2847 return (err); 2848 #undef exfer 2849 } 2850 2851 /* 2852 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 2853 * qTD status, or miss signalling occasionally under heavy load. If the host 2854 * machine is too fast, we we can miss transaction completion - when we scan 2855 * the active list the transaction still seems to be active. This generally 2856 * exhibits itself as a umass stall that never recovers. 2857 * 2858 * We work around this behaviour by setting up this callback after any softintr 2859 * that completes with transactions still pending, giving us another chance to 2860 * check for completion after the writeback has taken place. 2861 */ 2862 void 2863 ehci_intrlist_timeout(void *arg) 2864 { 2865 ehci_softc_t *sc = arg; 2866 int s = splusb(); 2867 2868 DPRINTF(("ehci_intrlist_timeout\n")); 2869 usb_schedsoftintr(&sc->sc_bus); 2870 2871 splx(s); 2872 } 2873 2874 /************************/ 2875 2876 Static usbd_status 2877 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 2878 { 2879 usbd_status err; 2880 2881 /* Insert last in queue. */ 2882 err = usb_insert_transfer(xfer); 2883 if (err) 2884 return (err); 2885 2886 /* Pipe isn't running, start first */ 2887 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2888 } 2889 2890 usbd_status 2891 ehci_device_bulk_start(usbd_xfer_handle xfer) 2892 { 2893 #define exfer EXFER(xfer) 2894 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2895 usbd_device_handle dev = epipe->pipe.device; 2896 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 2897 ehci_soft_qtd_t *data, *dataend; 2898 ehci_soft_qh_t *sqh; 2899 usbd_status err; 2900 int len, isread, endpt; 2901 int s; 2902 2903 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 2904 xfer, xfer->length, xfer->flags)); 2905 2906 if (sc->sc_dying) 2907 return (USBD_IOERROR); 2908 2909 #ifdef DIAGNOSTIC 2910 if (xfer->rqflags & URQ_REQUEST) 2911 panic("ehci_device_bulk_start: a request"); 2912 #endif 2913 2914 len = xfer->length; 2915 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 2916 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2917 sqh = epipe->sqh; 2918 2919 epipe->u.bulk.length = len; 2920 2921 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 2922 &dataend); 2923 if (err) { 2924 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 2925 xfer->status = err; 2926 usb_transfer_complete(xfer); 2927 return (err); 2928 } 2929 2930 #ifdef EHCI_DEBUG 2931 if (ehcidebug > 5) { 2932 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 2933 ehci_dump_sqh(sqh); 2934 ehci_dump_sqtds(data); 2935 } 2936 #endif 2937 2938 /* Set up interrupt info. */ 2939 exfer->sqtdstart = data; 2940 exfer->sqtdend = dataend; 2941 #ifdef DIAGNOSTIC 2942 if (!exfer->isdone) { 2943 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 2944 } 2945 exfer->isdone = 0; 2946 #endif 2947 2948 s = splusb(); 2949 ehci_set_qh_qtd(sqh, data); 2950 if (xfer->timeout && !sc->sc_bus.use_polling) { 2951 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2952 ehci_timeout, xfer); 2953 } 2954 ehci_add_intr_list(sc, exfer); 2955 xfer->status = USBD_IN_PROGRESS; 2956 splx(s); 2957 2958 #ifdef EHCI_DEBUG 2959 if (ehcidebug > 10) { 2960 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 2961 delay(10000); 2962 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 2963 ehci_dump_regs(sc); 2964 #if 0 2965 printf("async_head:\n"); 2966 ehci_dump_sqh(sc->sc_async_head); 2967 #endif 2968 printf("sqh:\n"); 2969 ehci_dump_sqh(sqh); 2970 ehci_dump_sqtds(data); 2971 } 2972 #endif 2973 2974 if (sc->sc_bus.use_polling) 2975 ehci_waitintr(sc, xfer); 2976 2977 return (USBD_IN_PROGRESS); 2978 #undef exfer 2979 } 2980 2981 Static void 2982 ehci_device_bulk_abort(usbd_xfer_handle xfer) 2983 { 2984 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 2985 ehci_abort_xfer(xfer, USBD_CANCELLED); 2986 } 2987 2988 /* 2989 * Close a device bulk pipe. 2990 */ 2991 Static void 2992 ehci_device_bulk_close(usbd_pipe_handle pipe) 2993 { 2994 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2995 2996 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 2997 ehci_close_pipe(pipe, sc->sc_async_head); 2998 } 2999 3000 void 3001 ehci_device_bulk_done(usbd_xfer_handle xfer) 3002 { 3003 struct ehci_xfer *ex = EXFER(xfer); 3004 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3005 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3006 3007 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3008 xfer, xfer->actlen)); 3009 3010 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3011 ehci_del_intr_list(ex); /* remove from active list */ 3012 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3013 } 3014 3015 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3016 } 3017 3018 /************************/ 3019 3020 Static usbd_status 3021 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3022 { 3023 struct ehci_soft_islot *isp; 3024 int islot, lev; 3025 3026 /* Find a poll rate that is large enough. */ 3027 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3028 if (EHCI_ILEV_IVAL(lev) <= ival) 3029 break; 3030 3031 /* Pick an interrupt slot at the right level. */ 3032 /* XXX could do better than picking at random */ 3033 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3034 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3035 3036 sqh->islot = islot; 3037 isp = &sc->sc_islots[islot]; 3038 ehci_add_qh(sqh, isp->sqh); 3039 3040 return (USBD_NORMAL_COMPLETION); 3041 } 3042 3043 Static usbd_status 3044 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3045 { 3046 usbd_status err; 3047 3048 /* Insert last in queue. */ 3049 err = usb_insert_transfer(xfer); 3050 if (err) 3051 return (err); 3052 3053 /* 3054 * Pipe isn't running (otherwise err would be USBD_INPROG), 3055 * so start it first. 3056 */ 3057 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3058 } 3059 3060 Static usbd_status 3061 ehci_device_intr_start(usbd_xfer_handle xfer) 3062 { 3063 #define exfer EXFER(xfer) 3064 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3065 usbd_device_handle dev = xfer->pipe->device; 3066 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3067 ehci_soft_qtd_t *data, *dataend; 3068 ehci_soft_qh_t *sqh; 3069 usbd_status err; 3070 int len, isread, endpt; 3071 int s; 3072 3073 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3074 xfer, xfer->length, xfer->flags)); 3075 3076 if (sc->sc_dying) 3077 return (USBD_IOERROR); 3078 3079 #ifdef DIAGNOSTIC 3080 if (xfer->rqflags & URQ_REQUEST) 3081 panic("ehci_device_intr_start: a request"); 3082 #endif 3083 3084 len = xfer->length; 3085 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3086 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3087 sqh = epipe->sqh; 3088 3089 epipe->u.intr.length = len; 3090 3091 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3092 &dataend); 3093 if (err) { 3094 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3095 xfer->status = err; 3096 usb_transfer_complete(xfer); 3097 return (err); 3098 } 3099 3100 #ifdef EHCI_DEBUG 3101 if (ehcidebug > 5) { 3102 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3103 ehci_dump_sqh(sqh); 3104 ehci_dump_sqtds(data); 3105 } 3106 #endif 3107 3108 /* Set up interrupt info. */ 3109 exfer->sqtdstart = data; 3110 exfer->sqtdend = dataend; 3111 #ifdef DIAGNOSTIC 3112 if (!exfer->isdone) { 3113 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3114 } 3115 exfer->isdone = 0; 3116 #endif 3117 3118 s = splusb(); 3119 ehci_set_qh_qtd(sqh, data); 3120 if (xfer->timeout && !sc->sc_bus.use_polling) { 3121 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3122 ehci_timeout, xfer); 3123 } 3124 ehci_add_intr_list(sc, exfer); 3125 xfer->status = USBD_IN_PROGRESS; 3126 splx(s); 3127 3128 #ifdef EHCI_DEBUG 3129 if (ehcidebug > 10) { 3130 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3131 delay(10000); 3132 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3133 ehci_dump_regs(sc); 3134 printf("sqh:\n"); 3135 ehci_dump_sqh(sqh); 3136 ehci_dump_sqtds(data); 3137 } 3138 #endif 3139 3140 if (sc->sc_bus.use_polling) 3141 ehci_waitintr(sc, xfer); 3142 3143 return (USBD_IN_PROGRESS); 3144 #undef exfer 3145 } 3146 3147 Static void 3148 ehci_device_intr_abort(usbd_xfer_handle xfer) 3149 { 3150 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3151 if (xfer->pipe->intrxfer == xfer) { 3152 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3153 xfer->pipe->intrxfer = NULL; 3154 } 3155 ehci_abort_xfer(xfer, USBD_CANCELLED); 3156 } 3157 3158 Static void 3159 ehci_device_intr_close(usbd_pipe_handle pipe) 3160 { 3161 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3162 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3163 struct ehci_soft_islot *isp; 3164 3165 isp = &sc->sc_islots[epipe->sqh->islot]; 3166 ehci_close_pipe(pipe, isp->sqh); 3167 } 3168 3169 Static void 3170 ehci_device_intr_done(usbd_xfer_handle xfer) 3171 { 3172 #define exfer EXFER(xfer) 3173 struct ehci_xfer *ex = EXFER(xfer); 3174 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3175 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3176 ehci_soft_qtd_t *data, *dataend; 3177 ehci_soft_qh_t *sqh; 3178 usbd_status err; 3179 int len, isread, endpt, s; 3180 3181 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3182 xfer, xfer->actlen)); 3183 3184 if (xfer->pipe->repeat) { 3185 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3186 3187 len = epipe->u.intr.length; 3188 xfer->length = len; 3189 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3190 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3191 sqh = epipe->sqh; 3192 3193 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3194 &data, &dataend); 3195 if (err) { 3196 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3197 xfer->status = err; 3198 return; 3199 } 3200 3201 /* Set up interrupt info. */ 3202 exfer->sqtdstart = data; 3203 exfer->sqtdend = dataend; 3204 #ifdef DIAGNOSTIC 3205 if (!exfer->isdone) { 3206 printf("ehci_device_intr_done: not done, ex=%p\n", 3207 exfer); 3208 } 3209 exfer->isdone = 0; 3210 #endif 3211 3212 s = splusb(); 3213 ehci_set_qh_qtd(sqh, data); 3214 if (xfer->timeout && !sc->sc_bus.use_polling) { 3215 usb_callout(xfer->timeout_handle, 3216 mstohz(xfer->timeout), ehci_timeout, xfer); 3217 } 3218 splx(s); 3219 3220 xfer->status = USBD_IN_PROGRESS; 3221 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3222 ehci_del_intr_list(ex); /* remove from active list */ 3223 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3224 } 3225 #undef exfer 3226 } 3227 3228 /************************/ 3229 3230 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; } 3231 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle xfer) { return USBD_IOERROR; } 3232 Static void ehci_device_isoc_abort(usbd_xfer_handle xfer) { } 3233 Static void ehci_device_isoc_close(usbd_pipe_handle pipe) { } 3234 Static void ehci_device_isoc_done(usbd_xfer_handle xfer) { } 3235
Indexes created Thu Oct 02 01:09:59 GMT 2025