ehcireg.h revision 1.26
1 /* $NetBSD: ehcireg.h,v 1.26 2008/01/27 20:06:48 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * The EHCI 0.96 spec can be found at 41 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 42 * and the USB 2.0 spec at 43 * http://www.usb.org/developers/data/usb_20.zip 44 */ 45 46 #ifndef _DEV_PCI_EHCIREG_H_ 47 #define _DEV_PCI_EHCIREG_H_ 48 49 /*** PCI config registers ***/ 50 51 #define PCI_CBMEM 0x10 /* configuration base MEM */ 52 53 #define PCI_INTERFACE_EHCI 0x20 54 55 #define PCI_USBREV 0x60 /* RO USB protocol revision */ 56 #define PCI_USBREV_MASK 0xff 57 #define PCI_USBREV_PRE_1_0 0x00 58 #define PCI_USBREV_1_0 0x10 59 #define PCI_USBREV_1_1 0x11 60 #define PCI_USBREV_2_0 0x20 61 62 #define PCI_EHCI_FLADJ 0x61 /*RW Frame len adj, SOF=59488+6*fladj */ 63 64 #define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */ 65 66 /* Regs at EECP + offset */ 67 #define PCI_EHCI_USBLEGSUP 0x00 68 #define EHCI_LEG_HC_OS_OWNED 0x01000000 69 #define EHCI_LEG_HC_BIOS_OWNED 0x00010000 70 #define PCI_EHCI_USBLEGCTLSTS 0x04 71 #define EHCI_LEG_EXT_SMI_BAR 0x80000000 72 #define EHCI_LEG_EXT_SMI_PCICMD 0x40000000 73 #define EHCI_LEG_EXT_SMI_OS_CHANGE 0x20000000 74 75 #define EHCI_CAP_GET_ID(cap) ((cap) & 0xff) 76 #define EHCI_CAP_GET_NEXT(cap) (((cap) >> 8) & 0xff) 77 #define EHCI_CAP_ID_LEGACY 1 78 79 /*** EHCI capability registers ***/ 80 81 #define EHCI_CAPLENGTH 0x00 /*RO Capability register length field */ 82 /* reserved 0x01 */ 83 #define EHCI_HCIVERSION 0x02 /* RO Interface version number */ 84 85 #define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */ 86 #define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf) 87 #define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000) 88 #define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */ 89 #define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */ 90 #define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */ 91 #define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */ 92 93 #define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */ 94 #define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */ 95 #define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */ 96 #define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */ 97 #define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */ 98 #define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */ 99 100 #define EHCI_HCSP_PORTROUTE 0x0c /*RO Companion port route description */ 101 102 /* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */ 103 #define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */ 104 #define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */ 105 #define EHCI_CMD_ITC_1 0x00010000 106 #define EHCI_CMD_ITC_2 0x00020000 107 #define EHCI_CMD_ITC_4 0x00040000 108 #define EHCI_CMD_ITC_8 0x00080000 109 #define EHCI_CMD_ITC_16 0x00100000 110 #define EHCI_CMD_ITC_32 0x00200000 111 #define EHCI_CMD_ITC_64 0x00400000 112 #define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */ 113 #define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */ 114 #define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */ 115 #define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door bell */ 116 #define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */ 117 #define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */ 118 #define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */ 119 #define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */ 120 #define EHCI_CMD_HCRESET 0x00000002 /* RW reset */ 121 #define EHCI_CMD_RS 0x00000001 /* RW run/stop */ 122 123 #define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */ 124 #define EHCI_STS_ASS 0x00008000 /* RO async sched status */ 125 #define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */ 126 #define EHCI_STS_REC 0x00002000 /* RO reclamation */ 127 #define EHCI_STS_HCH 0x00001000 /* RO host controller halted */ 128 #define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */ 129 #define EHCI_STS_HSE 0x00000010 /* RWC host system error */ 130 #define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */ 131 #define EHCI_STS_PCD 0x00000004 /* RWC port change detect */ 132 #define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */ 133 #define EHCI_STS_INT 0x00000001 /* RWC interrupt */ 134 #define EHCI_STS_INTRS(x) ((x) & 0x3f) 135 136 #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT) 137 138 #define EHCI_USBINTR 0x08 /* RW Interrupt register */ 139 #define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance ena */ 140 #define EHCI_INTR_HSEE 0x00000010 /* host system error ena */ 141 #define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */ 142 #define EHCI_INTR_PCIE 0x00000004 /* port change ena */ 143 #define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */ 144 #define EHCI_INTR_UIE 0x00000001 /* USB intr ena */ 145 146 #define EHCI_FRINDEX 0x0c /* RW Frame Index register */ 147 148 #define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */ 149 150 #define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */ 151 #define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */ 152 153 #define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */ 154 #define EHCI_CONF_CF 0x00000001 /* RW configure flag */ 155 156 #define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */ 157 #define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */ 158 #define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */ 159 #define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */ 160 #define EHCI_PS_PTC 0x000f0000 /* RW port test control */ 161 #define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */ 162 #define EHCI_PS_PO 0x00002000 /* RW port owner */ 163 #define EHCI_PS_PP 0x00001000 /* RW,RO port power */ 164 #define EHCI_PS_LS 0x00000c00 /* RO line status */ 165 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400) 166 #define EHCI_PS_PR 0x00000100 /* RW port reset */ 167 #define EHCI_PS_SUSP 0x00000080 /* RW suspend */ 168 #define EHCI_PS_FPR 0x00000040 /* RW force port resume */ 169 #define EHCI_PS_OCC 0x00000020 /* RWC over current change */ 170 #define EHCI_PS_OCA 0x00000010 /* RO over current active */ 171 #define EHCI_PS_PEC 0x00000008 /* RWC port enable change */ 172 #define EHCI_PS_PE 0x00000004 /* RW port enable */ 173 #define EHCI_PS_CSC 0x00000002 /* RWC connect status change */ 174 #define EHCI_PS_CS 0x00000001 /* RO connect status */ 175 #define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC) 176 177 #define EHCI_PORT_RESET_COMPLETE 2 /* ms */ 178 179 #define EHCI_FLALIGN_ALIGN 0x1000 180 #define EHCI_MAX_PORTS 16 /* only 4 bits available in EHCI_HCS_N_PORTS */ 181 182 /* No data structure may cross a page boundary. */ 183 #define EHCI_PAGE_SIZE 0x1000 184 #define EHCI_PAGE(x) ((x) &~ 0xfff) 185 #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff) 186 187 typedef u_int32_t ehci_link_t; 188 #define EHCI_LINK_TERMINATE 0x00000001 189 #define EHCI_LINK_TYPE(x) ((x) & 0x00000006) 190 #define EHCI_LINK_ITD 0x0 191 #define EHCI_LINK_QH 0x2 192 #define EHCI_LINK_SITD 0x4 193 #define EHCI_LINK_FSTN 0x6 194 #define EHCI_LINK_ADDR(x) ((x) &~ 0x1f) 195 196 typedef u_int32_t ehci_physaddr_t; 197 198 /* Isochronous Transfer Descriptor */ 199 typedef struct { 200 volatile ehci_link_t itd_next; 201 /* XXX many more */ 202 } ehci_itd_t; 203 #define EHCI_ITD_ALIGN 32 204 205 /* Split Transaction Isochronous Transfer Descriptor */ 206 typedef struct { 207 volatile ehci_link_t sitd_next; 208 /* XXX many more */ 209 } ehci_sitd_t; 210 #define EHCI_SITD_ALIGN 32 211 212 /* Queue Element Transfer Descriptor */ 213 #define EHCI_QTD_NBUFFERS 5 214 typedef struct { 215 volatile ehci_link_t qtd_next; 216 volatile ehci_link_t qtd_altnext; 217 volatile u_int32_t qtd_status; 218 #define EHCI_QTD_GET_STATUS(x) (((x) >> 0) & 0xff) 219 #define EHCI_QTD_SET_STATUS(x) ((x) << 0) 220 #define EHCI_QTD_ACTIVE 0x80 221 #define EHCI_QTD_HALTED 0x40 222 #define EHCI_QTD_BUFERR 0x20 223 #define EHCI_QTD_BABBLE 0x10 224 #define EHCI_QTD_XACTERR 0x08 225 #define EHCI_QTD_MISSEDMICRO 0x04 226 #define EHCI_QTD_SPLITXSTATE 0x02 227 #define EHCI_QTD_PINGSTATE 0x01 228 #define EHCI_QTD_STATERRS 0x3c 229 #define EHCI_QTD_GET_PID(x) (((x) >> 8) & 0x3) 230 #define EHCI_QTD_SET_PID(x) ((x) << 8) 231 #define EHCI_QTD_PID_OUT 0x0 232 #define EHCI_QTD_PID_IN 0x1 233 #define EHCI_QTD_PID_SETUP 0x2 234 #define EHCI_QTD_GET_CERR(x) (((x) >> 10) & 0x3) 235 #define EHCI_QTD_SET_CERR(x) ((x) << 10) 236 #define EHCI_QTD_GET_C_PAGE(x) (((x) >> 12) & 0x7) 237 #define EHCI_QTD_SET_C_PAGE(x) ((x) << 12) 238 #define EHCI_QTD_GET_IOC(x) (((x) >> 15) & 0x1) 239 #define EHCI_QTD_IOC 0x00008000 240 #define EHCI_QTD_GET_BYTES(x) (((x) >> 16) & 0x7fff) 241 #define EHCI_QTD_SET_BYTES(x) ((x) << 16) 242 #define EHCI_QTD_GET_TOGGLE(x) (((x) >> 31) & 0x1) 243 #define EHCI_QTD_SET_TOGGLE(x) ((x) << 31) 244 #define EHCI_QTD_TOGGLE_MASK 0x80000000 245 volatile ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS]; 246 volatile ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS]; 247 } ehci_qtd_t; 248 #define EHCI_QTD_ALIGN 32 249 250 /* Queue Head */ 251 typedef struct { 252 volatile ehci_link_t qh_link; 253 volatile u_int32_t qh_endp; 254 #define EHCI_QH_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */ 255 #define EHCI_QH_SET_ADDR(x) (x) 256 #define EHCI_QH_ADDRMASK 0x0000007f 257 #define EHCI_QH_GET_INACT(x) (((x) >> 7) & 0x01) /* inactivate on next */ 258 #define EHCI_QH_INACT 0x00000080 259 #define EHCI_QH_GET_ENDPT(x) (((x) >> 8) & 0x0f) /* endpoint no */ 260 #define EHCI_QH_SET_ENDPT(x) ((x) << 8) 261 #define EHCI_QH_GET_EPS(x) (((x) >> 12) & 0x03) /* endpoint speed */ 262 #define EHCI_QH_SET_EPS(x) ((x) << 12) 263 #define EHCI_QH_SPEED_FULL 0x0 264 #define EHCI_QH_SPEED_LOW 0x1 265 #define EHCI_QH_SPEED_HIGH 0x2 266 #define EHCI_QH_GET_DTC(x) (((x) >> 14) & 0x01) /* data toggle control */ 267 #define EHCI_QH_DTC 0x00004000 268 #define EHCI_QH_GET_HRECL(x) (((x) >> 15) & 0x01) /* head of reclamation */ 269 #define EHCI_QH_HRECL 0x00008000 270 #define EHCI_QH_GET_MPL(x) (((x) >> 16) & 0x7ff) /* max packet len */ 271 #define EHCI_QH_SET_MPL(x) ((x) << 16) 272 #define EHCI_QH_MPLMASK 0x07ff0000 273 #define EHCI_QH_GET_CTL(x) (((x) >> 27) & 0x01) /* control endpoint */ 274 #define EHCI_QH_CTL 0x08000000 275 #define EHCI_QH_GET_NRL(x) (((x) >> 28) & 0x0f) /* NAK reload */ 276 #define EHCI_QH_SET_NRL(x) ((x) << 28) 277 volatile u_int32_t qh_endphub; 278 #define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */ 279 #define EHCI_QH_SET_SMASK(x) ((x) << 0) 280 #define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */ 281 #define EHCI_QH_SET_CMASK(x) ((x) << 8) 282 #define EHCI_QH_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */ 283 #define EHCI_QH_SET_HUBA(x) ((x) << 16) 284 #define EHCI_QH_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */ 285 #define EHCI_QH_SET_PORT(x) ((x) << 23) 286 #define EHCI_QH_GET_MULT(x) (((x) >> 30) & 0x03) /* pipe multiplier */ 287 #define EHCI_QH_SET_MULT(x) ((x) << 30) 288 volatile ehci_link_t qh_curqtd; 289 ehci_qtd_t qh_qtd; 290 } ehci_qh_t; 291 #define EHCI_QH_ALIGN 32 292 293 /* Periodic Frame Span Traversal Node */ 294 typedef struct { 295 volatile ehci_link_t fstn_link; 296 volatile ehci_link_t fstn_back; 297 } ehci_fstn_t; 298 #define EHCI_FSTN_ALIGN 32 299 300 #endif /* _DEV_PCI_EHCIREG_H_ */ 301
Indexes created Thu Sep 25 16:09:42 GMT 2025