ehcireg.h revision 1.35
1 /* $NetBSD: ehcireg.h,v 1.35 2015/09/05 06:13:54 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * The EHCI 0.96 spec can be found at 34 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 35 * and the USB 2.0 spec at 36 * http://www.usb.org/developers/data/usb_20.zip 37 */ 38 39 #ifndef _DEV_USB_EHCIREG_H_ 40 #define _DEV_USB_EHCIREG_H_ 41 42 /*** PCI config registers ***/ 43 44 #define PCI_CBMEM 0x10 /* configuration base MEM */ 45 46 #define PCI_INTERFACE_EHCI 0x20 47 48 #define PCI_USBREV 0x60 /* RO USB protocol revision */ 49 #define PCI_USBREV_MASK 0xff 50 #define PCI_USBREV_PRE_1_0 0x00 51 #define PCI_USBREV_1_0 0x10 52 #define PCI_USBREV_1_1 0x11 53 #define PCI_USBREV_2_0 0x20 54 55 #define PCI_EHCI_FLADJ 0x61 /*RW Frame len adj, SOF=59488+6*fladj */ 56 57 #define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */ 58 59 /* Regs at EECP + offset */ 60 #define PCI_EHCI_USBLEGSUP 0x00 61 #define EHCI_LEG_HC_OS_OWNED 0x01000000 62 #define EHCI_LEG_HC_BIOS_OWNED 0x00010000 63 #define PCI_EHCI_USBLEGCTLSTS 0x04 64 #define EHCI_LEG_EXT_SMI_BAR 0x80000000 65 #define EHCI_LEG_EXT_SMI_PCICMD 0x40000000 66 #define EHCI_LEG_EXT_SMI_OS_CHANGE 0x20000000 67 68 #define EHCI_CAP_GET_ID(cap) ((cap) & 0xff) 69 #define EHCI_CAP_GET_NEXT(cap) (((cap) >> 8) & 0xff) 70 #define EHCI_CAP_ID_LEGACY 1 71 72 /*** EHCI capability registers ***/ 73 74 #define EHCI_CAPLENGTH 0x00 /*RO Capability register length field */ 75 /* reserved 0x01 */ 76 #define EHCI_HCIVERSION 0x02 /* RO Interface version number */ 77 78 #define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */ 79 #define EHCI_HCS_N_TT(x) (((x) >> 20) & 0xf) /* # of xacts xlater ETTF */ 80 #define EHCI_HCS_N_PTT(x) (((x) >> 20) & 0xf) /* ports per xlater ETTF */ 81 #define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf) 82 #define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000) 83 #define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */ 84 #define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */ 85 #define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */ 86 #define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */ 87 88 #define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */ 89 #define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */ 90 #define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */ 91 #define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */ 92 #define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */ 93 #define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */ 94 95 #define EHCI_HCSP_PORTROUTE 0x0c /*RO Companion port route description */ 96 97 /* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */ 98 #define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */ 99 #define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */ 100 #define EHCI_CMD_ITC_1 0x00010000 101 #define EHCI_CMD_ITC_2 0x00020000 102 #define EHCI_CMD_ITC_4 0x00040000 103 #define EHCI_CMD_ITC_8 0x00080000 104 #define EHCI_CMD_ITC_16 0x00100000 105 #define EHCI_CMD_ITC_32 0x00200000 106 #define EHCI_CMD_ITC_64 0x00400000 107 #define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */ 108 #define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */ 109 #define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */ 110 #define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door bell */ 111 #define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */ 112 #define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */ 113 #define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */ 114 #define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */ 115 #define EHCI_CMD_HCRESET 0x00000002 /* RW reset */ 116 #define EHCI_CMD_RS 0x00000001 /* RW run/stop */ 117 118 #define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */ 119 #define EHCI_STS_ASS 0x00008000 /* RO async sched status */ 120 #define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */ 121 #define EHCI_STS_REC 0x00002000 /* RO reclamation */ 122 #define EHCI_STS_HCH 0x00001000 /* RO host controller halted */ 123 #define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */ 124 #define EHCI_STS_HSE 0x00000010 /* RWC host system error */ 125 #define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */ 126 #define EHCI_STS_PCD 0x00000004 /* RWC port change detect */ 127 #define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */ 128 #define EHCI_STS_INT 0x00000001 /* RWC interrupt */ 129 #define EHCI_STS_INTRS(x) ((x) & 0x3f) 130 131 #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT) 132 133 #define EHCI_USBINTR 0x08 /* RW Interrupt register */ 134 #define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance ena */ 135 #define EHCI_INTR_HSEE 0x00000010 /* host system error ena */ 136 #define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */ 137 #define EHCI_INTR_PCIE 0x00000004 /* port change ena */ 138 #define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */ 139 #define EHCI_INTR_UIE 0x00000001 /* USB intr ena */ 140 141 #define EHCI_FRINDEX 0x0c /* RW Frame Index register */ 142 143 #define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */ 144 145 #define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */ 146 #define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */ 147 148 #define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */ 149 #define EHCI_CONF_CF 0x00000001 /* RW configure flag */ 150 151 #define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */ 152 #define EHCI_PS_PSPD 0x0C000000 /* RO port speed (ETTF) */ 153 #define EHCI_PS_PSPD_FS 0x00000000 /* Full speed (ETTF) */ 154 #define EHCI_PS_PSPD_LS 0x04000000 /* Low speed (ETTF) */ 155 #define EHCI_PS_PSPD_HS 0x08000000 /* High speed (ETTF) */ 156 #define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */ 157 #define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */ 158 #define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */ 159 #define EHCI_PS_PTC 0x000f0000 /* RW port test control */ 160 #define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */ 161 #define EHCI_PS_PO 0x00002000 /* RW port owner */ 162 #define EHCI_PS_PP 0x00001000 /* RW,RO port power */ 163 #define EHCI_PS_LS 0x00000c00 /* RO line status */ 164 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400) 165 #define EHCI_PS_PR 0x00000100 /* RW port reset */ 166 #define EHCI_PS_SUSP 0x00000080 /* RW suspend */ 167 #define EHCI_PS_FPR 0x00000040 /* RW force port resume */ 168 #define EHCI_PS_OCC 0x00000020 /* RWC over current change */ 169 #define EHCI_PS_OCA 0x00000010 /* RO over current active */ 170 #define EHCI_PS_PEC 0x00000008 /* RWC port enable change */ 171 #define EHCI_PS_PE 0x00000004 /* RW port enable */ 172 #define EHCI_PS_CSC 0x00000002 /* RWC connect status change */ 173 #define EHCI_PS_CS 0x00000001 /* RO connect status */ 174 #define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC) 175 176 #define EHCI_PORT_RESET_COMPLETE 2 /* ms */ 177 178 #define EHCI_USBMODE 0xa8 /* USB Device mode */ 179 #define EHCI_USBMODE_SDIS __BIT(4) /* Stream disable mode 1=act */ 180 #define EHCI_USBMODE_SLOM __BIT(3) /* setup lockouts on */ 181 #define EHCI_USBMODE_ES __BIT(2) /* Endian Select ES=1 */ 182 #define EHCI_USBMODE_CM __BITS(0,1) /* Controller Mode */ 183 #define EHCI_USBMODE_CM_IDLE 0x00 /* Idle (combo host/device) */ 184 #define EHCI_USBMODE_CM_DEV 0x02 /* Device Controller */ 185 #define EHCI_USBMODE_CM_HOST 0x03 /* Host Controller */ 186 187 #define EHCI_FLALIGN_ALIGN 0x1000 188 #define EHCI_MAX_PORTS 16 /* only 4 bits available in EHCI_HCS_N_PORTS */ 189 190 /* No data structure may cross a page boundary. */ 191 #define EHCI_PAGE_SIZE 0x1000 192 #define EHCI_PAGE(x) ((x) &~ 0xfff) 193 #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff) 194 195 typedef u_int32_t ehci_link_t; 196 #define EHCI_LINK_TERMINATE 0x00000001 197 #define EHCI_LINK_TYPE(x) ((x) & 0x00000006) 198 #define EHCI_LINK_ITD 0x0 199 #define EHCI_LINK_QH 0x2 200 #define EHCI_LINK_SITD 0x4 201 #define EHCI_LINK_FSTN 0x6 202 #define EHCI_LINK_ADDR(x) ((x) &~ 0x1f) 203 204 typedef u_int32_t ehci_physaddr_t; 205 206 typedef u_int32_t ehci_isoc_trans_t; 207 typedef u_int32_t ehci_isoc_bufr_ptr_t; 208 209 /* Isochronous Transfer Descriptor */ 210 #define EHCI_ITD_NUFRAMES USB_UFRAMES_PER_FRAME 211 #define EHCI_ITD_NBUFFERS 7 212 typedef struct { 213 volatile ehci_link_t itd_next; 214 volatile ehci_isoc_trans_t itd_ctl[EHCI_ITD_NUFRAMES]; 215 #define EHCI_ITD_GET_STATUS(x) (((x) >> 28) & 0xf) 216 #define EHCI_ITD_SET_STATUS(x) (((x) & 0xf) << 28) 217 #define EHCI_ITD_ACTIVE 0x80000000 218 #define EHCI_ITD_BUF_ERR 0x40000000 219 #define EHCI_ITD_BABBLE 0x20000000 220 #define EHCI_ITD_ERROR 0x10000000 221 #define EHCI_ITD_GET_LEN(x) (((x) >> 16) & 0xfff) 222 #define EHCI_ITD_SET_LEN(x) (((x) & 0xfff) << 16) 223 #define EHCI_ITD_IOC 0x8000 224 #define EHCI_ITD_GET_IOC(x) (((x) >> 15) & 1) 225 #define EHCI_ITD_SET_IOC(x) (((x) << 15) & EHCI_ITD_IOC) 226 #define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0x7) 227 #define EHCI_ITD_SET_PG(x) (((x) & 0x7) << 12) 228 #define EHCI_ITD_GET_OFFS(x) (((x) >> 0) & 0xfff) 229 #define EHCI_ITD_SET_OFFS(x) (((x) & 0xfff) << 0) 230 volatile ehci_isoc_bufr_ptr_t itd_bufr[EHCI_ITD_NBUFFERS]; 231 #define EHCI_ITD_GET_BPTR(x) ((x) & 0xfffff000) 232 #define EHCI_ITD_SET_BPTR(x) ((x) & 0xfffff000) 233 #define EHCI_ITD_GET_EP(x) (((x) >> 8) & 0xf) 234 #define EHCI_ITD_SET_EP(x) (((x) & 0xf) << 8) 235 #define EHCI_ITD_GET_DADDR(x) ((x) & 0x7f) 236 #define EHCI_ITD_SET_DADDR(x) ((x) & 0x7f) 237 #define EHCI_ITD_GET_DIR(x) (((x) >> 11) & 1) 238 #define EHCI_ITD_SET_DIR(x) (((x) & 1) << 11) 239 #define EHCI_ITD_GET_MAXPKT(x) ((x) & 0x7ff) 240 #define EHCI_ITD_SET_MAXPKT(x) ((x) & 0x7ff) 241 #define EHCI_ITD_GET_MULTI(x) ((x) & 0x3) 242 #define EHCI_ITD_SET_MULTI(x) ((x) & 0x3) 243 volatile ehci_isoc_bufr_ptr_t itd_bufr_hi[EHCI_ITD_NBUFFERS]; 244 } ehci_itd_t; 245 #define EHCI_ITD_ALIGN 32 246 247 /* Split Transaction Isochronous Transfer Descriptor */ 248 typedef struct { 249 volatile ehci_link_t sitd_next; 250 /* XXX many more */ 251 } ehci_sitd_t; 252 #define EHCI_SITD_ALIGN 32 253 254 /* Queue Element Transfer Descriptor */ 255 #define EHCI_QTD_NBUFFERS 5 256 typedef struct { 257 volatile ehci_link_t qtd_next; 258 volatile ehci_link_t qtd_altnext; 259 volatile u_int32_t qtd_status; 260 #define EHCI_QTD_GET_STATUS(x) (((x) >> 0) & 0xff) 261 #define EHCI_QTD_SET_STATUS(x) ((x) << 0) 262 #define EHCI_QTD_ACTIVE 0x80 263 #define EHCI_QTD_HALTED 0x40 264 #define EHCI_QTD_BUFERR 0x20 265 #define EHCI_QTD_BABBLE 0x10 266 #define EHCI_QTD_XACTERR 0x08 267 #define EHCI_QTD_MISSEDMICRO 0x04 268 #define EHCI_QTD_SPLITXSTATE 0x02 269 #define EHCI_QTD_PINGSTATE 0x01 270 #define EHCI_QTD_STATERRS 0x3c 271 #define EHCI_QTD_GET_PID(x) (((x) >> 8) & 0x3) 272 #define EHCI_QTD_SET_PID(x) ((x) << 8) 273 #define EHCI_QTD_PID_OUT 0x0 274 #define EHCI_QTD_PID_IN 0x1 275 #define EHCI_QTD_PID_SETUP 0x2 276 #define EHCI_QTD_GET_CERR(x) (((x) >> 10) & 0x3) 277 #define EHCI_QTD_SET_CERR(x) ((x) << 10) 278 #define EHCI_QTD_GET_C_PAGE(x) (((x) >> 12) & 0x7) 279 #define EHCI_QTD_SET_C_PAGE(x) ((x) << 12) 280 #define EHCI_QTD_GET_IOC(x) (((x) >> 15) & 0x1) 281 #define EHCI_QTD_IOC 0x00008000 282 #define EHCI_QTD_GET_BYTES(x) (((x) >> 16) & 0x7fff) 283 #define EHCI_QTD_SET_BYTES(x) ((x) << 16) 284 #define EHCI_QTD_GET_TOGGLE(x) (((x) >> 31) & 0x1) 285 #define EHCI_QTD_SET_TOGGLE(x) ((x) << 31) 286 #define EHCI_QTD_TOGGLE_MASK 0x80000000 287 volatile ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS]; 288 volatile ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS]; 289 } ehci_qtd_t; 290 #define EHCI_QTD_ALIGN 32 291 292 /* Queue Head */ 293 typedef struct { 294 volatile ehci_link_t qh_link; 295 volatile u_int32_t qh_endp; 296 #define EHCI_QH_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */ 297 #define EHCI_QH_SET_ADDR(x) (x) 298 #define EHCI_QH_ADDRMASK 0x0000007f 299 #define EHCI_QH_GET_INACT(x) (((x) >> 7) & 0x01) /* inactivate on next */ 300 #define EHCI_QH_INACT 0x00000080 301 #define EHCI_QH_GET_ENDPT(x) (((x) >> 8) & 0x0f) /* endpoint no */ 302 #define EHCI_QH_SET_ENDPT(x) ((x) << 8) 303 #define EHCI_QH_GET_EPS(x) (((x) >> 12) & 0x03) /* endpoint speed */ 304 #define EHCI_QH_SET_EPS(x) ((x) << 12) 305 #define EHCI_QH_SPEED_FULL 0x0 306 #define EHCI_QH_SPEED_LOW 0x1 307 #define EHCI_QH_SPEED_HIGH 0x2 308 #define EHCI_QH_GET_DTC(x) (((x) >> 14) & 0x01) /* data toggle control */ 309 #define EHCI_QH_DTC 0x00004000 310 #define EHCI_QH_GET_HRECL(x) (((x) >> 15) & 0x01) /* head of reclamation */ 311 #define EHCI_QH_HRECL 0x00008000 312 #define EHCI_QH_GET_MPL(x) (((x) >> 16) & 0x7ff) /* max packet len */ 313 #define EHCI_QH_SET_MPL(x) ((x) << 16) 314 #define EHCI_QH_MPLMASK 0x07ff0000 315 #define EHCI_QH_GET_CTL(x) (((x) >> 27) & 0x01) /* control endpoint */ 316 #define EHCI_QH_CTL 0x08000000 317 #define EHCI_QH_GET_NRL(x) (((x) >> 28) & 0x0f) /* NAK reload */ 318 #define EHCI_QH_SET_NRL(x) ((x) << 28) 319 volatile u_int32_t qh_endphub; 320 #define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */ 321 #define EHCI_QH_SET_SMASK(x) ((x) << 0) 322 #define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */ 323 #define EHCI_QH_SET_CMASK(x) ((x) << 8) 324 #define EHCI_QH_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */ 325 #define EHCI_QH_SET_HUBA(x) ((x) << 16) 326 #define EHCI_QH_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */ 327 #define EHCI_QH_SET_PORT(x) ((x) << 23) 328 #define EHCI_QH_GET_MULT(x) (((x) >> 30) & 0x03) /* pipe multiplier */ 329 #define EHCI_QH_SET_MULT(x) ((x) << 30) 330 volatile ehci_link_t qh_curqtd; 331 ehci_qtd_t qh_qtd; 332 } ehci_qh_t; 333 #define EHCI_QH_ALIGN 32 334 335 /* Periodic Frame Span Traversal Node */ 336 typedef struct { 337 volatile ehci_link_t fstn_link; 338 volatile ehci_link_t fstn_back; 339 } ehci_fstn_t; 340 #define EHCI_FSTN_ALIGN 32 341 342 /* Debug Port */ 343 #define PCI_CAP_DEBUGPORT_OFFSET __BITS(28,16) 344 #define PCI_CAP_DEBUGPORT_BAR __BITS(31,29) 345 /* Debug Port Registers, offset into DEBUGPORT_BAR at DEBUGPORT_OFFSET */ 346 #define EHCI_DEBUG_SC 0x00 347 /* Status/Control Register */ 348 #define EHCI_DSC_DATA_LENGTH __BITS(3,0) 349 #define EHCI_DSC_WRITE __BIT(4) 350 #define EHCI_DSC_GO __BIT(5) 351 #define EHCI_DSC_ERROR __BIT(6) 352 #define EHCI_DSC_EXCEPTION __BITS(9,7) 353 #define EHCI_DSC_EXCEPTION_NONE 0 354 #define EHCI_DSC_EXCEPTION_XACT 1 355 #define EHCI_DSC_EXCEPTION_HW 2 356 #define EHCI_DSC_IN_USE __BIT(10) 357 #define EHCI_DSC_DONE __BIT(16) 358 #define EHCI_DSC_ENABLED __BIT(28) 359 #define EHCI_DSC_OWNER __BIT(30) 360 #define EHCI_DEBUG_UPR 0x04 361 /* USB PIDs Register */ 362 #define EHCI_DPR_TOKEN __BITS(7,0) 363 #define EHCI_DPR_SEND __BITS(15,8) 364 #define EHCI_DPR_RECEIVED __BITS(23,16) 365 /* Data Registers */ 366 #define EHCI_DEBUG_DATA0123 0x08 367 #define EHCI_DEBUG_DATA4567 0x0c 368 #define EHCI_DEBUG_DAR 0x10 369 /* Device Address Register */ 370 #define EHCI_DAR_ENDPOINT __BITS(3,0) 371 #define EHCI_DAR_ADDRESS __BITS(14,8) 372 373 #endif /* _DEV_USB_EHCIREG_H_ */ 374
Indexes created Fri Sep 26 20:09:58 GMT 2025