ehcivar.h revision 1.41
1 /* $NetBSD: ehcivar.h,v 1.41 2013/01/29 00:00:15 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _EHCIVAR_H_ 33 #define _EHCIVAR_H_ 34 35 #include <sys/pool.h> 36 37 typedef struct ehci_soft_qtd { 38 ehci_qtd_t qtd; 39 struct ehci_soft_qtd *nextqtd; /* mirrors nextqtd in TD */ 40 ehci_physaddr_t physaddr; 41 usb_dma_t dma; /* qTD's DMA infos */ 42 int offs; /* qTD's offset in usb_dma_t */ 43 usbd_xfer_handle xfer; 44 LIST_ENTRY(ehci_soft_qtd) hnext; 45 u_int16_t len; 46 } ehci_soft_qtd_t; 47 #define EHCI_SQTD_SIZE ((sizeof (struct ehci_soft_qtd) + EHCI_QTD_ALIGN - 1) / EHCI_QTD_ALIGN * EHCI_QTD_ALIGN) 48 #define EHCI_SQTD_CHUNK (EHCI_PAGE_SIZE / EHCI_SQTD_SIZE) 49 50 typedef struct ehci_soft_qh { 51 ehci_qh_t qh; 52 struct ehci_soft_qh *next; 53 struct ehci_soft_qtd *sqtd; 54 ehci_physaddr_t physaddr; 55 usb_dma_t dma; /* QH's DMA infos */ 56 int offs; /* QH's offset in usb_dma_t */ 57 int islot; 58 } ehci_soft_qh_t; 59 #define EHCI_SQH_SIZE ((sizeof (struct ehci_soft_qh) + EHCI_QH_ALIGN - 1) / EHCI_QH_ALIGN * EHCI_QH_ALIGN) 60 #define EHCI_SQH_CHUNK (EHCI_PAGE_SIZE / EHCI_SQH_SIZE) 61 62 typedef struct ehci_soft_itd { 63 ehci_itd_t itd; 64 union { 65 struct { 66 /* soft_itds links in a periodic frame*/ 67 struct ehci_soft_itd *next; 68 struct ehci_soft_itd *prev; 69 } frame_list; 70 /* circular list of free itds */ 71 LIST_ENTRY(ehci_soft_itd) free_list; 72 } u; 73 struct ehci_soft_itd *xfer_next; /* Next soft_itd in xfer */ 74 ehci_physaddr_t physaddr; 75 usb_dma_t dma; 76 int offs; 77 int slot; 78 struct timeval t; /* store free time */ 79 } ehci_soft_itd_t; 80 #define EHCI_ITD_SIZE ((sizeof(struct ehci_soft_itd) + EHCI_QH_ALIGN - 1) / EHCI_ITD_ALIGN * EHCI_ITD_ALIGN) 81 #define EHCI_ITD_CHUNK (EHCI_PAGE_SIZE / EHCI_ITD_SIZE) 82 83 struct ehci_xfer { 84 struct usbd_xfer xfer; 85 struct usb_task abort_task; 86 TAILQ_ENTRY(ehci_xfer) inext; /* list of active xfers */ 87 ehci_soft_qtd_t *sqtdstart; 88 ehci_soft_qtd_t *sqtdend; 89 ehci_soft_itd_t *itdstart; 90 ehci_soft_itd_t *itdend; 91 u_int isoc_len; 92 int isdone; /* used only when DIAGNOSTIC is defined */ 93 }; 94 #define EXFER(xfer) ((struct ehci_xfer *)(xfer)) 95 96 /* Information about an entry in the interrupt list. */ 97 struct ehci_soft_islot { 98 ehci_soft_qh_t *sqh; /* Queue Head. */ 99 }; 100 101 #define EHCI_FRAMELIST_MAXCOUNT 1024 102 #define EHCI_IPOLLRATES 8 /* Poll rates (1ms, 2, 4, 8 .. 128) */ 103 #define EHCI_INTRQHS ((1 << EHCI_IPOLLRATES) - 1) 104 #define EHCI_MAX_POLLRATE (1 << (EHCI_IPOLLRATES - 1)) 105 #define EHCI_IQHIDX(lev, pos) \ 106 ((((pos) & ((1 << (lev)) - 1)) | (1 << (lev))) - 1) 107 #define EHCI_ILEV_IVAL(lev) (1 << (lev)) 108 109 110 #define EHCI_HASH_SIZE 128 111 #define EHCI_COMPANION_MAX 8 112 113 #define EHCI_FREE_LIST_INTERVAL 100 114 115 typedef struct ehci_softc { 116 device_t sc_dev; 117 kmutex_t sc_lock; 118 kmutex_t sc_intr_lock; 119 kcondvar_t sc_doorbell; 120 void *sc_doorbell_si; 121 void *sc_pcd_si; 122 struct usbd_bus sc_bus; 123 bus_space_tag_t iot; 124 bus_space_handle_t ioh; 125 bus_size_t sc_size; 126 u_int sc_offs; /* offset to operational regs */ 127 int sc_flags; /* misc flags */ 128 #define EHCIF_DROPPED_INTR_WORKAROUND 0x01 129 #define EHCIF_ETTF 0x02 /* Emb. Transaction Translater func. */ 130 131 char sc_vendor[32]; /* vendor string for root hub */ 132 int sc_id_vendor; /* vendor ID for root hub */ 133 134 u_int32_t sc_cmd; /* shadow of cmd reg during suspend */ 135 136 u_int sc_ncomp; 137 u_int sc_npcomp; 138 device_t sc_comps[EHCI_COMPANION_MAX]; 139 140 usb_dma_t sc_fldma; 141 ehci_link_t *sc_flist; 142 u_int sc_flsize; 143 u_int sc_rand; /* XXX need proper intr scheduling */ 144 145 struct ehci_soft_islot sc_islots[EHCI_INTRQHS]; 146 147 /* jcmm - an array matching sc_flist, but with software pointers, 148 * not hardware address pointers 149 */ 150 struct ehci_soft_itd **sc_softitds; 151 152 TAILQ_HEAD(, ehci_xfer) sc_intrhead; 153 154 ehci_soft_qh_t *sc_freeqhs; 155 ehci_soft_qtd_t *sc_freeqtds; 156 LIST_HEAD(sc_freeitds, ehci_soft_itd) sc_freeitds; 157 158 int sc_noport; 159 u_int8_t sc_hasppc; /* has Port Power Control */ 160 u_int8_t sc_addr; /* device address */ 161 u_int8_t sc_conf; /* device configuration */ 162 usbd_xfer_handle sc_intrxfer; 163 char sc_isreset[EHCI_MAX_PORTS]; 164 char sc_softwake; 165 kcondvar_t sc_softwake_cv; 166 167 u_int32_t sc_eintrs; 168 ehci_soft_qh_t *sc_async_head; 169 170 pool_cache_t sc_xferpool; /* free xfer pool */ 171 172 struct callout sc_tmo_intrlist; 173 174 device_t sc_child; /* /dev/usb# device */ 175 char sc_dying; 176 struct usb_dma_reserve sc_dma_reserve; 177 178 void (*sc_vendor_init)(struct ehci_softc *); 179 int (*sc_vendor_port_status)(struct ehci_softc *, uint32_t, int); 180 } ehci_softc_t; 181 182 #define EREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (a)) 183 #define EREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (a)) 184 #define EREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (a)) 185 #define EWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (a), (x)) 186 #define EWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (a), (x)) 187 #define EWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (a), (x)) 188 #define EOREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a)) 189 #define EOREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a)) 190 #define EOREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a)) 191 #define EOWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x)) 192 #define EOWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x)) 193 #define EOWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x)) 194 195 usbd_status ehci_init(ehci_softc_t *); 196 int ehci_intr(void *); 197 int ehci_detach(ehci_softc_t *, int); 198 int ehci_activate(device_t, enum devact); 199 void ehci_childdet(device_t, device_t); 200 bool ehci_suspend(device_t, const pmf_qual_t *); 201 bool ehci_resume(device_t, const pmf_qual_t *); 202 bool ehci_shutdown(device_t, int); 203 204 #endif /* _EHCIVAR_H_ */ 205
Indexes created Wed Sep 24 15:09:51 GMT 2025