ehcivar.h revision 1.42.14.5
1 /* $NetBSD: ehcivar.h,v 1.42.14.5 2014/12/05 13:23:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _EHCIVAR_H_ 33 #define _EHCIVAR_H_ 34 35 #include <sys/pool.h> 36 37 typedef struct ehci_soft_qtd { 38 ehci_qtd_t qtd; 39 struct ehci_soft_qtd *nextqtd; /* mirrors nextqtd in TD */ 40 ehci_physaddr_t physaddr; 41 usb_dma_t dma; /* qTD's DMA infos */ 42 int offs; /* qTD's offset in usb_dma_t */ 43 usbd_xfer_handle xfer; 44 LIST_ENTRY(ehci_soft_qtd) hnext; 45 uint16_t len; 46 } ehci_soft_qtd_t; 47 #define EHCI_SQTD_ALIGN MAX(EHCI_QTD_ALIGN, CACHE_LINE_SIZE) 48 #define EHCI_SQTD_SIZE ((sizeof (struct ehci_soft_qtd) + EHCI_SQTD_ALIGN - 1) & -EHCI_SQTD_ALIGN) 49 #define EHCI_SQTD_CHUNK (EHCI_PAGE_SIZE / EHCI_SQTD_SIZE) 50 51 typedef struct ehci_soft_qh { 52 ehci_qh_t qh; 53 struct ehci_soft_qh *next; 54 struct ehci_soft_qtd *sqtd; 55 ehci_physaddr_t physaddr; 56 usb_dma_t dma; /* QH's DMA infos */ 57 int offs; /* QH's offset in usb_dma_t */ 58 int islot; 59 } ehci_soft_qh_t; 60 #define EHCI_SQH_SIZE ((sizeof (struct ehci_soft_qh) + EHCI_QH_ALIGN - 1) / EHCI_QH_ALIGN * EHCI_QH_ALIGN) 61 #define EHCI_SQH_CHUNK (EHCI_PAGE_SIZE / EHCI_SQH_SIZE) 62 63 typedef struct ehci_soft_itd { 64 union { 65 ehci_itd_t itd; 66 ehci_sitd_t sitd; 67 }; 68 union { 69 struct { 70 /* soft_itds links in a periodic frame*/ 71 struct ehci_soft_itd *next; 72 struct ehci_soft_itd *prev; 73 } frame_list; 74 /* circular list of free itds */ 75 LIST_ENTRY(ehci_soft_itd) free_list; 76 } u; 77 struct ehci_soft_itd *xfer_next; /* Next soft_itd in xfer */ 78 ehci_physaddr_t physaddr; 79 usb_dma_t dma; 80 int offs; 81 int slot; 82 struct timeval t; /* store free time */ 83 } ehci_soft_itd_t; 84 #define EHCI_ITD_SIZE ((sizeof(struct ehci_soft_itd) + EHCI_QH_ALIGN - 1) / EHCI_ITD_ALIGN * EHCI_ITD_ALIGN) 85 #define EHCI_ITD_CHUNK (EHCI_PAGE_SIZE / EHCI_ITD_SIZE) 86 87 #define ehci_soft_sitd_t ehci_soft_itd_t 88 #define ehci_soft_sitd ehci_soft_itd 89 #define sc_softsitds sc_softitds 90 #define EHCI_SITD_SIZE ((sizeof(struct ehci_soft_sitd) + EHCI_QH_ALIGN - 1) / EHCI_SITD_ALIGN * EHCI_SITD_ALIGN) 91 #define EHCI_SITD_CHUNK (EHCI_PAGE_SIZE / EHCI_SITD_SIZE) 92 93 struct ehci_xfer { 94 struct usbd_xfer xfer; 95 struct usb_task abort_task; 96 TAILQ_ENTRY(ehci_xfer) inext; /* list of active xfers */ 97 ehci_soft_qtd_t *sqtdstart; 98 ehci_soft_qtd_t *sqtdend; 99 ehci_soft_itd_t *itdstart; 100 ehci_soft_itd_t *itdend; 101 ehci_soft_sitd_t *sitdstart; 102 ehci_soft_sitd_t *sitdend; 103 u_int isoc_len; 104 int isdone; /* used only when DIAGNOSTIC is defined */ 105 }; 106 #define EXFER(xfer) ((struct ehci_xfer *)(xfer)) 107 108 /* Information about an entry in the interrupt list. */ 109 struct ehci_soft_islot { 110 ehci_soft_qh_t *sqh; /* Queue Head. */ 111 }; 112 113 #define EHCI_FRAMELIST_MAXCOUNT 1024 114 #define EHCI_IPOLLRATES 8 /* Poll rates (1ms, 2, 4, 8 .. 128) */ 115 #define EHCI_INTRQHS ((1 << EHCI_IPOLLRATES) - 1) 116 #define EHCI_MAX_POLLRATE (1 << (EHCI_IPOLLRATES - 1)) 117 #define EHCI_IQHIDX(lev, pos) \ 118 ((((pos) & ((1 << (lev)) - 1)) | (1 << (lev))) - 1) 119 #define EHCI_ILEV_IVAL(lev) (1 << (lev)) 120 121 122 #define EHCI_HASH_SIZE 128 123 #define EHCI_COMPANION_MAX 8 124 125 #define EHCI_FREE_LIST_INTERVAL 100 126 127 typedef struct ehci_softc { 128 device_t sc_dev; 129 kmutex_t sc_lock; 130 kmutex_t sc_intr_lock; 131 kcondvar_t sc_doorbell; 132 void *sc_doorbell_si; 133 void *sc_pcd_si; 134 struct usbd_bus sc_bus; 135 bus_space_tag_t iot; 136 bus_space_handle_t ioh; 137 bus_size_t sc_size; 138 u_int sc_offs; /* offset to operational regs */ 139 int sc_flags; /* misc flags */ 140 #define EHCIF_DROPPED_INTR_WORKAROUND 0x01 141 #define EHCIF_ETTF 0x02 /* Emb. Transaction Translater func. */ 142 143 char sc_vendor[32]; /* vendor string for root hub */ 144 int sc_id_vendor; /* vendor ID for root hub */ 145 146 uint32_t sc_cmd; /* shadow of cmd reg during suspend */ 147 148 u_int sc_ncomp; 149 u_int sc_npcomp; 150 device_t sc_comps[EHCI_COMPANION_MAX]; 151 152 usb_dma_t sc_fldma; 153 ehci_link_t *sc_flist; 154 u_int sc_flsize; 155 u_int sc_rand; /* XXX need proper intr scheduling */ 156 157 struct ehci_soft_islot sc_islots[EHCI_INTRQHS]; 158 159 /* jcmm - an array matching sc_flist, but with software pointers, 160 * not hardware address pointers 161 */ 162 struct ehci_soft_itd **sc_softitds; 163 164 TAILQ_HEAD(, ehci_xfer) sc_intrhead; 165 166 ehci_soft_qh_t *sc_freeqhs; 167 ehci_soft_qtd_t *sc_freeqtds; 168 LIST_HEAD(sc_freeitds, ehci_soft_itd) sc_freeitds; 169 LIST_HEAD(sc_freesitds, ehci_soft_sitd) sc_freesitds; 170 171 int sc_noport; 172 uint8_t sc_hasppc; /* has Port Power Control */ 173 usbd_xfer_handle sc_intrxfer; 174 char sc_isreset[EHCI_MAX_PORTS]; 175 char sc_softwake; 176 kcondvar_t sc_softwake_cv; 177 178 uint32_t sc_eintrs; 179 ehci_soft_qh_t *sc_async_head; 180 181 pool_cache_t sc_xferpool; /* free xfer pool */ 182 183 struct callout sc_tmo_intrlist; 184 185 device_t sc_child; /* /dev/usb# device */ 186 char sc_dying; 187 188 void (*sc_vendor_init)(struct ehci_softc *); 189 int (*sc_vendor_port_status)(struct ehci_softc *, uint32_t, int); 190 } ehci_softc_t; 191 192 #define EREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (a)) 193 #define EREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (a)) 194 #define EREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (a)) 195 #define EWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (a), (x)) 196 #define EWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (a), (x)) 197 #define EWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (a), (x)) 198 #define EOREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a)) 199 #define EOREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a)) 200 #define EOREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a)) 201 #define EOWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x)) 202 #define EOWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x)) 203 #define EOWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x)) 204 205 int ehci_init(ehci_softc_t *); 206 int ehci_intr(void *); 207 int ehci_detach(ehci_softc_t *, int); 208 int ehci_activate(device_t, enum devact); 209 void ehci_childdet(device_t, device_t); 210 bool ehci_suspend(device_t, const pmf_qual_t *); 211 bool ehci_resume(device_t, const pmf_qual_t *); 212 bool ehci_shutdown(device_t, int); 213 214 #endif /* _EHCIVAR_H_ */ 215
Indexes created Sat Oct 11 19:10:01 GMT 2025