if_axe.c revision 1.114 1 1.114 mrg /* $NetBSD: if_axe.c,v 1.114 2019/08/14 03:44:58 mrg Exp $ */
2 1.76 skrll /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */
3 1.35 pgoyette
4 1.35 pgoyette /*
5 1.35 pgoyette * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org>
6 1.35 pgoyette *
7 1.35 pgoyette * Permission to use, copy, modify, and distribute this software for any
8 1.35 pgoyette * purpose with or without fee is hereby granted, provided that the above
9 1.35 pgoyette * copyright notice and this permission notice appear in all copies.
10 1.35 pgoyette *
11 1.35 pgoyette * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 1.35 pgoyette * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 1.35 pgoyette * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 1.35 pgoyette * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 1.35 pgoyette * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 1.35 pgoyette * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 1.35 pgoyette * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 1.35 pgoyette */
19 1.1 augustss
20 1.1 augustss /*
21 1.1 augustss * Copyright (c) 1997, 1998, 1999, 2000-2003
22 1.1 augustss * Bill Paul <wpaul (at) windriver.com>. All rights reserved.
23 1.1 augustss *
24 1.1 augustss * Redistribution and use in source and binary forms, with or without
25 1.1 augustss * modification, are permitted provided that the following conditions
26 1.1 augustss * are met:
27 1.1 augustss * 1. Redistributions of source code must retain the above copyright
28 1.1 augustss * notice, this list of conditions and the following disclaimer.
29 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
30 1.1 augustss * notice, this list of conditions and the following disclaimer in the
31 1.1 augustss * documentation and/or other materials provided with the distribution.
32 1.1 augustss * 3. All advertising materials mentioning features or use of this software
33 1.1 augustss * must display the following acknowledgement:
34 1.1 augustss * This product includes software developed by Bill Paul.
35 1.1 augustss * 4. Neither the name of the author nor the names of any co-contributors
36 1.1 augustss * may be used to endorse or promote products derived from this software
37 1.1 augustss * without specific prior written permission.
38 1.1 augustss *
39 1.1 augustss * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
40 1.1 augustss * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41 1.1 augustss * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
42 1.1 augustss * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
43 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
44 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
45 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
46 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
47 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
48 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
49 1.1 augustss * THE POSSIBILITY OF SUCH DAMAGE.
50 1.1 augustss */
51 1.1 augustss
52 1.1 augustss /*
53 1.76 skrll * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
54 1.76 skrll * Used in the LinkSys USB200M and various other adapters.
55 1.1 augustss *
56 1.1 augustss * Written by Bill Paul <wpaul (at) windriver.com>
57 1.1 augustss * Senior Engineer
58 1.1 augustss * Wind River Systems
59 1.1 augustss */
60 1.1 augustss
61 1.1 augustss /*
62 1.1 augustss * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
63 1.1 augustss * It uses an external PHY (reference designs use a RealTek chip),
64 1.1 augustss * and has a 64-bit multicast hash filter. There is some information
65 1.1 augustss * missing from the manual which one needs to know in order to make
66 1.1 augustss * the chip function:
67 1.1 augustss *
68 1.1 augustss * - You must set bit 7 in the RX control register, otherwise the
69 1.1 augustss * chip won't receive any packets.
70 1.1 augustss * - You must initialize all 3 IPG registers, or you won't be able
71 1.1 augustss * to send any packets.
72 1.1 augustss *
73 1.1 augustss * Note that this device appears to only support loading the station
74 1.76 skrll * address via autoload from the EEPROM (i.e. there's no way to manually
75 1.1 augustss * set it).
76 1.1 augustss *
77 1.1 augustss * (Adam Weinberger wanted me to name this driver if_gir.c.)
78 1.1 augustss */
79 1.1 augustss
80 1.1 augustss /*
81 1.76 skrll * Ax88178 and Ax88772 support backported from the OpenBSD driver.
82 1.76 skrll * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com
83 1.76 skrll *
84 1.76 skrll * Manual here:
85 1.76 skrll * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
86 1.76 skrll * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
87 1.1 augustss */
88 1.1 augustss
89 1.1 augustss #include <sys/cdefs.h>
90 1.114 mrg __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.114 2019/08/14 03:44:58 mrg Exp $");
91 1.1 augustss
92 1.62 christos #ifdef _KERNEL_OPT
93 1.75 skrll #include "opt_usb.h"
94 1.81 msaitoh #include "opt_net_mpsafe.h"
95 1.1 augustss #endif
96 1.1 augustss
97 1.1 augustss #include <sys/param.h>
98 1.1 augustss
99 1.104 mrg #include <dev/usb/usbnet.h>
100 1.76 skrll #include <dev/usb/usbhist.h>
101 1.1 augustss #include <dev/usb/if_axereg.h>
102 1.1 augustss
103 1.99 mrg struct axe_type {
104 1.99 mrg struct usb_devno axe_dev;
105 1.99 mrg uint16_t axe_flags;
106 1.99 mrg };
107 1.99 mrg
108 1.104 mrg struct axe_softc {
109 1.104 mrg struct usbnet axe_un;
110 1.99 mrg
111 1.108 mrg /* usbnet:un_flags values */
112 1.99 mrg #define AX178 __BIT(0) /* AX88178 */
113 1.99 mrg #define AX772 __BIT(1) /* AX88772 */
114 1.99 mrg #define AX772A __BIT(2) /* AX88772A */
115 1.99 mrg #define AX772B __BIT(3) /* AX88772B */
116 1.99 mrg #define AXSTD_FRAME __BIT(12)
117 1.99 mrg #define AXCSUM_FRAME __BIT(13)
118 1.99 mrg
119 1.99 mrg uint8_t axe_ipgs[3];
120 1.99 mrg uint8_t axe_phyaddrs[2];
121 1.99 mrg uint16_t sc_pwrcfg;
122 1.99 mrg uint16_t sc_lenmask;
123 1.99 mrg
124 1.99 mrg };
125 1.99 mrg
126 1.108 mrg #define AXE_IS_178_FAMILY(un) \
127 1.108 mrg ((un)->un_flags & (AX772 | AX772A | AX772B | AX178))
128 1.99 mrg
129 1.108 mrg #define AXE_IS_772(un) \
130 1.108 mrg ((un)->un_flags & (AX772 | AX772A | AX772B))
131 1.99 mrg
132 1.99 mrg #define AX_RXCSUM \
133 1.99 mrg (IFCAP_CSUM_IPv4_Rx | \
134 1.99 mrg IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \
135 1.99 mrg IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)
136 1.99 mrg
137 1.99 mrg #define AX_TXCSUM \
138 1.99 mrg (IFCAP_CSUM_IPv4_Tx | \
139 1.99 mrg IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \
140 1.99 mrg IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)
141 1.99 mrg
142 1.76 skrll /*
143 1.76 skrll * AXE_178_MAX_FRAME_BURST
144 1.76 skrll * max frame burst size for Ax88178 and Ax88772
145 1.76 skrll * 0 2048 bytes
146 1.76 skrll * 1 4096 bytes
147 1.76 skrll * 2 8192 bytes
148 1.76 skrll * 3 16384 bytes
149 1.76 skrll * use the largest your system can handle without USB stalling.
150 1.76 skrll *
151 1.76 skrll * NB: 88772 parts appear to generate lots of input errors with
152 1.76 skrll * a 2K rx buffer and 8K is only slightly faster than 4K on an
153 1.76 skrll * EHCI port on a T42 so change at your own risk.
154 1.76 skrll */
155 1.76 skrll #define AXE_178_MAX_FRAME_BURST 1
156 1.76 skrll
157 1.76 skrll
158 1.76 skrll #ifdef USB_DEBUG
159 1.76 skrll #ifndef AXE_DEBUG
160 1.76 skrll #define axedebug 0
161 1.1 augustss #else
162 1.76 skrll static int axedebug = 20;
163 1.76 skrll
164 1.76 skrll SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup")
165 1.76 skrll {
166 1.76 skrll int err;
167 1.76 skrll const struct sysctlnode *rnode;
168 1.76 skrll const struct sysctlnode *cnode;
169 1.76 skrll
170 1.76 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
171 1.76 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe",
172 1.76 skrll SYSCTL_DESCR("axe global controls"),
173 1.76 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
174 1.76 skrll
175 1.76 skrll if (err)
176 1.76 skrll goto fail;
177 1.76 skrll
178 1.76 skrll /* control debugging printfs */
179 1.76 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
180 1.96 msaitoh CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT,
181 1.76 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
182 1.76 skrll NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL);
183 1.76 skrll if (err)
184 1.76 skrll goto fail;
185 1.76 skrll
186 1.76 skrll return;
187 1.76 skrll fail:
188 1.76 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
189 1.76 skrll }
190 1.76 skrll
191 1.76 skrll #endif /* AXE_DEBUG */
192 1.76 skrll #endif /* USB_DEBUG */
193 1.76 skrll
194 1.76 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D)
195 1.76 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D)
196 1.76 skrll #define AXEHIST_FUNC() USBHIST_FUNC()
197 1.76 skrll #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug)
198 1.1 augustss
199 1.1 augustss /*
200 1.1 augustss * Various supported device vendors/products.
201 1.1 augustss */
202 1.35 pgoyette static const struct axe_type axe_devs[] = {
203 1.35 pgoyette { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 },
204 1.35 pgoyette { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 },
205 1.35 pgoyette { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 },
206 1.1 augustss { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 },
207 1.35 pgoyette { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 },
208 1.35 pgoyette { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 },
209 1.76 skrll { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B },
210 1.76 skrll { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B },
211 1.35 pgoyette { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 },
212 1.35 pgoyette { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 },
213 1.35 pgoyette { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 },
214 1.35 pgoyette { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0},
215 1.76 skrll { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A },
216 1.1 augustss { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0},
217 1.1 augustss { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 },
218 1.35 pgoyette { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 },
219 1.74 skrll { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 },
220 1.76 skrll { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B },
221 1.35 pgoyette { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 },
222 1.35 pgoyette { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 },
223 1.35 pgoyette { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 },
224 1.76 skrll { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B },
225 1.97 msaitoh { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B },
226 1.1 augustss { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 },
227 1.35 pgoyette { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 },
228 1.35 pgoyette { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 },
229 1.35 pgoyette { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 },
230 1.2 augustss { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 },
231 1.35 pgoyette { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 },
232 1.1 augustss { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 },
233 1.35 pgoyette { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 },
234 1.35 pgoyette { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 },
235 1.76 skrll { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 },
236 1.76 skrll { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 },
237 1.76 skrll { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 },
238 1.35 pgoyette { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 },
239 1.1 augustss };
240 1.9 christos #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p))
241 1.1 augustss
242 1.76 skrll static const struct ax88772b_mfb ax88772b_mfb_table[] = {
243 1.76 skrll { 0x8000, 0x8001, 2048 },
244 1.76 skrll { 0x8100, 0x8147, 4096 },
245 1.76 skrll { 0x8200, 0x81EB, 6144 },
246 1.76 skrll { 0x8300, 0x83D7, 8192 },
247 1.76 skrll { 0x8400, 0x851E, 16384 },
248 1.76 skrll { 0x8500, 0x8666, 20480 },
249 1.76 skrll { 0x8600, 0x87AE, 24576 },
250 1.76 skrll { 0x8700, 0x8A3D, 32768 }
251 1.76 skrll };
252 1.76 skrll
253 1.35 pgoyette int axe_match(device_t, cfdata_t, void *);
254 1.35 pgoyette void axe_attach(device_t, device_t, void *);
255 1.35 pgoyette
256 1.35 pgoyette CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc),
257 1.104 mrg axe_match, axe_attach, usbnet_detach, usbnet_activate);
258 1.35 pgoyette
259 1.110 mrg static void axe_stop(struct ifnet *, int);
260 1.110 mrg static int axe_ioctl(struct ifnet *, u_long, void *);
261 1.107 mrg static int axe_init(struct ifnet *);
262 1.107 mrg static usbd_status axe_mii_read_reg(struct usbnet *, int, int, uint16_t *);
263 1.107 mrg static usbd_status axe_mii_write_reg(struct usbnet *, int, int, uint16_t);
264 1.110 mrg static void axe_mii_statchg(struct ifnet *);
265 1.110 mrg static void axe_rx_loop(struct usbnet *, struct usbd_xfer *,
266 1.110 mrg struct usbnet_chain *, uint32_t);
267 1.110 mrg static unsigned axe_tx_prepare(struct usbnet *, struct mbuf *,
268 1.110 mrg struct usbnet_chain *);
269 1.35 pgoyette
270 1.35 pgoyette static void axe_ax88178_init(struct axe_softc *);
271 1.35 pgoyette static void axe_ax88772_init(struct axe_softc *);
272 1.82 ozaki static void axe_ax88772a_init(struct axe_softc *);
273 1.82 ozaki static void axe_ax88772b_init(struct axe_softc *);
274 1.1 augustss
275 1.107 mrg static struct usbnet_ops axe_ops = {
276 1.110 mrg .uno_stop = axe_stop,
277 1.110 mrg .uno_ioctl = axe_ioctl,
278 1.107 mrg .uno_read_reg = axe_mii_read_reg,
279 1.107 mrg .uno_write_reg = axe_mii_write_reg,
280 1.110 mrg .uno_statchg = axe_mii_statchg,
281 1.110 mrg .uno_tx_prepare = axe_tx_prepare,
282 1.110 mrg .uno_rx_loop = axe_rx_loop,
283 1.107 mrg .uno_init = axe_init,
284 1.107 mrg };
285 1.107 mrg
286 1.104 mrg static usbd_status
287 1.1 augustss axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
288 1.1 augustss {
289 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
290 1.104 mrg struct usbnet * const un = &sc->axe_un;
291 1.38 tsutsui usb_device_request_t req;
292 1.38 tsutsui usbd_status err;
293 1.1 augustss
294 1.104 mrg usbnet_isowned_mii(un);
295 1.21 ad
296 1.107 mrg if (usbnet_isdying(un))
297 1.86 christos return -1;
298 1.1 augustss
299 1.83 pgoyette DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0);
300 1.76 skrll
301 1.1 augustss if (AXE_CMD_DIR(cmd))
302 1.1 augustss req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
303 1.1 augustss else
304 1.1 augustss req.bmRequestType = UT_READ_VENDOR_DEVICE;
305 1.1 augustss req.bRequest = AXE_CMD_CMD(cmd);
306 1.1 augustss USETW(req.wValue, val);
307 1.1 augustss USETW(req.wIndex, index);
308 1.1 augustss USETW(req.wLength, AXE_CMD_LEN(cmd));
309 1.1 augustss
310 1.104 mrg err = usbd_do_request(un->un_udev, &req, buf);
311 1.104 mrg if (err)
312 1.104 mrg DPRINTF("cmd %jd err %jd", cmd, err, 0, 0);
313 1.1 augustss
314 1.104 mrg return err;
315 1.1 augustss }
316 1.1 augustss
317 1.104 mrg static usbd_status
318 1.104 mrg axe_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)
319 1.1 augustss {
320 1.77 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
321 1.104 mrg struct axe_softc * const sc = usbnet_softc(un);
322 1.38 tsutsui usbd_status err;
323 1.95 msaitoh uint16_t data;
324 1.1 augustss
325 1.83 pgoyette DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0);
326 1.76 skrll
327 1.66 roy axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
328 1.76 skrll
329 1.95 msaitoh err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data);
330 1.66 roy axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
331 1.100 mrg
332 1.66 roy if (err) {
333 1.104 mrg aprint_error_dev(un->un_dev, "read PHY failed\n");
334 1.95 msaitoh return err;
335 1.66 roy }
336 1.66 roy
337 1.95 msaitoh *val = le16toh(data);
338 1.108 mrg if (AXE_IS_772(un) && reg == MII_BMSR) {
339 1.66 roy /*
340 1.76 skrll * BMSR of AX88772 indicates that it supports extended
341 1.66 roy * capability but the extended status register is
342 1.76 skrll * reserved for embedded ethernet PHY. So clear the
343 1.66 roy * extended capability bit of BMSR.
344 1.66 roy */
345 1.95 msaitoh *val &= ~BMSR_EXTCAP;
346 1.1 augustss }
347 1.1 augustss
348 1.95 msaitoh DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0);
349 1.66 roy
350 1.104 mrg return USBD_NORMAL_COMPLETION;
351 1.1 augustss }
352 1.1 augustss
353 1.104 mrg static usbd_status
354 1.104 mrg axe_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)
355 1.1 augustss {
356 1.104 mrg struct axe_softc * const sc = usbnet_softc(un);
357 1.38 tsutsui usbd_status err;
358 1.104 mrg uint16_t aval;
359 1.1 augustss
360 1.104 mrg aval = htole16(val);
361 1.1 augustss
362 1.1 augustss axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
363 1.104 mrg err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval);
364 1.1 augustss axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
365 1.1 augustss
366 1.104 mrg return err;
367 1.66 roy }
368 1.66 roy
369 1.66 roy static void
370 1.110 mrg axe_mii_statchg(struct ifnet *ifp)
371 1.1 augustss {
372 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
373 1.76 skrll
374 1.104 mrg struct usbnet * const un = ifp->if_softc;
375 1.104 mrg struct axe_softc * const sc = usbnet_softc(un);
376 1.107 mrg struct mii_data *mii = usbnet_mii(un);
377 1.5 augustss int val, err;
378 1.5 augustss
379 1.107 mrg if (usbnet_isdying(un))
380 1.100 mrg return;
381 1.100 mrg
382 1.76 skrll val = 0;
383 1.109 mrg usbnet_set_link(un, false);
384 1.76 skrll if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
385 1.76 skrll val |= AXE_MEDIA_FULL_DUPLEX;
386 1.108 mrg if (AXE_IS_178_FAMILY(un)) {
387 1.76 skrll if ((IFM_OPTIONS(mii->mii_media_active) &
388 1.76 skrll IFM_ETH_TXPAUSE) != 0)
389 1.76 skrll val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN;
390 1.76 skrll if ((IFM_OPTIONS(mii->mii_media_active) &
391 1.76 skrll IFM_ETH_RXPAUSE) != 0)
392 1.76 skrll val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN;
393 1.76 skrll }
394 1.76 skrll }
395 1.108 mrg if (AXE_IS_178_FAMILY(un)) {
396 1.76 skrll val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
397 1.108 mrg if (un->un_flags & AX178)
398 1.66 roy val |= AXE_178_MEDIA_ENCK;
399 1.35 pgoyette switch (IFM_SUBTYPE(mii->mii_media_active)) {
400 1.38 tsutsui case IFM_1000_T:
401 1.35 pgoyette val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
402 1.109 mrg usbnet_set_link(un, true);
403 1.35 pgoyette break;
404 1.35 pgoyette case IFM_100_TX:
405 1.35 pgoyette val |= AXE_178_MEDIA_100TX;
406 1.109 mrg usbnet_set_link(un, true);
407 1.35 pgoyette break;
408 1.35 pgoyette case IFM_10_T:
409 1.109 mrg usbnet_set_link(un, true);
410 1.35 pgoyette break;
411 1.35 pgoyette }
412 1.35 pgoyette }
413 1.35 pgoyette
414 1.83 pgoyette DPRINTF("val=0x%jx", val, 0, 0, 0);
415 1.104 mrg usbnet_lock_mii(un);
416 1.5 augustss err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
417 1.104 mrg usbnet_unlock_mii(un);
418 1.104 mrg if (err)
419 1.104 mrg aprint_error_dev(un->un_dev, "media change failed\n");
420 1.1 augustss }
421 1.1 augustss
422 1.35 pgoyette static void
423 1.104 mrg axe_setiff_locked(struct usbnet *un)
424 1.1 augustss {
425 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
426 1.104 mrg struct axe_softc * const sc = usbnet_softc(un);
427 1.104 mrg struct ifnet * const ifp = usbnet_ifp(un);
428 1.104 mrg struct ethercom *ec = usbnet_ec(un);
429 1.38 tsutsui struct ether_multi *enm;
430 1.38 tsutsui struct ether_multistep step;
431 1.38 tsutsui uint32_t h = 0;
432 1.38 tsutsui uint16_t rxmode;
433 1.38 tsutsui uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
434 1.1 augustss
435 1.104 mrg usbnet_isowned_mii(un);
436 1.100 mrg
437 1.107 mrg if (usbnet_isdying(un))
438 1.1 augustss return;
439 1.1 augustss
440 1.86 christos if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) {
441 1.104 mrg aprint_error_dev(un->un_dev, "can't read rxmode");
442 1.86 christos return;
443 1.86 christos }
444 1.10 tron rxmode = le16toh(rxmode);
445 1.1 augustss
446 1.76 skrll rxmode &=
447 1.76 skrll ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC |
448 1.76 skrll AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST);
449 1.76 skrll
450 1.76 skrll rxmode |=
451 1.76 skrll (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0;
452 1.76 skrll
453 1.76 skrll if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
454 1.76 skrll if (ifp->if_flags & IFF_PROMISC)
455 1.76 skrll rxmode |= AXE_RXCMD_PROMISC;
456 1.35 pgoyette goto allmulti;
457 1.35 pgoyette }
458 1.1 augustss
459 1.35 pgoyette /* Now program new ones */
460 1.98 msaitoh ETHER_LOCK(ec);
461 1.98 msaitoh ETHER_FIRST_MULTI(step, ec, enm);
462 1.1 augustss while (enm != NULL) {
463 1.1 augustss if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
464 1.98 msaitoh ETHER_ADDR_LEN) != 0) {
465 1.98 msaitoh ETHER_UNLOCK(ec);
466 1.1 augustss goto allmulti;
467 1.98 msaitoh }
468 1.1 augustss
469 1.1 augustss h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
470 1.35 pgoyette hashtbl[h >> 3] |= 1U << (h & 7);
471 1.1 augustss ETHER_NEXT_MULTI(step, enm);
472 1.1 augustss }
473 1.98 msaitoh ETHER_UNLOCK(ec);
474 1.1 augustss ifp->if_flags &= ~IFF_ALLMULTI;
475 1.76 skrll rxmode |= AXE_RXCMD_MULTICAST;
476 1.76 skrll
477 1.86 christos axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl);
478 1.1 augustss axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
479 1.1 augustss return;
480 1.35 pgoyette
481 1.35 pgoyette allmulti:
482 1.35 pgoyette ifp->if_flags |= IFF_ALLMULTI;
483 1.35 pgoyette rxmode |= AXE_RXCMD_ALLMULTI;
484 1.35 pgoyette axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
485 1.100 mrg }
486 1.100 mrg
487 1.100 mrg static void
488 1.104 mrg axe_setiff(struct usbnet *un)
489 1.100 mrg {
490 1.104 mrg usbnet_lock_mii(un);
491 1.104 mrg axe_setiff_locked(un);
492 1.104 mrg usbnet_unlock_mii(un);
493 1.1 augustss }
494 1.1 augustss
495 1.88 christos static void
496 1.104 mrg axe_ax_init(struct usbnet *un)
497 1.88 christos {
498 1.104 mrg struct axe_softc * const sc = usbnet_softc(un);
499 1.104 mrg
500 1.89 christos int cmd = AXE_178_CMD_READ_NODEID;
501 1.89 christos
502 1.108 mrg if (un->un_flags & AX178) {
503 1.88 christos axe_ax88178_init(sc);
504 1.108 mrg } else if (un->un_flags & AX772) {
505 1.88 christos axe_ax88772_init(sc);
506 1.108 mrg } else if (un->un_flags & AX772A) {
507 1.88 christos axe_ax88772a_init(sc);
508 1.108 mrg } else if (un->un_flags & AX772B) {
509 1.88 christos axe_ax88772b_init(sc);
510 1.89 christos return;
511 1.89 christos } else {
512 1.89 christos cmd = AXE_172_CMD_READ_NODEID;
513 1.89 christos }
514 1.89 christos
515 1.104 mrg if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) {
516 1.104 mrg aprint_error_dev(un->un_dev,
517 1.89 christos "failed to read ethernet address\n");
518 1.88 christos }
519 1.88 christos }
520 1.88 christos
521 1.76 skrll
522 1.35 pgoyette static void
523 1.104 mrg axe_reset(struct usbnet *un)
524 1.1 augustss {
525 1.38 tsutsui
526 1.104 mrg usbnet_isowned_mii(un);
527 1.104 mrg
528 1.107 mrg if (usbnet_isdying(un))
529 1.1 augustss return;
530 1.76 skrll
531 1.76 skrll /*
532 1.76 skrll * softnet_lock can be taken when NET_MPAFE is not defined when calling
533 1.100 mrg * if_addr_init -> if_init. This doesn't mix well with the
534 1.76 skrll * usbd_delay_ms calls in the init routines as things like nd6_slowtimo
535 1.76 skrll * can fire during the wait and attempt to take softnet_lock and then
536 1.104 mrg * block the softclk thread meaning the wait never ends.
537 1.76 skrll */
538 1.76 skrll #ifndef NET_MPSAFE
539 1.1 augustss /* XXX What to reset? */
540 1.1 augustss
541 1.1 augustss /* Wait a little while for the chip to get its brains in order. */
542 1.1 augustss DELAY(1000);
543 1.76 skrll #else
544 1.104 mrg axe_ax_init(un);
545 1.76 skrll #endif
546 1.1 augustss }
547 1.1 augustss
548 1.66 roy static int
549 1.66 roy axe_get_phyno(struct axe_softc *sc, int sel)
550 1.66 roy {
551 1.66 roy int phyno;
552 1.66 roy
553 1.66 roy switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) {
554 1.66 roy case PHY_TYPE_100_HOME:
555 1.66 roy /* FALLTHROUGH */
556 1.66 roy case PHY_TYPE_GIG:
557 1.66 roy phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]);
558 1.66 roy break;
559 1.66 roy case PHY_TYPE_SPECIAL:
560 1.66 roy /* FALLTHROUGH */
561 1.66 roy case PHY_TYPE_RSVD:
562 1.66 roy /* FALLTHROUGH */
563 1.66 roy case PHY_TYPE_NON_SUP:
564 1.66 roy /* FALLTHROUGH */
565 1.66 roy default:
566 1.66 roy phyno = -1;
567 1.66 roy break;
568 1.66 roy }
569 1.66 roy
570 1.66 roy return phyno;
571 1.66 roy }
572 1.66 roy
573 1.66 roy #define AXE_GPIO_WRITE(x, y) do { \
574 1.66 roy axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
575 1.104 mrg usbd_delay_ms(sc->axe_un.un_udev, hztoms(y)); \
576 1.66 roy } while (0)
577 1.66 roy
578 1.35 pgoyette static void
579 1.35 pgoyette axe_ax88178_init(struct axe_softc *sc)
580 1.35 pgoyette {
581 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
582 1.104 mrg struct usbnet * const un = &sc->axe_un;
583 1.66 roy int gpio0, ledmode, phymode;
584 1.66 roy uint16_t eeprom, val;
585 1.35 pgoyette
586 1.35 pgoyette axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
587 1.35 pgoyette /* XXX magic */
588 1.86 christos if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0)
589 1.86 christos eeprom = 0xffff;
590 1.35 pgoyette axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
591 1.35 pgoyette
592 1.35 pgoyette eeprom = le16toh(eeprom);
593 1.35 pgoyette
594 1.83 pgoyette DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0);
595 1.35 pgoyette
596 1.35 pgoyette /* if EEPROM is invalid we have to use to GPIO0 */
597 1.35 pgoyette if (eeprom == 0xffff) {
598 1.66 roy phymode = AXE_PHY_MODE_MARVELL;
599 1.35 pgoyette gpio0 = 1;
600 1.66 roy ledmode = 0;
601 1.35 pgoyette } else {
602 1.66 roy phymode = eeprom & 0x7f;
603 1.35 pgoyette gpio0 = (eeprom & 0x80) ? 0 : 1;
604 1.66 roy ledmode = eeprom >> 8;
605 1.35 pgoyette }
606 1.35 pgoyette
607 1.83 pgoyette DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0);
608 1.35 pgoyette
609 1.66 roy /* Program GPIOs depending on PHY hardware. */
610 1.66 roy switch (phymode) {
611 1.66 roy case AXE_PHY_MODE_MARVELL:
612 1.66 roy if (gpio0 == 1) {
613 1.66 roy AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
614 1.66 roy hz / 32);
615 1.66 roy AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
616 1.66 roy hz / 32);
617 1.66 roy AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
618 1.66 roy AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
619 1.66 roy hz / 32);
620 1.66 roy } else {
621 1.66 roy AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
622 1.66 roy AXE_GPIO1_EN, hz / 3);
623 1.66 roy if (ledmode == 1) {
624 1.66 roy AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
625 1.66 roy AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
626 1.66 roy hz / 3);
627 1.66 roy } else {
628 1.66 roy AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
629 1.66 roy AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
630 1.66 roy AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
631 1.66 roy AXE_GPIO2_EN, hz / 4);
632 1.66 roy AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
633 1.66 roy AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
634 1.66 roy }
635 1.66 roy }
636 1.66 roy break;
637 1.66 roy case AXE_PHY_MODE_CICADA:
638 1.66 roy case AXE_PHY_MODE_CICADA_V2:
639 1.66 roy case AXE_PHY_MODE_CICADA_V2_ASIX:
640 1.66 roy if (gpio0 == 1)
641 1.66 roy AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
642 1.66 roy AXE_GPIO0_EN, hz / 32);
643 1.66 roy else
644 1.66 roy AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
645 1.66 roy AXE_GPIO1_EN, hz / 32);
646 1.66 roy break;
647 1.66 roy case AXE_PHY_MODE_AGERE:
648 1.66 roy AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
649 1.66 roy AXE_GPIO1_EN, hz / 32);
650 1.66 roy AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
651 1.66 roy AXE_GPIO2_EN, hz / 32);
652 1.66 roy AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
653 1.66 roy AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
654 1.66 roy AXE_GPIO2_EN, hz / 32);
655 1.66 roy break;
656 1.66 roy case AXE_PHY_MODE_REALTEK_8211CL:
657 1.66 roy case AXE_PHY_MODE_REALTEK_8211BN:
658 1.66 roy case AXE_PHY_MODE_REALTEK_8251CL:
659 1.66 roy val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
660 1.66 roy AXE_GPIO1 | AXE_GPIO1_EN;
661 1.66 roy AXE_GPIO_WRITE(val, hz / 32);
662 1.66 roy AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
663 1.66 roy AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
664 1.66 roy AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
665 1.66 roy if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
666 1.104 mrg axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0005);
667 1.104 mrg axe_mii_write_reg(un, un->un_phyno, 0x0C, 0x0000);
668 1.104 mrg axe_mii_read_reg(un, un->un_phyno, 0x0001, &val);
669 1.104 mrg axe_mii_write_reg(un, un->un_phyno, 0x01, val | 0x0080);
670 1.104 mrg axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0000);
671 1.66 roy }
672 1.66 roy break;
673 1.66 roy default:
674 1.66 roy /* Unknown PHY model or no need to program GPIOs. */
675 1.66 roy break;
676 1.35 pgoyette }
677 1.35 pgoyette
678 1.35 pgoyette /* soft reset */
679 1.35 pgoyette axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
680 1.104 mrg usbd_delay_ms(un->un_udev, 150);
681 1.35 pgoyette axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
682 1.35 pgoyette AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
683 1.104 mrg usbd_delay_ms(un->un_udev, 150);
684 1.76 skrll /* Enable MII/GMII/RGMII interface to work with external PHY. */
685 1.35 pgoyette axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
686 1.104 mrg usbd_delay_ms(un->un_udev, 10);
687 1.35 pgoyette axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
688 1.35 pgoyette }
689 1.35 pgoyette
690 1.35 pgoyette static void
691 1.35 pgoyette axe_ax88772_init(struct axe_softc *sc)
692 1.35 pgoyette {
693 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
694 1.104 mrg struct usbnet * const un = &sc->axe_un;
695 1.35 pgoyette
696 1.35 pgoyette axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
697 1.104 mrg usbd_delay_ms(un->un_udev, 40);
698 1.35 pgoyette
699 1.104 mrg if (un->un_phyno == AXE_772_PHY_NO_EPHY) {
700 1.35 pgoyette /* ask for the embedded PHY */
701 1.76 skrll axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0,
702 1.76 skrll AXE_SW_PHY_SELECT_EMBEDDED, NULL);
703 1.104 mrg usbd_delay_ms(un->un_udev, 10);
704 1.35 pgoyette
705 1.35 pgoyette /* power down and reset state, pin reset state */
706 1.35 pgoyette axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
707 1.104 mrg usbd_delay_ms(un->un_udev, 60);
708 1.35 pgoyette
709 1.35 pgoyette /* power down/reset state, pin operating state */
710 1.35 pgoyette axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
711 1.35 pgoyette AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
712 1.104 mrg usbd_delay_ms(un->un_udev, 150);
713 1.35 pgoyette
714 1.35 pgoyette /* power up, reset */
715 1.35 pgoyette axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
716 1.35 pgoyette
717 1.35 pgoyette /* power up, operating */
718 1.35 pgoyette axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
719 1.35 pgoyette AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
720 1.35 pgoyette } else {
721 1.35 pgoyette /* ask for external PHY */
722 1.76 skrll axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT,
723 1.76 skrll NULL);
724 1.104 mrg usbd_delay_ms(un->un_udev, 10);
725 1.35 pgoyette
726 1.35 pgoyette /* power down internal PHY */
727 1.35 pgoyette axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
728 1.35 pgoyette AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
729 1.35 pgoyette }
730 1.35 pgoyette
731 1.104 mrg usbd_delay_ms(un->un_udev, 150);
732 1.35 pgoyette axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
733 1.35 pgoyette }
734 1.35 pgoyette
735 1.76 skrll static void
736 1.76 skrll axe_ax88772_phywake(struct axe_softc *sc)
737 1.76 skrll {
738 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
739 1.104 mrg struct usbnet * const un = &sc->axe_un;
740 1.76 skrll
741 1.104 mrg if (un->un_phyno == AXE_772_PHY_NO_EPHY) {
742 1.76 skrll /* Manually select internal(embedded) PHY - MAC mode. */
743 1.76 skrll axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0,
744 1.86 christos AXE_SW_PHY_SELECT_EMBEDDED, NULL);
745 1.104 mrg usbd_delay_ms(un->un_udev, hztoms(hz / 32));
746 1.76 skrll } else {
747 1.76 skrll /*
748 1.76 skrll * Manually select external PHY - MAC mode.
749 1.76 skrll * Reverse MII/RMII is for AX88772A PHY mode.
750 1.76 skrll */
751 1.76 skrll axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
752 1.76 skrll AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
753 1.104 mrg usbd_delay_ms(un->un_udev, hztoms(hz / 32));
754 1.76 skrll }
755 1.76 skrll
756 1.76 skrll axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
757 1.76 skrll AXE_SW_RESET_IPRL, NULL);
758 1.76 skrll
759 1.76 skrll /* T1 = min 500ns everywhere */
760 1.104 mrg usbd_delay_ms(un->un_udev, 150);
761 1.76 skrll
762 1.76 skrll /* Take PHY out of power down. */
763 1.104 mrg if (un->un_phyno == AXE_772_PHY_NO_EPHY) {
764 1.76 skrll axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
765 1.76 skrll } else {
766 1.76 skrll axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL);
767 1.76 skrll }
768 1.76 skrll
769 1.76 skrll /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */
770 1.104 mrg usbd_delay_ms(un->un_udev, 600);
771 1.76 skrll
772 1.76 skrll axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
773 1.76 skrll
774 1.76 skrll /* T3 = 500ns everywhere */
775 1.104 mrg usbd_delay_ms(un->un_udev, hztoms(hz / 32));
776 1.76 skrll axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
777 1.104 mrg usbd_delay_ms(un->un_udev, hztoms(hz / 32));
778 1.76 skrll }
779 1.76 skrll
780 1.76 skrll static void
781 1.76 skrll axe_ax88772a_init(struct axe_softc *sc)
782 1.76 skrll {
783 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
784 1.76 skrll
785 1.76 skrll /* Reload EEPROM. */
786 1.76 skrll AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
787 1.76 skrll axe_ax88772_phywake(sc);
788 1.76 skrll /* Stop MAC. */
789 1.76 skrll axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
790 1.76 skrll }
791 1.76 skrll
792 1.76 skrll static void
793 1.76 skrll axe_ax88772b_init(struct axe_softc *sc)
794 1.76 skrll {
795 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
796 1.104 mrg struct usbnet * const un = &sc->axe_un;
797 1.76 skrll uint16_t eeprom;
798 1.76 skrll int i;
799 1.76 skrll
800 1.76 skrll /* Reload EEPROM. */
801 1.76 skrll AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32);
802 1.76 skrll
803 1.76 skrll /*
804 1.76 skrll * Save PHY power saving configuration(high byte) and
805 1.76 skrll * clear EEPROM checksum value(low byte).
806 1.76 skrll */
807 1.86 christos if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG,
808 1.86 christos &eeprom)) {
809 1.104 mrg aprint_error_dev(un->un_dev, "failed to read eeprom\n");
810 1.86 christos return;
811 1.86 christos }
812 1.86 christos
813 1.76 skrll sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
814 1.76 skrll
815 1.76 skrll /*
816 1.76 skrll * Auto-loaded default station address from internal ROM is
817 1.76 skrll * 00:00:00:00:00:00 such that an explicit access to EEPROM
818 1.76 skrll * is required to get real station address.
819 1.76 skrll */
820 1.104 mrg uint8_t *eaddr = un->un_eaddr;
821 1.76 skrll for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
822 1.86 christos if (axe_cmd(sc, AXE_CMD_SROM_READ, 0,
823 1.86 christos AXE_EEPROM_772B_NODE_ID + i, &eeprom)) {
824 1.104 mrg aprint_error_dev(un->un_dev,
825 1.86 christos "failed to read eeprom\n");
826 1.86 christos eeprom = 0;
827 1.86 christos }
828 1.76 skrll eeprom = le16toh(eeprom);
829 1.76 skrll *eaddr++ = (uint8_t)(eeprom & 0xFF);
830 1.76 skrll *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
831 1.76 skrll }
832 1.76 skrll /* Wakeup PHY. */
833 1.76 skrll axe_ax88772_phywake(sc);
834 1.76 skrll /* Stop MAC. */
835 1.76 skrll axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
836 1.76 skrll }
837 1.76 skrll
838 1.76 skrll #undef AXE_GPIO_WRITE
839 1.76 skrll
840 1.1 augustss /*
841 1.1 augustss * Probe for a AX88172 chip.
842 1.1 augustss */
843 1.27 dyoung int
844 1.27 dyoung axe_match(device_t parent, cfdata_t match, void *aux)
845 1.1 augustss {
846 1.27 dyoung struct usb_attach_arg *uaa = aux;
847 1.1 augustss
848 1.71 skrll return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ?
849 1.38 tsutsui UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
850 1.1 augustss }
851 1.1 augustss
852 1.1 augustss /*
853 1.1 augustss * Attach the interface. Allocate softc structures, do ifmedia
854 1.1 augustss * setup and ethernet/BPF attach.
855 1.1 augustss */
856 1.27 dyoung void
857 1.27 dyoung axe_attach(device_t parent, device_t self, void *aux)
858 1.1 augustss {
859 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
860 1.27 dyoung struct axe_softc *sc = device_private(self);
861 1.104 mrg struct usbnet * const un = &sc->axe_un;
862 1.27 dyoung struct usb_attach_arg *uaa = aux;
863 1.71 skrll struct usbd_device *dev = uaa->uaa_device;
864 1.1 augustss usbd_status err;
865 1.1 augustss usb_interface_descriptor_t *id;
866 1.1 augustss usb_endpoint_descriptor_t *ed;
867 1.8 augustss char *devinfop;
868 1.104 mrg unsigned bufsz;
869 1.100 mrg int i;
870 1.1 augustss
871 1.113 mrg KASSERT((void *)sc == un);
872 1.104 mrg
873 1.28 dyoung aprint_naive("\n");
874 1.28 dyoung aprint_normal("\n");
875 1.29 plunky devinfop = usbd_devinfo_alloc(dev, 0);
876 1.29 plunky aprint_normal_dev(self, "%s\n", devinfop);
877 1.29 plunky usbd_devinfo_free(devinfop);
878 1.1 augustss
879 1.104 mrg un->un_dev = self;
880 1.104 mrg un->un_udev = dev;
881 1.104 mrg un->un_sc = sc;
882 1.107 mrg un->un_ops = &axe_ops;
883 1.109 mrg un->un_rx_xfer_flags = USBD_SHORT_XFER_OK;
884 1.109 mrg un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER;
885 1.109 mrg un->un_rx_list_cnt = AXE_RX_LIST_CNT;
886 1.109 mrg un->un_tx_list_cnt = AXE_TX_LIST_CNT;
887 1.104 mrg
888 1.1 augustss err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1);
889 1.1 augustss if (err) {
890 1.61 skrll aprint_error_dev(self, "failed to set configuration"
891 1.61 skrll ", err=%s\n", usbd_errstr(err));
892 1.28 dyoung return;
893 1.1 augustss }
894 1.1 augustss
895 1.108 mrg un->un_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags;
896 1.35 pgoyette
897 1.104 mrg err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &un->un_iface);
898 1.1 augustss if (err) {
899 1.25 cube aprint_error_dev(self, "getting interface handle failed\n");
900 1.28 dyoung return;
901 1.1 augustss }
902 1.1 augustss
903 1.104 mrg id = usbd_get_interface_descriptor(un->un_iface);
904 1.1 augustss
905 1.35 pgoyette /* decide on what our bufsize will be */
906 1.108 mrg if (AXE_IS_178_FAMILY(un))
907 1.104 mrg bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ?
908 1.35 pgoyette AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ;
909 1.35 pgoyette else
910 1.104 mrg bufsz = AXE_172_BUFSZ;
911 1.109 mrg un->un_rx_bufsz = un->un_tx_bufsz = bufsz;
912 1.104 mrg
913 1.104 mrg un->un_ed[USBNET_ENDPT_RX] = 0;
914 1.104 mrg un->un_ed[USBNET_ENDPT_TX] = 0;
915 1.104 mrg un->un_ed[USBNET_ENDPT_INTR] = 0;
916 1.76 skrll
917 1.1 augustss /* Find endpoints. */
918 1.1 augustss for (i = 0; i < id->bNumEndpoints; i++) {
919 1.104 mrg ed = usbd_interface2endpoint_descriptor(un->un_iface, i);
920 1.38 tsutsui if (ed == NULL) {
921 1.25 cube aprint_error_dev(self, "couldn't get ep %d\n", i);
922 1.28 dyoung return;
923 1.1 augustss }
924 1.76 skrll const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes);
925 1.76 skrll const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress);
926 1.76 skrll
927 1.76 skrll if (dir == UE_DIR_IN && xt == UE_BULK &&
928 1.104 mrg un->un_ed[USBNET_ENDPT_RX] == 0) {
929 1.104 mrg un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress;
930 1.76 skrll } else if (dir == UE_DIR_OUT && xt == UE_BULK &&
931 1.104 mrg un->un_ed[USBNET_ENDPT_TX] == 0) {
932 1.104 mrg un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress;
933 1.76 skrll } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) {
934 1.104 mrg un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress;
935 1.1 augustss }
936 1.1 augustss }
937 1.1 augustss
938 1.100 mrg /* Set these up now for axe_cmd(). */
939 1.109 mrg usbnet_attach(un, "axedet");
940 1.1 augustss
941 1.35 pgoyette /* We need the PHYID for init dance in some cases */
942 1.104 mrg usbnet_lock_mii(un);
943 1.86 christos if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) {
944 1.86 christos aprint_error_dev(self, "failed to read phyaddrs\n");
945 1.100 mrg
946 1.86 christos return;
947 1.86 christos }
948 1.35 pgoyette
949 1.83 pgoyette DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx",
950 1.76 skrll sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0);
951 1.104 mrg un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
952 1.104 mrg if (un->un_phyno == -1)
953 1.104 mrg un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
954 1.104 mrg if (un->un_phyno == -1) {
955 1.76 skrll DPRINTF(" no valid PHY address found, assuming PHY address 0",
956 1.76 skrll 0, 0, 0, 0);
957 1.104 mrg un->un_phyno = 0;
958 1.66 roy }
959 1.35 pgoyette
960 1.76 skrll /* Initialize controller and get station address. */
961 1.76 skrll
962 1.104 mrg axe_ax_init(un);
963 1.86 christos
964 1.1 augustss /*
965 1.76 skrll * Fetch IPG values.
966 1.1 augustss */
967 1.108 mrg if (un->un_flags & (AX772A | AX772B)) {
968 1.76 skrll /* Set IPG values. */
969 1.76 skrll sc->axe_ipgs[0] = AXE_IPG0_DEFAULT;
970 1.76 skrll sc->axe_ipgs[1] = AXE_IPG1_DEFAULT;
971 1.76 skrll sc->axe_ipgs[2] = AXE_IPG2_DEFAULT;
972 1.86 christos } else {
973 1.86 christos if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) {
974 1.86 christos aprint_error_dev(self, "failed to read ipg\n");
975 1.104 mrg usbnet_unlock_mii(un);
976 1.86 christos return;
977 1.86 christos }
978 1.86 christos }
979 1.1 augustss
980 1.104 mrg usbnet_unlock_mii(un);
981 1.1 augustss
982 1.108 mrg if (AXE_IS_178_FAMILY(un))
983 1.104 mrg usbnet_ec(un)->ec_capabilities = ETHERCAP_VLAN_MTU;
984 1.108 mrg if (un->un_flags & AX772B) {
985 1.104 mrg struct ifnet *ifp = usbnet_ifp(un);
986 1.104 mrg
987 1.76 skrll ifp->if_capabilities =
988 1.76 skrll IFCAP_CSUM_IPv4_Rx |
989 1.76 skrll IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
990 1.76 skrll IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
991 1.76 skrll /*
992 1.76 skrll * Checksum offloading of AX88772B also works with VLAN
993 1.76 skrll * tagged frames but there is no way to take advantage
994 1.76 skrll * of the feature because vlan(4) assumes
995 1.76 skrll * IFCAP_VLAN_HWTAGGING is prerequisite condition to
996 1.76 skrll * support checksum offloading with VLAN. VLAN hardware
997 1.76 skrll * tagging support of AX88772B is very limited so it's
998 1.76 skrll * not possible to announce IFCAP_VLAN_HWTAGGING.
999 1.76 skrll */
1000 1.76 skrll }
1001 1.76 skrll u_int adv_pause;
1002 1.108 mrg if (un->un_flags & (AX772A | AX772B | AX178))
1003 1.76 skrll adv_pause = MIIF_DOPAUSE;
1004 1.76 skrll else
1005 1.76 skrll adv_pause = 0;
1006 1.76 skrll adv_pause = 0;
1007 1.1 augustss
1008 1.104 mrg usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST,
1009 1.104 mrg 0, adv_pause);
1010 1.1 augustss }
1011 1.1 augustss
1012 1.35 pgoyette static void
1013 1.110 mrg axe_rx_loop(struct usbnet * un, struct usbd_xfer *xfer,
1014 1.110 mrg struct usbnet_chain *c, uint32_t total_len)
1015 1.1 augustss {
1016 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
1017 1.104 mrg struct axe_softc * const sc = usbnet_softc(un);
1018 1.104 mrg struct ifnet *ifp = usbnet_ifp(un);
1019 1.104 mrg uint8_t *buf = c->unc_buf;
1020 1.1 augustss
1021 1.35 pgoyette do {
1022 1.76 skrll u_int pktlen = 0;
1023 1.76 skrll u_int rxlen = 0;
1024 1.76 skrll int flags = 0;
1025 1.104 mrg
1026 1.108 mrg if ((un->un_flags & AXSTD_FRAME) != 0) {
1027 1.76 skrll struct axe_sframe_hdr hdr;
1028 1.76 skrll
1029 1.35 pgoyette if (total_len < sizeof(hdr)) {
1030 1.35 pgoyette ifp->if_ierrors++;
1031 1.104 mrg break;
1032 1.35 pgoyette }
1033 1.35 pgoyette
1034 1.94 rin #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1)
1035 1.94 rin /*
1036 1.94 rin * XXX hdr is 2-byte aligned in buf, not 4-byte.
1037 1.94 rin * For some architectures, __builtin_memcpy() of
1038 1.94 rin * GCC 6 attempts to copy sizeof(hdr) = 4 bytes
1039 1.94 rin * at onece, which results in alignment error.
1040 1.94 rin */
1041 1.94 rin hdr.len = *(uint16_t *)buf;
1042 1.94 rin hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t));
1043 1.94 rin #else
1044 1.35 pgoyette memcpy(&hdr, buf, sizeof(hdr));
1045 1.94 rin #endif
1046 1.76 skrll
1047 1.83 pgoyette DPRINTFN(20, "total_len %#jx len %jx ilen %#jx",
1048 1.76 skrll total_len,
1049 1.76 skrll (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK),
1050 1.76 skrll (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0);
1051 1.76 skrll
1052 1.35 pgoyette total_len -= sizeof(hdr);
1053 1.42 tsutsui buf += sizeof(hdr);
1054 1.35 pgoyette
1055 1.58 christos if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^
1056 1.62 christos (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) !=
1057 1.62 christos AXE_RH1M_RXLEN_MASK) {
1058 1.35 pgoyette ifp->if_ierrors++;
1059 1.104 mrg break;
1060 1.35 pgoyette }
1061 1.42 tsutsui
1062 1.63 christos rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK;
1063 1.42 tsutsui if (total_len < rxlen) {
1064 1.42 tsutsui pktlen = total_len;
1065 1.42 tsutsui total_len = 0;
1066 1.42 tsutsui } else {
1067 1.43 tsutsui pktlen = rxlen;
1068 1.43 tsutsui rxlen = roundup2(rxlen, 2);
1069 1.42 tsutsui total_len -= rxlen;
1070 1.35 pgoyette }
1071 1.35 pgoyette
1072 1.108 mrg } else if ((un->un_flags & AXCSUM_FRAME) != 0) {
1073 1.76 skrll struct axe_csum_hdr csum_hdr;
1074 1.76 skrll
1075 1.104 mrg if (total_len < sizeof(csum_hdr)) {
1076 1.76 skrll ifp->if_ierrors++;
1077 1.104 mrg break;
1078 1.76 skrll }
1079 1.76 skrll
1080 1.76 skrll memcpy(&csum_hdr, buf, sizeof(csum_hdr));
1081 1.76 skrll
1082 1.76 skrll csum_hdr.len = le16toh(csum_hdr.len);
1083 1.76 skrll csum_hdr.ilen = le16toh(csum_hdr.ilen);
1084 1.76 skrll csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
1085 1.76 skrll
1086 1.83 pgoyette DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx"
1087 1.83 pgoyette " cstatus %#jx", total_len,
1088 1.76 skrll csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus);
1089 1.76 skrll
1090 1.76 skrll if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
1091 1.76 skrll AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
1092 1.76 skrll sc->sc_lenmask) {
1093 1.76 skrll /* we lost sync */
1094 1.76 skrll ifp->if_ierrors++;
1095 1.83 pgoyette DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx "
1096 1.83 pgoyette "err",
1097 1.76 skrll AXE_CSUM_RXBYTES(csum_hdr.len),
1098 1.76 skrll AXE_CSUM_RXBYTES(csum_hdr.ilen),
1099 1.76 skrll sc->sc_lenmask, 0);
1100 1.104 mrg break;
1101 1.76 skrll }
1102 1.76 skrll /*
1103 1.76 skrll * Get total transferred frame length including
1104 1.76 skrll * checksum header. The length should be multiple
1105 1.76 skrll * of 4.
1106 1.76 skrll */
1107 1.76 skrll pktlen = AXE_CSUM_RXBYTES(csum_hdr.len);
1108 1.78 skrll u_int len = sizeof(csum_hdr) + pktlen;
1109 1.76 skrll len = (len + 3) & ~3;
1110 1.76 skrll if (total_len < len) {
1111 1.83 pgoyette DPRINTFN(20, "total_len %#jx < len %#jx",
1112 1.76 skrll total_len, len, 0, 0);
1113 1.76 skrll /* invalid length */
1114 1.76 skrll ifp->if_ierrors++;
1115 1.104 mrg break;
1116 1.76 skrll }
1117 1.76 skrll buf += sizeof(csum_hdr);
1118 1.76 skrll
1119 1.76 skrll const uint16_t cstatus = csum_hdr.cstatus;
1120 1.76 skrll
1121 1.76 skrll if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) {
1122 1.76 skrll if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR)
1123 1.76 skrll flags |= M_CSUM_TCP_UDP_BAD;
1124 1.76 skrll if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR)
1125 1.76 skrll flags |= M_CSUM_IPv4_BAD;
1126 1.76 skrll
1127 1.76 skrll const uint16_t l4type =
1128 1.76 skrll cstatus & AXE_CSUM_HDR_L4_TYPE_MASK;
1129 1.76 skrll
1130 1.76 skrll if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP)
1131 1.76 skrll flags |= M_CSUM_TCPv4;
1132 1.76 skrll if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP)
1133 1.76 skrll flags |= M_CSUM_UDPv4;
1134 1.76 skrll }
1135 1.76 skrll if (total_len < len) {
1136 1.76 skrll pktlen = total_len;
1137 1.76 skrll total_len = 0;
1138 1.76 skrll } else {
1139 1.76 skrll total_len -= len;
1140 1.76 skrll rxlen = len - sizeof(csum_hdr);
1141 1.76 skrll }
1142 1.83 pgoyette DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx"
1143 1.83 pgoyette " rxlen %#jx", total_len, len, pktlen, rxlen);
1144 1.35 pgoyette } else { /* AX172 */
1145 1.42 tsutsui pktlen = rxlen = total_len;
1146 1.35 pgoyette total_len = 0;
1147 1.35 pgoyette }
1148 1.35 pgoyette
1149 1.105 mrg usbnet_enqueue(un, buf, pktlen, flags, 0, 0);
1150 1.42 tsutsui buf += rxlen;
1151 1.1 augustss
1152 1.35 pgoyette } while (total_len > 0);
1153 1.1 augustss
1154 1.76 skrll DPRINTFN(10, "start rx", 0, 0, 0, 0);
1155 1.1 augustss }
1156 1.1 augustss
1157 1.104 mrg static unsigned
1158 1.110 mrg axe_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c)
1159 1.1 augustss {
1160 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
1161 1.110 mrg struct axe_sframe_hdr hdr, tlr;
1162 1.110 mrg size_t hdr_len = 0, tlr_len = 0;
1163 1.38 tsutsui int length, boundary;
1164 1.1 augustss
1165 1.104 mrg usbnet_isowned_tx(un);
1166 1.1 augustss
1167 1.108 mrg if (AXE_IS_178_FAMILY(un)) {
1168 1.110 mrg /*
1169 1.110 mrg * Copy the mbuf data into a contiguous buffer, leaving two
1170 1.110 mrg * bytes at the beginning to hold the frame length.
1171 1.110 mrg */
1172 1.104 mrg boundary = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64;
1173 1.35 pgoyette
1174 1.35 pgoyette hdr.len = htole16(m->m_pkthdr.len);
1175 1.35 pgoyette hdr.ilen = ~hdr.len;
1176 1.110 mrg hdr_len = sizeof(hdr);
1177 1.35 pgoyette
1178 1.110 mrg length = hdr_len + m->m_pkthdr.len;
1179 1.35 pgoyette
1180 1.35 pgoyette if ((length % boundary) == 0) {
1181 1.110 mrg tlr.len = 0x0000;
1182 1.110 mrg tlr.ilen = 0xffff;
1183 1.110 mrg tlr_len = sizeof(tlr);
1184 1.35 pgoyette }
1185 1.104 mrg DPRINTFN(20, "length %jx m_pkthdr.len %jx hdrsize %#jx",
1186 1.104 mrg length, m->m_pkthdr.len, sizeof(hdr), 0);
1187 1.35 pgoyette }
1188 1.1 augustss
1189 1.112 mrg if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - hdr_len - tlr_len)
1190 1.111 mrg return 0;
1191 1.110 mrg length = hdr_len + m->m_pkthdr.len + tlr_len;
1192 1.110 mrg
1193 1.110 mrg if (hdr_len)
1194 1.110 mrg memcpy(c->unc_buf, &hdr, hdr_len);
1195 1.110 mrg m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf + hdr_len);
1196 1.110 mrg if (tlr_len)
1197 1.110 mrg memcpy(c->unc_buf + length, &tlr, tlr_len);
1198 1.1 augustss
1199 1.104 mrg return length;
1200 1.1 augustss }
1201 1.1 augustss
1202 1.76 skrll static void
1203 1.76 skrll axe_csum_cfg(struct axe_softc *sc)
1204 1.76 skrll {
1205 1.104 mrg struct usbnet * const un = &sc->axe_un;
1206 1.104 mrg struct ifnet * const ifp = usbnet_ifp(un);
1207 1.76 skrll uint16_t csum1, csum2;
1208 1.76 skrll
1209 1.108 mrg if ((un->un_flags & AX772B) != 0) {
1210 1.76 skrll csum1 = 0;
1211 1.76 skrll csum2 = 0;
1212 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0)
1213 1.76 skrll csum1 |= AXE_TXCSUM_IP;
1214 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0)
1215 1.76 skrll csum1 |= AXE_TXCSUM_TCP;
1216 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0)
1217 1.76 skrll csum1 |= AXE_TXCSUM_UDP;
1218 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0)
1219 1.76 skrll csum1 |= AXE_TXCSUM_TCPV6;
1220 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0)
1221 1.76 skrll csum1 |= AXE_TXCSUM_UDPV6;
1222 1.76 skrll axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1223 1.76 skrll csum1 = 0;
1224 1.76 skrll csum2 = 0;
1225 1.76 skrll
1226 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0)
1227 1.76 skrll csum1 |= AXE_RXCSUM_IP;
1228 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0)
1229 1.76 skrll csum1 |= AXE_RXCSUM_TCP;
1230 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0)
1231 1.76 skrll csum1 |= AXE_RXCSUM_UDP;
1232 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0)
1233 1.76 skrll csum1 |= AXE_RXCSUM_TCPV6;
1234 1.76 skrll if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0)
1235 1.76 skrll csum1 |= AXE_RXCSUM_UDPV6;
1236 1.76 skrll axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1237 1.76 skrll }
1238 1.76 skrll }
1239 1.76 skrll
1240 1.35 pgoyette static int
1241 1.100 mrg axe_init_locked(struct ifnet *ifp)
1242 1.1 augustss {
1243 1.76 skrll AXEHIST_FUNC(); AXEHIST_CALLED();
1244 1.104 mrg struct usbnet * const un = ifp->if_softc;
1245 1.104 mrg struct axe_softc * const sc = usbnet_softc(un);
1246 1.38 tsutsui int rxmode;
1247 1.35 pgoyette
1248 1.104 mrg usbnet_isowned(un);
1249 1.100 mrg
1250 1.107 mrg if (usbnet_isdying(un))
1251 1.100 mrg return EIO;
1252 1.1 augustss
1253 1.100 mrg /* Cancel pending I/O */
1254 1.104 mrg usbnet_stop(un, ifp, 1);
1255 1.104 mrg
1256 1.104 mrg usbnet_lock_mii_un_locked(un);
1257 1.1 augustss
1258 1.100 mrg /* Reset the ethernet interface. */
1259 1.104 mrg axe_reset(un);
1260 1.35 pgoyette
1261 1.76 skrll #if 0
1262 1.76 skrll ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
1263 1.76 skrll AX_GPIO_GPO2EN, 5, in_pm);
1264 1.76 skrll #endif
1265 1.76 skrll /* Set MAC address and transmitter IPG values. */
1266 1.108 mrg if (AXE_IS_178_FAMILY(un)) {
1267 1.104 mrg axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr);
1268 1.35 pgoyette axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2],
1269 1.35 pgoyette (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL);
1270 1.76 skrll } else {
1271 1.104 mrg axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr);
1272 1.35 pgoyette axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL);
1273 1.35 pgoyette axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL);
1274 1.35 pgoyette axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL);
1275 1.35 pgoyette }
1276 1.108 mrg if (AXE_IS_178_FAMILY(un)) {
1277 1.108 mrg un->un_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME);
1278 1.108 mrg if ((un->un_flags & AX772B) != 0 &&
1279 1.76 skrll (ifp->if_capenable & AX_RXCSUM) != 0) {
1280 1.76 skrll sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK;
1281 1.108 mrg un->un_flags |= AXCSUM_FRAME;
1282 1.76 skrll } else {
1283 1.76 skrll sc->sc_lenmask = AXE_HDR_LEN_MASK;
1284 1.108 mrg un->un_flags |= AXSTD_FRAME;
1285 1.76 skrll }
1286 1.76 skrll }
1287 1.76 skrll
1288 1.76 skrll /* Configure TX/RX checksum offloading. */
1289 1.76 skrll axe_csum_cfg(sc);
1290 1.1 augustss
1291 1.108 mrg if (un->un_flags & AX772B) {
1292 1.76 skrll /* AX88772B uses different maximum frame burst configuration. */
1293 1.76 skrll axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1294 1.76 skrll ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1295 1.76 skrll ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1296 1.76 skrll }
1297 1.1 augustss /* Enable receiver, set RX mode */
1298 1.76 skrll rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1299 1.108 mrg if (AXE_IS_178_FAMILY(un)) {
1300 1.108 mrg if (un->un_flags & AX772B) {
1301 1.76 skrll /*
1302 1.76 skrll * Select RX header format type 1. Aligning IP
1303 1.76 skrll * header on 4 byte boundary is not needed when
1304 1.76 skrll * checksum offloading feature is not used
1305 1.76 skrll * because we always copy the received frame in
1306 1.76 skrll * RX handler. When RX checksum offloading is
1307 1.76 skrll * active, aligning IP header is required to
1308 1.76 skrll * reflect actual frame length including RX
1309 1.76 skrll * header size.
1310 1.76 skrll */
1311 1.76 skrll rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1312 1.108 mrg if (un->un_flags & AXCSUM_FRAME)
1313 1.76 skrll rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN;
1314 1.76 skrll } else {
1315 1.76 skrll /*
1316 1.76 skrll * Default Rx buffer size is too small to get
1317 1.76 skrll * maximum performance.
1318 1.76 skrll */
1319 1.76 skrll #if 0
1320 1.104 mrg if (un->un_udev->ud_speed == USB_SPEED_HIGH) {
1321 1.76 skrll /* Largest possible USB buffer size for AX88178 */
1322 1.100 mrg }
1323 1.76 skrll #endif
1324 1.76 skrll rxmode |= AXE_178_RXCMD_MFB_16384;
1325 1.35 pgoyette }
1326 1.76 skrll } else {
1327 1.35 pgoyette rxmode |= AXE_172_RXCMD_UNICAST;
1328 1.76 skrll }
1329 1.76 skrll
1330 1.1 augustss
1331 1.1 augustss /* If we want promiscuous mode, set the allframes bit. */
1332 1.1 augustss if (ifp->if_flags & IFF_PROMISC)
1333 1.1 augustss rxmode |= AXE_RXCMD_PROMISC;
1334 1.1 augustss
1335 1.1 augustss if (ifp->if_flags & IFF_BROADCAST)
1336 1.1 augustss rxmode |= AXE_RXCMD_BROADCAST;
1337 1.1 augustss
1338 1.83 pgoyette DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0);
1339 1.76 skrll
1340 1.1 augustss axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1341 1.1 augustss
1342 1.1 augustss /* Load the multicast filter. */
1343 1.104 mrg axe_setiff_locked(un);
1344 1.1 augustss
1345 1.104 mrg usbnet_unlock_mii_un_locked(un);
1346 1.1 augustss
1347 1.107 mrg return usbnet_init_rx_tx(un);
1348 1.1 augustss }
1349 1.1 augustss
1350 1.35 pgoyette static int
1351 1.100 mrg axe_init(struct ifnet *ifp)
1352 1.100 mrg {
1353 1.104 mrg struct usbnet * const un = ifp->if_softc;
1354 1.100 mrg
1355 1.104 mrg usbnet_lock(un);
1356 1.100 mrg int ret = axe_init_locked(ifp);
1357 1.104 mrg usbnet_unlock(un);
1358 1.100 mrg
1359 1.100 mrg return ret;
1360 1.100 mrg }
1361 1.100 mrg
1362 1.100 mrg static int
1363 1.110 mrg axe_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1364 1.1 augustss {
1365 1.104 mrg struct usbnet * const un = ifp->if_softc;
1366 1.1 augustss
1367 1.96 msaitoh switch (cmd) {
1368 1.104 mrg case SIOCADDMULTI:
1369 1.104 mrg case SIOCDELMULTI:
1370 1.104 mrg axe_setiff(un);
1371 1.1 augustss break;
1372 1.35 pgoyette default:
1373 1.104 mrg break;
1374 1.1 augustss }
1375 1.1 augustss
1376 1.104 mrg return 0;
1377 1.100 mrg }
1378 1.71 skrll
1379 1.100 mrg static void
1380 1.110 mrg axe_stop(struct ifnet *ifp, int disable)
1381 1.100 mrg {
1382 1.104 mrg struct usbnet * const un = ifp->if_softc;
1383 1.100 mrg
1384 1.104 mrg usbnet_lock_mii_un_locked(un);
1385 1.104 mrg axe_reset(un);
1386 1.104 mrg usbnet_unlock_mii_un_locked(un);
1387 1.1 augustss }
1388 1.48 pgoyette
1389 1.48 pgoyette #ifdef _MODULE
1390 1.48 pgoyette #include "ioconf.c"
1391 1.48 pgoyette #endif
1392 1.48 pgoyette
1393 1.114 mrg USBNET_MODULE(axe)
1394