if_axe.c revision 1.101
1 /* $NetBSD: if_axe.c,v 1.101 2019/07/21 09:38:28 mrg Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.101 2019/07/21 09:38:28 mrg Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #include "opt_net_mpsafe.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/kernel.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/socket.h> 106 #include <sys/sockio.h> 107 #include <sys/systm.h> 108 109 #include <sys/rndsource.h> 110 111 #include <net/if.h> 112 #include <net/if_dl.h> 113 #include <net/if_ether.h> 114 #include <net/if_media.h> 115 116 #include <net/bpf.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/usb/usb.h> 122 #include <dev/usb/usbhist.h> 123 #include <dev/usb/usbdi.h> 124 #include <dev/usb/usbdi_util.h> 125 #include <dev/usb/usbdivar.h> 126 #include <dev/usb/usbdevs.h> 127 128 #include <dev/usb/if_axereg.h> 129 130 struct axe_type { 131 struct usb_devno axe_dev; 132 uint16_t axe_flags; 133 }; 134 135 struct axe_softc; 136 137 struct axe_chain { 138 struct axe_softc *axe_sc; 139 struct usbd_xfer *axe_xfer; 140 uint8_t *axe_buf; 141 }; 142 143 struct axe_cdata { 144 struct axe_chain axe_tx_chain[AXE_TX_LIST_CNT]; 145 struct axe_chain axe_rx_chain[AXE_RX_LIST_CNT]; 146 int axe_tx_prod; 147 int axe_tx_cons; 148 int axe_tx_cnt; 149 int axe_rx_prod; 150 }; 151 152 struct axe_softc { 153 device_t axe_dev; 154 struct ethercom axe_ec; 155 struct mii_data axe_mii; 156 krndsource_t rnd_source; 157 struct usbd_device * axe_udev; 158 struct usbd_interface * axe_iface; 159 160 uint16_t axe_vendor; 161 uint16_t axe_product; 162 uint16_t axe_timer; 163 uint32_t axe_flags; /* copied from axe_type */ 164 #define AX178 __BIT(0) /* AX88178 */ 165 #define AX772 __BIT(1) /* AX88772 */ 166 #define AX772A __BIT(2) /* AX88772A */ 167 #define AX772B __BIT(3) /* AX88772B */ 168 #define AXSTD_FRAME __BIT(12) 169 #define AXCSUM_FRAME __BIT(13) 170 171 int axe_ed[AXE_ENDPT_MAX]; 172 struct usbd_pipe * axe_ep[AXE_ENDPT_MAX]; 173 int axe_if_flags; 174 int axe_phyno; 175 struct axe_cdata axe_cdata; 176 struct callout axe_stat_ch; 177 178 uint8_t axe_enaddr[ETHER_ADDR_LEN]; 179 180 int axe_refcnt; 181 bool axe_dying; 182 bool axe_stopping; 183 bool axe_attached; 184 185 struct usb_task axe_tick_task; 186 187 kmutex_t axe_lock; 188 kmutex_t axe_mii_lock; 189 kmutex_t axe_rxlock; 190 kmutex_t axe_txlock; 191 kcondvar_t axe_detachcv; 192 193 int axe_link; 194 195 uint8_t axe_ipgs[3]; 196 uint8_t axe_phyaddrs[2]; 197 uint16_t sc_pwrcfg; 198 uint16_t sc_lenmask; 199 200 struct timeval axe_rx_notice; 201 struct timeval axe_tx_notice; 202 int axe_bufsz; 203 204 #define sc_if axe_ec.ec_if 205 }; 206 207 #define AXE_IS_178_FAMILY(sc) \ 208 ((sc)->axe_flags & (AX772 | AX772A | AX772B | AX178)) 209 210 #define AXE_IS_772(sc) \ 211 ((sc)->axe_flags & (AX772 | AX772A | AX772B)) 212 213 #define AX_RXCSUM \ 214 (IFCAP_CSUM_IPv4_Rx | \ 215 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 216 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 217 218 #define AX_TXCSUM \ 219 (IFCAP_CSUM_IPv4_Tx | \ 220 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 221 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 222 223 /* 224 * AXE_178_MAX_FRAME_BURST 225 * max frame burst size for Ax88178 and Ax88772 226 * 0 2048 bytes 227 * 1 4096 bytes 228 * 2 8192 bytes 229 * 3 16384 bytes 230 * use the largest your system can handle without USB stalling. 231 * 232 * NB: 88772 parts appear to generate lots of input errors with 233 * a 2K rx buffer and 8K is only slightly faster than 4K on an 234 * EHCI port on a T42 so change at your own risk. 235 */ 236 #define AXE_178_MAX_FRAME_BURST 1 237 238 239 #ifdef USB_DEBUG 240 #ifndef AXE_DEBUG 241 #define axedebug 0 242 #else 243 static int axedebug = 20; 244 245 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 246 { 247 int err; 248 const struct sysctlnode *rnode; 249 const struct sysctlnode *cnode; 250 251 err = sysctl_createv(clog, 0, NULL, &rnode, 252 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 253 SYSCTL_DESCR("axe global controls"), 254 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 255 256 if (err) 257 goto fail; 258 259 /* control debugging printfs */ 260 err = sysctl_createv(clog, 0, &rnode, &cnode, 261 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 262 "debug", SYSCTL_DESCR("Enable debugging output"), 263 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 264 if (err) 265 goto fail; 266 267 return; 268 fail: 269 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 270 } 271 272 #endif /* AXE_DEBUG */ 273 #endif /* USB_DEBUG */ 274 275 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 276 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 277 #define AXEHIST_FUNC() USBHIST_FUNC() 278 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 279 280 /* 281 * Various supported device vendors/products. 282 */ 283 static const struct axe_type axe_devs[] = { 284 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 285 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 286 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 287 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 288 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 289 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 290 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 291 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 292 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 293 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 294 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 295 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 296 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 297 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 298 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 299 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 300 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 301 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 302 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 303 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 304 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 305 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 306 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 307 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 308 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 309 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 310 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 311 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 312 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 313 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 314 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 315 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 316 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 317 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 318 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 319 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 320 }; 321 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 322 323 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 324 { 0x8000, 0x8001, 2048 }, 325 { 0x8100, 0x8147, 4096 }, 326 { 0x8200, 0x81EB, 6144 }, 327 { 0x8300, 0x83D7, 8192 }, 328 { 0x8400, 0x851E, 16384 }, 329 { 0x8500, 0x8666, 20480 }, 330 { 0x8600, 0x87AE, 24576 }, 331 { 0x8700, 0x8A3D, 32768 } 332 }; 333 334 int axe_match(device_t, cfdata_t, void *); 335 void axe_attach(device_t, device_t, void *); 336 int axe_detach(device_t, int); 337 int axe_activate(device_t, devact_t); 338 339 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 340 axe_match, axe_attach, axe_detach, axe_activate); 341 342 static int axe_tx_list_init(struct axe_softc *); 343 static int axe_rx_list_init(struct axe_softc *); 344 static int axe_encap(struct axe_softc *, struct mbuf *, int); 345 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 346 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 347 static void axe_tick(void *); 348 static void axe_tick_task(void *); 349 static void axe_start(struct ifnet *); 350 static void axe_start_locked(struct ifnet *); 351 static int axe_ioctl(struct ifnet *, u_long, void *); 352 static int axe_init(struct ifnet *); 353 static int axe_init_locked(struct ifnet *); 354 static void axe_stop(struct ifnet *, int); 355 static void axe_stop_locked(struct ifnet *, int); 356 static void axe_watchdog(struct ifnet *); 357 static int axe_miibus_readreg(device_t, int, int, uint16_t *); 358 static int axe_miibus_readreg_locked(device_t, int, int, uint16_t *); 359 static int axe_miibus_writereg(device_t, int, int, uint16_t); 360 static int axe_miibus_writereg_locked(device_t, int, int, uint16_t); 361 static void axe_miibus_statchg(struct ifnet *); 362 static int axe_cmd(struct axe_softc *, int, int, int, void *); 363 static void axe_reset(struct axe_softc *); 364 365 static void axe_setmulti(struct axe_softc *); 366 static void axe_setmulti_locked(struct axe_softc *); 367 static void axe_lock_mii(struct axe_softc *); 368 static void axe_unlock_mii(struct axe_softc *); 369 370 static void axe_ax88178_init(struct axe_softc *); 371 static void axe_ax88772_init(struct axe_softc *); 372 static void axe_ax88772a_init(struct axe_softc *); 373 static void axe_ax88772b_init(struct axe_softc *); 374 375 /* Get exclusive access to the MII registers */ 376 static void 377 axe_lock_mii(struct axe_softc *sc) 378 { 379 380 mutex_enter(&sc->axe_lock); 381 sc->axe_refcnt++; 382 mutex_exit(&sc->axe_lock); 383 384 mutex_enter(&sc->axe_mii_lock); 385 } 386 387 static void 388 axe_lock_mii_sc_locked(struct axe_softc *sc) 389 { 390 KASSERT(mutex_owned(&sc->axe_lock)); 391 392 sc->axe_refcnt++; 393 mutex_enter(&sc->axe_mii_lock); 394 } 395 396 static void 397 axe_unlock_mii(struct axe_softc *sc) 398 { 399 400 mutex_exit(&sc->axe_mii_lock); 401 mutex_enter(&sc->axe_lock); 402 if (--sc->axe_refcnt < 0) 403 cv_broadcast(&sc->axe_detachcv); 404 mutex_exit(&sc->axe_lock); 405 } 406 407 static void 408 axe_unlock_mii_sc_locked(struct axe_softc *sc) 409 { 410 KASSERT(mutex_owned(&sc->axe_lock)); 411 412 mutex_exit(&sc->axe_mii_lock); 413 if (--sc->axe_refcnt < 0) 414 cv_broadcast(&sc->axe_detachcv); 415 } 416 417 static int 418 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 419 { 420 AXEHIST_FUNC(); AXEHIST_CALLED(); 421 usb_device_request_t req; 422 usbd_status err; 423 424 KASSERT(mutex_owned(&sc->axe_mii_lock)); 425 426 if (sc->axe_dying) 427 return -1; 428 429 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 430 431 if (AXE_CMD_DIR(cmd)) 432 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 433 else 434 req.bmRequestType = UT_READ_VENDOR_DEVICE; 435 req.bRequest = AXE_CMD_CMD(cmd); 436 USETW(req.wValue, val); 437 USETW(req.wIndex, index); 438 USETW(req.wLength, AXE_CMD_LEN(cmd)); 439 440 err = usbd_do_request(sc->axe_udev, &req, buf); 441 442 if (err) { 443 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 444 return -1; 445 } 446 return 0; 447 } 448 449 static int 450 axe_miibus_readreg_locked(device_t dev, int phy, int reg, uint16_t *val) 451 { 452 AXEHIST_FUNC(); AXEHIST_CALLED(); 453 struct axe_softc *sc = device_private(dev); 454 usbd_status err; 455 uint16_t data; 456 457 mutex_enter(&sc->axe_lock); 458 if (sc->axe_dying || sc->axe_phyno != phy) { 459 mutex_exit(&sc->axe_lock); 460 return -1; 461 } 462 mutex_exit(&sc->axe_lock); 463 464 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 465 466 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 467 468 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 469 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 470 471 if (err) { 472 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 473 return err; 474 } 475 476 *val = le16toh(data); 477 if (AXE_IS_772(sc) && reg == MII_BMSR) { 478 /* 479 * BMSR of AX88772 indicates that it supports extended 480 * capability but the extended status register is 481 * reserved for embedded ethernet PHY. So clear the 482 * extended capability bit of BMSR. 483 */ 484 *val &= ~BMSR_EXTCAP; 485 } 486 487 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0); 488 489 return 0; 490 } 491 492 static int 493 axe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 494 { 495 struct axe_softc *sc = device_private(dev); 496 int rv; 497 498 mutex_enter(&sc->axe_lock); 499 if (sc->axe_dying || sc->axe_phyno != phy) { 500 mutex_exit(&sc->axe_lock); 501 return -1; 502 } 503 mutex_exit(&sc->axe_lock); 504 505 axe_lock_mii(sc); 506 rv = axe_miibus_readreg_locked(dev, phy, reg, val); 507 axe_unlock_mii(sc); 508 509 return rv; 510 } 511 512 static int 513 axe_miibus_writereg_locked(device_t dev, int phy, int reg, uint16_t aval) 514 { 515 struct axe_softc *sc = device_private(dev); 516 usbd_status err; 517 uint16_t val; 518 519 val = htole16(aval); 520 521 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 522 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 523 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 524 525 if (err) { 526 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 527 return err; 528 } 529 530 return 0; 531 } 532 533 static int 534 axe_miibus_writereg(device_t dev, int phy, int reg, uint16_t aval) 535 { 536 struct axe_softc *sc = device_private(dev); 537 int rv; 538 539 mutex_enter(&sc->axe_lock); 540 if (sc->axe_dying || sc->axe_phyno != phy) { 541 mutex_exit(&sc->axe_lock); 542 return -1; 543 } 544 mutex_exit(&sc->axe_lock); 545 546 axe_lock_mii(sc); 547 rv = axe_miibus_writereg_locked(dev, phy, reg, aval); 548 axe_unlock_mii(sc); 549 550 return rv; 551 } 552 553 static void 554 axe_miibus_statchg(struct ifnet *ifp) 555 { 556 AXEHIST_FUNC(); AXEHIST_CALLED(); 557 558 struct axe_softc * const sc = ifp->if_softc; 559 struct mii_data *mii = &sc->axe_mii; 560 int val, err; 561 562 if (sc->axe_dying) 563 return; 564 565 val = 0; 566 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 567 val |= AXE_MEDIA_FULL_DUPLEX; 568 if (AXE_IS_178_FAMILY(sc)) { 569 if ((IFM_OPTIONS(mii->mii_media_active) & 570 IFM_ETH_TXPAUSE) != 0) 571 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 572 if ((IFM_OPTIONS(mii->mii_media_active) & 573 IFM_ETH_RXPAUSE) != 0) 574 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 575 } 576 } 577 if (AXE_IS_178_FAMILY(sc)) { 578 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 579 if (sc->axe_flags & AX178) 580 val |= AXE_178_MEDIA_ENCK; 581 switch (IFM_SUBTYPE(mii->mii_media_active)) { 582 case IFM_1000_T: 583 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 584 break; 585 case IFM_100_TX: 586 val |= AXE_178_MEDIA_100TX; 587 break; 588 case IFM_10_T: 589 /* doesn't need to be handled */ 590 break; 591 } 592 } 593 594 DPRINTF("val=0x%jx", val, 0, 0, 0); 595 axe_lock_mii(sc); 596 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 597 axe_unlock_mii(sc); 598 if (err) { 599 aprint_error_dev(sc->axe_dev, "media change failed\n"); 600 return; 601 } 602 } 603 604 static void 605 axe_setmulti_locked(struct axe_softc *sc) 606 { 607 AXEHIST_FUNC(); AXEHIST_CALLED(); 608 struct ethercom *ec = &sc->axe_ec; 609 struct ifnet *ifp = &sc->sc_if; 610 struct ether_multi *enm; 611 struct ether_multistep step; 612 uint32_t h = 0; 613 uint16_t rxmode; 614 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 615 616 KASSERT(mutex_owned(&sc->axe_mii_lock)); 617 618 if (sc->axe_dying) 619 return; 620 621 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 622 aprint_error_dev(sc->axe_dev, "can't read rxmode"); 623 return; 624 } 625 rxmode = le16toh(rxmode); 626 627 rxmode &= 628 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 629 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 630 631 rxmode |= 632 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 633 634 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 635 if (ifp->if_flags & IFF_PROMISC) 636 rxmode |= AXE_RXCMD_PROMISC; 637 goto allmulti; 638 } 639 640 /* Now program new ones */ 641 ETHER_LOCK(ec); 642 ETHER_FIRST_MULTI(step, ec, enm); 643 while (enm != NULL) { 644 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 645 ETHER_ADDR_LEN) != 0) { 646 ETHER_UNLOCK(ec); 647 goto allmulti; 648 } 649 650 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 651 hashtbl[h >> 3] |= 1U << (h & 7); 652 ETHER_NEXT_MULTI(step, enm); 653 } 654 ETHER_UNLOCK(ec); 655 ifp->if_flags &= ~IFF_ALLMULTI; 656 rxmode |= AXE_RXCMD_MULTICAST; 657 658 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 659 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 660 return; 661 662 allmulti: 663 ifp->if_flags |= IFF_ALLMULTI; 664 rxmode |= AXE_RXCMD_ALLMULTI; 665 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 666 } 667 668 static void 669 axe_setmulti(struct axe_softc *sc) 670 { 671 axe_lock_mii(sc); 672 axe_setmulti_locked(sc); 673 axe_unlock_mii(sc); 674 } 675 676 static void 677 axe_ax_init(struct axe_softc *sc) 678 { 679 int cmd = AXE_178_CMD_READ_NODEID; 680 681 if (sc->axe_flags & AX178) { 682 axe_ax88178_init(sc); 683 } else if (sc->axe_flags & AX772) { 684 axe_ax88772_init(sc); 685 } else if (sc->axe_flags & AX772A) { 686 axe_ax88772a_init(sc); 687 } else if (sc->axe_flags & AX772B) { 688 axe_ax88772b_init(sc); 689 return; 690 } else { 691 cmd = AXE_172_CMD_READ_NODEID; 692 } 693 694 if (axe_cmd(sc, cmd, 0, 0, sc->axe_enaddr)) { 695 aprint_error_dev(sc->axe_dev, 696 "failed to read ethernet address\n"); 697 } 698 } 699 700 701 static void 702 axe_reset(struct axe_softc *sc) 703 { 704 705 if (sc->axe_dying) 706 return; 707 708 /* 709 * softnet_lock can be taken when NET_MPAFE is not defined when calling 710 * if_addr_init -> if_init. This doesn't mix well with the 711 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 712 * can fire during the wait and attempt to take softnet_lock and then 713 * block the softclk thread meaing the wait never ends. 714 */ 715 #ifndef NET_MPSAFE 716 /* XXX What to reset? */ 717 718 /* Wait a little while for the chip to get its brains in order. */ 719 DELAY(1000); 720 #else 721 axe_lock_mii(sc); 722 723 axe_ax_init(sc); 724 725 axe_unlock_mii(sc); 726 #endif 727 } 728 729 static int 730 axe_get_phyno(struct axe_softc *sc, int sel) 731 { 732 int phyno; 733 734 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 735 case PHY_TYPE_100_HOME: 736 /* FALLTHROUGH */ 737 case PHY_TYPE_GIG: 738 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 739 break; 740 case PHY_TYPE_SPECIAL: 741 /* FALLTHROUGH */ 742 case PHY_TYPE_RSVD: 743 /* FALLTHROUGH */ 744 case PHY_TYPE_NON_SUP: 745 /* FALLTHROUGH */ 746 default: 747 phyno = -1; 748 break; 749 } 750 751 return phyno; 752 } 753 754 #define AXE_GPIO_WRITE(x, y) do { \ 755 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 756 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 757 } while (0) 758 759 static void 760 axe_ax88178_init(struct axe_softc *sc) 761 { 762 AXEHIST_FUNC(); AXEHIST_CALLED(); 763 int gpio0, ledmode, phymode; 764 uint16_t eeprom, val; 765 766 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 767 /* XXX magic */ 768 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 769 eeprom = 0xffff; 770 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 771 772 eeprom = le16toh(eeprom); 773 774 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 775 776 /* if EEPROM is invalid we have to use to GPIO0 */ 777 if (eeprom == 0xffff) { 778 phymode = AXE_PHY_MODE_MARVELL; 779 gpio0 = 1; 780 ledmode = 0; 781 } else { 782 phymode = eeprom & 0x7f; 783 gpio0 = (eeprom & 0x80) ? 0 : 1; 784 ledmode = eeprom >> 8; 785 } 786 787 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 788 789 /* Program GPIOs depending on PHY hardware. */ 790 switch (phymode) { 791 case AXE_PHY_MODE_MARVELL: 792 if (gpio0 == 1) { 793 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 794 hz / 32); 795 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 796 hz / 32); 797 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 798 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 799 hz / 32); 800 } else { 801 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 802 AXE_GPIO1_EN, hz / 3); 803 if (ledmode == 1) { 804 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 805 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 806 hz / 3); 807 } else { 808 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 809 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 810 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 811 AXE_GPIO2_EN, hz / 4); 812 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 813 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 814 } 815 } 816 break; 817 case AXE_PHY_MODE_CICADA: 818 case AXE_PHY_MODE_CICADA_V2: 819 case AXE_PHY_MODE_CICADA_V2_ASIX: 820 if (gpio0 == 1) 821 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 822 AXE_GPIO0_EN, hz / 32); 823 else 824 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 825 AXE_GPIO1_EN, hz / 32); 826 break; 827 case AXE_PHY_MODE_AGERE: 828 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 829 AXE_GPIO1_EN, hz / 32); 830 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 831 AXE_GPIO2_EN, hz / 32); 832 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 833 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 834 AXE_GPIO2_EN, hz / 32); 835 break; 836 case AXE_PHY_MODE_REALTEK_8211CL: 837 case AXE_PHY_MODE_REALTEK_8211BN: 838 case AXE_PHY_MODE_REALTEK_8251CL: 839 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 840 AXE_GPIO1 | AXE_GPIO1_EN; 841 AXE_GPIO_WRITE(val, hz / 32); 842 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 843 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 844 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 845 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 846 axe_miibus_writereg_locked(sc->axe_dev, 847 sc->axe_phyno, 0x1F, 0x0005); 848 axe_miibus_writereg_locked(sc->axe_dev, 849 sc->axe_phyno, 0x0C, 0x0000); 850 axe_miibus_readreg_locked(sc->axe_dev, 851 sc->axe_phyno, 0x0001, &val); 852 axe_miibus_writereg_locked(sc->axe_dev, 853 sc->axe_phyno, 0x01, val | 0x0080); 854 axe_miibus_writereg_locked(sc->axe_dev, 855 sc->axe_phyno, 0x1F, 0x0000); 856 } 857 break; 858 default: 859 /* Unknown PHY model or no need to program GPIOs. */ 860 break; 861 } 862 863 /* soft reset */ 864 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 865 usbd_delay_ms(sc->axe_udev, 150); 866 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 867 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 868 usbd_delay_ms(sc->axe_udev, 150); 869 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 870 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 871 usbd_delay_ms(sc->axe_udev, 10); 872 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 873 } 874 875 static void 876 axe_ax88772_init(struct axe_softc *sc) 877 { 878 AXEHIST_FUNC(); AXEHIST_CALLED(); 879 880 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 881 usbd_delay_ms(sc->axe_udev, 40); 882 883 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 884 /* ask for the embedded PHY */ 885 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 886 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 887 usbd_delay_ms(sc->axe_udev, 10); 888 889 /* power down and reset state, pin reset state */ 890 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 891 usbd_delay_ms(sc->axe_udev, 60); 892 893 /* power down/reset state, pin operating state */ 894 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 895 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 896 usbd_delay_ms(sc->axe_udev, 150); 897 898 /* power up, reset */ 899 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 900 901 /* power up, operating */ 902 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 903 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 904 } else { 905 /* ask for external PHY */ 906 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 907 NULL); 908 usbd_delay_ms(sc->axe_udev, 10); 909 910 /* power down internal PHY */ 911 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 912 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 913 } 914 915 usbd_delay_ms(sc->axe_udev, 150); 916 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 917 } 918 919 static void 920 axe_ax88772_phywake(struct axe_softc *sc) 921 { 922 AXEHIST_FUNC(); AXEHIST_CALLED(); 923 924 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 925 /* Manually select internal(embedded) PHY - MAC mode. */ 926 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 927 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 928 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 929 } else { 930 /* 931 * Manually select external PHY - MAC mode. 932 * Reverse MII/RMII is for AX88772A PHY mode. 933 */ 934 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 935 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 936 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 937 } 938 939 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 940 AXE_SW_RESET_IPRL, NULL); 941 942 /* T1 = min 500ns everywhere */ 943 usbd_delay_ms(sc->axe_udev, 150); 944 945 /* Take PHY out of power down. */ 946 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 947 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 948 } else { 949 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 950 } 951 952 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 953 usbd_delay_ms(sc->axe_udev, 600); 954 955 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 956 957 /* T3 = 500ns everywhere */ 958 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 959 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 960 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 961 } 962 963 static void 964 axe_ax88772a_init(struct axe_softc *sc) 965 { 966 AXEHIST_FUNC(); AXEHIST_CALLED(); 967 968 /* Reload EEPROM. */ 969 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 970 axe_ax88772_phywake(sc); 971 /* Stop MAC. */ 972 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 973 } 974 975 static void 976 axe_ax88772b_init(struct axe_softc *sc) 977 { 978 AXEHIST_FUNC(); AXEHIST_CALLED(); 979 uint16_t eeprom; 980 int i; 981 982 /* Reload EEPROM. */ 983 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 984 985 /* 986 * Save PHY power saving configuration(high byte) and 987 * clear EEPROM checksum value(low byte). 988 */ 989 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 990 &eeprom)) { 991 aprint_error_dev(sc->axe_dev, "failed to read eeprom\n"); 992 return; 993 } 994 995 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 996 997 /* 998 * Auto-loaded default station address from internal ROM is 999 * 00:00:00:00:00:00 such that an explicit access to EEPROM 1000 * is required to get real station address. 1001 */ 1002 uint8_t *eaddr = sc->axe_enaddr; 1003 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 1004 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 1005 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 1006 aprint_error_dev(sc->axe_dev, 1007 "failed to read eeprom\n"); 1008 eeprom = 0; 1009 } 1010 eeprom = le16toh(eeprom); 1011 *eaddr++ = (uint8_t)(eeprom & 0xFF); 1012 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 1013 } 1014 /* Wakeup PHY. */ 1015 axe_ax88772_phywake(sc); 1016 /* Stop MAC. */ 1017 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 1018 } 1019 1020 #undef AXE_GPIO_WRITE 1021 1022 /* 1023 * Probe for a AX88172 chip. 1024 */ 1025 int 1026 axe_match(device_t parent, cfdata_t match, void *aux) 1027 { 1028 struct usb_attach_arg *uaa = aux; 1029 1030 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 1031 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 1032 } 1033 1034 /* 1035 * Attach the interface. Allocate softc structures, do ifmedia 1036 * setup and ethernet/BPF attach. 1037 */ 1038 void 1039 axe_attach(device_t parent, device_t self, void *aux) 1040 { 1041 AXEHIST_FUNC(); AXEHIST_CALLED(); 1042 struct axe_softc *sc = device_private(self); 1043 struct usb_attach_arg *uaa = aux; 1044 struct usbd_device *dev = uaa->uaa_device; 1045 usbd_status err; 1046 usb_interface_descriptor_t *id; 1047 usb_endpoint_descriptor_t *ed; 1048 struct mii_data *mii; 1049 char *devinfop; 1050 const char *devname = device_xname(self); 1051 struct ifnet *ifp; 1052 int i; 1053 1054 aprint_naive("\n"); 1055 aprint_normal("\n"); 1056 1057 sc->axe_dev = self; 1058 sc->axe_udev = dev; 1059 1060 devinfop = usbd_devinfo_alloc(dev, 0); 1061 aprint_normal_dev(self, "%s\n", devinfop); 1062 usbd_devinfo_free(devinfop); 1063 1064 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 1065 if (err) { 1066 aprint_error_dev(self, "failed to set configuration" 1067 ", err=%s\n", usbd_errstr(err)); 1068 return; 1069 } 1070 1071 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 1072 1073 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, USB_TASKQ_MPSAFE); 1074 1075 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 1076 if (err) { 1077 aprint_error_dev(self, "getting interface handle failed\n"); 1078 return; 1079 } 1080 1081 sc->axe_product = uaa->uaa_product; 1082 sc->axe_vendor = uaa->uaa_vendor; 1083 1084 id = usbd_get_interface_descriptor(sc->axe_iface); 1085 1086 /* decide on what our bufsize will be */ 1087 if (AXE_IS_178_FAMILY(sc)) 1088 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 1089 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 1090 else 1091 sc->axe_bufsz = AXE_172_BUFSZ; 1092 1093 sc->axe_ed[AXE_ENDPT_RX] = -1; 1094 sc->axe_ed[AXE_ENDPT_TX] = -1; 1095 sc->axe_ed[AXE_ENDPT_INTR] = -1; 1096 1097 /* Find endpoints. */ 1098 for (i = 0; i < id->bNumEndpoints; i++) { 1099 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 1100 if (ed == NULL) { 1101 aprint_error_dev(self, "couldn't get ep %d\n", i); 1102 return; 1103 } 1104 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 1105 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 1106 1107 if (dir == UE_DIR_IN && xt == UE_BULK && 1108 sc->axe_ed[AXE_ENDPT_RX] == -1) { 1109 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 1110 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 1111 sc->axe_ed[AXE_ENDPT_TX] == -1) { 1112 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 1113 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 1114 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 1115 } 1116 } 1117 1118 /* Set these up now for axe_cmd(). */ 1119 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 1120 mutex_init(&sc->axe_txlock, MUTEX_DEFAULT, IPL_SOFTUSB); 1121 mutex_init(&sc->axe_rxlock, MUTEX_DEFAULT, IPL_SOFTUSB); 1122 mutex_init(&sc->axe_lock, MUTEX_DEFAULT, IPL_NONE); 1123 cv_init(&sc->axe_detachcv, "axedet"); 1124 1125 /* We need the PHYID for init dance in some cases */ 1126 axe_lock_mii(sc); 1127 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 1128 aprint_error_dev(self, "failed to read phyaddrs\n"); 1129 1130 cv_destroy(&sc->axe_detachcv); 1131 mutex_destroy(&sc->axe_lock); 1132 mutex_destroy(&sc->axe_rxlock); 1133 mutex_destroy(&sc->axe_txlock); 1134 mutex_destroy(&sc->axe_mii_lock); 1135 1136 return; 1137 } 1138 1139 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 1140 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 1141 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 1142 if (sc->axe_phyno == -1) 1143 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 1144 if (sc->axe_phyno == -1) { 1145 DPRINTF(" no valid PHY address found, assuming PHY address 0", 1146 0, 0, 0, 0); 1147 sc->axe_phyno = 0; 1148 } 1149 1150 /* Initialize controller and get station address. */ 1151 1152 axe_ax_init(sc); 1153 1154 /* 1155 * Fetch IPG values. 1156 */ 1157 if (sc->axe_flags & (AX772A | AX772B)) { 1158 /* Set IPG values. */ 1159 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 1160 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 1161 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 1162 } else { 1163 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 1164 aprint_error_dev(self, "failed to read ipg\n"); 1165 1166 cv_destroy(&sc->axe_detachcv); 1167 mutex_destroy(&sc->axe_lock); 1168 mutex_destroy(&sc->axe_rxlock); 1169 mutex_destroy(&sc->axe_txlock); 1170 mutex_destroy(&sc->axe_mii_lock); 1171 1172 return; 1173 } 1174 } 1175 1176 axe_unlock_mii(sc); 1177 1178 /* 1179 * An ASIX chip was detected. Inform the world. 1180 */ 1181 aprint_normal_dev(self, "Ethernet address %s\n", 1182 ether_sprintf(sc->axe_enaddr)); 1183 1184 /* Initialize interface info.*/ 1185 ifp = &sc->sc_if; 1186 ifp->if_softc = sc; 1187 strlcpy(ifp->if_xname, devname, IFNAMSIZ); 1188 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1189 ifp->if_extflags = IFEF_MPSAFE; 1190 ifp->if_ioctl = axe_ioctl; 1191 ifp->if_start = axe_start; 1192 ifp->if_init = axe_init; 1193 ifp->if_stop = axe_stop; 1194 ifp->if_watchdog = axe_watchdog; 1195 1196 IFQ_SET_READY(&ifp->if_snd); 1197 1198 if (AXE_IS_178_FAMILY(sc)) 1199 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1200 if (sc->axe_flags & AX772B) { 1201 ifp->if_capabilities = 1202 IFCAP_CSUM_IPv4_Rx | 1203 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1204 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1205 /* 1206 * Checksum offloading of AX88772B also works with VLAN 1207 * tagged frames but there is no way to take advantage 1208 * of the feature because vlan(4) assumes 1209 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1210 * support checksum offloading with VLAN. VLAN hardware 1211 * tagging support of AX88772B is very limited so it's 1212 * not possible to announce IFCAP_VLAN_HWTAGGING. 1213 */ 1214 } 1215 u_int adv_pause; 1216 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1217 adv_pause = MIIF_DOPAUSE; 1218 else 1219 adv_pause = 0; 1220 adv_pause = 0; 1221 1222 /* Initialize MII/media info. */ 1223 mii = &sc->axe_mii; 1224 mii->mii_ifp = ifp; 1225 mii->mii_readreg = axe_miibus_readreg; 1226 mii->mii_writereg = axe_miibus_writereg; 1227 mii->mii_statchg = axe_miibus_statchg; 1228 mii->mii_flags = MIIF_AUTOTSLEEP; 1229 1230 sc->axe_ec.ec_mii = mii; 1231 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1232 1233 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1234 adv_pause); 1235 1236 if (LIST_EMPTY(&mii->mii_phys)) { 1237 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1238 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1239 } else 1240 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1241 1242 /* Attach the interface. */ 1243 if_attach(ifp); 1244 ether_ifattach(ifp, sc->axe_enaddr); 1245 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1246 RND_TYPE_NET, RND_FLAG_DEFAULT); 1247 1248 callout_init(&sc->axe_stat_ch, CALLOUT_MPSAFE); 1249 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1250 1251 sc->axe_attached = true; 1252 1253 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1254 1255 if (!pmf_device_register(self, NULL, NULL)) 1256 aprint_error_dev(self, "couldn't establish power handler\n"); 1257 } 1258 1259 int 1260 axe_detach(device_t self, int flags) 1261 { 1262 AXEHIST_FUNC(); AXEHIST_CALLED(); 1263 struct axe_softc *sc = device_private(self); 1264 struct ifnet *ifp = &sc->sc_if; 1265 1266 mutex_enter(&sc->axe_lock); 1267 sc->axe_dying = true; 1268 mutex_exit(&sc->axe_lock); 1269 1270 /* Detached before attached finished, so just bail out. */ 1271 if (!sc->axe_attached) 1272 return 0; 1273 1274 pmf_device_deregister(self); 1275 1276 callout_halt(&sc->axe_stat_ch, NULL); 1277 usb_rem_task_wait(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER, 1278 NULL); 1279 1280 if (ifp->if_flags & IFF_RUNNING) { 1281 IFNET_LOCK(ifp); 1282 axe_stop(ifp, 1); 1283 IFNET_UNLOCK(ifp); 1284 } 1285 1286 mutex_enter(&sc->axe_lock); 1287 sc->axe_refcnt--; 1288 while (sc->axe_refcnt > 0) { 1289 /* Wait for processes to go away */ 1290 cv_wait(&sc->axe_detachcv, &sc->axe_lock); 1291 } 1292 1293 #ifdef DIAGNOSTIC 1294 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1295 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1296 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1297 aprint_debug_dev(self, "detach has active endpoints\n"); 1298 #endif 1299 1300 mutex_exit(&sc->axe_lock); 1301 1302 callout_destroy(&sc->axe_stat_ch); 1303 rnd_detach_source(&sc->rnd_source); 1304 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1305 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1306 ether_ifdetach(ifp); 1307 if_detach(ifp); 1308 1309 sc->axe_attached = false; 1310 1311 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1312 1313 cv_destroy(&sc->axe_detachcv); 1314 mutex_destroy(&sc->axe_lock); 1315 mutex_destroy(&sc->axe_rxlock); 1316 mutex_destroy(&sc->axe_txlock); 1317 mutex_destroy(&sc->axe_mii_lock); 1318 1319 return 0; 1320 } 1321 1322 int 1323 axe_activate(device_t self, devact_t act) 1324 { 1325 AXEHIST_FUNC(); AXEHIST_CALLED(); 1326 struct axe_softc *sc = device_private(self); 1327 1328 switch (act) { 1329 case DVACT_DEACTIVATE: 1330 if_deactivate(&sc->axe_ec.ec_if); 1331 1332 mutex_enter(&sc->axe_lock); 1333 sc->axe_dying = true; 1334 mutex_exit(&sc->axe_lock); 1335 1336 mutex_enter(&sc->axe_rxlock); 1337 mutex_enter(&sc->axe_txlock); 1338 sc->axe_stopping = true; 1339 mutex_exit(&sc->axe_txlock); 1340 mutex_exit(&sc->axe_rxlock); 1341 1342 return 0; 1343 default: 1344 return EOPNOTSUPP; 1345 } 1346 } 1347 1348 static int 1349 axe_rx_list_init(struct axe_softc *sc) 1350 { 1351 AXEHIST_FUNC(); AXEHIST_CALLED(); 1352 1353 struct axe_cdata *cd; 1354 struct axe_chain *c; 1355 int i; 1356 1357 cd = &sc->axe_cdata; 1358 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1359 c = &cd->axe_rx_chain[i]; 1360 c->axe_sc = sc; 1361 if (c->axe_xfer == NULL) { 1362 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1363 sc->axe_bufsz, 0, 0, &c->axe_xfer); 1364 if (err) 1365 return err; 1366 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1367 } 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int 1374 axe_tx_list_init(struct axe_softc *sc) 1375 { 1376 AXEHIST_FUNC(); AXEHIST_CALLED(); 1377 struct axe_cdata *cd; 1378 struct axe_chain *c; 1379 int i; 1380 1381 cd = &sc->axe_cdata; 1382 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1383 c = &cd->axe_tx_chain[i]; 1384 c->axe_sc = sc; 1385 if (c->axe_xfer == NULL) { 1386 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1387 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1388 &c->axe_xfer); 1389 if (err) 1390 return err; 1391 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1392 } 1393 } 1394 1395 cd->axe_tx_cnt = 0; 1396 1397 return 0; 1398 } 1399 1400 /* 1401 * A frame has been uploaded: pass the resulting mbuf chain up to 1402 * the higher level protocols. 1403 */ 1404 static void 1405 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1406 { 1407 AXEHIST_FUNC(); AXEHIST_CALLED(); 1408 struct axe_chain *c = (struct axe_chain *)priv; 1409 struct axe_softc * const sc = c->axe_sc; 1410 struct ifnet *ifp = &sc->sc_if; 1411 uint8_t *buf = c->axe_buf; 1412 uint32_t total_len; 1413 struct mbuf *m; 1414 1415 mutex_enter(&sc->axe_rxlock); 1416 1417 if (sc->axe_dying || sc->axe_stopping || 1418 status == USBD_INVAL || status == USBD_NOT_STARTED || 1419 status == USBD_CANCELLED || !(ifp->if_flags & IFF_RUNNING)) { 1420 mutex_exit(&sc->axe_rxlock); 1421 return; 1422 } 1423 1424 if (status != USBD_NORMAL_COMPLETION) { 1425 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1426 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1427 usbd_errstr(status)); 1428 } 1429 if (status == USBD_STALLED) 1430 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1431 goto done; 1432 } 1433 1434 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1435 1436 do { 1437 u_int pktlen = 0; 1438 u_int rxlen = 0; 1439 int flags = 0; 1440 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1441 struct axe_sframe_hdr hdr; 1442 1443 if (total_len < sizeof(hdr)) { 1444 ifp->if_ierrors++; 1445 goto done; 1446 } 1447 1448 #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1) 1449 /* 1450 * XXX hdr is 2-byte aligned in buf, not 4-byte. 1451 * For some architectures, __builtin_memcpy() of 1452 * GCC 6 attempts to copy sizeof(hdr) = 4 bytes 1453 * at onece, which results in alignment error. 1454 */ 1455 hdr.len = *(uint16_t *)buf; 1456 hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t)); 1457 #else 1458 memcpy(&hdr, buf, sizeof(hdr)); 1459 #endif 1460 1461 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1462 total_len, 1463 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1464 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1465 1466 total_len -= sizeof(hdr); 1467 buf += sizeof(hdr); 1468 1469 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1470 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1471 AXE_RH1M_RXLEN_MASK) { 1472 ifp->if_ierrors++; 1473 goto done; 1474 } 1475 1476 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1477 if (total_len < rxlen) { 1478 pktlen = total_len; 1479 total_len = 0; 1480 } else { 1481 pktlen = rxlen; 1482 rxlen = roundup2(rxlen, 2); 1483 total_len -= rxlen; 1484 } 1485 1486 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1487 struct axe_csum_hdr csum_hdr; 1488 1489 if (total_len < sizeof(csum_hdr)) { 1490 ifp->if_ierrors++; 1491 goto done; 1492 } 1493 1494 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1495 1496 csum_hdr.len = le16toh(csum_hdr.len); 1497 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1498 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1499 1500 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1501 " cstatus %#jx", total_len, 1502 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1503 1504 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1505 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1506 sc->sc_lenmask) { 1507 /* we lost sync */ 1508 ifp->if_ierrors++; 1509 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1510 "err", 1511 AXE_CSUM_RXBYTES(csum_hdr.len), 1512 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1513 sc->sc_lenmask, 0); 1514 goto done; 1515 } 1516 /* 1517 * Get total transferred frame length including 1518 * checksum header. The length should be multiple 1519 * of 4. 1520 */ 1521 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1522 u_int len = sizeof(csum_hdr) + pktlen; 1523 len = (len + 3) & ~3; 1524 if (total_len < len) { 1525 DPRINTFN(20, "total_len %#jx < len %#jx", 1526 total_len, len, 0, 0); 1527 /* invalid length */ 1528 ifp->if_ierrors++; 1529 goto done; 1530 } 1531 buf += sizeof(csum_hdr); 1532 1533 const uint16_t cstatus = csum_hdr.cstatus; 1534 1535 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1536 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1537 flags |= M_CSUM_TCP_UDP_BAD; 1538 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1539 flags |= M_CSUM_IPv4_BAD; 1540 1541 const uint16_t l4type = 1542 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1543 1544 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1545 flags |= M_CSUM_TCPv4; 1546 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1547 flags |= M_CSUM_UDPv4; 1548 } 1549 if (total_len < len) { 1550 pktlen = total_len; 1551 total_len = 0; 1552 } else { 1553 total_len -= len; 1554 rxlen = len - sizeof(csum_hdr); 1555 } 1556 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1557 " rxlen %#jx", total_len, len, pktlen, rxlen); 1558 } else { /* AX172 */ 1559 pktlen = rxlen = total_len; 1560 total_len = 0; 1561 } 1562 1563 MGETHDR(m, M_DONTWAIT, MT_DATA); 1564 if (m == NULL) { 1565 ifp->if_ierrors++; 1566 goto done; 1567 } 1568 1569 if (pktlen > MHLEN - ETHER_ALIGN) { 1570 MCLGET(m, M_DONTWAIT); 1571 if ((m->m_flags & M_EXT) == 0) { 1572 m_freem(m); 1573 ifp->if_ierrors++; 1574 goto done; 1575 } 1576 } 1577 m->m_data += ETHER_ALIGN; 1578 1579 m_set_rcvif(m, ifp); 1580 m->m_pkthdr.len = m->m_len = pktlen; 1581 m->m_pkthdr.csum_flags = flags; 1582 1583 memcpy(mtod(m, uint8_t *), buf, pktlen); 1584 buf += rxlen; 1585 1586 DPRINTFN(10, "deliver %jd (%#jx)", m->m_len, m->m_len, 0, 0); 1587 1588 mutex_exit(&sc->axe_rxlock); 1589 1590 if_percpuq_enqueue((ifp)->if_percpuq, (m)); 1591 1592 mutex_enter(&sc->axe_rxlock); 1593 if (sc->axe_dying || sc->axe_stopping) { 1594 mutex_exit(&sc->axe_rxlock); 1595 return; 1596 } 1597 1598 } while (total_len > 0); 1599 1600 done: 1601 1602 if (sc->axe_dying || sc->axe_stopping) { 1603 mutex_exit(&sc->axe_rxlock); 1604 return; 1605 } 1606 1607 mutex_exit(&sc->axe_rxlock); 1608 1609 /* Setup new transfer. */ 1610 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1611 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1612 usbd_transfer(xfer); 1613 1614 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1615 } 1616 1617 /* 1618 * A frame was downloaded to the chip. It's safe for us to clean up 1619 * the list buffers. 1620 */ 1621 1622 static void 1623 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1624 { 1625 AXEHIST_FUNC(); AXEHIST_CALLED(); 1626 struct axe_chain *c = priv; 1627 struct axe_softc *sc = c->axe_sc; 1628 struct axe_cdata *cd = &sc->axe_cdata; 1629 struct ifnet *ifp = &sc->sc_if; 1630 1631 mutex_enter(&sc->axe_txlock); 1632 if (sc->axe_stopping || sc->axe_dying) { 1633 mutex_exit(&sc->axe_txlock); 1634 return; 1635 } 1636 1637 KASSERT(cd->axe_tx_cnt == 1); 1638 cd->axe_tx_cnt--; 1639 1640 sc->axe_timer = 0; 1641 1642 switch (status) { 1643 case USBD_NOT_STARTED: 1644 case USBD_CANCELLED: 1645 break; 1646 1647 case USBD_NORMAL_COMPLETION: 1648 ifp->if_opackets++; 1649 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1650 axe_start_locked(ifp); 1651 break; 1652 1653 default: 1654 1655 ifp->if_oerrors++; 1656 if (usbd_ratecheck(&sc->axe_tx_notice)) 1657 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1658 usbd_errstr(status)); 1659 if (status == USBD_STALLED) 1660 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1661 break; 1662 } 1663 1664 mutex_exit(&sc->axe_txlock); 1665 } 1666 1667 static void 1668 axe_tick(void *xsc) 1669 { 1670 AXEHIST_FUNC(); AXEHIST_CALLED(); 1671 struct axe_softc *sc = xsc; 1672 1673 if (sc == NULL) 1674 return; 1675 1676 mutex_enter(&sc->axe_lock); 1677 if (!sc->axe_stopping && !sc->axe_dying) { 1678 /* Perform periodic stuff in process context */ 1679 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1680 } 1681 mutex_exit(&sc->axe_lock); 1682 1683 } 1684 1685 static void 1686 axe_tick_task(void *xsc) 1687 { 1688 AXEHIST_FUNC(); AXEHIST_CALLED(); 1689 struct axe_softc *sc = xsc; 1690 struct ifnet *ifp; 1691 struct mii_data *mii; 1692 1693 if (sc == NULL) 1694 return; 1695 1696 mutex_enter(&sc->axe_lock); 1697 if (sc->axe_stopping || sc->axe_dying) { 1698 mutex_exit(&sc->axe_lock); 1699 return; 1700 } 1701 1702 ifp = &sc->sc_if; 1703 mii = &sc->axe_mii; 1704 1705 if (mii == NULL) { 1706 mutex_exit(&sc->axe_lock); 1707 return; 1708 } 1709 1710 sc->axe_refcnt++; 1711 mutex_exit(&sc->axe_lock); 1712 1713 if (sc->axe_timer != 0 && --sc->axe_timer == 0) 1714 axe_watchdog(ifp); 1715 1716 mii_tick(mii); 1717 1718 if (sc->axe_link == 0 && 1719 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1720 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1721 DPRINTF("got link", 0, 0, 0, 0); 1722 sc->axe_link++; 1723 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1724 axe_start(ifp); 1725 } 1726 1727 1728 mutex_enter(&sc->axe_lock); 1729 if (--sc->axe_refcnt < 0) 1730 cv_broadcast(&sc->axe_detachcv); 1731 if (!sc->axe_stopping && !sc->axe_dying) 1732 callout_schedule(&sc->axe_stat_ch, hz); 1733 mutex_exit(&sc->axe_lock); 1734 } 1735 1736 static int 1737 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1738 { 1739 struct ifnet *ifp = &sc->sc_if; 1740 struct axe_chain *c; 1741 usbd_status err; 1742 int length, boundary; 1743 1744 KASSERT(mutex_owned(&sc->axe_txlock)); 1745 1746 c = &sc->axe_cdata.axe_tx_chain[idx]; 1747 1748 /* 1749 * Copy the mbuf data into a contiguous buffer, leaving two 1750 * bytes at the beginning to hold the frame length. 1751 */ 1752 if (AXE_IS_178_FAMILY(sc)) { 1753 struct axe_sframe_hdr hdr; 1754 1755 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1756 1757 hdr.len = htole16(m->m_pkthdr.len); 1758 hdr.ilen = ~hdr.len; 1759 1760 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1761 length = sizeof(hdr); 1762 1763 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1764 length += m->m_pkthdr.len; 1765 1766 if ((length % boundary) == 0) { 1767 hdr.len = 0x0000; 1768 hdr.ilen = 0xffff; 1769 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1770 length += sizeof(hdr); 1771 } 1772 } else { 1773 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1774 length = m->m_pkthdr.len; 1775 } 1776 1777 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1778 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1779 1780 /* Transmit */ 1781 err = usbd_transfer(c->axe_xfer); 1782 if (err != USBD_IN_PROGRESS) { 1783 /* XXXSMP IFNET_LOCK */ 1784 axe_stop(ifp, 0); 1785 return EIO; 1786 } 1787 1788 sc->axe_cdata.axe_tx_cnt++; 1789 1790 return 0; 1791 } 1792 1793 1794 static void 1795 axe_csum_cfg(struct axe_softc *sc) 1796 { 1797 struct ifnet *ifp = &sc->sc_if; 1798 uint16_t csum1, csum2; 1799 1800 if ((sc->axe_flags & AX772B) != 0) { 1801 csum1 = 0; 1802 csum2 = 0; 1803 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1804 csum1 |= AXE_TXCSUM_IP; 1805 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1806 csum1 |= AXE_TXCSUM_TCP; 1807 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1808 csum1 |= AXE_TXCSUM_UDP; 1809 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1810 csum1 |= AXE_TXCSUM_TCPV6; 1811 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1812 csum1 |= AXE_TXCSUM_UDPV6; 1813 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1814 csum1 = 0; 1815 csum2 = 0; 1816 1817 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1818 csum1 |= AXE_RXCSUM_IP; 1819 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1820 csum1 |= AXE_RXCSUM_TCP; 1821 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1822 csum1 |= AXE_RXCSUM_UDP; 1823 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1824 csum1 |= AXE_RXCSUM_TCPV6; 1825 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1826 csum1 |= AXE_RXCSUM_UDPV6; 1827 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1828 } 1829 } 1830 1831 static void 1832 axe_start_locked(struct ifnet *ifp) 1833 { 1834 struct axe_softc *sc = ifp->if_softc; 1835 struct mbuf *m; 1836 struct axe_cdata *cd = &sc->axe_cdata; 1837 1838 KASSERT(mutex_owned(&sc->axe_txlock)); 1839 1840 if (cd->axe_tx_cnt != 0) 1841 return; 1842 1843 if (sc->axe_link == 0 || (ifp->if_flags & IFF_RUNNING) == 0) 1844 return; 1845 1846 IFQ_POLL(&ifp->if_snd, m); 1847 if (m == NULL) { 1848 return; 1849 } 1850 1851 if (axe_encap(sc, m, 0)) { 1852 return; 1853 } 1854 IFQ_DEQUEUE(&ifp->if_snd, m); 1855 1856 /* 1857 * If there's a BPF listener, bounce a copy of this frame 1858 * to him. 1859 */ 1860 bpf_mtap(ifp, m, BPF_D_OUT); 1861 m_freem(m); 1862 1863 /* 1864 * Set a timeout in case the chip goes out to lunch. 1865 */ 1866 sc->axe_timer = 5; 1867 1868 return; 1869 } 1870 1871 static void 1872 axe_start(struct ifnet *ifp) 1873 { 1874 struct axe_softc * const sc = ifp->if_softc; 1875 1876 mutex_enter(&sc->axe_txlock); 1877 if (!sc->axe_stopping) 1878 axe_start_locked(ifp); 1879 mutex_exit(&sc->axe_txlock); 1880 } 1881 1882 static int 1883 axe_init_locked(struct ifnet *ifp) 1884 { 1885 AXEHIST_FUNC(); AXEHIST_CALLED(); 1886 struct axe_softc *sc = ifp->if_softc; 1887 struct axe_chain *c; 1888 usbd_status err; 1889 int rxmode; 1890 int i; 1891 1892 KASSERT(mutex_owned(&sc->axe_lock)); 1893 1894 if (sc->axe_dying) 1895 return EIO; 1896 1897 /* Cancel pending I/O */ 1898 axe_stop_locked(ifp, 0); 1899 1900 /* Reset the ethernet interface. */ 1901 axe_reset(sc); 1902 1903 axe_lock_mii_sc_locked(sc); 1904 1905 #if 0 1906 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1907 AX_GPIO_GPO2EN, 5, in_pm); 1908 #endif 1909 /* Set MAC address and transmitter IPG values. */ 1910 if (AXE_IS_178_FAMILY(sc)) { 1911 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1912 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1913 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1914 } else { 1915 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1916 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1917 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1918 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1919 } 1920 if (AXE_IS_178_FAMILY(sc)) { 1921 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1922 if ((sc->axe_flags & AX772B) != 0 && 1923 (ifp->if_capenable & AX_RXCSUM) != 0) { 1924 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1925 sc->axe_flags |= AXCSUM_FRAME; 1926 } else { 1927 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1928 sc->axe_flags |= AXSTD_FRAME; 1929 } 1930 } 1931 1932 /* Configure TX/RX checksum offloading. */ 1933 axe_csum_cfg(sc); 1934 1935 if (sc->axe_flags & AX772B) { 1936 /* AX88772B uses different maximum frame burst configuration. */ 1937 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1938 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1939 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1940 } 1941 /* Enable receiver, set RX mode */ 1942 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1943 if (AXE_IS_178_FAMILY(sc)) { 1944 if (sc->axe_flags & AX772B) { 1945 /* 1946 * Select RX header format type 1. Aligning IP 1947 * header on 4 byte boundary is not needed when 1948 * checksum offloading feature is not used 1949 * because we always copy the received frame in 1950 * RX handler. When RX checksum offloading is 1951 * active, aligning IP header is required to 1952 * reflect actual frame length including RX 1953 * header size. 1954 */ 1955 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1956 if (sc->axe_flags & AXCSUM_FRAME) 1957 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1958 } else { 1959 /* 1960 * Default Rx buffer size is too small to get 1961 * maximum performance. 1962 */ 1963 #if 0 1964 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1965 /* Largest possible USB buffer size for AX88178 */ 1966 } 1967 #endif 1968 rxmode |= AXE_178_RXCMD_MFB_16384; 1969 } 1970 } else { 1971 rxmode |= AXE_172_RXCMD_UNICAST; 1972 } 1973 1974 1975 /* If we want promiscuous mode, set the allframes bit. */ 1976 if (ifp->if_flags & IFF_PROMISC) 1977 rxmode |= AXE_RXCMD_PROMISC; 1978 1979 if (ifp->if_flags & IFF_BROADCAST) 1980 rxmode |= AXE_RXCMD_BROADCAST; 1981 1982 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1983 1984 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1985 1986 /* Load the multicast filter. */ 1987 axe_setmulti_locked(sc); 1988 1989 axe_unlock_mii_sc_locked(sc); 1990 1991 /* Open RX and TX pipes. */ 1992 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1993 USBD_EXCLUSIVE_USE | USBD_MPSAFE, &sc->axe_ep[AXE_ENDPT_RX]); 1994 if (err) { 1995 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1996 usbd_errstr(err)); 1997 return EIO; 1998 } 1999 2000 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 2001 USBD_EXCLUSIVE_USE | USBD_MPSAFE, &sc->axe_ep[AXE_ENDPT_TX]); 2002 if (err) { 2003 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 2004 usbd_errstr(err)); 2005 return EIO; 2006 } 2007 2008 /* Init RX ring. */ 2009 if (axe_rx_list_init(sc) != 0) { 2010 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 2011 return ENOBUFS; 2012 } 2013 2014 /* Init TX ring. */ 2015 if (axe_tx_list_init(sc) != 0) { 2016 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 2017 return ENOBUFS; 2018 } 2019 2020 mutex_enter(&sc->axe_rxlock); 2021 mutex_enter(&sc->axe_txlock); 2022 sc->axe_stopping = false; 2023 2024 /* Start up the receive pipe. */ 2025 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 2026 c = &sc->axe_cdata.axe_rx_chain[i]; 2027 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 2028 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 2029 usbd_transfer(c->axe_xfer); 2030 } 2031 2032 mutex_exit(&sc->axe_txlock); 2033 mutex_exit(&sc->axe_rxlock); 2034 2035 /* Indicate we are up and running. */ 2036 KASSERT(IFNET_LOCKED(ifp)); 2037 ifp->if_flags |= IFF_RUNNING; 2038 2039 callout_schedule(&sc->axe_stat_ch, hz); 2040 return 0; 2041 } 2042 2043 static int 2044 axe_init(struct ifnet *ifp) 2045 { 2046 struct axe_softc * const sc = ifp->if_softc; 2047 2048 mutex_enter(&sc->axe_lock); 2049 int ret = axe_init_locked(ifp); 2050 mutex_exit(&sc->axe_lock); 2051 2052 return ret; 2053 } 2054 2055 static int 2056 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2057 { 2058 struct axe_softc *sc = ifp->if_softc; 2059 int error = 0; 2060 2061 switch (cmd) { 2062 case SIOCSIFFLAGS: 2063 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2064 break; 2065 2066 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2067 case IFF_RUNNING: 2068 axe_stop(ifp, 1); 2069 break; 2070 case IFF_UP: 2071 axe_init(ifp); 2072 break; 2073 case IFF_UP | IFF_RUNNING: 2074 if ((ifp->if_flags ^ sc->axe_if_flags) == IFF_PROMISC) 2075 axe_setmulti(sc); 2076 else 2077 axe_init(ifp); 2078 break; 2079 } 2080 mutex_enter(&sc->axe_rxlock); 2081 mutex_enter(&sc->axe_txlock); 2082 sc->axe_if_flags = ifp->if_flags; 2083 mutex_exit(&sc->axe_txlock); 2084 mutex_exit(&sc->axe_rxlock); 2085 break; 2086 2087 default: 2088 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2089 break; 2090 2091 error = 0; 2092 2093 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) 2094 axe_setmulti(sc); 2095 2096 } 2097 2098 return error; 2099 } 2100 2101 static void 2102 axe_watchdog(struct ifnet *ifp) 2103 { 2104 struct axe_softc * const sc = ifp->if_softc; 2105 struct axe_chain *c; 2106 usbd_status stat; 2107 2108 ifp->if_oerrors++; 2109 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 2110 2111 c = &sc->axe_cdata.axe_tx_chain[0]; 2112 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 2113 axe_txeof(c->axe_xfer, c, stat); 2114 2115 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2116 axe_start(ifp); 2117 } 2118 2119 /* 2120 * Stop the adapter and free any mbufs allocated to the 2121 * RX and TX lists. 2122 */ 2123 static void 2124 axe_stop_locked(struct ifnet *ifp, int disable) 2125 { 2126 struct axe_softc * const sc = ifp->if_softc; 2127 usbd_status err; 2128 int i; 2129 2130 KASSERT(mutex_owned(&sc->axe_lock)); 2131 2132 mutex_enter(&sc->axe_rxlock); 2133 mutex_enter(&sc->axe_txlock); 2134 sc->axe_stopping = true; 2135 mutex_exit(&sc->axe_txlock); 2136 mutex_exit(&sc->axe_rxlock); 2137 2138 /* 2139 * XXXSMP Would like to 2140 * KASSERT(IFNET_LOCKED(ifp)) 2141 * here but the locking order is: 2142 * ifnet -> sc lock -> rxlock -> txlock 2143 * and sc lock is already held. 2144 */ 2145 ifp->if_flags &= ~IFF_RUNNING; 2146 sc->axe_timer = 0; 2147 2148 callout_stop(&sc->axe_stat_ch); 2149 sc->axe_link = 0; 2150 2151 /* Stop transfers. */ 2152 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 2153 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 2154 if (err) { 2155 aprint_error_dev(sc->axe_dev, 2156 "abort rx pipe failed: %s\n", usbd_errstr(err)); 2157 } 2158 } 2159 2160 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 2161 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 2162 if (err) { 2163 aprint_error_dev(sc->axe_dev, 2164 "abort tx pipe failed: %s\n", usbd_errstr(err)); 2165 } 2166 } 2167 2168 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 2169 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 2170 if (err) { 2171 aprint_error_dev(sc->axe_dev, 2172 "abort intr pipe failed: %s\n", usbd_errstr(err)); 2173 } 2174 } 2175 2176 axe_reset(sc); 2177 2178 /* Free RX resources. */ 2179 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 2180 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 2181 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 2182 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 2183 } 2184 } 2185 2186 /* Free TX resources. */ 2187 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 2188 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 2189 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 2190 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 2191 } 2192 } 2193 2194 /* Close pipes. */ 2195 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 2196 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 2197 if (err) { 2198 aprint_error_dev(sc->axe_dev, 2199 "close rx pipe failed: %s\n", usbd_errstr(err)); 2200 } 2201 sc->axe_ep[AXE_ENDPT_RX] = NULL; 2202 } 2203 2204 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 2205 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 2206 if (err) { 2207 aprint_error_dev(sc->axe_dev, 2208 "close tx pipe failed: %s\n", usbd_errstr(err)); 2209 } 2210 sc->axe_ep[AXE_ENDPT_TX] = NULL; 2211 } 2212 2213 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 2214 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 2215 if (err) { 2216 aprint_error_dev(sc->axe_dev, 2217 "close intr pipe failed: %s\n", usbd_errstr(err)); 2218 } 2219 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 2220 } 2221 } 2222 2223 static void 2224 axe_stop(struct ifnet *ifp, int disable) 2225 { 2226 struct axe_softc * const sc = ifp->if_softc; 2227 2228 mutex_enter(&sc->axe_lock); 2229 axe_stop_locked(ifp, disable); 2230 mutex_exit(&sc->axe_lock); 2231 } 2232 2233 MODULE(MODULE_CLASS_DRIVER, if_axe, NULL); 2234 2235 #ifdef _MODULE 2236 #include "ioconf.c" 2237 #endif 2238 2239 static int 2240 if_axe_modcmd(modcmd_t cmd, void *aux) 2241 { 2242 int error = 0; 2243 2244 switch (cmd) { 2245 case MODULE_CMD_INIT: 2246 #ifdef _MODULE 2247 error = config_init_component(cfdriver_ioconf_axe, 2248 cfattach_ioconf_axe, cfdata_ioconf_axe); 2249 #endif 2250 return error; 2251 case MODULE_CMD_FINI: 2252 #ifdef _MODULE 2253 error = config_fini_component(cfdriver_ioconf_axe, 2254 cfattach_ioconf_axe, cfdata_ioconf_axe); 2255 #endif 2256 return error; 2257 default: 2258 return ENOTTY; 2259 } 2260 } 2261
Indexes created Wed Oct 01 18:09:54 GMT 2025