if_axe.c revision 1.102
1 /* $NetBSD: if_axe.c,v 1.102 2019/07/21 10:27:56 mrg Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.102 2019/07/21 10:27:56 mrg Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #include "opt_net_mpsafe.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/kernel.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/socket.h> 106 #include <sys/sockio.h> 107 #include <sys/systm.h> 108 109 #include <sys/rndsource.h> 110 111 #include <net/if.h> 112 #include <net/if_dl.h> 113 #include <net/if_ether.h> 114 #include <net/if_media.h> 115 116 #include <net/bpf.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/usb/usb.h> 122 #include <dev/usb/usbhist.h> 123 #include <dev/usb/usbdi.h> 124 #include <dev/usb/usbdi_util.h> 125 #include <dev/usb/usbdivar.h> 126 #include <dev/usb/usbdevs.h> 127 128 #include <dev/usb/if_axereg.h> 129 130 struct axe_type { 131 struct usb_devno axe_dev; 132 uint16_t axe_flags; 133 }; 134 135 struct axe_softc; 136 137 struct axe_chain { 138 struct axe_softc *axe_sc; 139 struct usbd_xfer *axe_xfer; 140 uint8_t *axe_buf; 141 }; 142 143 struct axe_cdata { 144 struct axe_chain axe_tx_chain[AXE_TX_LIST_CNT]; 145 struct axe_chain axe_rx_chain[AXE_RX_LIST_CNT]; 146 int axe_tx_prod; 147 int axe_tx_cnt; 148 }; 149 150 struct axe_softc { 151 device_t axe_dev; 152 struct ethercom axe_ec; 153 struct mii_data axe_mii; 154 krndsource_t rnd_source; 155 struct usbd_device * axe_udev; 156 struct usbd_interface * axe_iface; 157 158 uint16_t axe_vendor; 159 uint16_t axe_product; 160 uint16_t axe_timer; 161 uint32_t axe_flags; /* copied from axe_type */ 162 #define AX178 __BIT(0) /* AX88178 */ 163 #define AX772 __BIT(1) /* AX88772 */ 164 #define AX772A __BIT(2) /* AX88772A */ 165 #define AX772B __BIT(3) /* AX88772B */ 166 #define AXSTD_FRAME __BIT(12) 167 #define AXCSUM_FRAME __BIT(13) 168 169 int axe_ed[AXE_ENDPT_MAX]; 170 struct usbd_pipe * axe_ep[AXE_ENDPT_MAX]; 171 int axe_if_flags; 172 int axe_phyno; 173 struct axe_cdata axe_cdata; 174 struct callout axe_stat_ch; 175 176 uint8_t axe_enaddr[ETHER_ADDR_LEN]; 177 178 int axe_refcnt; 179 bool axe_dying; 180 bool axe_stopping; 181 bool axe_attached; 182 183 struct usb_task axe_tick_task; 184 185 kmutex_t axe_lock; 186 kmutex_t axe_mii_lock; 187 kmutex_t axe_rxlock; 188 kmutex_t axe_txlock; 189 kcondvar_t axe_detachcv; 190 191 int axe_link; 192 193 uint8_t axe_ipgs[3]; 194 uint8_t axe_phyaddrs[2]; 195 uint16_t sc_pwrcfg; 196 uint16_t sc_lenmask; 197 198 struct timeval axe_rx_notice; 199 struct timeval axe_tx_notice; 200 int axe_bufsz; 201 202 #define sc_if axe_ec.ec_if 203 }; 204 205 #define AXE_IS_178_FAMILY(sc) \ 206 ((sc)->axe_flags & (AX772 | AX772A | AX772B | AX178)) 207 208 #define AXE_IS_772(sc) \ 209 ((sc)->axe_flags & (AX772 | AX772A | AX772B)) 210 211 #define AX_RXCSUM \ 212 (IFCAP_CSUM_IPv4_Rx | \ 213 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 214 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 215 216 #define AX_TXCSUM \ 217 (IFCAP_CSUM_IPv4_Tx | \ 218 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 219 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 220 221 /* 222 * AXE_178_MAX_FRAME_BURST 223 * max frame burst size for Ax88178 and Ax88772 224 * 0 2048 bytes 225 * 1 4096 bytes 226 * 2 8192 bytes 227 * 3 16384 bytes 228 * use the largest your system can handle without USB stalling. 229 * 230 * NB: 88772 parts appear to generate lots of input errors with 231 * a 2K rx buffer and 8K is only slightly faster than 4K on an 232 * EHCI port on a T42 so change at your own risk. 233 */ 234 #define AXE_178_MAX_FRAME_BURST 1 235 236 237 #ifdef USB_DEBUG 238 #ifndef AXE_DEBUG 239 #define axedebug 0 240 #else 241 static int axedebug = 20; 242 243 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 244 { 245 int err; 246 const struct sysctlnode *rnode; 247 const struct sysctlnode *cnode; 248 249 err = sysctl_createv(clog, 0, NULL, &rnode, 250 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 251 SYSCTL_DESCR("axe global controls"), 252 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 253 254 if (err) 255 goto fail; 256 257 /* control debugging printfs */ 258 err = sysctl_createv(clog, 0, &rnode, &cnode, 259 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 260 "debug", SYSCTL_DESCR("Enable debugging output"), 261 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 262 if (err) 263 goto fail; 264 265 return; 266 fail: 267 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 268 } 269 270 #endif /* AXE_DEBUG */ 271 #endif /* USB_DEBUG */ 272 273 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 274 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 275 #define AXEHIST_FUNC() USBHIST_FUNC() 276 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 277 278 /* 279 * Various supported device vendors/products. 280 */ 281 static const struct axe_type axe_devs[] = { 282 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 283 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 284 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 285 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 286 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 287 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 288 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 289 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 290 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 291 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 292 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 293 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 294 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 295 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 296 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 297 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 298 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 299 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 300 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 301 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 302 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 303 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 304 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 305 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 306 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 307 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 308 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 309 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 310 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 311 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 312 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 313 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 314 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 315 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 316 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 317 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 318 }; 319 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 320 321 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 322 { 0x8000, 0x8001, 2048 }, 323 { 0x8100, 0x8147, 4096 }, 324 { 0x8200, 0x81EB, 6144 }, 325 { 0x8300, 0x83D7, 8192 }, 326 { 0x8400, 0x851E, 16384 }, 327 { 0x8500, 0x8666, 20480 }, 328 { 0x8600, 0x87AE, 24576 }, 329 { 0x8700, 0x8A3D, 32768 } 330 }; 331 332 int axe_match(device_t, cfdata_t, void *); 333 void axe_attach(device_t, device_t, void *); 334 int axe_detach(device_t, int); 335 int axe_activate(device_t, devact_t); 336 337 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 338 axe_match, axe_attach, axe_detach, axe_activate); 339 340 static int axe_tx_list_init(struct axe_softc *); 341 static int axe_rx_list_init(struct axe_softc *); 342 static int axe_encap(struct axe_softc *, struct mbuf *, int); 343 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 344 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 345 static void axe_tick(void *); 346 static void axe_tick_task(void *); 347 static void axe_start(struct ifnet *); 348 static void axe_start_locked(struct ifnet *); 349 static int axe_ioctl(struct ifnet *, u_long, void *); 350 static int axe_init(struct ifnet *); 351 static int axe_init_locked(struct ifnet *); 352 static void axe_stop(struct ifnet *, int); 353 static void axe_stop_locked(struct ifnet *, int); 354 static void axe_watchdog(struct ifnet *); 355 static int axe_miibus_readreg(device_t, int, int, uint16_t *); 356 static int axe_miibus_readreg_locked(device_t, int, int, uint16_t *); 357 static int axe_miibus_writereg(device_t, int, int, uint16_t); 358 static int axe_miibus_writereg_locked(device_t, int, int, uint16_t); 359 static void axe_miibus_statchg(struct ifnet *); 360 static int axe_cmd(struct axe_softc *, int, int, int, void *); 361 static void axe_reset(struct axe_softc *); 362 363 static void axe_setmulti(struct axe_softc *); 364 static void axe_setmulti_locked(struct axe_softc *); 365 static void axe_lock_mii(struct axe_softc *); 366 static void axe_unlock_mii(struct axe_softc *); 367 368 static void axe_ax88178_init(struct axe_softc *); 369 static void axe_ax88772_init(struct axe_softc *); 370 static void axe_ax88772a_init(struct axe_softc *); 371 static void axe_ax88772b_init(struct axe_softc *); 372 373 /* Get exclusive access to the MII registers */ 374 static void 375 axe_lock_mii(struct axe_softc *sc) 376 { 377 378 mutex_enter(&sc->axe_lock); 379 sc->axe_refcnt++; 380 mutex_exit(&sc->axe_lock); 381 382 mutex_enter(&sc->axe_mii_lock); 383 } 384 385 static void 386 axe_lock_mii_sc_locked(struct axe_softc *sc) 387 { 388 KASSERT(mutex_owned(&sc->axe_lock)); 389 390 sc->axe_refcnt++; 391 mutex_enter(&sc->axe_mii_lock); 392 } 393 394 static void 395 axe_unlock_mii(struct axe_softc *sc) 396 { 397 398 mutex_exit(&sc->axe_mii_lock); 399 mutex_enter(&sc->axe_lock); 400 if (--sc->axe_refcnt < 0) 401 cv_broadcast(&sc->axe_detachcv); 402 mutex_exit(&sc->axe_lock); 403 } 404 405 static void 406 axe_unlock_mii_sc_locked(struct axe_softc *sc) 407 { 408 KASSERT(mutex_owned(&sc->axe_lock)); 409 410 mutex_exit(&sc->axe_mii_lock); 411 if (--sc->axe_refcnt < 0) 412 cv_broadcast(&sc->axe_detachcv); 413 } 414 415 static int 416 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 417 { 418 AXEHIST_FUNC(); AXEHIST_CALLED(); 419 usb_device_request_t req; 420 usbd_status err; 421 422 KASSERT(mutex_owned(&sc->axe_mii_lock)); 423 424 if (sc->axe_dying) 425 return -1; 426 427 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 428 429 if (AXE_CMD_DIR(cmd)) 430 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 431 else 432 req.bmRequestType = UT_READ_VENDOR_DEVICE; 433 req.bRequest = AXE_CMD_CMD(cmd); 434 USETW(req.wValue, val); 435 USETW(req.wIndex, index); 436 USETW(req.wLength, AXE_CMD_LEN(cmd)); 437 438 err = usbd_do_request(sc->axe_udev, &req, buf); 439 440 if (err) { 441 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 442 return -1; 443 } 444 return 0; 445 } 446 447 static int 448 axe_miibus_readreg_locked(device_t dev, int phy, int reg, uint16_t *val) 449 { 450 AXEHIST_FUNC(); AXEHIST_CALLED(); 451 struct axe_softc *sc = device_private(dev); 452 usbd_status err; 453 uint16_t data; 454 455 mutex_enter(&sc->axe_lock); 456 if (sc->axe_dying || sc->axe_phyno != phy) { 457 mutex_exit(&sc->axe_lock); 458 return -1; 459 } 460 mutex_exit(&sc->axe_lock); 461 462 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 463 464 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 465 466 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 467 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 468 469 if (err) { 470 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 471 return err; 472 } 473 474 *val = le16toh(data); 475 if (AXE_IS_772(sc) && reg == MII_BMSR) { 476 /* 477 * BMSR of AX88772 indicates that it supports extended 478 * capability but the extended status register is 479 * reserved for embedded ethernet PHY. So clear the 480 * extended capability bit of BMSR. 481 */ 482 *val &= ~BMSR_EXTCAP; 483 } 484 485 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0); 486 487 return 0; 488 } 489 490 static int 491 axe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 492 { 493 struct axe_softc *sc = device_private(dev); 494 int rv; 495 496 mutex_enter(&sc->axe_lock); 497 if (sc->axe_dying || sc->axe_phyno != phy) { 498 mutex_exit(&sc->axe_lock); 499 return -1; 500 } 501 mutex_exit(&sc->axe_lock); 502 503 axe_lock_mii(sc); 504 rv = axe_miibus_readreg_locked(dev, phy, reg, val); 505 axe_unlock_mii(sc); 506 507 return rv; 508 } 509 510 static int 511 axe_miibus_writereg_locked(device_t dev, int phy, int reg, uint16_t aval) 512 { 513 struct axe_softc *sc = device_private(dev); 514 usbd_status err; 515 uint16_t val; 516 517 val = htole16(aval); 518 519 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 520 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 521 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 522 523 if (err) { 524 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 525 return err; 526 } 527 528 return 0; 529 } 530 531 static int 532 axe_miibus_writereg(device_t dev, int phy, int reg, uint16_t aval) 533 { 534 struct axe_softc *sc = device_private(dev); 535 int rv; 536 537 mutex_enter(&sc->axe_lock); 538 if (sc->axe_dying || sc->axe_phyno != phy) { 539 mutex_exit(&sc->axe_lock); 540 return -1; 541 } 542 mutex_exit(&sc->axe_lock); 543 544 axe_lock_mii(sc); 545 rv = axe_miibus_writereg_locked(dev, phy, reg, aval); 546 axe_unlock_mii(sc); 547 548 return rv; 549 } 550 551 static void 552 axe_miibus_statchg(struct ifnet *ifp) 553 { 554 AXEHIST_FUNC(); AXEHIST_CALLED(); 555 556 struct axe_softc * const sc = ifp->if_softc; 557 struct mii_data *mii = &sc->axe_mii; 558 int val, err; 559 560 if (sc->axe_dying) 561 return; 562 563 val = 0; 564 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 565 val |= AXE_MEDIA_FULL_DUPLEX; 566 if (AXE_IS_178_FAMILY(sc)) { 567 if ((IFM_OPTIONS(mii->mii_media_active) & 568 IFM_ETH_TXPAUSE) != 0) 569 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 570 if ((IFM_OPTIONS(mii->mii_media_active) & 571 IFM_ETH_RXPAUSE) != 0) 572 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 573 } 574 } 575 if (AXE_IS_178_FAMILY(sc)) { 576 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 577 if (sc->axe_flags & AX178) 578 val |= AXE_178_MEDIA_ENCK; 579 switch (IFM_SUBTYPE(mii->mii_media_active)) { 580 case IFM_1000_T: 581 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 582 break; 583 case IFM_100_TX: 584 val |= AXE_178_MEDIA_100TX; 585 break; 586 case IFM_10_T: 587 /* doesn't need to be handled */ 588 break; 589 } 590 } 591 592 DPRINTF("val=0x%jx", val, 0, 0, 0); 593 axe_lock_mii(sc); 594 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 595 axe_unlock_mii(sc); 596 if (err) { 597 aprint_error_dev(sc->axe_dev, "media change failed\n"); 598 return; 599 } 600 } 601 602 static void 603 axe_setmulti_locked(struct axe_softc *sc) 604 { 605 AXEHIST_FUNC(); AXEHIST_CALLED(); 606 struct ethercom *ec = &sc->axe_ec; 607 struct ifnet *ifp = &sc->sc_if; 608 struct ether_multi *enm; 609 struct ether_multistep step; 610 uint32_t h = 0; 611 uint16_t rxmode; 612 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 613 614 KASSERT(mutex_owned(&sc->axe_mii_lock)); 615 616 if (sc->axe_dying) 617 return; 618 619 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 620 aprint_error_dev(sc->axe_dev, "can't read rxmode"); 621 return; 622 } 623 rxmode = le16toh(rxmode); 624 625 rxmode &= 626 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 627 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 628 629 rxmode |= 630 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 631 632 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 633 if (ifp->if_flags & IFF_PROMISC) 634 rxmode |= AXE_RXCMD_PROMISC; 635 goto allmulti; 636 } 637 638 /* Now program new ones */ 639 ETHER_LOCK(ec); 640 ETHER_FIRST_MULTI(step, ec, enm); 641 while (enm != NULL) { 642 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 643 ETHER_ADDR_LEN) != 0) { 644 ETHER_UNLOCK(ec); 645 goto allmulti; 646 } 647 648 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 649 hashtbl[h >> 3] |= 1U << (h & 7); 650 ETHER_NEXT_MULTI(step, enm); 651 } 652 ETHER_UNLOCK(ec); 653 ifp->if_flags &= ~IFF_ALLMULTI; 654 rxmode |= AXE_RXCMD_MULTICAST; 655 656 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 657 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 658 return; 659 660 allmulti: 661 ifp->if_flags |= IFF_ALLMULTI; 662 rxmode |= AXE_RXCMD_ALLMULTI; 663 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 664 } 665 666 static void 667 axe_setmulti(struct axe_softc *sc) 668 { 669 axe_lock_mii(sc); 670 axe_setmulti_locked(sc); 671 axe_unlock_mii(sc); 672 } 673 674 static void 675 axe_ax_init(struct axe_softc *sc) 676 { 677 int cmd = AXE_178_CMD_READ_NODEID; 678 679 if (sc->axe_flags & AX178) { 680 axe_ax88178_init(sc); 681 } else if (sc->axe_flags & AX772) { 682 axe_ax88772_init(sc); 683 } else if (sc->axe_flags & AX772A) { 684 axe_ax88772a_init(sc); 685 } else if (sc->axe_flags & AX772B) { 686 axe_ax88772b_init(sc); 687 return; 688 } else { 689 cmd = AXE_172_CMD_READ_NODEID; 690 } 691 692 if (axe_cmd(sc, cmd, 0, 0, sc->axe_enaddr)) { 693 aprint_error_dev(sc->axe_dev, 694 "failed to read ethernet address\n"); 695 } 696 } 697 698 699 static void 700 axe_reset(struct axe_softc *sc) 701 { 702 703 if (sc->axe_dying) 704 return; 705 706 /* 707 * softnet_lock can be taken when NET_MPAFE is not defined when calling 708 * if_addr_init -> if_init. This doesn't mix well with the 709 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 710 * can fire during the wait and attempt to take softnet_lock and then 711 * block the softclk thread meaing the wait never ends. 712 */ 713 #ifndef NET_MPSAFE 714 /* XXX What to reset? */ 715 716 /* Wait a little while for the chip to get its brains in order. */ 717 DELAY(1000); 718 #else 719 axe_lock_mii(sc); 720 721 axe_ax_init(sc); 722 723 axe_unlock_mii(sc); 724 #endif 725 } 726 727 static int 728 axe_get_phyno(struct axe_softc *sc, int sel) 729 { 730 int phyno; 731 732 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 733 case PHY_TYPE_100_HOME: 734 /* FALLTHROUGH */ 735 case PHY_TYPE_GIG: 736 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 737 break; 738 case PHY_TYPE_SPECIAL: 739 /* FALLTHROUGH */ 740 case PHY_TYPE_RSVD: 741 /* FALLTHROUGH */ 742 case PHY_TYPE_NON_SUP: 743 /* FALLTHROUGH */ 744 default: 745 phyno = -1; 746 break; 747 } 748 749 return phyno; 750 } 751 752 #define AXE_GPIO_WRITE(x, y) do { \ 753 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 754 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 755 } while (0) 756 757 static void 758 axe_ax88178_init(struct axe_softc *sc) 759 { 760 AXEHIST_FUNC(); AXEHIST_CALLED(); 761 int gpio0, ledmode, phymode; 762 uint16_t eeprom, val; 763 764 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 765 /* XXX magic */ 766 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 767 eeprom = 0xffff; 768 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 769 770 eeprom = le16toh(eeprom); 771 772 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 773 774 /* if EEPROM is invalid we have to use to GPIO0 */ 775 if (eeprom == 0xffff) { 776 phymode = AXE_PHY_MODE_MARVELL; 777 gpio0 = 1; 778 ledmode = 0; 779 } else { 780 phymode = eeprom & 0x7f; 781 gpio0 = (eeprom & 0x80) ? 0 : 1; 782 ledmode = eeprom >> 8; 783 } 784 785 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 786 787 /* Program GPIOs depending on PHY hardware. */ 788 switch (phymode) { 789 case AXE_PHY_MODE_MARVELL: 790 if (gpio0 == 1) { 791 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 792 hz / 32); 793 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 794 hz / 32); 795 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 796 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 797 hz / 32); 798 } else { 799 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 800 AXE_GPIO1_EN, hz / 3); 801 if (ledmode == 1) { 802 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 803 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 804 hz / 3); 805 } else { 806 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 807 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 808 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 809 AXE_GPIO2_EN, hz / 4); 810 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 811 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 812 } 813 } 814 break; 815 case AXE_PHY_MODE_CICADA: 816 case AXE_PHY_MODE_CICADA_V2: 817 case AXE_PHY_MODE_CICADA_V2_ASIX: 818 if (gpio0 == 1) 819 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 820 AXE_GPIO0_EN, hz / 32); 821 else 822 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 823 AXE_GPIO1_EN, hz / 32); 824 break; 825 case AXE_PHY_MODE_AGERE: 826 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 827 AXE_GPIO1_EN, hz / 32); 828 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 829 AXE_GPIO2_EN, hz / 32); 830 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 831 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 832 AXE_GPIO2_EN, hz / 32); 833 break; 834 case AXE_PHY_MODE_REALTEK_8211CL: 835 case AXE_PHY_MODE_REALTEK_8211BN: 836 case AXE_PHY_MODE_REALTEK_8251CL: 837 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 838 AXE_GPIO1 | AXE_GPIO1_EN; 839 AXE_GPIO_WRITE(val, hz / 32); 840 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 841 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 842 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 843 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 844 axe_miibus_writereg_locked(sc->axe_dev, 845 sc->axe_phyno, 0x1F, 0x0005); 846 axe_miibus_writereg_locked(sc->axe_dev, 847 sc->axe_phyno, 0x0C, 0x0000); 848 axe_miibus_readreg_locked(sc->axe_dev, 849 sc->axe_phyno, 0x0001, &val); 850 axe_miibus_writereg_locked(sc->axe_dev, 851 sc->axe_phyno, 0x01, val | 0x0080); 852 axe_miibus_writereg_locked(sc->axe_dev, 853 sc->axe_phyno, 0x1F, 0x0000); 854 } 855 break; 856 default: 857 /* Unknown PHY model or no need to program GPIOs. */ 858 break; 859 } 860 861 /* soft reset */ 862 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 863 usbd_delay_ms(sc->axe_udev, 150); 864 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 865 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 866 usbd_delay_ms(sc->axe_udev, 150); 867 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 868 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 869 usbd_delay_ms(sc->axe_udev, 10); 870 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 871 } 872 873 static void 874 axe_ax88772_init(struct axe_softc *sc) 875 { 876 AXEHIST_FUNC(); AXEHIST_CALLED(); 877 878 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 879 usbd_delay_ms(sc->axe_udev, 40); 880 881 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 882 /* ask for the embedded PHY */ 883 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 884 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 885 usbd_delay_ms(sc->axe_udev, 10); 886 887 /* power down and reset state, pin reset state */ 888 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 889 usbd_delay_ms(sc->axe_udev, 60); 890 891 /* power down/reset state, pin operating state */ 892 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 893 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 894 usbd_delay_ms(sc->axe_udev, 150); 895 896 /* power up, reset */ 897 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 898 899 /* power up, operating */ 900 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 901 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 902 } else { 903 /* ask for external PHY */ 904 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 905 NULL); 906 usbd_delay_ms(sc->axe_udev, 10); 907 908 /* power down internal PHY */ 909 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 910 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 911 } 912 913 usbd_delay_ms(sc->axe_udev, 150); 914 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 915 } 916 917 static void 918 axe_ax88772_phywake(struct axe_softc *sc) 919 { 920 AXEHIST_FUNC(); AXEHIST_CALLED(); 921 922 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 923 /* Manually select internal(embedded) PHY - MAC mode. */ 924 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 925 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 926 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 927 } else { 928 /* 929 * Manually select external PHY - MAC mode. 930 * Reverse MII/RMII is for AX88772A PHY mode. 931 */ 932 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 933 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 934 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 935 } 936 937 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 938 AXE_SW_RESET_IPRL, NULL); 939 940 /* T1 = min 500ns everywhere */ 941 usbd_delay_ms(sc->axe_udev, 150); 942 943 /* Take PHY out of power down. */ 944 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 945 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 946 } else { 947 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 948 } 949 950 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 951 usbd_delay_ms(sc->axe_udev, 600); 952 953 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 954 955 /* T3 = 500ns everywhere */ 956 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 957 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 958 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 959 } 960 961 static void 962 axe_ax88772a_init(struct axe_softc *sc) 963 { 964 AXEHIST_FUNC(); AXEHIST_CALLED(); 965 966 /* Reload EEPROM. */ 967 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 968 axe_ax88772_phywake(sc); 969 /* Stop MAC. */ 970 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 971 } 972 973 static void 974 axe_ax88772b_init(struct axe_softc *sc) 975 { 976 AXEHIST_FUNC(); AXEHIST_CALLED(); 977 uint16_t eeprom; 978 int i; 979 980 /* Reload EEPROM. */ 981 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 982 983 /* 984 * Save PHY power saving configuration(high byte) and 985 * clear EEPROM checksum value(low byte). 986 */ 987 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 988 &eeprom)) { 989 aprint_error_dev(sc->axe_dev, "failed to read eeprom\n"); 990 return; 991 } 992 993 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 994 995 /* 996 * Auto-loaded default station address from internal ROM is 997 * 00:00:00:00:00:00 such that an explicit access to EEPROM 998 * is required to get real station address. 999 */ 1000 uint8_t *eaddr = sc->axe_enaddr; 1001 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 1002 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 1003 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 1004 aprint_error_dev(sc->axe_dev, 1005 "failed to read eeprom\n"); 1006 eeprom = 0; 1007 } 1008 eeprom = le16toh(eeprom); 1009 *eaddr++ = (uint8_t)(eeprom & 0xFF); 1010 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 1011 } 1012 /* Wakeup PHY. */ 1013 axe_ax88772_phywake(sc); 1014 /* Stop MAC. */ 1015 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 1016 } 1017 1018 #undef AXE_GPIO_WRITE 1019 1020 /* 1021 * Probe for a AX88172 chip. 1022 */ 1023 int 1024 axe_match(device_t parent, cfdata_t match, void *aux) 1025 { 1026 struct usb_attach_arg *uaa = aux; 1027 1028 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 1029 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 1030 } 1031 1032 /* 1033 * Attach the interface. Allocate softc structures, do ifmedia 1034 * setup and ethernet/BPF attach. 1035 */ 1036 void 1037 axe_attach(device_t parent, device_t self, void *aux) 1038 { 1039 AXEHIST_FUNC(); AXEHIST_CALLED(); 1040 struct axe_softc *sc = device_private(self); 1041 struct usb_attach_arg *uaa = aux; 1042 struct usbd_device *dev = uaa->uaa_device; 1043 usbd_status err; 1044 usb_interface_descriptor_t *id; 1045 usb_endpoint_descriptor_t *ed; 1046 struct mii_data *mii; 1047 char *devinfop; 1048 const char *devname = device_xname(self); 1049 struct ifnet *ifp; 1050 int i; 1051 1052 aprint_naive("\n"); 1053 aprint_normal("\n"); 1054 1055 sc->axe_dev = self; 1056 sc->axe_udev = dev; 1057 1058 devinfop = usbd_devinfo_alloc(dev, 0); 1059 aprint_normal_dev(self, "%s\n", devinfop); 1060 usbd_devinfo_free(devinfop); 1061 1062 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 1063 if (err) { 1064 aprint_error_dev(self, "failed to set configuration" 1065 ", err=%s\n", usbd_errstr(err)); 1066 return; 1067 } 1068 1069 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 1070 1071 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, USB_TASKQ_MPSAFE); 1072 1073 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 1074 if (err) { 1075 aprint_error_dev(self, "getting interface handle failed\n"); 1076 return; 1077 } 1078 1079 sc->axe_product = uaa->uaa_product; 1080 sc->axe_vendor = uaa->uaa_vendor; 1081 1082 id = usbd_get_interface_descriptor(sc->axe_iface); 1083 1084 /* decide on what our bufsize will be */ 1085 if (AXE_IS_178_FAMILY(sc)) 1086 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 1087 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 1088 else 1089 sc->axe_bufsz = AXE_172_BUFSZ; 1090 1091 sc->axe_ed[AXE_ENDPT_RX] = -1; 1092 sc->axe_ed[AXE_ENDPT_TX] = -1; 1093 sc->axe_ed[AXE_ENDPT_INTR] = -1; 1094 1095 /* Find endpoints. */ 1096 for (i = 0; i < id->bNumEndpoints; i++) { 1097 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 1098 if (ed == NULL) { 1099 aprint_error_dev(self, "couldn't get ep %d\n", i); 1100 return; 1101 } 1102 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 1103 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 1104 1105 if (dir == UE_DIR_IN && xt == UE_BULK && 1106 sc->axe_ed[AXE_ENDPT_RX] == -1) { 1107 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 1108 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 1109 sc->axe_ed[AXE_ENDPT_TX] == -1) { 1110 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 1111 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 1112 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 1113 } 1114 } 1115 1116 /* Set these up now for axe_cmd(). */ 1117 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 1118 mutex_init(&sc->axe_txlock, MUTEX_DEFAULT, IPL_SOFTUSB); 1119 mutex_init(&sc->axe_rxlock, MUTEX_DEFAULT, IPL_SOFTUSB); 1120 mutex_init(&sc->axe_lock, MUTEX_DEFAULT, IPL_NONE); 1121 cv_init(&sc->axe_detachcv, "axedet"); 1122 1123 /* We need the PHYID for init dance in some cases */ 1124 axe_lock_mii(sc); 1125 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 1126 aprint_error_dev(self, "failed to read phyaddrs\n"); 1127 1128 cv_destroy(&sc->axe_detachcv); 1129 mutex_destroy(&sc->axe_lock); 1130 mutex_destroy(&sc->axe_rxlock); 1131 mutex_destroy(&sc->axe_txlock); 1132 mutex_destroy(&sc->axe_mii_lock); 1133 1134 return; 1135 } 1136 1137 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 1138 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 1139 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 1140 if (sc->axe_phyno == -1) 1141 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 1142 if (sc->axe_phyno == -1) { 1143 DPRINTF(" no valid PHY address found, assuming PHY address 0", 1144 0, 0, 0, 0); 1145 sc->axe_phyno = 0; 1146 } 1147 1148 /* Initialize controller and get station address. */ 1149 1150 axe_ax_init(sc); 1151 1152 /* 1153 * Fetch IPG values. 1154 */ 1155 if (sc->axe_flags & (AX772A | AX772B)) { 1156 /* Set IPG values. */ 1157 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 1158 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 1159 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 1160 } else { 1161 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 1162 aprint_error_dev(self, "failed to read ipg\n"); 1163 1164 cv_destroy(&sc->axe_detachcv); 1165 mutex_destroy(&sc->axe_lock); 1166 mutex_destroy(&sc->axe_rxlock); 1167 mutex_destroy(&sc->axe_txlock); 1168 mutex_destroy(&sc->axe_mii_lock); 1169 1170 return; 1171 } 1172 } 1173 1174 axe_unlock_mii(sc); 1175 1176 /* 1177 * An ASIX chip was detected. Inform the world. 1178 */ 1179 aprint_normal_dev(self, "Ethernet address %s\n", 1180 ether_sprintf(sc->axe_enaddr)); 1181 1182 /* Initialize interface info.*/ 1183 ifp = &sc->sc_if; 1184 ifp->if_softc = sc; 1185 strlcpy(ifp->if_xname, devname, IFNAMSIZ); 1186 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1187 ifp->if_extflags = IFEF_MPSAFE; 1188 ifp->if_ioctl = axe_ioctl; 1189 ifp->if_start = axe_start; 1190 ifp->if_init = axe_init; 1191 ifp->if_stop = axe_stop; 1192 ifp->if_watchdog = axe_watchdog; 1193 1194 IFQ_SET_READY(&ifp->if_snd); 1195 1196 if (AXE_IS_178_FAMILY(sc)) 1197 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1198 if (sc->axe_flags & AX772B) { 1199 ifp->if_capabilities = 1200 IFCAP_CSUM_IPv4_Rx | 1201 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1202 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1203 /* 1204 * Checksum offloading of AX88772B also works with VLAN 1205 * tagged frames but there is no way to take advantage 1206 * of the feature because vlan(4) assumes 1207 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1208 * support checksum offloading with VLAN. VLAN hardware 1209 * tagging support of AX88772B is very limited so it's 1210 * not possible to announce IFCAP_VLAN_HWTAGGING. 1211 */ 1212 } 1213 u_int adv_pause; 1214 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1215 adv_pause = MIIF_DOPAUSE; 1216 else 1217 adv_pause = 0; 1218 adv_pause = 0; 1219 1220 /* Initialize MII/media info. */ 1221 mii = &sc->axe_mii; 1222 mii->mii_ifp = ifp; 1223 mii->mii_readreg = axe_miibus_readreg; 1224 mii->mii_writereg = axe_miibus_writereg; 1225 mii->mii_statchg = axe_miibus_statchg; 1226 mii->mii_flags = MIIF_AUTOTSLEEP; 1227 1228 sc->axe_ec.ec_mii = mii; 1229 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1230 1231 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1232 adv_pause); 1233 1234 if (LIST_EMPTY(&mii->mii_phys)) { 1235 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1236 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1237 } else 1238 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1239 1240 /* Attach the interface. */ 1241 if_attach(ifp); 1242 ether_ifattach(ifp, sc->axe_enaddr); 1243 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1244 RND_TYPE_NET, RND_FLAG_DEFAULT); 1245 1246 callout_init(&sc->axe_stat_ch, CALLOUT_MPSAFE); 1247 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1248 1249 sc->axe_attached = true; 1250 1251 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1252 1253 if (!pmf_device_register(self, NULL, NULL)) 1254 aprint_error_dev(self, "couldn't establish power handler\n"); 1255 } 1256 1257 int 1258 axe_detach(device_t self, int flags) 1259 { 1260 AXEHIST_FUNC(); AXEHIST_CALLED(); 1261 struct axe_softc *sc = device_private(self); 1262 struct ifnet *ifp = &sc->sc_if; 1263 1264 mutex_enter(&sc->axe_lock); 1265 sc->axe_dying = true; 1266 mutex_exit(&sc->axe_lock); 1267 1268 /* Detached before attached finished, so just bail out. */ 1269 if (!sc->axe_attached) 1270 return 0; 1271 1272 pmf_device_deregister(self); 1273 1274 callout_halt(&sc->axe_stat_ch, NULL); 1275 usb_rem_task_wait(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER, 1276 NULL); 1277 1278 if (ifp->if_flags & IFF_RUNNING) { 1279 IFNET_LOCK(ifp); 1280 axe_stop(ifp, 1); 1281 IFNET_UNLOCK(ifp); 1282 } 1283 1284 mutex_enter(&sc->axe_lock); 1285 sc->axe_refcnt--; 1286 while (sc->axe_refcnt > 0) { 1287 /* Wait for processes to go away */ 1288 cv_wait(&sc->axe_detachcv, &sc->axe_lock); 1289 } 1290 1291 #ifdef DIAGNOSTIC 1292 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1293 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1294 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1295 aprint_debug_dev(self, "detach has active endpoints\n"); 1296 #endif 1297 1298 mutex_exit(&sc->axe_lock); 1299 1300 callout_destroy(&sc->axe_stat_ch); 1301 rnd_detach_source(&sc->rnd_source); 1302 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1303 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1304 ether_ifdetach(ifp); 1305 if_detach(ifp); 1306 1307 sc->axe_attached = false; 1308 1309 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1310 1311 cv_destroy(&sc->axe_detachcv); 1312 mutex_destroy(&sc->axe_lock); 1313 mutex_destroy(&sc->axe_rxlock); 1314 mutex_destroy(&sc->axe_txlock); 1315 mutex_destroy(&sc->axe_mii_lock); 1316 1317 return 0; 1318 } 1319 1320 int 1321 axe_activate(device_t self, devact_t act) 1322 { 1323 AXEHIST_FUNC(); AXEHIST_CALLED(); 1324 struct axe_softc *sc = device_private(self); 1325 1326 switch (act) { 1327 case DVACT_DEACTIVATE: 1328 if_deactivate(&sc->axe_ec.ec_if); 1329 1330 mutex_enter(&sc->axe_lock); 1331 sc->axe_dying = true; 1332 mutex_exit(&sc->axe_lock); 1333 1334 mutex_enter(&sc->axe_rxlock); 1335 mutex_enter(&sc->axe_txlock); 1336 sc->axe_stopping = true; 1337 mutex_exit(&sc->axe_txlock); 1338 mutex_exit(&sc->axe_rxlock); 1339 1340 return 0; 1341 default: 1342 return EOPNOTSUPP; 1343 } 1344 } 1345 1346 static int 1347 axe_rx_list_init(struct axe_softc *sc) 1348 { 1349 AXEHIST_FUNC(); AXEHIST_CALLED(); 1350 1351 struct axe_cdata *cd; 1352 struct axe_chain *c; 1353 int i; 1354 1355 cd = &sc->axe_cdata; 1356 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1357 c = &cd->axe_rx_chain[i]; 1358 c->axe_sc = sc; 1359 if (c->axe_xfer == NULL) { 1360 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1361 sc->axe_bufsz, 0, 0, &c->axe_xfer); 1362 if (err) 1363 return err; 1364 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1365 } 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int 1372 axe_tx_list_init(struct axe_softc *sc) 1373 { 1374 AXEHIST_FUNC(); AXEHIST_CALLED(); 1375 struct axe_cdata *cd; 1376 struct axe_chain *c; 1377 int i; 1378 1379 cd = &sc->axe_cdata; 1380 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1381 c = &cd->axe_tx_chain[i]; 1382 c->axe_sc = sc; 1383 if (c->axe_xfer == NULL) { 1384 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1385 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1386 &c->axe_xfer); 1387 if (err) 1388 return err; 1389 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1390 } 1391 } 1392 1393 cd->axe_tx_cnt = 0; 1394 1395 return 0; 1396 } 1397 1398 /* 1399 * A frame has been uploaded: pass the resulting mbuf chain up to 1400 * the higher level protocols. 1401 */ 1402 static void 1403 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1404 { 1405 AXEHIST_FUNC(); AXEHIST_CALLED(); 1406 struct axe_chain *c = (struct axe_chain *)priv; 1407 struct axe_softc * const sc = c->axe_sc; 1408 struct ifnet *ifp = &sc->sc_if; 1409 uint8_t *buf = c->axe_buf; 1410 uint32_t total_len; 1411 struct mbuf *m; 1412 1413 mutex_enter(&sc->axe_rxlock); 1414 1415 if (sc->axe_dying || sc->axe_stopping || 1416 status == USBD_INVAL || status == USBD_NOT_STARTED || 1417 status == USBD_CANCELLED || !(ifp->if_flags & IFF_RUNNING)) { 1418 mutex_exit(&sc->axe_rxlock); 1419 return; 1420 } 1421 1422 if (status != USBD_NORMAL_COMPLETION) { 1423 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1424 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1425 usbd_errstr(status)); 1426 } 1427 if (status == USBD_STALLED) 1428 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1429 goto done; 1430 } 1431 1432 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1433 1434 do { 1435 u_int pktlen = 0; 1436 u_int rxlen = 0; 1437 int flags = 0; 1438 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1439 struct axe_sframe_hdr hdr; 1440 1441 if (total_len < sizeof(hdr)) { 1442 ifp->if_ierrors++; 1443 goto done; 1444 } 1445 1446 #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1) 1447 /* 1448 * XXX hdr is 2-byte aligned in buf, not 4-byte. 1449 * For some architectures, __builtin_memcpy() of 1450 * GCC 6 attempts to copy sizeof(hdr) = 4 bytes 1451 * at onece, which results in alignment error. 1452 */ 1453 hdr.len = *(uint16_t *)buf; 1454 hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t)); 1455 #else 1456 memcpy(&hdr, buf, sizeof(hdr)); 1457 #endif 1458 1459 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1460 total_len, 1461 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1462 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1463 1464 total_len -= sizeof(hdr); 1465 buf += sizeof(hdr); 1466 1467 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1468 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1469 AXE_RH1M_RXLEN_MASK) { 1470 ifp->if_ierrors++; 1471 goto done; 1472 } 1473 1474 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1475 if (total_len < rxlen) { 1476 pktlen = total_len; 1477 total_len = 0; 1478 } else { 1479 pktlen = rxlen; 1480 rxlen = roundup2(rxlen, 2); 1481 total_len -= rxlen; 1482 } 1483 1484 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1485 struct axe_csum_hdr csum_hdr; 1486 1487 if (total_len < sizeof(csum_hdr)) { 1488 ifp->if_ierrors++; 1489 goto done; 1490 } 1491 1492 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1493 1494 csum_hdr.len = le16toh(csum_hdr.len); 1495 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1496 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1497 1498 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1499 " cstatus %#jx", total_len, 1500 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1501 1502 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1503 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1504 sc->sc_lenmask) { 1505 /* we lost sync */ 1506 ifp->if_ierrors++; 1507 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1508 "err", 1509 AXE_CSUM_RXBYTES(csum_hdr.len), 1510 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1511 sc->sc_lenmask, 0); 1512 goto done; 1513 } 1514 /* 1515 * Get total transferred frame length including 1516 * checksum header. The length should be multiple 1517 * of 4. 1518 */ 1519 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1520 u_int len = sizeof(csum_hdr) + pktlen; 1521 len = (len + 3) & ~3; 1522 if (total_len < len) { 1523 DPRINTFN(20, "total_len %#jx < len %#jx", 1524 total_len, len, 0, 0); 1525 /* invalid length */ 1526 ifp->if_ierrors++; 1527 goto done; 1528 } 1529 buf += sizeof(csum_hdr); 1530 1531 const uint16_t cstatus = csum_hdr.cstatus; 1532 1533 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1534 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1535 flags |= M_CSUM_TCP_UDP_BAD; 1536 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1537 flags |= M_CSUM_IPv4_BAD; 1538 1539 const uint16_t l4type = 1540 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1541 1542 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1543 flags |= M_CSUM_TCPv4; 1544 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1545 flags |= M_CSUM_UDPv4; 1546 } 1547 if (total_len < len) { 1548 pktlen = total_len; 1549 total_len = 0; 1550 } else { 1551 total_len -= len; 1552 rxlen = len - sizeof(csum_hdr); 1553 } 1554 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1555 " rxlen %#jx", total_len, len, pktlen, rxlen); 1556 } else { /* AX172 */ 1557 pktlen = rxlen = total_len; 1558 total_len = 0; 1559 } 1560 1561 MGETHDR(m, M_DONTWAIT, MT_DATA); 1562 if (m == NULL) { 1563 ifp->if_ierrors++; 1564 goto done; 1565 } 1566 1567 if (pktlen > MHLEN - ETHER_ALIGN) { 1568 MCLGET(m, M_DONTWAIT); 1569 if ((m->m_flags & M_EXT) == 0) { 1570 m_freem(m); 1571 ifp->if_ierrors++; 1572 goto done; 1573 } 1574 } 1575 m->m_data += ETHER_ALIGN; 1576 1577 m_set_rcvif(m, ifp); 1578 m->m_pkthdr.len = m->m_len = pktlen; 1579 m->m_pkthdr.csum_flags = flags; 1580 1581 memcpy(mtod(m, uint8_t *), buf, pktlen); 1582 buf += rxlen; 1583 1584 DPRINTFN(10, "deliver %jd (%#jx)", m->m_len, m->m_len, 0, 0); 1585 1586 mutex_exit(&sc->axe_rxlock); 1587 1588 if_percpuq_enqueue((ifp)->if_percpuq, (m)); 1589 1590 mutex_enter(&sc->axe_rxlock); 1591 if (sc->axe_dying || sc->axe_stopping) { 1592 mutex_exit(&sc->axe_rxlock); 1593 return; 1594 } 1595 1596 } while (total_len > 0); 1597 1598 done: 1599 1600 if (sc->axe_dying || sc->axe_stopping) { 1601 mutex_exit(&sc->axe_rxlock); 1602 return; 1603 } 1604 1605 mutex_exit(&sc->axe_rxlock); 1606 1607 /* Setup new transfer. */ 1608 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1609 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1610 usbd_transfer(xfer); 1611 1612 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1613 } 1614 1615 /* 1616 * A frame was downloaded to the chip. It's safe for us to clean up 1617 * the list buffers. 1618 */ 1619 1620 static void 1621 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1622 { 1623 AXEHIST_FUNC(); AXEHIST_CALLED(); 1624 struct axe_chain *c = priv; 1625 struct axe_softc *sc = c->axe_sc; 1626 struct axe_cdata *cd = &sc->axe_cdata; 1627 struct ifnet *ifp = &sc->sc_if; 1628 1629 mutex_enter(&sc->axe_txlock); 1630 if (sc->axe_stopping || sc->axe_dying) { 1631 mutex_exit(&sc->axe_txlock); 1632 return; 1633 } 1634 1635 KASSERT(cd->axe_tx_cnt == 1); 1636 cd->axe_tx_cnt--; 1637 1638 sc->axe_timer = 0; 1639 1640 switch (status) { 1641 case USBD_NOT_STARTED: 1642 case USBD_CANCELLED: 1643 break; 1644 1645 case USBD_NORMAL_COMPLETION: 1646 ifp->if_opackets++; 1647 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1648 axe_start_locked(ifp); 1649 break; 1650 1651 default: 1652 1653 ifp->if_oerrors++; 1654 if (usbd_ratecheck(&sc->axe_tx_notice)) 1655 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1656 usbd_errstr(status)); 1657 if (status == USBD_STALLED) 1658 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1659 break; 1660 } 1661 1662 mutex_exit(&sc->axe_txlock); 1663 } 1664 1665 static void 1666 axe_tick(void *xsc) 1667 { 1668 AXEHIST_FUNC(); AXEHIST_CALLED(); 1669 struct axe_softc *sc = xsc; 1670 1671 if (sc == NULL) 1672 return; 1673 1674 mutex_enter(&sc->axe_lock); 1675 if (!sc->axe_stopping && !sc->axe_dying) { 1676 /* Perform periodic stuff in process context */ 1677 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1678 } 1679 mutex_exit(&sc->axe_lock); 1680 1681 } 1682 1683 static void 1684 axe_tick_task(void *xsc) 1685 { 1686 AXEHIST_FUNC(); AXEHIST_CALLED(); 1687 struct axe_softc *sc = xsc; 1688 struct ifnet *ifp; 1689 struct mii_data *mii; 1690 1691 if (sc == NULL) 1692 return; 1693 1694 mutex_enter(&sc->axe_lock); 1695 if (sc->axe_stopping || sc->axe_dying) { 1696 mutex_exit(&sc->axe_lock); 1697 return; 1698 } 1699 1700 ifp = &sc->sc_if; 1701 mii = &sc->axe_mii; 1702 1703 if (mii == NULL) { 1704 mutex_exit(&sc->axe_lock); 1705 return; 1706 } 1707 1708 sc->axe_refcnt++; 1709 mutex_exit(&sc->axe_lock); 1710 1711 if (sc->axe_timer != 0 && --sc->axe_timer == 0) 1712 axe_watchdog(ifp); 1713 1714 mii_tick(mii); 1715 1716 if (sc->axe_link == 0 && 1717 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1718 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1719 DPRINTF("got link", 0, 0, 0, 0); 1720 sc->axe_link++; 1721 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1722 axe_start(ifp); 1723 } 1724 1725 1726 mutex_enter(&sc->axe_lock); 1727 if (--sc->axe_refcnt < 0) 1728 cv_broadcast(&sc->axe_detachcv); 1729 if (!sc->axe_stopping && !sc->axe_dying) 1730 callout_schedule(&sc->axe_stat_ch, hz); 1731 mutex_exit(&sc->axe_lock); 1732 } 1733 1734 static int 1735 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1736 { 1737 struct ifnet *ifp = &sc->sc_if; 1738 struct axe_chain *c; 1739 usbd_status err; 1740 int length, boundary; 1741 1742 KASSERT(mutex_owned(&sc->axe_txlock)); 1743 1744 c = &sc->axe_cdata.axe_tx_chain[idx]; 1745 1746 /* 1747 * Copy the mbuf data into a contiguous buffer, leaving two 1748 * bytes at the beginning to hold the frame length. 1749 */ 1750 if (AXE_IS_178_FAMILY(sc)) { 1751 struct axe_sframe_hdr hdr; 1752 1753 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1754 1755 hdr.len = htole16(m->m_pkthdr.len); 1756 hdr.ilen = ~hdr.len; 1757 1758 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1759 length = sizeof(hdr); 1760 1761 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1762 length += m->m_pkthdr.len; 1763 1764 if ((length % boundary) == 0) { 1765 hdr.len = 0x0000; 1766 hdr.ilen = 0xffff; 1767 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1768 length += sizeof(hdr); 1769 } 1770 } else { 1771 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1772 length = m->m_pkthdr.len; 1773 } 1774 1775 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1776 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1777 1778 /* Transmit */ 1779 err = usbd_transfer(c->axe_xfer); 1780 if (err != USBD_IN_PROGRESS) { 1781 /* XXXSMP IFNET_LOCK */ 1782 axe_stop(ifp, 0); 1783 return EIO; 1784 } 1785 1786 sc->axe_cdata.axe_tx_cnt++; 1787 1788 return 0; 1789 } 1790 1791 1792 static void 1793 axe_csum_cfg(struct axe_softc *sc) 1794 { 1795 struct ifnet *ifp = &sc->sc_if; 1796 uint16_t csum1, csum2; 1797 1798 if ((sc->axe_flags & AX772B) != 0) { 1799 csum1 = 0; 1800 csum2 = 0; 1801 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1802 csum1 |= AXE_TXCSUM_IP; 1803 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1804 csum1 |= AXE_TXCSUM_TCP; 1805 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1806 csum1 |= AXE_TXCSUM_UDP; 1807 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1808 csum1 |= AXE_TXCSUM_TCPV6; 1809 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1810 csum1 |= AXE_TXCSUM_UDPV6; 1811 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1812 csum1 = 0; 1813 csum2 = 0; 1814 1815 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1816 csum1 |= AXE_RXCSUM_IP; 1817 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1818 csum1 |= AXE_RXCSUM_TCP; 1819 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1820 csum1 |= AXE_RXCSUM_UDP; 1821 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1822 csum1 |= AXE_RXCSUM_TCPV6; 1823 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1824 csum1 |= AXE_RXCSUM_UDPV6; 1825 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1826 } 1827 } 1828 1829 static void 1830 axe_start_locked(struct ifnet *ifp) 1831 { 1832 struct axe_softc *sc = ifp->if_softc; 1833 struct mbuf *m; 1834 struct axe_cdata *cd = &sc->axe_cdata; 1835 1836 KASSERT(mutex_owned(&sc->axe_txlock)); 1837 1838 if (cd->axe_tx_cnt != 0) 1839 return; 1840 1841 if (sc->axe_link == 0 || (ifp->if_flags & IFF_RUNNING) == 0) 1842 return; 1843 1844 IFQ_POLL(&ifp->if_snd, m); 1845 if (m == NULL) { 1846 return; 1847 } 1848 1849 if (axe_encap(sc, m, 0)) { 1850 return; 1851 } 1852 IFQ_DEQUEUE(&ifp->if_snd, m); 1853 1854 /* 1855 * If there's a BPF listener, bounce a copy of this frame 1856 * to him. 1857 */ 1858 bpf_mtap(ifp, m, BPF_D_OUT); 1859 m_freem(m); 1860 1861 /* 1862 * Set a timeout in case the chip goes out to lunch. 1863 */ 1864 sc->axe_timer = 5; 1865 1866 return; 1867 } 1868 1869 static void 1870 axe_start(struct ifnet *ifp) 1871 { 1872 struct axe_softc * const sc = ifp->if_softc; 1873 1874 mutex_enter(&sc->axe_txlock); 1875 if (!sc->axe_stopping) 1876 axe_start_locked(ifp); 1877 mutex_exit(&sc->axe_txlock); 1878 } 1879 1880 static int 1881 axe_init_locked(struct ifnet *ifp) 1882 { 1883 AXEHIST_FUNC(); AXEHIST_CALLED(); 1884 struct axe_softc *sc = ifp->if_softc; 1885 struct axe_chain *c; 1886 usbd_status err; 1887 int rxmode; 1888 int i; 1889 1890 KASSERT(mutex_owned(&sc->axe_lock)); 1891 1892 if (sc->axe_dying) 1893 return EIO; 1894 1895 /* Cancel pending I/O */ 1896 axe_stop_locked(ifp, 0); 1897 1898 /* Reset the ethernet interface. */ 1899 axe_reset(sc); 1900 1901 axe_lock_mii_sc_locked(sc); 1902 1903 #if 0 1904 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1905 AX_GPIO_GPO2EN, 5, in_pm); 1906 #endif 1907 /* Set MAC address and transmitter IPG values. */ 1908 if (AXE_IS_178_FAMILY(sc)) { 1909 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1910 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1911 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1912 } else { 1913 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1914 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1915 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1916 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1917 } 1918 if (AXE_IS_178_FAMILY(sc)) { 1919 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1920 if ((sc->axe_flags & AX772B) != 0 && 1921 (ifp->if_capenable & AX_RXCSUM) != 0) { 1922 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1923 sc->axe_flags |= AXCSUM_FRAME; 1924 } else { 1925 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1926 sc->axe_flags |= AXSTD_FRAME; 1927 } 1928 } 1929 1930 /* Configure TX/RX checksum offloading. */ 1931 axe_csum_cfg(sc); 1932 1933 if (sc->axe_flags & AX772B) { 1934 /* AX88772B uses different maximum frame burst configuration. */ 1935 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1936 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1937 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1938 } 1939 /* Enable receiver, set RX mode */ 1940 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1941 if (AXE_IS_178_FAMILY(sc)) { 1942 if (sc->axe_flags & AX772B) { 1943 /* 1944 * Select RX header format type 1. Aligning IP 1945 * header on 4 byte boundary is not needed when 1946 * checksum offloading feature is not used 1947 * because we always copy the received frame in 1948 * RX handler. When RX checksum offloading is 1949 * active, aligning IP header is required to 1950 * reflect actual frame length including RX 1951 * header size. 1952 */ 1953 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1954 if (sc->axe_flags & AXCSUM_FRAME) 1955 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1956 } else { 1957 /* 1958 * Default Rx buffer size is too small to get 1959 * maximum performance. 1960 */ 1961 #if 0 1962 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1963 /* Largest possible USB buffer size for AX88178 */ 1964 } 1965 #endif 1966 rxmode |= AXE_178_RXCMD_MFB_16384; 1967 } 1968 } else { 1969 rxmode |= AXE_172_RXCMD_UNICAST; 1970 } 1971 1972 1973 /* If we want promiscuous mode, set the allframes bit. */ 1974 if (ifp->if_flags & IFF_PROMISC) 1975 rxmode |= AXE_RXCMD_PROMISC; 1976 1977 if (ifp->if_flags & IFF_BROADCAST) 1978 rxmode |= AXE_RXCMD_BROADCAST; 1979 1980 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1981 1982 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1983 1984 /* Load the multicast filter. */ 1985 axe_setmulti_locked(sc); 1986 1987 axe_unlock_mii_sc_locked(sc); 1988 1989 /* Open RX and TX pipes. */ 1990 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1991 USBD_EXCLUSIVE_USE | USBD_MPSAFE, &sc->axe_ep[AXE_ENDPT_RX]); 1992 if (err) { 1993 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1994 usbd_errstr(err)); 1995 return EIO; 1996 } 1997 1998 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1999 USBD_EXCLUSIVE_USE | USBD_MPSAFE, &sc->axe_ep[AXE_ENDPT_TX]); 2000 if (err) { 2001 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 2002 usbd_errstr(err)); 2003 return EIO; 2004 } 2005 2006 /* Init RX ring. */ 2007 if (axe_rx_list_init(sc) != 0) { 2008 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 2009 return ENOBUFS; 2010 } 2011 2012 /* Init TX ring. */ 2013 if (axe_tx_list_init(sc) != 0) { 2014 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 2015 return ENOBUFS; 2016 } 2017 2018 mutex_enter(&sc->axe_rxlock); 2019 mutex_enter(&sc->axe_txlock); 2020 sc->axe_stopping = false; 2021 2022 /* Start up the receive pipe. */ 2023 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 2024 c = &sc->axe_cdata.axe_rx_chain[i]; 2025 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 2026 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 2027 usbd_transfer(c->axe_xfer); 2028 } 2029 2030 mutex_exit(&sc->axe_txlock); 2031 mutex_exit(&sc->axe_rxlock); 2032 2033 /* Indicate we are up and running. */ 2034 KASSERT(IFNET_LOCKED(ifp)); 2035 ifp->if_flags |= IFF_RUNNING; 2036 2037 callout_schedule(&sc->axe_stat_ch, hz); 2038 return 0; 2039 } 2040 2041 static int 2042 axe_init(struct ifnet *ifp) 2043 { 2044 struct axe_softc * const sc = ifp->if_softc; 2045 2046 mutex_enter(&sc->axe_lock); 2047 int ret = axe_init_locked(ifp); 2048 mutex_exit(&sc->axe_lock); 2049 2050 return ret; 2051 } 2052 2053 static int 2054 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2055 { 2056 struct axe_softc *sc = ifp->if_softc; 2057 int error = 0; 2058 2059 switch (cmd) { 2060 case SIOCSIFFLAGS: 2061 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2062 break; 2063 2064 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2065 case IFF_RUNNING: 2066 axe_stop(ifp, 1); 2067 break; 2068 case IFF_UP: 2069 axe_init(ifp); 2070 break; 2071 case IFF_UP | IFF_RUNNING: 2072 if ((ifp->if_flags ^ sc->axe_if_flags) == IFF_PROMISC) 2073 axe_setmulti(sc); 2074 else 2075 axe_init(ifp); 2076 break; 2077 } 2078 mutex_enter(&sc->axe_rxlock); 2079 mutex_enter(&sc->axe_txlock); 2080 sc->axe_if_flags = ifp->if_flags; 2081 mutex_exit(&sc->axe_txlock); 2082 mutex_exit(&sc->axe_rxlock); 2083 break; 2084 2085 default: 2086 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2087 break; 2088 2089 error = 0; 2090 2091 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) 2092 axe_setmulti(sc); 2093 2094 } 2095 2096 return error; 2097 } 2098 2099 static void 2100 axe_watchdog(struct ifnet *ifp) 2101 { 2102 struct axe_softc * const sc = ifp->if_softc; 2103 struct axe_chain *c; 2104 usbd_status stat; 2105 2106 ifp->if_oerrors++; 2107 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 2108 2109 c = &sc->axe_cdata.axe_tx_chain[0]; 2110 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 2111 axe_txeof(c->axe_xfer, c, stat); 2112 2113 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2114 axe_start(ifp); 2115 } 2116 2117 /* 2118 * Stop the adapter and free any mbufs allocated to the 2119 * RX and TX lists. 2120 */ 2121 static void 2122 axe_stop_locked(struct ifnet *ifp, int disable) 2123 { 2124 struct axe_softc * const sc = ifp->if_softc; 2125 usbd_status err; 2126 int i; 2127 2128 KASSERT(mutex_owned(&sc->axe_lock)); 2129 2130 mutex_enter(&sc->axe_rxlock); 2131 mutex_enter(&sc->axe_txlock); 2132 sc->axe_stopping = true; 2133 mutex_exit(&sc->axe_txlock); 2134 mutex_exit(&sc->axe_rxlock); 2135 2136 /* 2137 * XXXSMP Would like to 2138 * KASSERT(IFNET_LOCKED(ifp)) 2139 * here but the locking order is: 2140 * ifnet -> sc lock -> rxlock -> txlock 2141 * and sc lock is already held. 2142 */ 2143 ifp->if_flags &= ~IFF_RUNNING; 2144 sc->axe_timer = 0; 2145 2146 callout_stop(&sc->axe_stat_ch); 2147 sc->axe_link = 0; 2148 2149 /* Stop transfers. */ 2150 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 2151 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 2152 if (err) { 2153 aprint_error_dev(sc->axe_dev, 2154 "abort rx pipe failed: %s\n", usbd_errstr(err)); 2155 } 2156 } 2157 2158 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 2159 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 2160 if (err) { 2161 aprint_error_dev(sc->axe_dev, 2162 "abort tx pipe failed: %s\n", usbd_errstr(err)); 2163 } 2164 } 2165 2166 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 2167 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 2168 if (err) { 2169 aprint_error_dev(sc->axe_dev, 2170 "abort intr pipe failed: %s\n", usbd_errstr(err)); 2171 } 2172 } 2173 2174 axe_reset(sc); 2175 2176 /* Free RX resources. */ 2177 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 2178 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 2179 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 2180 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 2181 } 2182 } 2183 2184 /* Free TX resources. */ 2185 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 2186 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 2187 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 2188 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 2189 } 2190 } 2191 2192 /* Close pipes. */ 2193 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 2194 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 2195 if (err) { 2196 aprint_error_dev(sc->axe_dev, 2197 "close rx pipe failed: %s\n", usbd_errstr(err)); 2198 } 2199 sc->axe_ep[AXE_ENDPT_RX] = NULL; 2200 } 2201 2202 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 2203 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 2204 if (err) { 2205 aprint_error_dev(sc->axe_dev, 2206 "close tx pipe failed: %s\n", usbd_errstr(err)); 2207 } 2208 sc->axe_ep[AXE_ENDPT_TX] = NULL; 2209 } 2210 2211 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 2212 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 2213 if (err) { 2214 aprint_error_dev(sc->axe_dev, 2215 "close intr pipe failed: %s\n", usbd_errstr(err)); 2216 } 2217 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 2218 } 2219 } 2220 2221 static void 2222 axe_stop(struct ifnet *ifp, int disable) 2223 { 2224 struct axe_softc * const sc = ifp->if_softc; 2225 2226 mutex_enter(&sc->axe_lock); 2227 axe_stop_locked(ifp, disable); 2228 mutex_exit(&sc->axe_lock); 2229 } 2230 2231 MODULE(MODULE_CLASS_DRIVER, if_axe, NULL); 2232 2233 #ifdef _MODULE 2234 #include "ioconf.c" 2235 #endif 2236 2237 static int 2238 if_axe_modcmd(modcmd_t cmd, void *aux) 2239 { 2240 int error = 0; 2241 2242 switch (cmd) { 2243 case MODULE_CMD_INIT: 2244 #ifdef _MODULE 2245 error = config_init_component(cfdriver_ioconf_axe, 2246 cfattach_ioconf_axe, cfdata_ioconf_axe); 2247 #endif 2248 return error; 2249 case MODULE_CMD_FINI: 2250 #ifdef _MODULE 2251 error = config_fini_component(cfdriver_ioconf_axe, 2252 cfattach_ioconf_axe, cfdata_ioconf_axe); 2253 #endif 2254 return error; 2255 default: 2256 return ENOTTY; 2257 } 2258 } 2259
Indexes created Wed Oct 01 18:09:54 GMT 2025