if_axe.c revision 1.106
1 /* $NetBSD: if_axe.c,v 1.106 2019/08/06 01:42:22 mrg Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.106 2019/08/06 01:42:22 mrg Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_usb.h" 94 #include "opt_net_mpsafe.h" 95 #endif 96 97 #include <sys/param.h> 98 #include <sys/kernel.h> 99 #include <sys/module.h> 100 #include <sys/socket.h> 101 #include <sys/sockio.h> 102 #include <sys/systm.h> 103 104 #include <dev/usb/usbnet.h> 105 #include <dev/usb/usbhist.h> 106 #include <dev/usb/if_axereg.h> 107 108 struct axe_type { 109 struct usb_devno axe_dev; 110 uint16_t axe_flags; 111 }; 112 113 struct axe_softc { 114 struct usbnet axe_un; 115 116 uint32_t axe_flags; /* copied from axe_type */ 117 #define AX178 __BIT(0) /* AX88178 */ 118 #define AX772 __BIT(1) /* AX88772 */ 119 #define AX772A __BIT(2) /* AX88772A */ 120 #define AX772B __BIT(3) /* AX88772B */ 121 #define AXSTD_FRAME __BIT(12) 122 #define AXCSUM_FRAME __BIT(13) 123 124 uint8_t axe_ipgs[3]; 125 uint8_t axe_phyaddrs[2]; 126 uint16_t sc_pwrcfg; 127 uint16_t sc_lenmask; 128 129 }; 130 131 #define AXE_IS_178_FAMILY(sc) \ 132 ((sc)->axe_flags & (AX772 | AX772A | AX772B | AX178)) 133 134 #define AXE_IS_772(sc) \ 135 ((sc)->axe_flags & (AX772 | AX772A | AX772B)) 136 137 #define AX_RXCSUM \ 138 (IFCAP_CSUM_IPv4_Rx | \ 139 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 140 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 141 142 #define AX_TXCSUM \ 143 (IFCAP_CSUM_IPv4_Tx | \ 144 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 145 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 146 147 /* 148 * AXE_178_MAX_FRAME_BURST 149 * max frame burst size for Ax88178 and Ax88772 150 * 0 2048 bytes 151 * 1 4096 bytes 152 * 2 8192 bytes 153 * 3 16384 bytes 154 * use the largest your system can handle without USB stalling. 155 * 156 * NB: 88772 parts appear to generate lots of input errors with 157 * a 2K rx buffer and 8K is only slightly faster than 4K on an 158 * EHCI port on a T42 so change at your own risk. 159 */ 160 #define AXE_178_MAX_FRAME_BURST 1 161 162 163 #ifdef USB_DEBUG 164 #ifndef AXE_DEBUG 165 #define axedebug 0 166 #else 167 static int axedebug = 20; 168 169 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 170 { 171 int err; 172 const struct sysctlnode *rnode; 173 const struct sysctlnode *cnode; 174 175 err = sysctl_createv(clog, 0, NULL, &rnode, 176 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 177 SYSCTL_DESCR("axe global controls"), 178 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 179 180 if (err) 181 goto fail; 182 183 /* control debugging printfs */ 184 err = sysctl_createv(clog, 0, &rnode, &cnode, 185 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 186 "debug", SYSCTL_DESCR("Enable debugging output"), 187 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 188 if (err) 189 goto fail; 190 191 return; 192 fail: 193 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 194 } 195 196 #endif /* AXE_DEBUG */ 197 #endif /* USB_DEBUG */ 198 199 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 200 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 201 #define AXEHIST_FUNC() USBHIST_FUNC() 202 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 203 204 /* 205 * Various supported device vendors/products. 206 */ 207 static const struct axe_type axe_devs[] = { 208 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 209 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 210 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 211 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 212 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 213 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 214 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 215 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 216 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 217 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 218 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 219 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 220 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 221 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 222 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 223 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 224 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 225 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 226 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 227 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 228 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 229 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 230 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 231 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 232 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 233 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 234 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 235 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 236 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 237 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 238 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 239 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 240 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 241 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 242 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 243 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 244 }; 245 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 246 247 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 248 { 0x8000, 0x8001, 2048 }, 249 { 0x8100, 0x8147, 4096 }, 250 { 0x8200, 0x81EB, 6144 }, 251 { 0x8300, 0x83D7, 8192 }, 252 { 0x8400, 0x851E, 16384 }, 253 { 0x8500, 0x8666, 20480 }, 254 { 0x8600, 0x87AE, 24576 }, 255 { 0x8700, 0x8A3D, 32768 } 256 }; 257 258 int axe_match(device_t, cfdata_t, void *); 259 void axe_attach(device_t, device_t, void *); 260 261 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 262 axe_match, axe_attach, usbnet_detach, usbnet_activate); 263 264 static void axe_rx_loop_cb(struct usbnet *, struct usbd_xfer *, 265 struct usbnet_chain *, uint32_t); 266 static unsigned axe_tx_prepare_cb(struct usbnet *, struct mbuf *, 267 struct usbnet_chain *); 268 static int axe_init(struct ifnet *); 269 static void axe_stop_cb(struct ifnet *, int); 270 static int axe_ioctl_cb(struct ifnet *, u_long, void *); 271 272 static void axe_ax88178_init(struct axe_softc *); 273 static void axe_ax88772_init(struct axe_softc *); 274 static void axe_ax88772a_init(struct axe_softc *); 275 static void axe_ax88772b_init(struct axe_softc *); 276 277 static usbd_status 278 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 279 { 280 AXEHIST_FUNC(); AXEHIST_CALLED(); 281 struct usbnet * const un = &sc->axe_un; 282 usb_device_request_t req; 283 usbd_status err; 284 285 usbnet_isowned_mii(un); 286 287 if (un->un_dying) 288 return -1; 289 290 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 291 292 if (AXE_CMD_DIR(cmd)) 293 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 294 else 295 req.bmRequestType = UT_READ_VENDOR_DEVICE; 296 req.bRequest = AXE_CMD_CMD(cmd); 297 USETW(req.wValue, val); 298 USETW(req.wIndex, index); 299 USETW(req.wLength, AXE_CMD_LEN(cmd)); 300 301 err = usbd_do_request(un->un_udev, &req, buf); 302 if (err) 303 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 304 305 return err; 306 } 307 308 static usbd_status 309 axe_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 310 { 311 AXEHIST_FUNC(); AXEHIST_CALLED(); 312 struct axe_softc * const sc = usbnet_softc(un); 313 usbd_status err; 314 uint16_t data; 315 316 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 317 318 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 319 320 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 321 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 322 323 if (err) { 324 aprint_error_dev(un->un_dev, "read PHY failed\n"); 325 return err; 326 } 327 328 *val = le16toh(data); 329 if (AXE_IS_772(sc) && reg == MII_BMSR) { 330 /* 331 * BMSR of AX88772 indicates that it supports extended 332 * capability but the extended status register is 333 * reserved for embedded ethernet PHY. So clear the 334 * extended capability bit of BMSR. 335 */ 336 *val &= ~BMSR_EXTCAP; 337 } 338 339 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0); 340 341 return USBD_NORMAL_COMPLETION; 342 } 343 344 static usbd_status 345 axe_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 346 { 347 struct axe_softc * const sc = usbnet_softc(un); 348 usbd_status err; 349 uint16_t aval; 350 351 aval = htole16(val); 352 353 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 354 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval); 355 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 356 357 return err; 358 } 359 360 static void 361 axe_mii_statchg_cb(struct ifnet *ifp) 362 { 363 AXEHIST_FUNC(); AXEHIST_CALLED(); 364 365 struct usbnet * const un = ifp->if_softc; 366 struct axe_softc * const sc = usbnet_softc(un); 367 struct mii_data *mii = &un->un_mii; 368 int val, err; 369 370 if (un->un_dying) 371 return; 372 373 val = 0; 374 un->un_link = false; 375 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 376 val |= AXE_MEDIA_FULL_DUPLEX; 377 if (AXE_IS_178_FAMILY(sc)) { 378 if ((IFM_OPTIONS(mii->mii_media_active) & 379 IFM_ETH_TXPAUSE) != 0) 380 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 381 if ((IFM_OPTIONS(mii->mii_media_active) & 382 IFM_ETH_RXPAUSE) != 0) 383 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 384 } 385 } 386 if (AXE_IS_178_FAMILY(sc)) { 387 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 388 if (sc->axe_flags & AX178) 389 val |= AXE_178_MEDIA_ENCK; 390 switch (IFM_SUBTYPE(mii->mii_media_active)) { 391 case IFM_1000_T: 392 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 393 un->un_link = true; 394 break; 395 case IFM_100_TX: 396 val |= AXE_178_MEDIA_100TX; 397 un->un_link = true; 398 break; 399 case IFM_10_T: 400 un->un_link = true; 401 break; 402 } 403 } 404 405 DPRINTF("val=0x%jx", val, 0, 0, 0); 406 usbnet_lock_mii(un); 407 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 408 usbnet_unlock_mii(un); 409 if (err) 410 aprint_error_dev(un->un_dev, "media change failed\n"); 411 } 412 413 static void 414 axe_setiff_locked(struct usbnet *un) 415 { 416 AXEHIST_FUNC(); AXEHIST_CALLED(); 417 struct axe_softc * const sc = usbnet_softc(un); 418 struct ifnet * const ifp = usbnet_ifp(un); 419 struct ethercom *ec = usbnet_ec(un); 420 struct ether_multi *enm; 421 struct ether_multistep step; 422 uint32_t h = 0; 423 uint16_t rxmode; 424 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 425 426 usbnet_isowned_mii(un); 427 428 if (un->un_dying) 429 return; 430 431 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 432 aprint_error_dev(un->un_dev, "can't read rxmode"); 433 return; 434 } 435 rxmode = le16toh(rxmode); 436 437 rxmode &= 438 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 439 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 440 441 rxmode |= 442 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 443 444 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 445 if (ifp->if_flags & IFF_PROMISC) 446 rxmode |= AXE_RXCMD_PROMISC; 447 goto allmulti; 448 } 449 450 /* Now program new ones */ 451 ETHER_LOCK(ec); 452 ETHER_FIRST_MULTI(step, ec, enm); 453 while (enm != NULL) { 454 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 455 ETHER_ADDR_LEN) != 0) { 456 ETHER_UNLOCK(ec); 457 goto allmulti; 458 } 459 460 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 461 hashtbl[h >> 3] |= 1U << (h & 7); 462 ETHER_NEXT_MULTI(step, enm); 463 } 464 ETHER_UNLOCK(ec); 465 ifp->if_flags &= ~IFF_ALLMULTI; 466 rxmode |= AXE_RXCMD_MULTICAST; 467 468 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 469 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 470 return; 471 472 allmulti: 473 ifp->if_flags |= IFF_ALLMULTI; 474 rxmode |= AXE_RXCMD_ALLMULTI; 475 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 476 } 477 478 static void 479 axe_setiff(struct usbnet *un) 480 { 481 usbnet_lock_mii(un); 482 axe_setiff_locked(un); 483 usbnet_unlock_mii(un); 484 } 485 486 static void 487 axe_ax_init(struct usbnet *un) 488 { 489 struct axe_softc * const sc = usbnet_softc(un); 490 491 int cmd = AXE_178_CMD_READ_NODEID; 492 493 if (sc->axe_flags & AX178) { 494 axe_ax88178_init(sc); 495 } else if (sc->axe_flags & AX772) { 496 axe_ax88772_init(sc); 497 } else if (sc->axe_flags & AX772A) { 498 axe_ax88772a_init(sc); 499 } else if (sc->axe_flags & AX772B) { 500 axe_ax88772b_init(sc); 501 return; 502 } else { 503 cmd = AXE_172_CMD_READ_NODEID; 504 } 505 506 if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) { 507 aprint_error_dev(un->un_dev, 508 "failed to read ethernet address\n"); 509 } 510 } 511 512 513 static void 514 axe_reset(struct usbnet *un) 515 { 516 517 usbnet_isowned_mii(un); 518 519 if (un->un_dying) 520 return; 521 522 /* 523 * softnet_lock can be taken when NET_MPAFE is not defined when calling 524 * if_addr_init -> if_init. This doesn't mix well with the 525 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 526 * can fire during the wait and attempt to take softnet_lock and then 527 * block the softclk thread meaning the wait never ends. 528 */ 529 #ifndef NET_MPSAFE 530 /* XXX What to reset? */ 531 532 /* Wait a little while for the chip to get its brains in order. */ 533 DELAY(1000); 534 #else 535 axe_ax_init(un); 536 #endif 537 } 538 539 static int 540 axe_get_phyno(struct axe_softc *sc, int sel) 541 { 542 int phyno; 543 544 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 545 case PHY_TYPE_100_HOME: 546 /* FALLTHROUGH */ 547 case PHY_TYPE_GIG: 548 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 549 break; 550 case PHY_TYPE_SPECIAL: 551 /* FALLTHROUGH */ 552 case PHY_TYPE_RSVD: 553 /* FALLTHROUGH */ 554 case PHY_TYPE_NON_SUP: 555 /* FALLTHROUGH */ 556 default: 557 phyno = -1; 558 break; 559 } 560 561 return phyno; 562 } 563 564 #define AXE_GPIO_WRITE(x, y) do { \ 565 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 566 usbd_delay_ms(sc->axe_un.un_udev, hztoms(y)); \ 567 } while (0) 568 569 static void 570 axe_ax88178_init(struct axe_softc *sc) 571 { 572 AXEHIST_FUNC(); AXEHIST_CALLED(); 573 struct usbnet * const un = &sc->axe_un; 574 int gpio0, ledmode, phymode; 575 uint16_t eeprom, val; 576 577 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 578 /* XXX magic */ 579 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 580 eeprom = 0xffff; 581 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 582 583 eeprom = le16toh(eeprom); 584 585 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 586 587 /* if EEPROM is invalid we have to use to GPIO0 */ 588 if (eeprom == 0xffff) { 589 phymode = AXE_PHY_MODE_MARVELL; 590 gpio0 = 1; 591 ledmode = 0; 592 } else { 593 phymode = eeprom & 0x7f; 594 gpio0 = (eeprom & 0x80) ? 0 : 1; 595 ledmode = eeprom >> 8; 596 } 597 598 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 599 600 /* Program GPIOs depending on PHY hardware. */ 601 switch (phymode) { 602 case AXE_PHY_MODE_MARVELL: 603 if (gpio0 == 1) { 604 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 605 hz / 32); 606 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 607 hz / 32); 608 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 609 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 610 hz / 32); 611 } else { 612 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 613 AXE_GPIO1_EN, hz / 3); 614 if (ledmode == 1) { 615 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 616 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 617 hz / 3); 618 } else { 619 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 620 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 621 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 622 AXE_GPIO2_EN, hz / 4); 623 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 624 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 625 } 626 } 627 break; 628 case AXE_PHY_MODE_CICADA: 629 case AXE_PHY_MODE_CICADA_V2: 630 case AXE_PHY_MODE_CICADA_V2_ASIX: 631 if (gpio0 == 1) 632 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 633 AXE_GPIO0_EN, hz / 32); 634 else 635 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 636 AXE_GPIO1_EN, hz / 32); 637 break; 638 case AXE_PHY_MODE_AGERE: 639 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 640 AXE_GPIO1_EN, hz / 32); 641 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 642 AXE_GPIO2_EN, hz / 32); 643 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 644 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 645 AXE_GPIO2_EN, hz / 32); 646 break; 647 case AXE_PHY_MODE_REALTEK_8211CL: 648 case AXE_PHY_MODE_REALTEK_8211BN: 649 case AXE_PHY_MODE_REALTEK_8251CL: 650 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 651 AXE_GPIO1 | AXE_GPIO1_EN; 652 AXE_GPIO_WRITE(val, hz / 32); 653 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 654 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 655 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 656 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 657 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0005); 658 axe_mii_write_reg(un, un->un_phyno, 0x0C, 0x0000); 659 axe_mii_read_reg(un, un->un_phyno, 0x0001, &val); 660 axe_mii_write_reg(un, un->un_phyno, 0x01, val | 0x0080); 661 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0000); 662 } 663 break; 664 default: 665 /* Unknown PHY model or no need to program GPIOs. */ 666 break; 667 } 668 669 /* soft reset */ 670 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 671 usbd_delay_ms(un->un_udev, 150); 672 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 673 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 674 usbd_delay_ms(un->un_udev, 150); 675 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 676 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 677 usbd_delay_ms(un->un_udev, 10); 678 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 679 } 680 681 static void 682 axe_ax88772_init(struct axe_softc *sc) 683 { 684 AXEHIST_FUNC(); AXEHIST_CALLED(); 685 struct usbnet * const un = &sc->axe_un; 686 687 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 688 usbd_delay_ms(un->un_udev, 40); 689 690 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 691 /* ask for the embedded PHY */ 692 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 693 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 694 usbd_delay_ms(un->un_udev, 10); 695 696 /* power down and reset state, pin reset state */ 697 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 698 usbd_delay_ms(un->un_udev, 60); 699 700 /* power down/reset state, pin operating state */ 701 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 702 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 703 usbd_delay_ms(un->un_udev, 150); 704 705 /* power up, reset */ 706 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 707 708 /* power up, operating */ 709 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 710 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 711 } else { 712 /* ask for external PHY */ 713 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 714 NULL); 715 usbd_delay_ms(un->un_udev, 10); 716 717 /* power down internal PHY */ 718 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 719 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 720 } 721 722 usbd_delay_ms(un->un_udev, 150); 723 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 724 } 725 726 static void 727 axe_ax88772_phywake(struct axe_softc *sc) 728 { 729 AXEHIST_FUNC(); AXEHIST_CALLED(); 730 struct usbnet * const un = &sc->axe_un; 731 732 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 733 /* Manually select internal(embedded) PHY - MAC mode. */ 734 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 735 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 736 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 737 } else { 738 /* 739 * Manually select external PHY - MAC mode. 740 * Reverse MII/RMII is for AX88772A PHY mode. 741 */ 742 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 743 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 744 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 745 } 746 747 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 748 AXE_SW_RESET_IPRL, NULL); 749 750 /* T1 = min 500ns everywhere */ 751 usbd_delay_ms(un->un_udev, 150); 752 753 /* Take PHY out of power down. */ 754 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 755 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 756 } else { 757 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 758 } 759 760 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 761 usbd_delay_ms(un->un_udev, 600); 762 763 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 764 765 /* T3 = 500ns everywhere */ 766 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 767 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 768 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 769 } 770 771 static void 772 axe_ax88772a_init(struct axe_softc *sc) 773 { 774 AXEHIST_FUNC(); AXEHIST_CALLED(); 775 776 /* Reload EEPROM. */ 777 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 778 axe_ax88772_phywake(sc); 779 /* Stop MAC. */ 780 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 781 } 782 783 static void 784 axe_ax88772b_init(struct axe_softc *sc) 785 { 786 AXEHIST_FUNC(); AXEHIST_CALLED(); 787 struct usbnet * const un = &sc->axe_un; 788 uint16_t eeprom; 789 int i; 790 791 /* Reload EEPROM. */ 792 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 793 794 /* 795 * Save PHY power saving configuration(high byte) and 796 * clear EEPROM checksum value(low byte). 797 */ 798 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 799 &eeprom)) { 800 aprint_error_dev(un->un_dev, "failed to read eeprom\n"); 801 return; 802 } 803 804 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 805 806 /* 807 * Auto-loaded default station address from internal ROM is 808 * 00:00:00:00:00:00 such that an explicit access to EEPROM 809 * is required to get real station address. 810 */ 811 uint8_t *eaddr = un->un_eaddr; 812 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 813 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 814 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 815 aprint_error_dev(un->un_dev, 816 "failed to read eeprom\n"); 817 eeprom = 0; 818 } 819 eeprom = le16toh(eeprom); 820 *eaddr++ = (uint8_t)(eeprom & 0xFF); 821 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 822 } 823 /* Wakeup PHY. */ 824 axe_ax88772_phywake(sc); 825 /* Stop MAC. */ 826 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 827 } 828 829 #undef AXE_GPIO_WRITE 830 831 /* 832 * Probe for a AX88172 chip. 833 */ 834 int 835 axe_match(device_t parent, cfdata_t match, void *aux) 836 { 837 struct usb_attach_arg *uaa = aux; 838 839 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 840 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 841 } 842 843 /* 844 * Attach the interface. Allocate softc structures, do ifmedia 845 * setup and ethernet/BPF attach. 846 */ 847 void 848 axe_attach(device_t parent, device_t self, void *aux) 849 { 850 AXEHIST_FUNC(); AXEHIST_CALLED(); 851 struct axe_softc *sc = device_private(self); 852 struct usbnet * const un = &sc->axe_un; 853 struct usb_attach_arg *uaa = aux; 854 struct usbd_device *dev = uaa->uaa_device; 855 usbd_status err; 856 usb_interface_descriptor_t *id; 857 usb_endpoint_descriptor_t *ed; 858 char *devinfop; 859 unsigned bufsz; 860 int i; 861 862 /* Switch to usbnet for device_private() */ 863 self->dv_private = un; 864 865 aprint_naive("\n"); 866 aprint_normal("\n"); 867 devinfop = usbd_devinfo_alloc(dev, 0); 868 aprint_normal_dev(self, "%s\n", devinfop); 869 usbd_devinfo_free(devinfop); 870 871 un->un_dev = self; 872 un->un_udev = dev; 873 un->un_sc = sc; 874 un->un_stop_cb = axe_stop_cb; 875 un->un_ioctl_cb = axe_ioctl_cb; 876 un->un_read_reg_cb = axe_mii_read_reg; 877 un->un_write_reg_cb = axe_mii_write_reg; 878 un->un_statchg_cb = axe_mii_statchg_cb; 879 un->un_tx_prepare_cb = axe_tx_prepare_cb; 880 un->un_rx_loop_cb = axe_rx_loop_cb; 881 un->un_init_cb = axe_init; 882 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 883 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 884 885 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 886 if (err) { 887 aprint_error_dev(self, "failed to set configuration" 888 ", err=%s\n", usbd_errstr(err)); 889 return; 890 } 891 892 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 893 894 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &un->un_iface); 895 if (err) { 896 aprint_error_dev(self, "getting interface handle failed\n"); 897 return; 898 } 899 900 id = usbd_get_interface_descriptor(un->un_iface); 901 902 /* decide on what our bufsize will be */ 903 if (AXE_IS_178_FAMILY(sc)) 904 bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 905 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 906 else 907 bufsz = AXE_172_BUFSZ; 908 un->un_cdata.uncd_rx_bufsz = bufsz; 909 un->un_cdata.uncd_tx_bufsz = bufsz; 910 911 un->un_ed[USBNET_ENDPT_RX] = 0; 912 un->un_ed[USBNET_ENDPT_TX] = 0; 913 un->un_ed[USBNET_ENDPT_INTR] = 0; 914 915 /* Find endpoints. */ 916 for (i = 0; i < id->bNumEndpoints; i++) { 917 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 918 if (ed == NULL) { 919 aprint_error_dev(self, "couldn't get ep %d\n", i); 920 return; 921 } 922 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 923 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 924 925 if (dir == UE_DIR_IN && xt == UE_BULK && 926 un->un_ed[USBNET_ENDPT_RX] == 0) { 927 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 928 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 929 un->un_ed[USBNET_ENDPT_TX] == 0) { 930 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 931 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 932 un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress; 933 } 934 } 935 936 /* Set these up now for axe_cmd(). */ 937 usbnet_attach(un, "axedet", AXE_RX_LIST_CNT, AXE_TX_LIST_CNT); 938 939 /* We need the PHYID for init dance in some cases */ 940 usbnet_lock_mii(un); 941 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 942 aprint_error_dev(self, "failed to read phyaddrs\n"); 943 944 return; 945 } 946 947 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 948 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 949 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 950 if (un->un_phyno == -1) 951 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 952 if (un->un_phyno == -1) { 953 DPRINTF(" no valid PHY address found, assuming PHY address 0", 954 0, 0, 0, 0); 955 un->un_phyno = 0; 956 } 957 958 /* Initialize controller and get station address. */ 959 960 axe_ax_init(un); 961 962 /* 963 * Fetch IPG values. 964 */ 965 if (sc->axe_flags & (AX772A | AX772B)) { 966 /* Set IPG values. */ 967 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 968 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 969 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 970 } else { 971 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 972 aprint_error_dev(self, "failed to read ipg\n"); 973 usbnet_unlock_mii(un); 974 return; 975 } 976 } 977 978 usbnet_unlock_mii(un); 979 980 if (AXE_IS_178_FAMILY(sc)) 981 usbnet_ec(un)->ec_capabilities = ETHERCAP_VLAN_MTU; 982 if (sc->axe_flags & AX772B) { 983 struct ifnet *ifp = usbnet_ifp(un); 984 985 ifp->if_capabilities = 986 IFCAP_CSUM_IPv4_Rx | 987 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 988 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 989 /* 990 * Checksum offloading of AX88772B also works with VLAN 991 * tagged frames but there is no way to take advantage 992 * of the feature because vlan(4) assumes 993 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 994 * support checksum offloading with VLAN. VLAN hardware 995 * tagging support of AX88772B is very limited so it's 996 * not possible to announce IFCAP_VLAN_HWTAGGING. 997 */ 998 } 999 u_int adv_pause; 1000 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1001 adv_pause = MIIF_DOPAUSE; 1002 else 1003 adv_pause = 0; 1004 adv_pause = 0; 1005 1006 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 1007 0, adv_pause); 1008 } 1009 1010 static void 1011 axe_rx_loop_cb(struct usbnet * un, struct usbd_xfer *xfer, 1012 struct usbnet_chain *c, uint32_t total_len) 1013 { 1014 AXEHIST_FUNC(); AXEHIST_CALLED(); 1015 struct axe_softc * const sc = usbnet_softc(un); 1016 struct ifnet *ifp = usbnet_ifp(un); 1017 uint8_t *buf = c->unc_buf; 1018 1019 do { 1020 u_int pktlen = 0; 1021 u_int rxlen = 0; 1022 int flags = 0; 1023 1024 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1025 struct axe_sframe_hdr hdr; 1026 1027 if (total_len < sizeof(hdr)) { 1028 ifp->if_ierrors++; 1029 break; 1030 } 1031 1032 #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1) 1033 /* 1034 * XXX hdr is 2-byte aligned in buf, not 4-byte. 1035 * For some architectures, __builtin_memcpy() of 1036 * GCC 6 attempts to copy sizeof(hdr) = 4 bytes 1037 * at onece, which results in alignment error. 1038 */ 1039 hdr.len = *(uint16_t *)buf; 1040 hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t)); 1041 #else 1042 memcpy(&hdr, buf, sizeof(hdr)); 1043 #endif 1044 1045 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1046 total_len, 1047 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1048 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1049 1050 total_len -= sizeof(hdr); 1051 buf += sizeof(hdr); 1052 1053 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1054 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1055 AXE_RH1M_RXLEN_MASK) { 1056 ifp->if_ierrors++; 1057 break; 1058 } 1059 1060 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1061 if (total_len < rxlen) { 1062 pktlen = total_len; 1063 total_len = 0; 1064 } else { 1065 pktlen = rxlen; 1066 rxlen = roundup2(rxlen, 2); 1067 total_len -= rxlen; 1068 } 1069 1070 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1071 struct axe_csum_hdr csum_hdr; 1072 1073 if (total_len < sizeof(csum_hdr)) { 1074 ifp->if_ierrors++; 1075 break; 1076 } 1077 1078 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1079 1080 csum_hdr.len = le16toh(csum_hdr.len); 1081 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1082 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1083 1084 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1085 " cstatus %#jx", total_len, 1086 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1087 1088 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1089 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1090 sc->sc_lenmask) { 1091 /* we lost sync */ 1092 ifp->if_ierrors++; 1093 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1094 "err", 1095 AXE_CSUM_RXBYTES(csum_hdr.len), 1096 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1097 sc->sc_lenmask, 0); 1098 break; 1099 } 1100 /* 1101 * Get total transferred frame length including 1102 * checksum header. The length should be multiple 1103 * of 4. 1104 */ 1105 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1106 u_int len = sizeof(csum_hdr) + pktlen; 1107 len = (len + 3) & ~3; 1108 if (total_len < len) { 1109 DPRINTFN(20, "total_len %#jx < len %#jx", 1110 total_len, len, 0, 0); 1111 /* invalid length */ 1112 ifp->if_ierrors++; 1113 break; 1114 } 1115 buf += sizeof(csum_hdr); 1116 1117 const uint16_t cstatus = csum_hdr.cstatus; 1118 1119 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1120 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1121 flags |= M_CSUM_TCP_UDP_BAD; 1122 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1123 flags |= M_CSUM_IPv4_BAD; 1124 1125 const uint16_t l4type = 1126 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1127 1128 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1129 flags |= M_CSUM_TCPv4; 1130 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1131 flags |= M_CSUM_UDPv4; 1132 } 1133 if (total_len < len) { 1134 pktlen = total_len; 1135 total_len = 0; 1136 } else { 1137 total_len -= len; 1138 rxlen = len - sizeof(csum_hdr); 1139 } 1140 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1141 " rxlen %#jx", total_len, len, pktlen, rxlen); 1142 } else { /* AX172 */ 1143 pktlen = rxlen = total_len; 1144 total_len = 0; 1145 } 1146 1147 usbnet_enqueue(un, buf, pktlen, flags, 0, 0); 1148 buf += rxlen; 1149 1150 } while (total_len > 0); 1151 1152 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1153 } 1154 1155 static unsigned 1156 axe_tx_prepare_cb(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1157 { 1158 AXEHIST_FUNC(); AXEHIST_CALLED(); 1159 struct axe_softc * const sc = usbnet_softc(un); 1160 int length, boundary; 1161 1162 usbnet_isowned_tx(un); 1163 1164 /* 1165 * Copy the mbuf data into a contiguous buffer, leaving two 1166 * bytes at the beginning to hold the frame length. 1167 */ 1168 if (AXE_IS_178_FAMILY(sc)) { 1169 struct axe_sframe_hdr hdr; 1170 1171 boundary = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1172 1173 hdr.len = htole16(m->m_pkthdr.len); 1174 hdr.ilen = ~hdr.len; 1175 1176 memcpy(c->unc_buf, &hdr, sizeof(hdr)); 1177 length = sizeof(hdr); 1178 1179 m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf + length); 1180 length += m->m_pkthdr.len; 1181 1182 if ((length % boundary) == 0) { 1183 hdr.len = 0x0000; 1184 hdr.ilen = 0xffff; 1185 memcpy(c->unc_buf + length, &hdr, sizeof(hdr)); 1186 length += sizeof(hdr); 1187 } 1188 DPRINTFN(20, "length %jx m_pkthdr.len %jx hdrsize %#jx", 1189 length, m->m_pkthdr.len, sizeof(hdr), 0); 1190 } else { 1191 m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf); 1192 length = m->m_pkthdr.len; 1193 DPRINTFN(20, "length %jx", length, 0, 0, 0); 1194 } 1195 1196 1197 return length; 1198 } 1199 1200 static void 1201 axe_csum_cfg(struct axe_softc *sc) 1202 { 1203 struct usbnet * const un = &sc->axe_un; 1204 struct ifnet * const ifp = usbnet_ifp(un); 1205 uint16_t csum1, csum2; 1206 1207 if ((sc->axe_flags & AX772B) != 0) { 1208 csum1 = 0; 1209 csum2 = 0; 1210 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1211 csum1 |= AXE_TXCSUM_IP; 1212 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1213 csum1 |= AXE_TXCSUM_TCP; 1214 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1215 csum1 |= AXE_TXCSUM_UDP; 1216 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1217 csum1 |= AXE_TXCSUM_TCPV6; 1218 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1219 csum1 |= AXE_TXCSUM_UDPV6; 1220 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1221 csum1 = 0; 1222 csum2 = 0; 1223 1224 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1225 csum1 |= AXE_RXCSUM_IP; 1226 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1227 csum1 |= AXE_RXCSUM_TCP; 1228 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1229 csum1 |= AXE_RXCSUM_UDP; 1230 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1231 csum1 |= AXE_RXCSUM_TCPV6; 1232 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1233 csum1 |= AXE_RXCSUM_UDPV6; 1234 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1235 } 1236 } 1237 1238 static int 1239 axe_init_locked(struct ifnet *ifp) 1240 { 1241 AXEHIST_FUNC(); AXEHIST_CALLED(); 1242 struct usbnet * const un = ifp->if_softc; 1243 struct axe_softc * const sc = usbnet_softc(un); 1244 int rxmode; 1245 1246 usbnet_isowned(un); 1247 1248 if (un->un_dying) 1249 return EIO; 1250 1251 /* Cancel pending I/O */ 1252 usbnet_stop(un, ifp, 1); 1253 1254 usbnet_lock_mii_un_locked(un); 1255 1256 /* Reset the ethernet interface. */ 1257 axe_reset(un); 1258 1259 #if 0 1260 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1261 AX_GPIO_GPO2EN, 5, in_pm); 1262 #endif 1263 /* Set MAC address and transmitter IPG values. */ 1264 if (AXE_IS_178_FAMILY(sc)) { 1265 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1266 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1267 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1268 } else { 1269 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1270 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1271 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1272 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1273 } 1274 if (AXE_IS_178_FAMILY(sc)) { 1275 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1276 if ((sc->axe_flags & AX772B) != 0 && 1277 (ifp->if_capenable & AX_RXCSUM) != 0) { 1278 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1279 sc->axe_flags |= AXCSUM_FRAME; 1280 } else { 1281 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1282 sc->axe_flags |= AXSTD_FRAME; 1283 } 1284 } 1285 1286 /* Configure TX/RX checksum offloading. */ 1287 axe_csum_cfg(sc); 1288 1289 if (sc->axe_flags & AX772B) { 1290 /* AX88772B uses different maximum frame burst configuration. */ 1291 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1292 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1293 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1294 } 1295 /* Enable receiver, set RX mode */ 1296 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1297 if (AXE_IS_178_FAMILY(sc)) { 1298 if (sc->axe_flags & AX772B) { 1299 /* 1300 * Select RX header format type 1. Aligning IP 1301 * header on 4 byte boundary is not needed when 1302 * checksum offloading feature is not used 1303 * because we always copy the received frame in 1304 * RX handler. When RX checksum offloading is 1305 * active, aligning IP header is required to 1306 * reflect actual frame length including RX 1307 * header size. 1308 */ 1309 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1310 if (sc->axe_flags & AXCSUM_FRAME) 1311 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1312 } else { 1313 /* 1314 * Default Rx buffer size is too small to get 1315 * maximum performance. 1316 */ 1317 #if 0 1318 if (un->un_udev->ud_speed == USB_SPEED_HIGH) { 1319 /* Largest possible USB buffer size for AX88178 */ 1320 } 1321 #endif 1322 rxmode |= AXE_178_RXCMD_MFB_16384; 1323 } 1324 } else { 1325 rxmode |= AXE_172_RXCMD_UNICAST; 1326 } 1327 1328 1329 /* If we want promiscuous mode, set the allframes bit. */ 1330 if (ifp->if_flags & IFF_PROMISC) 1331 rxmode |= AXE_RXCMD_PROMISC; 1332 1333 if (ifp->if_flags & IFF_BROADCAST) 1334 rxmode |= AXE_RXCMD_BROADCAST; 1335 1336 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1337 1338 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1339 1340 /* Load the multicast filter. */ 1341 axe_setiff_locked(un); 1342 1343 usbnet_unlock_mii_un_locked(un); 1344 1345 return usbnet_init_rx_tx(un, 0, USBD_FORCE_SHORT_XFER); 1346 } 1347 1348 static int 1349 axe_init(struct ifnet *ifp) 1350 { 1351 struct usbnet * const un = ifp->if_softc; 1352 1353 usbnet_lock(un); 1354 int ret = axe_init_locked(ifp); 1355 usbnet_unlock(un); 1356 1357 return ret; 1358 } 1359 1360 static int 1361 axe_ioctl_cb(struct ifnet *ifp, u_long cmd, void *data) 1362 { 1363 struct usbnet * const un = ifp->if_softc; 1364 1365 switch (cmd) { 1366 case SIOCADDMULTI: 1367 case SIOCDELMULTI: 1368 axe_setiff(un); 1369 break; 1370 default: 1371 break; 1372 } 1373 1374 return 0; 1375 } 1376 1377 static void 1378 axe_stop_cb(struct ifnet *ifp, int disable) 1379 { 1380 struct usbnet * const un = ifp->if_softc; 1381 1382 usbnet_lock_mii_un_locked(un); 1383 axe_reset(un); 1384 usbnet_unlock_mii_un_locked(un); 1385 } 1386 1387 MODULE(MODULE_CLASS_DRIVER, if_axe, "usbnet"); 1388 1389 #ifdef _MODULE 1390 #include "ioconf.c" 1391 #endif 1392 1393 static int 1394 if_axe_modcmd(modcmd_t cmd, void *aux) 1395 { 1396 int error = 0; 1397 1398 switch (cmd) { 1399 case MODULE_CMD_INIT: 1400 #ifdef _MODULE 1401 error = config_init_component(cfdriver_ioconf_axe, 1402 cfattach_ioconf_axe, cfdata_ioconf_axe); 1403 #endif 1404 return error; 1405 case MODULE_CMD_FINI: 1406 #ifdef _MODULE 1407 error = config_fini_component(cfdriver_ioconf_axe, 1408 cfattach_ioconf_axe, cfdata_ioconf_axe); 1409 #endif 1410 return error; 1411 default: 1412 return ENOTTY; 1413 } 1414 } 1415
Indexes created Wed Oct 01 18:09:54 GMT 2025